1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP 26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP 27 28 #include "asm/assembler.hpp" 29 #include "utilities/macros.hpp" 30 #include "runtime/rtmLocking.hpp" 31 32 33 // MacroAssembler extends Assembler by frequently used macros. 34 // 35 // Instructions for which a 'better' code sequence exists depending 36 // on arguments should also go in here. 37 38 class MacroAssembler: public Assembler { 39 friend class LIR_Assembler; 40 friend class Runtime1; // as_Address() 41 42 protected: 43 44 Address as_Address(AddressLiteral adr); 45 Address as_Address(ArrayAddress adr); 46 47 // Support for VM calls 48 // 49 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 50 // may customize this version by overriding it for its purposes (e.g., to save/restore 51 // additional registers when doing a VM call). 52 #ifdef CC_INTERP 53 // c++ interpreter never wants to use interp_masm version of call_VM 54 #define VIRTUAL 55 #else 56 #define VIRTUAL virtual 57 #endif 58 59 VIRTUAL void call_VM_leaf_base( 60 address entry_point, // the entry point 61 int number_of_arguments // the number of arguments to pop after the call 62 ); 63 64 // This is the base routine called by the different versions of call_VM. The interpreter 65 // may customize this version by overriding it for its purposes (e.g., to save/restore 66 // additional registers when doing a VM call). 67 // 68 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base 69 // returns the register which contains the thread upon return. If a thread register has been 70 // specified, the return value will correspond to that register. If no last_java_sp is specified 71 // (noreg) than rsp will be used instead. 72 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 73 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 74 Register java_thread, // the thread if computed before ; use noreg otherwise 75 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 76 address entry_point, // the entry point 77 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 78 bool check_exceptions // whether to check for pending exceptions after return 79 ); 80 81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 82 // The implementation is only non-empty for the InterpreterMacroAssembler, 83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 84 virtual void check_and_handle_popframe(Register java_thread); 85 virtual void check_and_handle_earlyret(Register java_thread); 86 87 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 88 89 // helpers for FPU flag access 90 // tmp is a temporary register, if none is available use noreg 91 void save_rax (Register tmp); 92 void restore_rax(Register tmp); 93 94 public: MacroAssembler(CodeBuffer * code)95 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 96 97 // Support for NULL-checks 98 // 99 // Generates code that causes a NULL OS exception if the content of reg is NULL. 100 // If the accessed location is M[reg + offset] and the offset is known, provide the 101 // offset. No explicit code generation is needed if the offset is within a certain 102 // range (0 <= offset <= page_size). 103 104 void null_check(Register reg, int offset = -1); 105 static bool needs_explicit_null_check(intptr_t offset); 106 107 // Required platform-specific helpers for Label::patch_instructions. 108 // They _shadow_ the declarations in AbstractAssembler, which are undefined. pd_patch_instruction(address branch,address target)109 void pd_patch_instruction(address branch, address target) { 110 unsigned char op = branch[0]; 111 assert(op == 0xE8 /* call */ || 112 op == 0xE9 /* jmp */ || 113 op == 0xEB /* short jmp */ || 114 (op & 0xF0) == 0x70 /* short jcc */ || 115 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ || 116 op == 0xC7 && branch[1] == 0xF8 /* xbegin */, 117 "Invalid opcode at patch point"); 118 119 if (op == 0xEB || (op & 0xF0) == 0x70) { 120 // short offset operators (jmp and jcc) 121 char* disp = (char*) &branch[1]; 122 int imm8 = target - (address) &disp[1]; 123 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset"); 124 *disp = imm8; 125 } else { 126 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1]; 127 int imm32 = target - (address) &disp[1]; 128 *disp = imm32; 129 } 130 } 131 132 // The following 4 methods return the offset of the appropriate move instruction 133 134 // Support for fast byte/short loading with zero extension (depending on particular CPU) 135 int load_unsigned_byte(Register dst, Address src); 136 int load_unsigned_short(Register dst, Address src); 137 138 // Support for fast byte/short loading with sign extension (depending on particular CPU) 139 int load_signed_byte(Register dst, Address src); 140 int load_signed_short(Register dst, Address src); 141 142 // Support for sign-extension (hi:lo = extend_sign(lo)) 143 void extend_sign(Register hi, Register lo); 144 145 // Load and store values by size and signed-ness 146 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 147 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 148 149 // Support for inc/dec with optimal instruction selection depending on value 150 increment(Register reg,int value=1)151 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } decrement(Register reg,int value=1)152 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } 153 154 void decrementl(Address dst, int value = 1); 155 void decrementl(Register reg, int value = 1); 156 157 void decrementq(Register reg, int value = 1); 158 void decrementq(Address dst, int value = 1); 159 160 void incrementl(Address dst, int value = 1); 161 void incrementl(Register reg, int value = 1); 162 163 void incrementq(Register reg, int value = 1); 164 void incrementq(Address dst, int value = 1); 165 166 // Support optimal SSE move instructions. movflt(XMMRegister dst,XMMRegister src)167 void movflt(XMMRegister dst, XMMRegister src) { 168 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } 169 else { movss (dst, src); return; } 170 } movflt(XMMRegister dst,Address src)171 void movflt(XMMRegister dst, Address src) { movss(dst, src); } 172 void movflt(XMMRegister dst, AddressLiteral src); movflt(Address dst,XMMRegister src)173 void movflt(Address dst, XMMRegister src) { movss(dst, src); } 174 movdbl(XMMRegister dst,XMMRegister src)175 void movdbl(XMMRegister dst, XMMRegister src) { 176 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } 177 else { movsd (dst, src); return; } 178 } 179 180 void movdbl(XMMRegister dst, AddressLiteral src); 181 movdbl(XMMRegister dst,Address src)182 void movdbl(XMMRegister dst, Address src) { 183 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } 184 else { movlpd(dst, src); return; } 185 } movdbl(Address dst,XMMRegister src)186 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } 187 188 void incrementl(AddressLiteral dst); 189 void incrementl(ArrayAddress dst); 190 191 void incrementq(AddressLiteral dst); 192 193 // Alignment 194 void align(int modulus); 195 196 // A 5 byte nop that is safe for patching (see patch_verified_entry) 197 void fat_nop(); 198 199 // Stack frame creation/removal 200 void enter(); 201 void leave(); 202 203 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 204 // The pointer will be loaded into the thread register. 205 void get_thread(Register thread); 206 207 208 // Support for VM calls 209 // 210 // It is imperative that all calls into the VM are handled via the call_VM macros. 211 // They make sure that the stack linkage is setup correctly. call_VM's correspond 212 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 213 214 215 void call_VM(Register oop_result, 216 address entry_point, 217 bool check_exceptions = true); 218 void call_VM(Register oop_result, 219 address entry_point, 220 Register arg_1, 221 bool check_exceptions = true); 222 void call_VM(Register oop_result, 223 address entry_point, 224 Register arg_1, Register arg_2, 225 bool check_exceptions = true); 226 void call_VM(Register oop_result, 227 address entry_point, 228 Register arg_1, Register arg_2, Register arg_3, 229 bool check_exceptions = true); 230 231 // Overloadings with last_Java_sp 232 void call_VM(Register oop_result, 233 Register last_java_sp, 234 address entry_point, 235 int number_of_arguments = 0, 236 bool check_exceptions = true); 237 void call_VM(Register oop_result, 238 Register last_java_sp, 239 address entry_point, 240 Register arg_1, bool 241 check_exceptions = true); 242 void call_VM(Register oop_result, 243 Register last_java_sp, 244 address entry_point, 245 Register arg_1, Register arg_2, 246 bool check_exceptions = true); 247 void call_VM(Register oop_result, 248 Register last_java_sp, 249 address entry_point, 250 Register arg_1, Register arg_2, Register arg_3, 251 bool check_exceptions = true); 252 253 void get_vm_result (Register oop_result, Register thread); 254 void get_vm_result_2(Register metadata_result, Register thread); 255 256 // These always tightly bind to MacroAssembler::call_VM_base 257 // bypassing the virtual implementation 258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 261 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 262 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 263 264 void call_VM_leaf(address entry_point, 265 int number_of_arguments = 0); 266 void call_VM_leaf(address entry_point, 267 Register arg_1); 268 void call_VM_leaf(address entry_point, 269 Register arg_1, Register arg_2); 270 void call_VM_leaf(address entry_point, 271 Register arg_1, Register arg_2, Register arg_3); 272 273 // These always tightly bind to MacroAssembler::call_VM_leaf_base 274 // bypassing the virtual implementation 275 void super_call_VM_leaf(address entry_point); 276 void super_call_VM_leaf(address entry_point, Register arg_1); 277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 279 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 280 281 // last Java Frame (fills frame anchor) 282 void set_last_Java_frame(Register thread, 283 Register last_java_sp, 284 Register last_java_fp, 285 address last_java_pc); 286 287 // thread in the default location (r15_thread on 64bit) 288 void set_last_Java_frame(Register last_java_sp, 289 Register last_java_fp, 290 address last_java_pc); 291 292 void reset_last_Java_frame(Register thread, bool clear_fp); 293 294 // thread in the default location (r15_thread on 64bit) 295 void reset_last_Java_frame(bool clear_fp); 296 297 // Stores 298 void store_check(Register obj); // store check for obj - register is destroyed afterwards 299 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 300 301 void resolve_jobject(Register value, Register thread, Register tmp); 302 void clear_jweak_tag(Register possibly_jweak); 303 304 #if INCLUDE_ALL_GCS 305 306 void g1_write_barrier_pre(Register obj, 307 Register pre_val, 308 Register thread, 309 Register tmp, 310 bool tosca_live, 311 bool expand_call); 312 313 void g1_write_barrier_post(Register store_addr, 314 Register new_val, 315 Register thread, 316 Register tmp, 317 Register tmp2); 318 319 #endif // INCLUDE_ALL_GCS 320 321 // split store_check(Register obj) to enhance instruction interleaving 322 void store_check_part_1(Register obj); 323 void store_check_part_2(Register obj); 324 325 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 326 void c2bool(Register x); 327 328 // C++ bool manipulation 329 330 void movbool(Register dst, Address src); 331 void movbool(Address dst, bool boolconst); 332 void movbool(Address dst, Register src); 333 void testbool(Register dst); 334 335 // oop manipulations 336 void load_klass(Register dst, Register src); 337 void store_klass(Register dst, Register src); 338 339 void load_heap_oop(Register dst, Address src); 340 void load_heap_oop_not_null(Register dst, Address src); 341 void store_heap_oop(Address dst, Register src); 342 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg); 343 344 // Used for storing NULL. All other oop constants should be 345 // stored using routines that take a jobject. 346 void store_heap_oop_null(Address dst); 347 348 void load_prototype_header(Register dst, Register src); 349 350 #ifdef _LP64 351 void store_klass_gap(Register dst, Register src); 352 353 // This dummy is to prevent a call to store_heap_oop from 354 // converting a zero (like NULL) into a Register by giving 355 // the compiler two choices it can't resolve 356 357 void store_heap_oop(Address dst, void* dummy); 358 359 void encode_heap_oop(Register r); 360 void decode_heap_oop(Register r); 361 void encode_heap_oop_not_null(Register r); 362 void decode_heap_oop_not_null(Register r); 363 void encode_heap_oop_not_null(Register dst, Register src); 364 void decode_heap_oop_not_null(Register dst, Register src); 365 366 void set_narrow_oop(Register dst, jobject obj); 367 void set_narrow_oop(Address dst, jobject obj); 368 void cmp_narrow_oop(Register dst, jobject obj); 369 void cmp_narrow_oop(Address dst, jobject obj); 370 371 void encode_klass_not_null(Register r); 372 void decode_klass_not_null(Register r); 373 void encode_klass_not_null(Register dst, Register src); 374 void decode_klass_not_null(Register dst, Register src); 375 void set_narrow_klass(Register dst, Klass* k); 376 void set_narrow_klass(Address dst, Klass* k); 377 void cmp_narrow_klass(Register dst, Klass* k); 378 void cmp_narrow_klass(Address dst, Klass* k); 379 380 // Returns the byte size of the instructions generated by decode_klass_not_null() 381 // when compressed klass pointers are being used. 382 static int instr_size_for_decode_klass_not_null(); 383 384 // if heap base register is used - reinit it with the correct value 385 void reinit_heapbase(); 386 387 DEBUG_ONLY(void verify_heapbase(const char* msg);) 388 389 #endif // _LP64 390 391 // Int division/remainder for Java 392 // (as idivl, but checks for special case as described in JVM spec.) 393 // returns idivl instruction offset for implicit exception handling 394 int corrected_idivl(Register reg); 395 396 // Long division/remainder for Java 397 // (as idivq, but checks for special case as described in JVM spec.) 398 // returns idivq instruction offset for implicit exception handling 399 int corrected_idivq(Register reg); 400 401 void int3(); 402 403 // Long operation macros for a 32bit cpu 404 // Long negation for Java 405 void lneg(Register hi, Register lo); 406 407 // Long multiplication for Java 408 // (destroys contents of eax, ebx, ecx and edx) 409 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y 410 411 // Long shifts for Java 412 // (semantics as described in JVM spec.) 413 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) 414 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) 415 416 // Long compare for Java 417 // (semantics as described in JVM spec.) 418 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) 419 420 421 // misc 422 423 // Sign extension 424 void sign_extend_short(Register reg); 425 void sign_extend_byte(Register reg); 426 427 // Division by power of 2, rounding towards 0 428 void division_with_shift(Register reg, int shift_value); 429 430 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: 431 // 432 // CF (corresponds to C0) if x < y 433 // PF (corresponds to C2) if unordered 434 // ZF (corresponds to C3) if x = y 435 // 436 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 437 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) 438 void fcmp(Register tmp); 439 // Variant of the above which allows y to be further down the stack 440 // and which only pops x and y if specified. If pop_right is 441 // specified then pop_left must also be specified. 442 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); 443 444 // Floating-point comparison for Java 445 // Compares the top-most stack entries on the FPU stack and stores the result in dst. 446 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 447 // (semantics as described in JVM spec.) 448 void fcmp2int(Register dst, bool unordered_is_less); 449 // Variant of the above which allows y to be further down the stack 450 // and which only pops x and y if specified. If pop_right is 451 // specified then pop_left must also be specified. 452 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); 453 454 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) 455 // tmp is a temporary register, if none is available use noreg 456 void fremr(Register tmp); 457 458 459 // same as fcmp2int, but using SSE2 460 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 461 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 462 463 // Inlined sin/cos generator for Java; must not use CPU instruction 464 // directly on Intel as it does not have high enough precision 465 // outside of the range [-pi/4, pi/4]. Extra argument indicate the 466 // number of FPU stack slots in use; all but the topmost will 467 // require saving if a slow case is necessary. Assumes argument is 468 // on FP TOS; result is on FP TOS. No cpu registers are changed by 469 // this code. 470 void trigfunc(char trig, int num_fpu_regs_in_use = 1); 471 472 // branch to L if FPU flag C2 is set/not set 473 // tmp is a temporary register, if none is available use noreg 474 void jC2 (Register tmp, Label& L); 475 void jnC2(Register tmp, Label& L); 476 477 // Pop ST (ffree & fincstp combined) 478 void fpop(); 479 480 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 481 void push_fTOS(); 482 483 // pops double TOS element from CPU stack and pushes on FPU stack 484 void pop_fTOS(); 485 486 void empty_FPU_stack(); 487 488 void push_IU_state(); 489 void pop_IU_state(); 490 491 void push_FPU_state(); 492 void pop_FPU_state(); 493 494 void push_CPU_state(); 495 void pop_CPU_state(); 496 497 // Round up to a power of two 498 void round_to(Register reg, int modulus); 499 500 // Callee saved registers handling 501 void push_callee_saved_registers(); 502 void pop_callee_saved_registers(); 503 504 // allocation 505 void eden_allocate( 506 Register obj, // result: pointer to object after successful allocation 507 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 508 int con_size_in_bytes, // object size in bytes if known at compile time 509 Register t1, // temp register 510 Label& slow_case // continuation point if fast allocation fails 511 ); 512 void tlab_allocate( 513 Register obj, // result: pointer to object after successful allocation 514 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 515 int con_size_in_bytes, // object size in bytes if known at compile time 516 Register t1, // temp register 517 Register t2, // temp register 518 Label& slow_case // continuation point if fast allocation fails 519 ); 520 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 521 void incr_allocated_bytes(Register thread, 522 Register var_size_in_bytes, int con_size_in_bytes, 523 Register t1 = noreg); 524 525 // interface method calling 526 void lookup_interface_method(Register recv_klass, 527 Register intf_klass, 528 RegisterOrConstant itable_index, 529 Register method_result, 530 Register scan_temp, 531 Label& no_such_interface, 532 bool return_method = true); 533 534 // virtual method calling 535 void lookup_virtual_method(Register recv_klass, 536 RegisterOrConstant vtable_index, 537 Register method_result); 538 539 // Test sub_klass against super_klass, with fast and slow paths. 540 541 // The fast path produces a tri-state answer: yes / no / maybe-slow. 542 // One of the three labels can be NULL, meaning take the fall-through. 543 // If super_check_offset is -1, the value is loaded up from super_klass. 544 // No registers are killed, except temp_reg. 545 void check_klass_subtype_fast_path(Register sub_klass, 546 Register super_klass, 547 Register temp_reg, 548 Label* L_success, 549 Label* L_failure, 550 Label* L_slow_path, 551 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 552 553 // The rest of the type check; must be wired to a corresponding fast path. 554 // It does not repeat the fast path logic, so don't use it standalone. 555 // The temp_reg and temp2_reg can be noreg, if no temps are available. 556 // Updates the sub's secondary super cache as necessary. 557 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 558 void check_klass_subtype_slow_path(Register sub_klass, 559 Register super_klass, 560 Register temp_reg, 561 Register temp2_reg, 562 Label* L_success, 563 Label* L_failure, 564 bool set_cond_codes = false); 565 566 // Simplified, combined version, good for typical uses. 567 // Falls through on failure. 568 void check_klass_subtype(Register sub_klass, 569 Register super_klass, 570 Register temp_reg, 571 Label& L_success); 572 573 // method handles (JSR 292) 574 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 575 576 //---- 577 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 578 579 // Debugging 580 581 // only if +VerifyOops 582 // TODO: Make these macros with file and line like sparc version! 583 void verify_oop(Register reg, const char* s = "broken oop"); 584 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 585 586 // TODO: verify method and klass metadata (compare against vptr?) _verify_method_ptr(Register reg,const char * msg,const char * file,int line)587 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} _verify_klass_ptr(Register reg,const char * msg,const char * file,int line)588 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 589 590 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 591 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 592 593 // only if +VerifyFPU 594 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 595 596 // Verify or restore cpu control state after JNI call 597 void restore_cpu_control_state_after_jni(); 598 599 // prints msg, dumps registers and stops execution 600 void stop(const char* msg); 601 602 // prints msg and continues 603 void warn(const char* msg); 604 605 // dumps registers and other state 606 void print_state(); 607 608 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); 609 static void debug64(char* msg, int64_t pc, int64_t regs[]); 610 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip); 611 static void print_state64(int64_t pc, int64_t regs[]); 612 613 void os_breakpoint(); 614 untested()615 void untested() { stop("untested"); } 616 unimplemented(const char * what="")617 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 618 should_not_reach_here()619 void should_not_reach_here() { stop("should not reach here"); } 620 621 void print_CPU_state(); 622 623 // Stack overflow checking bang_stack_with_offset(int offset)624 void bang_stack_with_offset(int offset) { 625 // stack grows down, caller passes positive offset 626 assert(offset > 0, "must bang with negative offset"); 627 movl(Address(rsp, (-offset)), rax); 628 } 629 630 // Writes to stack successive pages until offset reached to check for 631 // stack overflow + shadow pages. Also, clobbers tmp 632 void bang_stack_size(Register size, Register tmp); 633 634 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 635 Register tmp, 636 int offset); 637 638 // Support for serializing memory accesses between threads 639 void serialize_memory(Register thread, Register tmp); 640 641 void verify_tlab(); 642 643 // Biased locking support 644 // lock_reg and obj_reg must be loaded up with the appropriate values. 645 // swap_reg must be rax, and is killed. 646 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 647 // be killed; if not supplied, push/pop will be used internally to 648 // allocate a temporary (inefficient, avoid if possible). 649 // Optional slow case is for implementations (interpreter and C1) which branch to 650 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 651 // Returns offset of first potentially-faulting instruction for null 652 // check info (currently consumed only by C1). If 653 // swap_reg_contains_mark is true then returns -1 as it is assumed 654 // the calling code has already passed any potential faults. 655 int biased_locking_enter(Register lock_reg, Register obj_reg, 656 Register swap_reg, Register tmp_reg, 657 bool swap_reg_contains_mark, 658 Label& done, Label* slow_case = NULL, 659 BiasedLockingCounters* counters = NULL); 660 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 661 #ifdef COMPILER2 662 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file. 663 // See full desription in macroAssembler_x86.cpp. 664 void fast_lock(Register obj, Register box, Register tmp, 665 Register scr, Register cx1, Register cx2, 666 BiasedLockingCounters* counters, 667 RTMLockingCounters* rtm_counters, 668 RTMLockingCounters* stack_rtm_counters, 669 Metadata* method_data, 670 bool use_rtm, bool profile_rtm); 671 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm); 672 #if INCLUDE_RTM_OPT 673 void rtm_counters_update(Register abort_status, Register rtm_counters); 674 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel); 675 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg, 676 RTMLockingCounters* rtm_counters, 677 Metadata* method_data); 678 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg, 679 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm); 680 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel); 681 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel); 682 void rtm_stack_locking(Register obj, Register tmp, Register scr, 683 Register retry_on_abort_count, 684 RTMLockingCounters* stack_rtm_counters, 685 Metadata* method_data, bool profile_rtm, 686 Label& DONE_LABEL, Label& IsInflated); 687 void rtm_inflated_locking(Register obj, Register box, Register tmp, 688 Register scr, Register retry_on_busy_count, 689 Register retry_on_abort_count, 690 RTMLockingCounters* rtm_counters, 691 Metadata* method_data, bool profile_rtm, 692 Label& DONE_LABEL); 693 #endif 694 #endif 695 696 Condition negate_condition(Condition cond); 697 698 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit 699 // operands. In general the names are modified to avoid hiding the instruction in Assembler 700 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers 701 // here in MacroAssembler. The major exception to this rule is call 702 703 // Arithmetics 704 705 addptr(Address dst,int32_t src)706 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } 707 void addptr(Address dst, Register src); 708 addptr(Register dst,Address src)709 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } 710 void addptr(Register dst, int32_t src); 711 void addptr(Register dst, Register src); addptr(Register dst,RegisterOrConstant src)712 void addptr(Register dst, RegisterOrConstant src) { 713 if (src.is_constant()) addptr(dst, (int) src.as_constant()); 714 else addptr(dst, src.as_register()); 715 } 716 717 void andptr(Register dst, int32_t src); andptr(Register src1,Register src2)718 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } 719 720 void cmp8(AddressLiteral src1, int imm); 721 722 // renamed to drag out the casting of address to int32_t/intptr_t 723 void cmp32(Register src1, int32_t imm); 724 725 void cmp32(AddressLiteral src1, int32_t imm); 726 // compare reg - mem, or reg - &mem 727 void cmp32(Register src1, AddressLiteral src2); 728 729 void cmp32(Register src1, Address src2); 730 731 #ifndef _LP64 732 void cmpklass(Address dst, Metadata* obj); 733 void cmpklass(Register dst, Metadata* obj); 734 void cmpoop(Address dst, jobject obj); 735 void cmpoop(Register dst, jobject obj); 736 #endif // _LP64 737 738 // NOTE src2 must be the lval. This is NOT an mem-mem compare 739 void cmpptr(Address src1, AddressLiteral src2); 740 741 void cmpptr(Register src1, AddressLiteral src2); 742 cmpptr(Register src1,Register src2)743 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } cmpptr(Register src1,Address src2)744 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 745 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 746 cmpptr(Register src1,int32_t src2)747 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } cmpptr(Address src1,int32_t src2)748 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 749 750 // cmp64 to avoild hiding cmpq 751 void cmp64(Register src1, AddressLiteral src); 752 753 void cmpxchgptr(Register reg, Address adr); 754 755 void locked_cmpxchgptr(Register reg, AddressLiteral adr); 756 757 imulptr(Register dst,Register src)758 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } imulptr(Register dst,Register src,int imm32)759 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); } 760 761 negptr(Register dst)762 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } 763 notptr(Register dst)764 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } 765 766 void shlptr(Register dst, int32_t shift); shlptr(Register dst)767 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } 768 769 void shrptr(Register dst, int32_t shift); shrptr(Register dst)770 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } 771 sarptr(Register dst)772 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } sarptr(Register dst,int32_t src)773 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } 774 subptr(Address dst,int32_t src)775 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 776 subptr(Register dst,Address src)777 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 778 void subptr(Register dst, int32_t src); 779 // Force generation of a 4 byte immediate value even if it fits into 8bit 780 void subptr_imm32(Register dst, int32_t src); 781 void subptr(Register dst, Register src); subptr(Register dst,RegisterOrConstant src)782 void subptr(Register dst, RegisterOrConstant src) { 783 if (src.is_constant()) subptr(dst, (int) src.as_constant()); 784 else subptr(dst, src.as_register()); 785 } 786 sbbptr(Address dst,int32_t src)787 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } sbbptr(Register dst,int32_t src)788 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 789 xchgptr(Register src1,Register src2)790 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } xchgptr(Register src1,Address src2)791 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 792 xaddptr(Address src1,Register src2)793 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } 794 795 796 797 // Helper functions for statistics gathering. 798 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. 799 void cond_inc32(Condition cond, AddressLiteral counter_addr); 800 // Unconditional atomic increment. 801 void atomic_incl(Address counter_addr); 802 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1); 803 #ifdef _LP64 804 void atomic_incq(Address counter_addr); 805 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1); 806 #endif atomic_incptr(AddressLiteral counter_addr,Register scr=rscratch1)807 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; } atomic_incptr(Address counter_addr)808 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; } 809 810 void lea(Register dst, AddressLiteral adr); 811 void lea(Address dst, AddressLiteral adr); lea(Register dst,Address adr)812 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } 813 leal32(Register dst,Address src)814 void leal32(Register dst, Address src) { leal(dst, src); } 815 816 // Import other testl() methods from the parent class or else 817 // they will be hidden by the following overriding declaration. 818 using Assembler::testl; 819 void testl(Register dst, AddressLiteral src); 820 orptr(Register dst,Address src)821 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } orptr(Register dst,Register src)822 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } orptr(Register dst,int32_t src)823 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } orptr(Address dst,int32_t imm32)824 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); } 825 testptr(Register src,int32_t imm32)826 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } 827 void testptr(Register src1, Register src2); 828 xorptr(Register dst,Register src)829 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } xorptr(Register dst,Address src)830 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 831 832 // Calls 833 834 void call(Label& L, relocInfo::relocType rtype); 835 void call(Register entry); 836 837 // NOTE: this call tranfers to the effective address of entry NOT 838 // the address contained by entry. This is because this is more natural 839 // for jumps/calls. 840 void call(AddressLiteral entry); 841 842 // Emit the CompiledIC call idiom 843 void ic_call(address entry); 844 845 // Jumps 846 847 // NOTE: these jumps tranfer to the effective address of dst NOT 848 // the address contained by dst. This is because this is more natural 849 // for jumps/calls. 850 void jump(AddressLiteral dst); 851 void jump_cc(Condition cc, AddressLiteral dst); 852 853 // 32bit can do a case table jump in one instruction but we no longer allow the base 854 // to be installed in the Address class. This jump will tranfers to the address 855 // contained in the location described by entry (not the address of entry) 856 void jump(ArrayAddress entry); 857 858 // Floating 859 andpd(XMMRegister dst,Address src)860 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } 861 void andpd(XMMRegister dst, AddressLiteral src); 862 andps(XMMRegister dst,XMMRegister src)863 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } andps(XMMRegister dst,Address src)864 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } 865 void andps(XMMRegister dst, AddressLiteral src); 866 comiss(XMMRegister dst,XMMRegister src)867 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } comiss(XMMRegister dst,Address src)868 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } 869 void comiss(XMMRegister dst, AddressLiteral src); 870 comisd(XMMRegister dst,XMMRegister src)871 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } comisd(XMMRegister dst,Address src)872 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } 873 void comisd(XMMRegister dst, AddressLiteral src); 874 fadd_s(Address src)875 void fadd_s(Address src) { Assembler::fadd_s(src); } fadd_s(AddressLiteral src)876 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } 877 fldcw(Address src)878 void fldcw(Address src) { Assembler::fldcw(src); } 879 void fldcw(AddressLiteral src); 880 fld_s(int index)881 void fld_s(int index) { Assembler::fld_s(index); } fld_s(Address src)882 void fld_s(Address src) { Assembler::fld_s(src); } 883 void fld_s(AddressLiteral src); 884 fld_d(Address src)885 void fld_d(Address src) { Assembler::fld_d(src); } 886 void fld_d(AddressLiteral src); 887 fld_x(Address src)888 void fld_x(Address src) { Assembler::fld_x(src); } 889 void fld_x(AddressLiteral src); 890 fmul_s(Address src)891 void fmul_s(Address src) { Assembler::fmul_s(src); } fmul_s(AddressLiteral src)892 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } 893 ldmxcsr(Address src)894 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } 895 void ldmxcsr(AddressLiteral src); 896 897 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover 898 // all corner cases and may result in NaN and require fallback to a 899 // runtime call. 900 void fast_pow(); 901 void fast_exp(); 902 void increase_precision(); 903 void restore_precision(); 904 905 // computes exp(x). Fallback to runtime call included. exp_with_fallback(int num_fpu_regs_in_use)906 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); } 907 // computes pow(x,y). Fallback to runtime call included. pow_with_fallback(int num_fpu_regs_in_use)908 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); } 909 910 private: 911 912 // call runtime as a fallback for trig functions and pow/exp. 913 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use); 914 915 // computes 2^(Ylog2X); Ylog2X in ST(0) 916 void pow_exp_core_encoding(); 917 918 // computes pow(x,y) or exp(x). Fallback to runtime call included. 919 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use); 920 921 // these are private because users should be doing movflt/movdbl 922 movss(Address dst,XMMRegister src)923 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } movss(XMMRegister dst,XMMRegister src)924 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } movss(XMMRegister dst,Address src)925 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } 926 void movss(XMMRegister dst, AddressLiteral src); 927 movlpd(XMMRegister dst,Address src)928 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } 929 void movlpd(XMMRegister dst, AddressLiteral src); 930 931 public: 932 addsd(XMMRegister dst,XMMRegister src)933 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } addsd(XMMRegister dst,Address src)934 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } 935 void addsd(XMMRegister dst, AddressLiteral src); 936 addss(XMMRegister dst,XMMRegister src)937 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } addss(XMMRegister dst,Address src)938 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } 939 void addss(XMMRegister dst, AddressLiteral src); 940 divsd(XMMRegister dst,XMMRegister src)941 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } divsd(XMMRegister dst,Address src)942 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } 943 void divsd(XMMRegister dst, AddressLiteral src); 944 divss(XMMRegister dst,XMMRegister src)945 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } divss(XMMRegister dst,Address src)946 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } 947 void divss(XMMRegister dst, AddressLiteral src); 948 949 // Move Unaligned Double Quadword movdqu(Address dst,XMMRegister src)950 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); } movdqu(XMMRegister dst,Address src)951 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); } movdqu(XMMRegister dst,XMMRegister src)952 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); } 953 void movdqu(XMMRegister dst, AddressLiteral src); 954 955 // Move Aligned Double Quadword movdqa(XMMRegister dst,Address src)956 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); } movdqa(XMMRegister dst,XMMRegister src)957 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); } 958 void movdqa(XMMRegister dst, AddressLiteral src); 959 movsd(XMMRegister dst,XMMRegister src)960 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } movsd(Address dst,XMMRegister src)961 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } movsd(XMMRegister dst,Address src)962 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } 963 void movsd(XMMRegister dst, AddressLiteral src); 964 mulsd(XMMRegister dst,XMMRegister src)965 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } mulsd(XMMRegister dst,Address src)966 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } 967 void mulsd(XMMRegister dst, AddressLiteral src); 968 mulss(XMMRegister dst,XMMRegister src)969 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } mulss(XMMRegister dst,Address src)970 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } 971 void mulss(XMMRegister dst, AddressLiteral src); 972 973 // Carry-Less Multiplication Quadword pclmulldq(XMMRegister dst,XMMRegister src)974 void pclmulldq(XMMRegister dst, XMMRegister src) { 975 // 0x00 - multiply lower 64 bits [0:63] 976 Assembler::pclmulqdq(dst, src, 0x00); 977 } pclmulhdq(XMMRegister dst,XMMRegister src)978 void pclmulhdq(XMMRegister dst, XMMRegister src) { 979 // 0x11 - multiply upper 64 bits [64:127] 980 Assembler::pclmulqdq(dst, src, 0x11); 981 } 982 sqrtsd(XMMRegister dst,XMMRegister src)983 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } sqrtsd(XMMRegister dst,Address src)984 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } 985 void sqrtsd(XMMRegister dst, AddressLiteral src); 986 sqrtss(XMMRegister dst,XMMRegister src)987 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } sqrtss(XMMRegister dst,Address src)988 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } 989 void sqrtss(XMMRegister dst, AddressLiteral src); 990 subsd(XMMRegister dst,XMMRegister src)991 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } subsd(XMMRegister dst,Address src)992 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } 993 void subsd(XMMRegister dst, AddressLiteral src); 994 subss(XMMRegister dst,XMMRegister src)995 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } subss(XMMRegister dst,Address src)996 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } 997 void subss(XMMRegister dst, AddressLiteral src); 998 ucomiss(XMMRegister dst,XMMRegister src)999 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } ucomiss(XMMRegister dst,Address src)1000 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } 1001 void ucomiss(XMMRegister dst, AddressLiteral src); 1002 ucomisd(XMMRegister dst,XMMRegister src)1003 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } ucomisd(XMMRegister dst,Address src)1004 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } 1005 void ucomisd(XMMRegister dst, AddressLiteral src); 1006 1007 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values xorpd(XMMRegister dst,XMMRegister src)1008 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } xorpd(XMMRegister dst,Address src)1009 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } 1010 void xorpd(XMMRegister dst, AddressLiteral src); 1011 1012 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values xorps(XMMRegister dst,XMMRegister src)1013 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } xorps(XMMRegister dst,Address src)1014 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } 1015 void xorps(XMMRegister dst, AddressLiteral src); 1016 1017 // Shuffle Bytes pshufb(XMMRegister dst,XMMRegister src)1018 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); } pshufb(XMMRegister dst,Address src)1019 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); } 1020 void pshufb(XMMRegister dst, AddressLiteral src); 1021 // AVX 3-operands instructions 1022 vaddsd(XMMRegister dst,XMMRegister nds,XMMRegister src)1023 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } vaddsd(XMMRegister dst,XMMRegister nds,Address src)1024 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } 1025 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1026 vaddss(XMMRegister dst,XMMRegister nds,XMMRegister src)1027 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } vaddss(XMMRegister dst,XMMRegister nds,Address src)1028 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } 1029 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1030 vandpd(XMMRegister dst,XMMRegister nds,XMMRegister src,bool vector256)1031 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); } vandpd(XMMRegister dst,XMMRegister nds,Address src,bool vector256)1032 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); } 1033 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); 1034 vandps(XMMRegister dst,XMMRegister nds,XMMRegister src,bool vector256)1035 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); } vandps(XMMRegister dst,XMMRegister nds,Address src,bool vector256)1036 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); } 1037 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); 1038 vdivsd(XMMRegister dst,XMMRegister nds,XMMRegister src)1039 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } vdivsd(XMMRegister dst,XMMRegister nds,Address src)1040 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } 1041 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1042 vdivss(XMMRegister dst,XMMRegister nds,XMMRegister src)1043 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } vdivss(XMMRegister dst,XMMRegister nds,Address src)1044 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } 1045 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1046 vmulsd(XMMRegister dst,XMMRegister nds,XMMRegister src)1047 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } vmulsd(XMMRegister dst,XMMRegister nds,Address src)1048 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } 1049 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1050 vmulss(XMMRegister dst,XMMRegister nds,XMMRegister src)1051 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } vmulss(XMMRegister dst,XMMRegister nds,Address src)1052 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } 1053 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1054 vsubsd(XMMRegister dst,XMMRegister nds,XMMRegister src)1055 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } vsubsd(XMMRegister dst,XMMRegister nds,Address src)1056 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } 1057 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1058 vsubss(XMMRegister dst,XMMRegister nds,XMMRegister src)1059 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } vsubss(XMMRegister dst,XMMRegister nds,Address src)1060 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } 1061 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1062 1063 // AVX Vector instructions 1064 vxorpd(XMMRegister dst,XMMRegister nds,XMMRegister src,bool vector256)1065 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } vxorpd(XMMRegister dst,XMMRegister nds,Address src,bool vector256)1066 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } 1067 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); 1068 vxorps(XMMRegister dst,XMMRegister nds,XMMRegister src,bool vector256)1069 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } vxorps(XMMRegister dst,XMMRegister nds,Address src,bool vector256)1070 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } 1071 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); 1072 vpxor(XMMRegister dst,XMMRegister nds,XMMRegister src,bool vector256)1073 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { 1074 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 1075 Assembler::vpxor(dst, nds, src, vector256); 1076 else 1077 Assembler::vxorpd(dst, nds, src, vector256); 1078 } vpxor(XMMRegister dst,XMMRegister nds,Address src,bool vector256)1079 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { 1080 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 1081 Assembler::vpxor(dst, nds, src, vector256); 1082 else 1083 Assembler::vxorpd(dst, nds, src, vector256); 1084 } 1085 1086 // Simple version for AVX2 256bit vectors vpxor(XMMRegister dst,XMMRegister src)1087 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); } vpxor(XMMRegister dst,Address src)1088 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); } 1089 1090 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector. vinserti128h(XMMRegister dst,XMMRegister nds,XMMRegister src)1091 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1092 if (UseAVX > 1) // vinserti128h is available only in AVX2 1093 Assembler::vinserti128h(dst, nds, src); 1094 else 1095 Assembler::vinsertf128h(dst, nds, src); 1096 } 1097 1098 // Carry-Less Multiplication Quadword vpclmulldq(XMMRegister dst,XMMRegister nds,XMMRegister src)1099 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1100 // 0x00 - multiply lower 64 bits [0:63] 1101 Assembler::vpclmulqdq(dst, nds, src, 0x00); 1102 } vpclmulhdq(XMMRegister dst,XMMRegister nds,XMMRegister src)1103 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1104 // 0x11 - multiply upper 64 bits [64:127] 1105 Assembler::vpclmulqdq(dst, nds, src, 0x11); 1106 } 1107 1108 // Data 1109 1110 void cmov32( Condition cc, Register dst, Address src); 1111 void cmov32( Condition cc, Register dst, Register src); 1112 cmov(Condition cc,Register dst,Register src)1113 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } 1114 cmovptr(Condition cc,Register dst,Address src)1115 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } cmovptr(Condition cc,Register dst,Register src)1116 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 1117 1118 void movoop(Register dst, jobject obj); 1119 void movoop(Address dst, jobject obj); 1120 1121 void mov_metadata(Register dst, Metadata* obj); 1122 void mov_metadata(Address dst, Metadata* obj); 1123 1124 void movptr(ArrayAddress dst, Register src); 1125 // can this do an lea? 1126 void movptr(Register dst, ArrayAddress src); 1127 1128 void movptr(Register dst, Address src); 1129 1130 #ifdef _LP64 1131 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1); 1132 #else 1133 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit 1134 #endif 1135 1136 void movptr(Register dst, intptr_t src); 1137 void movptr(Register dst, Register src); 1138 void movptr(Address dst, intptr_t src); 1139 1140 void movptr(Address dst, Register src); 1141 movptr(Register dst,RegisterOrConstant src)1142 void movptr(Register dst, RegisterOrConstant src) { 1143 if (src.is_constant()) movptr(dst, src.as_constant()); 1144 else movptr(dst, src.as_register()); 1145 } 1146 1147 #ifdef _LP64 1148 // Generally the next two are only used for moving NULL 1149 // Although there are situations in initializing the mark word where 1150 // they could be used. They are dangerous. 1151 1152 // They only exist on LP64 so that int32_t and intptr_t are not the same 1153 // and we have ambiguous declarations. 1154 1155 void movptr(Address dst, int32_t imm32); 1156 void movptr(Register dst, int32_t imm32); 1157 #endif // _LP64 1158 1159 // to avoid hiding movl 1160 void mov32(AddressLiteral dst, Register src); 1161 void mov32(Register dst, AddressLiteral src); 1162 1163 // to avoid hiding movb 1164 void movbyte(ArrayAddress dst, int src); 1165 1166 // Import other mov() methods from the parent class or else 1167 // they will be hidden by the following overriding declaration. 1168 using Assembler::movdl; 1169 using Assembler::movq; 1170 void movdl(XMMRegister dst, AddressLiteral src); 1171 void movq(XMMRegister dst, AddressLiteral src); 1172 1173 // Can push value or effective address 1174 void pushptr(AddressLiteral src); 1175 pushptr(Address src)1176 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } popptr(Address src)1177 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } 1178 1179 void pushoop(jobject obj); 1180 void pushklass(Metadata* obj); 1181 1182 // sign extend as need a l to ptr sized element movl2ptr(Register dst,Address src)1183 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } movl2ptr(Register dst,Register src)1184 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } 1185 1186 // C2 compiled method's prolog code. 1187 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b); 1188 1189 // clear memory of size 'cnt' qwords, starting at 'base'. 1190 void clear_mem(Register base, Register cnt, Register rtmp); 1191 1192 // IndexOf strings. 1193 // Small strings are loaded through stack if they cross page boundary. 1194 void string_indexof(Register str1, Register str2, 1195 Register cnt1, Register cnt2, 1196 int int_cnt2, Register result, 1197 XMMRegister vec, Register tmp); 1198 1199 // IndexOf for constant substrings with size >= 8 elements 1200 // which don't need to be loaded through stack. 1201 void string_indexofC8(Register str1, Register str2, 1202 Register cnt1, Register cnt2, 1203 int int_cnt2, Register result, 1204 XMMRegister vec, Register tmp); 1205 1206 // Smallest code: we don't need to load through stack, 1207 // check string tail. 1208 1209 // Compare strings. 1210 void string_compare(Register str1, Register str2, 1211 Register cnt1, Register cnt2, Register result, 1212 XMMRegister vec1); 1213 1214 // Compare char[] arrays. 1215 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, 1216 Register limit, Register result, Register chr, 1217 XMMRegister vec1, XMMRegister vec2); 1218 1219 // Fill primitive arrays 1220 void generate_fill(BasicType t, bool aligned, 1221 Register to, Register value, Register count, 1222 Register rtmp, XMMRegister xtmp); 1223 1224 void encode_iso_array(Register src, Register dst, Register len, 1225 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3, 1226 XMMRegister tmp4, Register tmp5, Register result); 1227 1228 #ifdef _LP64 1229 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2); 1230 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1231 Register y, Register y_idx, Register z, 1232 Register carry, Register product, 1233 Register idx, Register kdx); 1234 void multiply_add_128_x_128(Register x_xstart, Register y, Register z, 1235 Register yz_idx, Register idx, 1236 Register carry, Register product, int offset); 1237 void multiply_128_x_128_bmi2_loop(Register y, Register z, 1238 Register carry, Register carry2, 1239 Register idx, Register jdx, 1240 Register yz_idx1, Register yz_idx2, 1241 Register tmp, Register tmp3, Register tmp4); 1242 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 1243 Register yz_idx, Register idx, Register jdx, 1244 Register carry, Register product, 1245 Register carry2); 1246 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 1247 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5); 1248 1249 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3, 1250 Register tmp4, Register tmp5, Register rdxReg, Register raxReg); 1251 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, 1252 Register tmp2); 1253 void multiply_add_64(Register sum, Register op1, Register op2, Register carry, 1254 Register rdxReg, Register raxReg); 1255 void add_one_64(Register z, Register zlen, Register carry, Register tmp1); 1256 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, 1257 Register tmp3, Register tmp4); 1258 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, 1259 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg); 1260 1261 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1, 1262 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, 1263 Register raxReg); 1264 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1, 1265 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, 1266 Register raxReg); 1267 #endif 1268 1269 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic. 1270 void update_byte_crc32(Register crc, Register val, Register table); 1271 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp); 1272 // Fold 128-bit data chunk 1273 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset); 1274 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf); 1275 // Fold 8-bit data 1276 void fold_8bit_crc32(Register crc, Register table, Register tmp); 1277 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp); 1278 1279 #undef VIRTUAL 1280 1281 }; 1282 1283 /** 1284 * class SkipIfEqual: 1285 * 1286 * Instantiating this class will result in assembly code being output that will 1287 * jump around any code emitted between the creation of the instance and it's 1288 * automatic destruction at the end of a scope block, depending on the value of 1289 * the flag passed to the constructor, which will be checked at run-time. 1290 */ 1291 class SkipIfEqual { 1292 private: 1293 MacroAssembler* _masm; 1294 Label _label; 1295 1296 public: 1297 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1298 ~SkipIfEqual(); 1299 }; 1300 1301 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP 1302