1 // AsmJit - Machine code generation for C++
2 //
3 // * Official AsmJit Home Page: https://asmjit.com
4 // * Official Github Repository: https://github.com/asmjit/asmjit
5 //
6 // Copyright (c) 2008-2020 The AsmJit Authors
7 //
8 // This software is provided 'as-is', without any express or implied
9 // warranty. In no event will the authors be held liable for any damages
10 // arising from the use of this software.
11 //
12 // Permission is granted to anyone to use this software for any purpose,
13 // including commercial applications, and to alter it and redistribute it
14 // freely, subject to the following restrictions:
15 //
16 // 1. The origin of this software must not be misrepresented; you must not
17 // claim that you wrote the original software. If you use this software
18 // in a product, an acknowledgment in the product documentation would be
19 // appreciated but is not required.
20 // 2. Altered source versions must be plainly marked as such, and must not be
21 // misrepresented as being the original software.
22 // 3. This notice may not be removed or altered from any source distribution.
23
24 // ----------------------------------------------------------------------------
25 // IMPORTANT: AsmJit now uses an external instruction database to populate
26 // static tables within this file. Perform the following steps to regenerate
27 // all tables enclosed by ${...}:
28 //
29 // 1. Install node.js environment <https://nodejs.org>
30 // 2. Go to asmjit/tools directory
31 // 3. Get the latest asmdb from <https://github.com/asmjit/asmdb> and
32 // copy/link the `asmdb` directory to `asmjit/tools/asmdb`.
33 // 4. Execute `node tablegen-x86.js`
34 //
35 // Instruction encoding and opcodes were added to the `x86inst.cpp` database
36 // manually in the past and they are not updated by the script as it became
37 // tricky. However, everything else is updated including instruction operands
38 // and tables required to validate them, instruction read/write information
39 // (including registers and flags), and all indexes to all tables.
40 // ----------------------------------------------------------------------------
41
42 #include "../core/api-build_p.h"
43 #ifdef ASMJIT_BUILD_X86
44
45 #include "../core/cpuinfo.h"
46 #include "../core/misc_p.h"
47 #include "../core/support.h"
48 #include "../x86/x86features.h"
49 #include "../x86/x86instdb_p.h"
50 #include "../x86/x86opcode_p.h"
51 #include "../x86/x86operand.h"
52
53 ASMJIT_BEGIN_SUB_NAMESPACE(x86)
54
55 // ============================================================================
56 // [asmjit::x86::InstDB - InstInfo]
57 // ============================================================================
58
59 // Instruction opcode definitions:
60 // - `O` encodes X86|MMX|SSE instructions.
61 // - `V` encodes VEX|XOP|EVEX instructions.
62 // - `E` encodes EVEX instructions only.
63 #define O_ENCODE(VEX, PREFIX, OPCODE, O, L, W, EvexW, N, TT) \
64 ((PREFIX) | (OPCODE) | (O) | (L) | (W) | (EvexW) | (N) | (TT) | \
65 (VEX && ((PREFIX) & Opcode::kMM_Mask) != Opcode::kMM_0F ? int(Opcode::kMM_ForceVex3) : 0))
66
67 #define O(PREFIX, OPCODE, ModO, LL, W, EvexW, N, ModRM) (O_ENCODE(0, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kModO_##ModO, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kModRM_##ModRM))
68 #define V(PREFIX, OPCODE, ModO, LL, W, EvexW, N, TT) (O_ENCODE(1, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kModO_##ModO, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kCDTT_##TT))
69 #define E(PREFIX, OPCODE, ModO, LL, W, EvexW, N, TT) (O_ENCODE(1, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kModO_##ModO, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kCDTT_##TT) | Opcode::kMM_ForceEvex)
70 #define O_FPU(PREFIX, OPCODE, ModO) (Opcode::kFPU_##PREFIX | (0x##OPCODE & 0xFFu) | ((0x##OPCODE >> 8) << Opcode::kFPU_2B_Shift) | Opcode::kModO_##ModO)
71
72 // Don't store `_nameDataIndex` if instruction names are disabled. Since some
73 // APIs can use `_nameDataIndex` it's much safer if it's zero if it's not defined.
74 #ifndef ASMJIT_NO_TEXT
75 #define NAME_DATA_INDEX(Index) Index
76 #else
77 #define NAME_DATA_INDEX(Index) 0
78 #endif
79
80 // Defines an X86 instruction.
81 #define INST(id, encoding, opcode0, opcode1, mainOpcodeIndex, altOpcodeIndex, nameDataIndex, commomInfoIndexA, commomInfoIndexB) { \
82 uint32_t(NAME_DATA_INDEX(nameDataIndex)), \
83 uint32_t(commomInfoIndexA), \
84 uint32_t(commomInfoIndexB), \
85 uint8_t(InstDB::kEncoding##encoding), \
86 uint8_t((opcode0) & 0xFFu), \
87 uint8_t(mainOpcodeIndex), \
88 uint8_t(altOpcodeIndex) \
89 }
90
91 const InstDB::InstInfo InstDB::_instInfoTable[] = {
92 /*--------------------+--------------------+------------------+--------+------------------+--------+----+----+------+----+----+
93 | Instruction | Instruction | Main Opcode | EVEX |Alternative Opcode| EVEX |Op0X|Op1X|Name-X|IdxA|IdxB|
94 | Id & Name | Encoding | (pp+mmm|op/o|L|w|W|N|TT.)|--(pp+mmm|op/o|L|w|W|N|TT.)| (auto-generated) |
95 +---------------------+--------------------+---------+----+-+-+-+-+----+---------+----+-+-+-+-+----+----+----+------+----+---*/
96 // ${InstInfo:Begin}
97 INST(None , None , 0 , 0 , 0 , 0 , 0 , 0 , 0 ), // #0
98 INST(Aaa , X86Op_xAX , O(000000,37,_,_,_,_,_,_ ), 0 , 0 , 0 , 1 , 1 , 1 ), // #1
99 INST(Aad , X86I_xAX , O(000000,D5,_,_,_,_,_,_ ), 0 , 0 , 0 , 5 , 2 , 1 ), // #2
100 INST(Aam , X86I_xAX , O(000000,D4,_,_,_,_,_,_ ), 0 , 0 , 0 , 9 , 2 , 1 ), // #3
101 INST(Aas , X86Op_xAX , O(000000,3F,_,_,_,_,_,_ ), 0 , 0 , 0 , 13 , 1 , 1 ), // #4
102 INST(Adc , X86Arith , O(000000,10,2,_,x,_,_,_ ), 0 , 1 , 0 , 17 , 3 , 2 ), // #5
103 INST(Adcx , X86Rm , O(660F38,F6,_,_,x,_,_,_ ), 0 , 2 , 0 , 21 , 4 , 3 ), // #6
104 INST(Add , X86Arith , O(000000,00,0,_,x,_,_,_ ), 0 , 0 , 0 , 3146 , 3 , 1 ), // #7
105 INST(Addpd , ExtRm , O(660F00,58,_,_,_,_,_,_ ), 0 , 3 , 0 , 5106 , 5 , 4 ), // #8
106 INST(Addps , ExtRm , O(000F00,58,_,_,_,_,_,_ ), 0 , 4 , 0 , 5118 , 5 , 5 ), // #9
107 INST(Addsd , ExtRm , O(F20F00,58,_,_,_,_,_,_ ), 0 , 5 , 0 , 5340 , 6 , 4 ), // #10
108 INST(Addss , ExtRm , O(F30F00,58,_,_,_,_,_,_ ), 0 , 6 , 0 , 3283 , 7 , 5 ), // #11
109 INST(Addsubpd , ExtRm , O(660F00,D0,_,_,_,_,_,_ ), 0 , 3 , 0 , 4845 , 5 , 6 ), // #12
110 INST(Addsubps , ExtRm , O(F20F00,D0,_,_,_,_,_,_ ), 0 , 5 , 0 , 4857 , 5 , 6 ), // #13
111 INST(Adox , X86Rm , O(F30F38,F6,_,_,x,_,_,_ ), 0 , 7 , 0 , 26 , 4 , 7 ), // #14
112 INST(Aesdec , ExtRm , O(660F38,DE,_,_,_,_,_,_ ), 0 , 2 , 0 , 3338 , 5 , 8 ), // #15
113 INST(Aesdeclast , ExtRm , O(660F38,DF,_,_,_,_,_,_ ), 0 , 2 , 0 , 3346 , 5 , 8 ), // #16
114 INST(Aesenc , ExtRm , O(660F38,DC,_,_,_,_,_,_ ), 0 , 2 , 0 , 3358 , 5 , 8 ), // #17
115 INST(Aesenclast , ExtRm , O(660F38,DD,_,_,_,_,_,_ ), 0 , 2 , 0 , 3366 , 5 , 8 ), // #18
116 INST(Aesimc , ExtRm , O(660F38,DB,_,_,_,_,_,_ ), 0 , 2 , 0 , 3378 , 5 , 8 ), // #19
117 INST(Aeskeygenassist , ExtRmi , O(660F3A,DF,_,_,_,_,_,_ ), 0 , 8 , 0 , 3386 , 8 , 8 ), // #20
118 INST(And , X86Arith , O(000000,20,4,_,x,_,_,_ ), 0 , 9 , 0 , 2525 , 9 , 1 ), // #21
119 INST(Andn , VexRvm_Wx , V(000F38,F2,_,0,x,_,_,_ ), 0 , 10 , 0 , 6814 , 10 , 9 ), // #22
120 INST(Andnpd , ExtRm , O(660F00,55,_,_,_,_,_,_ ), 0 , 3 , 0 , 3419 , 5 , 4 ), // #23
121 INST(Andnps , ExtRm , O(000F00,55,_,_,_,_,_,_ ), 0 , 4 , 0 , 3427 , 5 , 5 ), // #24
122 INST(Andpd , ExtRm , O(660F00,54,_,_,_,_,_,_ ), 0 , 3 , 0 , 4359 , 11 , 4 ), // #25
123 INST(Andps , ExtRm , O(000F00,54,_,_,_,_,_,_ ), 0 , 4 , 0 , 4369 , 11 , 5 ), // #26
124 INST(Arpl , X86Mr_NoSize , O(000000,63,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 12 , 10 ), // #27
125 INST(Bextr , VexRmv_Wx , V(000F38,F7,_,0,x,_,_,_ ), 0 , 10 , 0 , 36 , 13 , 9 ), // #28
126 INST(Blcfill , VexVm_Wx , V(XOP_M9,01,1,0,x,_,_,_ ), 0 , 11 , 0 , 42 , 14 , 11 ), // #29
127 INST(Blci , VexVm_Wx , V(XOP_M9,02,6,0,x,_,_,_ ), 0 , 12 , 0 , 50 , 14 , 11 ), // #30
128 INST(Blcic , VexVm_Wx , V(XOP_M9,01,5,0,x,_,_,_ ), 0 , 13 , 0 , 55 , 14 , 11 ), // #31
129 INST(Blcmsk , VexVm_Wx , V(XOP_M9,02,1,0,x,_,_,_ ), 0 , 11 , 0 , 61 , 14 , 11 ), // #32
130 INST(Blcs , VexVm_Wx , V(XOP_M9,01,3,0,x,_,_,_ ), 0 , 14 , 0 , 68 , 14 , 11 ), // #33
131 INST(Blendpd , ExtRmi , O(660F3A,0D,_,_,_,_,_,_ ), 0 , 8 , 0 , 3469 , 8 , 12 ), // #34
132 INST(Blendps , ExtRmi , O(660F3A,0C,_,_,_,_,_,_ ), 0 , 8 , 0 , 3478 , 8 , 12 ), // #35
133 INST(Blendvpd , ExtRm_XMM0 , O(660F38,15,_,_,_,_,_,_ ), 0 , 2 , 0 , 3487 , 15 , 12 ), // #36
134 INST(Blendvps , ExtRm_XMM0 , O(660F38,14,_,_,_,_,_,_ ), 0 , 2 , 0 , 3497 , 15 , 12 ), // #37
135 INST(Blsfill , VexVm_Wx , V(XOP_M9,01,2,0,x,_,_,_ ), 0 , 15 , 0 , 73 , 14 , 11 ), // #38
136 INST(Blsi , VexVm_Wx , V(000F38,F3,3,0,x,_,_,_ ), 0 , 16 , 0 , 81 , 14 , 9 ), // #39
137 INST(Blsic , VexVm_Wx , V(XOP_M9,01,6,0,x,_,_,_ ), 0 , 12 , 0 , 86 , 14 , 11 ), // #40
138 INST(Blsmsk , VexVm_Wx , V(000F38,F3,2,0,x,_,_,_ ), 0 , 17 , 0 , 92 , 14 , 9 ), // #41
139 INST(Blsr , VexVm_Wx , V(000F38,F3,1,0,x,_,_,_ ), 0 , 18 , 0 , 99 , 14 , 9 ), // #42
140 INST(Bndcl , X86Rm , O(F30F00,1A,_,_,_,_,_,_ ), 0 , 6 , 0 , 104 , 16 , 13 ), // #43
141 INST(Bndcn , X86Rm , O(F20F00,1B,_,_,_,_,_,_ ), 0 , 5 , 0 , 110 , 16 , 13 ), // #44
142 INST(Bndcu , X86Rm , O(F20F00,1A,_,_,_,_,_,_ ), 0 , 5 , 0 , 116 , 16 , 13 ), // #45
143 INST(Bndldx , X86Rm , O(000F00,1A,_,_,_,_,_,_ ), 0 , 4 , 0 , 122 , 17 , 13 ), // #46
144 INST(Bndmk , X86Rm , O(F30F00,1B,_,_,_,_,_,_ ), 0 , 6 , 0 , 129 , 18 , 13 ), // #47
145 INST(Bndmov , X86Bndmov , O(660F00,1A,_,_,_,_,_,_ ), O(660F00,1B,_,_,_,_,_,_ ), 3 , 1 , 135 , 19 , 13 ), // #48
146 INST(Bndstx , X86Mr , O(000F00,1B,_,_,_,_,_,_ ), 0 , 4 , 0 , 142 , 20 , 13 ), // #49
147 INST(Bound , X86Rm , O(000000,62,_,_,_,_,_,_ ), 0 , 0 , 0 , 149 , 21 , 0 ), // #50
148 INST(Bsf , X86Rm , O(000F00,BC,_,_,x,_,_,_ ), 0 , 4 , 0 , 155 , 22 , 1 ), // #51
149 INST(Bsr , X86Rm , O(000F00,BD,_,_,x,_,_,_ ), 0 , 4 , 0 , 159 , 22 , 1 ), // #52
150 INST(Bswap , X86Bswap , O(000F00,C8,_,_,x,_,_,_ ), 0 , 4 , 0 , 163 , 23 , 0 ), // #53
151 INST(Bt , X86Bt , O(000F00,A3,_,_,x,_,_,_ ), O(000F00,BA,4,_,x,_,_,_ ), 4 , 2 , 169 , 24 , 14 ), // #54
152 INST(Btc , X86Bt , O(000F00,BB,_,_,x,_,_,_ ), O(000F00,BA,7,_,x,_,_,_ ), 4 , 3 , 172 , 25 , 14 ), // #55
153 INST(Btr , X86Bt , O(000F00,B3,_,_,x,_,_,_ ), O(000F00,BA,6,_,x,_,_,_ ), 4 , 4 , 176 , 25 , 14 ), // #56
154 INST(Bts , X86Bt , O(000F00,AB,_,_,x,_,_,_ ), O(000F00,BA,5,_,x,_,_,_ ), 4 , 5 , 180 , 25 , 14 ), // #57
155 INST(Bzhi , VexRmv_Wx , V(000F38,F5,_,0,x,_,_,_ ), 0 , 10 , 0 , 184 , 13 , 15 ), // #58
156 INST(Call , X86Call , O(000000,FF,2,_,_,_,_,_ ), 0 , 1 , 0 , 3038 , 26 , 1 ), // #59
157 INST(Cbw , X86Op_xAX , O(660000,98,_,_,_,_,_,_ ), 0 , 19 , 0 , 189 , 27 , 0 ), // #60
158 INST(Cdq , X86Op_xDX_xAX , O(000000,99,_,_,_,_,_,_ ), 0 , 0 , 0 , 193 , 28 , 0 ), // #61
159 INST(Cdqe , X86Op_xAX , O(000000,98,_,_,1,_,_,_ ), 0 , 20 , 0 , 197 , 29 , 0 ), // #62
160 INST(Clac , X86Op , O(000F01,CA,_,_,_,_,_,_ ), 0 , 21 , 0 , 202 , 30 , 16 ), // #63
161 INST(Clc , X86Op , O(000000,F8,_,_,_,_,_,_ ), 0 , 0 , 0 , 207 , 30 , 17 ), // #64
162 INST(Cld , X86Op , O(000000,FC,_,_,_,_,_,_ ), 0 , 0 , 0 , 211 , 30 , 18 ), // #65
163 INST(Cldemote , X86M_Only , O(000F00,1C,0,_,_,_,_,_ ), 0 , 4 , 0 , 215 , 31 , 19 ), // #66
164 INST(Clflush , X86M_Only , O(000F00,AE,7,_,_,_,_,_ ), 0 , 22 , 0 , 224 , 31 , 20 ), // #67
165 INST(Clflushopt , X86M_Only , O(660F00,AE,7,_,_,_,_,_ ), 0 , 23 , 0 , 232 , 31 , 21 ), // #68
166 INST(Clgi , X86Op , O(000F01,DD,_,_,_,_,_,_ ), 0 , 21 , 0 , 243 , 30 , 22 ), // #69
167 INST(Cli , X86Op , O(000000,FA,_,_,_,_,_,_ ), 0 , 0 , 0 , 248 , 30 , 23 ), // #70
168 INST(Clrssbsy , X86M_Only , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 24 , 0 , 252 , 32 , 24 ), // #71
169 INST(Clts , X86Op , O(000F00,06,_,_,_,_,_,_ ), 0 , 4 , 0 , 261 , 30 , 0 ), // #72
170 INST(Clui , X86Op , O(F30F01,EE,_,_,_,_,_,_ ), 0 , 25 , 0 , 266 , 33 , 25 ), // #73
171 INST(Clwb , X86M_Only , O(660F00,AE,6,_,_,_,_,_ ), 0 , 26 , 0 , 271 , 31 , 26 ), // #74
172 INST(Clzero , X86Op_MemZAX , O(000F01,FC,_,_,_,_,_,_ ), 0 , 21 , 0 , 276 , 34 , 27 ), // #75
173 INST(Cmc , X86Op , O(000000,F5,_,_,_,_,_,_ ), 0 , 0 , 0 , 283 , 30 , 28 ), // #76
174 INST(Cmova , X86Rm , O(000F00,47,_,_,x,_,_,_ ), 0 , 4 , 0 , 287 , 22 , 29 ), // #77
175 INST(Cmovae , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 4 , 0 , 293 , 22 , 30 ), // #78
176 INST(Cmovb , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 4 , 0 , 648 , 22 , 30 ), // #79
177 INST(Cmovbe , X86Rm , O(000F00,46,_,_,x,_,_,_ ), 0 , 4 , 0 , 655 , 22 , 29 ), // #80
178 INST(Cmovc , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 4 , 0 , 300 , 22 , 30 ), // #81
179 INST(Cmove , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 4 , 0 , 663 , 22 , 31 ), // #82
180 INST(Cmovg , X86Rm , O(000F00,4F,_,_,x,_,_,_ ), 0 , 4 , 0 , 306 , 22 , 32 ), // #83
181 INST(Cmovge , X86Rm , O(000F00,4D,_,_,x,_,_,_ ), 0 , 4 , 0 , 312 , 22 , 33 ), // #84
182 INST(Cmovl , X86Rm , O(000F00,4C,_,_,x,_,_,_ ), 0 , 4 , 0 , 319 , 22 , 33 ), // #85
183 INST(Cmovle , X86Rm , O(000F00,4E,_,_,x,_,_,_ ), 0 , 4 , 0 , 325 , 22 , 32 ), // #86
184 INST(Cmovna , X86Rm , O(000F00,46,_,_,x,_,_,_ ), 0 , 4 , 0 , 332 , 22 , 29 ), // #87
185 INST(Cmovnae , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 4 , 0 , 339 , 22 , 30 ), // #88
186 INST(Cmovnb , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 4 , 0 , 670 , 22 , 30 ), // #89
187 INST(Cmovnbe , X86Rm , O(000F00,47,_,_,x,_,_,_ ), 0 , 4 , 0 , 678 , 22 , 29 ), // #90
188 INST(Cmovnc , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 4 , 0 , 347 , 22 , 30 ), // #91
189 INST(Cmovne , X86Rm , O(000F00,45,_,_,x,_,_,_ ), 0 , 4 , 0 , 687 , 22 , 31 ), // #92
190 INST(Cmovng , X86Rm , O(000F00,4E,_,_,x,_,_,_ ), 0 , 4 , 0 , 354 , 22 , 32 ), // #93
191 INST(Cmovnge , X86Rm , O(000F00,4C,_,_,x,_,_,_ ), 0 , 4 , 0 , 361 , 22 , 33 ), // #94
192 INST(Cmovnl , X86Rm , O(000F00,4D,_,_,x,_,_,_ ), 0 , 4 , 0 , 369 , 22 , 33 ), // #95
193 INST(Cmovnle , X86Rm , O(000F00,4F,_,_,x,_,_,_ ), 0 , 4 , 0 , 376 , 22 , 32 ), // #96
194 INST(Cmovno , X86Rm , O(000F00,41,_,_,x,_,_,_ ), 0 , 4 , 0 , 384 , 22 , 34 ), // #97
195 INST(Cmovnp , X86Rm , O(000F00,4B,_,_,x,_,_,_ ), 0 , 4 , 0 , 391 , 22 , 35 ), // #98
196 INST(Cmovns , X86Rm , O(000F00,49,_,_,x,_,_,_ ), 0 , 4 , 0 , 398 , 22 , 36 ), // #99
197 INST(Cmovnz , X86Rm , O(000F00,45,_,_,x,_,_,_ ), 0 , 4 , 0 , 405 , 22 , 31 ), // #100
198 INST(Cmovo , X86Rm , O(000F00,40,_,_,x,_,_,_ ), 0 , 4 , 0 , 412 , 22 , 34 ), // #101
199 INST(Cmovp , X86Rm , O(000F00,4A,_,_,x,_,_,_ ), 0 , 4 , 0 , 418 , 22 , 35 ), // #102
200 INST(Cmovpe , X86Rm , O(000F00,4A,_,_,x,_,_,_ ), 0 , 4 , 0 , 424 , 22 , 35 ), // #103
201 INST(Cmovpo , X86Rm , O(000F00,4B,_,_,x,_,_,_ ), 0 , 4 , 0 , 431 , 22 , 35 ), // #104
202 INST(Cmovs , X86Rm , O(000F00,48,_,_,x,_,_,_ ), 0 , 4 , 0 , 438 , 22 , 36 ), // #105
203 INST(Cmovz , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 4 , 0 , 444 , 22 , 31 ), // #106
204 INST(Cmp , X86Arith , O(000000,38,7,_,x,_,_,_ ), 0 , 27 , 0 , 450 , 35 , 1 ), // #107
205 INST(Cmppd , ExtRmi , O(660F00,C2,_,_,_,_,_,_ ), 0 , 3 , 0 , 3723 , 8 , 4 ), // #108
206 INST(Cmpps , ExtRmi , O(000F00,C2,_,_,_,_,_,_ ), 0 , 4 , 0 , 3730 , 8 , 5 ), // #109
207 INST(Cmps , X86StrMm , O(000000,A6,_,_,_,_,_,_ ), 0 , 0 , 0 , 454 , 36 , 37 ), // #110
208 INST(Cmpsd , ExtRmi , O(F20F00,C2,_,_,_,_,_,_ ), 0 , 5 , 0 , 3737 , 37 , 4 ), // #111
209 INST(Cmpss , ExtRmi , O(F30F00,C2,_,_,_,_,_,_ ), 0 , 6 , 0 , 3744 , 38 , 5 ), // #112
210 INST(Cmpxchg , X86Cmpxchg , O(000F00,B0,_,_,x,_,_,_ ), 0 , 4 , 0 , 459 , 39 , 38 ), // #113
211 INST(Cmpxchg16b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,1,_,_,_ ), 0 , 28 , 0 , 467 , 40 , 39 ), // #114
212 INST(Cmpxchg8b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,_,_,_,_ ), 0 , 29 , 0 , 478 , 41 , 40 ), // #115
213 INST(Comisd , ExtRm , O(660F00,2F,_,_,_,_,_,_ ), 0 , 3 , 0 , 10290, 6 , 41 ), // #116
214 INST(Comiss , ExtRm , O(000F00,2F,_,_,_,_,_,_ ), 0 , 4 , 0 , 10299, 7 , 42 ), // #117
215 INST(Cpuid , X86Op , O(000F00,A2,_,_,_,_,_,_ ), 0 , 4 , 0 , 488 , 42 , 43 ), // #118
216 INST(Cqo , X86Op_xDX_xAX , O(000000,99,_,_,1,_,_,_ ), 0 , 20 , 0 , 494 , 43 , 0 ), // #119
217 INST(Crc32 , X86Crc , O(F20F38,F0,_,_,x,_,_,_ ), 0 , 30 , 0 , 498 , 44 , 44 ), // #120
218 INST(Cvtdq2pd , ExtRm , O(F30F00,E6,_,_,_,_,_,_ ), 0 , 6 , 0 , 3791 , 6 , 4 ), // #121
219 INST(Cvtdq2ps , ExtRm , O(000F00,5B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3801 , 5 , 4 ), // #122
220 INST(Cvtpd2dq , ExtRm , O(F20F00,E6,_,_,_,_,_,_ ), 0 , 5 , 0 , 3840 , 5 , 4 ), // #123
221 INST(Cvtpd2pi , ExtRm , O(660F00,2D,_,_,_,_,_,_ ), 0 , 3 , 0 , 504 , 45 , 4 ), // #124
222 INST(Cvtpd2ps , ExtRm , O(660F00,5A,_,_,_,_,_,_ ), 0 , 3 , 0 , 3850 , 5 , 4 ), // #125
223 INST(Cvtpi2pd , ExtRm , O(660F00,2A,_,_,_,_,_,_ ), 0 , 3 , 0 , 513 , 46 , 4 ), // #126
224 INST(Cvtpi2ps , ExtRm , O(000F00,2A,_,_,_,_,_,_ ), 0 , 4 , 0 , 522 , 46 , 5 ), // #127
225 INST(Cvtps2dq , ExtRm , O(660F00,5B,_,_,_,_,_,_ ), 0 , 3 , 0 , 3902 , 5 , 4 ), // #128
226 INST(Cvtps2pd , ExtRm , O(000F00,5A,_,_,_,_,_,_ ), 0 , 4 , 0 , 3912 , 6 , 4 ), // #129
227 INST(Cvtps2pi , ExtRm , O(000F00,2D,_,_,_,_,_,_ ), 0 , 4 , 0 , 531 , 47 , 5 ), // #130
228 INST(Cvtsd2si , ExtRm_Wx_GpqOnly , O(F20F00,2D,_,_,x,_,_,_ ), 0 , 5 , 0 , 3984 , 48 , 4 ), // #131
229 INST(Cvtsd2ss , ExtRm , O(F20F00,5A,_,_,_,_,_,_ ), 0 , 5 , 0 , 3994 , 6 , 4 ), // #132
230 INST(Cvtsi2sd , ExtRm_Wx , O(F20F00,2A,_,_,x,_,_,_ ), 0 , 5 , 0 , 4015 , 49 , 4 ), // #133
231 INST(Cvtsi2ss , ExtRm_Wx , O(F30F00,2A,_,_,x,_,_,_ ), 0 , 6 , 0 , 4025 , 49 , 5 ), // #134
232 INST(Cvtss2sd , ExtRm , O(F30F00,5A,_,_,_,_,_,_ ), 0 , 6 , 0 , 4035 , 7 , 4 ), // #135
233 INST(Cvtss2si , ExtRm_Wx_GpqOnly , O(F30F00,2D,_,_,x,_,_,_ ), 0 , 6 , 0 , 4045 , 50 , 5 ), // #136
234 INST(Cvttpd2dq , ExtRm , O(660F00,E6,_,_,_,_,_,_ ), 0 , 3 , 0 , 4066 , 5 , 4 ), // #137
235 INST(Cvttpd2pi , ExtRm , O(660F00,2C,_,_,_,_,_,_ ), 0 , 3 , 0 , 540 , 45 , 4 ), // #138
236 INST(Cvttps2dq , ExtRm , O(F30F00,5B,_,_,_,_,_,_ ), 0 , 6 , 0 , 4112 , 5 , 4 ), // #139
237 INST(Cvttps2pi , ExtRm , O(000F00,2C,_,_,_,_,_,_ ), 0 , 4 , 0 , 550 , 47 , 5 ), // #140
238 INST(Cvttsd2si , ExtRm_Wx_GpqOnly , O(F20F00,2C,_,_,x,_,_,_ ), 0 , 5 , 0 , 4158 , 48 , 4 ), // #141
239 INST(Cvttss2si , ExtRm_Wx_GpqOnly , O(F30F00,2C,_,_,x,_,_,_ ), 0 , 6 , 0 , 4181 , 50 , 5 ), // #142
240 INST(Cwd , X86Op_xDX_xAX , O(660000,99,_,_,_,_,_,_ ), 0 , 19 , 0 , 560 , 51 , 0 ), // #143
241 INST(Cwde , X86Op_xAX , O(000000,98,_,_,_,_,_,_ ), 0 , 0 , 0 , 564 , 52 , 0 ), // #144
242 INST(Daa , X86Op , O(000000,27,_,_,_,_,_,_ ), 0 , 0 , 0 , 569 , 1 , 1 ), // #145
243 INST(Das , X86Op , O(000000,2F,_,_,_,_,_,_ ), 0 , 0 , 0 , 573 , 1 , 1 ), // #146
244 INST(Dec , X86IncDec , O(000000,FE,1,_,x,_,_,_ ), O(000000,48,_,_,x,_,_,_ ), 31 , 6 , 3341 , 53 , 45 ), // #147
245 INST(Div , X86M_GPB_MulDiv , O(000000,F6,6,_,x,_,_,_ ), 0 , 32 , 0 , 810 , 54 , 1 ), // #148
246 INST(Divpd , ExtRm , O(660F00,5E,_,_,_,_,_,_ ), 0 , 3 , 0 , 4280 , 5 , 4 ), // #149
247 INST(Divps , ExtRm , O(000F00,5E,_,_,_,_,_,_ ), 0 , 4 , 0 , 4287 , 5 , 5 ), // #150
248 INST(Divsd , ExtRm , O(F20F00,5E,_,_,_,_,_,_ ), 0 , 5 , 0 , 4294 , 6 , 4 ), // #151
249 INST(Divss , ExtRm , O(F30F00,5E,_,_,_,_,_,_ ), 0 , 6 , 0 , 4301 , 7 , 5 ), // #152
250 INST(Dppd , ExtRmi , O(660F3A,41,_,_,_,_,_,_ ), 0 , 8 , 0 , 4318 , 8 , 12 ), // #153
251 INST(Dpps , ExtRmi , O(660F3A,40,_,_,_,_,_,_ ), 0 , 8 , 0 , 4324 , 8 , 12 ), // #154
252 INST(Emms , X86Op , O(000F00,77,_,_,_,_,_,_ ), 0 , 4 , 0 , 778 , 55 , 46 ), // #155
253 INST(Endbr32 , X86Op_Mod11RM , O(F30F00,1E,7,_,_,_,_,3 ), 0 , 33 , 0 , 577 , 30 , 47 ), // #156
254 INST(Endbr64 , X86Op_Mod11RM , O(F30F00,1E,7,_,_,_,_,2 ), 0 , 34 , 0 , 585 , 30 , 47 ), // #157
255 INST(Enqcmd , X86EnqcmdMovdir64b , O(F20F38,F8,_,_,_,_,_,_ ), 0 , 30 , 0 , 593 , 56 , 48 ), // #158
256 INST(Enqcmds , X86EnqcmdMovdir64b , O(F30F38,F8,_,_,_,_,_,_ ), 0 , 7 , 0 , 600 , 56 , 48 ), // #159
257 INST(Enter , X86Enter , O(000000,C8,_,_,_,_,_,_ ), 0 , 0 , 0 , 3046 , 57 , 0 ), // #160
258 INST(Extractps , ExtExtract , O(660F3A,17,_,_,_,_,_,_ ), 0 , 8 , 0 , 4514 , 58 , 12 ), // #161
259 INST(Extrq , ExtExtrq , O(660F00,79,_,_,_,_,_,_ ), O(660F00,78,0,_,_,_,_,_ ), 3 , 7 , 7650 , 59 , 49 ), // #162
260 INST(F2xm1 , FpuOp , O_FPU(00,D9F0,_) , 0 , 35 , 0 , 608 , 30 , 0 ), // #163
261 INST(Fabs , FpuOp , O_FPU(00,D9E1,_) , 0 , 35 , 0 , 614 , 30 , 0 ), // #164
262 INST(Fadd , FpuArith , O_FPU(00,C0C0,0) , 0 , 36 , 0 , 2121 , 60 , 0 ), // #165
263 INST(Faddp , FpuRDef , O_FPU(00,DEC0,_) , 0 , 37 , 0 , 619 , 61 , 0 ), // #166
264 INST(Fbld , X86M_Only , O_FPU(00,00DF,4) , 0 , 38 , 0 , 625 , 62 , 0 ), // #167
265 INST(Fbstp , X86M_Only , O_FPU(00,00DF,6) , 0 , 39 , 0 , 630 , 62 , 0 ), // #168
266 INST(Fchs , FpuOp , O_FPU(00,D9E0,_) , 0 , 35 , 0 , 636 , 30 , 0 ), // #169
267 INST(Fclex , FpuOp , O_FPU(9B,DBE2,_) , 0 , 40 , 0 , 641 , 30 , 0 ), // #170
268 INST(Fcmovb , FpuR , O_FPU(00,DAC0,_) , 0 , 41 , 0 , 647 , 63 , 30 ), // #171
269 INST(Fcmovbe , FpuR , O_FPU(00,DAD0,_) , 0 , 41 , 0 , 654 , 63 , 29 ), // #172
270 INST(Fcmove , FpuR , O_FPU(00,DAC8,_) , 0 , 41 , 0 , 662 , 63 , 31 ), // #173
271 INST(Fcmovnb , FpuR , O_FPU(00,DBC0,_) , 0 , 42 , 0 , 669 , 63 , 30 ), // #174
272 INST(Fcmovnbe , FpuR , O_FPU(00,DBD0,_) , 0 , 42 , 0 , 677 , 63 , 29 ), // #175
273 INST(Fcmovne , FpuR , O_FPU(00,DBC8,_) , 0 , 42 , 0 , 686 , 63 , 31 ), // #176
274 INST(Fcmovnu , FpuR , O_FPU(00,DBD8,_) , 0 , 42 , 0 , 694 , 63 , 35 ), // #177
275 INST(Fcmovu , FpuR , O_FPU(00,DAD8,_) , 0 , 41 , 0 , 702 , 63 , 35 ), // #178
276 INST(Fcom , FpuCom , O_FPU(00,D0D0,2) , 0 , 43 , 0 , 709 , 64 , 0 ), // #179
277 INST(Fcomi , FpuR , O_FPU(00,DBF0,_) , 0 , 42 , 0 , 714 , 63 , 50 ), // #180
278 INST(Fcomip , FpuR , O_FPU(00,DFF0,_) , 0 , 44 , 0 , 720 , 63 , 50 ), // #181
279 INST(Fcomp , FpuCom , O_FPU(00,D8D8,3) , 0 , 45 , 0 , 727 , 64 , 0 ), // #182
280 INST(Fcompp , FpuOp , O_FPU(00,DED9,_) , 0 , 37 , 0 , 733 , 30 , 0 ), // #183
281 INST(Fcos , FpuOp , O_FPU(00,D9FF,_) , 0 , 35 , 0 , 740 , 30 , 0 ), // #184
282 INST(Fdecstp , FpuOp , O_FPU(00,D9F6,_) , 0 , 35 , 0 , 745 , 30 , 0 ), // #185
283 INST(Fdiv , FpuArith , O_FPU(00,F0F8,6) , 0 , 46 , 0 , 753 , 60 , 0 ), // #186
284 INST(Fdivp , FpuRDef , O_FPU(00,DEF8,_) , 0 , 37 , 0 , 758 , 61 , 0 ), // #187
285 INST(Fdivr , FpuArith , O_FPU(00,F8F0,7) , 0 , 47 , 0 , 764 , 60 , 0 ), // #188
286 INST(Fdivrp , FpuRDef , O_FPU(00,DEF0,_) , 0 , 37 , 0 , 770 , 61 , 0 ), // #189
287 INST(Femms , X86Op , O(000F00,0E,_,_,_,_,_,_ ), 0 , 4 , 0 , 777 , 30 , 51 ), // #190
288 INST(Ffree , FpuR , O_FPU(00,DDC0,_) , 0 , 48 , 0 , 783 , 63 , 0 ), // #191
289 INST(Fiadd , FpuM , O_FPU(00,00DA,0) , 0 , 49 , 0 , 789 , 65 , 0 ), // #192
290 INST(Ficom , FpuM , O_FPU(00,00DA,2) , 0 , 50 , 0 , 795 , 65 , 0 ), // #193
291 INST(Ficomp , FpuM , O_FPU(00,00DA,3) , 0 , 51 , 0 , 801 , 65 , 0 ), // #194
292 INST(Fidiv , FpuM , O_FPU(00,00DA,6) , 0 , 39 , 0 , 808 , 65 , 0 ), // #195
293 INST(Fidivr , FpuM , O_FPU(00,00DA,7) , 0 , 52 , 0 , 814 , 65 , 0 ), // #196
294 INST(Fild , FpuM , O_FPU(00,00DB,0) , O_FPU(00,00DF,5) , 49 , 8 , 821 , 66 , 0 ), // #197
295 INST(Fimul , FpuM , O_FPU(00,00DA,1) , 0 , 53 , 0 , 826 , 65 , 0 ), // #198
296 INST(Fincstp , FpuOp , O_FPU(00,D9F7,_) , 0 , 35 , 0 , 832 , 30 , 0 ), // #199
297 INST(Finit , FpuOp , O_FPU(9B,DBE3,_) , 0 , 40 , 0 , 840 , 30 , 0 ), // #200
298 INST(Fist , FpuM , O_FPU(00,00DB,2) , 0 , 50 , 0 , 846 , 65 , 0 ), // #201
299 INST(Fistp , FpuM , O_FPU(00,00DB,3) , O_FPU(00,00DF,7) , 51 , 9 , 851 , 66 , 0 ), // #202
300 INST(Fisttp , FpuM , O_FPU(00,00DB,1) , O_FPU(00,00DD,1) , 53 , 10 , 857 , 66 , 6 ), // #203
301 INST(Fisub , FpuM , O_FPU(00,00DA,4) , 0 , 38 , 0 , 864 , 65 , 0 ), // #204
302 INST(Fisubr , FpuM , O_FPU(00,00DA,5) , 0 , 54 , 0 , 870 , 65 , 0 ), // #205
303 INST(Fld , FpuFldFst , O_FPU(00,00D9,0) , O_FPU(00,00DB,5) , 49 , 11 , 877 , 67 , 0 ), // #206
304 INST(Fld1 , FpuOp , O_FPU(00,D9E8,_) , 0 , 35 , 0 , 881 , 30 , 0 ), // #207
305 INST(Fldcw , X86M_Only , O_FPU(00,00D9,5) , 0 , 54 , 0 , 886 , 68 , 0 ), // #208
306 INST(Fldenv , X86M_Only , O_FPU(00,00D9,4) , 0 , 38 , 0 , 892 , 31 , 0 ), // #209
307 INST(Fldl2e , FpuOp , O_FPU(00,D9EA,_) , 0 , 35 , 0 , 899 , 30 , 0 ), // #210
308 INST(Fldl2t , FpuOp , O_FPU(00,D9E9,_) , 0 , 35 , 0 , 906 , 30 , 0 ), // #211
309 INST(Fldlg2 , FpuOp , O_FPU(00,D9EC,_) , 0 , 35 , 0 , 913 , 30 , 0 ), // #212
310 INST(Fldln2 , FpuOp , O_FPU(00,D9ED,_) , 0 , 35 , 0 , 920 , 30 , 0 ), // #213
311 INST(Fldpi , FpuOp , O_FPU(00,D9EB,_) , 0 , 35 , 0 , 927 , 30 , 0 ), // #214
312 INST(Fldz , FpuOp , O_FPU(00,D9EE,_) , 0 , 35 , 0 , 933 , 30 , 0 ), // #215
313 INST(Fmul , FpuArith , O_FPU(00,C8C8,1) , 0 , 55 , 0 , 2163 , 60 , 0 ), // #216
314 INST(Fmulp , FpuRDef , O_FPU(00,DEC8,_) , 0 , 37 , 0 , 938 , 61 , 0 ), // #217
315 INST(Fnclex , FpuOp , O_FPU(00,DBE2,_) , 0 , 42 , 0 , 944 , 30 , 0 ), // #218
316 INST(Fninit , FpuOp , O_FPU(00,DBE3,_) , 0 , 42 , 0 , 951 , 30 , 0 ), // #219
317 INST(Fnop , FpuOp , O_FPU(00,D9D0,_) , 0 , 35 , 0 , 958 , 30 , 0 ), // #220
318 INST(Fnsave , X86M_Only , O_FPU(00,00DD,6) , 0 , 39 , 0 , 963 , 31 , 0 ), // #221
319 INST(Fnstcw , X86M_Only , O_FPU(00,00D9,7) , 0 , 52 , 0 , 970 , 68 , 0 ), // #222
320 INST(Fnstenv , X86M_Only , O_FPU(00,00D9,6) , 0 , 39 , 0 , 977 , 31 , 0 ), // #223
321 INST(Fnstsw , FpuStsw , O_FPU(00,00DD,7) , O_FPU(00,DFE0,_) , 52 , 12 , 985 , 69 , 0 ), // #224
322 INST(Fpatan , FpuOp , O_FPU(00,D9F3,_) , 0 , 35 , 0 , 992 , 30 , 0 ), // #225
323 INST(Fprem , FpuOp , O_FPU(00,D9F8,_) , 0 , 35 , 0 , 999 , 30 , 0 ), // #226
324 INST(Fprem1 , FpuOp , O_FPU(00,D9F5,_) , 0 , 35 , 0 , 1005 , 30 , 0 ), // #227
325 INST(Fptan , FpuOp , O_FPU(00,D9F2,_) , 0 , 35 , 0 , 1012 , 30 , 0 ), // #228
326 INST(Frndint , FpuOp , O_FPU(00,D9FC,_) , 0 , 35 , 0 , 1018 , 30 , 0 ), // #229
327 INST(Frstor , X86M_Only , O_FPU(00,00DD,4) , 0 , 38 , 0 , 1026 , 31 , 0 ), // #230
328 INST(Fsave , X86M_Only , O_FPU(9B,00DD,6) , 0 , 56 , 0 , 1033 , 31 , 0 ), // #231
329 INST(Fscale , FpuOp , O_FPU(00,D9FD,_) , 0 , 35 , 0 , 1039 , 30 , 0 ), // #232
330 INST(Fsin , FpuOp , O_FPU(00,D9FE,_) , 0 , 35 , 0 , 1046 , 30 , 0 ), // #233
331 INST(Fsincos , FpuOp , O_FPU(00,D9FB,_) , 0 , 35 , 0 , 1051 , 30 , 0 ), // #234
332 INST(Fsqrt , FpuOp , O_FPU(00,D9FA,_) , 0 , 35 , 0 , 1059 , 30 , 0 ), // #235
333 INST(Fst , FpuFldFst , O_FPU(00,00D9,2) , 0 , 50 , 0 , 1065 , 70 , 0 ), // #236
334 INST(Fstcw , X86M_Only , O_FPU(9B,00D9,7) , 0 , 57 , 0 , 1069 , 68 , 0 ), // #237
335 INST(Fstenv , X86M_Only , O_FPU(9B,00D9,6) , 0 , 56 , 0 , 1075 , 31 , 0 ), // #238
336 INST(Fstp , FpuFldFst , O_FPU(00,00D9,3) , O(000000,DB,7,_,_,_,_,_ ), 51 , 13 , 1082 , 67 , 0 ), // #239
337 INST(Fstsw , FpuStsw , O_FPU(9B,00DD,7) , O_FPU(9B,DFE0,_) , 57 , 14 , 1087 , 69 , 0 ), // #240
338 INST(Fsub , FpuArith , O_FPU(00,E0E8,4) , 0 , 58 , 0 , 2241 , 60 , 0 ), // #241
339 INST(Fsubp , FpuRDef , O_FPU(00,DEE8,_) , 0 , 37 , 0 , 1093 , 61 , 0 ), // #242
340 INST(Fsubr , FpuArith , O_FPU(00,E8E0,5) , 0 , 59 , 0 , 2247 , 60 , 0 ), // #243
341 INST(Fsubrp , FpuRDef , O_FPU(00,DEE0,_) , 0 , 37 , 0 , 1099 , 61 , 0 ), // #244
342 INST(Ftst , FpuOp , O_FPU(00,D9E4,_) , 0 , 35 , 0 , 1106 , 30 , 0 ), // #245
343 INST(Fucom , FpuRDef , O_FPU(00,DDE0,_) , 0 , 48 , 0 , 1111 , 61 , 0 ), // #246
344 INST(Fucomi , FpuR , O_FPU(00,DBE8,_) , 0 , 42 , 0 , 1117 , 63 , 50 ), // #247
345 INST(Fucomip , FpuR , O_FPU(00,DFE8,_) , 0 , 44 , 0 , 1124 , 63 , 50 ), // #248
346 INST(Fucomp , FpuRDef , O_FPU(00,DDE8,_) , 0 , 48 , 0 , 1132 , 61 , 0 ), // #249
347 INST(Fucompp , FpuOp , O_FPU(00,DAE9,_) , 0 , 41 , 0 , 1139 , 30 , 0 ), // #250
348 INST(Fwait , X86Op , O_FPU(00,009B,_) , 0 , 60 , 0 , 1147 , 30 , 0 ), // #251
349 INST(Fxam , FpuOp , O_FPU(00,D9E5,_) , 0 , 35 , 0 , 1153 , 30 , 0 ), // #252
350 INST(Fxch , FpuR , O_FPU(00,D9C8,_) , 0 , 35 , 0 , 1158 , 61 , 0 ), // #253
351 INST(Fxrstor , X86M_Only , O(000F00,AE,1,_,_,_,_,_ ), 0 , 29 , 0 , 1163 , 31 , 52 ), // #254
352 INST(Fxrstor64 , X86M_Only , O(000F00,AE,1,_,1,_,_,_ ), 0 , 28 , 0 , 1171 , 71 , 52 ), // #255
353 INST(Fxsave , X86M_Only , O(000F00,AE,0,_,_,_,_,_ ), 0 , 4 , 0 , 1181 , 31 , 52 ), // #256
354 INST(Fxsave64 , X86M_Only , O(000F00,AE,0,_,1,_,_,_ ), 0 , 61 , 0 , 1188 , 71 , 52 ), // #257
355 INST(Fxtract , FpuOp , O_FPU(00,D9F4,_) , 0 , 35 , 0 , 1197 , 30 , 0 ), // #258
356 INST(Fyl2x , FpuOp , O_FPU(00,D9F1,_) , 0 , 35 , 0 , 1205 , 30 , 0 ), // #259
357 INST(Fyl2xp1 , FpuOp , O_FPU(00,D9F9,_) , 0 , 35 , 0 , 1211 , 30 , 0 ), // #260
358 INST(Getsec , X86Op , O(000F00,37,_,_,_,_,_,_ ), 0 , 4 , 0 , 1219 , 30 , 53 ), // #261
359 INST(Gf2p8affineinvqb , ExtRmi , O(660F3A,CF,_,_,_,_,_,_ ), 0 , 8 , 0 , 5869 , 8 , 54 ), // #262
360 INST(Gf2p8affineqb , ExtRmi , O(660F3A,CE,_,_,_,_,_,_ ), 0 , 8 , 0 , 5887 , 8 , 54 ), // #263
361 INST(Gf2p8mulb , ExtRm , O(660F38,CF,_,_,_,_,_,_ ), 0 , 2 , 0 , 5902 , 5 , 54 ), // #264
362 INST(Haddpd , ExtRm , O(660F00,7C,_,_,_,_,_,_ ), 0 , 3 , 0 , 5913 , 5 , 6 ), // #265
363 INST(Haddps , ExtRm , O(F20F00,7C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5921 , 5 , 6 ), // #266
364 INST(Hlt , X86Op , O(000000,F4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1226 , 30 , 0 ), // #267
365 INST(Hreset , X86Op_Mod11RM_I8 , O(F30F3A,F0,0,_,_,_,_,_ ), 0 , 62 , 0 , 1230 , 72 , 55 ), // #268
366 INST(Hsubpd , ExtRm , O(660F00,7D,_,_,_,_,_,_ ), 0 , 3 , 0 , 5929 , 5 , 6 ), // #269
367 INST(Hsubps , ExtRm , O(F20F00,7D,_,_,_,_,_,_ ), 0 , 5 , 0 , 5937 , 5 , 6 ), // #270
368 INST(Idiv , X86M_GPB_MulDiv , O(000000,F6,7,_,x,_,_,_ ), 0 , 27 , 0 , 809 , 54 , 1 ), // #271
369 INST(Imul , X86Imul , O(000000,F6,5,_,x,_,_,_ ), 0 , 63 , 0 , 827 , 73 , 1 ), // #272
370 INST(In , X86In , O(000000,EC,_,_,_,_,_,_ ), O(000000,E4,_,_,_,_,_,_ ), 0 , 15 , 10462, 74 , 0 ), // #273
371 INST(Inc , X86IncDec , O(000000,FE,0,_,x,_,_,_ ), O(000000,40,_,_,x,_,_,_ ), 0 , 16 , 1237 , 53 , 45 ), // #274
372 INST(Incsspd , X86M , O(F30F00,AE,5,_,0,_,_,_ ), 0 , 64 , 0 , 1241 , 75 , 56 ), // #275
373 INST(Incsspq , X86M , O(F30F00,AE,5,_,1,_,_,_ ), 0 , 65 , 0 , 1249 , 76 , 56 ), // #276
374 INST(Ins , X86Ins , O(000000,6C,_,_,_,_,_,_ ), 0 , 0 , 0 , 1916 , 77 , 0 ), // #277
375 INST(Insertps , ExtRmi , O(660F3A,21,_,_,_,_,_,_ ), 0 , 8 , 0 , 6073 , 38 , 12 ), // #278
376 INST(Insertq , ExtInsertq , O(F20F00,79,_,_,_,_,_,_ ), O(F20F00,78,_,_,_,_,_,_ ), 5 , 17 , 1257 , 78 , 49 ), // #279
377 INST(Int , X86Int , O(000000,CD,_,_,_,_,_,_ ), 0 , 0 , 0 , 1022 , 79 , 0 ), // #280
378 INST(Int3 , X86Op , O(000000,CC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1265 , 30 , 0 ), // #281
379 INST(Into , X86Op , O(000000,CE,_,_,_,_,_,_ ), 0 , 0 , 0 , 1270 , 80 , 57 ), // #282
380 INST(Invd , X86Op , O(000F00,08,_,_,_,_,_,_ ), 0 , 4 , 0 , 10391, 30 , 43 ), // #283
381 INST(Invept , X86Rm_NoSize , O(660F38,80,_,_,_,_,_,_ ), 0 , 2 , 0 , 1275 , 81 , 58 ), // #284
382 INST(Invlpg , X86M_Only , O(000F00,01,7,_,_,_,_,_ ), 0 , 22 , 0 , 1282 , 31 , 43 ), // #285
383 INST(Invlpga , X86Op_xAddr , O(000F01,DF,_,_,_,_,_,_ ), 0 , 21 , 0 , 1289 , 82 , 22 ), // #286
384 INST(Invpcid , X86Rm_NoSize , O(660F38,82,_,_,_,_,_,_ ), 0 , 2 , 0 , 1297 , 81 , 43 ), // #287
385 INST(Invvpid , X86Rm_NoSize , O(660F38,81,_,_,_,_,_,_ ), 0 , 2 , 0 , 1305 , 81 , 58 ), // #288
386 INST(Iret , X86Op , O(660000,CF,_,_,_,_,_,_ ), 0 , 19 , 0 , 3226 , 83 , 1 ), // #289
387 INST(Iretd , X86Op , O(000000,CF,_,_,_,_,_,_ ), 0 , 0 , 0 , 1313 , 83 , 1 ), // #290
388 INST(Iretq , X86Op , O(000000,CF,_,_,1,_,_,_ ), 0 , 20 , 0 , 1319 , 84 , 1 ), // #291
389 INST(Ja , X86Jcc , O(000F00,87,_,_,_,_,_,_ ), O(000000,77,_,_,_,_,_,_ ), 4 , 18 , 1325 , 85 , 59 ), // #292
390 INST(Jae , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 4 , 19 , 1328 , 85 , 60 ), // #293
391 INST(Jb , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 4 , 20 , 1332 , 85 , 60 ), // #294
392 INST(Jbe , X86Jcc , O(000F00,86,_,_,_,_,_,_ ), O(000000,76,_,_,_,_,_,_ ), 4 , 21 , 1335 , 85 , 59 ), // #295
393 INST(Jc , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 4 , 20 , 1339 , 85 , 60 ), // #296
394 INST(Je , X86Jcc , O(000F00,84,_,_,_,_,_,_ ), O(000000,74,_,_,_,_,_,_ ), 4 , 22 , 1342 , 85 , 61 ), // #297
395 INST(Jecxz , X86JecxzLoop , 0 , O(000000,E3,_,_,_,_,_,_ ), 0 , 23 , 1345 , 86 , 0 ), // #298
396 INST(Jg , X86Jcc , O(000F00,8F,_,_,_,_,_,_ ), O(000000,7F,_,_,_,_,_,_ ), 4 , 24 , 1351 , 85 , 62 ), // #299
397 INST(Jge , X86Jcc , O(000F00,8D,_,_,_,_,_,_ ), O(000000,7D,_,_,_,_,_,_ ), 4 , 25 , 1354 , 85 , 63 ), // #300
398 INST(Jl , X86Jcc , O(000F00,8C,_,_,_,_,_,_ ), O(000000,7C,_,_,_,_,_,_ ), 4 , 26 , 1358 , 85 , 63 ), // #301
399 INST(Jle , X86Jcc , O(000F00,8E,_,_,_,_,_,_ ), O(000000,7E,_,_,_,_,_,_ ), 4 , 27 , 1361 , 85 , 62 ), // #302
400 INST(Jmp , X86Jmp , O(000000,FF,4,_,_,_,_,_ ), O(000000,EB,_,_,_,_,_,_ ), 9 , 28 , 1861 , 87 , 0 ), // #303
401 INST(Jna , X86Jcc , O(000F00,86,_,_,_,_,_,_ ), O(000000,76,_,_,_,_,_,_ ), 4 , 21 , 1365 , 85 , 59 ), // #304
402 INST(Jnae , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 4 , 20 , 1369 , 85 , 60 ), // #305
403 INST(Jnb , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 4 , 19 , 1374 , 85 , 60 ), // #306
404 INST(Jnbe , X86Jcc , O(000F00,87,_,_,_,_,_,_ ), O(000000,77,_,_,_,_,_,_ ), 4 , 18 , 1378 , 85 , 59 ), // #307
405 INST(Jnc , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 4 , 19 , 1383 , 85 , 60 ), // #308
406 INST(Jne , X86Jcc , O(000F00,85,_,_,_,_,_,_ ), O(000000,75,_,_,_,_,_,_ ), 4 , 29 , 1387 , 85 , 61 ), // #309
407 INST(Jng , X86Jcc , O(000F00,8E,_,_,_,_,_,_ ), O(000000,7E,_,_,_,_,_,_ ), 4 , 27 , 1391 , 85 , 62 ), // #310
408 INST(Jnge , X86Jcc , O(000F00,8C,_,_,_,_,_,_ ), O(000000,7C,_,_,_,_,_,_ ), 4 , 26 , 1395 , 85 , 63 ), // #311
409 INST(Jnl , X86Jcc , O(000F00,8D,_,_,_,_,_,_ ), O(000000,7D,_,_,_,_,_,_ ), 4 , 25 , 1400 , 85 , 63 ), // #312
410 INST(Jnle , X86Jcc , O(000F00,8F,_,_,_,_,_,_ ), O(000000,7F,_,_,_,_,_,_ ), 4 , 24 , 1404 , 85 , 62 ), // #313
411 INST(Jno , X86Jcc , O(000F00,81,_,_,_,_,_,_ ), O(000000,71,_,_,_,_,_,_ ), 4 , 30 , 1409 , 85 , 57 ), // #314
412 INST(Jnp , X86Jcc , O(000F00,8B,_,_,_,_,_,_ ), O(000000,7B,_,_,_,_,_,_ ), 4 , 31 , 1413 , 85 , 64 ), // #315
413 INST(Jns , X86Jcc , O(000F00,89,_,_,_,_,_,_ ), O(000000,79,_,_,_,_,_,_ ), 4 , 32 , 1417 , 85 , 65 ), // #316
414 INST(Jnz , X86Jcc , O(000F00,85,_,_,_,_,_,_ ), O(000000,75,_,_,_,_,_,_ ), 4 , 29 , 1421 , 85 , 61 ), // #317
415 INST(Jo , X86Jcc , O(000F00,80,_,_,_,_,_,_ ), O(000000,70,_,_,_,_,_,_ ), 4 , 33 , 1425 , 85 , 57 ), // #318
416 INST(Jp , X86Jcc , O(000F00,8A,_,_,_,_,_,_ ), O(000000,7A,_,_,_,_,_,_ ), 4 , 34 , 1428 , 85 , 64 ), // #319
417 INST(Jpe , X86Jcc , O(000F00,8A,_,_,_,_,_,_ ), O(000000,7A,_,_,_,_,_,_ ), 4 , 34 , 1431 , 85 , 64 ), // #320
418 INST(Jpo , X86Jcc , O(000F00,8B,_,_,_,_,_,_ ), O(000000,7B,_,_,_,_,_,_ ), 4 , 31 , 1435 , 85 , 64 ), // #321
419 INST(Js , X86Jcc , O(000F00,88,_,_,_,_,_,_ ), O(000000,78,_,_,_,_,_,_ ), 4 , 35 , 1439 , 85 , 65 ), // #322
420 INST(Jz , X86Jcc , O(000F00,84,_,_,_,_,_,_ ), O(000000,74,_,_,_,_,_,_ ), 4 , 22 , 1442 , 85 , 61 ), // #323
421 INST(Kaddb , VexRvm , V(660F00,4A,_,1,0,_,_,_ ), 0 , 66 , 0 , 1445 , 88 , 66 ), // #324
422 INST(Kaddd , VexRvm , V(660F00,4A,_,1,1,_,_,_ ), 0 , 67 , 0 , 1451 , 88 , 67 ), // #325
423 INST(Kaddq , VexRvm , V(000F00,4A,_,1,1,_,_,_ ), 0 , 68 , 0 , 1457 , 88 , 67 ), // #326
424 INST(Kaddw , VexRvm , V(000F00,4A,_,1,0,_,_,_ ), 0 , 69 , 0 , 1463 , 88 , 66 ), // #327
425 INST(Kandb , VexRvm , V(660F00,41,_,1,0,_,_,_ ), 0 , 66 , 0 , 1469 , 88 , 66 ), // #328
426 INST(Kandd , VexRvm , V(660F00,41,_,1,1,_,_,_ ), 0 , 67 , 0 , 1475 , 88 , 67 ), // #329
427 INST(Kandnb , VexRvm , V(660F00,42,_,1,0,_,_,_ ), 0 , 66 , 0 , 1481 , 88 , 66 ), // #330
428 INST(Kandnd , VexRvm , V(660F00,42,_,1,1,_,_,_ ), 0 , 67 , 0 , 1488 , 88 , 67 ), // #331
429 INST(Kandnq , VexRvm , V(000F00,42,_,1,1,_,_,_ ), 0 , 68 , 0 , 1495 , 88 , 67 ), // #332
430 INST(Kandnw , VexRvm , V(000F00,42,_,1,0,_,_,_ ), 0 , 69 , 0 , 1502 , 88 , 68 ), // #333
431 INST(Kandq , VexRvm , V(000F00,41,_,1,1,_,_,_ ), 0 , 68 , 0 , 1509 , 88 , 67 ), // #334
432 INST(Kandw , VexRvm , V(000F00,41,_,1,0,_,_,_ ), 0 , 69 , 0 , 1515 , 88 , 68 ), // #335
433 INST(Kmovb , VexKmov , V(660F00,90,_,0,0,_,_,_ ), V(660F00,92,_,0,0,_,_,_ ), 70 , 36 , 1521 , 89 , 66 ), // #336
434 INST(Kmovd , VexKmov , V(660F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,0,_,_,_ ), 71 , 37 , 8130 , 90 , 67 ), // #337
435 INST(Kmovq , VexKmov , V(000F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,1,_,_,_ ), 72 , 38 , 8141 , 91 , 67 ), // #338
436 INST(Kmovw , VexKmov , V(000F00,90,_,0,0,_,_,_ ), V(000F00,92,_,0,0,_,_,_ ), 73 , 39 , 1527 , 92 , 68 ), // #339
437 INST(Knotb , VexRm , V(660F00,44,_,0,0,_,_,_ ), 0 , 70 , 0 , 1533 , 93 , 66 ), // #340
438 INST(Knotd , VexRm , V(660F00,44,_,0,1,_,_,_ ), 0 , 71 , 0 , 1539 , 93 , 67 ), // #341
439 INST(Knotq , VexRm , V(000F00,44,_,0,1,_,_,_ ), 0 , 72 , 0 , 1545 , 93 , 67 ), // #342
440 INST(Knotw , VexRm , V(000F00,44,_,0,0,_,_,_ ), 0 , 73 , 0 , 1551 , 93 , 68 ), // #343
441 INST(Korb , VexRvm , V(660F00,45,_,1,0,_,_,_ ), 0 , 66 , 0 , 1557 , 88 , 66 ), // #344
442 INST(Kord , VexRvm , V(660F00,45,_,1,1,_,_,_ ), 0 , 67 , 0 , 1562 , 88 , 67 ), // #345
443 INST(Korq , VexRvm , V(000F00,45,_,1,1,_,_,_ ), 0 , 68 , 0 , 1567 , 88 , 67 ), // #346
444 INST(Kortestb , VexRm , V(660F00,98,_,0,0,_,_,_ ), 0 , 70 , 0 , 1572 , 93 , 69 ), // #347
445 INST(Kortestd , VexRm , V(660F00,98,_,0,1,_,_,_ ), 0 , 71 , 0 , 1581 , 93 , 70 ), // #348
446 INST(Kortestq , VexRm , V(000F00,98,_,0,1,_,_,_ ), 0 , 72 , 0 , 1590 , 93 , 70 ), // #349
447 INST(Kortestw , VexRm , V(000F00,98,_,0,0,_,_,_ ), 0 , 73 , 0 , 1599 , 93 , 71 ), // #350
448 INST(Korw , VexRvm , V(000F00,45,_,1,0,_,_,_ ), 0 , 69 , 0 , 1608 , 88 , 68 ), // #351
449 INST(Kshiftlb , VexRmi , V(660F3A,32,_,0,0,_,_,_ ), 0 , 74 , 0 , 1613 , 94 , 66 ), // #352
450 INST(Kshiftld , VexRmi , V(660F3A,33,_,0,0,_,_,_ ), 0 , 74 , 0 , 1622 , 94 , 67 ), // #353
451 INST(Kshiftlq , VexRmi , V(660F3A,33,_,0,1,_,_,_ ), 0 , 75 , 0 , 1631 , 94 , 67 ), // #354
452 INST(Kshiftlw , VexRmi , V(660F3A,32,_,0,1,_,_,_ ), 0 , 75 , 0 , 1640 , 94 , 68 ), // #355
453 INST(Kshiftrb , VexRmi , V(660F3A,30,_,0,0,_,_,_ ), 0 , 74 , 0 , 1649 , 94 , 66 ), // #356
454 INST(Kshiftrd , VexRmi , V(660F3A,31,_,0,0,_,_,_ ), 0 , 74 , 0 , 1658 , 94 , 67 ), // #357
455 INST(Kshiftrq , VexRmi , V(660F3A,31,_,0,1,_,_,_ ), 0 , 75 , 0 , 1667 , 94 , 67 ), // #358
456 INST(Kshiftrw , VexRmi , V(660F3A,30,_,0,1,_,_,_ ), 0 , 75 , 0 , 1676 , 94 , 68 ), // #359
457 INST(Ktestb , VexRm , V(660F00,99,_,0,0,_,_,_ ), 0 , 70 , 0 , 1685 , 93 , 69 ), // #360
458 INST(Ktestd , VexRm , V(660F00,99,_,0,1,_,_,_ ), 0 , 71 , 0 , 1692 , 93 , 70 ), // #361
459 INST(Ktestq , VexRm , V(000F00,99,_,0,1,_,_,_ ), 0 , 72 , 0 , 1699 , 93 , 70 ), // #362
460 INST(Ktestw , VexRm , V(000F00,99,_,0,0,_,_,_ ), 0 , 73 , 0 , 1706 , 93 , 69 ), // #363
461 INST(Kunpckbw , VexRvm , V(660F00,4B,_,1,0,_,_,_ ), 0 , 66 , 0 , 1713 , 88 , 68 ), // #364
462 INST(Kunpckdq , VexRvm , V(000F00,4B,_,1,1,_,_,_ ), 0 , 68 , 0 , 1722 , 88 , 67 ), // #365
463 INST(Kunpckwd , VexRvm , V(000F00,4B,_,1,0,_,_,_ ), 0 , 69 , 0 , 1731 , 88 , 67 ), // #366
464 INST(Kxnorb , VexRvm , V(660F00,46,_,1,0,_,_,_ ), 0 , 66 , 0 , 1740 , 88 , 66 ), // #367
465 INST(Kxnord , VexRvm , V(660F00,46,_,1,1,_,_,_ ), 0 , 67 , 0 , 1747 , 88 , 67 ), // #368
466 INST(Kxnorq , VexRvm , V(000F00,46,_,1,1,_,_,_ ), 0 , 68 , 0 , 1754 , 88 , 67 ), // #369
467 INST(Kxnorw , VexRvm , V(000F00,46,_,1,0,_,_,_ ), 0 , 69 , 0 , 1761 , 88 , 68 ), // #370
468 INST(Kxorb , VexRvm , V(660F00,47,_,1,0,_,_,_ ), 0 , 66 , 0 , 1768 , 88 , 66 ), // #371
469 INST(Kxord , VexRvm , V(660F00,47,_,1,1,_,_,_ ), 0 , 67 , 0 , 1774 , 88 , 67 ), // #372
470 INST(Kxorq , VexRvm , V(000F00,47,_,1,1,_,_,_ ), 0 , 68 , 0 , 1780 , 88 , 67 ), // #373
471 INST(Kxorw , VexRvm , V(000F00,47,_,1,0,_,_,_ ), 0 , 69 , 0 , 1786 , 88 , 68 ), // #374
472 INST(Lahf , X86Op , O(000000,9F,_,_,_,_,_,_ ), 0 , 0 , 0 , 1792 , 95 , 72 ), // #375
473 INST(Lar , X86Rm , O(000F00,02,_,_,_,_,_,_ ), 0 , 4 , 0 , 1797 , 96 , 10 ), // #376
474 INST(Lcall , X86LcallLjmp , O(000000,FF,3,_,_,_,_,_ ), O(000000,9A,_,_,_,_,_,_ ), 76 , 40 , 1801 , 97 , 1 ), // #377
475 INST(Lddqu , ExtRm , O(F20F00,F0,_,_,_,_,_,_ ), 0 , 5 , 0 , 6083 , 98 , 6 ), // #378
476 INST(Ldmxcsr , X86M_Only , O(000F00,AE,2,_,_,_,_,_ ), 0 , 77 , 0 , 6090 , 99 , 5 ), // #379
477 INST(Lds , X86Rm , O(000000,C5,_,_,_,_,_,_ ), 0 , 0 , 0 , 1807 , 100, 0 ), // #380
478 INST(Ldtilecfg , AmxCfg , V(000F38,49,_,0,0,_,_,_ ), 0 , 10 , 0 , 1811 , 101, 73 ), // #381
479 INST(Lea , X86Lea , O(000000,8D,_,_,x,_,_,_ ), 0 , 0 , 0 , 1821 , 102, 0 ), // #382
480 INST(Leave , X86Op , O(000000,C9,_,_,_,_,_,_ ), 0 , 0 , 0 , 1825 , 30 , 0 ), // #383
481 INST(Les , X86Rm , O(000000,C4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1831 , 100, 0 ), // #384
482 INST(Lfence , X86Fence , O(000F00,AE,5,_,_,_,_,_ ), 0 , 78 , 0 , 1835 , 30 , 4 ), // #385
483 INST(Lfs , X86Rm , O(000F00,B4,_,_,_,_,_,_ ), 0 , 4 , 0 , 1842 , 103, 0 ), // #386
484 INST(Lgdt , X86M_Only , O(000F00,01,2,_,_,_,_,_ ), 0 , 77 , 0 , 1846 , 31 , 0 ), // #387
485 INST(Lgs , X86Rm , O(000F00,B5,_,_,_,_,_,_ ), 0 , 4 , 0 , 1851 , 103, 0 ), // #388
486 INST(Lidt , X86M_Only , O(000F00,01,3,_,_,_,_,_ ), 0 , 79 , 0 , 1855 , 31 , 0 ), // #389
487 INST(Ljmp , X86LcallLjmp , O(000000,FF,5,_,_,_,_,_ ), O(000000,EA,_,_,_,_,_,_ ), 63 , 41 , 1860 , 104, 0 ), // #390
488 INST(Lldt , X86M_NoSize , O(000F00,00,2,_,_,_,_,_ ), 0 , 77 , 0 , 1865 , 105, 0 ), // #391
489 INST(Llwpcb , VexR_Wx , V(XOP_M9,12,0,0,x,_,_,_ ), 0 , 80 , 0 , 1870 , 106, 74 ), // #392
490 INST(Lmsw , X86M_NoSize , O(000F00,01,6,_,_,_,_,_ ), 0 , 81 , 0 , 1877 , 105, 0 ), // #393
491 INST(Lods , X86StrRm , O(000000,AC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1882 , 107, 75 ), // #394
492 INST(Loop , X86JecxzLoop , 0 , O(000000,E2,_,_,_,_,_,_ ), 0 , 42 , 1887 , 108, 0 ), // #395
493 INST(Loope , X86JecxzLoop , 0 , O(000000,E1,_,_,_,_,_,_ ), 0 , 43 , 1892 , 108, 61 ), // #396
494 INST(Loopne , X86JecxzLoop , 0 , O(000000,E0,_,_,_,_,_,_ ), 0 , 44 , 1898 , 108, 61 ), // #397
495 INST(Lsl , X86Rm , O(000F00,03,_,_,_,_,_,_ ), 0 , 4 , 0 , 1905 , 109, 10 ), // #398
496 INST(Lss , X86Rm , O(000F00,B2,_,_,_,_,_,_ ), 0 , 4 , 0 , 6581 , 103, 0 ), // #399
497 INST(Ltr , X86M_NoSize , O(000F00,00,3,_,_,_,_,_ ), 0 , 79 , 0 , 1909 , 105, 0 ), // #400
498 INST(Lwpins , VexVmi4_Wx , V(XOP_MA,12,0,0,x,_,_,_ ), 0 , 82 , 0 , 1913 , 110, 74 ), // #401
499 INST(Lwpval , VexVmi4_Wx , V(XOP_MA,12,1,0,x,_,_,_ ), 0 , 83 , 0 , 1920 , 110, 74 ), // #402
500 INST(Lzcnt , X86Rm_Raw66H , O(F30F00,BD,_,_,x,_,_,_ ), 0 , 6 , 0 , 1927 , 22 , 76 ), // #403
501 INST(Maskmovdqu , ExtRm_ZDI , O(660F00,F7,_,_,_,_,_,_ ), 0 , 3 , 0 , 6099 , 111, 4 ), // #404
502 INST(Maskmovq , ExtRm_ZDI , O(000F00,F7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8138 , 112, 77 ), // #405
503 INST(Maxpd , ExtRm , O(660F00,5F,_,_,_,_,_,_ ), 0 , 3 , 0 , 6133 , 5 , 4 ), // #406
504 INST(Maxps , ExtRm , O(000F00,5F,_,_,_,_,_,_ ), 0 , 4 , 0 , 6140 , 5 , 5 ), // #407
505 INST(Maxsd , ExtRm , O(F20F00,5F,_,_,_,_,_,_ ), 0 , 5 , 0 , 8157 , 6 , 4 ), // #408
506 INST(Maxss , ExtRm , O(F30F00,5F,_,_,_,_,_,_ ), 0 , 6 , 0 , 6154 , 7 , 5 ), // #409
507 INST(Mcommit , X86Op , O(F30F01,FA,_,_,_,_,_,_ ), 0 , 25 , 0 , 1933 , 30 , 78 ), // #410
508 INST(Mfence , X86Fence , O(000F00,AE,6,_,_,_,_,_ ), 0 , 81 , 0 , 1941 , 30 , 4 ), // #411
509 INST(Minpd , ExtRm , O(660F00,5D,_,_,_,_,_,_ ), 0 , 3 , 0 , 6183 , 5 , 4 ), // #412
510 INST(Minps , ExtRm , O(000F00,5D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6190 , 5 , 5 ), // #413
511 INST(Minsd , ExtRm , O(F20F00,5D,_,_,_,_,_,_ ), 0 , 5 , 0 , 8221 , 6 , 4 ), // #414
512 INST(Minss , ExtRm , O(F30F00,5D,_,_,_,_,_,_ ), 0 , 6 , 0 , 6204 , 7 , 5 ), // #415
513 INST(Monitor , X86Op , O(000F01,C8,_,_,_,_,_,_ ), 0 , 21 , 0 , 3232 , 113, 79 ), // #416
514 INST(Monitorx , X86Op , O(000F01,FA,_,_,_,_,_,_ ), 0 , 21 , 0 , 1948 , 113, 80 ), // #417
515 INST(Mov , X86Mov , 0 , 0 , 0 , 0 , 138 , 114, 0 ), // #418
516 INST(Movabs , X86Movabs , 0 , 0 , 0 , 0 , 1957 , 115, 0 ), // #419
517 INST(Movapd , ExtMov , O(660F00,28,_,_,_,_,_,_ ), O(660F00,29,_,_,_,_,_,_ ), 3 , 45 , 6235 , 116, 4 ), // #420
518 INST(Movaps , ExtMov , O(000F00,28,_,_,_,_,_,_ ), O(000F00,29,_,_,_,_,_,_ ), 4 , 46 , 6243 , 116, 5 ), // #421
519 INST(Movbe , ExtMovbe , O(000F38,F0,_,_,x,_,_,_ ), O(000F38,F1,_,_,x,_,_,_ ), 84 , 47 , 656 , 117, 81 ), // #422
520 INST(Movd , ExtMovd , O(000F00,6E,_,_,_,_,_,_ ), O(000F00,7E,_,_,_,_,_,_ ), 4 , 48 , 8131 , 118, 82 ), // #423
521 INST(Movddup , ExtMov , O(F20F00,12,_,_,_,_,_,_ ), 0 , 5 , 0 , 6257 , 6 , 6 ), // #424
522 INST(Movdir64b , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_ ), 0 , 2 , 0 , 1964 , 119, 83 ), // #425
523 INST(Movdiri , X86MovntiMovdiri , O(000F38,F9,_,_,_,_,_,_ ), 0 , 84 , 0 , 1974 , 120, 84 ), // #426
524 INST(Movdq2q , ExtMov , O(F20F00,D6,_,_,_,_,_,_ ), 0 , 5 , 0 , 1982 , 121, 4 ), // #427
525 INST(Movdqa , ExtMov , O(660F00,6F,_,_,_,_,_,_ ), O(660F00,7F,_,_,_,_,_,_ ), 3 , 49 , 6266 , 116, 4 ), // #428
526 INST(Movdqu , ExtMov , O(F30F00,6F,_,_,_,_,_,_ ), O(F30F00,7F,_,_,_,_,_,_ ), 6 , 50 , 6103 , 116, 4 ), // #429
527 INST(Movhlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), 0 , 4 , 0 , 6341 , 122, 5 ), // #430
528 INST(Movhpd , ExtMov , O(660F00,16,_,_,_,_,_,_ ), O(660F00,17,_,_,_,_,_,_ ), 3 , 51 , 6350 , 123, 4 ), // #431
529 INST(Movhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), O(000F00,17,_,_,_,_,_,_ ), 4 , 52 , 6358 , 123, 5 ), // #432
530 INST(Movlhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), 0 , 4 , 0 , 6366 , 122, 5 ), // #433
531 INST(Movlpd , ExtMov , O(660F00,12,_,_,_,_,_,_ ), O(660F00,13,_,_,_,_,_,_ ), 3 , 53 , 6375 , 123, 4 ), // #434
532 INST(Movlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), O(000F00,13,_,_,_,_,_,_ ), 4 , 54 , 6383 , 123, 5 ), // #435
533 INST(Movmskpd , ExtMov , O(660F00,50,_,_,_,_,_,_ ), 0 , 3 , 0 , 6391 , 124, 4 ), // #436
534 INST(Movmskps , ExtMov , O(000F00,50,_,_,_,_,_,_ ), 0 , 4 , 0 , 6401 , 124, 5 ), // #437
535 INST(Movntdq , ExtMov , 0 , O(660F00,E7,_,_,_,_,_,_ ), 0 , 55 , 6411 , 125, 4 ), // #438
536 INST(Movntdqa , ExtMov , O(660F38,2A,_,_,_,_,_,_ ), 0 , 2 , 0 , 6420 , 98 , 12 ), // #439
537 INST(Movnti , X86MovntiMovdiri , O(000F00,C3,_,_,x,_,_,_ ), 0 , 4 , 0 , 1990 , 120, 4 ), // #440
538 INST(Movntpd , ExtMov , 0 , O(660F00,2B,_,_,_,_,_,_ ), 0 , 56 , 6430 , 125, 4 ), // #441
539 INST(Movntps , ExtMov , 0 , O(000F00,2B,_,_,_,_,_,_ ), 0 , 57 , 6439 , 125, 5 ), // #442
540 INST(Movntq , ExtMov , 0 , O(000F00,E7,_,_,_,_,_,_ ), 0 , 58 , 1997 , 126, 77 ), // #443
541 INST(Movntsd , ExtMov , 0 , O(F20F00,2B,_,_,_,_,_,_ ), 0 , 59 , 2004 , 127, 49 ), // #444
542 INST(Movntss , ExtMov , 0 , O(F30F00,2B,_,_,_,_,_,_ ), 0 , 60 , 2012 , 128, 49 ), // #445
543 INST(Movq , ExtMovq , O(000F00,6E,_,_,x,_,_,_ ), O(000F00,7E,_,_,x,_,_,_ ), 4 , 61 , 8142 , 129, 82 ), // #446
544 INST(Movq2dq , ExtRm , O(F30F00,D6,_,_,_,_,_,_ ), 0 , 6 , 0 , 2020 , 130, 4 ), // #447
545 INST(Movs , X86StrMm , O(000000,A4,_,_,_,_,_,_ ), 0 , 0 , 0 , 439 , 131, 75 ), // #448
546 INST(Movsd , ExtMov , O(F20F00,10,_,_,_,_,_,_ ), O(F20F00,11,_,_,_,_,_,_ ), 5 , 62 , 6454 , 132, 4 ), // #449
547 INST(Movshdup , ExtRm , O(F30F00,16,_,_,_,_,_,_ ), 0 , 6 , 0 , 6461 , 5 , 6 ), // #450
548 INST(Movsldup , ExtRm , O(F30F00,12,_,_,_,_,_,_ ), 0 , 6 , 0 , 6471 , 5 , 6 ), // #451
549 INST(Movss , ExtMov , O(F30F00,10,_,_,_,_,_,_ ), O(F30F00,11,_,_,_,_,_,_ ), 6 , 63 , 6481 , 133, 5 ), // #452
550 INST(Movsx , X86MovsxMovzx , O(000F00,BE,_,_,x,_,_,_ ), 0 , 4 , 0 , 2028 , 134, 0 ), // #453
551 INST(Movsxd , X86Rm , O(000000,63,_,_,x,_,_,_ ), 0 , 0 , 0 , 2034 , 135, 0 ), // #454
552 INST(Movupd , ExtMov , O(660F00,10,_,_,_,_,_,_ ), O(660F00,11,_,_,_,_,_,_ ), 3 , 64 , 6488 , 116, 4 ), // #455
553 INST(Movups , ExtMov , O(000F00,10,_,_,_,_,_,_ ), O(000F00,11,_,_,_,_,_,_ ), 4 , 65 , 6496 , 116, 5 ), // #456
554 INST(Movzx , X86MovsxMovzx , O(000F00,B6,_,_,x,_,_,_ ), 0 , 4 , 0 , 2041 , 134, 0 ), // #457
555 INST(Mpsadbw , ExtRmi , O(660F3A,42,_,_,_,_,_,_ ), 0 , 8 , 0 , 6504 , 8 , 12 ), // #458
556 INST(Mul , X86M_GPB_MulDiv , O(000000,F6,4,_,x,_,_,_ ), 0 , 9 , 0 , 828 , 54 , 1 ), // #459
557 INST(Mulpd , ExtRm , O(660F00,59,_,_,_,_,_,_ ), 0 , 3 , 0 , 6558 , 5 , 4 ), // #460
558 INST(Mulps , ExtRm , O(000F00,59,_,_,_,_,_,_ ), 0 , 4 , 0 , 6565 , 5 , 5 ), // #461
559 INST(Mulsd , ExtRm , O(F20F00,59,_,_,_,_,_,_ ), 0 , 5 , 0 , 6572 , 6 , 4 ), // #462
560 INST(Mulss , ExtRm , O(F30F00,59,_,_,_,_,_,_ ), 0 , 6 , 0 , 6579 , 7 , 5 ), // #463
561 INST(Mulx , VexRvm_ZDX_Wx , V(F20F38,F6,_,0,x,_,_,_ ), 0 , 85 , 0 , 2047 , 136, 85 ), // #464
562 INST(Mwait , X86Op , O(000F01,C9,_,_,_,_,_,_ ), 0 , 21 , 0 , 3241 , 137, 79 ), // #465
563 INST(Mwaitx , X86Op , O(000F01,FB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2052 , 138, 80 ), // #466
564 INST(Neg , X86M_GPB , O(000000,F6,3,_,x,_,_,_ ), 0 , 76 , 0 , 2059 , 139, 1 ), // #467
565 INST(Nop , X86M_Nop , O(000000,90,_,_,_,_,_,_ ), 0 , 0 , 0 , 959 , 140, 0 ), // #468
566 INST(Not , X86M_GPB , O(000000,F6,2,_,x,_,_,_ ), 0 , 1 , 0 , 2063 , 139, 0 ), // #469
567 INST(Or , X86Arith , O(000000,08,1,_,x,_,_,_ ), 0 , 31 , 0 , 3237 , 141, 1 ), // #470
568 INST(Orpd , ExtRm , O(660F00,56,_,_,_,_,_,_ ), 0 , 3 , 0 , 10348, 11 , 4 ), // #471
569 INST(Orps , ExtRm , O(000F00,56,_,_,_,_,_,_ ), 0 , 4 , 0 , 10355, 11 , 5 ), // #472
570 INST(Out , X86Out , O(000000,EE,_,_,_,_,_,_ ), O(000000,E6,_,_,_,_,_,_ ), 0 , 66 , 2067 , 142, 0 ), // #473
571 INST(Outs , X86Outs , O(000000,6E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2071 , 143, 0 ), // #474
572 INST(Pabsb , ExtRm_P , O(000F38,1C,_,_,_,_,_,_ ), 0 , 84 , 0 , 6661 , 144, 86 ), // #475
573 INST(Pabsd , ExtRm_P , O(000F38,1E,_,_,_,_,_,_ ), 0 , 84 , 0 , 6668 , 144, 86 ), // #476
574 INST(Pabsw , ExtRm_P , O(000F38,1D,_,_,_,_,_,_ ), 0 , 84 , 0 , 6682 , 144, 86 ), // #477
575 INST(Packssdw , ExtRm_P , O(000F00,6B,_,_,_,_,_,_ ), 0 , 4 , 0 , 6689 , 144, 82 ), // #478
576 INST(Packsswb , ExtRm_P , O(000F00,63,_,_,_,_,_,_ ), 0 , 4 , 0 , 6699 , 144, 82 ), // #479
577 INST(Packusdw , ExtRm , O(660F38,2B,_,_,_,_,_,_ ), 0 , 2 , 0 , 6709 , 5 , 12 ), // #480
578 INST(Packuswb , ExtRm_P , O(000F00,67,_,_,_,_,_,_ ), 0 , 4 , 0 , 6719 , 144, 82 ), // #481
579 INST(Paddb , ExtRm_P , O(000F00,FC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6729 , 144, 82 ), // #482
580 INST(Paddd , ExtRm_P , O(000F00,FE,_,_,_,_,_,_ ), 0 , 4 , 0 , 6736 , 144, 82 ), // #483
581 INST(Paddq , ExtRm_P , O(000F00,D4,_,_,_,_,_,_ ), 0 , 4 , 0 , 6743 , 144, 4 ), // #484
582 INST(Paddsb , ExtRm_P , O(000F00,EC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6750 , 144, 82 ), // #485
583 INST(Paddsw , ExtRm_P , O(000F00,ED,_,_,_,_,_,_ ), 0 , 4 , 0 , 6758 , 144, 82 ), // #486
584 INST(Paddusb , ExtRm_P , O(000F00,DC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6766 , 144, 82 ), // #487
585 INST(Paddusw , ExtRm_P , O(000F00,DD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6775 , 144, 82 ), // #488
586 INST(Paddw , ExtRm_P , O(000F00,FD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6784 , 144, 82 ), // #489
587 INST(Palignr , ExtRmi_P , O(000F3A,0F,_,_,_,_,_,_ ), 0 , 86 , 0 , 6791 , 145, 6 ), // #490
588 INST(Pand , ExtRm_P , O(000F00,DB,_,_,_,_,_,_ ), 0 , 4 , 0 , 6800 , 146, 82 ), // #491
589 INST(Pandn , ExtRm_P , O(000F00,DF,_,_,_,_,_,_ ), 0 , 4 , 0 , 6813 , 147, 82 ), // #492
590 INST(Pause , X86Op , O(F30000,90,_,_,_,_,_,_ ), 0 , 87 , 0 , 3195 , 30 , 0 ), // #493
591 INST(Pavgb , ExtRm_P , O(000F00,E0,_,_,_,_,_,_ ), 0 , 4 , 0 , 6843 , 144, 87 ), // #494
592 INST(Pavgusb , Ext3dNow , O(000F0F,BF,_,_,_,_,_,_ ), 0 , 88 , 0 , 2076 , 148, 51 ), // #495
593 INST(Pavgw , ExtRm_P , O(000F00,E3,_,_,_,_,_,_ ), 0 , 4 , 0 , 6850 , 144, 87 ), // #496
594 INST(Pblendvb , ExtRm_XMM0 , O(660F38,10,_,_,_,_,_,_ ), 0 , 2 , 0 , 6906 , 15 , 12 ), // #497
595 INST(Pblendw , ExtRmi , O(660F3A,0E,_,_,_,_,_,_ ), 0 , 8 , 0 , 6916 , 8 , 12 ), // #498
596 INST(Pclmulqdq , ExtRmi , O(660F3A,44,_,_,_,_,_,_ ), 0 , 8 , 0 , 7009 , 8 , 88 ), // #499
597 INST(Pcmpeqb , ExtRm_P , O(000F00,74,_,_,_,_,_,_ ), 0 , 4 , 0 , 7041 , 147, 82 ), // #500
598 INST(Pcmpeqd , ExtRm_P , O(000F00,76,_,_,_,_,_,_ ), 0 , 4 , 0 , 7050 , 147, 82 ), // #501
599 INST(Pcmpeqq , ExtRm , O(660F38,29,_,_,_,_,_,_ ), 0 , 2 , 0 , 7059 , 149, 12 ), // #502
600 INST(Pcmpeqw , ExtRm_P , O(000F00,75,_,_,_,_,_,_ ), 0 , 4 , 0 , 7068 , 147, 82 ), // #503
601 INST(Pcmpestri , ExtRmi , O(660F3A,61,_,_,_,_,_,_ ), 0 , 8 , 0 , 7077 , 150, 89 ), // #504
602 INST(Pcmpestrm , ExtRmi , O(660F3A,60,_,_,_,_,_,_ ), 0 , 8 , 0 , 7088 , 151, 89 ), // #505
603 INST(Pcmpgtb , ExtRm_P , O(000F00,64,_,_,_,_,_,_ ), 0 , 4 , 0 , 7099 , 147, 82 ), // #506
604 INST(Pcmpgtd , ExtRm_P , O(000F00,66,_,_,_,_,_,_ ), 0 , 4 , 0 , 7108 , 147, 82 ), // #507
605 INST(Pcmpgtq , ExtRm , O(660F38,37,_,_,_,_,_,_ ), 0 , 2 , 0 , 7117 , 149, 44 ), // #508
606 INST(Pcmpgtw , ExtRm_P , O(000F00,65,_,_,_,_,_,_ ), 0 , 4 , 0 , 7126 , 147, 82 ), // #509
607 INST(Pcmpistri , ExtRmi , O(660F3A,63,_,_,_,_,_,_ ), 0 , 8 , 0 , 7135 , 152, 89 ), // #510
608 INST(Pcmpistrm , ExtRmi , O(660F3A,62,_,_,_,_,_,_ ), 0 , 8 , 0 , 7146 , 153, 89 ), // #511
609 INST(Pconfig , X86Op , O(000F01,C5,_,_,_,_,_,_ ), 0 , 21 , 0 , 2084 , 30 , 90 ), // #512
610 INST(Pdep , VexRvm_Wx , V(F20F38,F5,_,0,x,_,_,_ ), 0 , 85 , 0 , 2092 , 10 , 85 ), // #513
611 INST(Pext , VexRvm_Wx , V(F30F38,F5,_,0,x,_,_,_ ), 0 , 89 , 0 , 2097 , 10 , 85 ), // #514
612 INST(Pextrb , ExtExtract , O(000F3A,14,_,_,_,_,_,_ ), 0 , 86 , 0 , 7633 , 154, 12 ), // #515
613 INST(Pextrd , ExtExtract , O(000F3A,16,_,_,_,_,_,_ ), 0 , 86 , 0 , 7641 , 58 , 12 ), // #516
614 INST(Pextrq , ExtExtract , O(000F3A,16,_,_,1,_,_,_ ), 0 , 90 , 0 , 7649 , 155, 12 ), // #517
615 INST(Pextrw , ExtPextrw , O(000F00,C5,_,_,_,_,_,_ ), O(000F3A,15,_,_,_,_,_,_ ), 4 , 67 , 7657 , 156, 91 ), // #518
616 INST(Pf2id , Ext3dNow , O(000F0F,1D,_,_,_,_,_,_ ), 0 , 88 , 0 , 2102 , 148, 51 ), // #519
617 INST(Pf2iw , Ext3dNow , O(000F0F,1C,_,_,_,_,_,_ ), 0 , 88 , 0 , 2108 , 148, 92 ), // #520
618 INST(Pfacc , Ext3dNow , O(000F0F,AE,_,_,_,_,_,_ ), 0 , 88 , 0 , 2114 , 148, 51 ), // #521
619 INST(Pfadd , Ext3dNow , O(000F0F,9E,_,_,_,_,_,_ ), 0 , 88 , 0 , 2120 , 148, 51 ), // #522
620 INST(Pfcmpeq , Ext3dNow , O(000F0F,B0,_,_,_,_,_,_ ), 0 , 88 , 0 , 2126 , 148, 51 ), // #523
621 INST(Pfcmpge , Ext3dNow , O(000F0F,90,_,_,_,_,_,_ ), 0 , 88 , 0 , 2134 , 148, 51 ), // #524
622 INST(Pfcmpgt , Ext3dNow , O(000F0F,A0,_,_,_,_,_,_ ), 0 , 88 , 0 , 2142 , 148, 51 ), // #525
623 INST(Pfmax , Ext3dNow , O(000F0F,A4,_,_,_,_,_,_ ), 0 , 88 , 0 , 2150 , 148, 51 ), // #526
624 INST(Pfmin , Ext3dNow , O(000F0F,94,_,_,_,_,_,_ ), 0 , 88 , 0 , 2156 , 148, 51 ), // #527
625 INST(Pfmul , Ext3dNow , O(000F0F,B4,_,_,_,_,_,_ ), 0 , 88 , 0 , 2162 , 148, 51 ), // #528
626 INST(Pfnacc , Ext3dNow , O(000F0F,8A,_,_,_,_,_,_ ), 0 , 88 , 0 , 2168 , 148, 92 ), // #529
627 INST(Pfpnacc , Ext3dNow , O(000F0F,8E,_,_,_,_,_,_ ), 0 , 88 , 0 , 2175 , 148, 92 ), // #530
628 INST(Pfrcp , Ext3dNow , O(000F0F,96,_,_,_,_,_,_ ), 0 , 88 , 0 , 2183 , 148, 51 ), // #531
629 INST(Pfrcpit1 , Ext3dNow , O(000F0F,A6,_,_,_,_,_,_ ), 0 , 88 , 0 , 2189 , 148, 51 ), // #532
630 INST(Pfrcpit2 , Ext3dNow , O(000F0F,B6,_,_,_,_,_,_ ), 0 , 88 , 0 , 2198 , 148, 51 ), // #533
631 INST(Pfrcpv , Ext3dNow , O(000F0F,86,_,_,_,_,_,_ ), 0 , 88 , 0 , 2207 , 148, 93 ), // #534
632 INST(Pfrsqit1 , Ext3dNow , O(000F0F,A7,_,_,_,_,_,_ ), 0 , 88 , 0 , 2214 , 148, 51 ), // #535
633 INST(Pfrsqrt , Ext3dNow , O(000F0F,97,_,_,_,_,_,_ ), 0 , 88 , 0 , 2223 , 148, 51 ), // #536
634 INST(Pfrsqrtv , Ext3dNow , O(000F0F,87,_,_,_,_,_,_ ), 0 , 88 , 0 , 2231 , 148, 93 ), // #537
635 INST(Pfsub , Ext3dNow , O(000F0F,9A,_,_,_,_,_,_ ), 0 , 88 , 0 , 2240 , 148, 51 ), // #538
636 INST(Pfsubr , Ext3dNow , O(000F0F,AA,_,_,_,_,_,_ ), 0 , 88 , 0 , 2246 , 148, 51 ), // #539
637 INST(Phaddd , ExtRm_P , O(000F38,02,_,_,_,_,_,_ ), 0 , 84 , 0 , 7736 , 144, 86 ), // #540
638 INST(Phaddsw , ExtRm_P , O(000F38,03,_,_,_,_,_,_ ), 0 , 84 , 0 , 7753 , 144, 86 ), // #541
639 INST(Phaddw , ExtRm_P , O(000F38,01,_,_,_,_,_,_ ), 0 , 84 , 0 , 7822 , 144, 86 ), // #542
640 INST(Phminposuw , ExtRm , O(660F38,41,_,_,_,_,_,_ ), 0 , 2 , 0 , 7848 , 5 , 12 ), // #543
641 INST(Phsubd , ExtRm_P , O(000F38,06,_,_,_,_,_,_ ), 0 , 84 , 0 , 7869 , 144, 86 ), // #544
642 INST(Phsubsw , ExtRm_P , O(000F38,07,_,_,_,_,_,_ ), 0 , 84 , 0 , 7886 , 144, 86 ), // #545
643 INST(Phsubw , ExtRm_P , O(000F38,05,_,_,_,_,_,_ ), 0 , 84 , 0 , 7895 , 144, 86 ), // #546
644 INST(Pi2fd , Ext3dNow , O(000F0F,0D,_,_,_,_,_,_ ), 0 , 88 , 0 , 2253 , 148, 51 ), // #547
645 INST(Pi2fw , Ext3dNow , O(000F0F,0C,_,_,_,_,_,_ ), 0 , 88 , 0 , 2259 , 148, 92 ), // #548
646 INST(Pinsrb , ExtRmi , O(660F3A,20,_,_,_,_,_,_ ), 0 , 8 , 0 , 7912 , 157, 12 ), // #549
647 INST(Pinsrd , ExtRmi , O(660F3A,22,_,_,_,_,_,_ ), 0 , 8 , 0 , 7920 , 158, 12 ), // #550
648 INST(Pinsrq , ExtRmi , O(660F3A,22,_,_,1,_,_,_ ), 0 , 91 , 0 , 7928 , 159, 12 ), // #551
649 INST(Pinsrw , ExtRmi_P , O(000F00,C4,_,_,_,_,_,_ ), 0 , 4 , 0 , 7936 , 160, 87 ), // #552
650 INST(Pmaddubsw , ExtRm_P , O(000F38,04,_,_,_,_,_,_ ), 0 , 84 , 0 , 8106 , 144, 86 ), // #553
651 INST(Pmaddwd , ExtRm_P , O(000F00,F5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8117 , 144, 82 ), // #554
652 INST(Pmaxsb , ExtRm , O(660F38,3C,_,_,_,_,_,_ ), 0 , 2 , 0 , 8148 , 11 , 12 ), // #555
653 INST(Pmaxsd , ExtRm , O(660F38,3D,_,_,_,_,_,_ ), 0 , 2 , 0 , 8156 , 11 , 12 ), // #556
654 INST(Pmaxsw , ExtRm_P , O(000F00,EE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8172 , 146, 87 ), // #557
655 INST(Pmaxub , ExtRm_P , O(000F00,DE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8180 , 146, 87 ), // #558
656 INST(Pmaxud , ExtRm , O(660F38,3F,_,_,_,_,_,_ ), 0 , 2 , 0 , 8188 , 11 , 12 ), // #559
657 INST(Pmaxuw , ExtRm , O(660F38,3E,_,_,_,_,_,_ ), 0 , 2 , 0 , 8204 , 11 , 12 ), // #560
658 INST(Pminsb , ExtRm , O(660F38,38,_,_,_,_,_,_ ), 0 , 2 , 0 , 8212 , 11 , 12 ), // #561
659 INST(Pminsd , ExtRm , O(660F38,39,_,_,_,_,_,_ ), 0 , 2 , 0 , 8220 , 11 , 12 ), // #562
660 INST(Pminsw , ExtRm_P , O(000F00,EA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8236 , 146, 87 ), // #563
661 INST(Pminub , ExtRm_P , O(000F00,DA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8244 , 146, 87 ), // #564
662 INST(Pminud , ExtRm , O(660F38,3B,_,_,_,_,_,_ ), 0 , 2 , 0 , 8252 , 11 , 12 ), // #565
663 INST(Pminuw , ExtRm , O(660F38,3A,_,_,_,_,_,_ ), 0 , 2 , 0 , 8268 , 11 , 12 ), // #566
664 INST(Pmovmskb , ExtRm_P , O(000F00,D7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8346 , 161, 87 ), // #567
665 INST(Pmovsxbd , ExtRm , O(660F38,21,_,_,_,_,_,_ ), 0 , 2 , 0 , 8443 , 7 , 12 ), // #568
666 INST(Pmovsxbq , ExtRm , O(660F38,22,_,_,_,_,_,_ ), 0 , 2 , 0 , 8453 , 162, 12 ), // #569
667 INST(Pmovsxbw , ExtRm , O(660F38,20,_,_,_,_,_,_ ), 0 , 2 , 0 , 8463 , 6 , 12 ), // #570
668 INST(Pmovsxdq , ExtRm , O(660F38,25,_,_,_,_,_,_ ), 0 , 2 , 0 , 8473 , 6 , 12 ), // #571
669 INST(Pmovsxwd , ExtRm , O(660F38,23,_,_,_,_,_,_ ), 0 , 2 , 0 , 8483 , 6 , 12 ), // #572
670 INST(Pmovsxwq , ExtRm , O(660F38,24,_,_,_,_,_,_ ), 0 , 2 , 0 , 8493 , 7 , 12 ), // #573
671 INST(Pmovzxbd , ExtRm , O(660F38,31,_,_,_,_,_,_ ), 0 , 2 , 0 , 8580 , 7 , 12 ), // #574
672 INST(Pmovzxbq , ExtRm , O(660F38,32,_,_,_,_,_,_ ), 0 , 2 , 0 , 8590 , 162, 12 ), // #575
673 INST(Pmovzxbw , ExtRm , O(660F38,30,_,_,_,_,_,_ ), 0 , 2 , 0 , 8600 , 6 , 12 ), // #576
674 INST(Pmovzxdq , ExtRm , O(660F38,35,_,_,_,_,_,_ ), 0 , 2 , 0 , 8610 , 6 , 12 ), // #577
675 INST(Pmovzxwd , ExtRm , O(660F38,33,_,_,_,_,_,_ ), 0 , 2 , 0 , 8620 , 6 , 12 ), // #578
676 INST(Pmovzxwq , ExtRm , O(660F38,34,_,_,_,_,_,_ ), 0 , 2 , 0 , 8630 , 7 , 12 ), // #579
677 INST(Pmuldq , ExtRm , O(660F38,28,_,_,_,_,_,_ ), 0 , 2 , 0 , 8640 , 5 , 12 ), // #580
678 INST(Pmulhrsw , ExtRm_P , O(000F38,0B,_,_,_,_,_,_ ), 0 , 84 , 0 , 8648 , 144, 86 ), // #581
679 INST(Pmulhrw , Ext3dNow , O(000F0F,B7,_,_,_,_,_,_ ), 0 , 88 , 0 , 2265 , 148, 51 ), // #582
680 INST(Pmulhuw , ExtRm_P , O(000F00,E4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8658 , 144, 87 ), // #583
681 INST(Pmulhw , ExtRm_P , O(000F00,E5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8667 , 144, 82 ), // #584
682 INST(Pmulld , ExtRm , O(660F38,40,_,_,_,_,_,_ ), 0 , 2 , 0 , 8675 , 5 , 12 ), // #585
683 INST(Pmullw , ExtRm_P , O(000F00,D5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8691 , 144, 82 ), // #586
684 INST(Pmuludq , ExtRm_P , O(000F00,F4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8714 , 144, 4 ), // #587
685 INST(Pop , X86Pop , O(000000,8F,0,_,_,_,_,_ ), O(000000,58,_,_,_,_,_,_ ), 0 , 68 , 2273 , 163, 0 ), // #588
686 INST(Popa , X86Op , O(660000,61,_,_,_,_,_,_ ), 0 , 19 , 0 , 2277 , 80 , 0 ), // #589
687 INST(Popad , X86Op , O(000000,61,_,_,_,_,_,_ ), 0 , 0 , 0 , 2282 , 80 , 0 ), // #590
688 INST(Popcnt , X86Rm_Raw66H , O(F30F00,B8,_,_,x,_,_,_ ), 0 , 6 , 0 , 2288 , 22 , 94 ), // #591
689 INST(Popf , X86Op , O(660000,9D,_,_,_,_,_,_ ), 0 , 19 , 0 , 2295 , 30 , 95 ), // #592
690 INST(Popfd , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2300 , 80 , 95 ), // #593
691 INST(Popfq , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2306 , 33 , 95 ), // #594
692 INST(Por , ExtRm_P , O(000F00,EB,_,_,_,_,_,_ ), 0 , 4 , 0 , 8759 , 146, 82 ), // #595
693 INST(Prefetch , X86M_Only , O(000F00,0D,0,_,_,_,_,_ ), 0 , 4 , 0 , 2312 , 31 , 51 ), // #596
694 INST(Prefetchnta , X86M_Only , O(000F00,18,0,_,_,_,_,_ ), 0 , 4 , 0 , 2321 , 31 , 77 ), // #597
695 INST(Prefetcht0 , X86M_Only , O(000F00,18,1,_,_,_,_,_ ), 0 , 29 , 0 , 2333 , 31 , 77 ), // #598
696 INST(Prefetcht1 , X86M_Only , O(000F00,18,2,_,_,_,_,_ ), 0 , 77 , 0 , 2344 , 31 , 77 ), // #599
697 INST(Prefetcht2 , X86M_Only , O(000F00,18,3,_,_,_,_,_ ), 0 , 79 , 0 , 2355 , 31 , 77 ), // #600
698 INST(Prefetchw , X86M_Only , O(000F00,0D,1,_,_,_,_,_ ), 0 , 29 , 0 , 2366 , 31 , 96 ), // #601
699 INST(Prefetchwt1 , X86M_Only , O(000F00,0D,2,_,_,_,_,_ ), 0 , 77 , 0 , 2376 , 31 , 97 ), // #602
700 INST(Psadbw , ExtRm_P , O(000F00,F6,_,_,_,_,_,_ ), 0 , 4 , 0 , 4272 , 144, 87 ), // #603
701 INST(Pshufb , ExtRm_P , O(000F38,00,_,_,_,_,_,_ ), 0 , 84 , 0 , 9085 , 144, 86 ), // #604
702 INST(Pshufd , ExtRmi , O(660F00,70,_,_,_,_,_,_ ), 0 , 3 , 0 , 9106 , 8 , 4 ), // #605
703 INST(Pshufhw , ExtRmi , O(F30F00,70,_,_,_,_,_,_ ), 0 , 6 , 0 , 9114 , 8 , 4 ), // #606
704 INST(Pshuflw , ExtRmi , O(F20F00,70,_,_,_,_,_,_ ), 0 , 5 , 0 , 9123 , 8 , 4 ), // #607
705 INST(Pshufw , ExtRmi_P , O(000F00,70,_,_,_,_,_,_ ), 0 , 4 , 0 , 2388 , 164, 77 ), // #608
706 INST(Psignb , ExtRm_P , O(000F38,08,_,_,_,_,_,_ ), 0 , 84 , 0 , 9132 , 144, 86 ), // #609
707 INST(Psignd , ExtRm_P , O(000F38,0A,_,_,_,_,_,_ ), 0 , 84 , 0 , 9140 , 144, 86 ), // #610
708 INST(Psignw , ExtRm_P , O(000F38,09,_,_,_,_,_,_ ), 0 , 84 , 0 , 9148 , 144, 86 ), // #611
709 INST(Pslld , ExtRmRi_P , O(000F00,F2,_,_,_,_,_,_ ), O(000F00,72,6,_,_,_,_,_ ), 4 , 69 , 9156 , 165, 82 ), // #612
710 INST(Pslldq , ExtRmRi , 0 , O(660F00,73,7,_,_,_,_,_ ), 0 , 70 , 9163 , 166, 4 ), // #613
711 INST(Psllq , ExtRmRi_P , O(000F00,F3,_,_,_,_,_,_ ), O(000F00,73,6,_,_,_,_,_ ), 4 , 71 , 9171 , 165, 82 ), // #614
712 INST(Psllw , ExtRmRi_P , O(000F00,F1,_,_,_,_,_,_ ), O(000F00,71,6,_,_,_,_,_ ), 4 , 72 , 9202 , 165, 82 ), // #615
713 INST(Psmash , X86Op , O(F30F01,FF,_,_,_,_,_,_ ), 0 , 25 , 0 , 2395 , 33 , 98 ), // #616
714 INST(Psrad , ExtRmRi_P , O(000F00,E2,_,_,_,_,_,_ ), O(000F00,72,4,_,_,_,_,_ ), 4 , 73 , 9209 , 165, 82 ), // #617
715 INST(Psraw , ExtRmRi_P , O(000F00,E1,_,_,_,_,_,_ ), O(000F00,71,4,_,_,_,_,_ ), 4 , 74 , 9247 , 165, 82 ), // #618
716 INST(Psrld , ExtRmRi_P , O(000F00,D2,_,_,_,_,_,_ ), O(000F00,72,2,_,_,_,_,_ ), 4 , 75 , 9254 , 165, 82 ), // #619
717 INST(Psrldq , ExtRmRi , 0 , O(660F00,73,3,_,_,_,_,_ ), 0 , 76 , 9261 , 166, 4 ), // #620
718 INST(Psrlq , ExtRmRi_P , O(000F00,D3,_,_,_,_,_,_ ), O(000F00,73,2,_,_,_,_,_ ), 4 , 77 , 9269 , 165, 82 ), // #621
719 INST(Psrlw , ExtRmRi_P , O(000F00,D1,_,_,_,_,_,_ ), O(000F00,71,2,_,_,_,_,_ ), 4 , 78 , 9300 , 165, 82 ), // #622
720 INST(Psubb , ExtRm_P , O(000F00,F8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9307 , 147, 82 ), // #623
721 INST(Psubd , ExtRm_P , O(000F00,FA,_,_,_,_,_,_ ), 0 , 4 , 0 , 9314 , 147, 82 ), // #624
722 INST(Psubq , ExtRm_P , O(000F00,FB,_,_,_,_,_,_ ), 0 , 4 , 0 , 9321 , 147, 4 ), // #625
723 INST(Psubsb , ExtRm_P , O(000F00,E8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9328 , 147, 82 ), // #626
724 INST(Psubsw , ExtRm_P , O(000F00,E9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9336 , 147, 82 ), // #627
725 INST(Psubusb , ExtRm_P , O(000F00,D8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9344 , 147, 82 ), // #628
726 INST(Psubusw , ExtRm_P , O(000F00,D9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9353 , 147, 82 ), // #629
727 INST(Psubw , ExtRm_P , O(000F00,F9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9362 , 147, 82 ), // #630
728 INST(Pswapd , Ext3dNow , O(000F0F,BB,_,_,_,_,_,_ ), 0 , 88 , 0 , 2402 , 148, 92 ), // #631
729 INST(Ptest , ExtRm , O(660F38,17,_,_,_,_,_,_ ), 0 , 2 , 0 , 9391 , 5 , 99 ), // #632
730 INST(Ptwrite , X86M , O(F30F00,AE,4,_,_,_,_,_ ), 0 , 92 , 0 , 2409 , 167, 100), // #633
731 INST(Punpckhbw , ExtRm_P , O(000F00,68,_,_,_,_,_,_ ), 0 , 4 , 0 , 9474 , 144, 82 ), // #634
732 INST(Punpckhdq , ExtRm_P , O(000F00,6A,_,_,_,_,_,_ ), 0 , 4 , 0 , 9485 , 144, 82 ), // #635
733 INST(Punpckhqdq , ExtRm , O(660F00,6D,_,_,_,_,_,_ ), 0 , 3 , 0 , 9496 , 5 , 4 ), // #636
734 INST(Punpckhwd , ExtRm_P , O(000F00,69,_,_,_,_,_,_ ), 0 , 4 , 0 , 9508 , 144, 82 ), // #637
735 INST(Punpcklbw , ExtRm_P , O(000F00,60,_,_,_,_,_,_ ), 0 , 4 , 0 , 9519 , 168, 82 ), // #638
736 INST(Punpckldq , ExtRm_P , O(000F00,62,_,_,_,_,_,_ ), 0 , 4 , 0 , 9530 , 168, 82 ), // #639
737 INST(Punpcklqdq , ExtRm , O(660F00,6C,_,_,_,_,_,_ ), 0 , 3 , 0 , 9541 , 5 , 4 ), // #640
738 INST(Punpcklwd , ExtRm_P , O(000F00,61,_,_,_,_,_,_ ), 0 , 4 , 0 , 9553 , 168, 82 ), // #641
739 INST(Push , X86Push , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 32 , 79 , 2417 , 169, 0 ), // #642
740 INST(Pusha , X86Op , O(660000,60,_,_,_,_,_,_ ), 0 , 19 , 0 , 2422 , 80 , 0 ), // #643
741 INST(Pushad , X86Op , O(000000,60,_,_,_,_,_,_ ), 0 , 0 , 0 , 2428 , 80 , 0 ), // #644
742 INST(Pushf , X86Op , O(660000,9C,_,_,_,_,_,_ ), 0 , 19 , 0 , 2435 , 30 , 101), // #645
743 INST(Pushfd , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2441 , 80 , 101), // #646
744 INST(Pushfq , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2448 , 33 , 101), // #647
745 INST(Pvalidate , X86Op , O(F20F01,FF,_,_,_,_,_,_ ), 0 , 93 , 0 , 2455 , 30 , 102), // #648
746 INST(Pxor , ExtRm_P , O(000F00,EF,_,_,_,_,_,_ ), 0 , 4 , 0 , 9564 , 147, 82 ), // #649
747 INST(Rcl , X86Rot , O(000000,D0,2,_,x,_,_,_ ), 0 , 1 , 0 , 2465 , 170, 103), // #650
748 INST(Rcpps , ExtRm , O(000F00,53,_,_,_,_,_,_ ), 0 , 4 , 0 , 9692 , 5 , 5 ), // #651
749 INST(Rcpss , ExtRm , O(F30F00,53,_,_,_,_,_,_ ), 0 , 6 , 0 , 9699 , 7 , 5 ), // #652
750 INST(Rcr , X86Rot , O(000000,D0,3,_,x,_,_,_ ), 0 , 76 , 0 , 2469 , 170, 103), // #653
751 INST(Rdfsbase , X86M , O(F30F00,AE,0,_,x,_,_,_ ), 0 , 6 , 0 , 2473 , 171, 104), // #654
752 INST(Rdgsbase , X86M , O(F30F00,AE,1,_,x,_,_,_ ), 0 , 94 , 0 , 2482 , 171, 104), // #655
753 INST(Rdmsr , X86Op , O(000F00,32,_,_,_,_,_,_ ), 0 , 4 , 0 , 2491 , 172, 105), // #656
754 INST(Rdpid , X86R_Native , O(F30F00,C7,7,_,_,_,_,_ ), 0 , 95 , 0 , 2497 , 173, 106), // #657
755 INST(Rdpkru , X86Op , O(000F01,EE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2503 , 172, 107), // #658
756 INST(Rdpmc , X86Op , O(000F00,33,_,_,_,_,_,_ ), 0 , 4 , 0 , 2510 , 172, 0 ), // #659
757 INST(Rdpru , X86Op , O(000F01,FD,_,_,_,_,_,_ ), 0 , 21 , 0 , 2516 , 172, 108), // #660
758 INST(Rdrand , X86M , O(000F00,C7,6,_,x,_,_,_ ), 0 , 81 , 0 , 2522 , 23 , 109), // #661
759 INST(Rdseed , X86M , O(000F00,C7,7,_,x,_,_,_ ), 0 , 22 , 0 , 2529 , 23 , 110), // #662
760 INST(Rdsspd , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 94 , 0 , 2536 , 75 , 56 ), // #663
761 INST(Rdsspq , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 94 , 0 , 2543 , 76 , 56 ), // #664
762 INST(Rdtsc , X86Op , O(000F00,31,_,_,_,_,_,_ ), 0 , 4 , 0 , 2550 , 28 , 111), // #665
763 INST(Rdtscp , X86Op , O(000F01,F9,_,_,_,_,_,_ ), 0 , 21 , 0 , 2556 , 172, 112), // #666
764 INST(Ret , X86Ret , O(000000,C2,_,_,_,_,_,_ ), 0 , 0 , 0 , 3072 , 174, 0 ), // #667
765 INST(Retf , X86Ret , O(000000,CA,_,_,x,_,_,_ ), 0 , 0 , 0 , 2563 , 175, 0 ), // #668
766 INST(Rmpadjust , X86Op , O(F30F01,FE,_,_,_,_,_,_ ), 0 , 25 , 0 , 2568 , 33 , 98 ), // #669
767 INST(Rmpupdate , X86Op , O(F20F01,FE,_,_,_,_,_,_ ), 0 , 93 , 0 , 2578 , 33 , 98 ), // #670
768 INST(Rol , X86Rot , O(000000,D0,0,_,x,_,_,_ ), 0 , 0 , 0 , 2588 , 170, 113), // #671
769 INST(Ror , X86Rot , O(000000,D0,1,_,x,_,_,_ ), 0 , 31 , 0 , 2592 , 170, 113), // #672
770 INST(Rorx , VexRmi_Wx , V(F20F3A,F0,_,0,x,_,_,_ ), 0 , 96 , 0 , 2596 , 176, 85 ), // #673
771 INST(Roundpd , ExtRmi , O(660F3A,09,_,_,_,_,_,_ ), 0 , 8 , 0 , 9794 , 8 , 12 ), // #674
772 INST(Roundps , ExtRmi , O(660F3A,08,_,_,_,_,_,_ ), 0 , 8 , 0 , 9803 , 8 , 12 ), // #675
773 INST(Roundsd , ExtRmi , O(660F3A,0B,_,_,_,_,_,_ ), 0 , 8 , 0 , 9812 , 37 , 12 ), // #676
774 INST(Roundss , ExtRmi , O(660F3A,0A,_,_,_,_,_,_ ), 0 , 8 , 0 , 9821 , 38 , 12 ), // #677
775 INST(Rsm , X86Op , O(000F00,AA,_,_,_,_,_,_ ), 0 , 4 , 0 , 2601 , 80 , 1 ), // #678
776 INST(Rsqrtps , ExtRm , O(000F00,52,_,_,_,_,_,_ ), 0 , 4 , 0 , 9918 , 5 , 5 ), // #679
777 INST(Rsqrtss , ExtRm , O(F30F00,52,_,_,_,_,_,_ ), 0 , 6 , 0 , 9927 , 7 , 5 ), // #680
778 INST(Rstorssp , X86M_Only , O(F30F00,01,5,_,_,_,_,_ ), 0 , 64 , 0 , 2605 , 32 , 24 ), // #681
779 INST(Sahf , X86Op , O(000000,9E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2614 , 95 , 114), // #682
780 INST(Sal , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2619 , 170, 1 ), // #683
781 INST(Sar , X86Rot , O(000000,D0,7,_,x,_,_,_ ), 0 , 27 , 0 , 2623 , 170, 1 ), // #684
782 INST(Sarx , VexRmv_Wx , V(F30F38,F7,_,0,x,_,_,_ ), 0 , 89 , 0 , 2627 , 13 , 85 ), // #685
783 INST(Saveprevssp , X86Op , O(F30F01,EA,_,_,_,_,_,_ ), 0 , 25 , 0 , 2632 , 30 , 24 ), // #686
784 INST(Sbb , X86Arith , O(000000,18,3,_,x,_,_,_ ), 0 , 76 , 0 , 2644 , 177, 2 ), // #687
785 INST(Scas , X86StrRm , O(000000,AE,_,_,_,_,_,_ ), 0 , 0 , 0 , 2648 , 178, 37 ), // #688
786 INST(Senduipi , X86M_NoSize , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 24 , 0 , 2653 , 76 , 25 ), // #689
787 INST(Serialize , X86Op , O(000F01,E8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2662 , 30 , 115), // #690
788 INST(Seta , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2672 , 179, 59 ), // #691
789 INST(Setae , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2677 , 179, 60 ), // #692
790 INST(Setb , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2683 , 179, 60 ), // #693
791 INST(Setbe , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2688 , 179, 59 ), // #694
792 INST(Setc , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2694 , 179, 60 ), // #695
793 INST(Sete , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2699 , 179, 61 ), // #696
794 INST(Setg , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2704 , 179, 62 ), // #697
795 INST(Setge , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2709 , 179, 63 ), // #698
796 INST(Setl , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2715 , 179, 63 ), // #699
797 INST(Setle , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2720 , 179, 62 ), // #700
798 INST(Setna , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2726 , 179, 59 ), // #701
799 INST(Setnae , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2732 , 179, 60 ), // #702
800 INST(Setnb , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2739 , 179, 60 ), // #703
801 INST(Setnbe , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2745 , 179, 59 ), // #704
802 INST(Setnc , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2752 , 179, 60 ), // #705
803 INST(Setne , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2758 , 179, 61 ), // #706
804 INST(Setng , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2764 , 179, 62 ), // #707
805 INST(Setnge , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2770 , 179, 63 ), // #708
806 INST(Setnl , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2777 , 179, 63 ), // #709
807 INST(Setnle , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2783 , 179, 62 ), // #710
808 INST(Setno , X86Set , O(000F00,91,_,_,_,_,_,_ ), 0 , 4 , 0 , 2790 , 179, 57 ), // #711
809 INST(Setnp , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2796 , 179, 64 ), // #712
810 INST(Setns , X86Set , O(000F00,99,_,_,_,_,_,_ ), 0 , 4 , 0 , 2802 , 179, 65 ), // #713
811 INST(Setnz , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2808 , 179, 61 ), // #714
812 INST(Seto , X86Set , O(000F00,90,_,_,_,_,_,_ ), 0 , 4 , 0 , 2814 , 179, 57 ), // #715
813 INST(Setp , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2819 , 179, 64 ), // #716
814 INST(Setpe , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2824 , 179, 64 ), // #717
815 INST(Setpo , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2830 , 179, 64 ), // #718
816 INST(Sets , X86Set , O(000F00,98,_,_,_,_,_,_ ), 0 , 4 , 0 , 2836 , 179, 65 ), // #719
817 INST(Setssbsy , X86Op , O(F30F01,E8,_,_,_,_,_,_ ), 0 , 25 , 0 , 2841 , 30 , 56 ), // #720
818 INST(Setz , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2850 , 179, 61 ), // #721
819 INST(Sfence , X86Fence , O(000F00,AE,7,_,_,_,_,_ ), 0 , 22 , 0 , 2855 , 30 , 77 ), // #722
820 INST(Sgdt , X86M_Only , O(000F00,01,0,_,_,_,_,_ ), 0 , 4 , 0 , 2862 , 31 , 0 ), // #723
821 INST(Sha1msg1 , ExtRm , O(000F38,C9,_,_,_,_,_,_ ), 0 , 84 , 0 , 2867 , 5 , 116), // #724
822 INST(Sha1msg2 , ExtRm , O(000F38,CA,_,_,_,_,_,_ ), 0 , 84 , 0 , 2876 , 5 , 116), // #725
823 INST(Sha1nexte , ExtRm , O(000F38,C8,_,_,_,_,_,_ ), 0 , 84 , 0 , 2885 , 5 , 116), // #726
824 INST(Sha1rnds4 , ExtRmi , O(000F3A,CC,_,_,_,_,_,_ ), 0 , 86 , 0 , 2895 , 8 , 116), // #727
825 INST(Sha256msg1 , ExtRm , O(000F38,CC,_,_,_,_,_,_ ), 0 , 84 , 0 , 2905 , 5 , 116), // #728
826 INST(Sha256msg2 , ExtRm , O(000F38,CD,_,_,_,_,_,_ ), 0 , 84 , 0 , 2916 , 5 , 116), // #729
827 INST(Sha256rnds2 , ExtRm_XMM0 , O(000F38,CB,_,_,_,_,_,_ ), 0 , 84 , 0 , 2927 , 15 , 116), // #730
828 INST(Shl , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2939 , 170, 1 ), // #731
829 INST(Shld , X86ShldShrd , O(000F00,A4,_,_,x,_,_,_ ), 0 , 4 , 0 , 8963 , 180, 1 ), // #732
830 INST(Shlx , VexRmv_Wx , V(660F38,F7,_,0,x,_,_,_ ), 0 , 97 , 0 , 2943 , 13 , 85 ), // #733
831 INST(Shr , X86Rot , O(000000,D0,5,_,x,_,_,_ ), 0 , 63 , 0 , 2948 , 170, 1 ), // #734
832 INST(Shrd , X86ShldShrd , O(000F00,AC,_,_,x,_,_,_ ), 0 , 4 , 0 , 2952 , 180, 1 ), // #735
833 INST(Shrx , VexRmv_Wx , V(F20F38,F7,_,0,x,_,_,_ ), 0 , 85 , 0 , 2957 , 13 , 85 ), // #736
834 INST(Shufpd , ExtRmi , O(660F00,C6,_,_,_,_,_,_ ), 0 , 3 , 0 , 10188, 8 , 4 ), // #737
835 INST(Shufps , ExtRmi , O(000F00,C6,_,_,_,_,_,_ ), 0 , 4 , 0 , 10196, 8 , 5 ), // #738
836 INST(Sidt , X86M_Only , O(000F00,01,1,_,_,_,_,_ ), 0 , 29 , 0 , 2962 , 31 , 0 ), // #739
837 INST(Skinit , X86Op_xAX , O(000F01,DE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2967 , 52 , 117), // #740
838 INST(Sldt , X86M_NoMemSize , O(000F00,00,0,_,_,_,_,_ ), 0 , 4 , 0 , 2974 , 181, 0 ), // #741
839 INST(Slwpcb , VexR_Wx , V(XOP_M9,12,1,0,x,_,_,_ ), 0 , 11 , 0 , 2979 , 106, 74 ), // #742
840 INST(Smsw , X86M_NoMemSize , O(000F00,01,4,_,_,_,_,_ ), 0 , 98 , 0 , 2986 , 181, 0 ), // #743
841 INST(Sqrtpd , ExtRm , O(660F00,51,_,_,_,_,_,_ ), 0 , 3 , 0 , 10204, 5 , 4 ), // #744
842 INST(Sqrtps , ExtRm , O(000F00,51,_,_,_,_,_,_ ), 0 , 4 , 0 , 9919 , 5 , 5 ), // #745
843 INST(Sqrtsd , ExtRm , O(F20F00,51,_,_,_,_,_,_ ), 0 , 5 , 0 , 10220, 6 , 4 ), // #746
844 INST(Sqrtss , ExtRm , O(F30F00,51,_,_,_,_,_,_ ), 0 , 6 , 0 , 9928 , 7 , 5 ), // #747
845 INST(Stac , X86Op , O(000F01,CB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2991 , 30 , 16 ), // #748
846 INST(Stc , X86Op , O(000000,F9,_,_,_,_,_,_ ), 0 , 0 , 0 , 2996 , 30 , 17 ), // #749
847 INST(Std , X86Op , O(000000,FD,_,_,_,_,_,_ ), 0 , 0 , 0 , 6946 , 30 , 18 ), // #750
848 INST(Stgi , X86Op , O(000F01,DC,_,_,_,_,_,_ ), 0 , 21 , 0 , 3000 , 30 , 117), // #751
849 INST(Sti , X86Op , O(000000,FB,_,_,_,_,_,_ ), 0 , 0 , 0 , 3005 , 30 , 23 ), // #752
850 INST(Stmxcsr , X86M_Only , O(000F00,AE,3,_,_,_,_,_ ), 0 , 79 , 0 , 10236, 99 , 5 ), // #753
851 INST(Stos , X86StrMr , O(000000,AA,_,_,_,_,_,_ ), 0 , 0 , 0 , 3009 , 182, 75 ), // #754
852 INST(Str , X86M_NoMemSize , O(000F00,00,1,_,_,_,_,_ ), 0 , 29 , 0 , 3014 , 181, 0 ), // #755
853 INST(Sttilecfg , AmxCfg , V(660F38,49,_,0,0,_,_,_ ), 0 , 97 , 0 , 3018 , 101, 73 ), // #756
854 INST(Stui , X86Op , O(F30F01,EF,_,_,_,_,_,_ ), 0 , 25 , 0 , 3135 , 33 , 25 ), // #757
855 INST(Sub , X86Arith , O(000000,28,5,_,x,_,_,_ ), 0 , 63 , 0 , 866 , 177, 1 ), // #758
856 INST(Subpd , ExtRm , O(660F00,5C,_,_,_,_,_,_ ), 0 , 3 , 0 , 4848 , 5 , 4 ), // #759
857 INST(Subps , ExtRm , O(000F00,5C,_,_,_,_,_,_ ), 0 , 4 , 0 , 4860 , 5 , 5 ), // #760
858 INST(Subsd , ExtRm , O(F20F00,5C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5536 , 6 , 4 ), // #761
859 INST(Subss , ExtRm , O(F30F00,5C,_,_,_,_,_,_ ), 0 , 6 , 0 , 5546 , 7 , 5 ), // #762
860 INST(Swapgs , X86Op , O(000F01,F8,_,_,_,_,_,_ ), 0 , 21 , 0 , 3028 , 33 , 0 ), // #763
861 INST(Syscall , X86Op , O(000F00,05,_,_,_,_,_,_ ), 0 , 4 , 0 , 3035 , 33 , 0 ), // #764
862 INST(Sysenter , X86Op , O(000F00,34,_,_,_,_,_,_ ), 0 , 4 , 0 , 3043 , 30 , 0 ), // #765
863 INST(Sysexit , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 3052 , 30 , 0 ), // #766
864 INST(Sysexitq , X86Op , O(000F00,35,_,_,1,_,_,_ ), 0 , 61 , 0 , 3060 , 30 , 0 ), // #767
865 INST(Sysret , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 3069 , 33 , 0 ), // #768
866 INST(Sysretq , X86Op , O(000F00,07,_,_,1,_,_,_ ), 0 , 61 , 0 , 3076 , 33 , 0 ), // #769
867 INST(T1mskc , VexVm_Wx , V(XOP_M9,01,7,0,x,_,_,_ ), 0 , 99 , 0 , 3084 , 14 , 11 ), // #770
868 INST(Tdpbf16ps , AmxRmv , V(F30F38,5C,_,0,0,_,_,_ ), 0 , 89 , 0 , 3091 , 183, 118), // #771
869 INST(Tdpbssd , AmxRmv , V(F20F38,5E,_,0,0,_,_,_ ), 0 , 85 , 0 , 3101 , 183, 119), // #772
870 INST(Tdpbsud , AmxRmv , V(F30F38,5E,_,0,0,_,_,_ ), 0 , 89 , 0 , 3109 , 183, 119), // #773
871 INST(Tdpbusd , AmxRmv , V(660F38,5E,_,0,0,_,_,_ ), 0 , 97 , 0 , 3117 , 183, 119), // #774
872 INST(Tdpbuud , AmxRmv , V(000F38,5E,_,0,0,_,_,_ ), 0 , 10 , 0 , 3125 , 183, 119), // #775
873 INST(Test , X86Test , O(000000,84,_,_,x,_,_,_ ), O(000000,F6,_,_,x,_,_,_ ), 0 , 80 , 9392 , 184, 1 ), // #776
874 INST(Testui , X86Op , O(F30F01,ED,_,_,_,_,_,_ ), 0 , 25 , 0 , 3133 , 33 , 120), // #777
875 INST(Tileloadd , AmxRm , V(F20F38,4B,_,0,0,_,_,_ ), 0 , 85 , 0 , 3140 , 185, 73 ), // #778
876 INST(Tileloaddt1 , AmxRm , V(660F38,4B,_,0,0,_,_,_ ), 0 , 97 , 0 , 3150 , 185, 73 ), // #779
877 INST(Tilerelease , VexOpMod , V(000F38,49,0,0,0,_,_,_ ), 0 , 10 , 0 , 3162 , 186, 73 ), // #780
878 INST(Tilestored , AmxMr , V(F30F38,4B,_,0,0,_,_,_ ), 0 , 89 , 0 , 3174 , 187, 73 ), // #781
879 INST(Tilezero , AmxR , V(F20F38,49,_,0,0,_,_,_ ), 0 , 85 , 0 , 3185 , 188, 73 ), // #782
880 INST(Tpause , X86R32_EDX_EAX , O(660F00,AE,6,_,_,_,_,_ ), 0 , 26 , 0 , 3194 , 189, 121), // #783
881 INST(Tzcnt , X86Rm_Raw66H , O(F30F00,BC,_,_,x,_,_,_ ), 0 , 6 , 0 , 3201 , 22 , 9 ), // #784
882 INST(Tzmsk , VexVm_Wx , V(XOP_M9,01,4,0,x,_,_,_ ), 0 , 100, 0 , 3207 , 14 , 11 ), // #785
883 INST(Ucomisd , ExtRm , O(660F00,2E,_,_,_,_,_,_ ), 0 , 3 , 0 , 10289, 6 , 41 ), // #786
884 INST(Ucomiss , ExtRm , O(000F00,2E,_,_,_,_,_,_ ), 0 , 4 , 0 , 10298, 7 , 42 ), // #787
885 INST(Ud0 , X86Rm , O(000F00,FF,_,_,_,_,_,_ ), 0 , 4 , 0 , 3213 , 190, 0 ), // #788
886 INST(Ud1 , X86Rm , O(000F00,B9,_,_,_,_,_,_ ), 0 , 4 , 0 , 3217 , 190, 0 ), // #789
887 INST(Ud2 , X86Op , O(000F00,0B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3221 , 30 , 0 ), // #790
888 INST(Uiret , X86Op , O(F30F01,EC,_,_,_,_,_,_ ), 0 , 25 , 0 , 3225 , 33 , 25 ), // #791
889 INST(Umonitor , X86R_FromM , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 24 , 0 , 3231 , 191, 122), // #792
890 INST(Umwait , X86R32_EDX_EAX , O(F20F00,AE,6,_,_,_,_,_ ), 0 , 101, 0 , 3240 , 189, 121), // #793
891 INST(Unpckhpd , ExtRm , O(660F00,15,_,_,_,_,_,_ ), 0 , 3 , 0 , 10307, 5 , 4 ), // #794
892 INST(Unpckhps , ExtRm , O(000F00,15,_,_,_,_,_,_ ), 0 , 4 , 0 , 10317, 5 , 5 ), // #795
893 INST(Unpcklpd , ExtRm , O(660F00,14,_,_,_,_,_,_ ), 0 , 3 , 0 , 10327, 5 , 4 ), // #796
894 INST(Unpcklps , ExtRm , O(000F00,14,_,_,_,_,_,_ ), 0 , 4 , 0 , 10337, 5 , 5 ), // #797
895 INST(V4fmaddps , VexRm_T1_4X , E(F20F38,9A,_,2,_,0,4,T4X), 0 , 102, 0 , 3247 , 192, 123), // #798
896 INST(V4fmaddss , VexRm_T1_4X , E(F20F38,9B,_,0,_,0,4,T4X), 0 , 103, 0 , 3257 , 193, 123), // #799
897 INST(V4fnmaddps , VexRm_T1_4X , E(F20F38,AA,_,2,_,0,4,T4X), 0 , 102, 0 , 3267 , 192, 123), // #800
898 INST(V4fnmaddss , VexRm_T1_4X , E(F20F38,AB,_,0,_,0,4,T4X), 0 , 103, 0 , 3278 , 193, 123), // #801
899 INST(Vaddpd , VexRvm_Lx , V(660F00,58,_,x,I,1,4,FV ), 0 , 104, 0 , 3289 , 194, 124), // #802
900 INST(Vaddps , VexRvm_Lx , V(000F00,58,_,x,I,0,4,FV ), 0 , 105, 0 , 3296 , 195, 124), // #803
901 INST(Vaddsd , VexRvm , V(F20F00,58,_,I,I,1,3,T1S), 0 , 106, 0 , 3303 , 196, 125), // #804
902 INST(Vaddss , VexRvm , V(F30F00,58,_,I,I,0,2,T1S), 0 , 107, 0 , 3310 , 197, 125), // #805
903 INST(Vaddsubpd , VexRvm_Lx , V(660F00,D0,_,x,I,_,_,_ ), 0 , 70 , 0 , 3317 , 198, 126), // #806
904 INST(Vaddsubps , VexRvm_Lx , V(F20F00,D0,_,x,I,_,_,_ ), 0 , 108, 0 , 3327 , 198, 126), // #807
905 INST(Vaesdec , VexRvm_Lx , V(660F38,DE,_,x,I,_,4,FVM), 0 , 109, 0 , 3337 , 199, 127), // #808
906 INST(Vaesdeclast , VexRvm_Lx , V(660F38,DF,_,x,I,_,4,FVM), 0 , 109, 0 , 3345 , 199, 127), // #809
907 INST(Vaesenc , VexRvm_Lx , V(660F38,DC,_,x,I,_,4,FVM), 0 , 109, 0 , 3357 , 199, 127), // #810
908 INST(Vaesenclast , VexRvm_Lx , V(660F38,DD,_,x,I,_,4,FVM), 0 , 109, 0 , 3365 , 199, 127), // #811
909 INST(Vaesimc , VexRm , V(660F38,DB,_,0,I,_,_,_ ), 0 , 97 , 0 , 3377 , 200, 128), // #812
910 INST(Vaeskeygenassist , VexRmi , V(660F3A,DF,_,0,I,_,_,_ ), 0 , 74 , 0 , 3385 , 201, 128), // #813
911 INST(Valignd , VexRvmi_Lx , E(660F3A,03,_,x,_,0,4,FV ), 0 , 110, 0 , 3402 , 202, 129), // #814
912 INST(Valignq , VexRvmi_Lx , E(660F3A,03,_,x,_,1,4,FV ), 0 , 111, 0 , 3410 , 203, 129), // #815
913 INST(Vandnpd , VexRvm_Lx , V(660F00,55,_,x,I,1,4,FV ), 0 , 104, 0 , 3418 , 204, 130), // #816
914 INST(Vandnps , VexRvm_Lx , V(000F00,55,_,x,I,0,4,FV ), 0 , 105, 0 , 3426 , 205, 130), // #817
915 INST(Vandpd , VexRvm_Lx , V(660F00,54,_,x,I,1,4,FV ), 0 , 104, 0 , 3434 , 206, 130), // #818
916 INST(Vandps , VexRvm_Lx , V(000F00,54,_,x,I,0,4,FV ), 0 , 105, 0 , 3441 , 207, 130), // #819
917 INST(Vblendmpd , VexRvm_Lx , E(660F38,65,_,x,_,1,4,FV ), 0 , 112, 0 , 3448 , 208, 129), // #820
918 INST(Vblendmps , VexRvm_Lx , E(660F38,65,_,x,_,0,4,FV ), 0 , 113, 0 , 3458 , 209, 129), // #821
919 INST(Vblendpd , VexRvmi_Lx , V(660F3A,0D,_,x,I,_,_,_ ), 0 , 74 , 0 , 3468 , 210, 126), // #822
920 INST(Vblendps , VexRvmi_Lx , V(660F3A,0C,_,x,I,_,_,_ ), 0 , 74 , 0 , 3477 , 210, 126), // #823
921 INST(Vblendvpd , VexRvmr_Lx , V(660F3A,4B,_,x,0,_,_,_ ), 0 , 74 , 0 , 3486 , 211, 126), // #824
922 INST(Vblendvps , VexRvmr_Lx , V(660F3A,4A,_,x,0,_,_,_ ), 0 , 74 , 0 , 3496 , 211, 126), // #825
923 INST(Vbroadcastf128 , VexRm , V(660F38,1A,_,1,0,_,_,_ ), 0 , 114, 0 , 3506 , 212, 126), // #826
924 INST(Vbroadcastf32x2 , VexRm_Lx , E(660F38,19,_,x,_,0,3,T2 ), 0 , 115, 0 , 3521 , 213, 131), // #827
925 INST(Vbroadcastf32x4 , VexRm_Lx , E(660F38,1A,_,x,_,0,4,T4 ), 0 , 116, 0 , 3537 , 214, 68 ), // #828
926 INST(Vbroadcastf32x8 , VexRm , E(660F38,1B,_,2,_,0,5,T8 ), 0 , 117, 0 , 3553 , 215, 66 ), // #829
927 INST(Vbroadcastf64x2 , VexRm_Lx , E(660F38,1A,_,x,_,1,4,T2 ), 0 , 118, 0 , 3569 , 214, 131), // #830
928 INST(Vbroadcastf64x4 , VexRm , E(660F38,1B,_,2,_,1,5,T4 ), 0 , 119, 0 , 3585 , 215, 68 ), // #831
929 INST(Vbroadcasti128 , VexRm , V(660F38,5A,_,1,0,_,_,_ ), 0 , 114, 0 , 3601 , 212, 132), // #832
930 INST(Vbroadcasti32x2 , VexRm_Lx , E(660F38,59,_,x,_,0,3,T2 ), 0 , 115, 0 , 3616 , 216, 131), // #833
931 INST(Vbroadcasti32x4 , VexRm_Lx , E(660F38,5A,_,x,_,0,4,T4 ), 0 , 116, 0 , 3632 , 214, 129), // #834
932 INST(Vbroadcasti32x8 , VexRm , E(660F38,5B,_,2,_,0,5,T8 ), 0 , 117, 0 , 3648 , 215, 66 ), // #835
933 INST(Vbroadcasti64x2 , VexRm_Lx , E(660F38,5A,_,x,_,1,4,T2 ), 0 , 118, 0 , 3664 , 214, 131), // #836
934 INST(Vbroadcasti64x4 , VexRm , E(660F38,5B,_,2,_,1,5,T4 ), 0 , 119, 0 , 3680 , 215, 68 ), // #837
935 INST(Vbroadcastsd , VexRm_Lx , V(660F38,19,_,x,0,1,3,T1S), 0 , 120, 0 , 3696 , 217, 133), // #838
936 INST(Vbroadcastss , VexRm_Lx , V(660F38,18,_,x,0,0,2,T1S), 0 , 121, 0 , 3709 , 218, 133), // #839
937 INST(Vcmppd , VexRvmi_Lx_KEvex , V(660F00,C2,_,x,I,1,4,FV ), 0 , 104, 0 , 3722 , 219, 124), // #840
938 INST(Vcmpps , VexRvmi_Lx_KEvex , V(000F00,C2,_,x,I,0,4,FV ), 0 , 105, 0 , 3729 , 220, 124), // #841
939 INST(Vcmpsd , VexRvmi_KEvex , V(F20F00,C2,_,I,I,1,3,T1S), 0 , 106, 0 , 3736 , 221, 125), // #842
940 INST(Vcmpss , VexRvmi_KEvex , V(F30F00,C2,_,I,I,0,2,T1S), 0 , 107, 0 , 3743 , 222, 125), // #843
941 INST(Vcomisd , VexRm , V(660F00,2F,_,I,I,1,3,T1S), 0 , 122, 0 , 3750 , 223, 134), // #844
942 INST(Vcomiss , VexRm , V(000F00,2F,_,I,I,0,2,T1S), 0 , 123, 0 , 3758 , 224, 134), // #845
943 INST(Vcompresspd , VexMr_Lx , E(660F38,8A,_,x,_,1,3,T1S), 0 , 124, 0 , 3766 , 225, 129), // #846
944 INST(Vcompressps , VexMr_Lx , E(660F38,8A,_,x,_,0,2,T1S), 0 , 125, 0 , 3778 , 225, 129), // #847
945 INST(Vcvtdq2pd , VexRm_Lx , V(F30F00,E6,_,x,I,0,3,HV ), 0 , 126, 0 , 3790 , 226, 124), // #848
946 INST(Vcvtdq2ps , VexRm_Lx , V(000F00,5B,_,x,I,0,4,FV ), 0 , 105, 0 , 3800 , 227, 124), // #849
947 INST(Vcvtne2ps2bf16 , VexRvm_Lx , E(F20F38,72,_,_,_,0,4,FV ), 0 , 127, 0 , 3810 , 209, 135), // #850
948 INST(Vcvtneps2bf16 , VexRm_Lx_Narrow , E(F30F38,72,_,_,_,0,4,FV ), 0 , 128, 0 , 3825 , 228, 135), // #851
949 INST(Vcvtpd2dq , VexRm_Lx_Narrow , V(F20F00,E6,_,x,I,1,4,FV ), 0 , 129, 0 , 3839 , 229, 124), // #852
950 INST(Vcvtpd2ps , VexRm_Lx_Narrow , V(660F00,5A,_,x,I,1,4,FV ), 0 , 104, 0 , 3849 , 229, 124), // #853
951 INST(Vcvtpd2qq , VexRm_Lx , E(660F00,7B,_,x,_,1,4,FV ), 0 , 130, 0 , 3859 , 230, 131), // #854
952 INST(Vcvtpd2udq , VexRm_Lx_Narrow , E(000F00,79,_,x,_,1,4,FV ), 0 , 131, 0 , 3869 , 231, 129), // #855
953 INST(Vcvtpd2uqq , VexRm_Lx , E(660F00,79,_,x,_,1,4,FV ), 0 , 130, 0 , 3880 , 230, 131), // #856
954 INST(Vcvtph2ps , VexRm_Lx , V(660F38,13,_,x,0,0,3,HVM), 0 , 132, 0 , 3891 , 232, 136), // #857
955 INST(Vcvtps2dq , VexRm_Lx , V(660F00,5B,_,x,I,0,4,FV ), 0 , 133, 0 , 3901 , 227, 124), // #858
956 INST(Vcvtps2pd , VexRm_Lx , V(000F00,5A,_,x,I,0,3,HV ), 0 , 134, 0 , 3911 , 233, 124), // #859
957 INST(Vcvtps2ph , VexMri_Lx , V(660F3A,1D,_,x,0,0,3,HVM), 0 , 135, 0 , 3921 , 234, 136), // #860
958 INST(Vcvtps2qq , VexRm_Lx , E(660F00,7B,_,x,_,0,3,HV ), 0 , 136, 0 , 3931 , 235, 131), // #861
959 INST(Vcvtps2udq , VexRm_Lx , E(000F00,79,_,x,_,0,4,FV ), 0 , 137, 0 , 3941 , 236, 129), // #862
960 INST(Vcvtps2uqq , VexRm_Lx , E(660F00,79,_,x,_,0,3,HV ), 0 , 136, 0 , 3952 , 235, 131), // #863
961 INST(Vcvtqq2pd , VexRm_Lx , E(F30F00,E6,_,x,_,1,4,FV ), 0 , 138, 0 , 3963 , 230, 131), // #864
962 INST(Vcvtqq2ps , VexRm_Lx_Narrow , E(000F00,5B,_,x,_,1,4,FV ), 0 , 131, 0 , 3973 , 231, 131), // #865
963 INST(Vcvtsd2si , VexRm_Wx , V(F20F00,2D,_,I,x,x,3,T1F), 0 , 139, 0 , 3983 , 237, 125), // #866
964 INST(Vcvtsd2ss , VexRvm , V(F20F00,5A,_,I,I,1,3,T1S), 0 , 106, 0 , 3993 , 196, 125), // #867
965 INST(Vcvtsd2usi , VexRm_Wx , E(F20F00,79,_,I,_,x,3,T1F), 0 , 140, 0 , 4003 , 238, 68 ), // #868
966 INST(Vcvtsi2sd , VexRvm_Wx , V(F20F00,2A,_,I,x,x,2,T1W), 0 , 141, 0 , 4014 , 239, 125), // #869
967 INST(Vcvtsi2ss , VexRvm_Wx , V(F30F00,2A,_,I,x,x,2,T1W), 0 , 142, 0 , 4024 , 239, 125), // #870
968 INST(Vcvtss2sd , VexRvm , V(F30F00,5A,_,I,I,0,2,T1S), 0 , 107, 0 , 4034 , 240, 125), // #871
969 INST(Vcvtss2si , VexRm_Wx , V(F30F00,2D,_,I,x,x,2,T1F), 0 , 143, 0 , 4044 , 241, 125), // #872
970 INST(Vcvtss2usi , VexRm_Wx , E(F30F00,79,_,I,_,x,2,T1F), 0 , 144, 0 , 4054 , 242, 68 ), // #873
971 INST(Vcvttpd2dq , VexRm_Lx_Narrow , V(660F00,E6,_,x,I,1,4,FV ), 0 , 104, 0 , 4065 , 243, 124), // #874
972 INST(Vcvttpd2qq , VexRm_Lx , E(660F00,7A,_,x,_,1,4,FV ), 0 , 130, 0 , 4076 , 244, 129), // #875
973 INST(Vcvttpd2udq , VexRm_Lx_Narrow , E(000F00,78,_,x,_,1,4,FV ), 0 , 131, 0 , 4087 , 245, 129), // #876
974 INST(Vcvttpd2uqq , VexRm_Lx , E(660F00,78,_,x,_,1,4,FV ), 0 , 130, 0 , 4099 , 244, 131), // #877
975 INST(Vcvttps2dq , VexRm_Lx , V(F30F00,5B,_,x,I,0,4,FV ), 0 , 145, 0 , 4111 , 246, 124), // #878
976 INST(Vcvttps2qq , VexRm_Lx , E(660F00,7A,_,x,_,0,3,HV ), 0 , 136, 0 , 4122 , 247, 131), // #879
977 INST(Vcvttps2udq , VexRm_Lx , E(000F00,78,_,x,_,0,4,FV ), 0 , 137, 0 , 4133 , 248, 129), // #880
978 INST(Vcvttps2uqq , VexRm_Lx , E(660F00,78,_,x,_,0,3,HV ), 0 , 136, 0 , 4145 , 247, 131), // #881
979 INST(Vcvttsd2si , VexRm_Wx , V(F20F00,2C,_,I,x,x,3,T1F), 0 , 139, 0 , 4157 , 249, 125), // #882
980 INST(Vcvttsd2usi , VexRm_Wx , E(F20F00,78,_,I,_,x,3,T1F), 0 , 140, 0 , 4168 , 250, 68 ), // #883
981 INST(Vcvttss2si , VexRm_Wx , V(F30F00,2C,_,I,x,x,2,T1F), 0 , 143, 0 , 4180 , 251, 125), // #884
982 INST(Vcvttss2usi , VexRm_Wx , E(F30F00,78,_,I,_,x,2,T1F), 0 , 144, 0 , 4191 , 252, 68 ), // #885
983 INST(Vcvtudq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,0,3,HV ), 0 , 146, 0 , 4203 , 253, 129), // #886
984 INST(Vcvtudq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,0,4,FV ), 0 , 147, 0 , 4214 , 236, 129), // #887
985 INST(Vcvtuqq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,1,4,FV ), 0 , 138, 0 , 4225 , 230, 131), // #888
986 INST(Vcvtuqq2ps , VexRm_Lx_Narrow , E(F20F00,7A,_,x,_,1,4,FV ), 0 , 148, 0 , 4236 , 231, 131), // #889
987 INST(Vcvtusi2sd , VexRvm_Wx , E(F20F00,7B,_,I,_,x,2,T1W), 0 , 149, 0 , 4247 , 254, 68 ), // #890
988 INST(Vcvtusi2ss , VexRvm_Wx , E(F30F00,7B,_,I,_,x,2,T1W), 0 , 150, 0 , 4258 , 254, 68 ), // #891
989 INST(Vdbpsadbw , VexRvmi_Lx , E(660F3A,42,_,x,_,0,4,FVM), 0 , 151, 0 , 4269 , 255, 137), // #892
990 INST(Vdivpd , VexRvm_Lx , V(660F00,5E,_,x,I,1,4,FV ), 0 , 104, 0 , 4279 , 194, 124), // #893
991 INST(Vdivps , VexRvm_Lx , V(000F00,5E,_,x,I,0,4,FV ), 0 , 105, 0 , 4286 , 195, 124), // #894
992 INST(Vdivsd , VexRvm , V(F20F00,5E,_,I,I,1,3,T1S), 0 , 106, 0 , 4293 , 196, 125), // #895
993 INST(Vdivss , VexRvm , V(F30F00,5E,_,I,I,0,2,T1S), 0 , 107, 0 , 4300 , 197, 125), // #896
994 INST(Vdpbf16ps , VexRvm_Lx , E(F30F38,52,_,_,_,0,4,FV ), 0 , 128, 0 , 4307 , 209, 135), // #897
995 INST(Vdppd , VexRvmi_Lx , V(660F3A,41,_,x,I,_,_,_ ), 0 , 74 , 0 , 4317 , 256, 126), // #898
996 INST(Vdpps , VexRvmi_Lx , V(660F3A,40,_,x,I,_,_,_ ), 0 , 74 , 0 , 4323 , 210, 126), // #899
997 INST(Verr , X86M_NoSize , O(000F00,00,4,_,_,_,_,_ ), 0 , 98 , 0 , 4329 , 105, 10 ), // #900
998 INST(Verw , X86M_NoSize , O(000F00,00,5,_,_,_,_,_ ), 0 , 78 , 0 , 4334 , 105, 10 ), // #901
999 INST(Vexp2pd , VexRm , E(660F38,C8,_,2,_,1,4,FV ), 0 , 152, 0 , 4339 , 257, 138), // #902
1000 INST(Vexp2ps , VexRm , E(660F38,C8,_,2,_,0,4,FV ), 0 , 153, 0 , 4347 , 258, 138), // #903
1001 INST(Vexpandpd , VexRm_Lx , E(660F38,88,_,x,_,1,3,T1S), 0 , 124, 0 , 4355 , 259, 129), // #904
1002 INST(Vexpandps , VexRm_Lx , E(660F38,88,_,x,_,0,2,T1S), 0 , 125, 0 , 4365 , 259, 129), // #905
1003 INST(Vextractf128 , VexMri , V(660F3A,19,_,1,0,_,_,_ ), 0 , 154, 0 , 4375 , 260, 126), // #906
1004 INST(Vextractf32x4 , VexMri_Lx , E(660F3A,19,_,x,_,0,4,T4 ), 0 , 155, 0 , 4388 , 261, 129), // #907
1005 INST(Vextractf32x8 , VexMri , E(660F3A,1B,_,2,_,0,5,T8 ), 0 , 156, 0 , 4402 , 262, 66 ), // #908
1006 INST(Vextractf64x2 , VexMri_Lx , E(660F3A,19,_,x,_,1,4,T2 ), 0 , 157, 0 , 4416 , 261, 131), // #909
1007 INST(Vextractf64x4 , VexMri , E(660F3A,1B,_,2,_,1,5,T4 ), 0 , 158, 0 , 4430 , 262, 68 ), // #910
1008 INST(Vextracti128 , VexMri , V(660F3A,39,_,1,0,_,_,_ ), 0 , 154, 0 , 4444 , 260, 132), // #911
1009 INST(Vextracti32x4 , VexMri_Lx , E(660F3A,39,_,x,_,0,4,T4 ), 0 , 155, 0 , 4457 , 261, 129), // #912
1010 INST(Vextracti32x8 , VexMri , E(660F3A,3B,_,2,_,0,5,T8 ), 0 , 156, 0 , 4471 , 262, 66 ), // #913
1011 INST(Vextracti64x2 , VexMri_Lx , E(660F3A,39,_,x,_,1,4,T2 ), 0 , 157, 0 , 4485 , 261, 131), // #914
1012 INST(Vextracti64x4 , VexMri , E(660F3A,3B,_,2,_,1,5,T4 ), 0 , 158, 0 , 4499 , 262, 68 ), // #915
1013 INST(Vextractps , VexMri , V(660F3A,17,_,0,I,I,2,T1S), 0 , 159, 0 , 4513 , 263, 125), // #916
1014 INST(Vfixupimmpd , VexRvmi_Lx , E(660F3A,54,_,x,_,1,4,FV ), 0 , 111, 0 , 4524 , 264, 129), // #917
1015 INST(Vfixupimmps , VexRvmi_Lx , E(660F3A,54,_,x,_,0,4,FV ), 0 , 110, 0 , 4536 , 265, 129), // #918
1016 INST(Vfixupimmsd , VexRvmi , E(660F3A,55,_,I,_,1,3,T1S), 0 , 160, 0 , 4548 , 266, 68 ), // #919
1017 INST(Vfixupimmss , VexRvmi , E(660F3A,55,_,I,_,0,2,T1S), 0 , 161, 0 , 4560 , 267, 68 ), // #920
1018 INST(Vfmadd132pd , VexRvm_Lx , V(660F38,98,_,x,1,1,4,FV ), 0 , 162, 0 , 4572 , 194, 139), // #921
1019 INST(Vfmadd132ps , VexRvm_Lx , V(660F38,98,_,x,0,0,4,FV ), 0 , 163, 0 , 4584 , 195, 139), // #922
1020 INST(Vfmadd132sd , VexRvm , V(660F38,99,_,I,1,1,3,T1S), 0 , 164, 0 , 4596 , 196, 140), // #923
1021 INST(Vfmadd132ss , VexRvm , V(660F38,99,_,I,0,0,2,T1S), 0 , 121, 0 , 4608 , 197, 140), // #924
1022 INST(Vfmadd213pd , VexRvm_Lx , V(660F38,A8,_,x,1,1,4,FV ), 0 , 162, 0 , 4620 , 194, 139), // #925
1023 INST(Vfmadd213ps , VexRvm_Lx , V(660F38,A8,_,x,0,0,4,FV ), 0 , 163, 0 , 4632 , 195, 139), // #926
1024 INST(Vfmadd213sd , VexRvm , V(660F38,A9,_,I,1,1,3,T1S), 0 , 164, 0 , 4644 , 196, 140), // #927
1025 INST(Vfmadd213ss , VexRvm , V(660F38,A9,_,I,0,0,2,T1S), 0 , 121, 0 , 4656 , 197, 140), // #928
1026 INST(Vfmadd231pd , VexRvm_Lx , V(660F38,B8,_,x,1,1,4,FV ), 0 , 162, 0 , 4668 , 194, 139), // #929
1027 INST(Vfmadd231ps , VexRvm_Lx , V(660F38,B8,_,x,0,0,4,FV ), 0 , 163, 0 , 4680 , 195, 139), // #930
1028 INST(Vfmadd231sd , VexRvm , V(660F38,B9,_,I,1,1,3,T1S), 0 , 164, 0 , 4692 , 196, 140), // #931
1029 INST(Vfmadd231ss , VexRvm , V(660F38,B9,_,I,0,0,2,T1S), 0 , 121, 0 , 4704 , 197, 140), // #932
1030 INST(Vfmaddpd , Fma4_Lx , V(660F3A,69,_,x,x,_,_,_ ), 0 , 74 , 0 , 4716 , 268, 141), // #933
1031 INST(Vfmaddps , Fma4_Lx , V(660F3A,68,_,x,x,_,_,_ ), 0 , 74 , 0 , 4725 , 268, 141), // #934
1032 INST(Vfmaddsd , Fma4 , V(660F3A,6B,_,0,x,_,_,_ ), 0 , 74 , 0 , 4734 , 269, 141), // #935
1033 INST(Vfmaddss , Fma4 , V(660F3A,6A,_,0,x,_,_,_ ), 0 , 74 , 0 , 4743 , 270, 141), // #936
1034 INST(Vfmaddsub132pd , VexRvm_Lx , V(660F38,96,_,x,1,1,4,FV ), 0 , 162, 0 , 4752 , 194, 139), // #937
1035 INST(Vfmaddsub132ps , VexRvm_Lx , V(660F38,96,_,x,0,0,4,FV ), 0 , 163, 0 , 4767 , 195, 139), // #938
1036 INST(Vfmaddsub213pd , VexRvm_Lx , V(660F38,A6,_,x,1,1,4,FV ), 0 , 162, 0 , 4782 , 194, 139), // #939
1037 INST(Vfmaddsub213ps , VexRvm_Lx , V(660F38,A6,_,x,0,0,4,FV ), 0 , 163, 0 , 4797 , 195, 139), // #940
1038 INST(Vfmaddsub231pd , VexRvm_Lx , V(660F38,B6,_,x,1,1,4,FV ), 0 , 162, 0 , 4812 , 194, 139), // #941
1039 INST(Vfmaddsub231ps , VexRvm_Lx , V(660F38,B6,_,x,0,0,4,FV ), 0 , 163, 0 , 4827 , 195, 139), // #942
1040 INST(Vfmaddsubpd , Fma4_Lx , V(660F3A,5D,_,x,x,_,_,_ ), 0 , 74 , 0 , 4842 , 268, 141), // #943
1041 INST(Vfmaddsubps , Fma4_Lx , V(660F3A,5C,_,x,x,_,_,_ ), 0 , 74 , 0 , 4854 , 268, 141), // #944
1042 INST(Vfmsub132pd , VexRvm_Lx , V(660F38,9A,_,x,1,1,4,FV ), 0 , 162, 0 , 4866 , 194, 139), // #945
1043 INST(Vfmsub132ps , VexRvm_Lx , V(660F38,9A,_,x,0,0,4,FV ), 0 , 163, 0 , 4878 , 195, 139), // #946
1044 INST(Vfmsub132sd , VexRvm , V(660F38,9B,_,I,1,1,3,T1S), 0 , 164, 0 , 4890 , 196, 140), // #947
1045 INST(Vfmsub132ss , VexRvm , V(660F38,9B,_,I,0,0,2,T1S), 0 , 121, 0 , 4902 , 197, 140), // #948
1046 INST(Vfmsub213pd , VexRvm_Lx , V(660F38,AA,_,x,1,1,4,FV ), 0 , 162, 0 , 4914 , 194, 139), // #949
1047 INST(Vfmsub213ps , VexRvm_Lx , V(660F38,AA,_,x,0,0,4,FV ), 0 , 163, 0 , 4926 , 195, 139), // #950
1048 INST(Vfmsub213sd , VexRvm , V(660F38,AB,_,I,1,1,3,T1S), 0 , 164, 0 , 4938 , 196, 140), // #951
1049 INST(Vfmsub213ss , VexRvm , V(660F38,AB,_,I,0,0,2,T1S), 0 , 121, 0 , 4950 , 197, 140), // #952
1050 INST(Vfmsub231pd , VexRvm_Lx , V(660F38,BA,_,x,1,1,4,FV ), 0 , 162, 0 , 4962 , 194, 139), // #953
1051 INST(Vfmsub231ps , VexRvm_Lx , V(660F38,BA,_,x,0,0,4,FV ), 0 , 163, 0 , 4974 , 195, 139), // #954
1052 INST(Vfmsub231sd , VexRvm , V(660F38,BB,_,I,1,1,3,T1S), 0 , 164, 0 , 4986 , 196, 140), // #955
1053 INST(Vfmsub231ss , VexRvm , V(660F38,BB,_,I,0,0,2,T1S), 0 , 121, 0 , 4998 , 197, 140), // #956
1054 INST(Vfmsubadd132pd , VexRvm_Lx , V(660F38,97,_,x,1,1,4,FV ), 0 , 162, 0 , 5010 , 194, 139), // #957
1055 INST(Vfmsubadd132ps , VexRvm_Lx , V(660F38,97,_,x,0,0,4,FV ), 0 , 163, 0 , 5025 , 195, 139), // #958
1056 INST(Vfmsubadd213pd , VexRvm_Lx , V(660F38,A7,_,x,1,1,4,FV ), 0 , 162, 0 , 5040 , 194, 139), // #959
1057 INST(Vfmsubadd213ps , VexRvm_Lx , V(660F38,A7,_,x,0,0,4,FV ), 0 , 163, 0 , 5055 , 195, 139), // #960
1058 INST(Vfmsubadd231pd , VexRvm_Lx , V(660F38,B7,_,x,1,1,4,FV ), 0 , 162, 0 , 5070 , 194, 139), // #961
1059 INST(Vfmsubadd231ps , VexRvm_Lx , V(660F38,B7,_,x,0,0,4,FV ), 0 , 163, 0 , 5085 , 195, 139), // #962
1060 INST(Vfmsubaddpd , Fma4_Lx , V(660F3A,5F,_,x,x,_,_,_ ), 0 , 74 , 0 , 5100 , 268, 141), // #963
1061 INST(Vfmsubaddps , Fma4_Lx , V(660F3A,5E,_,x,x,_,_,_ ), 0 , 74 , 0 , 5112 , 268, 141), // #964
1062 INST(Vfmsubpd , Fma4_Lx , V(660F3A,6D,_,x,x,_,_,_ ), 0 , 74 , 0 , 5124 , 268, 141), // #965
1063 INST(Vfmsubps , Fma4_Lx , V(660F3A,6C,_,x,x,_,_,_ ), 0 , 74 , 0 , 5133 , 268, 141), // #966
1064 INST(Vfmsubsd , Fma4 , V(660F3A,6F,_,0,x,_,_,_ ), 0 , 74 , 0 , 5142 , 269, 141), // #967
1065 INST(Vfmsubss , Fma4 , V(660F3A,6E,_,0,x,_,_,_ ), 0 , 74 , 0 , 5151 , 270, 141), // #968
1066 INST(Vfnmadd132pd , VexRvm_Lx , V(660F38,9C,_,x,1,1,4,FV ), 0 , 162, 0 , 5160 , 194, 139), // #969
1067 INST(Vfnmadd132ps , VexRvm_Lx , V(660F38,9C,_,x,0,0,4,FV ), 0 , 163, 0 , 5173 , 195, 139), // #970
1068 INST(Vfnmadd132sd , VexRvm , V(660F38,9D,_,I,1,1,3,T1S), 0 , 164, 0 , 5186 , 196, 140), // #971
1069 INST(Vfnmadd132ss , VexRvm , V(660F38,9D,_,I,0,0,2,T1S), 0 , 121, 0 , 5199 , 197, 140), // #972
1070 INST(Vfnmadd213pd , VexRvm_Lx , V(660F38,AC,_,x,1,1,4,FV ), 0 , 162, 0 , 5212 , 194, 139), // #973
1071 INST(Vfnmadd213ps , VexRvm_Lx , V(660F38,AC,_,x,0,0,4,FV ), 0 , 163, 0 , 5225 , 195, 139), // #974
1072 INST(Vfnmadd213sd , VexRvm , V(660F38,AD,_,I,1,1,3,T1S), 0 , 164, 0 , 5238 , 196, 140), // #975
1073 INST(Vfnmadd213ss , VexRvm , V(660F38,AD,_,I,0,0,2,T1S), 0 , 121, 0 , 5251 , 197, 140), // #976
1074 INST(Vfnmadd231pd , VexRvm_Lx , V(660F38,BC,_,x,1,1,4,FV ), 0 , 162, 0 , 5264 , 194, 139), // #977
1075 INST(Vfnmadd231ps , VexRvm_Lx , V(660F38,BC,_,x,0,0,4,FV ), 0 , 163, 0 , 5277 , 195, 139), // #978
1076 INST(Vfnmadd231sd , VexRvm , V(660F38,BD,_,I,1,1,3,T1S), 0 , 164, 0 , 5290 , 196, 140), // #979
1077 INST(Vfnmadd231ss , VexRvm , V(660F38,BD,_,I,0,0,2,T1S), 0 , 121, 0 , 5303 , 197, 140), // #980
1078 INST(Vfnmaddpd , Fma4_Lx , V(660F3A,79,_,x,x,_,_,_ ), 0 , 74 , 0 , 5316 , 268, 141), // #981
1079 INST(Vfnmaddps , Fma4_Lx , V(660F3A,78,_,x,x,_,_,_ ), 0 , 74 , 0 , 5326 , 268, 141), // #982
1080 INST(Vfnmaddsd , Fma4 , V(660F3A,7B,_,0,x,_,_,_ ), 0 , 74 , 0 , 5336 , 269, 141), // #983
1081 INST(Vfnmaddss , Fma4 , V(660F3A,7A,_,0,x,_,_,_ ), 0 , 74 , 0 , 5346 , 270, 141), // #984
1082 INST(Vfnmsub132pd , VexRvm_Lx , V(660F38,9E,_,x,1,1,4,FV ), 0 , 162, 0 , 5356 , 194, 139), // #985
1083 INST(Vfnmsub132ps , VexRvm_Lx , V(660F38,9E,_,x,0,0,4,FV ), 0 , 163, 0 , 5369 , 195, 139), // #986
1084 INST(Vfnmsub132sd , VexRvm , V(660F38,9F,_,I,1,1,3,T1S), 0 , 164, 0 , 5382 , 196, 140), // #987
1085 INST(Vfnmsub132ss , VexRvm , V(660F38,9F,_,I,0,0,2,T1S), 0 , 121, 0 , 5395 , 197, 140), // #988
1086 INST(Vfnmsub213pd , VexRvm_Lx , V(660F38,AE,_,x,1,1,4,FV ), 0 , 162, 0 , 5408 , 194, 139), // #989
1087 INST(Vfnmsub213ps , VexRvm_Lx , V(660F38,AE,_,x,0,0,4,FV ), 0 , 163, 0 , 5421 , 195, 139), // #990
1088 INST(Vfnmsub213sd , VexRvm , V(660F38,AF,_,I,1,1,3,T1S), 0 , 164, 0 , 5434 , 196, 140), // #991
1089 INST(Vfnmsub213ss , VexRvm , V(660F38,AF,_,I,0,0,2,T1S), 0 , 121, 0 , 5447 , 197, 140), // #992
1090 INST(Vfnmsub231pd , VexRvm_Lx , V(660F38,BE,_,x,1,1,4,FV ), 0 , 162, 0 , 5460 , 194, 139), // #993
1091 INST(Vfnmsub231ps , VexRvm_Lx , V(660F38,BE,_,x,0,0,4,FV ), 0 , 163, 0 , 5473 , 195, 139), // #994
1092 INST(Vfnmsub231sd , VexRvm , V(660F38,BF,_,I,1,1,3,T1S), 0 , 164, 0 , 5486 , 196, 140), // #995
1093 INST(Vfnmsub231ss , VexRvm , V(660F38,BF,_,I,0,0,2,T1S), 0 , 121, 0 , 5499 , 197, 140), // #996
1094 INST(Vfnmsubpd , Fma4_Lx , V(660F3A,7D,_,x,x,_,_,_ ), 0 , 74 , 0 , 5512 , 268, 141), // #997
1095 INST(Vfnmsubps , Fma4_Lx , V(660F3A,7C,_,x,x,_,_,_ ), 0 , 74 , 0 , 5522 , 268, 141), // #998
1096 INST(Vfnmsubsd , Fma4 , V(660F3A,7F,_,0,x,_,_,_ ), 0 , 74 , 0 , 5532 , 269, 141), // #999
1097 INST(Vfnmsubss , Fma4 , V(660F3A,7E,_,0,x,_,_,_ ), 0 , 74 , 0 , 5542 , 270, 141), // #1000
1098 INST(Vfpclasspd , VexRmi_Lx , E(660F3A,66,_,x,_,1,4,FV ), 0 , 111, 0 , 5552 , 271, 131), // #1001
1099 INST(Vfpclassps , VexRmi_Lx , E(660F3A,66,_,x,_,0,4,FV ), 0 , 110, 0 , 5563 , 272, 131), // #1002
1100 INST(Vfpclasssd , VexRmi_Lx , E(660F3A,67,_,I,_,1,3,T1S), 0 , 160, 0 , 5574 , 273, 66 ), // #1003
1101 INST(Vfpclassss , VexRmi_Lx , E(660F3A,67,_,I,_,0,2,T1S), 0 , 161, 0 , 5585 , 274, 66 ), // #1004
1102 INST(Vfrczpd , VexRm_Lx , V(XOP_M9,81,_,x,0,_,_,_ ), 0 , 80 , 0 , 5596 , 275, 142), // #1005
1103 INST(Vfrczps , VexRm_Lx , V(XOP_M9,80,_,x,0,_,_,_ ), 0 , 80 , 0 , 5604 , 275, 142), // #1006
1104 INST(Vfrczsd , VexRm , V(XOP_M9,83,_,0,0,_,_,_ ), 0 , 80 , 0 , 5612 , 276, 142), // #1007
1105 INST(Vfrczss , VexRm , V(XOP_M9,82,_,0,0,_,_,_ ), 0 , 80 , 0 , 5620 , 277, 142), // #1008
1106 INST(Vgatherdpd , VexRmvRm_VM , V(660F38,92,_,x,1,_,_,_ ), E(660F38,92,_,x,_,1,3,T1S), 165, 81 , 5628 , 278, 143), // #1009
1107 INST(Vgatherdps , VexRmvRm_VM , V(660F38,92,_,x,0,_,_,_ ), E(660F38,92,_,x,_,0,2,T1S), 97 , 82 , 5639 , 279, 143), // #1010
1108 INST(Vgatherpf0dpd , VexM_VM , E(660F38,C6,1,2,_,1,3,T1S), 0 , 166, 0 , 5650 , 280, 144), // #1011
1109 INST(Vgatherpf0dps , VexM_VM , E(660F38,C6,1,2,_,0,2,T1S), 0 , 167, 0 , 5664 , 281, 144), // #1012
1110 INST(Vgatherpf0qpd , VexM_VM , E(660F38,C7,1,2,_,1,3,T1S), 0 , 166, 0 , 5678 , 282, 144), // #1013
1111 INST(Vgatherpf0qps , VexM_VM , E(660F38,C7,1,2,_,0,2,T1S), 0 , 167, 0 , 5692 , 282, 144), // #1014
1112 INST(Vgatherpf1dpd , VexM_VM , E(660F38,C6,2,2,_,1,3,T1S), 0 , 168, 0 , 5706 , 280, 144), // #1015
1113 INST(Vgatherpf1dps , VexM_VM , E(660F38,C6,2,2,_,0,2,T1S), 0 , 169, 0 , 5720 , 281, 144), // #1016
1114 INST(Vgatherpf1qpd , VexM_VM , E(660F38,C7,2,2,_,1,3,T1S), 0 , 168, 0 , 5734 , 282, 144), // #1017
1115 INST(Vgatherpf1qps , VexM_VM , E(660F38,C7,2,2,_,0,2,T1S), 0 , 169, 0 , 5748 , 282, 144), // #1018
1116 INST(Vgatherqpd , VexRmvRm_VM , V(660F38,93,_,x,1,_,_,_ ), E(660F38,93,_,x,_,1,3,T1S), 165, 83 , 5762 , 283, 143), // #1019
1117 INST(Vgatherqps , VexRmvRm_VM , V(660F38,93,_,x,0,_,_,_ ), E(660F38,93,_,x,_,0,2,T1S), 97 , 84 , 5773 , 284, 143), // #1020
1118 INST(Vgetexppd , VexRm_Lx , E(660F38,42,_,x,_,1,4,FV ), 0 , 112, 0 , 5784 , 244, 129), // #1021
1119 INST(Vgetexpps , VexRm_Lx , E(660F38,42,_,x,_,0,4,FV ), 0 , 113, 0 , 5794 , 248, 129), // #1022
1120 INST(Vgetexpsd , VexRvm , E(660F38,43,_,I,_,1,3,T1S), 0 , 124, 0 , 5804 , 285, 68 ), // #1023
1121 INST(Vgetexpss , VexRvm , E(660F38,43,_,I,_,0,2,T1S), 0 , 125, 0 , 5814 , 286, 68 ), // #1024
1122 INST(Vgetmantpd , VexRmi_Lx , E(660F3A,26,_,x,_,1,4,FV ), 0 , 111, 0 , 5824 , 287, 129), // #1025
1123 INST(Vgetmantps , VexRmi_Lx , E(660F3A,26,_,x,_,0,4,FV ), 0 , 110, 0 , 5835 , 288, 129), // #1026
1124 INST(Vgetmantsd , VexRvmi , E(660F3A,27,_,I,_,1,3,T1S), 0 , 160, 0 , 5846 , 266, 68 ), // #1027
1125 INST(Vgetmantss , VexRvmi , E(660F3A,27,_,I,_,0,2,T1S), 0 , 161, 0 , 5857 , 267, 68 ), // #1028
1126 INST(Vgf2p8affineinvqb, VexRvmi_Lx , V(660F3A,CF,_,x,1,1,4,FV ), 0 , 170, 0 , 5868 , 289, 145), // #1029
1127 INST(Vgf2p8affineqb , VexRvmi_Lx , V(660F3A,CE,_,x,1,1,4,FV ), 0 , 170, 0 , 5886 , 289, 145), // #1030
1128 INST(Vgf2p8mulb , VexRvm_Lx , V(660F38,CF,_,x,0,0,4,FV ), 0 , 163, 0 , 5901 , 290, 145), // #1031
1129 INST(Vhaddpd , VexRvm_Lx , V(660F00,7C,_,x,I,_,_,_ ), 0 , 70 , 0 , 5912 , 198, 126), // #1032
1130 INST(Vhaddps , VexRvm_Lx , V(F20F00,7C,_,x,I,_,_,_ ), 0 , 108, 0 , 5920 , 198, 126), // #1033
1131 INST(Vhsubpd , VexRvm_Lx , V(660F00,7D,_,x,I,_,_,_ ), 0 , 70 , 0 , 5928 , 198, 126), // #1034
1132 INST(Vhsubps , VexRvm_Lx , V(F20F00,7D,_,x,I,_,_,_ ), 0 , 108, 0 , 5936 , 198, 126), // #1035
1133 INST(Vinsertf128 , VexRvmi , V(660F3A,18,_,1,0,_,_,_ ), 0 , 154, 0 , 5944 , 291, 126), // #1036
1134 INST(Vinsertf32x4 , VexRvmi_Lx , E(660F3A,18,_,x,_,0,4,T4 ), 0 , 155, 0 , 5956 , 292, 129), // #1037
1135 INST(Vinsertf32x8 , VexRvmi , E(660F3A,1A,_,2,_,0,5,T8 ), 0 , 156, 0 , 5969 , 293, 66 ), // #1038
1136 INST(Vinsertf64x2 , VexRvmi_Lx , E(660F3A,18,_,x,_,1,4,T2 ), 0 , 157, 0 , 5982 , 292, 131), // #1039
1137 INST(Vinsertf64x4 , VexRvmi , E(660F3A,1A,_,2,_,1,5,T4 ), 0 , 158, 0 , 5995 , 293, 68 ), // #1040
1138 INST(Vinserti128 , VexRvmi , V(660F3A,38,_,1,0,_,_,_ ), 0 , 154, 0 , 6008 , 291, 132), // #1041
1139 INST(Vinserti32x4 , VexRvmi_Lx , E(660F3A,38,_,x,_,0,4,T4 ), 0 , 155, 0 , 6020 , 292, 129), // #1042
1140 INST(Vinserti32x8 , VexRvmi , E(660F3A,3A,_,2,_,0,5,T8 ), 0 , 156, 0 , 6033 , 293, 66 ), // #1043
1141 INST(Vinserti64x2 , VexRvmi_Lx , E(660F3A,38,_,x,_,1,4,T2 ), 0 , 157, 0 , 6046 , 292, 131), // #1044
1142 INST(Vinserti64x4 , VexRvmi , E(660F3A,3A,_,2,_,1,5,T4 ), 0 , 158, 0 , 6059 , 293, 68 ), // #1045
1143 INST(Vinsertps , VexRvmi , V(660F3A,21,_,0,I,0,2,T1S), 0 , 159, 0 , 6072 , 294, 125), // #1046
1144 INST(Vlddqu , VexRm_Lx , V(F20F00,F0,_,x,I,_,_,_ ), 0 , 108, 0 , 6082 , 295, 126), // #1047
1145 INST(Vldmxcsr , VexM , V(000F00,AE,2,0,I,_,_,_ ), 0 , 171, 0 , 6089 , 296, 126), // #1048
1146 INST(Vmaskmovdqu , VexRm_ZDI , V(660F00,F7,_,0,I,_,_,_ ), 0 , 70 , 0 , 6098 , 297, 126), // #1049
1147 INST(Vmaskmovpd , VexRvmMvr_Lx , V(660F38,2D,_,x,0,_,_,_ ), V(660F38,2F,_,x,0,_,_,_ ), 97 , 85 , 6110 , 298, 126), // #1050
1148 INST(Vmaskmovps , VexRvmMvr_Lx , V(660F38,2C,_,x,0,_,_,_ ), V(660F38,2E,_,x,0,_,_,_ ), 97 , 86 , 6121 , 298, 126), // #1051
1149 INST(Vmaxpd , VexRvm_Lx , V(660F00,5F,_,x,I,1,4,FV ), 0 , 104, 0 , 6132 , 299, 124), // #1052
1150 INST(Vmaxps , VexRvm_Lx , V(000F00,5F,_,x,I,0,4,FV ), 0 , 105, 0 , 6139 , 300, 124), // #1053
1151 INST(Vmaxsd , VexRvm , V(F20F00,5F,_,I,I,1,3,T1S), 0 , 106, 0 , 6146 , 301, 124), // #1054
1152 INST(Vmaxss , VexRvm , V(F30F00,5F,_,I,I,0,2,T1S), 0 , 107, 0 , 6153 , 240, 124), // #1055
1153 INST(Vmcall , X86Op , O(000F01,C1,_,_,_,_,_,_ ), 0 , 21 , 0 , 6160 , 30 , 58 ), // #1056
1154 INST(Vmclear , X86M_Only , O(660F00,C7,6,_,_,_,_,_ ), 0 , 26 , 0 , 6167 , 32 , 58 ), // #1057
1155 INST(Vmfunc , X86Op , O(000F01,D4,_,_,_,_,_,_ ), 0 , 21 , 0 , 6175 , 30 , 58 ), // #1058
1156 INST(Vminpd , VexRvm_Lx , V(660F00,5D,_,x,I,1,4,FV ), 0 , 104, 0 , 6182 , 299, 124), // #1059
1157 INST(Vminps , VexRvm_Lx , V(000F00,5D,_,x,I,0,4,FV ), 0 , 105, 0 , 6189 , 300, 124), // #1060
1158 INST(Vminsd , VexRvm , V(F20F00,5D,_,I,I,1,3,T1S), 0 , 106, 0 , 6196 , 301, 124), // #1061
1159 INST(Vminss , VexRvm , V(F30F00,5D,_,I,I,0,2,T1S), 0 , 107, 0 , 6203 , 240, 124), // #1062
1160 INST(Vmlaunch , X86Op , O(000F01,C2,_,_,_,_,_,_ ), 0 , 21 , 0 , 6210 , 30 , 58 ), // #1063
1161 INST(Vmload , X86Op_xAX , O(000F01,DA,_,_,_,_,_,_ ), 0 , 21 , 0 , 6219 , 302, 22 ), // #1064
1162 INST(Vmmcall , X86Op , O(000F01,D9,_,_,_,_,_,_ ), 0 , 21 , 0 , 6226 , 30 , 22 ), // #1065
1163 INST(Vmovapd , VexRmMr_Lx , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 172, 87 , 6234 , 303, 124), // #1066
1164 INST(Vmovaps , VexRmMr_Lx , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 173, 88 , 6242 , 303, 124), // #1067
1165 INST(Vmovd , VexMovdMovq , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 174, 89 , 6250 , 304, 125), // #1068
1166 INST(Vmovddup , VexRm_Lx , V(F20F00,12,_,x,I,1,3,DUP), 0 , 175, 0 , 6256 , 305, 124), // #1069
1167 INST(Vmovdqa , VexRmMr_Lx , V(660F00,6F,_,x,I,_,_,_ ), V(660F00,7F,_,x,I,_,_,_ ), 70 , 90 , 6265 , 306, 126), // #1070
1168 INST(Vmovdqa32 , VexRmMr_Lx , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 176, 91 , 6273 , 307, 129), // #1071
1169 INST(Vmovdqa64 , VexRmMr_Lx , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 177, 92 , 6283 , 307, 129), // #1072
1170 INST(Vmovdqu , VexRmMr_Lx , V(F30F00,6F,_,x,I,_,_,_ ), V(F30F00,7F,_,x,I,_,_,_ ), 178, 93 , 6293 , 306, 126), // #1073
1171 INST(Vmovdqu16 , VexRmMr_Lx , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 179, 94 , 6301 , 307, 137), // #1074
1172 INST(Vmovdqu32 , VexRmMr_Lx , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 180, 95 , 6311 , 307, 129), // #1075
1173 INST(Vmovdqu64 , VexRmMr_Lx , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 181, 96 , 6321 , 307, 129), // #1076
1174 INST(Vmovdqu8 , VexRmMr_Lx , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 182, 97 , 6331 , 307, 137), // #1077
1175 INST(Vmovhlps , VexRvm , V(000F00,12,_,0,I,0,_,_ ), 0 , 73 , 0 , 6340 , 308, 125), // #1078
1176 INST(Vmovhpd , VexRvmMr , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 122, 98 , 6349 , 309, 125), // #1079
1177 INST(Vmovhps , VexRvmMr , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 183, 99 , 6357 , 309, 125), // #1080
1178 INST(Vmovlhps , VexRvm , V(000F00,16,_,0,I,0,_,_ ), 0 , 73 , 0 , 6365 , 308, 125), // #1081
1179 INST(Vmovlpd , VexRvmMr , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 122, 100, 6374 , 309, 125), // #1082
1180 INST(Vmovlps , VexRvmMr , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 183, 101, 6382 , 309, 125), // #1083
1181 INST(Vmovmskpd , VexRm_Lx , V(660F00,50,_,x,I,_,_,_ ), 0 , 70 , 0 , 6390 , 310, 126), // #1084
1182 INST(Vmovmskps , VexRm_Lx , V(000F00,50,_,x,I,_,_,_ ), 0 , 73 , 0 , 6400 , 310, 126), // #1085
1183 INST(Vmovntdq , VexMr_Lx , V(660F00,E7,_,x,I,0,4,FVM), 0 , 184, 0 , 6410 , 311, 124), // #1086
1184 INST(Vmovntdqa , VexRm_Lx , V(660F38,2A,_,x,I,0,4,FVM), 0 , 109, 0 , 6419 , 312, 133), // #1087
1185 INST(Vmovntpd , VexMr_Lx , V(660F00,2B,_,x,I,1,4,FVM), 0 , 172, 0 , 6429 , 311, 124), // #1088
1186 INST(Vmovntps , VexMr_Lx , V(000F00,2B,_,x,I,0,4,FVM), 0 , 173, 0 , 6438 , 311, 124), // #1089
1187 INST(Vmovq , VexMovdMovq , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 122, 102, 6447 , 313, 125), // #1090
1188 INST(Vmovsd , VexMovssMovsd , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 106, 103, 6453 , 314, 125), // #1091
1189 INST(Vmovshdup , VexRm_Lx , V(F30F00,16,_,x,I,0,4,FVM), 0 , 185, 0 , 6460 , 315, 124), // #1092
1190 INST(Vmovsldup , VexRm_Lx , V(F30F00,12,_,x,I,0,4,FVM), 0 , 185, 0 , 6470 , 315, 124), // #1093
1191 INST(Vmovss , VexMovssMovsd , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 107, 104, 6480 , 316, 125), // #1094
1192 INST(Vmovupd , VexRmMr_Lx , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 172, 105, 6487 , 303, 124), // #1095
1193 INST(Vmovups , VexRmMr_Lx , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 173, 106, 6495 , 303, 124), // #1096
1194 INST(Vmpsadbw , VexRvmi_Lx , V(660F3A,42,_,x,I,_,_,_ ), 0 , 74 , 0 , 6503 , 210, 146), // #1097
1195 INST(Vmptrld , X86M_Only , O(000F00,C7,6,_,_,_,_,_ ), 0 , 81 , 0 , 6512 , 32 , 58 ), // #1098
1196 INST(Vmptrst , X86M_Only , O(000F00,C7,7,_,_,_,_,_ ), 0 , 22 , 0 , 6520 , 32 , 58 ), // #1099
1197 INST(Vmread , X86Mr_NoSize , O(000F00,78,_,_,_,_,_,_ ), 0 , 4 , 0 , 6528 , 317, 58 ), // #1100
1198 INST(Vmresume , X86Op , O(000F01,C3,_,_,_,_,_,_ ), 0 , 21 , 0 , 6535 , 30 , 58 ), // #1101
1199 INST(Vmrun , X86Op_xAX , O(000F01,D8,_,_,_,_,_,_ ), 0 , 21 , 0 , 6544 , 302, 22 ), // #1102
1200 INST(Vmsave , X86Op_xAX , O(000F01,DB,_,_,_,_,_,_ ), 0 , 21 , 0 , 6550 , 302, 22 ), // #1103
1201 INST(Vmulpd , VexRvm_Lx , V(660F00,59,_,x,I,1,4,FV ), 0 , 104, 0 , 6557 , 194, 124), // #1104
1202 INST(Vmulps , VexRvm_Lx , V(000F00,59,_,x,I,0,4,FV ), 0 , 105, 0 , 6564 , 195, 124), // #1105
1203 INST(Vmulsd , VexRvm_Lx , V(F20F00,59,_,I,I,1,3,T1S), 0 , 106, 0 , 6571 , 196, 125), // #1106
1204 INST(Vmulss , VexRvm_Lx , V(F30F00,59,_,I,I,0,2,T1S), 0 , 107, 0 , 6578 , 197, 125), // #1107
1205 INST(Vmwrite , X86Rm_NoSize , O(000F00,79,_,_,_,_,_,_ ), 0 , 4 , 0 , 6585 , 318, 58 ), // #1108
1206 INST(Vmxon , X86M_Only , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 24 , 0 , 6593 , 32 , 58 ), // #1109
1207 INST(Vorpd , VexRvm_Lx , V(660F00,56,_,x,I,1,4,FV ), 0 , 104, 0 , 6599 , 206, 130), // #1110
1208 INST(Vorps , VexRvm_Lx , V(000F00,56,_,x,I,0,4,FV ), 0 , 105, 0 , 6605 , 207, 130), // #1111
1209 INST(Vp2intersectd , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,0,4,FV ), 0 , 127, 0 , 6611 , 319, 147), // #1112
1210 INST(Vp2intersectq , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,1,4,FV ), 0 , 186, 0 , 6625 , 320, 147), // #1113
1211 INST(Vp4dpwssd , VexRm_T1_4X , E(F20F38,52,_,2,_,0,4,T4X), 0 , 102, 0 , 6639 , 192, 148), // #1114
1212 INST(Vp4dpwssds , VexRm_T1_4X , E(F20F38,53,_,2,_,0,4,T4X), 0 , 102, 0 , 6649 , 192, 148), // #1115
1213 INST(Vpabsb , VexRm_Lx , V(660F38,1C,_,x,I,_,4,FVM), 0 , 109, 0 , 6660 , 315, 149), // #1116
1214 INST(Vpabsd , VexRm_Lx , V(660F38,1E,_,x,I,0,4,FV ), 0 , 163, 0 , 6667 , 315, 133), // #1117
1215 INST(Vpabsq , VexRm_Lx , E(660F38,1F,_,x,_,1,4,FV ), 0 , 112, 0 , 6674 , 259, 129), // #1118
1216 INST(Vpabsw , VexRm_Lx , V(660F38,1D,_,x,I,_,4,FVM), 0 , 109, 0 , 6681 , 315, 149), // #1119
1217 INST(Vpackssdw , VexRvm_Lx , V(660F00,6B,_,x,I,0,4,FV ), 0 , 133, 0 , 6688 , 205, 149), // #1120
1218 INST(Vpacksswb , VexRvm_Lx , V(660F00,63,_,x,I,I,4,FVM), 0 , 184, 0 , 6698 , 290, 149), // #1121
1219 INST(Vpackusdw , VexRvm_Lx , V(660F38,2B,_,x,I,0,4,FV ), 0 , 163, 0 , 6708 , 205, 149), // #1122
1220 INST(Vpackuswb , VexRvm_Lx , V(660F00,67,_,x,I,I,4,FVM), 0 , 184, 0 , 6718 , 290, 149), // #1123
1221 INST(Vpaddb , VexRvm_Lx , V(660F00,FC,_,x,I,I,4,FVM), 0 , 184, 0 , 6728 , 290, 149), // #1124
1222 INST(Vpaddd , VexRvm_Lx , V(660F00,FE,_,x,I,0,4,FV ), 0 , 133, 0 , 6735 , 205, 133), // #1125
1223 INST(Vpaddq , VexRvm_Lx , V(660F00,D4,_,x,I,1,4,FV ), 0 , 104, 0 , 6742 , 204, 133), // #1126
1224 INST(Vpaddsb , VexRvm_Lx , V(660F00,EC,_,x,I,I,4,FVM), 0 , 184, 0 , 6749 , 290, 149), // #1127
1225 INST(Vpaddsw , VexRvm_Lx , V(660F00,ED,_,x,I,I,4,FVM), 0 , 184, 0 , 6757 , 290, 149), // #1128
1226 INST(Vpaddusb , VexRvm_Lx , V(660F00,DC,_,x,I,I,4,FVM), 0 , 184, 0 , 6765 , 290, 149), // #1129
1227 INST(Vpaddusw , VexRvm_Lx , V(660F00,DD,_,x,I,I,4,FVM), 0 , 184, 0 , 6774 , 290, 149), // #1130
1228 INST(Vpaddw , VexRvm_Lx , V(660F00,FD,_,x,I,I,4,FVM), 0 , 184, 0 , 6783 , 290, 149), // #1131
1229 INST(Vpalignr , VexRvmi_Lx , V(660F3A,0F,_,x,I,I,4,FVM), 0 , 187, 0 , 6790 , 289, 149), // #1132
1230 INST(Vpand , VexRvm_Lx , V(660F00,DB,_,x,I,_,_,_ ), 0 , 70 , 0 , 6799 , 321, 146), // #1133
1231 INST(Vpandd , VexRvm_Lx , E(660F00,DB,_,x,_,0,4,FV ), 0 , 188, 0 , 6805 , 322, 129), // #1134
1232 INST(Vpandn , VexRvm_Lx , V(660F00,DF,_,x,I,_,_,_ ), 0 , 70 , 0 , 6812 , 323, 146), // #1135
1233 INST(Vpandnd , VexRvm_Lx , E(660F00,DF,_,x,_,0,4,FV ), 0 , 188, 0 , 6819 , 324, 129), // #1136
1234 INST(Vpandnq , VexRvm_Lx , E(660F00,DF,_,x,_,1,4,FV ), 0 , 130, 0 , 6827 , 325, 129), // #1137
1235 INST(Vpandq , VexRvm_Lx , E(660F00,DB,_,x,_,1,4,FV ), 0 , 130, 0 , 6835 , 326, 129), // #1138
1236 INST(Vpavgb , VexRvm_Lx , V(660F00,E0,_,x,I,I,4,FVM), 0 , 184, 0 , 6842 , 290, 149), // #1139
1237 INST(Vpavgw , VexRvm_Lx , V(660F00,E3,_,x,I,I,4,FVM), 0 , 184, 0 , 6849 , 290, 149), // #1140
1238 INST(Vpblendd , VexRvmi_Lx , V(660F3A,02,_,x,0,_,_,_ ), 0 , 74 , 0 , 6856 , 210, 132), // #1141
1239 INST(Vpblendmb , VexRvm_Lx , E(660F38,66,_,x,_,0,4,FVM), 0 , 189, 0 , 6865 , 327, 137), // #1142
1240 INST(Vpblendmd , VexRvm_Lx , E(660F38,64,_,x,_,0,4,FV ), 0 , 113, 0 , 6875 , 209, 129), // #1143
1241 INST(Vpblendmq , VexRvm_Lx , E(660F38,64,_,x,_,1,4,FV ), 0 , 112, 0 , 6885 , 208, 129), // #1144
1242 INST(Vpblendmw , VexRvm_Lx , E(660F38,66,_,x,_,1,4,FVM), 0 , 190, 0 , 6895 , 327, 137), // #1145
1243 INST(Vpblendvb , VexRvmr_Lx , V(660F3A,4C,_,x,0,_,_,_ ), 0 , 74 , 0 , 6905 , 211, 146), // #1146
1244 INST(Vpblendw , VexRvmi_Lx , V(660F3A,0E,_,x,I,_,_,_ ), 0 , 74 , 0 , 6915 , 210, 146), // #1147
1245 INST(Vpbroadcastb , VexRm_Lx_Bcst , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 191, 107, 6924 , 328, 150), // #1148
1246 INST(Vpbroadcastd , VexRm_Lx_Bcst , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 121, 108, 6937 , 329, 143), // #1149
1247 INST(Vpbroadcastmb2q , VexRm_Lx , E(F30F38,2A,_,x,_,1,_,_ ), 0 , 192, 0 , 6950 , 330, 151), // #1150
1248 INST(Vpbroadcastmw2d , VexRm_Lx , E(F30F38,3A,_,x,_,0,_,_ ), 0 , 193, 0 , 6966 , 330, 151), // #1151
1249 INST(Vpbroadcastq , VexRm_Lx_Bcst , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 120, 109, 6982 , 331, 143), // #1152
1250 INST(Vpbroadcastw , VexRm_Lx_Bcst , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 194, 110, 6995 , 332, 150), // #1153
1251 INST(Vpclmulqdq , VexRvmi_Lx , V(660F3A,44,_,x,I,_,4,FVM), 0 , 187, 0 , 7008 , 333, 152), // #1154
1252 INST(Vpcmov , VexRvrmRvmr_Lx , V(XOP_M8,A2,_,x,x,_,_,_ ), 0 , 195, 0 , 7019 , 268, 142), // #1155
1253 INST(Vpcmpb , VexRvmi_Lx , E(660F3A,3F,_,x,_,0,4,FVM), 0 , 151, 0 , 7026 , 334, 137), // #1156
1254 INST(Vpcmpd , VexRvmi_Lx , E(660F3A,1F,_,x,_,0,4,FV ), 0 , 110, 0 , 7033 , 335, 129), // #1157
1255 INST(Vpcmpeqb , VexRvm_Lx_KEvex , V(660F00,74,_,x,I,I,4,FV ), 0 , 133, 0 , 7040 , 336, 149), // #1158
1256 INST(Vpcmpeqd , VexRvm_Lx_KEvex , V(660F00,76,_,x,I,0,4,FVM), 0 , 184, 0 , 7049 , 337, 133), // #1159
1257 INST(Vpcmpeqq , VexRvm_Lx_KEvex , V(660F38,29,_,x,I,1,4,FVM), 0 , 196, 0 , 7058 , 338, 133), // #1160
1258 INST(Vpcmpeqw , VexRvm_Lx_KEvex , V(660F00,75,_,x,I,I,4,FV ), 0 , 133, 0 , 7067 , 336, 149), // #1161
1259 INST(Vpcmpestri , VexRmi , V(660F3A,61,_,0,I,_,_,_ ), 0 , 74 , 0 , 7076 , 339, 153), // #1162
1260 INST(Vpcmpestrm , VexRmi , V(660F3A,60,_,0,I,_,_,_ ), 0 , 74 , 0 , 7087 , 340, 153), // #1163
1261 INST(Vpcmpgtb , VexRvm_Lx_KEvex , V(660F00,64,_,x,I,I,4,FV ), 0 , 133, 0 , 7098 , 336, 149), // #1164
1262 INST(Vpcmpgtd , VexRvm_Lx_KEvex , V(660F00,66,_,x,I,0,4,FVM), 0 , 184, 0 , 7107 , 337, 133), // #1165
1263 INST(Vpcmpgtq , VexRvm_Lx_KEvex , V(660F38,37,_,x,I,1,4,FVM), 0 , 196, 0 , 7116 , 338, 133), // #1166
1264 INST(Vpcmpgtw , VexRvm_Lx_KEvex , V(660F00,65,_,x,I,I,4,FV ), 0 , 133, 0 , 7125 , 336, 149), // #1167
1265 INST(Vpcmpistri , VexRmi , V(660F3A,63,_,0,I,_,_,_ ), 0 , 74 , 0 , 7134 , 341, 153), // #1168
1266 INST(Vpcmpistrm , VexRmi , V(660F3A,62,_,0,I,_,_,_ ), 0 , 74 , 0 , 7145 , 342, 153), // #1169
1267 INST(Vpcmpq , VexRvmi_Lx , E(660F3A,1F,_,x,_,1,4,FV ), 0 , 111, 0 , 7156 , 343, 129), // #1170
1268 INST(Vpcmpub , VexRvmi_Lx , E(660F3A,3E,_,x,_,0,4,FVM), 0 , 151, 0 , 7163 , 334, 137), // #1171
1269 INST(Vpcmpud , VexRvmi_Lx , E(660F3A,1E,_,x,_,0,4,FV ), 0 , 110, 0 , 7171 , 335, 129), // #1172
1270 INST(Vpcmpuq , VexRvmi_Lx , E(660F3A,1E,_,x,_,1,4,FV ), 0 , 111, 0 , 7179 , 343, 129), // #1173
1271 INST(Vpcmpuw , VexRvmi_Lx , E(660F3A,3E,_,x,_,1,4,FVM), 0 , 197, 0 , 7187 , 343, 137), // #1174
1272 INST(Vpcmpw , VexRvmi_Lx , E(660F3A,3F,_,x,_,1,4,FVM), 0 , 197, 0 , 7195 , 343, 137), // #1175
1273 INST(Vpcomb , VexRvmi , V(XOP_M8,CC,_,0,0,_,_,_ ), 0 , 195, 0 , 7202 , 256, 142), // #1176
1274 INST(Vpcomd , VexRvmi , V(XOP_M8,CE,_,0,0,_,_,_ ), 0 , 195, 0 , 7209 , 256, 142), // #1177
1275 INST(Vpcompressb , VexMr_Lx , E(660F38,63,_,x,_,0,0,T1S), 0 , 198, 0 , 7216 , 225, 154), // #1178
1276 INST(Vpcompressd , VexMr_Lx , E(660F38,8B,_,x,_,0,2,T1S), 0 , 125, 0 , 7228 , 225, 129), // #1179
1277 INST(Vpcompressq , VexMr_Lx , E(660F38,8B,_,x,_,1,3,T1S), 0 , 124, 0 , 7240 , 225, 129), // #1180
1278 INST(Vpcompressw , VexMr_Lx , E(660F38,63,_,x,_,1,1,T1S), 0 , 199, 0 , 7252 , 225, 154), // #1181
1279 INST(Vpcomq , VexRvmi , V(XOP_M8,CF,_,0,0,_,_,_ ), 0 , 195, 0 , 7264 , 256, 142), // #1182
1280 INST(Vpcomub , VexRvmi , V(XOP_M8,EC,_,0,0,_,_,_ ), 0 , 195, 0 , 7271 , 256, 142), // #1183
1281 INST(Vpcomud , VexRvmi , V(XOP_M8,EE,_,0,0,_,_,_ ), 0 , 195, 0 , 7279 , 256, 142), // #1184
1282 INST(Vpcomuq , VexRvmi , V(XOP_M8,EF,_,0,0,_,_,_ ), 0 , 195, 0 , 7287 , 256, 142), // #1185
1283 INST(Vpcomuw , VexRvmi , V(XOP_M8,ED,_,0,0,_,_,_ ), 0 , 195, 0 , 7295 , 256, 142), // #1186
1284 INST(Vpcomw , VexRvmi , V(XOP_M8,CD,_,0,0,_,_,_ ), 0 , 195, 0 , 7303 , 256, 142), // #1187
1285 INST(Vpconflictd , VexRm_Lx , E(660F38,C4,_,x,_,0,4,FV ), 0 , 113, 0 , 7310 , 344, 151), // #1188
1286 INST(Vpconflictq , VexRm_Lx , E(660F38,C4,_,x,_,1,4,FV ), 0 , 112, 0 , 7322 , 344, 151), // #1189
1287 INST(Vpdpbusd , VexRvm_Lx , V(660F38,50,_,x,_,0,4,FV ), 0 , 163, 0 , 7334 , 345, 155), // #1190
1288 INST(Vpdpbusds , VexRvm_Lx , V(660F38,51,_,x,_,0,4,FV ), 0 , 163, 0 , 7343 , 345, 155), // #1191
1289 INST(Vpdpwssd , VexRvm_Lx , V(660F38,52,_,x,_,0,4,FV ), 0 , 163, 0 , 7353 , 345, 155), // #1192
1290 INST(Vpdpwssds , VexRvm_Lx , V(660F38,53,_,x,_,0,4,FV ), 0 , 163, 0 , 7362 , 345, 155), // #1193
1291 INST(Vperm2f128 , VexRvmi , V(660F3A,06,_,1,0,_,_,_ ), 0 , 154, 0 , 7372 , 346, 126), // #1194
1292 INST(Vperm2i128 , VexRvmi , V(660F3A,46,_,1,0,_,_,_ ), 0 , 154, 0 , 7383 , 346, 132), // #1195
1293 INST(Vpermb , VexRvm_Lx , E(660F38,8D,_,x,_,0,4,FVM), 0 , 189, 0 , 7394 , 327, 156), // #1196
1294 INST(Vpermd , VexRvm_Lx , V(660F38,36,_,x,0,0,4,FV ), 0 , 163, 0 , 7401 , 347, 143), // #1197
1295 INST(Vpermi2b , VexRvm_Lx , E(660F38,75,_,x,_,0,4,FVM), 0 , 189, 0 , 7408 , 327, 156), // #1198
1296 INST(Vpermi2d , VexRvm_Lx , E(660F38,76,_,x,_,0,4,FV ), 0 , 113, 0 , 7417 , 209, 129), // #1199
1297 INST(Vpermi2pd , VexRvm_Lx , E(660F38,77,_,x,_,1,4,FV ), 0 , 112, 0 , 7426 , 208, 129), // #1200
1298 INST(Vpermi2ps , VexRvm_Lx , E(660F38,77,_,x,_,0,4,FV ), 0 , 113, 0 , 7436 , 209, 129), // #1201
1299 INST(Vpermi2q , VexRvm_Lx , E(660F38,76,_,x,_,1,4,FV ), 0 , 112, 0 , 7446 , 208, 129), // #1202
1300 INST(Vpermi2w , VexRvm_Lx , E(660F38,75,_,x,_,1,4,FVM), 0 , 190, 0 , 7455 , 327, 137), // #1203
1301 INST(Vpermil2pd , VexRvrmiRvmri_Lx , V(660F3A,49,_,x,x,_,_,_ ), 0 , 74 , 0 , 7464 , 348, 142), // #1204
1302 INST(Vpermil2ps , VexRvrmiRvmri_Lx , V(660F3A,48,_,x,x,_,_,_ ), 0 , 74 , 0 , 7475 , 348, 142), // #1205
1303 INST(Vpermilpd , VexRvmRmi_Lx , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 200, 111, 7486 , 349, 124), // #1206
1304 INST(Vpermilps , VexRvmRmi_Lx , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 163, 112, 7496 , 349, 124), // #1207
1305 INST(Vpermpd , VexRvmRmi_Lx , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 201, 113, 7506 , 350, 143), // #1208
1306 INST(Vpermps , VexRvm_Lx , V(660F38,16,_,x,0,0,4,FV ), 0 , 163, 0 , 7514 , 347, 143), // #1209
1307 INST(Vpermq , VexRvmRmi_Lx , E(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 112, 114, 7522 , 350, 143), // #1210
1308 INST(Vpermt2b , VexRvm_Lx , E(660F38,7D,_,x,_,0,4,FVM), 0 , 189, 0 , 7529 , 327, 156), // #1211
1309 INST(Vpermt2d , VexRvm_Lx , E(660F38,7E,_,x,_,0,4,FV ), 0 , 113, 0 , 7538 , 209, 129), // #1212
1310 INST(Vpermt2pd , VexRvm_Lx , E(660F38,7F,_,x,_,1,4,FV ), 0 , 112, 0 , 7547 , 208, 129), // #1213
1311 INST(Vpermt2ps , VexRvm_Lx , E(660F38,7F,_,x,_,0,4,FV ), 0 , 113, 0 , 7557 , 209, 129), // #1214
1312 INST(Vpermt2q , VexRvm_Lx , E(660F38,7E,_,x,_,1,4,FV ), 0 , 112, 0 , 7567 , 208, 129), // #1215
1313 INST(Vpermt2w , VexRvm_Lx , E(660F38,7D,_,x,_,1,4,FVM), 0 , 190, 0 , 7576 , 327, 137), // #1216
1314 INST(Vpermw , VexRvm_Lx , E(660F38,8D,_,x,_,1,4,FVM), 0 , 190, 0 , 7585 , 327, 137), // #1217
1315 INST(Vpexpandb , VexRm_Lx , E(660F38,62,_,x,_,0,0,T1S), 0 , 198, 0 , 7592 , 259, 154), // #1218
1316 INST(Vpexpandd , VexRm_Lx , E(660F38,89,_,x,_,0,2,T1S), 0 , 125, 0 , 7602 , 259, 129), // #1219
1317 INST(Vpexpandq , VexRm_Lx , E(660F38,89,_,x,_,1,3,T1S), 0 , 124, 0 , 7612 , 259, 129), // #1220
1318 INST(Vpexpandw , VexRm_Lx , E(660F38,62,_,x,_,1,1,T1S), 0 , 199, 0 , 7622 , 259, 154), // #1221
1319 INST(Vpextrb , VexMri , V(660F3A,14,_,0,0,I,0,T1S), 0 , 202, 0 , 7632 , 351, 157), // #1222
1320 INST(Vpextrd , VexMri , V(660F3A,16,_,0,0,0,2,T1S), 0 , 159, 0 , 7640 , 263, 158), // #1223
1321 INST(Vpextrq , VexMri , V(660F3A,16,_,0,1,1,3,T1S), 0 , 203, 0 , 7648 , 352, 158), // #1224
1322 INST(Vpextrw , VexMri_Vpextrw , V(660F3A,15,_,0,0,I,1,T1S), 0 , 204, 0 , 7656 , 353, 157), // #1225
1323 INST(Vpgatherdd , VexRmvRm_VM , V(660F38,90,_,x,0,_,_,_ ), E(660F38,90,_,x,_,0,2,T1S), 97 , 115, 7664 , 279, 143), // #1226
1324 INST(Vpgatherdq , VexRmvRm_VM , V(660F38,90,_,x,1,_,_,_ ), E(660F38,90,_,x,_,1,3,T1S), 165, 116, 7675 , 278, 143), // #1227
1325 INST(Vpgatherqd , VexRmvRm_VM , V(660F38,91,_,x,0,_,_,_ ), E(660F38,91,_,x,_,0,2,T1S), 97 , 117, 7686 , 284, 143), // #1228
1326 INST(Vpgatherqq , VexRmvRm_VM , V(660F38,91,_,x,1,_,_,_ ), E(660F38,91,_,x,_,1,3,T1S), 165, 118, 7697 , 283, 143), // #1229
1327 INST(Vphaddbd , VexRm , V(XOP_M9,C2,_,0,0,_,_,_ ), 0 , 80 , 0 , 7708 , 200, 142), // #1230
1328 INST(Vphaddbq , VexRm , V(XOP_M9,C3,_,0,0,_,_,_ ), 0 , 80 , 0 , 7717 , 200, 142), // #1231
1329 INST(Vphaddbw , VexRm , V(XOP_M9,C1,_,0,0,_,_,_ ), 0 , 80 , 0 , 7726 , 200, 142), // #1232
1330 INST(Vphaddd , VexRvm_Lx , V(660F38,02,_,x,I,_,_,_ ), 0 , 97 , 0 , 7735 , 198, 146), // #1233
1331 INST(Vphadddq , VexRm , V(XOP_M9,CB,_,0,0,_,_,_ ), 0 , 80 , 0 , 7743 , 200, 142), // #1234
1332 INST(Vphaddsw , VexRvm_Lx , V(660F38,03,_,x,I,_,_,_ ), 0 , 97 , 0 , 7752 , 198, 146), // #1235
1333 INST(Vphaddubd , VexRm , V(XOP_M9,D2,_,0,0,_,_,_ ), 0 , 80 , 0 , 7761 , 200, 142), // #1236
1334 INST(Vphaddubq , VexRm , V(XOP_M9,D3,_,0,0,_,_,_ ), 0 , 80 , 0 , 7771 , 200, 142), // #1237
1335 INST(Vphaddubw , VexRm , V(XOP_M9,D1,_,0,0,_,_,_ ), 0 , 80 , 0 , 7781 , 200, 142), // #1238
1336 INST(Vphaddudq , VexRm , V(XOP_M9,DB,_,0,0,_,_,_ ), 0 , 80 , 0 , 7791 , 200, 142), // #1239
1337 INST(Vphadduwd , VexRm , V(XOP_M9,D6,_,0,0,_,_,_ ), 0 , 80 , 0 , 7801 , 200, 142), // #1240
1338 INST(Vphadduwq , VexRm , V(XOP_M9,D7,_,0,0,_,_,_ ), 0 , 80 , 0 , 7811 , 200, 142), // #1241
1339 INST(Vphaddw , VexRvm_Lx , V(660F38,01,_,x,I,_,_,_ ), 0 , 97 , 0 , 7821 , 198, 146), // #1242
1340 INST(Vphaddwd , VexRm , V(XOP_M9,C6,_,0,0,_,_,_ ), 0 , 80 , 0 , 7829 , 200, 142), // #1243
1341 INST(Vphaddwq , VexRm , V(XOP_M9,C7,_,0,0,_,_,_ ), 0 , 80 , 0 , 7838 , 200, 142), // #1244
1342 INST(Vphminposuw , VexRm , V(660F38,41,_,0,I,_,_,_ ), 0 , 97 , 0 , 7847 , 200, 126), // #1245
1343 INST(Vphsubbw , VexRm , V(XOP_M9,E1,_,0,0,_,_,_ ), 0 , 80 , 0 , 7859 , 200, 142), // #1246
1344 INST(Vphsubd , VexRvm_Lx , V(660F38,06,_,x,I,_,_,_ ), 0 , 97 , 0 , 7868 , 198, 146), // #1247
1345 INST(Vphsubdq , VexRm , V(XOP_M9,E3,_,0,0,_,_,_ ), 0 , 80 , 0 , 7876 , 200, 142), // #1248
1346 INST(Vphsubsw , VexRvm_Lx , V(660F38,07,_,x,I,_,_,_ ), 0 , 97 , 0 , 7885 , 198, 146), // #1249
1347 INST(Vphsubw , VexRvm_Lx , V(660F38,05,_,x,I,_,_,_ ), 0 , 97 , 0 , 7894 , 198, 146), // #1250
1348 INST(Vphsubwd , VexRm , V(XOP_M9,E2,_,0,0,_,_,_ ), 0 , 80 , 0 , 7902 , 200, 142), // #1251
1349 INST(Vpinsrb , VexRvmi , V(660F3A,20,_,0,0,I,0,T1S), 0 , 202, 0 , 7911 , 354, 157), // #1252
1350 INST(Vpinsrd , VexRvmi , V(660F3A,22,_,0,0,0,2,T1S), 0 , 159, 0 , 7919 , 355, 158), // #1253
1351 INST(Vpinsrq , VexRvmi , V(660F3A,22,_,0,1,1,3,T1S), 0 , 203, 0 , 7927 , 356, 158), // #1254
1352 INST(Vpinsrw , VexRvmi , V(660F00,C4,_,0,0,I,1,T1S), 0 , 205, 0 , 7935 , 357, 157), // #1255
1353 INST(Vplzcntd , VexRm_Lx , E(660F38,44,_,x,_,0,4,FV ), 0 , 113, 0 , 7943 , 344, 151), // #1256
1354 INST(Vplzcntq , VexRm_Lx , E(660F38,44,_,x,_,1,4,FV ), 0 , 112, 0 , 7952 , 358, 151), // #1257
1355 INST(Vpmacsdd , VexRvmr , V(XOP_M8,9E,_,0,0,_,_,_ ), 0 , 195, 0 , 7961 , 359, 142), // #1258
1356 INST(Vpmacsdqh , VexRvmr , V(XOP_M8,9F,_,0,0,_,_,_ ), 0 , 195, 0 , 7970 , 359, 142), // #1259
1357 INST(Vpmacsdql , VexRvmr , V(XOP_M8,97,_,0,0,_,_,_ ), 0 , 195, 0 , 7980 , 359, 142), // #1260
1358 INST(Vpmacssdd , VexRvmr , V(XOP_M8,8E,_,0,0,_,_,_ ), 0 , 195, 0 , 7990 , 359, 142), // #1261
1359 INST(Vpmacssdqh , VexRvmr , V(XOP_M8,8F,_,0,0,_,_,_ ), 0 , 195, 0 , 8000 , 359, 142), // #1262
1360 INST(Vpmacssdql , VexRvmr , V(XOP_M8,87,_,0,0,_,_,_ ), 0 , 195, 0 , 8011 , 359, 142), // #1263
1361 INST(Vpmacsswd , VexRvmr , V(XOP_M8,86,_,0,0,_,_,_ ), 0 , 195, 0 , 8022 , 359, 142), // #1264
1362 INST(Vpmacssww , VexRvmr , V(XOP_M8,85,_,0,0,_,_,_ ), 0 , 195, 0 , 8032 , 359, 142), // #1265
1363 INST(Vpmacswd , VexRvmr , V(XOP_M8,96,_,0,0,_,_,_ ), 0 , 195, 0 , 8042 , 359, 142), // #1266
1364 INST(Vpmacsww , VexRvmr , V(XOP_M8,95,_,0,0,_,_,_ ), 0 , 195, 0 , 8051 , 359, 142), // #1267
1365 INST(Vpmadcsswd , VexRvmr , V(XOP_M8,A6,_,0,0,_,_,_ ), 0 , 195, 0 , 8060 , 359, 142), // #1268
1366 INST(Vpmadcswd , VexRvmr , V(XOP_M8,B6,_,0,0,_,_,_ ), 0 , 195, 0 , 8071 , 359, 142), // #1269
1367 INST(Vpmadd52huq , VexRvm_Lx , E(660F38,B5,_,x,_,1,4,FV ), 0 , 112, 0 , 8081 , 208, 159), // #1270
1368 INST(Vpmadd52luq , VexRvm_Lx , E(660F38,B4,_,x,_,1,4,FV ), 0 , 112, 0 , 8093 , 208, 159), // #1271
1369 INST(Vpmaddubsw , VexRvm_Lx , V(660F38,04,_,x,I,I,4,FVM), 0 , 109, 0 , 8105 , 290, 149), // #1272
1370 INST(Vpmaddwd , VexRvm_Lx , V(660F00,F5,_,x,I,I,4,FVM), 0 , 184, 0 , 8116 , 290, 149), // #1273
1371 INST(Vpmaskmovd , VexRvmMvr_Lx , V(660F38,8C,_,x,0,_,_,_ ), V(660F38,8E,_,x,0,_,_,_ ), 97 , 119, 8125 , 298, 132), // #1274
1372 INST(Vpmaskmovq , VexRvmMvr_Lx , V(660F38,8C,_,x,1,_,_,_ ), V(660F38,8E,_,x,1,_,_,_ ), 165, 120, 8136 , 298, 132), // #1275
1373 INST(Vpmaxsb , VexRvm_Lx , V(660F38,3C,_,x,I,I,4,FVM), 0 , 109, 0 , 8147 , 360, 149), // #1276
1374 INST(Vpmaxsd , VexRvm_Lx , V(660F38,3D,_,x,I,0,4,FV ), 0 , 163, 0 , 8155 , 207, 133), // #1277
1375 INST(Vpmaxsq , VexRvm_Lx , E(660F38,3D,_,x,_,1,4,FV ), 0 , 112, 0 , 8163 , 208, 129), // #1278
1376 INST(Vpmaxsw , VexRvm_Lx , V(660F00,EE,_,x,I,I,4,FVM), 0 , 184, 0 , 8171 , 360, 149), // #1279
1377 INST(Vpmaxub , VexRvm_Lx , V(660F00,DE,_,x,I,I,4,FVM), 0 , 184, 0 , 8179 , 360, 149), // #1280
1378 INST(Vpmaxud , VexRvm_Lx , V(660F38,3F,_,x,I,0,4,FV ), 0 , 163, 0 , 8187 , 207, 133), // #1281
1379 INST(Vpmaxuq , VexRvm_Lx , E(660F38,3F,_,x,_,1,4,FV ), 0 , 112, 0 , 8195 , 208, 129), // #1282
1380 INST(Vpmaxuw , VexRvm_Lx , V(660F38,3E,_,x,I,I,4,FVM), 0 , 109, 0 , 8203 , 360, 149), // #1283
1381 INST(Vpminsb , VexRvm_Lx , V(660F38,38,_,x,I,I,4,FVM), 0 , 109, 0 , 8211 , 360, 149), // #1284
1382 INST(Vpminsd , VexRvm_Lx , V(660F38,39,_,x,I,0,4,FV ), 0 , 163, 0 , 8219 , 207, 133), // #1285
1383 INST(Vpminsq , VexRvm_Lx , E(660F38,39,_,x,_,1,4,FV ), 0 , 112, 0 , 8227 , 208, 129), // #1286
1384 INST(Vpminsw , VexRvm_Lx , V(660F00,EA,_,x,I,I,4,FVM), 0 , 184, 0 , 8235 , 360, 149), // #1287
1385 INST(Vpminub , VexRvm_Lx , V(660F00,DA,_,x,I,_,4,FVM), 0 , 184, 0 , 8243 , 360, 149), // #1288
1386 INST(Vpminud , VexRvm_Lx , V(660F38,3B,_,x,I,0,4,FV ), 0 , 163, 0 , 8251 , 207, 133), // #1289
1387 INST(Vpminuq , VexRvm_Lx , E(660F38,3B,_,x,_,1,4,FV ), 0 , 112, 0 , 8259 , 208, 129), // #1290
1388 INST(Vpminuw , VexRvm_Lx , V(660F38,3A,_,x,I,_,4,FVM), 0 , 109, 0 , 8267 , 360, 149), // #1291
1389 INST(Vpmovb2m , VexRm_Lx , E(F30F38,29,_,x,_,0,_,_ ), 0 , 193, 0 , 8275 , 361, 137), // #1292
1390 INST(Vpmovd2m , VexRm_Lx , E(F30F38,39,_,x,_,0,_,_ ), 0 , 193, 0 , 8284 , 361, 131), // #1293
1391 INST(Vpmovdb , VexMr_Lx , E(F30F38,31,_,x,_,0,2,QVM), 0 , 206, 0 , 8293 , 362, 129), // #1294
1392 INST(Vpmovdw , VexMr_Lx , E(F30F38,33,_,x,_,0,3,HVM), 0 , 207, 0 , 8301 , 363, 129), // #1295
1393 INST(Vpmovm2b , VexRm_Lx , E(F30F38,28,_,x,_,0,_,_ ), 0 , 193, 0 , 8309 , 330, 137), // #1296
1394 INST(Vpmovm2d , VexRm_Lx , E(F30F38,38,_,x,_,0,_,_ ), 0 , 193, 0 , 8318 , 330, 131), // #1297
1395 INST(Vpmovm2q , VexRm_Lx , E(F30F38,38,_,x,_,1,_,_ ), 0 , 192, 0 , 8327 , 330, 131), // #1298
1396 INST(Vpmovm2w , VexRm_Lx , E(F30F38,28,_,x,_,1,_,_ ), 0 , 192, 0 , 8336 , 330, 137), // #1299
1397 INST(Vpmovmskb , VexRm_Lx , V(660F00,D7,_,x,I,_,_,_ ), 0 , 70 , 0 , 8345 , 310, 146), // #1300
1398 INST(Vpmovq2m , VexRm_Lx , E(F30F38,39,_,x,_,1,_,_ ), 0 , 192, 0 , 8355 , 361, 131), // #1301
1399 INST(Vpmovqb , VexMr_Lx , E(F30F38,32,_,x,_,0,1,OVM), 0 , 208, 0 , 8364 , 364, 129), // #1302
1400 INST(Vpmovqd , VexMr_Lx , E(F30F38,35,_,x,_,0,3,HVM), 0 , 207, 0 , 8372 , 363, 129), // #1303
1401 INST(Vpmovqw , VexMr_Lx , E(F30F38,34,_,x,_,0,2,QVM), 0 , 206, 0 , 8380 , 362, 129), // #1304
1402 INST(Vpmovsdb , VexMr_Lx , E(F30F38,21,_,x,_,0,2,QVM), 0 , 206, 0 , 8388 , 362, 129), // #1305
1403 INST(Vpmovsdw , VexMr_Lx , E(F30F38,23,_,x,_,0,3,HVM), 0 , 207, 0 , 8397 , 363, 129), // #1306
1404 INST(Vpmovsqb , VexMr_Lx , E(F30F38,22,_,x,_,0,1,OVM), 0 , 208, 0 , 8406 , 364, 129), // #1307
1405 INST(Vpmovsqd , VexMr_Lx , E(F30F38,25,_,x,_,0,3,HVM), 0 , 207, 0 , 8415 , 363, 129), // #1308
1406 INST(Vpmovsqw , VexMr_Lx , E(F30F38,24,_,x,_,0,2,QVM), 0 , 206, 0 , 8424 , 362, 129), // #1309
1407 INST(Vpmovswb , VexMr_Lx , E(F30F38,20,_,x,_,0,3,HVM), 0 , 207, 0 , 8433 , 363, 137), // #1310
1408 INST(Vpmovsxbd , VexRm_Lx , V(660F38,21,_,x,I,I,2,QVM), 0 , 209, 0 , 8442 , 365, 133), // #1311
1409 INST(Vpmovsxbq , VexRm_Lx , V(660F38,22,_,x,I,I,1,OVM), 0 , 210, 0 , 8452 , 366, 133), // #1312
1410 INST(Vpmovsxbw , VexRm_Lx , V(660F38,20,_,x,I,I,3,HVM), 0 , 132, 0 , 8462 , 367, 149), // #1313
1411 INST(Vpmovsxdq , VexRm_Lx , V(660F38,25,_,x,I,0,3,HVM), 0 , 132, 0 , 8472 , 367, 133), // #1314
1412 INST(Vpmovsxwd , VexRm_Lx , V(660F38,23,_,x,I,I,3,HVM), 0 , 132, 0 , 8482 , 367, 133), // #1315
1413 INST(Vpmovsxwq , VexRm_Lx , V(660F38,24,_,x,I,I,2,QVM), 0 , 209, 0 , 8492 , 365, 133), // #1316
1414 INST(Vpmovusdb , VexMr_Lx , E(F30F38,11,_,x,_,0,2,QVM), 0 , 206, 0 , 8502 , 362, 129), // #1317
1415 INST(Vpmovusdw , VexMr_Lx , E(F30F38,13,_,x,_,0,3,HVM), 0 , 207, 0 , 8512 , 363, 129), // #1318
1416 INST(Vpmovusqb , VexMr_Lx , E(F30F38,12,_,x,_,0,1,OVM), 0 , 208, 0 , 8522 , 364, 129), // #1319
1417 INST(Vpmovusqd , VexMr_Lx , E(F30F38,15,_,x,_,0,3,HVM), 0 , 207, 0 , 8532 , 363, 129), // #1320
1418 INST(Vpmovusqw , VexMr_Lx , E(F30F38,14,_,x,_,0,2,QVM), 0 , 206, 0 , 8542 , 362, 129), // #1321
1419 INST(Vpmovuswb , VexMr_Lx , E(F30F38,10,_,x,_,0,3,HVM), 0 , 207, 0 , 8552 , 363, 137), // #1322
1420 INST(Vpmovw2m , VexRm_Lx , E(F30F38,29,_,x,_,1,_,_ ), 0 , 192, 0 , 8562 , 361, 137), // #1323
1421 INST(Vpmovwb , VexMr_Lx , E(F30F38,30,_,x,_,0,3,HVM), 0 , 207, 0 , 8571 , 363, 137), // #1324
1422 INST(Vpmovzxbd , VexRm_Lx , V(660F38,31,_,x,I,I,2,QVM), 0 , 209, 0 , 8579 , 365, 133), // #1325
1423 INST(Vpmovzxbq , VexRm_Lx , V(660F38,32,_,x,I,I,1,OVM), 0 , 210, 0 , 8589 , 366, 133), // #1326
1424 INST(Vpmovzxbw , VexRm_Lx , V(660F38,30,_,x,I,I,3,HVM), 0 , 132, 0 , 8599 , 367, 149), // #1327
1425 INST(Vpmovzxdq , VexRm_Lx , V(660F38,35,_,x,I,0,3,HVM), 0 , 132, 0 , 8609 , 367, 133), // #1328
1426 INST(Vpmovzxwd , VexRm_Lx , V(660F38,33,_,x,I,I,3,HVM), 0 , 132, 0 , 8619 , 367, 133), // #1329
1427 INST(Vpmovzxwq , VexRm_Lx , V(660F38,34,_,x,I,I,2,QVM), 0 , 209, 0 , 8629 , 365, 133), // #1330
1428 INST(Vpmuldq , VexRvm_Lx , V(660F38,28,_,x,I,1,4,FV ), 0 , 200, 0 , 8639 , 204, 133), // #1331
1429 INST(Vpmulhrsw , VexRvm_Lx , V(660F38,0B,_,x,I,I,4,FVM), 0 , 109, 0 , 8647 , 290, 149), // #1332
1430 INST(Vpmulhuw , VexRvm_Lx , V(660F00,E4,_,x,I,I,4,FVM), 0 , 184, 0 , 8657 , 290, 149), // #1333
1431 INST(Vpmulhw , VexRvm_Lx , V(660F00,E5,_,x,I,I,4,FVM), 0 , 184, 0 , 8666 , 290, 149), // #1334
1432 INST(Vpmulld , VexRvm_Lx , V(660F38,40,_,x,I,0,4,FV ), 0 , 163, 0 , 8674 , 205, 133), // #1335
1433 INST(Vpmullq , VexRvm_Lx , E(660F38,40,_,x,_,1,4,FV ), 0 , 112, 0 , 8682 , 208, 131), // #1336
1434 INST(Vpmullw , VexRvm_Lx , V(660F00,D5,_,x,I,I,4,FVM), 0 , 184, 0 , 8690 , 290, 149), // #1337
1435 INST(Vpmultishiftqb , VexRvm_Lx , E(660F38,83,_,x,_,1,4,FV ), 0 , 112, 0 , 8698 , 208, 156), // #1338
1436 INST(Vpmuludq , VexRvm_Lx , V(660F00,F4,_,x,I,1,4,FV ), 0 , 104, 0 , 8713 , 204, 133), // #1339
1437 INST(Vpopcntb , VexRm_Lx , E(660F38,54,_,x,_,0,4,FV ), 0 , 113, 0 , 8722 , 259, 160), // #1340
1438 INST(Vpopcntd , VexRm_Lx , E(660F38,55,_,x,_,0,4,FVM), 0 , 189, 0 , 8731 , 344, 161), // #1341
1439 INST(Vpopcntq , VexRm_Lx , E(660F38,55,_,x,_,1,4,FVM), 0 , 190, 0 , 8740 , 358, 161), // #1342
1440 INST(Vpopcntw , VexRm_Lx , E(660F38,54,_,x,_,1,4,FV ), 0 , 112, 0 , 8749 , 259, 160), // #1343
1441 INST(Vpor , VexRvm_Lx , V(660F00,EB,_,x,I,_,_,_ ), 0 , 70 , 0 , 8758 , 321, 146), // #1344
1442 INST(Vpord , VexRvm_Lx , E(660F00,EB,_,x,_,0,4,FV ), 0 , 188, 0 , 8763 , 322, 129), // #1345
1443 INST(Vporq , VexRvm_Lx , E(660F00,EB,_,x,_,1,4,FV ), 0 , 130, 0 , 8769 , 326, 129), // #1346
1444 INST(Vpperm , VexRvrmRvmr , V(XOP_M8,A3,_,0,x,_,_,_ ), 0 , 195, 0 , 8775 , 368, 142), // #1347
1445 INST(Vprold , VexVmi_Lx , E(660F00,72,1,x,_,0,4,FV ), 0 , 211, 0 , 8782 , 369, 129), // #1348
1446 INST(Vprolq , VexVmi_Lx , E(660F00,72,1,x,_,1,4,FV ), 0 , 212, 0 , 8789 , 370, 129), // #1349
1447 INST(Vprolvd , VexRvm_Lx , E(660F38,15,_,x,_,0,4,FV ), 0 , 113, 0 , 8796 , 209, 129), // #1350
1448 INST(Vprolvq , VexRvm_Lx , E(660F38,15,_,x,_,1,4,FV ), 0 , 112, 0 , 8804 , 208, 129), // #1351
1449 INST(Vprord , VexVmi_Lx , E(660F00,72,0,x,_,0,4,FV ), 0 , 188, 0 , 8812 , 369, 129), // #1352
1450 INST(Vprorq , VexVmi_Lx , E(660F00,72,0,x,_,1,4,FV ), 0 , 130, 0 , 8819 , 370, 129), // #1353
1451 INST(Vprorvd , VexRvm_Lx , E(660F38,14,_,x,_,0,4,FV ), 0 , 113, 0 , 8826 , 209, 129), // #1354
1452 INST(Vprorvq , VexRvm_Lx , E(660F38,14,_,x,_,1,4,FV ), 0 , 112, 0 , 8834 , 208, 129), // #1355
1453 INST(Vprotb , VexRvmRmvRmi , V(XOP_M9,90,_,0,x,_,_,_ ), V(XOP_M8,C0,_,0,x,_,_,_ ), 80 , 121, 8842 , 371, 142), // #1356
1454 INST(Vprotd , VexRvmRmvRmi , V(XOP_M9,92,_,0,x,_,_,_ ), V(XOP_M8,C2,_,0,x,_,_,_ ), 80 , 122, 8849 , 371, 142), // #1357
1455 INST(Vprotq , VexRvmRmvRmi , V(XOP_M9,93,_,0,x,_,_,_ ), V(XOP_M8,C3,_,0,x,_,_,_ ), 80 , 123, 8856 , 371, 142), // #1358
1456 INST(Vprotw , VexRvmRmvRmi , V(XOP_M9,91,_,0,x,_,_,_ ), V(XOP_M8,C1,_,0,x,_,_,_ ), 80 , 124, 8863 , 371, 142), // #1359
1457 INST(Vpsadbw , VexRvm_Lx , V(660F00,F6,_,x,I,I,4,FVM), 0 , 184, 0 , 8870 , 199, 149), // #1360
1458 INST(Vpscatterdd , VexMr_VM , E(660F38,A0,_,x,_,0,2,T1S), 0 , 125, 0 , 8878 , 372, 129), // #1361
1459 INST(Vpscatterdq , VexMr_VM , E(660F38,A0,_,x,_,1,3,T1S), 0 , 124, 0 , 8890 , 373, 129), // #1362
1460 INST(Vpscatterqd , VexMr_VM , E(660F38,A1,_,x,_,0,2,T1S), 0 , 125, 0 , 8902 , 374, 129), // #1363
1461 INST(Vpscatterqq , VexMr_VM , E(660F38,A1,_,x,_,1,3,T1S), 0 , 124, 0 , 8914 , 375, 129), // #1364
1462 INST(Vpshab , VexRvmRmv , V(XOP_M9,98,_,0,x,_,_,_ ), 0 , 80 , 0 , 8926 , 376, 142), // #1365
1463 INST(Vpshad , VexRvmRmv , V(XOP_M9,9A,_,0,x,_,_,_ ), 0 , 80 , 0 , 8933 , 376, 142), // #1366
1464 INST(Vpshaq , VexRvmRmv , V(XOP_M9,9B,_,0,x,_,_,_ ), 0 , 80 , 0 , 8940 , 376, 142), // #1367
1465 INST(Vpshaw , VexRvmRmv , V(XOP_M9,99,_,0,x,_,_,_ ), 0 , 80 , 0 , 8947 , 376, 142), // #1368
1466 INST(Vpshlb , VexRvmRmv , V(XOP_M9,94,_,0,x,_,_,_ ), 0 , 80 , 0 , 8954 , 376, 142), // #1369
1467 INST(Vpshld , VexRvmRmv , V(XOP_M9,96,_,0,x,_,_,_ ), 0 , 80 , 0 , 8961 , 376, 142), // #1370
1468 INST(Vpshldd , VexRvmi_Lx , E(660F3A,71,_,x,_,0,4,FV ), 0 , 110, 0 , 8968 , 202, 154), // #1371
1469 INST(Vpshldq , VexRvmi_Lx , E(660F3A,71,_,x,_,1,4,FV ), 0 , 111, 0 , 8976 , 203, 154), // #1372
1470 INST(Vpshldvd , VexRvm_Lx , E(660F38,71,_,x,_,0,4,FV ), 0 , 113, 0 , 8984 , 209, 154), // #1373
1471 INST(Vpshldvq , VexRvm_Lx , E(660F38,71,_,x,_,1,4,FV ), 0 , 112, 0 , 8993 , 208, 154), // #1374
1472 INST(Vpshldvw , VexRvm_Lx , E(660F38,70,_,x,_,1,4,FVM), 0 , 190, 0 , 9002 , 327, 154), // #1375
1473 INST(Vpshldw , VexRvmi_Lx , E(660F3A,70,_,x,_,1,4,FVM), 0 , 197, 0 , 9011 , 255, 154), // #1376
1474 INST(Vpshlq , VexRvmRmv , V(XOP_M9,97,_,0,x,_,_,_ ), 0 , 80 , 0 , 9019 , 376, 142), // #1377
1475 INST(Vpshlw , VexRvmRmv , V(XOP_M9,95,_,0,x,_,_,_ ), 0 , 80 , 0 , 9026 , 376, 142), // #1378
1476 INST(Vpshrdd , VexRvmi_Lx , E(660F3A,73,_,x,_,0,4,FV ), 0 , 110, 0 , 9033 , 202, 154), // #1379
1477 INST(Vpshrdq , VexRvmi_Lx , E(660F3A,73,_,x,_,1,4,FV ), 0 , 111, 0 , 9041 , 203, 154), // #1380
1478 INST(Vpshrdvd , VexRvm_Lx , E(660F38,73,_,x,_,0,4,FV ), 0 , 113, 0 , 9049 , 209, 154), // #1381
1479 INST(Vpshrdvq , VexRvm_Lx , E(660F38,73,_,x,_,1,4,FV ), 0 , 112, 0 , 9058 , 208, 154), // #1382
1480 INST(Vpshrdvw , VexRvm_Lx , E(660F38,72,_,x,_,1,4,FVM), 0 , 190, 0 , 9067 , 327, 154), // #1383
1481 INST(Vpshrdw , VexRvmi_Lx , E(660F3A,72,_,x,_,1,4,FVM), 0 , 197, 0 , 9076 , 255, 154), // #1384
1482 INST(Vpshufb , VexRvm_Lx , V(660F38,00,_,x,I,I,4,FVM), 0 , 109, 0 , 9084 , 290, 149), // #1385
1483 INST(Vpshufbitqmb , VexRvm_Lx , E(660F38,8F,_,x,0,0,4,FVM), 0 , 189, 0 , 9092 , 377, 160), // #1386
1484 INST(Vpshufd , VexRmi_Lx , V(660F00,70,_,x,I,0,4,FV ), 0 , 133, 0 , 9105 , 378, 133), // #1387
1485 INST(Vpshufhw , VexRmi_Lx , V(F30F00,70,_,x,I,I,4,FVM), 0 , 185, 0 , 9113 , 379, 149), // #1388
1486 INST(Vpshuflw , VexRmi_Lx , V(F20F00,70,_,x,I,I,4,FVM), 0 , 213, 0 , 9122 , 379, 149), // #1389
1487 INST(Vpsignb , VexRvm_Lx , V(660F38,08,_,x,I,_,_,_ ), 0 , 97 , 0 , 9131 , 198, 146), // #1390
1488 INST(Vpsignd , VexRvm_Lx , V(660F38,0A,_,x,I,_,_,_ ), 0 , 97 , 0 , 9139 , 198, 146), // #1391
1489 INST(Vpsignw , VexRvm_Lx , V(660F38,09,_,x,I,_,_,_ ), 0 , 97 , 0 , 9147 , 198, 146), // #1392
1490 INST(Vpslld , VexRvmVmi_Lx_MEvex , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 214, 125, 9155 , 380, 133), // #1393
1491 INST(Vpslldq , VexVmi_Lx_MEvex , V(660F00,73,7,x,I,I,4,FVM), 0 , 215, 0 , 9162 , 381, 149), // #1394
1492 INST(Vpsllq , VexRvmVmi_Lx_MEvex , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 216, 126, 9170 , 382, 133), // #1395
1493 INST(Vpsllvd , VexRvm_Lx , V(660F38,47,_,x,0,0,4,FV ), 0 , 163, 0 , 9177 , 205, 143), // #1396
1494 INST(Vpsllvq , VexRvm_Lx , V(660F38,47,_,x,1,1,4,FV ), 0 , 162, 0 , 9185 , 204, 143), // #1397
1495 INST(Vpsllvw , VexRvm_Lx , E(660F38,12,_,x,_,1,4,FVM), 0 , 190, 0 , 9193 , 327, 137), // #1398
1496 INST(Vpsllw , VexRvmVmi_Lx_MEvex , V(660F00,F1,_,x,I,I,4,128), V(660F00,71,6,x,I,I,4,FVM), 214, 127, 9201 , 383, 149), // #1399
1497 INST(Vpsrad , VexRvmVmi_Lx_MEvex , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 214, 128, 9208 , 380, 133), // #1400
1498 INST(Vpsraq , VexRvmVmi_Lx_MEvex , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 217, 129, 9215 , 384, 129), // #1401
1499 INST(Vpsravd , VexRvm_Lx , V(660F38,46,_,x,0,0,4,FV ), 0 , 163, 0 , 9222 , 205, 143), // #1402
1500 INST(Vpsravq , VexRvm_Lx , E(660F38,46,_,x,_,1,4,FV ), 0 , 112, 0 , 9230 , 208, 129), // #1403
1501 INST(Vpsravw , VexRvm_Lx , E(660F38,11,_,x,_,1,4,FVM), 0 , 190, 0 , 9238 , 327, 137), // #1404
1502 INST(Vpsraw , VexRvmVmi_Lx_MEvex , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 214, 130, 9246 , 383, 149), // #1405
1503 INST(Vpsrld , VexRvmVmi_Lx_MEvex , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 214, 131, 9253 , 380, 133), // #1406
1504 INST(Vpsrldq , VexVmi_Lx_MEvex , V(660F00,73,3,x,I,I,4,FVM), 0 , 218, 0 , 9260 , 381, 149), // #1407
1505 INST(Vpsrlq , VexRvmVmi_Lx_MEvex , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 216, 132, 9268 , 382, 133), // #1408
1506 INST(Vpsrlvd , VexRvm_Lx , V(660F38,45,_,x,0,0,4,FV ), 0 , 163, 0 , 9275 , 205, 143), // #1409
1507 INST(Vpsrlvq , VexRvm_Lx , V(660F38,45,_,x,1,1,4,FV ), 0 , 162, 0 , 9283 , 204, 143), // #1410
1508 INST(Vpsrlvw , VexRvm_Lx , E(660F38,10,_,x,_,1,4,FVM), 0 , 190, 0 , 9291 , 327, 137), // #1411
1509 INST(Vpsrlw , VexRvmVmi_Lx_MEvex , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 214, 133, 9299 , 383, 149), // #1412
1510 INST(Vpsubb , VexRvm_Lx , V(660F00,F8,_,x,I,I,4,FVM), 0 , 184, 0 , 9306 , 385, 149), // #1413
1511 INST(Vpsubd , VexRvm_Lx , V(660F00,FA,_,x,I,0,4,FV ), 0 , 133, 0 , 9313 , 386, 133), // #1414
1512 INST(Vpsubq , VexRvm_Lx , V(660F00,FB,_,x,I,1,4,FV ), 0 , 104, 0 , 9320 , 387, 133), // #1415
1513 INST(Vpsubsb , VexRvm_Lx , V(660F00,E8,_,x,I,I,4,FVM), 0 , 184, 0 , 9327 , 385, 149), // #1416
1514 INST(Vpsubsw , VexRvm_Lx , V(660F00,E9,_,x,I,I,4,FVM), 0 , 184, 0 , 9335 , 385, 149), // #1417
1515 INST(Vpsubusb , VexRvm_Lx , V(660F00,D8,_,x,I,I,4,FVM), 0 , 184, 0 , 9343 , 385, 149), // #1418
1516 INST(Vpsubusw , VexRvm_Lx , V(660F00,D9,_,x,I,I,4,FVM), 0 , 184, 0 , 9352 , 385, 149), // #1419
1517 INST(Vpsubw , VexRvm_Lx , V(660F00,F9,_,x,I,I,4,FVM), 0 , 184, 0 , 9361 , 385, 149), // #1420
1518 INST(Vpternlogd , VexRvmi_Lx , E(660F3A,25,_,x,_,0,4,FV ), 0 , 110, 0 , 9368 , 202, 129), // #1421
1519 INST(Vpternlogq , VexRvmi_Lx , E(660F3A,25,_,x,_,1,4,FV ), 0 , 111, 0 , 9379 , 203, 129), // #1422
1520 INST(Vptest , VexRm_Lx , V(660F38,17,_,x,I,_,_,_ ), 0 , 97 , 0 , 9390 , 275, 153), // #1423
1521 INST(Vptestmb , VexRvm_Lx , E(660F38,26,_,x,_,0,4,FVM), 0 , 189, 0 , 9397 , 377, 137), // #1424
1522 INST(Vptestmd , VexRvm_Lx , E(660F38,27,_,x,_,0,4,FV ), 0 , 113, 0 , 9406 , 388, 129), // #1425
1523 INST(Vptestmq , VexRvm_Lx , E(660F38,27,_,x,_,1,4,FV ), 0 , 112, 0 , 9415 , 389, 129), // #1426
1524 INST(Vptestmw , VexRvm_Lx , E(660F38,26,_,x,_,1,4,FVM), 0 , 190, 0 , 9424 , 377, 137), // #1427
1525 INST(Vptestnmb , VexRvm_Lx , E(F30F38,26,_,x,_,0,4,FVM), 0 , 219, 0 , 9433 , 377, 137), // #1428
1526 INST(Vptestnmd , VexRvm_Lx , E(F30F38,27,_,x,_,0,4,FV ), 0 , 128, 0 , 9443 , 388, 129), // #1429
1527 INST(Vptestnmq , VexRvm_Lx , E(F30F38,27,_,x,_,1,4,FV ), 0 , 220, 0 , 9453 , 389, 129), // #1430
1528 INST(Vptestnmw , VexRvm_Lx , E(F30F38,26,_,x,_,1,4,FVM), 0 , 221, 0 , 9463 , 377, 137), // #1431
1529 INST(Vpunpckhbw , VexRvm_Lx , V(660F00,68,_,x,I,I,4,FVM), 0 , 184, 0 , 9473 , 290, 149), // #1432
1530 INST(Vpunpckhdq , VexRvm_Lx , V(660F00,6A,_,x,I,0,4,FV ), 0 , 133, 0 , 9484 , 205, 133), // #1433
1531 INST(Vpunpckhqdq , VexRvm_Lx , V(660F00,6D,_,x,I,1,4,FV ), 0 , 104, 0 , 9495 , 204, 133), // #1434
1532 INST(Vpunpckhwd , VexRvm_Lx , V(660F00,69,_,x,I,I,4,FVM), 0 , 184, 0 , 9507 , 290, 149), // #1435
1533 INST(Vpunpcklbw , VexRvm_Lx , V(660F00,60,_,x,I,I,4,FVM), 0 , 184, 0 , 9518 , 290, 149), // #1436
1534 INST(Vpunpckldq , VexRvm_Lx , V(660F00,62,_,x,I,0,4,FV ), 0 , 133, 0 , 9529 , 205, 133), // #1437
1535 INST(Vpunpcklqdq , VexRvm_Lx , V(660F00,6C,_,x,I,1,4,FV ), 0 , 104, 0 , 9540 , 204, 133), // #1438
1536 INST(Vpunpcklwd , VexRvm_Lx , V(660F00,61,_,x,I,I,4,FVM), 0 , 184, 0 , 9552 , 290, 149), // #1439
1537 INST(Vpxor , VexRvm_Lx , V(660F00,EF,_,x,I,_,_,_ ), 0 , 70 , 0 , 9563 , 323, 146), // #1440
1538 INST(Vpxord , VexRvm_Lx , E(660F00,EF,_,x,_,0,4,FV ), 0 , 188, 0 , 9569 , 324, 129), // #1441
1539 INST(Vpxorq , VexRvm_Lx , E(660F00,EF,_,x,_,1,4,FV ), 0 , 130, 0 , 9576 , 325, 129), // #1442
1540 INST(Vrangepd , VexRvmi_Lx , E(660F3A,50,_,x,_,1,4,FV ), 0 , 111, 0 , 9583 , 264, 131), // #1443
1541 INST(Vrangeps , VexRvmi_Lx , E(660F3A,50,_,x,_,0,4,FV ), 0 , 110, 0 , 9592 , 265, 131), // #1444
1542 INST(Vrangesd , VexRvmi , E(660F3A,51,_,I,_,1,3,T1S), 0 , 160, 0 , 9601 , 266, 66 ), // #1445
1543 INST(Vrangess , VexRvmi , E(660F3A,51,_,I,_,0,2,T1S), 0 , 161, 0 , 9610 , 267, 66 ), // #1446
1544 INST(Vrcp14pd , VexRm_Lx , E(660F38,4C,_,x,_,1,4,FV ), 0 , 112, 0 , 9619 , 358, 129), // #1447
1545 INST(Vrcp14ps , VexRm_Lx , E(660F38,4C,_,x,_,0,4,FV ), 0 , 113, 0 , 9628 , 344, 129), // #1448
1546 INST(Vrcp14sd , VexRvm , E(660F38,4D,_,I,_,1,3,T1S), 0 , 124, 0 , 9637 , 390, 68 ), // #1449
1547 INST(Vrcp14ss , VexRvm , E(660F38,4D,_,I,_,0,2,T1S), 0 , 125, 0 , 9646 , 391, 68 ), // #1450
1548 INST(Vrcp28pd , VexRm , E(660F38,CA,_,2,_,1,4,FV ), 0 , 152, 0 , 9655 , 257, 138), // #1451
1549 INST(Vrcp28ps , VexRm , E(660F38,CA,_,2,_,0,4,FV ), 0 , 153, 0 , 9664 , 258, 138), // #1452
1550 INST(Vrcp28sd , VexRvm , E(660F38,CB,_,I,_,1,3,T1S), 0 , 124, 0 , 9673 , 285, 138), // #1453
1551 INST(Vrcp28ss , VexRvm , E(660F38,CB,_,I,_,0,2,T1S), 0 , 125, 0 , 9682 , 286, 138), // #1454
1552 INST(Vrcpps , VexRm_Lx , V(000F00,53,_,x,I,_,_,_ ), 0 , 73 , 0 , 9691 , 275, 126), // #1455
1553 INST(Vrcpss , VexRvm , V(F30F00,53,_,I,I,_,_,_ ), 0 , 178, 0 , 9698 , 392, 126), // #1456
1554 INST(Vreducepd , VexRmi_Lx , E(660F3A,56,_,x,_,1,4,FV ), 0 , 111, 0 , 9705 , 370, 131), // #1457
1555 INST(Vreduceps , VexRmi_Lx , E(660F3A,56,_,x,_,0,4,FV ), 0 , 110, 0 , 9715 , 369, 131), // #1458
1556 INST(Vreducesd , VexRvmi , E(660F3A,57,_,I,_,1,3,T1S), 0 , 160, 0 , 9725 , 393, 66 ), // #1459
1557 INST(Vreducess , VexRvmi , E(660F3A,57,_,I,_,0,2,T1S), 0 , 161, 0 , 9735 , 394, 66 ), // #1460
1558 INST(Vrndscalepd , VexRmi_Lx , E(660F3A,09,_,x,_,1,4,FV ), 0 , 111, 0 , 9745 , 287, 129), // #1461
1559 INST(Vrndscaleps , VexRmi_Lx , E(660F3A,08,_,x,_,0,4,FV ), 0 , 110, 0 , 9757 , 288, 129), // #1462
1560 INST(Vrndscalesd , VexRvmi , E(660F3A,0B,_,I,_,1,3,T1S), 0 , 160, 0 , 9769 , 266, 68 ), // #1463
1561 INST(Vrndscaless , VexRvmi , E(660F3A,0A,_,I,_,0,2,T1S), 0 , 161, 0 , 9781 , 267, 68 ), // #1464
1562 INST(Vroundpd , VexRmi_Lx , V(660F3A,09,_,x,I,_,_,_ ), 0 , 74 , 0 , 9793 , 395, 126), // #1465
1563 INST(Vroundps , VexRmi_Lx , V(660F3A,08,_,x,I,_,_,_ ), 0 , 74 , 0 , 9802 , 395, 126), // #1466
1564 INST(Vroundsd , VexRvmi , V(660F3A,0B,_,I,I,_,_,_ ), 0 , 74 , 0 , 9811 , 396, 126), // #1467
1565 INST(Vroundss , VexRvmi , V(660F3A,0A,_,I,I,_,_,_ ), 0 , 74 , 0 , 9820 , 397, 126), // #1468
1566 INST(Vrsqrt14pd , VexRm_Lx , E(660F38,4E,_,x,_,1,4,FV ), 0 , 112, 0 , 9829 , 358, 129), // #1469
1567 INST(Vrsqrt14ps , VexRm_Lx , E(660F38,4E,_,x,_,0,4,FV ), 0 , 113, 0 , 9840 , 344, 129), // #1470
1568 INST(Vrsqrt14sd , VexRvm , E(660F38,4F,_,I,_,1,3,T1S), 0 , 124, 0 , 9851 , 390, 68 ), // #1471
1569 INST(Vrsqrt14ss , VexRvm , E(660F38,4F,_,I,_,0,2,T1S), 0 , 125, 0 , 9862 , 391, 68 ), // #1472
1570 INST(Vrsqrt28pd , VexRm , E(660F38,CC,_,2,_,1,4,FV ), 0 , 152, 0 , 9873 , 257, 138), // #1473
1571 INST(Vrsqrt28ps , VexRm , E(660F38,CC,_,2,_,0,4,FV ), 0 , 153, 0 , 9884 , 258, 138), // #1474
1572 INST(Vrsqrt28sd , VexRvm , E(660F38,CD,_,I,_,1,3,T1S), 0 , 124, 0 , 9895 , 285, 138), // #1475
1573 INST(Vrsqrt28ss , VexRvm , E(660F38,CD,_,I,_,0,2,T1S), 0 , 125, 0 , 9906 , 286, 138), // #1476
1574 INST(Vrsqrtps , VexRm_Lx , V(000F00,52,_,x,I,_,_,_ ), 0 , 73 , 0 , 9917 , 275, 126), // #1477
1575 INST(Vrsqrtss , VexRvm , V(F30F00,52,_,I,I,_,_,_ ), 0 , 178, 0 , 9926 , 392, 126), // #1478
1576 INST(Vscalefpd , VexRvm_Lx , E(660F38,2C,_,x,_,1,4,FV ), 0 , 112, 0 , 9935 , 398, 129), // #1479
1577 INST(Vscalefps , VexRvm_Lx , E(660F38,2C,_,x,_,0,4,FV ), 0 , 113, 0 , 9945 , 399, 129), // #1480
1578 INST(Vscalefsd , VexRvm , E(660F38,2D,_,I,_,1,3,T1S), 0 , 124, 0 , 9955 , 400, 68 ), // #1481
1579 INST(Vscalefss , VexRvm , E(660F38,2D,_,I,_,0,2,T1S), 0 , 125, 0 , 9965 , 401, 68 ), // #1482
1580 INST(Vscatterdpd , VexMr_VM , E(660F38,A2,_,x,_,1,3,T1S), 0 , 124, 0 , 9975 , 373, 129), // #1483
1581 INST(Vscatterdps , VexMr_VM , E(660F38,A2,_,x,_,0,2,T1S), 0 , 125, 0 , 9987 , 372, 129), // #1484
1582 INST(Vscatterpf0dpd , VexM_VM , E(660F38,C6,5,2,_,1,3,T1S), 0 , 222, 0 , 9999 , 280, 144), // #1485
1583 INST(Vscatterpf0dps , VexM_VM , E(660F38,C6,5,2,_,0,2,T1S), 0 , 223, 0 , 10014, 281, 144), // #1486
1584 INST(Vscatterpf0qpd , VexM_VM , E(660F38,C7,5,2,_,1,3,T1S), 0 , 222, 0 , 10029, 282, 144), // #1487
1585 INST(Vscatterpf0qps , VexM_VM , E(660F38,C7,5,2,_,0,2,T1S), 0 , 223, 0 , 10044, 282, 144), // #1488
1586 INST(Vscatterpf1dpd , VexM_VM , E(660F38,C6,6,2,_,1,3,T1S), 0 , 224, 0 , 10059, 280, 144), // #1489
1587 INST(Vscatterpf1dps , VexM_VM , E(660F38,C6,6,2,_,0,2,T1S), 0 , 225, 0 , 10074, 281, 144), // #1490
1588 INST(Vscatterpf1qpd , VexM_VM , E(660F38,C7,6,2,_,1,3,T1S), 0 , 224, 0 , 10089, 282, 144), // #1491
1589 INST(Vscatterpf1qps , VexM_VM , E(660F38,C7,6,2,_,0,2,T1S), 0 , 225, 0 , 10104, 282, 144), // #1492
1590 INST(Vscatterqpd , VexMr_VM , E(660F38,A3,_,x,_,1,3,T1S), 0 , 124, 0 , 10119, 375, 129), // #1493
1591 INST(Vscatterqps , VexMr_VM , E(660F38,A3,_,x,_,0,2,T1S), 0 , 125, 0 , 10131, 374, 129), // #1494
1592 INST(Vshuff32x4 , VexRvmi_Lx , E(660F3A,23,_,x,_,0,4,FV ), 0 , 110, 0 , 10143, 402, 129), // #1495
1593 INST(Vshuff64x2 , VexRvmi_Lx , E(660F3A,23,_,x,_,1,4,FV ), 0 , 111, 0 , 10154, 403, 129), // #1496
1594 INST(Vshufi32x4 , VexRvmi_Lx , E(660F3A,43,_,x,_,0,4,FV ), 0 , 110, 0 , 10165, 402, 129), // #1497
1595 INST(Vshufi64x2 , VexRvmi_Lx , E(660F3A,43,_,x,_,1,4,FV ), 0 , 111, 0 , 10176, 403, 129), // #1498
1596 INST(Vshufpd , VexRvmi_Lx , V(660F00,C6,_,x,I,1,4,FV ), 0 , 104, 0 , 10187, 404, 124), // #1499
1597 INST(Vshufps , VexRvmi_Lx , V(000F00,C6,_,x,I,0,4,FV ), 0 , 105, 0 , 10195, 405, 124), // #1500
1598 INST(Vsqrtpd , VexRm_Lx , V(660F00,51,_,x,I,1,4,FV ), 0 , 104, 0 , 10203, 406, 124), // #1501
1599 INST(Vsqrtps , VexRm_Lx , V(000F00,51,_,x,I,0,4,FV ), 0 , 105, 0 , 10211, 227, 124), // #1502
1600 INST(Vsqrtsd , VexRvm , V(F20F00,51,_,I,I,1,3,T1S), 0 , 106, 0 , 10219, 196, 125), // #1503
1601 INST(Vsqrtss , VexRvm , V(F30F00,51,_,I,I,0,2,T1S), 0 , 107, 0 , 10227, 197, 125), // #1504
1602 INST(Vstmxcsr , VexM , V(000F00,AE,3,0,I,_,_,_ ), 0 , 226, 0 , 10235, 296, 126), // #1505
1603 INST(Vsubpd , VexRvm_Lx , V(660F00,5C,_,x,I,1,4,FV ), 0 , 104, 0 , 10244, 194, 124), // #1506
1604 INST(Vsubps , VexRvm_Lx , V(000F00,5C,_,x,I,0,4,FV ), 0 , 105, 0 , 10251, 195, 124), // #1507
1605 INST(Vsubsd , VexRvm , V(F20F00,5C,_,I,I,1,3,T1S), 0 , 106, 0 , 10258, 196, 125), // #1508
1606 INST(Vsubss , VexRvm , V(F30F00,5C,_,I,I,0,2,T1S), 0 , 107, 0 , 10265, 197, 125), // #1509
1607 INST(Vtestpd , VexRm_Lx , V(660F38,0F,_,x,0,_,_,_ ), 0 , 97 , 0 , 10272, 275, 153), // #1510
1608 INST(Vtestps , VexRm_Lx , V(660F38,0E,_,x,0,_,_,_ ), 0 , 97 , 0 , 10280, 275, 153), // #1511
1609 INST(Vucomisd , VexRm , V(660F00,2E,_,I,I,1,3,T1S), 0 , 122, 0 , 10288, 223, 134), // #1512
1610 INST(Vucomiss , VexRm , V(000F00,2E,_,I,I,0,2,T1S), 0 , 123, 0 , 10297, 224, 134), // #1513
1611 INST(Vunpckhpd , VexRvm_Lx , V(660F00,15,_,x,I,1,4,FV ), 0 , 104, 0 , 10306, 204, 124), // #1514
1612 INST(Vunpckhps , VexRvm_Lx , V(000F00,15,_,x,I,0,4,FV ), 0 , 105, 0 , 10316, 205, 124), // #1515
1613 INST(Vunpcklpd , VexRvm_Lx , V(660F00,14,_,x,I,1,4,FV ), 0 , 104, 0 , 10326, 204, 124), // #1516
1614 INST(Vunpcklps , VexRvm_Lx , V(000F00,14,_,x,I,0,4,FV ), 0 , 105, 0 , 10336, 205, 124), // #1517
1615 INST(Vxorpd , VexRvm_Lx , V(660F00,57,_,x,I,1,4,FV ), 0 , 104, 0 , 10346, 387, 130), // #1518
1616 INST(Vxorps , VexRvm_Lx , V(000F00,57,_,x,I,0,4,FV ), 0 , 105, 0 , 10353, 386, 130), // #1519
1617 INST(Vzeroall , VexOp , V(000F00,77,_,1,I,_,_,_ ), 0 , 69 , 0 , 10360, 407, 126), // #1520
1618 INST(Vzeroupper , VexOp , V(000F00,77,_,0,I,_,_,_ ), 0 , 73 , 0 , 10369, 407, 126), // #1521
1619 INST(Wbinvd , X86Op , O(000F00,09,_,_,_,_,_,_ ), 0 , 4 , 0 , 10380, 30 , 0 ), // #1522
1620 INST(Wbnoinvd , X86Op , O(F30F00,09,_,_,_,_,_,_ ), 0 , 6 , 0 , 10387, 30 , 162), // #1523
1621 INST(Wrfsbase , X86M , O(F30F00,AE,2,_,x,_,_,_ ), 0 , 227, 0 , 10396, 171, 104), // #1524
1622 INST(Wrgsbase , X86M , O(F30F00,AE,3,_,x,_,_,_ ), 0 , 228, 0 , 10405, 171, 104), // #1525
1623 INST(Wrmsr , X86Op , O(000F00,30,_,_,_,_,_,_ ), 0 , 4 , 0 , 10414, 172, 105), // #1526
1624 INST(Wrssd , X86Mr , O(000F38,F6,_,_,_,_,_,_ ), 0 , 84 , 0 , 10420, 408, 56 ), // #1527
1625 INST(Wrssq , X86Mr , O(000F38,F6,_,_,1,_,_,_ ), 0 , 229, 0 , 10426, 409, 56 ), // #1528
1626 INST(Wrussd , X86Mr , O(660F38,F5,_,_,_,_,_,_ ), 0 , 2 , 0 , 10432, 408, 56 ), // #1529
1627 INST(Wrussq , X86Mr , O(660F38,F5,_,_,1,_,_,_ ), 0 , 230, 0 , 10439, 409, 56 ), // #1530
1628 INST(Xabort , X86Op_Mod11RM_I8 , O(000000,C6,7,_,_,_,_,_ ), 0 , 27 , 0 , 10446, 79 , 163), // #1531
1629 INST(Xadd , X86Xadd , O(000F00,C0,_,_,x,_,_,_ ), 0 , 4 , 0 , 10453, 410, 38 ), // #1532
1630 INST(Xbegin , X86JmpRel , O(000000,C7,7,_,_,_,_,_ ), 0 , 27 , 0 , 10458, 411, 163), // #1533
1631 INST(Xchg , X86Xchg , O(000000,86,_,_,x,_,_,_ ), 0 , 0 , 0 , 462 , 412, 0 ), // #1534
1632 INST(Xend , X86Op , O(000F01,D5,_,_,_,_,_,_ ), 0 , 21 , 0 , 10465, 30 , 163), // #1535
1633 INST(Xgetbv , X86Op , O(000F01,D0,_,_,_,_,_,_ ), 0 , 21 , 0 , 10470, 172, 164), // #1536
1634 INST(Xlatb , X86Op , O(000000,D7,_,_,_,_,_,_ ), 0 , 0 , 0 , 10477, 30 , 0 ), // #1537
1635 INST(Xor , X86Arith , O(000000,30,6,_,x,_,_,_ ), 0 , 32 , 0 , 9565 , 177, 1 ), // #1538
1636 INST(Xorpd , ExtRm , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 10347, 149, 4 ), // #1539
1637 INST(Xorps , ExtRm , O(000F00,57,_,_,_,_,_,_ ), 0 , 4 , 0 , 10354, 149, 5 ), // #1540
1638 INST(Xresldtrk , X86Op , O(F20F01,E9,_,_,_,_,_,_ ), 0 , 93 , 0 , 10483, 30 , 165), // #1541
1639 INST(Xrstor , X86M_Only_EDX_EAX , O(000F00,AE,5,_,_,_,_,_ ), 0 , 78 , 0 , 1164 , 413, 164), // #1542
1640 INST(Xrstor64 , X86M_Only_EDX_EAX , O(000F00,AE,5,_,1,_,_,_ ), 0 , 231, 0 , 1172 , 414, 164), // #1543
1641 INST(Xrstors , X86M_Only_EDX_EAX , O(000F00,C7,3,_,_,_,_,_ ), 0 , 79 , 0 , 10493, 413, 166), // #1544
1642 INST(Xrstors64 , X86M_Only_EDX_EAX , O(000F00,C7,3,_,1,_,_,_ ), 0 , 232, 0 , 10501, 414, 166), // #1545
1643 INST(Xsave , X86M_Only_EDX_EAX , O(000F00,AE,4,_,_,_,_,_ ), 0 , 98 , 0 , 1182 , 413, 164), // #1546
1644 INST(Xsave64 , X86M_Only_EDX_EAX , O(000F00,AE,4,_,1,_,_,_ ), 0 , 233, 0 , 1189 , 414, 164), // #1547
1645 INST(Xsavec , X86M_Only_EDX_EAX , O(000F00,C7,4,_,_,_,_,_ ), 0 , 98 , 0 , 10511, 413, 167), // #1548
1646 INST(Xsavec64 , X86M_Only_EDX_EAX , O(000F00,C7,4,_,1,_,_,_ ), 0 , 233, 0 , 10518, 414, 167), // #1549
1647 INST(Xsaveopt , X86M_Only_EDX_EAX , O(000F00,AE,6,_,_,_,_,_ ), 0 , 81 , 0 , 10527, 413, 168), // #1550
1648 INST(Xsaveopt64 , X86M_Only_EDX_EAX , O(000F00,AE,6,_,1,_,_,_ ), 0 , 234, 0 , 10536, 414, 168), // #1551
1649 INST(Xsaves , X86M_Only_EDX_EAX , O(000F00,C7,5,_,_,_,_,_ ), 0 , 78 , 0 , 10547, 413, 166), // #1552
1650 INST(Xsaves64 , X86M_Only_EDX_EAX , O(000F00,C7,5,_,1,_,_,_ ), 0 , 231, 0 , 10554, 414, 166), // #1553
1651 INST(Xsetbv , X86Op , O(000F01,D1,_,_,_,_,_,_ ), 0 , 21 , 0 , 10563, 172, 164), // #1554
1652 INST(Xsusldtrk , X86Op , O(F20F01,E8,_,_,_,_,_,_ ), 0 , 93 , 0 , 10570, 30 , 165), // #1555
1653 INST(Xtest , X86Op , O(000F01,D6,_,_,_,_,_,_ ), 0 , 21 , 0 , 10580, 30 , 169) // #1556
1654 // ${InstInfo:End}
1655 };
1656 #undef NAME_DATA_INDEX
1657 #undef INST
1658
1659 // ============================================================================
1660 // [asmjit::x86::InstDB - Opcode Tables]
1661 // ============================================================================
1662
1663 // ${MainOpcodeTable:Begin}
1664 // ------------------- Automatically generated, do not edit -------------------
1665 const uint32_t InstDB::_mainOpcodeTable[] = {
1666 O(000000,00,0,0,0,0,0,_ ), // #0 [ref=56x]
1667 O(000000,00,2,0,0,0,0,_ ), // #1 [ref=4x]
1668 O(660F38,00,0,0,0,0,0,_ ), // #2 [ref=43x]
1669 O(660F00,00,0,0,0,0,0,_ ), // #3 [ref=38x]
1670 O(000F00,00,0,0,0,0,0,_ ), // #4 [ref=231x]
1671 O(F20F00,00,0,0,0,0,0,_ ), // #5 [ref=24x]
1672 O(F30F00,00,0,0,0,0,0,_ ), // #6 [ref=29x]
1673 O(F30F38,00,0,0,0,0,0,_ ), // #7 [ref=2x]
1674 O(660F3A,00,0,0,0,0,0,_ ), // #8 [ref=22x]
1675 O(000000,00,4,0,0,0,0,_ ), // #9 [ref=5x]
1676 V(000F38,00,0,0,0,0,0,_ ), // #10 [ref=6x]
1677 V(XOP_M9,00,1,0,0,0,0,_ ), // #11 [ref=3x]
1678 V(XOP_M9,00,6,0,0,0,0,_ ), // #12 [ref=2x]
1679 V(XOP_M9,00,5,0,0,0,0,_ ), // #13 [ref=1x]
1680 V(XOP_M9,00,3,0,0,0,0,_ ), // #14 [ref=1x]
1681 V(XOP_M9,00,2,0,0,0,0,_ ), // #15 [ref=1x]
1682 V(000F38,00,3,0,0,0,0,_ ), // #16 [ref=1x]
1683 V(000F38,00,2,0,0,0,0,_ ), // #17 [ref=1x]
1684 V(000F38,00,1,0,0,0,0,_ ), // #18 [ref=1x]
1685 O(660000,00,0,0,0,0,0,_ ), // #19 [ref=7x]
1686 O(000000,00,0,0,1,0,0,_ ), // #20 [ref=3x]
1687 O(000F01,00,0,0,0,0,0,_ ), // #21 [ref=29x]
1688 O(000F00,00,7,0,0,0,0,_ ), // #22 [ref=5x]
1689 O(660F00,00,7,0,0,0,0,_ ), // #23 [ref=1x]
1690 O(F30F00,00,6,0,0,0,0,_ ), // #24 [ref=4x]
1691 O(F30F01,00,0,0,0,0,0,_ ), // #25 [ref=9x]
1692 O(660F00,00,6,0,0,0,0,_ ), // #26 [ref=3x]
1693 O(000000,00,7,0,0,0,0,_ ), // #27 [ref=5x]
1694 O(000F00,00,1,0,1,0,0,_ ), // #28 [ref=2x]
1695 O(000F00,00,1,0,0,0,0,_ ), // #29 [ref=6x]
1696 O(F20F38,00,0,0,0,0,0,_ ), // #30 [ref=2x]
1697 O(000000,00,1,0,0,0,0,_ ), // #31 [ref=3x]
1698 O(000000,00,6,0,0,0,0,_ ), // #32 [ref=3x]
1699 O(F30F00,00,7,0,0,0,0,3 ), // #33 [ref=1x]
1700 O(F30F00,00,7,0,0,0,0,2 ), // #34 [ref=1x]
1701 O_FPU(00,D900,_) , // #35 [ref=29x]
1702 O_FPU(00,C000,0) , // #36 [ref=1x]
1703 O_FPU(00,DE00,_) , // #37 [ref=7x]
1704 O_FPU(00,0000,4) , // #38 [ref=4x]
1705 O_FPU(00,0000,6) , // #39 [ref=4x]
1706 O_FPU(9B,DB00,_) , // #40 [ref=2x]
1707 O_FPU(00,DA00,_) , // #41 [ref=5x]
1708 O_FPU(00,DB00,_) , // #42 [ref=8x]
1709 O_FPU(00,D000,2) , // #43 [ref=1x]
1710 O_FPU(00,DF00,_) , // #44 [ref=2x]
1711 O_FPU(00,D800,3) , // #45 [ref=1x]
1712 O_FPU(00,F000,6) , // #46 [ref=1x]
1713 O_FPU(00,F800,7) , // #47 [ref=1x]
1714 O_FPU(00,DD00,_) , // #48 [ref=3x]
1715 O_FPU(00,0000,0) , // #49 [ref=3x]
1716 O_FPU(00,0000,2) , // #50 [ref=3x]
1717 O_FPU(00,0000,3) , // #51 [ref=3x]
1718 O_FPU(00,0000,7) , // #52 [ref=3x]
1719 O_FPU(00,0000,1) , // #53 [ref=2x]
1720 O_FPU(00,0000,5) , // #54 [ref=2x]
1721 O_FPU(00,C800,1) , // #55 [ref=1x]
1722 O_FPU(9B,0000,6) , // #56 [ref=2x]
1723 O_FPU(9B,0000,7) , // #57 [ref=2x]
1724 O_FPU(00,E000,4) , // #58 [ref=1x]
1725 O_FPU(00,E800,5) , // #59 [ref=1x]
1726 O_FPU(00,0000,_) , // #60 [ref=1x]
1727 O(000F00,00,0,0,1,0,0,_ ), // #61 [ref=3x]
1728 O(F30F3A,00,0,0,0,0,0,_ ), // #62 [ref=1x]
1729 O(000000,00,5,0,0,0,0,_ ), // #63 [ref=4x]
1730 O(F30F00,00,5,0,0,0,0,_ ), // #64 [ref=2x]
1731 O(F30F00,00,5,0,1,0,0,_ ), // #65 [ref=1x]
1732 V(660F00,00,0,1,0,0,0,_ ), // #66 [ref=7x]
1733 V(660F00,00,0,1,1,0,0,_ ), // #67 [ref=6x]
1734 V(000F00,00,0,1,1,0,0,_ ), // #68 [ref=7x]
1735 V(000F00,00,0,1,0,0,0,_ ), // #69 [ref=8x]
1736 V(660F00,00,0,0,0,0,0,_ ), // #70 [ref=15x]
1737 V(660F00,00,0,0,1,0,0,_ ), // #71 [ref=4x]
1738 V(000F00,00,0,0,1,0,0,_ ), // #72 [ref=4x]
1739 V(000F00,00,0,0,0,0,0,_ ), // #73 [ref=10x]
1740 V(660F3A,00,0,0,0,0,0,_ ), // #74 [ref=45x]
1741 V(660F3A,00,0,0,1,0,0,_ ), // #75 [ref=4x]
1742 O(000000,00,3,0,0,0,0,_ ), // #76 [ref=4x]
1743 O(000F00,00,2,0,0,0,0,_ ), // #77 [ref=5x]
1744 O(000F00,00,5,0,0,0,0,_ ), // #78 [ref=4x]
1745 O(000F00,00,3,0,0,0,0,_ ), // #79 [ref=5x]
1746 V(XOP_M9,00,0,0,0,0,0,_ ), // #80 [ref=32x]
1747 O(000F00,00,6,0,0,0,0,_ ), // #81 [ref=5x]
1748 V(XOP_MA,00,0,0,0,0,0,_ ), // #82 [ref=1x]
1749 V(XOP_MA,00,1,0,0,0,0,_ ), // #83 [ref=1x]
1750 O(000F38,00,0,0,0,0,0,_ ), // #84 [ref=24x]
1751 V(F20F38,00,0,0,0,0,0,_ ), // #85 [ref=6x]
1752 O(000F3A,00,0,0,0,0,0,_ ), // #86 [ref=4x]
1753 O(F30000,00,0,0,0,0,0,_ ), // #87 [ref=1x]
1754 O(000F0F,00,0,0,0,0,0,_ ), // #88 [ref=26x]
1755 V(F30F38,00,0,0,0,0,0,_ ), // #89 [ref=5x]
1756 O(000F3A,00,0,0,1,0,0,_ ), // #90 [ref=1x]
1757 O(660F3A,00,0,0,1,0,0,_ ), // #91 [ref=1x]
1758 O(F30F00,00,4,0,0,0,0,_ ), // #92 [ref=1x]
1759 O(F20F01,00,0,0,0,0,0,_ ), // #93 [ref=4x]
1760 O(F30F00,00,1,0,0,0,0,_ ), // #94 [ref=3x]
1761 O(F30F00,00,7,0,0,0,0,_ ), // #95 [ref=1x]
1762 V(F20F3A,00,0,0,0,0,0,_ ), // #96 [ref=1x]
1763 V(660F38,00,0,0,0,0,0,_ ), // #97 [ref=25x]
1764 O(000F00,00,4,0,0,0,0,_ ), // #98 [ref=4x]
1765 V(XOP_M9,00,7,0,0,0,0,_ ), // #99 [ref=1x]
1766 V(XOP_M9,00,4,0,0,0,0,_ ), // #100 [ref=1x]
1767 O(F20F00,00,6,0,0,0,0,_ ), // #101 [ref=1x]
1768 E(F20F38,00,0,2,0,0,4,T4X), // #102 [ref=4x]
1769 E(F20F38,00,0,0,0,0,4,T4X), // #103 [ref=2x]
1770 V(660F00,00,0,0,0,1,4,FV ), // #104 [ref=22x]
1771 V(000F00,00,0,0,0,0,4,FV ), // #105 [ref=16x]
1772 V(F20F00,00,0,0,0,1,3,T1S), // #106 [ref=10x]
1773 V(F30F00,00,0,0,0,0,2,T1S), // #107 [ref=10x]
1774 V(F20F00,00,0,0,0,0,0,_ ), // #108 [ref=4x]
1775 V(660F38,00,0,0,0,0,4,FVM), // #109 [ref=14x]
1776 E(660F3A,00,0,0,0,0,4,FV ), // #110 [ref=14x]
1777 E(660F3A,00,0,0,0,1,4,FV ), // #111 [ref=14x]
1778 E(660F38,00,0,0,0,1,4,FV ), // #112 [ref=29x]
1779 E(660F38,00,0,0,0,0,4,FV ), // #113 [ref=18x]
1780 V(660F38,00,0,1,0,0,0,_ ), // #114 [ref=2x]
1781 E(660F38,00,0,0,0,0,3,T2 ), // #115 [ref=2x]
1782 E(660F38,00,0,0,0,0,4,T4 ), // #116 [ref=2x]
1783 E(660F38,00,0,2,0,0,5,T8 ), // #117 [ref=2x]
1784 E(660F38,00,0,0,0,1,4,T2 ), // #118 [ref=2x]
1785 E(660F38,00,0,2,0,1,5,T4 ), // #119 [ref=2x]
1786 V(660F38,00,0,0,0,1,3,T1S), // #120 [ref=2x]
1787 V(660F38,00,0,0,0,0,2,T1S), // #121 [ref=14x]
1788 V(660F00,00,0,0,0,1,3,T1S), // #122 [ref=5x]
1789 V(000F00,00,0,0,0,0,2,T1S), // #123 [ref=2x]
1790 E(660F38,00,0,0,0,1,3,T1S), // #124 [ref=14x]
1791 E(660F38,00,0,0,0,0,2,T1S), // #125 [ref=14x]
1792 V(F30F00,00,0,0,0,0,3,HV ), // #126 [ref=1x]
1793 E(F20F38,00,0,0,0,0,4,FV ), // #127 [ref=2x]
1794 E(F30F38,00,0,0,0,0,4,FV ), // #128 [ref=3x]
1795 V(F20F00,00,0,0,0,1,4,FV ), // #129 [ref=1x]
1796 E(660F00,00,0,0,0,1,4,FV ), // #130 [ref=9x]
1797 E(000F00,00,0,0,0,1,4,FV ), // #131 [ref=3x]
1798 V(660F38,00,0,0,0,0,3,HVM), // #132 [ref=7x]
1799 V(660F00,00,0,0,0,0,4,FV ), // #133 [ref=11x]
1800 V(000F00,00,0,0,0,0,3,HV ), // #134 [ref=1x]
1801 V(660F3A,00,0,0,0,0,3,HVM), // #135 [ref=1x]
1802 E(660F00,00,0,0,0,0,3,HV ), // #136 [ref=4x]
1803 E(000F00,00,0,0,0,0,4,FV ), // #137 [ref=2x]
1804 E(F30F00,00,0,0,0,1,4,FV ), // #138 [ref=2x]
1805 V(F20F00,00,0,0,0,0,3,T1F), // #139 [ref=2x]
1806 E(F20F00,00,0,0,0,0,3,T1F), // #140 [ref=2x]
1807 V(F20F00,00,0,0,0,0,2,T1W), // #141 [ref=1x]
1808 V(F30F00,00,0,0,0,0,2,T1W), // #142 [ref=1x]
1809 V(F30F00,00,0,0,0,0,2,T1F), // #143 [ref=2x]
1810 E(F30F00,00,0,0,0,0,2,T1F), // #144 [ref=2x]
1811 V(F30F00,00,0,0,0,0,4,FV ), // #145 [ref=1x]
1812 E(F30F00,00,0,0,0,0,3,HV ), // #146 [ref=1x]
1813 E(F20F00,00,0,0,0,0,4,FV ), // #147 [ref=1x]
1814 E(F20F00,00,0,0,0,1,4,FV ), // #148 [ref=1x]
1815 E(F20F00,00,0,0,0,0,2,T1W), // #149 [ref=1x]
1816 E(F30F00,00,0,0,0,0,2,T1W), // #150 [ref=1x]
1817 E(660F3A,00,0,0,0,0,4,FVM), // #151 [ref=3x]
1818 E(660F38,00,0,2,0,1,4,FV ), // #152 [ref=3x]
1819 E(660F38,00,0,2,0,0,4,FV ), // #153 [ref=3x]
1820 V(660F3A,00,0,1,0,0,0,_ ), // #154 [ref=6x]
1821 E(660F3A,00,0,0,0,0,4,T4 ), // #155 [ref=4x]
1822 E(660F3A,00,0,2,0,0,5,T8 ), // #156 [ref=4x]
1823 E(660F3A,00,0,0,0,1,4,T2 ), // #157 [ref=4x]
1824 E(660F3A,00,0,2,0,1,5,T4 ), // #158 [ref=4x]
1825 V(660F3A,00,0,0,0,0,2,T1S), // #159 [ref=4x]
1826 E(660F3A,00,0,0,0,1,3,T1S), // #160 [ref=6x]
1827 E(660F3A,00,0,0,0,0,2,T1S), // #161 [ref=6x]
1828 V(660F38,00,0,0,1,1,4,FV ), // #162 [ref=20x]
1829 V(660F38,00,0,0,0,0,4,FV ), // #163 [ref=36x]
1830 V(660F38,00,0,0,1,1,3,T1S), // #164 [ref=12x]
1831 V(660F38,00,0,0,1,0,0,_ ), // #165 [ref=5x]
1832 E(660F38,00,1,2,0,1,3,T1S), // #166 [ref=2x]
1833 E(660F38,00,1,2,0,0,2,T1S), // #167 [ref=2x]
1834 E(660F38,00,2,2,0,1,3,T1S), // #168 [ref=2x]
1835 E(660F38,00,2,2,0,0,2,T1S), // #169 [ref=2x]
1836 V(660F3A,00,0,0,1,1,4,FV ), // #170 [ref=2x]
1837 V(000F00,00,2,0,0,0,0,_ ), // #171 [ref=1x]
1838 V(660F00,00,0,0,0,1,4,FVM), // #172 [ref=3x]
1839 V(000F00,00,0,0,0,0,4,FVM), // #173 [ref=3x]
1840 V(660F00,00,0,0,0,0,2,T1S), // #174 [ref=1x]
1841 V(F20F00,00,0,0,0,1,3,DUP), // #175 [ref=1x]
1842 E(660F00,00,0,0,0,0,4,FVM), // #176 [ref=1x]
1843 E(660F00,00,0,0,0,1,4,FVM), // #177 [ref=1x]
1844 V(F30F00,00,0,0,0,0,0,_ ), // #178 [ref=3x]
1845 E(F20F00,00,0,0,0,1,4,FVM), // #179 [ref=1x]
1846 E(F30F00,00,0,0,0,0,4,FVM), // #180 [ref=1x]
1847 E(F30F00,00,0,0,0,1,4,FVM), // #181 [ref=1x]
1848 E(F20F00,00,0,0,0,0,4,FVM), // #182 [ref=1x]
1849 V(000F00,00,0,0,0,0,3,T2 ), // #183 [ref=2x]
1850 V(660F00,00,0,0,0,0,4,FVM), // #184 [ref=32x]
1851 V(F30F00,00,0,0,0,0,4,FVM), // #185 [ref=3x]
1852 E(F20F38,00,0,0,0,1,4,FV ), // #186 [ref=1x]
1853 V(660F3A,00,0,0,0,0,4,FVM), // #187 [ref=2x]
1854 E(660F00,00,0,0,0,0,4,FV ), // #188 [ref=5x]
1855 E(660F38,00,0,0,0,0,4,FVM), // #189 [ref=7x]
1856 E(660F38,00,0,0,0,1,4,FVM), // #190 [ref=11x]
1857 V(660F38,00,0,0,0,0,0,T1S), // #191 [ref=1x]
1858 E(F30F38,00,0,0,0,1,0,_ ), // #192 [ref=5x]
1859 E(F30F38,00,0,0,0,0,0,_ ), // #193 [ref=5x]
1860 V(660F38,00,0,0,0,0,1,T1S), // #194 [ref=1x]
1861 V(XOP_M8,00,0,0,0,0,0,_ ), // #195 [ref=22x]
1862 V(660F38,00,0,0,0,1,4,FVM), // #196 [ref=2x]
1863 E(660F3A,00,0,0,0,1,4,FVM), // #197 [ref=4x]
1864 E(660F38,00,0,0,0,0,0,T1S), // #198 [ref=2x]
1865 E(660F38,00,0,0,0,1,1,T1S), // #199 [ref=2x]
1866 V(660F38,00,0,0,0,1,4,FV ), // #200 [ref=2x]
1867 E(660F38,00,0,0,1,1,4,FV ), // #201 [ref=1x]
1868 V(660F3A,00,0,0,0,0,0,T1S), // #202 [ref=2x]
1869 V(660F3A,00,0,0,1,1,3,T1S), // #203 [ref=2x]
1870 V(660F3A,00,0,0,0,0,1,T1S), // #204 [ref=1x]
1871 V(660F00,00,0,0,0,0,1,T1S), // #205 [ref=1x]
1872 E(F30F38,00,0,0,0,0,2,QVM), // #206 [ref=6x]
1873 E(F30F38,00,0,0,0,0,3,HVM), // #207 [ref=9x]
1874 E(F30F38,00,0,0,0,0,1,OVM), // #208 [ref=3x]
1875 V(660F38,00,0,0,0,0,2,QVM), // #209 [ref=4x]
1876 V(660F38,00,0,0,0,0,1,OVM), // #210 [ref=2x]
1877 E(660F00,00,1,0,0,0,4,FV ), // #211 [ref=1x]
1878 E(660F00,00,1,0,0,1,4,FV ), // #212 [ref=1x]
1879 V(F20F00,00,0,0,0,0,4,FVM), // #213 [ref=1x]
1880 V(660F00,00,0,0,0,0,4,128), // #214 [ref=6x]
1881 V(660F00,00,7,0,0,0,4,FVM), // #215 [ref=1x]
1882 V(660F00,00,0,0,0,1,4,128), // #216 [ref=2x]
1883 E(660F00,00,0,0,0,1,4,128), // #217 [ref=1x]
1884 V(660F00,00,3,0,0,0,4,FVM), // #218 [ref=1x]
1885 E(F30F38,00,0,0,0,0,4,FVM), // #219 [ref=1x]
1886 E(F30F38,00,0,0,0,1,4,FV ), // #220 [ref=1x]
1887 E(F30F38,00,0,0,0,1,4,FVM), // #221 [ref=1x]
1888 E(660F38,00,5,2,0,1,3,T1S), // #222 [ref=2x]
1889 E(660F38,00,5,2,0,0,2,T1S), // #223 [ref=2x]
1890 E(660F38,00,6,2,0,1,3,T1S), // #224 [ref=2x]
1891 E(660F38,00,6,2,0,0,2,T1S), // #225 [ref=2x]
1892 V(000F00,00,3,0,0,0,0,_ ), // #226 [ref=1x]
1893 O(F30F00,00,2,0,0,0,0,_ ), // #227 [ref=1x]
1894 O(F30F00,00,3,0,0,0,0,_ ), // #228 [ref=1x]
1895 O(000F38,00,0,0,1,0,0,_ ), // #229 [ref=1x]
1896 O(660F38,00,0,0,1,0,0,_ ), // #230 [ref=1x]
1897 O(000F00,00,5,0,1,0,0,_ ), // #231 [ref=2x]
1898 O(000F00,00,3,0,1,0,0,_ ), // #232 [ref=1x]
1899 O(000F00,00,4,0,1,0,0,_ ), // #233 [ref=2x]
1900 O(000F00,00,6,0,1,0,0,_ ) // #234 [ref=1x]
1901 };
1902 // ----------------------------------------------------------------------------
1903 // ${MainOpcodeTable:End}
1904
1905 // ${AltOpcodeTable:Begin}
1906 // ------------------- Automatically generated, do not edit -------------------
1907 const uint32_t InstDB::_altOpcodeTable[] = {
1908 0 , // #0 [ref=1410x]
1909 O(660F00,1B,_,_,_,_,_,_ ), // #1 [ref=1x]
1910 O(000F00,BA,4,_,x,_,_,_ ), // #2 [ref=1x]
1911 O(000F00,BA,7,_,x,_,_,_ ), // #3 [ref=1x]
1912 O(000F00,BA,6,_,x,_,_,_ ), // #4 [ref=1x]
1913 O(000F00,BA,5,_,x,_,_,_ ), // #5 [ref=1x]
1914 O(000000,48,_,_,x,_,_,_ ), // #6 [ref=1x]
1915 O(660F00,78,0,_,_,_,_,_ ), // #7 [ref=1x]
1916 O_FPU(00,00DF,5) , // #8 [ref=1x]
1917 O_FPU(00,00DF,7) , // #9 [ref=1x]
1918 O_FPU(00,00DD,1) , // #10 [ref=1x]
1919 O_FPU(00,00DB,5) , // #11 [ref=1x]
1920 O_FPU(00,DFE0,_) , // #12 [ref=1x]
1921 O(000000,DB,7,_,_,_,_,_ ), // #13 [ref=1x]
1922 O_FPU(9B,DFE0,_) , // #14 [ref=1x]
1923 O(000000,E4,_,_,_,_,_,_ ), // #15 [ref=1x]
1924 O(000000,40,_,_,x,_,_,_ ), // #16 [ref=1x]
1925 O(F20F00,78,_,_,_,_,_,_ ), // #17 [ref=1x]
1926 O(000000,77,_,_,_,_,_,_ ), // #18 [ref=2x]
1927 O(000000,73,_,_,_,_,_,_ ), // #19 [ref=3x]
1928 O(000000,72,_,_,_,_,_,_ ), // #20 [ref=3x]
1929 O(000000,76,_,_,_,_,_,_ ), // #21 [ref=2x]
1930 O(000000,74,_,_,_,_,_,_ ), // #22 [ref=2x]
1931 O(000000,E3,_,_,_,_,_,_ ), // #23 [ref=1x]
1932 O(000000,7F,_,_,_,_,_,_ ), // #24 [ref=2x]
1933 O(000000,7D,_,_,_,_,_,_ ), // #25 [ref=2x]
1934 O(000000,7C,_,_,_,_,_,_ ), // #26 [ref=2x]
1935 O(000000,7E,_,_,_,_,_,_ ), // #27 [ref=2x]
1936 O(000000,EB,_,_,_,_,_,_ ), // #28 [ref=1x]
1937 O(000000,75,_,_,_,_,_,_ ), // #29 [ref=2x]
1938 O(000000,71,_,_,_,_,_,_ ), // #30 [ref=1x]
1939 O(000000,7B,_,_,_,_,_,_ ), // #31 [ref=2x]
1940 O(000000,79,_,_,_,_,_,_ ), // #32 [ref=1x]
1941 O(000000,70,_,_,_,_,_,_ ), // #33 [ref=1x]
1942 O(000000,7A,_,_,_,_,_,_ ), // #34 [ref=2x]
1943 O(000000,78,_,_,_,_,_,_ ), // #35 [ref=1x]
1944 V(660F00,92,_,0,0,_,_,_ ), // #36 [ref=1x]
1945 V(F20F00,92,_,0,0,_,_,_ ), // #37 [ref=1x]
1946 V(F20F00,92,_,0,1,_,_,_ ), // #38 [ref=1x]
1947 V(000F00,92,_,0,0,_,_,_ ), // #39 [ref=1x]
1948 O(000000,9A,_,_,_,_,_,_ ), // #40 [ref=1x]
1949 O(000000,EA,_,_,_,_,_,_ ), // #41 [ref=1x]
1950 O(000000,E2,_,_,_,_,_,_ ), // #42 [ref=1x]
1951 O(000000,E1,_,_,_,_,_,_ ), // #43 [ref=1x]
1952 O(000000,E0,_,_,_,_,_,_ ), // #44 [ref=1x]
1953 O(660F00,29,_,_,_,_,_,_ ), // #45 [ref=1x]
1954 O(000F00,29,_,_,_,_,_,_ ), // #46 [ref=1x]
1955 O(000F38,F1,_,_,x,_,_,_ ), // #47 [ref=1x]
1956 O(000F00,7E,_,_,_,_,_,_ ), // #48 [ref=1x]
1957 O(660F00,7F,_,_,_,_,_,_ ), // #49 [ref=1x]
1958 O(F30F00,7F,_,_,_,_,_,_ ), // #50 [ref=1x]
1959 O(660F00,17,_,_,_,_,_,_ ), // #51 [ref=1x]
1960 O(000F00,17,_,_,_,_,_,_ ), // #52 [ref=1x]
1961 O(660F00,13,_,_,_,_,_,_ ), // #53 [ref=1x]
1962 O(000F00,13,_,_,_,_,_,_ ), // #54 [ref=1x]
1963 O(660F00,E7,_,_,_,_,_,_ ), // #55 [ref=1x]
1964 O(660F00,2B,_,_,_,_,_,_ ), // #56 [ref=1x]
1965 O(000F00,2B,_,_,_,_,_,_ ), // #57 [ref=1x]
1966 O(000F00,E7,_,_,_,_,_,_ ), // #58 [ref=1x]
1967 O(F20F00,2B,_,_,_,_,_,_ ), // #59 [ref=1x]
1968 O(F30F00,2B,_,_,_,_,_,_ ), // #60 [ref=1x]
1969 O(000F00,7E,_,_,x,_,_,_ ), // #61 [ref=1x]
1970 O(F20F00,11,_,_,_,_,_,_ ), // #62 [ref=1x]
1971 O(F30F00,11,_,_,_,_,_,_ ), // #63 [ref=1x]
1972 O(660F00,11,_,_,_,_,_,_ ), // #64 [ref=1x]
1973 O(000F00,11,_,_,_,_,_,_ ), // #65 [ref=1x]
1974 O(000000,E6,_,_,_,_,_,_ ), // #66 [ref=1x]
1975 O(000F3A,15,_,_,_,_,_,_ ), // #67 [ref=1x]
1976 O(000000,58,_,_,_,_,_,_ ), // #68 [ref=1x]
1977 O(000F00,72,6,_,_,_,_,_ ), // #69 [ref=1x]
1978 O(660F00,73,7,_,_,_,_,_ ), // #70 [ref=1x]
1979 O(000F00,73,6,_,_,_,_,_ ), // #71 [ref=1x]
1980 O(000F00,71,6,_,_,_,_,_ ), // #72 [ref=1x]
1981 O(000F00,72,4,_,_,_,_,_ ), // #73 [ref=1x]
1982 O(000F00,71,4,_,_,_,_,_ ), // #74 [ref=1x]
1983 O(000F00,72,2,_,_,_,_,_ ), // #75 [ref=1x]
1984 O(660F00,73,3,_,_,_,_,_ ), // #76 [ref=1x]
1985 O(000F00,73,2,_,_,_,_,_ ), // #77 [ref=1x]
1986 O(000F00,71,2,_,_,_,_,_ ), // #78 [ref=1x]
1987 O(000000,50,_,_,_,_,_,_ ), // #79 [ref=1x]
1988 O(000000,F6,_,_,x,_,_,_ ), // #80 [ref=1x]
1989 E(660F38,92,_,x,_,1,3,T1S), // #81 [ref=1x]
1990 E(660F38,92,_,x,_,0,2,T1S), // #82 [ref=1x]
1991 E(660F38,93,_,x,_,1,3,T1S), // #83 [ref=1x]
1992 E(660F38,93,_,x,_,0,2,T1S), // #84 [ref=1x]
1993 V(660F38,2F,_,x,0,_,_,_ ), // #85 [ref=1x]
1994 V(660F38,2E,_,x,0,_,_,_ ), // #86 [ref=1x]
1995 V(660F00,29,_,x,I,1,4,FVM), // #87 [ref=1x]
1996 V(000F00,29,_,x,I,0,4,FVM), // #88 [ref=1x]
1997 V(660F00,7E,_,0,0,0,2,T1S), // #89 [ref=1x]
1998 V(660F00,7F,_,x,I,_,_,_ ), // #90 [ref=1x]
1999 E(660F00,7F,_,x,_,0,4,FVM), // #91 [ref=1x]
2000 E(660F00,7F,_,x,_,1,4,FVM), // #92 [ref=1x]
2001 V(F30F00,7F,_,x,I,_,_,_ ), // #93 [ref=1x]
2002 E(F20F00,7F,_,x,_,1,4,FVM), // #94 [ref=1x]
2003 E(F30F00,7F,_,x,_,0,4,FVM), // #95 [ref=1x]
2004 E(F30F00,7F,_,x,_,1,4,FVM), // #96 [ref=1x]
2005 E(F20F00,7F,_,x,_,0,4,FVM), // #97 [ref=1x]
2006 V(660F00,17,_,0,I,1,3,T1S), // #98 [ref=1x]
2007 V(000F00,17,_,0,I,0,3,T2 ), // #99 [ref=1x]
2008 V(660F00,13,_,0,I,1,3,T1S), // #100 [ref=1x]
2009 V(000F00,13,_,0,I,0,3,T2 ), // #101 [ref=1x]
2010 V(660F00,7E,_,0,I,1,3,T1S), // #102 [ref=1x]
2011 V(F20F00,11,_,I,I,1,3,T1S), // #103 [ref=1x]
2012 V(F30F00,11,_,I,I,0,2,T1S), // #104 [ref=1x]
2013 V(660F00,11,_,x,I,1,4,FVM), // #105 [ref=1x]
2014 V(000F00,11,_,x,I,0,4,FVM), // #106 [ref=1x]
2015 E(660F38,7A,_,x,0,0,0,T1S), // #107 [ref=1x]
2016 E(660F38,7C,_,x,0,0,0,T1S), // #108 [ref=1x]
2017 E(660F38,7C,_,x,0,1,0,T1S), // #109 [ref=1x]
2018 E(660F38,7B,_,x,0,0,0,T1S), // #110 [ref=1x]
2019 V(660F3A,05,_,x,0,1,4,FV ), // #111 [ref=1x]
2020 V(660F3A,04,_,x,0,0,4,FV ), // #112 [ref=1x]
2021 V(660F3A,01,_,x,1,1,4,FV ), // #113 [ref=1x]
2022 V(660F3A,00,_,x,1,1,4,FV ), // #114 [ref=1x]
2023 E(660F38,90,_,x,_,0,2,T1S), // #115 [ref=1x]
2024 E(660F38,90,_,x,_,1,3,T1S), // #116 [ref=1x]
2025 E(660F38,91,_,x,_,0,2,T1S), // #117 [ref=1x]
2026 E(660F38,91,_,x,_,1,3,T1S), // #118 [ref=1x]
2027 V(660F38,8E,_,x,0,_,_,_ ), // #119 [ref=1x]
2028 V(660F38,8E,_,x,1,_,_,_ ), // #120 [ref=1x]
2029 V(XOP_M8,C0,_,0,x,_,_,_ ), // #121 [ref=1x]
2030 V(XOP_M8,C2,_,0,x,_,_,_ ), // #122 [ref=1x]
2031 V(XOP_M8,C3,_,0,x,_,_,_ ), // #123 [ref=1x]
2032 V(XOP_M8,C1,_,0,x,_,_,_ ), // #124 [ref=1x]
2033 V(660F00,72,6,x,I,0,4,FV ), // #125 [ref=1x]
2034 V(660F00,73,6,x,I,1,4,FV ), // #126 [ref=1x]
2035 V(660F00,71,6,x,I,I,4,FVM), // #127 [ref=1x]
2036 V(660F00,72,4,x,I,0,4,FV ), // #128 [ref=1x]
2037 E(660F00,72,4,x,_,1,4,FV ), // #129 [ref=1x]
2038 V(660F00,71,4,x,I,I,4,FVM), // #130 [ref=1x]
2039 V(660F00,72,2,x,I,0,4,FV ), // #131 [ref=1x]
2040 V(660F00,73,2,x,I,1,4,FV ), // #132 [ref=1x]
2041 V(660F00,71,2,x,I,I,4,FVM) // #133 [ref=1x]
2042 };
2043 // ----------------------------------------------------------------------------
2044 // ${AltOpcodeTable:End}
2045
2046 #undef O
2047 #undef V
2048 #undef E
2049 #undef O_FPU
2050
2051 // ============================================================================
2052 // [asmjit::x86::InstDB - CommonInfoTableA]
2053 // ============================================================================
2054
2055 // ${InstCommonTable:Begin}
2056 // ------------------- Automatically generated, do not edit -------------------
2057 #define F(VAL) InstDB::kFlag##VAL
2058 #define CONTROL(VAL) Inst::kControl##VAL
2059 #define SINGLE_REG(VAL) InstDB::kSingleReg##VAL
2060 const InstDB::CommonInfo InstDB::_commonInfoTable[] = {
2061 { 0 , 0 , 0 , CONTROL(None) , SINGLE_REG(None), 0 }, // #0 [ref=1x]
2062 { 0 , 376, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #1 [ref=4x]
2063 { 0 , 377, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #2 [ref=2x]
2064 { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #3 [ref=2x]
2065 { 0 , 180, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #4 [ref=2x]
2066 { F(Vec) , 79 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #5 [ref=54x]
2067 { F(Vec) , 106, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #6 [ref=19x]
2068 { F(Vec) , 257, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #7 [ref=16x]
2069 { F(Vec) , 215, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #8 [ref=20x]
2070 { F(Lock)|F(XAcquire)|F(XRelease) , 28 , 11, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #9 [ref=1x]
2071 { F(Vex) , 272, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #10 [ref=3x]
2072 { F(Vec) , 79 , 1 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #11 [ref=12x]
2073 { 0 , 378, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #12 [ref=1x]
2074 { F(Vex) , 274, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #13 [ref=5x]
2075 { F(Vex) , 180, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #14 [ref=12x]
2076 { F(Vec) , 379, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #15 [ref=4x]
2077 { 0 , 276, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #16 [ref=3x]
2078 { F(Mib) , 380, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #17 [ref=1x]
2079 { 0 , 381, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #18 [ref=1x]
2080 { 0 , 278, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #19 [ref=1x]
2081 { F(Mib) , 382, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #20 [ref=1x]
2082 { 0 , 280, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #21 [ref=1x]
2083 { 0 , 179, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #22 [ref=35x]
2084 { 0 , 383, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #23 [ref=3x]
2085 { 0 , 123, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #24 [ref=1x]
2086 { F(Lock)|F(XAcquire)|F(XRelease) , 123, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #25 [ref=3x]
2087 { F(Rep)|F(RepIgnored) , 282, 2 , CONTROL(Call) , SINGLE_REG(None), 0 }, // #26 [ref=1x]
2088 { 0 , 384, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #27 [ref=1x]
2089 { 0 , 385, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #28 [ref=2x]
2090 { 0 , 359, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #29 [ref=1x]
2091 { 0 , 108, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #30 [ref=83x]
2092 { 0 , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #31 [ref=24x]
2093 { 0 , 387, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #32 [ref=6x]
2094 { 0 , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #33 [ref=13x]
2095 { 0 , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #34 [ref=1x]
2096 { 0 , 16 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #35 [ref=1x]
2097 { F(Rep) , 127, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #36 [ref=1x]
2098 { F(Vec) , 390, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #37 [ref=2x]
2099 { F(Vec) , 391, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #38 [ref=3x]
2100 { F(Lock)|F(XAcquire)|F(XRelease) , 131, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #39 [ref=1x]
2101 { F(Lock)|F(XAcquire)|F(XRelease) , 392, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #40 [ref=1x]
2102 { F(Lock)|F(XAcquire)|F(XRelease) , 393, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #41 [ref=1x]
2103 { 0 , 394, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #42 [ref=1x]
2104 { 0 , 395, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #43 [ref=1x]
2105 { 0 , 284, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #44 [ref=1x]
2106 { F(Mmx)|F(Vec) , 396, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #45 [ref=2x]
2107 { F(Mmx)|F(Vec) , 397, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #46 [ref=2x]
2108 { F(Mmx)|F(Vec) , 398, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #47 [ref=2x]
2109 { F(Vec) , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #48 [ref=2x]
2110 { F(Vec) , 400, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #49 [ref=2x]
2111 { F(Vec) , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #50 [ref=2x]
2112 { 0 , 402, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #51 [ref=1x]
2113 { 0 , 403, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #52 [ref=2x]
2114 { F(Lock)|F(XAcquire)|F(XRelease) , 286, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #53 [ref=2x]
2115 { 0 , 39 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #54 [ref=3x]
2116 { F(Mmx) , 108, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #55 [ref=1x]
2117 { 0 , 288, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #56 [ref=2x]
2118 { 0 , 404, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #57 [ref=1x]
2119 { F(Vec) , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #58 [ref=2x]
2120 { F(Vec) , 290, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #59 [ref=1x]
2121 { F(FpuM32)|F(FpuM64) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #60 [ref=6x]
2122 { 0 , 292, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #61 [ref=9x]
2123 { F(FpuM80) , 406, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #62 [ref=2x]
2124 { 0 , 293, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #63 [ref=13x]
2125 { F(FpuM32)|F(FpuM64) , 294, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #64 [ref=2x]
2126 { F(FpuM16)|F(FpuM32) , 407, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #65 [ref=9x]
2127 { F(FpuM16)|F(FpuM32)|F(FpuM64) , 408, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #66 [ref=3x]
2128 { F(FpuM32)|F(FpuM64)|F(FpuM80) , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #67 [ref=2x]
2129 { F(FpuM16) , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #68 [ref=3x]
2130 { F(FpuM16) , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #69 [ref=2x]
2131 { F(FpuM32)|F(FpuM64) , 295, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #70 [ref=1x]
2132 { 0 , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #71 [ref=2x]
2133 { 0 , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #72 [ref=1x]
2134 { 0 , 39 , 10, CONTROL(None) , SINGLE_REG(None), 0 }, // #73 [ref=1x]
2135 { 0 , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #74 [ref=1x]
2136 { 0 , 415, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #75 [ref=2x]
2137 { 0 , 343, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #76 [ref=3x]
2138 { F(Rep) , 416, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #77 [ref=1x]
2139 { F(Vec) , 296, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #78 [ref=1x]
2140 { 0 , 417, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #79 [ref=2x]
2141 { 0 , 418, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #80 [ref=8x]
2142 { 0 , 298, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #81 [ref=3x]
2143 { 0 , 300, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #82 [ref=1x]
2144 { 0 , 108, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #83 [ref=2x]
2145 { 0 , 388, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #84 [ref=1x]
2146 { F(Rep)|F(RepIgnored) , 302, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #85 [ref=30x]
2147 { F(Rep)|F(RepIgnored) , 304, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #86 [ref=1x]
2148 { F(Rep)|F(RepIgnored) , 306, 2 , CONTROL(Jump) , SINGLE_REG(None), 0 }, // #87 [ref=1x]
2149 { F(Vec)|F(Vex) , 419, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #88 [ref=27x]
2150 { F(Vec)|F(Vex) , 308, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #89 [ref=1x]
2151 { F(Vec)|F(Vex) , 310, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #90 [ref=1x]
2152 { F(Vec)|F(Vex) , 312, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #91 [ref=1x]
2153 { F(Vec)|F(Vex) , 314, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #92 [ref=1x]
2154 { F(Vec)|F(Vex) , 420, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #93 [ref=12x]
2155 { F(Vec)|F(Vex) , 421, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #94 [ref=8x]
2156 { 0 , 422, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #95 [ref=2x]
2157 { 0 , 316, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #96 [ref=1x]
2158 { 0 , 318, 2 , CONTROL(Call) , SINGLE_REG(None), 0 }, // #97 [ref=1x]
2159 { F(Vec) , 224, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #98 [ref=2x]
2160 { 0 , 423, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #99 [ref=2x]
2161 { 0 , 320, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #100 [ref=2x]
2162 { F(Vex) , 424, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #101 [ref=2x]
2163 { 0 , 425, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #102 [ref=1x]
2164 { 0 , 185, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #103 [ref=3x]
2165 { 0 , 318, 2 , CONTROL(Jump) , SINGLE_REG(None), 0 }, // #104 [ref=1x]
2166 { 0 , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #105 [ref=5x]
2167 { F(Vex) , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #106 [ref=2x]
2168 { F(Rep) , 135, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #107 [ref=1x]
2169 { 0 , 304, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #108 [ref=3x]
2170 { 0 , 322, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #109 [ref=1x]
2171 { F(Vex) , 428, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #110 [ref=2x]
2172 { F(Vec) , 429, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #111 [ref=1x]
2173 { F(Mmx) , 430, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #112 [ref=1x]
2174 { 0 , 431, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #113 [ref=2x]
2175 { F(XRelease) , 0 , 16, CONTROL(None) , SINGLE_REG(None), 0 }, // #114 [ref=1x]
2176 { 0 , 49 , 9 , CONTROL(None) , SINGLE_REG(None), 0 }, // #115 [ref=1x]
2177 { F(Vec) , 79 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #116 [ref=6x]
2178 { 0 , 73 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #117 [ref=1x]
2179 { F(Mmx)|F(Vec) , 324, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #118 [ref=1x]
2180 { 0 , 432, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #119 [ref=1x]
2181 { 0 , 77 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #120 [ref=2x]
2182 { F(Mmx)|F(Vec) , 433, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #121 [ref=1x]
2183 { F(Vec) , 291, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #122 [ref=2x]
2184 { F(Vec) , 230, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #123 [ref=4x]
2185 { F(Vec) , 434, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #124 [ref=2x]
2186 { F(Vec) , 80 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #125 [ref=3x]
2187 { F(Mmx) , 435, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #126 [ref=1x]
2188 { F(Vec) , 107, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #127 [ref=1x]
2189 { F(Vec) , 233, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #128 [ref=1x]
2190 { F(Mmx)|F(Vec) , 103, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #129 [ref=1x]
2191 { F(Mmx)|F(Vec) , 436, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #130 [ref=1x]
2192 { F(Rep) , 139, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #131 [ref=1x]
2193 { F(Vec) , 106, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #132 [ref=1x]
2194 { F(Vec) , 326, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #133 [ref=1x]
2195 { 0 , 328, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #134 [ref=2x]
2196 { 0 , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #135 [ref=1x]
2197 { F(Vex) , 330, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #136 [ref=1x]
2198 { 0 , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #137 [ref=1x]
2199 { 0 , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #138 [ref=1x]
2200 { F(Lock)|F(XAcquire)|F(XRelease) , 287, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #139 [ref=2x]
2201 { 0 , 108, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #140 [ref=1x]
2202 { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #141 [ref=1x]
2203 { 0 , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #142 [ref=1x]
2204 { F(Rep) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #143 [ref=1x]
2205 { F(Mmx)|F(Vec) , 332, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #144 [ref=37x]
2206 { F(Mmx)|F(Vec) , 334, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #145 [ref=1x]
2207 { F(Mmx)|F(Vec) , 332, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #146 [ref=6x]
2208 { F(Mmx)|F(Vec) , 332, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #147 [ref=16x]
2209 { F(Mmx) , 332, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #148 [ref=26x]
2210 { F(Vec) , 79 , 1 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #149 [ref=4x]
2211 { F(Vec) , 442, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #150 [ref=1x]
2212 { F(Vec) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #151 [ref=1x]
2213 { F(Vec) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #152 [ref=1x]
2214 { F(Vec) , 445, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #153 [ref=1x]
2215 { F(Vec) , 446, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #154 [ref=1x]
2216 { F(Vec) , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #155 [ref=1x]
2217 { F(Mmx)|F(Vec) , 336, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #156 [ref=1x]
2218 { F(Vec) , 448, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #157 [ref=1x]
2219 { F(Vec) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #158 [ref=1x]
2220 { F(Vec) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #159 [ref=1x]
2221 { F(Mmx)|F(Vec) , 451, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #160 [ref=1x]
2222 { F(Mmx)|F(Vec) , 452, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #161 [ref=1x]
2223 { F(Vec) , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #162 [ref=2x]
2224 { 0 , 143, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #163 [ref=1x]
2225 { F(Mmx) , 334, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #164 [ref=1x]
2226 { F(Mmx)|F(Vec) , 338, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #165 [ref=8x]
2227 { F(Vec) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #166 [ref=2x]
2228 { 0 , 454, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #167 [ref=1x]
2229 { F(Mmx)|F(Vec) , 340, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #168 [ref=3x]
2230 { 0 , 147, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #169 [ref=1x]
2231 { 0 , 455, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #170 [ref=8x]
2232 { 0 , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #171 [ref=4x]
2233 { 0 , 457, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #172 [ref=8x]
2234 { 0 , 342, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #173 [ref=1x]
2235 { F(Rep)|F(RepIgnored) , 344, 2 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #174 [ref=1x]
2236 { 0 , 344, 2 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #175 [ref=1x]
2237 { F(Vex) , 346, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #176 [ref=1x]
2238 { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(WO) , 0 }, // #177 [ref=3x]
2239 { F(Rep) , 151, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #178 [ref=1x]
2240 { 0 , 458, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #179 [ref=30x]
2241 { 0 , 188, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #180 [ref=2x]
2242 { 0 , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #181 [ref=3x]
2243 { F(Rep) , 155, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #182 [ref=1x]
2244 { F(Vex) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #183 [ref=5x]
2245 { 0 , 66 , 7 , CONTROL(None) , SINGLE_REG(None), 0 }, // #184 [ref=1x]
2246 { F(Tsib)|F(Vex) , 461, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #185 [ref=2x]
2247 { F(Vex) , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #186 [ref=1x]
2248 { F(Tsib)|F(Vex) , 462, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #187 [ref=1x]
2249 { F(Vex) , 463, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #188 [ref=1x]
2250 { 0 , 464, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #189 [ref=2x]
2251 { 0 , 180, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #190 [ref=2x]
2252 { 0 , 465, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #191 [ref=1x]
2253 { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 466, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #192 [ref=4x]
2254 { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 467, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #193 [ref=2x]
2255 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #194 [ref=22x]
2256 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #195 [ref=22x]
2257 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #196 [ref=18x]
2258 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #197 [ref=17x]
2259 { F(Vec)|F(Vex) , 191, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #198 [ref=15x]
2260 { F(Vec)|F(Vex)|F(Evex) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #199 [ref=5x]
2261 { F(Vec)|F(Vex) , 79 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #200 [ref=17x]
2262 { F(Vec)|F(Vex) , 215, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #201 [ref=1x]
2263 { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #202 [ref=4x]
2264 { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #203 [ref=4x]
2265 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #204 [ref=10x]
2266 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #205 [ref=12x]
2267 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 191, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #206 [ref=2x]
2268 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #207 [ref=6x]
2269 { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #208 [ref=19x]
2270 { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #209 [ref=12x]
2271 { F(Vec)|F(Vex) , 194, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #210 [ref=6x]
2272 { F(Vec)|F(Vex) , 348, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #211 [ref=3x]
2273 { F(Vec)|F(Vex) , 470, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #212 [ref=2x]
2274 { F(Vec)|F(Evex)|F(Avx512KZ) , 471, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #213 [ref=1x]
2275 { F(Vec)|F(Evex)|F(Avx512KZ) , 472, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #214 [ref=4x]
2276 { F(Vec)|F(Evex)|F(Avx512KZ) , 473, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #215 [ref=4x]
2277 { F(Vec)|F(Evex)|F(Avx512KZ) , 474, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #216 [ref=1x]
2278 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 471, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #217 [ref=1x]
2279 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 475, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #218 [ref=1x]
2280 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 197, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #219 [ref=1x]
2281 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 197, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #220 [ref=1x]
2282 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 476, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #221 [ref=1x]
2283 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 477, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #222 [ref=1x]
2284 { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 106, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #223 [ref=2x]
2285 { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 257, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #224 [ref=2x]
2286 { F(Vec)|F(Evex)|F(Avx512KZ) , 200, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #225 [ref=6x]
2287 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 203, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #226 [ref=1x]
2288 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #227 [ref=3x]
2289 { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 350, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #228 [ref=1x]
2290 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 350, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #229 [ref=2x]
2291 { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #230 [ref=4x]
2292 { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 350, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #231 [ref=3x]
2293 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 203, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #232 [ref=1x]
2294 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 203, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #233 [ref=1x]
2295 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 209, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #234 [ref=1x]
2296 { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 203, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #235 [ref=2x]
2297 { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #236 [ref=2x]
2298 { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #237 [ref=1x]
2299 { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #238 [ref=1x]
2300 { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 478, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #239 [ref=2x]
2301 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #240 [ref=3x]
2302 { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #241 [ref=1x]
2303 { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #242 [ref=1x]
2304 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 350, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #243 [ref=1x]
2305 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #244 [ref=3x]
2306 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 350, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #245 [ref=1x]
2307 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #246 [ref=1x]
2308 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 203, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #247 [ref=2x]
2309 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #248 [ref=2x]
2310 { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #249 [ref=1x]
2311 { F(Vec)|F(Evex)|F(Avx512SAE) , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #250 [ref=1x]
2312 { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #251 [ref=1x]
2313 { F(Vec)|F(Evex)|F(Avx512SAE) , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #252 [ref=1x]
2314 { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 203, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #253 [ref=1x]
2315 { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 478, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #254 [ref=2x]
2316 { F(Vec)|F(Evex)|F(Avx512KZ) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #255 [ref=3x]
2317 { F(Vec)|F(Vex) , 194, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #256 [ref=9x]
2318 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 83 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #257 [ref=3x]
2319 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 83 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #258 [ref=3x]
2320 { F(Vec)|F(Evex)|F(Avx512KZ) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #259 [ref=9x]
2321 { F(Vec)|F(Vex) , 210, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #260 [ref=2x]
2322 { F(Vec)|F(Evex)|F(Avx512KZ) , 479, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #261 [ref=4x]
2323 { F(Vec)|F(Evex)|F(Avx512KZ) , 211, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #262 [ref=4x]
2324 { F(Vec)|F(Vex)|F(Evex) , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #263 [ref=2x]
2325 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #264 [ref=2x]
2326 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #265 [ref=2x]
2327 { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 480, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #266 [ref=4x]
2328 { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 481, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #267 [ref=4x]
2329 { F(Vec)|F(Vex) , 159, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #268 [ref=13x]
2330 { F(Vec)|F(Vex) , 352, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #269 [ref=4x]
2331 { F(Vec)|F(Vex) , 354, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #270 [ref=4x]
2332 { F(Vec)|F(Evex)|F(Avx512K_B64) , 482, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #271 [ref=1x]
2333 { F(Vec)|F(Evex)|F(Avx512K_B32) , 482, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #272 [ref=1x]
2334 { F(Vec)|F(Evex)|F(Avx512K) , 483, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #273 [ref=1x]
2335 { F(Vec)|F(Evex)|F(Avx512K) , 484, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #274 [ref=1x]
2336 { F(Vec)|F(Vex) , 206, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #275 [ref=7x]
2337 { F(Vec)|F(Vex) , 106, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #276 [ref=1x]
2338 { F(Vec)|F(Vex) , 257, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #277 [ref=1x]
2339 { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 163, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #278 [ref=2x]
2340 { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 113, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #279 [ref=2x]
2341 { F(Vsib)|F(Evex)|F(Avx512K) , 485, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #280 [ref=4x]
2342 { F(Vsib)|F(Evex)|F(Avx512K) , 486, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #281 [ref=4x]
2343 { F(Vsib)|F(Evex)|F(Avx512K) , 487, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #282 [ref=8x]
2344 { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 118, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #283 [ref=2x]
2345 { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 212, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #284 [ref=2x]
2346 { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #285 [ref=3x]
2347 { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #286 [ref=3x]
2348 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 215, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #287 [ref=2x]
2349 { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 215, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #288 [ref=2x]
2350 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #289 [ref=3x]
2351 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #290 [ref=22x]
2352 { F(Vec)|F(Vex) , 356, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #291 [ref=2x]
2353 { F(Vec)|F(Evex)|F(Avx512KZ) , 356, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #292 [ref=4x]
2354 { F(Vec)|F(Evex)|F(Avx512KZ) , 488, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #293 [ref=4x]
2355 { F(Vec)|F(Vex)|F(Evex) , 481, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #294 [ref=1x]
2356 { F(Vec)|F(Vex) , 224, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #295 [ref=1x]
2357 { F(Vex) , 423, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #296 [ref=2x]
2358 { F(Vec)|F(Vex) , 429, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #297 [ref=1x]
2359 { F(Vec)|F(Vex) , 167, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #298 [ref=4x]
2360 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #299 [ref=2x]
2361 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #300 [ref=2x]
2362 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #301 [ref=2x]
2363 { 0 , 358, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #302 [ref=3x]
2364 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 79 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #303 [ref=4x]
2365 { F(Vec)|F(Vex)|F(Evex) , 360, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #304 [ref=1x]
2366 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 218, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #305 [ref=1x]
2367 { F(Vec)|F(Vex) , 79 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #306 [ref=2x]
2368 { F(Vec)|F(Evex)|F(Avx512KZ) , 79 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #307 [ref=6x]
2369 { F(Vec)|F(Vex)|F(Evex) , 232, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #308 [ref=2x]
2370 { F(Vec)|F(Vex)|F(Evex) , 362, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #309 [ref=4x]
2371 { F(Vec)|F(Vex) , 489, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #310 [ref=3x]
2372 { F(Vec)|F(Vex)|F(Evex) , 221, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #311 [ref=3x]
2373 { F(Vec)|F(Vex)|F(Evex) , 224, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #312 [ref=1x]
2374 { F(Vec)|F(Vex)|F(Evex) , 227, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #313 [ref=1x]
2375 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 230, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #314 [ref=1x]
2376 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #315 [ref=5x]
2377 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 233, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #316 [ref=1x]
2378 { 0 , 364, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #317 [ref=1x]
2379 { 0 , 366, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #318 [ref=1x]
2380 { F(Vec)|F(Evex)|F(Avx512B32) , 236, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #319 [ref=1x]
2381 { F(Vec)|F(Evex)|F(Avx512B64) , 236, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #320 [ref=1x]
2382 { F(Vec)|F(Vex) , 191, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #321 [ref=2x]
2383 { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #322 [ref=2x]
2384 { F(Vec)|F(Vex) , 191, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #323 [ref=2x]
2385 { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #324 [ref=2x]
2386 { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 191, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #325 [ref=2x]
2387 { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 191, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #326 [ref=2x]
2388 { F(Vec)|F(Evex)|F(Avx512KZ) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #327 [ref=13x]
2389 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 490, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #328 [ref=1x]
2390 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 491, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #329 [ref=1x]
2391 { F(Vec)|F(Evex) , 492, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #330 [ref=6x]
2392 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 239, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #331 [ref=1x]
2393 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 493, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #332 [ref=1x]
2394 { F(Vec)|F(Vex)|F(Evex) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #333 [ref=1x]
2395 { F(Vec)|F(Evex)|F(Avx512K) , 242, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #334 [ref=2x]
2396 { F(Vec)|F(Evex)|F(Avx512K_B32) , 242, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #335 [ref=2x]
2397 { F(Vec)|F(Vex)|F(Evex)|F(Avx512K) , 245, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #336 [ref=4x]
2398 { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B32) , 245, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #337 [ref=2x]
2399 { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B64) , 245, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #338 [ref=2x]
2400 { F(Vec)|F(Vex) , 442, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #339 [ref=1x]
2401 { F(Vec)|F(Vex) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #340 [ref=1x]
2402 { F(Vec)|F(Vex) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #341 [ref=1x]
2403 { F(Vec)|F(Vex) , 445, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #342 [ref=1x]
2404 { F(Vec)|F(Evex)|F(Avx512K_B64) , 242, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #343 [ref=4x]
2405 { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #344 [ref=6x]
2406 { F(Vec)|F(Vex)|F(Evex)|F(PreferEvex)|F(Avx512KZ_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #345 [ref=4x]
2407 { F(Vec)|F(Vex) , 195, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #346 [ref=2x]
2408 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 192, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #347 [ref=2x]
2409 { F(Vec)|F(Vex) , 171, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #348 [ref=2x]
2410 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 85 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #349 [ref=2x]
2411 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 175, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #350 [ref=2x]
2412 { F(Vec)|F(Vex)|F(Evex) , 446, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #351 [ref=1x]
2413 { F(Vec)|F(Vex)|F(Evex) , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #352 [ref=1x]
2414 { F(Vec)|F(Vex)|F(Evex) , 494, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #353 [ref=1x]
2415 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 495, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #354 [ref=1x]
2416 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 496, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #355 [ref=1x]
2417 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 497, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #356 [ref=1x]
2418 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 498, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #357 [ref=1x]
2419 { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #358 [ref=4x]
2420 { F(Vec)|F(Vex) , 348, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #359 [ref=12x]
2421 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 191, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #360 [ref=8x]
2422 { F(Vec)|F(Evex) , 499, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #361 [ref=4x]
2423 { F(Vec)|F(Evex)|F(Avx512KZ) , 248, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #362 [ref=6x]
2424 { F(Vec)|F(Evex)|F(Avx512KZ) , 251, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #363 [ref=9x]
2425 { F(Vec)|F(Evex)|F(Avx512KZ) , 254, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #364 [ref=3x]
2426 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 257, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #365 [ref=4x]
2427 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 260, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #366 [ref=2x]
2428 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 203, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #367 [ref=6x]
2429 { F(Vec)|F(Vex) , 159, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #368 [ref=1x]
2430 { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 215, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #369 [ref=3x]
2431 { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 215, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #370 [ref=3x]
2432 { F(Vec)|F(Vex) , 368, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #371 [ref=4x]
2433 { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 263, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #372 [ref=2x]
2434 { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 370, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #373 [ref=2x]
2435 { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 372, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #374 [ref=2x]
2436 { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 266, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #375 [ref=2x]
2437 { F(Vec)|F(Vex) , 374, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #376 [ref=8x]
2438 { F(Vec)|F(Evex)|F(Avx512K) , 269, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #377 [ref=5x]
2439 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 215, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #378 [ref=1x]
2440 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 215, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #379 [ref=2x]
2441 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 91 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #380 [ref=3x]
2442 { F(Vec)|F(Vex)|F(Evex) , 215, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #381 [ref=2x]
2443 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 91 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #382 [ref=2x]
2444 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 91 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #383 [ref=3x]
2445 { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 97 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #384 [ref=1x]
2446 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 191, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #385 [ref=6x]
2447 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #386 [ref=2x]
2448 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 191, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #387 [ref=2x]
2449 { F(Vec)|F(Evex)|F(Avx512K_B32) , 269, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #388 [ref=2x]
2450 { F(Vec)|F(Evex)|F(Avx512K_B64) , 269, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #389 [ref=2x]
2451 { F(Vec)|F(Evex)|F(Avx512KZ) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #390 [ref=2x]
2452 { F(Vec)|F(Evex)|F(Avx512KZ) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #391 [ref=2x]
2453 { F(Vec)|F(Vex) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #392 [ref=2x]
2454 { F(Vec)|F(Evex)|F(Avx512KZ) , 480, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #393 [ref=1x]
2455 { F(Vec)|F(Evex)|F(Avx512KZ) , 481, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #394 [ref=1x]
2456 { F(Vec)|F(Vex) , 215, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #395 [ref=2x]
2457 { F(Vec)|F(Vex) , 480, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #396 [ref=1x]
2458 { F(Vec)|F(Vex) , 481, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #397 [ref=1x]
2459 { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #398 [ref=1x]
2460 { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #399 [ref=1x]
2461 { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #400 [ref=1x]
2462 { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #401 [ref=1x]
2463 { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 195, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #402 [ref=2x]
2464 { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 195, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #403 [ref=2x]
2465 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #404 [ref=1x]
2466 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #405 [ref=1x]
2467 { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #406 [ref=1x]
2468 { F(Vec)|F(Vex) , 108, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #407 [ref=2x]
2469 { 0 , 23 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #408 [ref=2x]
2470 { 0 , 61 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #409 [ref=2x]
2471 { F(Lock)|F(XAcquire)|F(XRelease) , 58 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #410 [ref=1x]
2472 { 0 , 500, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #411 [ref=1x]
2473 { F(Lock)|F(XAcquire) , 58 , 8 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #412 [ref=1x]
2474 { 0 , 501, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #413 [ref=6x]
2475 { 0 , 502, 1 , CONTROL(None) , SINGLE_REG(None), 0 } // #414 [ref=6x]
2476 };
2477 #undef SINGLE_REG
2478 #undef CONTROL
2479 #undef F
2480 // ----------------------------------------------------------------------------
2481 // ${InstCommonTable:End}
2482
2483 // ============================================================================
2484 // [asmjit::x86::InstDB - CommonInfoTableB]
2485 // ============================================================================
2486
2487 // ${InstCommonInfoTableB:Begin}
2488 // ------------------- Automatically generated, do not edit -------------------
2489 #define EXT(VAL) uint32_t(Features::k##VAL)
2490 const InstDB::CommonInfoTableB InstDB::_commonInfoTableB[] = {
2491 { { 0 }, 0, 0 }, // #0 [ref=149x]
2492 { { 0 }, 1, 0 }, // #1 [ref=32x]
2493 { { 0 }, 2, 0 }, // #2 [ref=2x]
2494 { { EXT(ADX) }, 3, 0 }, // #3 [ref=1x]
2495 { { EXT(SSE2) }, 0, 0 }, // #4 [ref=65x]
2496 { { EXT(SSE) }, 0, 0 }, // #5 [ref=44x]
2497 { { EXT(SSE3) }, 0, 0 }, // #6 [ref=12x]
2498 { { EXT(ADX) }, 4, 0 }, // #7 [ref=1x]
2499 { { EXT(AESNI) }, 0, 0 }, // #8 [ref=6x]
2500 { { EXT(BMI) }, 1, 0 }, // #9 [ref=6x]
2501 { { 0 }, 5, 0 }, // #10 [ref=5x]
2502 { { EXT(TBM) }, 0, 0 }, // #11 [ref=9x]
2503 { { EXT(SSE4_1) }, 0, 0 }, // #12 [ref=47x]
2504 { { EXT(MPX) }, 0, 0 }, // #13 [ref=7x]
2505 { { 0 }, 6, 0 }, // #14 [ref=4x]
2506 { { EXT(BMI2) }, 1, 0 }, // #15 [ref=1x]
2507 { { EXT(SMAP) }, 7, 0 }, // #16 [ref=2x]
2508 { { 0 }, 8, 0 }, // #17 [ref=2x]
2509 { { 0 }, 9, 0 }, // #18 [ref=2x]
2510 { { EXT(CLDEMOTE) }, 0, 0 }, // #19 [ref=1x]
2511 { { EXT(CLFLUSH) }, 0, 0 }, // #20 [ref=1x]
2512 { { EXT(CLFLUSHOPT) }, 0, 0 }, // #21 [ref=1x]
2513 { { EXT(SVM) }, 0, 0 }, // #22 [ref=6x]
2514 { { 0 }, 10, 0 }, // #23 [ref=2x]
2515 { { EXT(CET_SS) }, 1, 0 }, // #24 [ref=3x]
2516 { { EXT(UINTR) }, 0, 0 }, // #25 [ref=4x]
2517 { { EXT(CLWB) }, 0, 0 }, // #26 [ref=1x]
2518 { { EXT(CLZERO) }, 0, 0 }, // #27 [ref=1x]
2519 { { 0 }, 3, 0 }, // #28 [ref=1x]
2520 { { EXT(CMOV) }, 11, 0 }, // #29 [ref=6x]
2521 { { EXT(CMOV) }, 12, 0 }, // #30 [ref=8x]
2522 { { EXT(CMOV) }, 13, 0 }, // #31 [ref=6x]
2523 { { EXT(CMOV) }, 14, 0 }, // #32 [ref=4x]
2524 { { EXT(CMOV) }, 15, 0 }, // #33 [ref=4x]
2525 { { EXT(CMOV) }, 16, 0 }, // #34 [ref=2x]
2526 { { EXT(CMOV) }, 17, 0 }, // #35 [ref=6x]
2527 { { EXT(CMOV) }, 18, 0 }, // #36 [ref=2x]
2528 { { 0 }, 19, 0 }, // #37 [ref=2x]
2529 { { EXT(I486) }, 1, 0 }, // #38 [ref=2x]
2530 { { EXT(CMPXCHG16B) }, 5, 0 }, // #39 [ref=1x]
2531 { { EXT(CMPXCHG8B) }, 5, 0 }, // #40 [ref=1x]
2532 { { EXT(SSE2) }, 1, 0 }, // #41 [ref=2x]
2533 { { EXT(SSE) }, 1, 0 }, // #42 [ref=2x]
2534 { { EXT(I486) }, 0, 0 }, // #43 [ref=4x]
2535 { { EXT(SSE4_2) }, 0, 0 }, // #44 [ref=2x]
2536 { { 0 }, 20, 0 }, // #45 [ref=2x]
2537 { { EXT(MMX) }, 0, 0 }, // #46 [ref=1x]
2538 { { EXT(CET_IBT) }, 0, 0 }, // #47 [ref=2x]
2539 { { EXT(ENQCMD) }, 0, 0 }, // #48 [ref=2x]
2540 { { EXT(SSE4A) }, 0, 0 }, // #49 [ref=4x]
2541 { { 0 }, 21, 0 }, // #50 [ref=4x]
2542 { { EXT(3DNOW) }, 0, 0 }, // #51 [ref=21x]
2543 { { EXT(FXSR) }, 0, 0 }, // #52 [ref=4x]
2544 { { EXT(SMX) }, 0, 0 }, // #53 [ref=1x]
2545 { { EXT(GFNI) }, 0, 0 }, // #54 [ref=3x]
2546 { { EXT(HRESET) }, 0, 0 }, // #55 [ref=1x]
2547 { { EXT(CET_SS) }, 0, 0 }, // #56 [ref=9x]
2548 { { 0 }, 16, 0 }, // #57 [ref=5x]
2549 { { EXT(VMX) }, 0, 0 }, // #58 [ref=12x]
2550 { { 0 }, 11, 0 }, // #59 [ref=8x]
2551 { { 0 }, 12, 0 }, // #60 [ref=12x]
2552 { { 0 }, 13, 0 }, // #61 [ref=10x]
2553 { { 0 }, 14, 0 }, // #62 [ref=8x]
2554 { { 0 }, 15, 0 }, // #63 [ref=8x]
2555 { { 0 }, 17, 0 }, // #64 [ref=8x]
2556 { { 0 }, 18, 0 }, // #65 [ref=4x]
2557 { { EXT(AVX512_DQ) }, 0, 0 }, // #66 [ref=23x]
2558 { { EXT(AVX512_BW) }, 0, 0 }, // #67 [ref=22x]
2559 { { EXT(AVX512_F) }, 0, 0 }, // #68 [ref=37x]
2560 { { EXT(AVX512_DQ) }, 1, 0 }, // #69 [ref=3x]
2561 { { EXT(AVX512_BW) }, 1, 0 }, // #70 [ref=4x]
2562 { { EXT(AVX512_F) }, 1, 0 }, // #71 [ref=1x]
2563 { { EXT(LAHFSAHF) }, 22, 0 }, // #72 [ref=1x]
2564 { { EXT(AMX_TILE) }, 0, 0 }, // #73 [ref=7x]
2565 { { EXT(LWP) }, 0, 0 }, // #74 [ref=4x]
2566 { { 0 }, 23, 0 }, // #75 [ref=3x]
2567 { { EXT(LZCNT) }, 1, 0 }, // #76 [ref=1x]
2568 { { EXT(MMX2) }, 0, 0 }, // #77 [ref=8x]
2569 { { EXT(MCOMMIT) }, 1, 0 }, // #78 [ref=1x]
2570 { { EXT(MONITOR) }, 0, 0 }, // #79 [ref=2x]
2571 { { EXT(MONITORX) }, 0, 0 }, // #80 [ref=2x]
2572 { { EXT(MOVBE) }, 0, 0 }, // #81 [ref=1x]
2573 { { EXT(MMX), EXT(SSE2) }, 0, 0 }, // #82 [ref=46x]
2574 { { EXT(MOVDIR64B) }, 0, 0 }, // #83 [ref=1x]
2575 { { EXT(MOVDIRI) }, 0, 0 }, // #84 [ref=1x]
2576 { { EXT(BMI2) }, 0, 0 }, // #85 [ref=7x]
2577 { { EXT(SSSE3) }, 0, 0 }, // #86 [ref=15x]
2578 { { EXT(MMX2), EXT(SSE2) }, 0, 0 }, // #87 [ref=10x]
2579 { { EXT(PCLMULQDQ) }, 0, 0 }, // #88 [ref=1x]
2580 { { EXT(SSE4_2) }, 1, 0 }, // #89 [ref=4x]
2581 { { EXT(PCONFIG) }, 0, 0 }, // #90 [ref=1x]
2582 { { EXT(MMX2), EXT(SSE2), EXT(SSE4_1) }, 0, 0 }, // #91 [ref=1x]
2583 { { EXT(3DNOW2) }, 0, 0 }, // #92 [ref=5x]
2584 { { EXT(GEODE) }, 0, 0 }, // #93 [ref=2x]
2585 { { EXT(POPCNT) }, 1, 0 }, // #94 [ref=1x]
2586 { { 0 }, 24, 0 }, // #95 [ref=3x]
2587 { { EXT(PREFETCHW) }, 1, 0 }, // #96 [ref=1x]
2588 { { EXT(PREFETCHWT1) }, 1, 0 }, // #97 [ref=1x]
2589 { { EXT(SNP) }, 20, 0 }, // #98 [ref=3x]
2590 { { EXT(SSE4_1) }, 1, 0 }, // #99 [ref=1x]
2591 { { EXT(PTWRITE) }, 0, 0 }, // #100 [ref=1x]
2592 { { 0 }, 25, 0 }, // #101 [ref=3x]
2593 { { EXT(SNP) }, 1, 0 }, // #102 [ref=1x]
2594 { { 0 }, 26, 0 }, // #103 [ref=2x]
2595 { { EXT(FSGSBASE) }, 0, 0 }, // #104 [ref=4x]
2596 { { EXT(MSR) }, 0, 0 }, // #105 [ref=2x]
2597 { { EXT(RDPID) }, 0, 0 }, // #106 [ref=1x]
2598 { { EXT(OSPKE) }, 0, 0 }, // #107 [ref=1x]
2599 { { EXT(RDPRU) }, 0, 0 }, // #108 [ref=1x]
2600 { { EXT(RDRAND) }, 1, 0 }, // #109 [ref=1x]
2601 { { EXT(RDSEED) }, 1, 0 }, // #110 [ref=1x]
2602 { { EXT(RDTSC) }, 0, 0 }, // #111 [ref=1x]
2603 { { EXT(RDTSCP) }, 0, 0 }, // #112 [ref=1x]
2604 { { 0 }, 27, 0 }, // #113 [ref=2x]
2605 { { EXT(LAHFSAHF) }, 28, 0 }, // #114 [ref=1x]
2606 { { EXT(SERIALIZE) }, 0, 0 }, // #115 [ref=1x]
2607 { { EXT(SHA) }, 0, 0 }, // #116 [ref=7x]
2608 { { EXT(SKINIT) }, 0, 0 }, // #117 [ref=2x]
2609 { { EXT(AMX_BF16) }, 0, 0 }, // #118 [ref=1x]
2610 { { EXT(AMX_INT8) }, 0, 0 }, // #119 [ref=4x]
2611 { { EXT(UINTR) }, 1, 0 }, // #120 [ref=1x]
2612 { { EXT(WAITPKG) }, 1, 0 }, // #121 [ref=2x]
2613 { { EXT(WAITPKG) }, 0, 0 }, // #122 [ref=1x]
2614 { { EXT(AVX512_4FMAPS) }, 0, 0 }, // #123 [ref=4x]
2615 { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #124 [ref=46x]
2616 { { EXT(AVX), EXT(AVX512_F) }, 0, 0 }, // #125 [ref=32x]
2617 { { EXT(AVX) }, 0, 0 }, // #126 [ref=37x]
2618 { { EXT(AESNI), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(VAES) }, 0, 0 }, // #127 [ref=4x]
2619 { { EXT(AESNI), EXT(AVX) }, 0, 0 }, // #128 [ref=2x]
2620 { { EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #129 [ref=112x]
2621 { { EXT(AVX), EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #130 [ref=8x]
2622 { { EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #131 [ref=30x]
2623 { { EXT(AVX2) }, 0, 0 }, // #132 [ref=7x]
2624 { { EXT(AVX), EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #133 [ref=39x]
2625 { { EXT(AVX), EXT(AVX512_F) }, 1, 0 }, // #134 [ref=4x]
2626 { { EXT(AVX512_BF16), EXT(AVX512_VL) }, 0, 0 }, // #135 [ref=3x]
2627 { { EXT(AVX512_F), EXT(AVX512_VL), EXT(F16C) }, 0, 0 }, // #136 [ref=2x]
2628 { { EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #137 [ref=26x]
2629 { { EXT(AVX512_ERI) }, 0, 0 }, // #138 [ref=10x]
2630 { { EXT(AVX512_F), EXT(AVX512_VL), EXT(FMA) }, 0, 0 }, // #139 [ref=36x]
2631 { { EXT(AVX512_F), EXT(FMA) }, 0, 0 }, // #140 [ref=24x]
2632 { { EXT(FMA4) }, 0, 0 }, // #141 [ref=20x]
2633 { { EXT(XOP) }, 0, 0 }, // #142 [ref=55x]
2634 { { EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #143 [ref=19x]
2635 { { EXT(AVX512_PFI) }, 0, 0 }, // #144 [ref=16x]
2636 { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(GFNI) }, 0, 0 }, // #145 [ref=3x]
2637 { { EXT(AVX), EXT(AVX2) }, 0, 0 }, // #146 [ref=17x]
2638 { { EXT(AVX512_VP2INTERSECT) }, 0, 0 }, // #147 [ref=2x]
2639 { { EXT(AVX512_4VNNIW) }, 0, 0 }, // #148 [ref=2x]
2640 { { EXT(AVX), EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #149 [ref=54x]
2641 { { EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #150 [ref=2x]
2642 { { EXT(AVX512_CDI), EXT(AVX512_VL) }, 0, 0 }, // #151 [ref=6x]
2643 { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(PCLMULQDQ), EXT(VPCLMULQDQ) }, 0, 0 }, // #152 [ref=1x]
2644 { { EXT(AVX) }, 1, 0 }, // #153 [ref=7x]
2645 { { EXT(AVX512_VBMI2), EXT(AVX512_VL) }, 0, 0 }, // #154 [ref=16x]
2646 { { EXT(AVX512_VL), EXT(AVX512_VNNI), EXT(AVX_VNNI) }, 0, 0 }, // #155 [ref=4x]
2647 { { EXT(AVX512_VBMI), EXT(AVX512_VL) }, 0, 0 }, // #156 [ref=4x]
2648 { { EXT(AVX), EXT(AVX512_BW) }, 0, 0 }, // #157 [ref=4x]
2649 { { EXT(AVX), EXT(AVX512_DQ) }, 0, 0 }, // #158 [ref=4x]
2650 { { EXT(AVX512_IFMA), EXT(AVX512_VL) }, 0, 0 }, // #159 [ref=2x]
2651 { { EXT(AVX512_BITALG), EXT(AVX512_VL) }, 0, 0 }, // #160 [ref=3x]
2652 { { EXT(AVX512_VL), EXT(AVX512_VPOPCNTDQ) }, 0, 0 }, // #161 [ref=2x]
2653 { { EXT(WBNOINVD) }, 0, 0 }, // #162 [ref=1x]
2654 { { EXT(RTM) }, 0, 0 }, // #163 [ref=3x]
2655 { { EXT(XSAVE) }, 0, 0 }, // #164 [ref=6x]
2656 { { EXT(TSXLDTRK) }, 0, 0 }, // #165 [ref=2x]
2657 { { EXT(XSAVES) }, 0, 0 }, // #166 [ref=4x]
2658 { { EXT(XSAVEC) }, 0, 0 }, // #167 [ref=2x]
2659 { { EXT(XSAVEOPT) }, 0, 0 }, // #168 [ref=2x]
2660 { { EXT(TSX) }, 1, 0 } // #169 [ref=1x]
2661 };
2662 #undef EXT
2663
2664 #define FLAG(VAL) uint32_t(Status::k##VAL)
2665 const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = {
2666 { 0, 0 }, // #0 [ref=1323x]
2667 { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #1 [ref=84x]
2668 { FLAG(CF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #2 [ref=2x]
2669 { FLAG(CF), FLAG(CF) }, // #3 [ref=2x]
2670 { FLAG(OF), FLAG(OF) }, // #4 [ref=1x]
2671 { 0, FLAG(ZF) }, // #5 [ref=7x]
2672 { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) }, // #6 [ref=4x]
2673 { 0, FLAG(AC) }, // #7 [ref=2x]
2674 { 0, FLAG(CF) }, // #8 [ref=2x]
2675 { 0, FLAG(DF) }, // #9 [ref=2x]
2676 { 0, FLAG(IF) }, // #10 [ref=2x]
2677 { FLAG(CF) | FLAG(ZF), 0 }, // #11 [ref=14x]
2678 { FLAG(CF), 0 }, // #12 [ref=20x]
2679 { FLAG(ZF), 0 }, // #13 [ref=16x]
2680 { FLAG(OF) | FLAG(SF) | FLAG(ZF), 0 }, // #14 [ref=12x]
2681 { FLAG(OF) | FLAG(SF), 0 }, // #15 [ref=12x]
2682 { FLAG(OF), 0 }, // #16 [ref=7x]
2683 { FLAG(PF), 0 }, // #17 [ref=14x]
2684 { FLAG(SF), 0 }, // #18 [ref=6x]
2685 { FLAG(DF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #19 [ref=2x]
2686 { 0, FLAG(AF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #20 [ref=5x]
2687 { 0, FLAG(CF) | FLAG(PF) | FLAG(ZF) }, // #21 [ref=4x]
2688 { FLAG(AF) | FLAG(CF) | FLAG(PF) | FLAG(SF) | FLAG(ZF), 0 }, // #22 [ref=1x]
2689 { FLAG(DF), 0 }, // #23 [ref=3x]
2690 { 0, FLAG(AF) | FLAG(CF) | FLAG(DF) | FLAG(IF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #24 [ref=3x]
2691 { FLAG(AF) | FLAG(CF) | FLAG(DF) | FLAG(IF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF), 0 }, // #25 [ref=3x]
2692 { FLAG(CF) | FLAG(OF), FLAG(CF) | FLAG(OF) }, // #26 [ref=2x]
2693 { 0, FLAG(CF) | FLAG(OF) }, // #27 [ref=2x]
2694 { 0, FLAG(AF) | FLAG(CF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) } // #28 [ref=1x]
2695 };
2696 #undef FLAG
2697 // ----------------------------------------------------------------------------
2698 // ${InstCommonInfoTableB:End}
2699
2700 // ============================================================================
2701 // [asmjit::Inst - NameData]
2702 // ============================================================================
2703
2704 #ifndef ASMJIT_NO_TEXT
2705 // ${NameData:Begin}
2706 // ------------------- Automatically generated, do not edit -------------------
2707 const char InstDB::_nameData[] =
2708 "\0" "aaa\0" "aad\0" "aam\0" "aas\0" "adc\0" "adcx\0" "adox\0" "arpl\0" "bextr\0" "blcfill\0" "blci\0" "blcic\0"
2709 "blcmsk\0" "blcs\0" "blsfill\0" "blsi\0" "blsic\0" "blsmsk\0" "blsr\0" "bndcl\0" "bndcn\0" "bndcu\0" "bndldx\0"
2710 "bndmk\0" "bndmov\0" "bndstx\0" "bound\0" "bsf\0" "bsr\0" "bswap\0" "bt\0" "btc\0" "btr\0" "bts\0" "bzhi\0" "cbw\0"
2711 "cdq\0" "cdqe\0" "clac\0" "clc\0" "cld\0" "cldemote\0" "clflush\0" "clflushopt\0" "clgi\0" "cli\0" "clrssbsy\0"
2712 "clts\0" "clui\0" "clwb\0" "clzero\0" "cmc\0" "cmova\0" "cmovae\0" "cmovc\0" "cmovg\0" "cmovge\0" "cmovl\0"
2713 "cmovle\0" "cmovna\0" "cmovnae\0" "cmovnc\0" "cmovng\0" "cmovnge\0" "cmovnl\0" "cmovnle\0" "cmovno\0" "cmovnp\0"
2714 "cmovns\0" "cmovnz\0" "cmovo\0" "cmovp\0" "cmovpe\0" "cmovpo\0" "cmovs\0" "cmovz\0" "cmp\0" "cmps\0" "cmpxchg\0"
2715 "cmpxchg16b\0" "cmpxchg8b\0" "cpuid\0" "cqo\0" "crc32\0" "cvtpd2pi\0" "cvtpi2pd\0" "cvtpi2ps\0" "cvtps2pi\0"
2716 "cvttpd2pi\0" "cvttps2pi\0" "cwd\0" "cwde\0" "daa\0" "das\0" "endbr32\0" "endbr64\0" "enqcmd\0" "enqcmds\0" "f2xm1\0"
2717 "fabs\0" "faddp\0" "fbld\0" "fbstp\0" "fchs\0" "fclex\0" "fcmovb\0" "fcmovbe\0" "fcmove\0" "fcmovnb\0" "fcmovnbe\0"
2718 "fcmovne\0" "fcmovnu\0" "fcmovu\0" "fcom\0" "fcomi\0" "fcomip\0" "fcomp\0" "fcompp\0" "fcos\0" "fdecstp\0" "fdiv\0"
2719 "fdivp\0" "fdivr\0" "fdivrp\0" "femms\0" "ffree\0" "fiadd\0" "ficom\0" "ficomp\0" "fidiv\0" "fidivr\0" "fild\0"
2720 "fimul\0" "fincstp\0" "finit\0" "fist\0" "fistp\0" "fisttp\0" "fisub\0" "fisubr\0" "fld\0" "fld1\0" "fldcw\0"
2721 "fldenv\0" "fldl2e\0" "fldl2t\0" "fldlg2\0" "fldln2\0" "fldpi\0" "fldz\0" "fmulp\0" "fnclex\0" "fninit\0" "fnop\0"
2722 "fnsave\0" "fnstcw\0" "fnstenv\0" "fnstsw\0" "fpatan\0" "fprem\0" "fprem1\0" "fptan\0" "frndint\0" "frstor\0"
2723 "fsave\0" "fscale\0" "fsin\0" "fsincos\0" "fsqrt\0" "fst\0" "fstcw\0" "fstenv\0" "fstp\0" "fstsw\0" "fsubp\0"
2724 "fsubrp\0" "ftst\0" "fucom\0" "fucomi\0" "fucomip\0" "fucomp\0" "fucompp\0" "fwait\0" "fxam\0" "fxch\0" "fxrstor\0"
2725 "fxrstor64\0" "fxsave\0" "fxsave64\0" "fxtract\0" "fyl2x\0" "fyl2xp1\0" "getsec\0" "hlt\0" "hreset\0" "inc\0"
2726 "incsspd\0" "incsspq\0" "insertq\0" "int3\0" "into\0" "invept\0" "invlpg\0" "invlpga\0" "invpcid\0" "invvpid\0"
2727 "iretd\0" "iretq\0" "ja\0" "jae\0" "jb\0" "jbe\0" "jc\0" "je\0" "jecxz\0" "jg\0" "jge\0" "jl\0" "jle\0" "jna\0"
2728 "jnae\0" "jnb\0" "jnbe\0" "jnc\0" "jne\0" "jng\0" "jnge\0" "jnl\0" "jnle\0" "jno\0" "jnp\0" "jns\0" "jnz\0" "jo\0"
2729 "jp\0" "jpe\0" "jpo\0" "js\0" "jz\0" "kaddb\0" "kaddd\0" "kaddq\0" "kaddw\0" "kandb\0" "kandd\0" "kandnb\0"
2730 "kandnd\0" "kandnq\0" "kandnw\0" "kandq\0" "kandw\0" "kmovb\0" "kmovw\0" "knotb\0" "knotd\0" "knotq\0" "knotw\0"
2731 "korb\0" "kord\0" "korq\0" "kortestb\0" "kortestd\0" "kortestq\0" "kortestw\0" "korw\0" "kshiftlb\0" "kshiftld\0"
2732 "kshiftlq\0" "kshiftlw\0" "kshiftrb\0" "kshiftrd\0" "kshiftrq\0" "kshiftrw\0" "ktestb\0" "ktestd\0" "ktestq\0"
2733 "ktestw\0" "kunpckbw\0" "kunpckdq\0" "kunpckwd\0" "kxnorb\0" "kxnord\0" "kxnorq\0" "kxnorw\0" "kxorb\0" "kxord\0"
2734 "kxorq\0" "kxorw\0" "lahf\0" "lar\0" "lcall\0" "lds\0" "ldtilecfg\0" "lea\0" "leave\0" "les\0" "lfence\0" "lfs\0"
2735 "lgdt\0" "lgs\0" "lidt\0" "ljmp\0" "lldt\0" "llwpcb\0" "lmsw\0" "lods\0" "loop\0" "loope\0" "loopne\0" "lsl\0"
2736 "ltr\0" "lwpins\0" "lwpval\0" "lzcnt\0" "mcommit\0" "mfence\0" "monitorx\0" "movabs\0" "movdir64b\0" "movdiri\0"
2737 "movdq2q\0" "movnti\0" "movntq\0" "movntsd\0" "movntss\0" "movq2dq\0" "movsx\0" "movsxd\0" "movzx\0" "mulx\0"
2738 "mwaitx\0" "neg\0" "not\0" "out\0" "outs\0" "pavgusb\0" "pconfig\0" "pdep\0" "pext\0" "pf2id\0" "pf2iw\0" "pfacc\0"
2739 "pfadd\0" "pfcmpeq\0" "pfcmpge\0" "pfcmpgt\0" "pfmax\0" "pfmin\0" "pfmul\0" "pfnacc\0" "pfpnacc\0" "pfrcp\0"
2740 "pfrcpit1\0" "pfrcpit2\0" "pfrcpv\0" "pfrsqit1\0" "pfrsqrt\0" "pfrsqrtv\0" "pfsub\0" "pfsubr\0" "pi2fd\0" "pi2fw\0"
2741 "pmulhrw\0" "pop\0" "popa\0" "popad\0" "popcnt\0" "popf\0" "popfd\0" "popfq\0" "prefetch\0" "prefetchnta\0"
2742 "prefetcht0\0" "prefetcht1\0" "prefetcht2\0" "prefetchw\0" "prefetchwt1\0" "pshufw\0" "psmash\0" "pswapd\0"
2743 "ptwrite\0" "push\0" "pusha\0" "pushad\0" "pushf\0" "pushfd\0" "pushfq\0" "pvalidate\0" "rcl\0" "rcr\0" "rdfsbase\0"
2744 "rdgsbase\0" "rdmsr\0" "rdpid\0" "rdpkru\0" "rdpmc\0" "rdpru\0" "rdrand\0" "rdseed\0" "rdsspd\0" "rdsspq\0" "rdtsc\0"
2745 "rdtscp\0" "retf\0" "rmpadjust\0" "rmpupdate\0" "rol\0" "ror\0" "rorx\0" "rsm\0" "rstorssp\0" "sahf\0" "sal\0"
2746 "sar\0" "sarx\0" "saveprevssp\0" "sbb\0" "scas\0" "senduipi\0" "serialize\0" "seta\0" "setae\0" "setb\0" "setbe\0"
2747 "setc\0" "sete\0" "setg\0" "setge\0" "setl\0" "setle\0" "setna\0" "setnae\0" "setnb\0" "setnbe\0" "setnc\0" "setne\0"
2748 "setng\0" "setnge\0" "setnl\0" "setnle\0" "setno\0" "setnp\0" "setns\0" "setnz\0" "seto\0" "setp\0" "setpe\0"
2749 "setpo\0" "sets\0" "setssbsy\0" "setz\0" "sfence\0" "sgdt\0" "sha1msg1\0" "sha1msg2\0" "sha1nexte\0" "sha1rnds4\0"
2750 "sha256msg1\0" "sha256msg2\0" "sha256rnds2\0" "shl\0" "shlx\0" "shr\0" "shrd\0" "shrx\0" "sidt\0" "skinit\0" "sldt\0"
2751 "slwpcb\0" "smsw\0" "stac\0" "stc\0" "stgi\0" "sti\0" "stos\0" "str\0" "sttilecfg\0" "swapgs\0" "syscall\0"
2752 "sysenter\0" "sysexit\0" "sysexitq\0" "sysret\0" "sysretq\0" "t1mskc\0" "tdpbf16ps\0" "tdpbssd\0" "tdpbsud\0"
2753 "tdpbusd\0" "tdpbuud\0" "testui\0" "tileloadd\0" "tileloaddt1\0" "tilerelease\0" "tilestored\0" "tilezero\0"
2754 "tpause\0" "tzcnt\0" "tzmsk\0" "ud0\0" "ud1\0" "ud2\0" "uiret\0" "umonitor\0" "umwait\0" "v4fmaddps\0" "v4fmaddss\0"
2755 "v4fnmaddps\0" "v4fnmaddss\0" "vaddpd\0" "vaddps\0" "vaddsd\0" "vaddss\0" "vaddsubpd\0" "vaddsubps\0" "vaesdec\0"
2756 "vaesdeclast\0" "vaesenc\0" "vaesenclast\0" "vaesimc\0" "vaeskeygenassist\0" "valignd\0" "valignq\0" "vandnpd\0"
2757 "vandnps\0" "vandpd\0" "vandps\0" "vblendmpd\0" "vblendmps\0" "vblendpd\0" "vblendps\0" "vblendvpd\0" "vblendvps\0"
2758 "vbroadcastf128\0" "vbroadcastf32x2\0" "vbroadcastf32x4\0" "vbroadcastf32x8\0" "vbroadcastf64x2\0"
2759 "vbroadcastf64x4\0" "vbroadcasti128\0" "vbroadcasti32x2\0" "vbroadcasti32x4\0" "vbroadcasti32x8\0"
2760 "vbroadcasti64x2\0" "vbroadcasti64x4\0" "vbroadcastsd\0" "vbroadcastss\0" "vcmppd\0" "vcmpps\0" "vcmpsd\0" "vcmpss\0"
2761 "vcomisd\0" "vcomiss\0" "vcompresspd\0" "vcompressps\0" "vcvtdq2pd\0" "vcvtdq2ps\0" "vcvtne2ps2bf16\0"
2762 "vcvtneps2bf16\0" "vcvtpd2dq\0" "vcvtpd2ps\0" "vcvtpd2qq\0" "vcvtpd2udq\0" "vcvtpd2uqq\0" "vcvtph2ps\0" "vcvtps2dq\0"
2763 "vcvtps2pd\0" "vcvtps2ph\0" "vcvtps2qq\0" "vcvtps2udq\0" "vcvtps2uqq\0" "vcvtqq2pd\0" "vcvtqq2ps\0" "vcvtsd2si\0"
2764 "vcvtsd2ss\0" "vcvtsd2usi\0" "vcvtsi2sd\0" "vcvtsi2ss\0" "vcvtss2sd\0" "vcvtss2si\0" "vcvtss2usi\0" "vcvttpd2dq\0"
2765 "vcvttpd2qq\0" "vcvttpd2udq\0" "vcvttpd2uqq\0" "vcvttps2dq\0" "vcvttps2qq\0" "vcvttps2udq\0" "vcvttps2uqq\0"
2766 "vcvttsd2si\0" "vcvttsd2usi\0" "vcvttss2si\0" "vcvttss2usi\0" "vcvtudq2pd\0" "vcvtudq2ps\0" "vcvtuqq2pd\0"
2767 "vcvtuqq2ps\0" "vcvtusi2sd\0" "vcvtusi2ss\0" "vdbpsadbw\0" "vdivpd\0" "vdivps\0" "vdivsd\0" "vdivss\0" "vdpbf16ps\0"
2768 "vdppd\0" "vdpps\0" "verr\0" "verw\0" "vexp2pd\0" "vexp2ps\0" "vexpandpd\0" "vexpandps\0" "vextractf128\0"
2769 "vextractf32x4\0" "vextractf32x8\0" "vextractf64x2\0" "vextractf64x4\0" "vextracti128\0" "vextracti32x4\0"
2770 "vextracti32x8\0" "vextracti64x2\0" "vextracti64x4\0" "vextractps\0" "vfixupimmpd\0" "vfixupimmps\0" "vfixupimmsd\0"
2771 "vfixupimmss\0" "vfmadd132pd\0" "vfmadd132ps\0" "vfmadd132sd\0" "vfmadd132ss\0" "vfmadd213pd\0" "vfmadd213ps\0"
2772 "vfmadd213sd\0" "vfmadd213ss\0" "vfmadd231pd\0" "vfmadd231ps\0" "vfmadd231sd\0" "vfmadd231ss\0" "vfmaddpd\0"
2773 "vfmaddps\0" "vfmaddsd\0" "vfmaddss\0" "vfmaddsub132pd\0" "vfmaddsub132ps\0" "vfmaddsub213pd\0" "vfmaddsub213ps\0"
2774 "vfmaddsub231pd\0" "vfmaddsub231ps\0" "vfmaddsubpd\0" "vfmaddsubps\0" "vfmsub132pd\0" "vfmsub132ps\0" "vfmsub132sd\0"
2775 "vfmsub132ss\0" "vfmsub213pd\0" "vfmsub213ps\0" "vfmsub213sd\0" "vfmsub213ss\0" "vfmsub231pd\0" "vfmsub231ps\0"
2776 "vfmsub231sd\0" "vfmsub231ss\0" "vfmsubadd132pd\0" "vfmsubadd132ps\0" "vfmsubadd213pd\0" "vfmsubadd213ps\0"
2777 "vfmsubadd231pd\0" "vfmsubadd231ps\0" "vfmsubaddpd\0" "vfmsubaddps\0" "vfmsubpd\0" "vfmsubps\0" "vfmsubsd\0"
2778 "vfmsubss\0" "vfnmadd132pd\0" "vfnmadd132ps\0" "vfnmadd132sd\0" "vfnmadd132ss\0" "vfnmadd213pd\0" "vfnmadd213ps\0"
2779 "vfnmadd213sd\0" "vfnmadd213ss\0" "vfnmadd231pd\0" "vfnmadd231ps\0" "vfnmadd231sd\0" "vfnmadd231ss\0" "vfnmaddpd\0"
2780 "vfnmaddps\0" "vfnmaddsd\0" "vfnmaddss\0" "vfnmsub132pd\0" "vfnmsub132ps\0" "vfnmsub132sd\0" "vfnmsub132ss\0"
2781 "vfnmsub213pd\0" "vfnmsub213ps\0" "vfnmsub213sd\0" "vfnmsub213ss\0" "vfnmsub231pd\0" "vfnmsub231ps\0"
2782 "vfnmsub231sd\0" "vfnmsub231ss\0" "vfnmsubpd\0" "vfnmsubps\0" "vfnmsubsd\0" "vfnmsubss\0" "vfpclasspd\0"
2783 "vfpclassps\0" "vfpclasssd\0" "vfpclassss\0" "vfrczpd\0" "vfrczps\0" "vfrczsd\0" "vfrczss\0" "vgatherdpd\0"
2784 "vgatherdps\0" "vgatherpf0dpd\0" "vgatherpf0dps\0" "vgatherpf0qpd\0" "vgatherpf0qps\0" "vgatherpf1dpd\0"
2785 "vgatherpf1dps\0" "vgatherpf1qpd\0" "vgatherpf1qps\0" "vgatherqpd\0" "vgatherqps\0" "vgetexppd\0" "vgetexpps\0"
2786 "vgetexpsd\0" "vgetexpss\0" "vgetmantpd\0" "vgetmantps\0" "vgetmantsd\0" "vgetmantss\0" "vgf2p8affineinvqb\0"
2787 "vgf2p8affineqb\0" "vgf2p8mulb\0" "vhaddpd\0" "vhaddps\0" "vhsubpd\0" "vhsubps\0" "vinsertf128\0" "vinsertf32x4\0"
2788 "vinsertf32x8\0" "vinsertf64x2\0" "vinsertf64x4\0" "vinserti128\0" "vinserti32x4\0" "vinserti32x8\0" "vinserti64x2\0"
2789 "vinserti64x4\0" "vinsertps\0" "vlddqu\0" "vldmxcsr\0" "vmaskmovdqu\0" "vmaskmovpd\0" "vmaskmovps\0" "vmaxpd\0"
2790 "vmaxps\0" "vmaxsd\0" "vmaxss\0" "vmcall\0" "vmclear\0" "vmfunc\0" "vminpd\0" "vminps\0" "vminsd\0" "vminss\0"
2791 "vmlaunch\0" "vmload\0" "vmmcall\0" "vmovapd\0" "vmovaps\0" "vmovd\0" "vmovddup\0" "vmovdqa\0" "vmovdqa32\0"
2792 "vmovdqa64\0" "vmovdqu\0" "vmovdqu16\0" "vmovdqu32\0" "vmovdqu64\0" "vmovdqu8\0" "vmovhlps\0" "vmovhpd\0" "vmovhps\0"
2793 "vmovlhps\0" "vmovlpd\0" "vmovlps\0" "vmovmskpd\0" "vmovmskps\0" "vmovntdq\0" "vmovntdqa\0" "vmovntpd\0" "vmovntps\0"
2794 "vmovq\0" "vmovsd\0" "vmovshdup\0" "vmovsldup\0" "vmovss\0" "vmovupd\0" "vmovups\0" "vmpsadbw\0" "vmptrld\0"
2795 "vmptrst\0" "vmread\0" "vmresume\0" "vmrun\0" "vmsave\0" "vmulpd\0" "vmulps\0" "vmulsd\0" "vmulss\0" "vmwrite\0"
2796 "vmxon\0" "vorpd\0" "vorps\0" "vp2intersectd\0" "vp2intersectq\0" "vp4dpwssd\0" "vp4dpwssds\0" "vpabsb\0" "vpabsd\0"
2797 "vpabsq\0" "vpabsw\0" "vpackssdw\0" "vpacksswb\0" "vpackusdw\0" "vpackuswb\0" "vpaddb\0" "vpaddd\0" "vpaddq\0"
2798 "vpaddsb\0" "vpaddsw\0" "vpaddusb\0" "vpaddusw\0" "vpaddw\0" "vpalignr\0" "vpand\0" "vpandd\0" "vpandn\0" "vpandnd\0"
2799 "vpandnq\0" "vpandq\0" "vpavgb\0" "vpavgw\0" "vpblendd\0" "vpblendmb\0" "vpblendmd\0" "vpblendmq\0" "vpblendmw\0"
2800 "vpblendvb\0" "vpblendw\0" "vpbroadcastb\0" "vpbroadcastd\0" "vpbroadcastmb2q\0" "vpbroadcastmw2d\0" "vpbroadcastq\0"
2801 "vpbroadcastw\0" "vpclmulqdq\0" "vpcmov\0" "vpcmpb\0" "vpcmpd\0" "vpcmpeqb\0" "vpcmpeqd\0" "vpcmpeqq\0" "vpcmpeqw\0"
2802 "vpcmpestri\0" "vpcmpestrm\0" "vpcmpgtb\0" "vpcmpgtd\0" "vpcmpgtq\0" "vpcmpgtw\0" "vpcmpistri\0" "vpcmpistrm\0"
2803 "vpcmpq\0" "vpcmpub\0" "vpcmpud\0" "vpcmpuq\0" "vpcmpuw\0" "vpcmpw\0" "vpcomb\0" "vpcomd\0" "vpcompressb\0"
2804 "vpcompressd\0" "vpcompressq\0" "vpcompressw\0" "vpcomq\0" "vpcomub\0" "vpcomud\0" "vpcomuq\0" "vpcomuw\0" "vpcomw\0"
2805 "vpconflictd\0" "vpconflictq\0" "vpdpbusd\0" "vpdpbusds\0" "vpdpwssd\0" "vpdpwssds\0" "vperm2f128\0" "vperm2i128\0"
2806 "vpermb\0" "vpermd\0" "vpermi2b\0" "vpermi2d\0" "vpermi2pd\0" "vpermi2ps\0" "vpermi2q\0" "vpermi2w\0" "vpermil2pd\0"
2807 "vpermil2ps\0" "vpermilpd\0" "vpermilps\0" "vpermpd\0" "vpermps\0" "vpermq\0" "vpermt2b\0" "vpermt2d\0" "vpermt2pd\0"
2808 "vpermt2ps\0" "vpermt2q\0" "vpermt2w\0" "vpermw\0" "vpexpandb\0" "vpexpandd\0" "vpexpandq\0" "vpexpandw\0"
2809 "vpextrb\0" "vpextrd\0" "vpextrq\0" "vpextrw\0" "vpgatherdd\0" "vpgatherdq\0" "vpgatherqd\0" "vpgatherqq\0"
2810 "vphaddbd\0" "vphaddbq\0" "vphaddbw\0" "vphaddd\0" "vphadddq\0" "vphaddsw\0" "vphaddubd\0" "vphaddubq\0"
2811 "vphaddubw\0" "vphaddudq\0" "vphadduwd\0" "vphadduwq\0" "vphaddw\0" "vphaddwd\0" "vphaddwq\0" "vphminposuw\0"
2812 "vphsubbw\0" "vphsubd\0" "vphsubdq\0" "vphsubsw\0" "vphsubw\0" "vphsubwd\0" "vpinsrb\0" "vpinsrd\0" "vpinsrq\0"
2813 "vpinsrw\0" "vplzcntd\0" "vplzcntq\0" "vpmacsdd\0" "vpmacsdqh\0" "vpmacsdql\0" "vpmacssdd\0" "vpmacssdqh\0"
2814 "vpmacssdql\0" "vpmacsswd\0" "vpmacssww\0" "vpmacswd\0" "vpmacsww\0" "vpmadcsswd\0" "vpmadcswd\0" "vpmadd52huq\0"
2815 "vpmadd52luq\0" "vpmaddubsw\0" "vpmaddwd\0" "vpmaskmovd\0" "vpmaskmovq\0" "vpmaxsb\0" "vpmaxsd\0" "vpmaxsq\0"
2816 "vpmaxsw\0" "vpmaxub\0" "vpmaxud\0" "vpmaxuq\0" "vpmaxuw\0" "vpminsb\0" "vpminsd\0" "vpminsq\0" "vpminsw\0"
2817 "vpminub\0" "vpminud\0" "vpminuq\0" "vpminuw\0" "vpmovb2m\0" "vpmovd2m\0" "vpmovdb\0" "vpmovdw\0" "vpmovm2b\0"
2818 "vpmovm2d\0" "vpmovm2q\0" "vpmovm2w\0" "vpmovmskb\0" "vpmovq2m\0" "vpmovqb\0" "vpmovqd\0" "vpmovqw\0" "vpmovsdb\0"
2819 "vpmovsdw\0" "vpmovsqb\0" "vpmovsqd\0" "vpmovsqw\0" "vpmovswb\0" "vpmovsxbd\0" "vpmovsxbq\0" "vpmovsxbw\0"
2820 "vpmovsxdq\0" "vpmovsxwd\0" "vpmovsxwq\0" "vpmovusdb\0" "vpmovusdw\0" "vpmovusqb\0" "vpmovusqd\0" "vpmovusqw\0"
2821 "vpmovuswb\0" "vpmovw2m\0" "vpmovwb\0" "vpmovzxbd\0" "vpmovzxbq\0" "vpmovzxbw\0" "vpmovzxdq\0" "vpmovzxwd\0"
2822 "vpmovzxwq\0" "vpmuldq\0" "vpmulhrsw\0" "vpmulhuw\0" "vpmulhw\0" "vpmulld\0" "vpmullq\0" "vpmullw\0"
2823 "vpmultishiftqb\0" "vpmuludq\0" "vpopcntb\0" "vpopcntd\0" "vpopcntq\0" "vpopcntw\0" "vpor\0" "vpord\0" "vporq\0"
2824 "vpperm\0" "vprold\0" "vprolq\0" "vprolvd\0" "vprolvq\0" "vprord\0" "vprorq\0" "vprorvd\0" "vprorvq\0" "vprotb\0"
2825 "vprotd\0" "vprotq\0" "vprotw\0" "vpsadbw\0" "vpscatterdd\0" "vpscatterdq\0" "vpscatterqd\0" "vpscatterqq\0"
2826 "vpshab\0" "vpshad\0" "vpshaq\0" "vpshaw\0" "vpshlb\0" "vpshld\0" "vpshldd\0" "vpshldq\0" "vpshldvd\0" "vpshldvq\0"
2827 "vpshldvw\0" "vpshldw\0" "vpshlq\0" "vpshlw\0" "vpshrdd\0" "vpshrdq\0" "vpshrdvd\0" "vpshrdvq\0" "vpshrdvw\0"
2828 "vpshrdw\0" "vpshufb\0" "vpshufbitqmb\0" "vpshufd\0" "vpshufhw\0" "vpshuflw\0" "vpsignb\0" "vpsignd\0" "vpsignw\0"
2829 "vpslld\0" "vpslldq\0" "vpsllq\0" "vpsllvd\0" "vpsllvq\0" "vpsllvw\0" "vpsllw\0" "vpsrad\0" "vpsraq\0" "vpsravd\0"
2830 "vpsravq\0" "vpsravw\0" "vpsraw\0" "vpsrld\0" "vpsrldq\0" "vpsrlq\0" "vpsrlvd\0" "vpsrlvq\0" "vpsrlvw\0" "vpsrlw\0"
2831 "vpsubb\0" "vpsubd\0" "vpsubq\0" "vpsubsb\0" "vpsubsw\0" "vpsubusb\0" "vpsubusw\0" "vpsubw\0" "vpternlogd\0"
2832 "vpternlogq\0" "vptest\0" "vptestmb\0" "vptestmd\0" "vptestmq\0" "vptestmw\0" "vptestnmb\0" "vptestnmd\0"
2833 "vptestnmq\0" "vptestnmw\0" "vpunpckhbw\0" "vpunpckhdq\0" "vpunpckhqdq\0" "vpunpckhwd\0" "vpunpcklbw\0"
2834 "vpunpckldq\0" "vpunpcklqdq\0" "vpunpcklwd\0" "vpxor\0" "vpxord\0" "vpxorq\0" "vrangepd\0" "vrangeps\0" "vrangesd\0"
2835 "vrangess\0" "vrcp14pd\0" "vrcp14ps\0" "vrcp14sd\0" "vrcp14ss\0" "vrcp28pd\0" "vrcp28ps\0" "vrcp28sd\0" "vrcp28ss\0"
2836 "vrcpps\0" "vrcpss\0" "vreducepd\0" "vreduceps\0" "vreducesd\0" "vreducess\0" "vrndscalepd\0" "vrndscaleps\0"
2837 "vrndscalesd\0" "vrndscaless\0" "vroundpd\0" "vroundps\0" "vroundsd\0" "vroundss\0" "vrsqrt14pd\0" "vrsqrt14ps\0"
2838 "vrsqrt14sd\0" "vrsqrt14ss\0" "vrsqrt28pd\0" "vrsqrt28ps\0" "vrsqrt28sd\0" "vrsqrt28ss\0" "vrsqrtps\0" "vrsqrtss\0"
2839 "vscalefpd\0" "vscalefps\0" "vscalefsd\0" "vscalefss\0" "vscatterdpd\0" "vscatterdps\0" "vscatterpf0dpd\0"
2840 "vscatterpf0dps\0" "vscatterpf0qpd\0" "vscatterpf0qps\0" "vscatterpf1dpd\0" "vscatterpf1dps\0" "vscatterpf1qpd\0"
2841 "vscatterpf1qps\0" "vscatterqpd\0" "vscatterqps\0" "vshuff32x4\0" "vshuff64x2\0" "vshufi32x4\0" "vshufi64x2\0"
2842 "vshufpd\0" "vshufps\0" "vsqrtpd\0" "vsqrtps\0" "vsqrtsd\0" "vsqrtss\0" "vstmxcsr\0" "vsubpd\0" "vsubps\0" "vsubsd\0"
2843 "vsubss\0" "vtestpd\0" "vtestps\0" "vucomisd\0" "vucomiss\0" "vunpckhpd\0" "vunpckhps\0" "vunpcklpd\0" "vunpcklps\0"
2844 "vxorpd\0" "vxorps\0" "vzeroall\0" "vzeroupper\0" "wbinvd\0" "wbnoinvd\0" "wrfsbase\0" "wrgsbase\0" "wrmsr\0"
2845 "wrssd\0" "wrssq\0" "wrussd\0" "wrussq\0" "xabort\0" "xadd\0" "xbegin\0" "xend\0" "xgetbv\0" "xlatb\0" "xresldtrk\0"
2846 "xrstors\0" "xrstors64\0" "xsavec\0" "xsavec64\0" "xsaveopt\0" "xsaveopt64\0" "xsaves\0" "xsaves64\0" "xsetbv\0"
2847 "xsusldtrk\0" "xtest";
2848
2849 const InstDB::InstNameIndex InstDB::instNameIndex[26] = {
2850 { Inst::kIdAaa , Inst::kIdArpl + 1 },
2851 { Inst::kIdBextr , Inst::kIdBzhi + 1 },
2852 { Inst::kIdCall , Inst::kIdCwde + 1 },
2853 { Inst::kIdDaa , Inst::kIdDpps + 1 },
2854 { Inst::kIdEmms , Inst::kIdExtrq + 1 },
2855 { Inst::kIdF2xm1 , Inst::kIdFyl2xp1 + 1 },
2856 { Inst::kIdGetsec , Inst::kIdGf2p8mulb + 1 },
2857 { Inst::kIdHaddpd , Inst::kIdHsubps + 1 },
2858 { Inst::kIdIdiv , Inst::kIdIretq + 1 },
2859 { Inst::kIdJa , Inst::kIdJz + 1 },
2860 { Inst::kIdKaddb , Inst::kIdKxorw + 1 },
2861 { Inst::kIdLahf , Inst::kIdLzcnt + 1 },
2862 { Inst::kIdMaskmovdqu , Inst::kIdMwaitx + 1 },
2863 { Inst::kIdNeg , Inst::kIdNot + 1 },
2864 { Inst::kIdOr , Inst::kIdOuts + 1 },
2865 { Inst::kIdPabsb , Inst::kIdPxor + 1 },
2866 { Inst::kIdNone , Inst::kIdNone + 1 },
2867 { Inst::kIdRcl , Inst::kIdRstorssp + 1 },
2868 { Inst::kIdSahf , Inst::kIdSysretq + 1 },
2869 { Inst::kIdT1mskc , Inst::kIdTzmsk + 1 },
2870 { Inst::kIdUcomisd , Inst::kIdUnpcklps + 1 },
2871 { Inst::kIdV4fmaddps , Inst::kIdVzeroupper + 1 },
2872 { Inst::kIdWbinvd , Inst::kIdWrussq + 1 },
2873 { Inst::kIdXabort , Inst::kIdXtest + 1 },
2874 { Inst::kIdNone , Inst::kIdNone + 1 },
2875 { Inst::kIdNone , Inst::kIdNone + 1 }
2876 };
2877 // ----------------------------------------------------------------------------
2878 // ${NameData:End}
2879 #endif // !ASMJIT_NO_TEXT
2880
2881 // ============================================================================
2882 // [asmjit::x86::InstDB - InstSignature / OpSignature]
2883 // ============================================================================
2884
2885 #ifndef ASMJIT_NO_VALIDATION
2886 // ${InstSignatureTable:Begin}
2887 // ------------------- Automatically generated, do not edit -------------------
2888 #define ROW(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \
2889 { count, (x86 ? uint8_t(InstDB::kModeX86) : uint8_t(0)) | \
2890 (x64 ? uint8_t(InstDB::kModeX64) : uint8_t(0)) , \
2891 implicit, \
2892 0, \
2893 { o0, o1, o2, o3, o4, o5 } \
2894 }
2895 const InstDB::InstSignature InstDB::_instSignatureTable[] = {
2896 ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #0 {r8lo|r8hi|m8|mem, r8lo|r8hi}
2897 ROW(2, 1, 1, 0, 3 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem|sreg, r16}
2898 ROW(2, 1, 1, 0, 5 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem|sreg, r32}
2899 ROW(2, 0, 1, 0, 7 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem|sreg|creg|dreg, r64}
2900 ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8, i8|u8}
2901 ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16}
2902 ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32}
2903 ROW(2, 0, 1, 0, 15 , 16 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, i32}
2904 ROW(2, 0, 1, 0, 8 , 17 , 0 , 0 , 0 , 0 ), // {r64, i64|u64|m64|mem|sreg|creg|dreg}
2905 ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem}
2906 ROW(2, 1, 1, 0, 4 , 19 , 0 , 0 , 0 , 0 ), // {r16, m16|mem|sreg}
2907 ROW(2, 1, 1, 0, 6 , 20 , 0 , 0 , 0 , 0 ), // {r32, m32|mem|sreg}
2908 ROW(2, 1, 1, 0, 21 , 22 , 0 , 0 , 0 , 0 ), // {m16|mem, sreg}
2909 ROW(2, 1, 1, 0, 22 , 21 , 0 , 0 , 0 , 0 ), // {sreg, m16|mem}
2910 ROW(2, 1, 0, 0, 6 , 23 , 0 , 0 , 0 , 0 ), // {r32, creg|dreg}
2911 ROW(2, 1, 0, 0, 23 , 6 , 0 , 0 , 0 , 0 ), // {creg|dreg, r32}
2912 ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // #16 {r8lo|r8hi|m8, i8|u8}
2913 ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16}
2914 ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32}
2915 ROW(2, 0, 1, 0, 15 , 24 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, i32|r64}
2916 ROW(2, 1, 1, 0, 25 , 26 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32|r64|m64|mem, i8}
2917 ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8|mem, r8lo|r8hi}
2918 ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16}
2919 ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // #23 {r32|m32|mem, r32}
2920 ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem}
2921 ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem}
2922 ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem}
2923 ROW(2, 0, 1, 0, 8 , 30 , 0 , 0 , 0 , 0 ), // {r64, m64|mem}
2924 ROW(2, 1, 1, 0, 31 , 10 , 0 , 0 , 0 , 0 ), // #28 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, i8|u8}
2925 ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16}
2926 ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32}
2927 ROW(2, 0, 1, 0, 8 , 32 , 0 , 0 , 0 , 0 ), // {r64, u32|i32|r64|m64|mem}
2928 ROW(2, 0, 1, 0, 30 , 24 , 0 , 0 , 0 , 0 ), // {m64|mem, i32|r64}
2929 ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8|mem, r8lo|r8hi}
2930 ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16}
2931 ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32}
2932 ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem}
2933 ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem}
2934 ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem}
2935 ROW(2, 1, 1, 1, 33 , 1 , 0 , 0 , 0 , 0 ), // #39 {<ax>, r8lo|r8hi|m8|mem}
2936 ROW(3, 1, 1, 2, 34 , 33 , 27 , 0 , 0 , 0 ), // {<dx>, <ax>, r16|m16|mem}
2937 ROW(3, 1, 1, 2, 35 , 36 , 28 , 0 , 0 , 0 ), // {<edx>, <eax>, r32|m32|mem}
2938 ROW(3, 0, 1, 2, 37 , 38 , 15 , 0 , 0 , 0 ), // {<rdx>, <rax>, r64|m64|mem}
2939 ROW(2, 1, 1, 0, 4 , 39 , 0 , 0 , 0 , 0 ), // {r16, r16|m16|mem|i8|i16}
2940 ROW(2, 1, 1, 0, 6 , 40 , 0 , 0 , 0 , 0 ), // {r32, r32|m32|mem|i8|i32}
2941 ROW(2, 0, 1, 0, 8 , 41 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem|i8|i32}
2942 ROW(3, 1, 1, 0, 4 , 27 , 42 , 0 , 0 , 0 ), // {r16, r16|m16|mem, i8|i16|u16}
2943 ROW(3, 1, 1, 0, 6 , 28 , 43 , 0 , 0 , 0 ), // {r32, r32|m32|mem, i8|i32|u32}
2944 ROW(3, 0, 1, 0, 8 , 15 , 44 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|i32}
2945 ROW(2, 0, 1, 0, 8 , 45 , 0 , 0 , 0 , 0 ), // #49 {r64, i64|u64}
2946 ROW(2, 0, 1, 0, 46 , 18 , 0 , 0 , 0 , 0 ), // {al, m8|mem}
2947 ROW(2, 0, 1, 0, 47 , 21 , 0 , 0 , 0 , 0 ), // {ax, m16|mem}
2948 ROW(2, 0, 1, 0, 48 , 29 , 0 , 0 , 0 , 0 ), // {eax, m32|mem}
2949 ROW(2, 0, 1, 0, 49 , 30 , 0 , 0 , 0 , 0 ), // {rax, m64|mem}
2950 ROW(2, 0, 1, 0, 18 , 46 , 0 , 0 , 0 , 0 ), // {m8|mem, al}
2951 ROW(2, 0, 1, 0, 21 , 47 , 0 , 0 , 0 , 0 ), // {m16|mem, ax}
2952 ROW(2, 0, 1, 0, 29 , 48 , 0 , 0 , 0 , 0 ), // {m32|mem, eax}
2953 ROW(2, 0, 1, 0, 30 , 49 , 0 , 0 , 0 , 0 ), // {m64|mem, rax}
2954 ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #58 {r8lo|r8hi|m8|mem, r8lo|r8hi}
2955 ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16}
2956 ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32}
2957 ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // #61 {r64|m64|mem, r64}
2958 ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem}
2959 ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem}
2960 ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem}
2961 ROW(2, 0, 1, 0, 8 , 30 , 0 , 0 , 0 , 0 ), // {r64, m64|mem}
2962 ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // #66 {r8lo|r8hi|m8, i8|u8}
2963 ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16}
2964 ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32}
2965 ROW(2, 0, 1, 0, 15 , 24 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, i32|r64}
2966 ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8|mem, r8lo|r8hi}
2967 ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16}
2968 ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32}
2969 ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // #73 {r16, m16|mem}
2970 ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem}
2971 ROW(2, 0, 1, 0, 8 , 30 , 0 , 0 , 0 , 0 ), // {r64, m64|mem}
2972 ROW(2, 1, 1, 0, 21 , 4 , 0 , 0 , 0 , 0 ), // {m16|mem, r16}
2973 ROW(2, 1, 1, 0, 29 , 6 , 0 , 0 , 0 , 0 ), // #77 {m32|mem, r32}
2974 ROW(2, 0, 1, 0, 30 , 8 , 0 , 0 , 0 , 0 ), // {m64|mem, r64}
2975 ROW(2, 1, 1, 0, 50 , 51 , 0 , 0 , 0 , 0 ), // #79 {xmm, xmm|m128|mem}
2976 ROW(2, 1, 1, 0, 52 , 50 , 0 , 0 , 0 , 0 ), // #80 {m128|mem, xmm}
2977 ROW(2, 1, 1, 0, 53 , 54 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem}
2978 ROW(2, 1, 1, 0, 55 , 53 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm}
2979 ROW(2, 1, 1, 0, 56 , 57 , 0 , 0 , 0 , 0 ), // #83 {zmm, zmm|m512|mem}
2980 ROW(2, 1, 1, 0, 58 , 56 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm}
2981 ROW(3, 1, 1, 0, 50 , 50 , 59 , 0 , 0 , 0 ), // #85 {xmm, xmm, xmm|m128|mem|i8|u8}
2982 ROW(3, 1, 1, 0, 50 , 52 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8}
2983 ROW(3, 1, 1, 0, 53 , 53 , 60 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem|i8|u8}
2984 ROW(3, 1, 1, 0, 53 , 55 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8}
2985 ROW(3, 1, 1, 0, 56 , 56 , 61 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8}
2986 ROW(3, 1, 1, 0, 56 , 58 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8}
2987 ROW(3, 1, 1, 0, 50 , 50 , 59 , 0 , 0 , 0 ), // #91 {xmm, xmm, i8|u8|xmm|m128|mem}
2988 ROW(3, 1, 1, 0, 53 , 53 , 59 , 0 , 0 , 0 ), // {ymm, ymm, i8|u8|xmm|m128|mem}
2989 ROW(3, 1, 1, 0, 50 , 52 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8}
2990 ROW(3, 1, 1, 0, 53 , 55 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8}
2991 ROW(3, 1, 1, 0, 56 , 56 , 59 , 0 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem|i8|u8}
2992 ROW(3, 1, 1, 0, 56 , 58 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8}
2993 ROW(3, 1, 1, 0, 50 , 50 , 59 , 0 , 0 , 0 ), // #97 {xmm, xmm, xmm|m128|mem|i8|u8}
2994 ROW(3, 1, 1, 0, 50 , 52 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8}
2995 ROW(3, 1, 1, 0, 53 , 53 , 59 , 0 , 0 , 0 ), // {ymm, ymm, xmm|m128|mem|i8|u8}
2996 ROW(3, 1, 1, 0, 53 , 55 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8}
2997 ROW(3, 1, 1, 0, 56 , 56 , 59 , 0 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem|i8|u8}
2998 ROW(3, 1, 1, 0, 56 , 58 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8}
2999 ROW(2, 1, 1, 0, 62 , 63 , 0 , 0 , 0 , 0 ), // #103 {mm, mm|m64|mem|r64}
3000 ROW(2, 1, 1, 0, 15 , 64 , 0 , 0 , 0 , 0 ), // {m64|mem|r64, mm|xmm}
3001 ROW(2, 0, 1, 0, 50 , 15 , 0 , 0 , 0 , 0 ), // {xmm, r64|m64|mem}
3002 ROW(2, 1, 1, 0, 50 , 65 , 0 , 0 , 0 , 0 ), // #106 {xmm, xmm|m64|mem}
3003 ROW(2, 1, 1, 0, 30 , 50 , 0 , 0 , 0 , 0 ), // #107 {m64|mem, xmm}
3004 ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #108 {}
3005 ROW(1, 1, 1, 0, 66 , 0 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32|r64|m64}
3006 ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16}
3007 ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32}
3008 ROW(2, 1, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64}
3009 ROW(3, 1, 1, 0, 50 , 67 , 50 , 0 , 0 , 0 ), // #113 {xmm, vm32x, xmm}
3010 ROW(3, 1, 1, 0, 53 , 68 , 53 , 0 , 0 , 0 ), // {ymm, vm32y, ymm}
3011 ROW(2, 1, 1, 0, 50 , 67 , 0 , 0 , 0 , 0 ), // {xmm, vm32x}
3012 ROW(2, 1, 1, 0, 53 , 68 , 0 , 0 , 0 , 0 ), // {ymm, vm32y}
3013 ROW(2, 1, 1, 0, 56 , 69 , 0 , 0 , 0 , 0 ), // {zmm, vm32z}
3014 ROW(3, 1, 1, 0, 50 , 70 , 50 , 0 , 0 , 0 ), // #118 {xmm, vm64x, xmm}
3015 ROW(3, 1, 1, 0, 53 , 71 , 53 , 0 , 0 , 0 ), // {ymm, vm64y, ymm}
3016 ROW(2, 1, 1, 0, 50 , 70 , 0 , 0 , 0 , 0 ), // {xmm, vm64x}
3017 ROW(2, 1, 1, 0, 53 , 71 , 0 , 0 , 0 , 0 ), // {ymm, vm64y}
3018 ROW(2, 1, 1, 0, 56 , 72 , 0 , 0 , 0 , 0 ), // {zmm, vm64z}
3019 ROW(2, 1, 1, 0, 25 , 10 , 0 , 0 , 0 , 0 ), // #123 {r16|m16|r32|m32|r64|m64|mem, i8|u8}
3020 ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16}
3021 ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32}
3022 ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64}
3023 ROW(2, 1, 1, 2, 73 , 74 , 0 , 0 , 0 , 0 ), // #127 {<ds:[m8|memBase|zsi]>, <es:[m8|memBase|zdi]>}
3024 ROW(2, 1, 1, 2, 75 , 76 , 0 , 0 , 0 , 0 ), // {<ds:[m16|memBase|zsi]>, <es:[m16|memBase|zdi]>}
3025 ROW(2, 1, 1, 2, 77 , 78 , 0 , 0 , 0 , 0 ), // {<ds:[m32|memBase|zsi]>, <es:[m32|memBase|zdi]>}
3026 ROW(2, 0, 1, 2, 79 , 80 , 0 , 0 , 0 , 0 ), // {<ds:[m64|memBase|zsi]>, <es:[m64|memBase|zdi]>}
3027 ROW(3, 1, 1, 1, 1 , 2 , 81 , 0 , 0 , 0 ), // #131 {r8lo|r8hi|m8|mem, r8lo|r8hi, <al>}
3028 ROW(3, 1, 1, 1, 27 , 4 , 33 , 0 , 0 , 0 ), // {r16|m16|mem, r16, <ax>}
3029 ROW(3, 1, 1, 1, 28 , 6 , 36 , 0 , 0 , 0 ), // {r32|m32|mem, r32, <eax>}
3030 ROW(3, 0, 1, 1, 15 , 8 , 38 , 0 , 0 , 0 ), // {r64|m64|mem, r64, <rax>}
3031 ROW(2, 1, 1, 2, 81 , 82 , 0 , 0 , 0 , 0 ), // #135 {<al>, <ds:[m8|memBase|zsi|mem]>}
3032 ROW(2, 1, 1, 2, 33 , 83 , 0 , 0 , 0 , 0 ), // {<ax>, <ds:[m16|memBase|zsi|mem]>}
3033 ROW(2, 1, 1, 2, 36 , 84 , 0 , 0 , 0 , 0 ), // {<eax>, <ds:[m32|memBase|zsi|mem]>}
3034 ROW(2, 0, 1, 2, 38 , 85 , 0 , 0 , 0 , 0 ), // {<rax>, <ds:[m64|memBase|zsi|mem]>}
3035 ROW(2, 1, 1, 2, 74 , 73 , 0 , 0 , 0 , 0 ), // #139 {<es:[m8|memBase|zdi]>, <ds:[m8|memBase|zsi]>}
3036 ROW(2, 1, 1, 2, 76 , 75 , 0 , 0 , 0 , 0 ), // {<es:[m16|memBase|zdi]>, <ds:[m16|memBase|zsi]>}
3037 ROW(2, 1, 1, 2, 78 , 77 , 0 , 0 , 0 , 0 ), // {<es:[m32|memBase|zdi]>, <ds:[m32|memBase|zsi]>}
3038 ROW(2, 0, 1, 2, 80 , 79 , 0 , 0 , 0 , 0 ), // {<es:[m64|memBase|zdi]>, <ds:[m64|memBase|zsi]>}
3039 ROW(1, 1, 1, 0, 86 , 0 , 0 , 0 , 0 , 0 ), // #143 {r16|m16|r64|m64}
3040 ROW(1, 1, 0, 0, 13 , 0 , 0 , 0 , 0 , 0 ), // {r32|m32}
3041 ROW(1, 1, 0, 0, 87 , 0 , 0 , 0 , 0 , 0 ), // {ds|es|ss}
3042 ROW(1, 1, 1, 0, 88 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs}
3043 ROW(1, 1, 1, 0, 89 , 0 , 0 , 0 , 0 , 0 ), // #147 {r16|m16|r64|m64|i8|i16|i32}
3044 ROW(1, 1, 0, 0, 90 , 0 , 0 , 0 , 0 , 0 ), // {r32|m32|i32|u32}
3045 ROW(1, 1, 0, 0, 91 , 0 , 0 , 0 , 0 , 0 ), // {cs|ss|ds|es}
3046 ROW(1, 1, 1, 0, 88 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs}
3047 ROW(2, 1, 1, 2, 81 , 92 , 0 , 0 , 0 , 0 ), // #151 {<al>, <es:[m8|memBase|zdi|mem]>}
3048 ROW(2, 1, 1, 2, 33 , 93 , 0 , 0 , 0 , 0 ), // {<ax>, <es:[m16|memBase|zdi|mem]>}
3049 ROW(2, 1, 1, 2, 36 , 94 , 0 , 0 , 0 , 0 ), // {<eax>, <es:[m32|memBase|zdi|mem]>}
3050 ROW(2, 0, 1, 2, 38 , 95 , 0 , 0 , 0 , 0 ), // {<rax>, <es:[m64|memBase|zdi|mem]>}
3051 ROW(2, 1, 1, 2, 92 , 81 , 0 , 0 , 0 , 0 ), // #155 {<es:[m8|memBase|zdi|mem]>, <al>}
3052 ROW(2, 1, 1, 2, 93 , 33 , 0 , 0 , 0 , 0 ), // {<es:[m16|memBase|zdi|mem]>, <ax>}
3053 ROW(2, 1, 1, 2, 94 , 36 , 0 , 0 , 0 , 0 ), // {<es:[m32|memBase|zdi|mem]>, <eax>}
3054 ROW(2, 0, 1, 2, 95 , 38 , 0 , 0 , 0 , 0 ), // {<es:[m64|memBase|zdi|mem]>, <rax>}
3055 ROW(4, 1, 1, 0, 50 , 50 , 50 , 51 , 0 , 0 ), // #159 {xmm, xmm, xmm, xmm|m128|mem}
3056 ROW(4, 1, 1, 0, 50 , 50 , 52 , 50 , 0 , 0 ), // {xmm, xmm, m128|mem, xmm}
3057 ROW(4, 1, 1, 0, 53 , 53 , 53 , 54 , 0 , 0 ), // {ymm, ymm, ymm, ymm|m256|mem}
3058 ROW(4, 1, 1, 0, 53 , 53 , 55 , 53 , 0 , 0 ), // {ymm, ymm, m256|mem, ymm}
3059 ROW(3, 1, 1, 0, 50 , 67 , 50 , 0 , 0 , 0 ), // #163 {xmm, vm32x, xmm}
3060 ROW(3, 1, 1, 0, 53 , 67 , 53 , 0 , 0 , 0 ), // {ymm, vm32x, ymm}
3061 ROW(2, 1, 1, 0, 96 , 67 , 0 , 0 , 0 , 0 ), // {xmm|ymm, vm32x}
3062 ROW(2, 1, 1, 0, 56 , 68 , 0 , 0 , 0 , 0 ), // {zmm, vm32y}
3063 ROW(3, 1, 1, 0, 52 , 50 , 50 , 0 , 0 , 0 ), // #167 {m128|mem, xmm, xmm}
3064 ROW(3, 1, 1, 0, 55 , 53 , 53 , 0 , 0 , 0 ), // {m256|mem, ymm, ymm}
3065 ROW(3, 1, 1, 0, 50 , 50 , 52 , 0 , 0 , 0 ), // {xmm, xmm, m128|mem}
3066 ROW(3, 1, 1, 0, 53 , 53 , 55 , 0 , 0 , 0 ), // {ymm, ymm, m256|mem}
3067 ROW(5, 1, 1, 0, 50 , 50 , 51 , 50 , 97 , 0 ), // #171 {xmm, xmm, xmm|m128|mem, xmm, i4|u4}
3068 ROW(5, 1, 1, 0, 50 , 50 , 50 , 52 , 97 , 0 ), // {xmm, xmm, xmm, m128|mem, i4|u4}
3069 ROW(5, 1, 1, 0, 53 , 53 , 54 , 53 , 97 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm, i4|u4}
3070 ROW(5, 1, 1, 0, 53 , 53 , 53 , 55 , 97 , 0 ), // {ymm, ymm, ymm, m256|mem, i4|u4}
3071 ROW(3, 1, 1, 0, 53 , 54 , 10 , 0 , 0 , 0 ), // #175 {ymm, ymm|m256|mem, i8|u8}
3072 ROW(3, 1, 1, 0, 53 , 53 , 54 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem}
3073 ROW(3, 1, 1, 0, 56 , 56 , 61 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8}
3074 ROW(3, 1, 1, 0, 56 , 58 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8}
3075 ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #179 {r16, r16|m16|mem}
3076 ROW(2, 1, 1, 0, 6 , 28 , 0 , 0 , 0 , 0 ), // #180 {r32, r32|m32|mem}
3077 ROW(2, 0, 1, 0, 8 , 15 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem}
3078 ROW(1, 1, 1, 0, 98 , 0 , 0 , 0 , 0 , 0 ), // #182 {m32|m64}
3079 ROW(2, 1, 1, 0, 99 , 100, 0 , 0 , 0 , 0 ), // {st0, st}
3080 ROW(2, 1, 1, 0, 100, 99 , 0 , 0 , 0 , 0 ), // {st, st0}
3081 ROW(2, 1, 1, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #185 {r16, m32|mem}
3082 ROW(2, 1, 1, 0, 6 , 101, 0 , 0 , 0 , 0 ), // {r32, m48|mem}
3083 ROW(2, 0, 1, 0, 8 , 102, 0 , 0 , 0 , 0 ), // {r64, m80|mem}
3084 ROW(3, 1, 1, 0, 27 , 4 , 103, 0 , 0 , 0 ), // #188 {r16|m16|mem, r16, cl|i8|u8}
3085 ROW(3, 1, 1, 0, 28 , 6 , 103, 0 , 0 , 0 ), // {r32|m32|mem, r32, cl|i8|u8}
3086 ROW(3, 0, 1, 0, 15 , 8 , 103, 0 , 0 , 0 ), // {r64|m64|mem, r64, cl|i8|u8}
3087 ROW(3, 1, 1, 0, 50 , 50 , 51 , 0 , 0 , 0 ), // #191 {xmm, xmm, xmm|m128|mem}
3088 ROW(3, 1, 1, 0, 53 , 53 , 54 , 0 , 0 , 0 ), // #192 {ymm, ymm, ymm|m256|mem}
3089 ROW(3, 1, 1, 0, 56 , 56 , 57 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem}
3090 ROW(4, 1, 1, 0, 50 , 50 , 51 , 10 , 0 , 0 ), // #194 {xmm, xmm, xmm|m128|mem, i8|u8}
3091 ROW(4, 1, 1, 0, 53 , 53 , 54 , 10 , 0 , 0 ), // #195 {ymm, ymm, ymm|m256|mem, i8|u8}
3092 ROW(4, 1, 1, 0, 56 , 56 , 57 , 10 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem, i8|u8}
3093 ROW(4, 1, 1, 0, 104, 50 , 51 , 10 , 0 , 0 ), // #197 {xmm|k, xmm, xmm|m128|mem, i8|u8}
3094 ROW(4, 1, 1, 0, 105, 53 , 54 , 10 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem, i8|u8}
3095 ROW(4, 1, 1, 0, 106, 56 , 57 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8}
3096 ROW(2, 1, 1, 0, 51 , 50 , 0 , 0 , 0 , 0 ), // #200 {xmm|m128|mem, xmm}
3097 ROW(2, 1, 1, 0, 54 , 53 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, ymm}
3098 ROW(2, 1, 1, 0, 57 , 56 , 0 , 0 , 0 , 0 ), // {zmm|m512|mem, zmm}
3099 ROW(2, 1, 1, 0, 50 , 65 , 0 , 0 , 0 , 0 ), // #203 {xmm, xmm|m64|mem}
3100 ROW(2, 1, 1, 0, 53 , 51 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m128|mem}
3101 ROW(2, 1, 1, 0, 56 , 54 , 0 , 0 , 0 , 0 ), // {zmm, ymm|m256|mem}
3102 ROW(2, 1, 1, 0, 50 , 51 , 0 , 0 , 0 , 0 ), // #206 {xmm, xmm|m128|mem}
3103 ROW(2, 1, 1, 0, 53 , 54 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem}
3104 ROW(2, 1, 1, 0, 56 , 57 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem}
3105 ROW(3, 1, 1, 0, 65 , 50 , 10 , 0 , 0 , 0 ), // #209 {xmm|m64|mem, xmm, i8|u8}
3106 ROW(3, 1, 1, 0, 51 , 53 , 10 , 0 , 0 , 0 ), // #210 {xmm|m128|mem, ymm, i8|u8}
3107 ROW(3, 1, 1, 0, 54 , 56 , 10 , 0 , 0 , 0 ), // #211 {ymm|m256|mem, zmm, i8|u8}
3108 ROW(3, 1, 1, 0, 50 , 107, 50 , 0 , 0 , 0 ), // #212 {xmm, vm64x|vm64y, xmm}
3109 ROW(2, 1, 1, 0, 50 , 107, 0 , 0 , 0 , 0 ), // {xmm, vm64x|vm64y}
3110 ROW(2, 1, 1, 0, 53 , 72 , 0 , 0 , 0 , 0 ), // {ymm, vm64z}
3111 ROW(3, 1, 1, 0, 50 , 51 , 10 , 0 , 0 , 0 ), // #215 {xmm, xmm|m128|mem, i8|u8}
3112 ROW(3, 1, 1, 0, 53 , 54 , 10 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem, i8|u8}
3113 ROW(3, 1, 1, 0, 56 , 57 , 10 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem, i8|u8}
3114 ROW(2, 1, 1, 0, 50 , 65 , 0 , 0 , 0 , 0 ), // #218 {xmm, xmm|m64|mem}
3115 ROW(2, 1, 1, 0, 53 , 54 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem}
3116 ROW(2, 1, 1, 0, 56 , 57 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem}
3117 ROW(2, 1, 1, 0, 52 , 50 , 0 , 0 , 0 , 0 ), // #221 {m128|mem, xmm}
3118 ROW(2, 1, 1, 0, 55 , 53 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm}
3119 ROW(2, 1, 1, 0, 58 , 56 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm}
3120 ROW(2, 1, 1, 0, 50 , 52 , 0 , 0 , 0 , 0 ), // #224 {xmm, m128|mem}
3121 ROW(2, 1, 1, 0, 53 , 55 , 0 , 0 , 0 , 0 ), // {ymm, m256|mem}
3122 ROW(2, 1, 1, 0, 56 , 58 , 0 , 0 , 0 , 0 ), // {zmm, m512|mem}
3123 ROW(2, 0, 1, 0, 15 , 50 , 0 , 0 , 0 , 0 ), // #227 {r64|m64|mem, xmm}
3124 ROW(2, 1, 1, 0, 50 , 108, 0 , 0 , 0 , 0 ), // {xmm, xmm|m64|mem|r64}
3125 ROW(2, 1, 1, 0, 30 , 50 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm}
3126 ROW(2, 1, 1, 0, 30 , 50 , 0 , 0 , 0 , 0 ), // #230 {m64|mem, xmm}
3127 ROW(2, 1, 1, 0, 50 , 30 , 0 , 0 , 0 , 0 ), // {xmm, m64|mem}
3128 ROW(3, 1, 1, 0, 50 , 50 , 50 , 0 , 0 , 0 ), // #232 {xmm, xmm, xmm}
3129 ROW(2, 1, 1, 0, 29 , 50 , 0 , 0 , 0 , 0 ), // #233 {m32|mem, xmm}
3130 ROW(2, 1, 1, 0, 50 , 29 , 0 , 0 , 0 , 0 ), // {xmm, m32|mem}
3131 ROW(3, 1, 1, 0, 50 , 50 , 50 , 0 , 0 , 0 ), // {xmm, xmm, xmm}
3132 ROW(4, 1, 1, 0, 106, 106, 50 , 51 , 0 , 0 ), // #236 {k, k, xmm, xmm|m128|mem}
3133 ROW(4, 1, 1, 0, 106, 106, 53 , 54 , 0 , 0 ), // {k, k, ymm, ymm|m256|mem}
3134 ROW(4, 1, 1, 0, 106, 106, 56 , 57 , 0 , 0 ), // {k, k, zmm, zmm|m512|mem}
3135 ROW(2, 1, 1, 0, 96 , 108, 0 , 0 , 0 , 0 ), // #239 {xmm|ymm, xmm|m64|mem|r64}
3136 ROW(2, 0, 1, 0, 56 , 8 , 0 , 0 , 0 , 0 ), // {zmm, r64}
3137 ROW(2, 1, 1, 0, 56 , 65 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem}
3138 ROW(4, 1, 1, 0, 106, 50 , 51 , 10 , 0 , 0 ), // #242 {k, xmm, xmm|m128|mem, i8|u8}
3139 ROW(4, 1, 1, 0, 106, 53 , 54 , 10 , 0 , 0 ), // {k, ymm, ymm|m256|mem, i8|u8}
3140 ROW(4, 1, 1, 0, 106, 56 , 57 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8}
3141 ROW(3, 1, 1, 0, 104, 50 , 51 , 0 , 0 , 0 ), // #245 {xmm|k, xmm, xmm|m128|mem}
3142 ROW(3, 1, 1, 0, 105, 53 , 54 , 0 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem}
3143 ROW(3, 1, 1, 0, 106, 56 , 57 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem}
3144 ROW(2, 1, 1, 0, 109, 50 , 0 , 0 , 0 , 0 ), // #248 {xmm|m32|mem, xmm}
3145 ROW(2, 1, 1, 0, 65 , 53 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, ymm}
3146 ROW(2, 1, 1, 0, 51 , 56 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, zmm}
3147 ROW(2, 1, 1, 0, 65 , 50 , 0 , 0 , 0 , 0 ), // #251 {xmm|m64|mem, xmm}
3148 ROW(2, 1, 1, 0, 51 , 53 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, ymm}
3149 ROW(2, 1, 1, 0, 54 , 56 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, zmm}
3150 ROW(2, 1, 1, 0, 110, 50 , 0 , 0 , 0 , 0 ), // #254 {xmm|m16|mem, xmm}
3151 ROW(2, 1, 1, 0, 109, 53 , 0 , 0 , 0 , 0 ), // {xmm|m32|mem, ymm}
3152 ROW(2, 1, 1, 0, 65 , 56 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, zmm}
3153 ROW(2, 1, 1, 0, 50 , 109, 0 , 0 , 0 , 0 ), // #257 {xmm, xmm|m32|mem}
3154 ROW(2, 1, 1, 0, 53 , 65 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m64|mem}
3155 ROW(2, 1, 1, 0, 56 , 51 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m128|mem}
3156 ROW(2, 1, 1, 0, 50 , 110, 0 , 0 , 0 , 0 ), // #260 {xmm, xmm|m16|mem}
3157 ROW(2, 1, 1, 0, 53 , 109, 0 , 0 , 0 , 0 ), // {ymm, xmm|m32|mem}
3158 ROW(2, 1, 1, 0, 56 , 65 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem}
3159 ROW(2, 1, 1, 0, 67 , 50 , 0 , 0 , 0 , 0 ), // #263 {vm32x, xmm}
3160 ROW(2, 1, 1, 0, 68 , 53 , 0 , 0 , 0 , 0 ), // {vm32y, ymm}
3161 ROW(2, 1, 1, 0, 69 , 56 , 0 , 0 , 0 , 0 ), // {vm32z, zmm}
3162 ROW(2, 1, 1, 0, 70 , 50 , 0 , 0 , 0 , 0 ), // #266 {vm64x, xmm}
3163 ROW(2, 1, 1, 0, 71 , 53 , 0 , 0 , 0 , 0 ), // {vm64y, ymm}
3164 ROW(2, 1, 1, 0, 72 , 56 , 0 , 0 , 0 , 0 ), // {vm64z, zmm}
3165 ROW(3, 1, 1, 0, 106, 50 , 51 , 0 , 0 , 0 ), // #269 {k, xmm, xmm|m128|mem}
3166 ROW(3, 1, 1, 0, 106, 53 , 54 , 0 , 0 , 0 ), // {k, ymm, ymm|m256|mem}
3167 ROW(3, 1, 1, 0, 106, 56 , 57 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem}
3168 ROW(3, 1, 1, 0, 6 , 6 , 28 , 0 , 0 , 0 ), // #272 {r32, r32, r32|m32|mem}
3169 ROW(3, 0, 1, 0, 8 , 8 , 15 , 0 , 0 , 0 ), // {r64, r64, r64|m64|mem}
3170 ROW(3, 1, 1, 0, 6 , 28 , 6 , 0 , 0 , 0 ), // #274 {r32, r32|m32|mem, r32}
3171 ROW(3, 0, 1, 0, 8 , 15 , 8 , 0 , 0 , 0 ), // {r64, r64|m64|mem, r64}
3172 ROW(2, 1, 0, 0, 111, 28 , 0 , 0 , 0 , 0 ), // #276 {bnd, r32|m32|mem}
3173 ROW(2, 0, 1, 0, 111, 15 , 0 , 0 , 0 , 0 ), // {bnd, r64|m64|mem}
3174 ROW(2, 1, 1, 0, 111, 112, 0 , 0 , 0 , 0 ), // #278 {bnd, bnd|mem}
3175 ROW(2, 1, 1, 0, 113, 111, 0 , 0 , 0 , 0 ), // {mem, bnd}
3176 ROW(2, 1, 0, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #280 {r16, m32|mem}
3177 ROW(2, 1, 0, 0, 6 , 30 , 0 , 0 , 0 , 0 ), // {r32, m64|mem}
3178 ROW(1, 1, 0, 0, 114, 0 , 0 , 0 , 0 , 0 ), // #282 {rel16|r16|m16|r32|m32}
3179 ROW(1, 1, 1, 0, 115, 0 , 0 , 0 , 0 , 0 ), // {rel32|r64|m64|mem}
3180 ROW(2, 1, 1, 0, 6 , 116, 0 , 0 , 0 , 0 ), // #284 {r32, r8lo|r8hi|m8|r16|m16|r32|m32}
3181 ROW(2, 0, 1, 0, 8 , 117, 0 , 0 , 0 , 0 ), // {r64, r8lo|r8hi|m8|r64|m64}
3182 ROW(1, 1, 0, 0, 118, 0 , 0 , 0 , 0 , 0 ), // #286 {r16|r32}
3183 ROW(1, 1, 1, 0, 31 , 0 , 0 , 0 , 0 , 0 ), // #287 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem}
3184 ROW(2, 1, 0, 0, 119, 58 , 0 , 0 , 0 , 0 ), // #288 {es:[mem|m512|memBase], m512|mem}
3185 ROW(2, 0, 1, 0, 119, 58 , 0 , 0 , 0 , 0 ), // {es:[mem|m512|memBase], m512|mem}
3186 ROW(3, 1, 1, 0, 50 , 10 , 10 , 0 , 0 , 0 ), // #290 {xmm, i8|u8, i8|u8}
3187 ROW(2, 1, 1, 0, 50 , 50 , 0 , 0 , 0 , 0 ), // #291 {xmm, xmm}
3188 ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #292 {}
3189 ROW(1, 1, 1, 0, 100, 0 , 0 , 0 , 0 , 0 ), // #293 {st}
3190 ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #294 {}
3191 ROW(1, 1, 1, 0, 120, 0 , 0 , 0 , 0 , 0 ), // #295 {m32|m64|st}
3192 ROW(2, 1, 1, 0, 50 , 50 , 0 , 0 , 0 , 0 ), // #296 {xmm, xmm}
3193 ROW(4, 1, 1, 0, 50 , 50 , 10 , 10 , 0 , 0 ), // {xmm, xmm, i8|u8, i8|u8}
3194 ROW(2, 1, 0, 0, 6 , 52 , 0 , 0 , 0 , 0 ), // #298 {r32, m128|mem}
3195 ROW(2, 0, 1, 0, 8 , 52 , 0 , 0 , 0 , 0 ), // {r64, m128|mem}
3196 ROW(2, 1, 0, 2, 36 , 121, 0 , 0 , 0 , 0 ), // #300 {<eax>, <ecx>}
3197 ROW(2, 0, 1, 2, 122, 121, 0 , 0 , 0 , 0 ), // {<eax|rax>, <ecx>}
3198 ROW(1, 1, 1, 0, 123, 0 , 0 , 0 , 0 , 0 ), // #302 {rel8|rel32}
3199 ROW(1, 1, 0, 0, 124, 0 , 0 , 0 , 0 , 0 ), // {rel16}
3200 ROW(2, 1, 0, 1, 125, 126, 0 , 0 , 0 , 0 ), // #304 {<cx|ecx>, rel8}
3201 ROW(2, 0, 1, 1, 127, 126, 0 , 0 , 0 , 0 ), // {<ecx|rcx>, rel8}
3202 ROW(1, 1, 1, 0, 128, 0 , 0 , 0 , 0 , 0 ), // #306 {rel8|rel32|r64|m64|mem}
3203 ROW(1, 1, 0, 0, 129, 0 , 0 , 0 , 0 , 0 ), // {rel16|r32|m32|mem}
3204 ROW(2, 1, 1, 0, 106, 130, 0 , 0 , 0 , 0 ), // #308 {k, k|m8|mem|r32}
3205 ROW(2, 1, 1, 0, 131, 106, 0 , 0 , 0 , 0 ), // {m8|mem|r32, k}
3206 ROW(2, 1, 1, 0, 106, 132, 0 , 0 , 0 , 0 ), // #310 {k, k|m32|mem|r32}
3207 ROW(2, 1, 1, 0, 28 , 106, 0 , 0 , 0 , 0 ), // {m32|mem|r32, k}
3208 ROW(2, 1, 1, 0, 106, 133, 0 , 0 , 0 , 0 ), // #312 {k, k|m64|mem|r64}
3209 ROW(2, 1, 1, 0, 15 , 106, 0 , 0 , 0 , 0 ), // {m64|mem|r64, k}
3210 ROW(2, 1, 1, 0, 106, 134, 0 , 0 , 0 , 0 ), // #314 {k, k|m16|mem|r32}
3211 ROW(2, 1, 1, 0, 135, 106, 0 , 0 , 0 , 0 ), // {m16|mem|r32, k}
3212 ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #316 {r16, r16|m16|mem}
3213 ROW(2, 1, 1, 0, 6 , 135, 0 , 0 , 0 , 0 ), // {r32, r32|m16|mem}
3214 ROW(2, 1, 0, 0, 136, 137, 0 , 0 , 0 , 0 ), // #318 {i16, i16|i32}
3215 ROW(1, 1, 1, 0, 138, 0 , 0 , 0 , 0 , 0 ), // {m32|m48|m80|mem}
3216 ROW(2, 1, 0, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #320 {r16, m32|mem}
3217 ROW(2, 1, 0, 0, 6 , 101, 0 , 0 , 0 , 0 ), // {r32, m48|mem}
3218 ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #322 {r16, r16|m16|mem}
3219 ROW(2, 1, 1, 0, 139, 135, 0 , 0 , 0 , 0 ), // {r32|r64, r32|m16|mem}
3220 ROW(2, 1, 1, 0, 64 , 28 , 0 , 0 , 0 , 0 ), // #324 {mm|xmm, r32|m32|mem}
3221 ROW(2, 1, 1, 0, 28 , 64 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, mm|xmm}
3222 ROW(2, 1, 1, 0, 50 , 109, 0 , 0 , 0 , 0 ), // #326 {xmm, xmm|m32|mem}
3223 ROW(2, 1, 1, 0, 29 , 50 , 0 , 0 , 0 , 0 ), // {m32|mem, xmm}
3224 ROW(2, 1, 1, 0, 4 , 9 , 0 , 0 , 0 , 0 ), // #328 {r16, r8lo|r8hi|m8}
3225 ROW(2, 1, 1, 0, 139, 140, 0 , 0 , 0 , 0 ), // {r32|r64, r8lo|r8hi|m8|r16|m16}
3226 ROW(4, 1, 1, 1, 6 , 6 , 28 , 35 , 0 , 0 ), // #330 {r32, r32, r32|m32|mem, <edx>}
3227 ROW(4, 0, 1, 1, 8 , 8 , 15 , 37 , 0 , 0 ), // {r64, r64, r64|m64|mem, <rdx>}
3228 ROW(2, 1, 1, 0, 62 , 141, 0 , 0 , 0 , 0 ), // #332 {mm, mm|m64|mem}
3229 ROW(2, 1, 1, 0, 50 , 51 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem}
3230 ROW(3, 1, 1, 0, 62 , 141, 10 , 0 , 0 , 0 ), // #334 {mm, mm|m64|mem, i8|u8}
3231 ROW(3, 1, 1, 0, 50 , 51 , 10 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem, i8|u8}
3232 ROW(3, 1, 1, 0, 6 , 64 , 10 , 0 , 0 , 0 ), // #336 {r32, mm|xmm, i8|u8}
3233 ROW(3, 1, 1, 0, 21 , 50 , 10 , 0 , 0 , 0 ), // {m16|mem, xmm, i8|u8}
3234 ROW(2, 1, 1, 0, 62 , 142, 0 , 0 , 0 , 0 ), // #338 {mm, i8|u8|mm|m64|mem}
3235 ROW(2, 1, 1, 0, 50 , 59 , 0 , 0 , 0 , 0 ), // {xmm, i8|u8|xmm|m128|mem}
3236 ROW(2, 1, 1, 0, 62 , 143, 0 , 0 , 0 , 0 ), // #340 {mm, mm|m32|mem}
3237 ROW(2, 1, 1, 0, 50 , 51 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem}
3238 ROW(1, 1, 0, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #342 {r32}
3239 ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // #343 {r64}
3240 ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #344 {}
3241 ROW(1, 1, 1, 0, 144, 0 , 0 , 0 , 0 , 0 ), // {u16}
3242 ROW(3, 1, 1, 0, 6 , 28 , 10 , 0 , 0 , 0 ), // #346 {r32, r32|m32|mem, i8|u8}
3243 ROW(3, 0, 1, 0, 8 , 15 , 10 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|u8}
3244 ROW(4, 1, 1, 0, 50 , 50 , 51 , 50 , 0 , 0 ), // #348 {xmm, xmm, xmm|m128|mem, xmm}
3245 ROW(4, 1, 1, 0, 53 , 53 , 54 , 53 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm}
3246 ROW(2, 1, 1, 0, 50 , 145, 0 , 0 , 0 , 0 ), // #350 {xmm, xmm|m128|ymm|m256}
3247 ROW(2, 1, 1, 0, 53 , 57 , 0 , 0 , 0 , 0 ), // {ymm, zmm|m512|mem}
3248 ROW(4, 1, 1, 0, 50 , 50 , 50 , 65 , 0 , 0 ), // #352 {xmm, xmm, xmm, xmm|m64|mem}
3249 ROW(4, 1, 1, 0, 50 , 50 , 30 , 50 , 0 , 0 ), // {xmm, xmm, m64|mem, xmm}
3250 ROW(4, 1, 1, 0, 50 , 50 , 50 , 109, 0 , 0 ), // #354 {xmm, xmm, xmm, xmm|m32|mem}
3251 ROW(4, 1, 1, 0, 50 , 50 , 29 , 50 , 0 , 0 ), // {xmm, xmm, m32|mem, xmm}
3252 ROW(4, 1, 1, 0, 53 , 53 , 51 , 10 , 0 , 0 ), // #356 {ymm, ymm, xmm|m128|mem, i8|u8}
3253 ROW(4, 1, 1, 0, 56 , 56 , 51 , 10 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem, i8|u8}
3254 ROW(1, 1, 0, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #358 {<eax>}
3255 ROW(1, 0, 1, 1, 38 , 0 , 0 , 0 , 0 , 0 ), // #359 {<rax>}
3256 ROW(2, 1, 1, 0, 28 , 50 , 0 , 0 , 0 , 0 ), // #360 {r32|m32|mem, xmm}
3257 ROW(2, 1, 1, 0, 50 , 28 , 0 , 0 , 0 , 0 ), // {xmm, r32|m32|mem}
3258 ROW(2, 1, 1, 0, 30 , 50 , 0 , 0 , 0 , 0 ), // #362 {m64|mem, xmm}
3259 ROW(3, 1, 1, 0, 50 , 50 , 30 , 0 , 0 , 0 ), // {xmm, xmm, m64|mem}
3260 ROW(2, 1, 0, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // #364 {r32|m32|mem, r32}
3261 ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64}
3262 ROW(2, 1, 0, 0, 6 , 28 , 0 , 0 , 0 , 0 ), // #366 {r32, r32|m32|mem}
3263 ROW(2, 0, 1, 0, 8 , 15 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem}
3264 ROW(3, 1, 1, 0, 50 , 50 , 59 , 0 , 0 , 0 ), // #368 {xmm, xmm, xmm|m128|mem|i8|u8}
3265 ROW(3, 1, 1, 0, 50 , 52 , 146, 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8|xmm}
3266 ROW(2, 1, 1, 0, 67 , 96 , 0 , 0 , 0 , 0 ), // #370 {vm32x, xmm|ymm}
3267 ROW(2, 1, 1, 0, 68 , 56 , 0 , 0 , 0 , 0 ), // {vm32y, zmm}
3268 ROW(2, 1, 1, 0, 107, 50 , 0 , 0 , 0 , 0 ), // #372 {vm64x|vm64y, xmm}
3269 ROW(2, 1, 1, 0, 72 , 53 , 0 , 0 , 0 , 0 ), // {vm64z, ymm}
3270 ROW(3, 1, 1, 0, 50 , 50 , 51 , 0 , 0 , 0 ), // #374 {xmm, xmm, xmm|m128|mem}
3271 ROW(3, 1, 1, 0, 50 , 52 , 50 , 0 , 0 , 0 ), // {xmm, m128|mem, xmm}
3272 ROW(1, 1, 0, 1, 33 , 0 , 0 , 0 , 0 , 0 ), // #376 {<ax>}
3273 ROW(2, 1, 0, 1, 33 , 10 , 0 , 0 , 0 , 0 ), // #377 {<ax>, i8|u8}
3274 ROW(2, 1, 0, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // #378 {r16|m16|mem, r16}
3275 ROW(3, 1, 1, 1, 50 , 51 , 147, 0 , 0 , 0 ), // #379 {xmm, xmm|m128|mem, <xmm0>}
3276 ROW(2, 1, 1, 0, 111, 148, 0 , 0 , 0 , 0 ), // #380 {bnd, mib}
3277 ROW(2, 1, 1, 0, 111, 113, 0 , 0 , 0 , 0 ), // #381 {bnd, mem}
3278 ROW(2, 1, 1, 0, 148, 111, 0 , 0 , 0 , 0 ), // #382 {mib, bnd}
3279 ROW(1, 1, 1, 0, 149, 0 , 0 , 0 , 0 , 0 ), // #383 {r16|r32|r64}
3280 ROW(1, 1, 1, 1, 33 , 0 , 0 , 0 , 0 , 0 ), // #384 {<ax>}
3281 ROW(2, 1, 1, 2, 35 , 36 , 0 , 0 , 0 , 0 ), // #385 {<edx>, <eax>}
3282 ROW(1, 1, 1, 0, 113, 0 , 0 , 0 , 0 , 0 ), // #386 {mem}
3283 ROW(1, 1, 1, 0, 30 , 0 , 0 , 0 , 0 , 0 ), // #387 {m64|mem}
3284 ROW(0, 0, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #388 {}
3285 ROW(1, 1, 1, 1, 150, 0 , 0 , 0 , 0 , 0 ), // #389 {<ds:[mem|m512|memBase|zax]>}
3286 ROW(3, 1, 1, 0, 50 , 65 , 10 , 0 , 0 , 0 ), // #390 {xmm, xmm|m64|mem, i8|u8}
3287 ROW(3, 1, 1, 0, 50 , 109, 10 , 0 , 0 , 0 ), // #391 {xmm, xmm|m32|mem, i8|u8}
3288 ROW(5, 0, 1, 4, 52 , 37 , 38 , 151, 152, 0 ), // #392 {m128|mem, <rdx>, <rax>, <rcx>, <rbx>}
3289 ROW(5, 1, 1, 4, 30 , 35 , 36 , 121, 153, 0 ), // #393 {m64|mem, <edx>, <eax>, <ecx>, <ebx>}
3290 ROW(4, 1, 1, 4, 36 , 153, 121, 35 , 0 , 0 ), // #394 {<eax>, <ebx>, <ecx>, <edx>}
3291 ROW(2, 0, 1, 2, 37 , 38 , 0 , 0 , 0 , 0 ), // #395 {<rdx>, <rax>}
3292 ROW(2, 1, 1, 0, 62 , 51 , 0 , 0 , 0 , 0 ), // #396 {mm, xmm|m128|mem}
3293 ROW(2, 1, 1, 0, 50 , 141, 0 , 0 , 0 , 0 ), // #397 {xmm, mm|m64|mem}
3294 ROW(2, 1, 1, 0, 62 , 65 , 0 , 0 , 0 , 0 ), // #398 {mm, xmm|m64|mem}
3295 ROW(2, 1, 1, 0, 139, 65 , 0 , 0 , 0 , 0 ), // #399 {r32|r64, xmm|m64|mem}
3296 ROW(2, 1, 1, 0, 50 , 154, 0 , 0 , 0 , 0 ), // #400 {xmm, r32|m32|mem|r64|m64}
3297 ROW(2, 1, 1, 0, 139, 109, 0 , 0 , 0 , 0 ), // #401 {r32|r64, xmm|m32|mem}
3298 ROW(2, 1, 1, 2, 34 , 33 , 0 , 0 , 0 , 0 ), // #402 {<dx>, <ax>}
3299 ROW(1, 1, 1, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #403 {<eax>}
3300 ROW(2, 1, 1, 0, 12 , 10 , 0 , 0 , 0 , 0 ), // #404 {i16|u16, i8|u8}
3301 ROW(3, 1, 1, 0, 28 , 50 , 10 , 0 , 0 , 0 ), // #405 {r32|m32|mem, xmm, i8|u8}
3302 ROW(1, 1, 1, 0, 102, 0 , 0 , 0 , 0 , 0 ), // #406 {m80|mem}
3303 ROW(1, 1, 1, 0, 155, 0 , 0 , 0 , 0 , 0 ), // #407 {m16|m32}
3304 ROW(1, 1, 1, 0, 156, 0 , 0 , 0 , 0 , 0 ), // #408 {m16|m32|m64}
3305 ROW(1, 1, 1, 0, 157, 0 , 0 , 0 , 0 , 0 ), // #409 {m32|m64|m80|st}
3306 ROW(1, 1, 1, 0, 21 , 0 , 0 , 0 , 0 , 0 ), // #410 {m16|mem}
3307 ROW(1, 1, 1, 0, 158, 0 , 0 , 0 , 0 , 0 ), // #411 {ax|m16|mem}
3308 ROW(1, 0, 1, 0, 113, 0 , 0 , 0 , 0 , 0 ), // #412 {mem}
3309 ROW(2, 1, 1, 1, 10 , 36 , 0 , 0 , 0 , 0 ), // #413 {i8|u8, <eax>}
3310 ROW(2, 1, 1, 0, 159, 160, 0 , 0 , 0 , 0 ), // #414 {al|ax|eax, i8|u8|dx}
3311 ROW(1, 1, 1, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #415 {r32}
3312 ROW(2, 1, 1, 0, 161, 162, 0 , 0 , 0 , 0 ), // #416 {es:[m8|memBase|zdi|m16|m32], dx}
3313 ROW(1, 1, 1, 0, 10 , 0 , 0 , 0 , 0 , 0 ), // #417 {i8|u8}
3314 ROW(0, 1, 0, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #418 {}
3315 ROW(3, 1, 1, 0, 106, 106, 106, 0 , 0 , 0 ), // #419 {k, k, k}
3316 ROW(2, 1, 1, 0, 106, 106, 0 , 0 , 0 , 0 ), // #420 {k, k}
3317 ROW(3, 1, 1, 0, 106, 106, 10 , 0 , 0 , 0 ), // #421 {k, k, i8|u8}
3318 ROW(1, 1, 1, 1, 163, 0 , 0 , 0 , 0 , 0 ), // #422 {<ah>}
3319 ROW(1, 1, 1, 0, 29 , 0 , 0 , 0 , 0 , 0 ), // #423 {m32|mem}
3320 ROW(1, 0, 1, 0, 58 , 0 , 0 , 0 , 0 , 0 ), // #424 {m512|mem}
3321 ROW(2, 1, 1, 0, 149, 164, 0 , 0 , 0 , 0 ), // #425 {r16|r32|r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024}
3322 ROW(1, 1, 1, 0, 27 , 0 , 0 , 0 , 0 , 0 ), // #426 {r16|m16|mem}
3323 ROW(1, 1, 1, 0, 139, 0 , 0 , 0 , 0 , 0 ), // #427 {r32|r64}
3324 ROW(3, 1, 1, 0, 139, 28 , 14 , 0 , 0 , 0 ), // #428 {r32|r64, r32|m32|mem, i32|u32}
3325 ROW(3, 1, 1, 1, 50 , 50 , 165, 0 , 0 , 0 ), // #429 {xmm, xmm, <ds:[mem|m128|memBase|zdi]>}
3326 ROW(3, 1, 1, 1, 62 , 62 , 166, 0 , 0 , 0 ), // #430 {mm, mm, <ds:[mem|m64|memBase|zdi]>}
3327 ROW(3, 1, 1, 3, 167, 121, 35 , 0 , 0 , 0 ), // #431 {<ds:[mem|memBase|zax]>, <ecx>, <edx>}
3328 ROW(2, 1, 1, 0, 119, 58 , 0 , 0 , 0 , 0 ), // #432 {es:[mem|m512|memBase], m512|mem}
3329 ROW(2, 1, 1, 0, 62 , 50 , 0 , 0 , 0 , 0 ), // #433 {mm, xmm}
3330 ROW(2, 1, 1, 0, 6 , 50 , 0 , 0 , 0 , 0 ), // #434 {r32, xmm}
3331 ROW(2, 1, 1, 0, 30 , 62 , 0 , 0 , 0 , 0 ), // #435 {m64|mem, mm}
3332 ROW(2, 1, 1, 0, 50 , 62 , 0 , 0 , 0 , 0 ), // #436 {xmm, mm}
3333 ROW(2, 0, 1, 0, 149, 28 , 0 , 0 , 0 , 0 ), // #437 {r16|r32|r64, r32|m32|mem}
3334 ROW(2, 1, 1, 2, 36 , 121, 0 , 0 , 0 , 0 ), // #438 {<eax>, <ecx>}
3335 ROW(3, 1, 1, 3, 36 , 121, 153, 0 , 0 , 0 ), // #439 {<eax>, <ecx>, <ebx>}
3336 ROW(2, 1, 1, 0, 168, 159, 0 , 0 , 0 , 0 ), // #440 {u8|dx, al|ax|eax}
3337 ROW(2, 1, 1, 0, 162, 169, 0 , 0 , 0 , 0 ), // #441 {dx, ds:[m8|memBase|zsi|m16|m32]}
3338 ROW(6, 1, 1, 3, 50 , 51 , 10 , 121, 36 , 35 ), // #442 {xmm, xmm|m128|mem, i8|u8, <ecx>, <eax>, <edx>}
3339 ROW(6, 1, 1, 3, 50 , 51 , 10 , 147, 36 , 35 ), // #443 {xmm, xmm|m128|mem, i8|u8, <xmm0>, <eax>, <edx>}
3340 ROW(4, 1, 1, 1, 50 , 51 , 10 , 121, 0 , 0 ), // #444 {xmm, xmm|m128|mem, i8|u8, <ecx>}
3341 ROW(4, 1, 1, 1, 50 , 51 , 10 , 147, 0 , 0 ), // #445 {xmm, xmm|m128|mem, i8|u8, <xmm0>}
3342 ROW(3, 1, 1, 0, 131, 50 , 10 , 0 , 0 , 0 ), // #446 {r32|m8|mem, xmm, i8|u8}
3343 ROW(3, 0, 1, 0, 15 , 50 , 10 , 0 , 0 , 0 ), // #447 {r64|m64|mem, xmm, i8|u8}
3344 ROW(3, 1, 1, 0, 50 , 131, 10 , 0 , 0 , 0 ), // #448 {xmm, r32|m8|mem, i8|u8}
3345 ROW(3, 1, 1, 0, 50 , 28 , 10 , 0 , 0 , 0 ), // #449 {xmm, r32|m32|mem, i8|u8}
3346 ROW(3, 0, 1, 0, 50 , 15 , 10 , 0 , 0 , 0 ), // #450 {xmm, r64|m64|mem, i8|u8}
3347 ROW(3, 1, 1, 0, 64 , 135, 10 , 0 , 0 , 0 ), // #451 {mm|xmm, r32|m16|mem, i8|u8}
3348 ROW(2, 1, 1, 0, 6 , 64 , 0 , 0 , 0 , 0 ), // #452 {r32, mm|xmm}
3349 ROW(2, 1, 1, 0, 50 , 10 , 0 , 0 , 0 , 0 ), // #453 {xmm, i8|u8}
3350 ROW(1, 1, 1, 0, 154, 0 , 0 , 0 , 0 , 0 ), // #454 {r32|m32|mem|r64|m64}
3351 ROW(2, 1, 1, 0, 31 , 103, 0 , 0 , 0 , 0 ), // #455 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, cl|i8|u8}
3352 ROW(1, 0, 1, 0, 139, 0 , 0 , 0 , 0 , 0 ), // #456 {r32|r64}
3353 ROW(3, 1, 1, 3, 35 , 36 , 121, 0 , 0 , 0 ), // #457 {<edx>, <eax>, <ecx>}
3354 ROW(1, 1, 1, 0, 1 , 0 , 0 , 0 , 0 , 0 ), // #458 {r8lo|r8hi|m8|mem}
3355 ROW(1, 1, 1, 0, 170, 0 , 0 , 0 , 0 , 0 ), // #459 {r16|m16|mem|r32|r64}
3356 ROW(3, 0, 1, 0, 171, 171, 171, 0 , 0 , 0 ), // #460 {tmm, tmm, tmm}
3357 ROW(2, 0, 1, 0, 171, 113, 0 , 0 , 0 , 0 ), // #461 {tmm, tmem}
3358 ROW(2, 0, 1, 0, 113, 171, 0 , 0 , 0 , 0 ), // #462 {tmem, tmm}
3359 ROW(1, 0, 1, 0, 171, 0 , 0 , 0 , 0 , 0 ), // #463 {tmm}
3360 ROW(3, 1, 1, 2, 6 , 35 , 36 , 0 , 0 , 0 ), // #464 {r32, <edx>, <eax>}
3361 ROW(1, 1, 1, 0, 172, 0 , 0 , 0 , 0 , 0 ), // #465 {ds:[mem|memBase]}
3362 ROW(6, 1, 1, 0, 56 , 56 , 56 , 56 , 56 , 52 ), // #466 {zmm, zmm, zmm, zmm, zmm, m128|mem}
3363 ROW(6, 1, 1, 0, 50 , 50 , 50 , 50 , 50 , 52 ), // #467 {xmm, xmm, xmm, xmm, xmm, m128|mem}
3364 ROW(3, 1, 1, 0, 50 , 50 , 65 , 0 , 0 , 0 ), // #468 {xmm, xmm, xmm|m64|mem}
3365 ROW(3, 1, 1, 0, 50 , 50 , 109, 0 , 0 , 0 ), // #469 {xmm, xmm, xmm|m32|mem}
3366 ROW(2, 1, 1, 0, 53 , 52 , 0 , 0 , 0 , 0 ), // #470 {ymm, m128|mem}
3367 ROW(2, 1, 1, 0, 173, 65 , 0 , 0 , 0 , 0 ), // #471 {ymm|zmm, xmm|m64|mem}
3368 ROW(2, 1, 1, 0, 173, 52 , 0 , 0 , 0 , 0 ), // #472 {ymm|zmm, m128|mem}
3369 ROW(2, 1, 1, 0, 56 , 55 , 0 , 0 , 0 , 0 ), // #473 {zmm, m256|mem}
3370 ROW(2, 1, 1, 0, 174, 65 , 0 , 0 , 0 , 0 ), // #474 {xmm|ymm|zmm, xmm|m64|mem}
3371 ROW(2, 1, 1, 0, 174, 109, 0 , 0 , 0 , 0 ), // #475 {xmm|ymm|zmm, m32|mem|xmm}
3372 ROW(4, 1, 1, 0, 104, 50 , 65 , 10 , 0 , 0 ), // #476 {xmm|k, xmm, xmm|m64|mem, i8|u8}
3373 ROW(4, 1, 1, 0, 104, 50 , 109, 10 , 0 , 0 ), // #477 {xmm|k, xmm, xmm|m32|mem, i8|u8}
3374 ROW(3, 1, 1, 0, 50 , 50 , 154, 0 , 0 , 0 ), // #478 {xmm, xmm, r32|m32|mem|r64|m64}
3375 ROW(3, 1, 1, 0, 51 , 173, 10 , 0 , 0 , 0 ), // #479 {xmm|m128|mem, ymm|zmm, i8|u8}
3376 ROW(4, 1, 1, 0, 50 , 50 , 65 , 10 , 0 , 0 ), // #480 {xmm, xmm, xmm|m64|mem, i8|u8}
3377 ROW(4, 1, 1, 0, 50 , 50 , 109, 10 , 0 , 0 ), // #481 {xmm, xmm, xmm|m32|mem, i8|u8}
3378 ROW(3, 1, 1, 0, 106, 175, 10 , 0 , 0 , 0 ), // #482 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8}
3379 ROW(3, 1, 1, 0, 106, 65 , 10 , 0 , 0 , 0 ), // #483 {k, xmm|m64|mem, i8|u8}
3380 ROW(3, 1, 1, 0, 106, 109, 10 , 0 , 0 , 0 ), // #484 {k, xmm|m32|mem, i8|u8}
3381 ROW(1, 1, 1, 0, 68 , 0 , 0 , 0 , 0 , 0 ), // #485 {vm32y}
3382 ROW(1, 1, 1, 0, 69 , 0 , 0 , 0 , 0 , 0 ), // #486 {vm32z}
3383 ROW(1, 1, 1, 0, 72 , 0 , 0 , 0 , 0 , 0 ), // #487 {vm64z}
3384 ROW(4, 1, 1, 0, 56 , 56 , 54 , 10 , 0 , 0 ), // #488 {zmm, zmm, ymm|m256|mem, i8|u8}
3385 ROW(2, 1, 1, 0, 6 , 96 , 0 , 0 , 0 , 0 ), // #489 {r32, xmm|ymm}
3386 ROW(2, 1, 1, 0, 174, 176, 0 , 0 , 0 , 0 ), // #490 {xmm|ymm|zmm, xmm|m8|mem|r32}
3387 ROW(2, 1, 1, 0, 174, 177, 0 , 0 , 0 , 0 ), // #491 {xmm|ymm|zmm, xmm|m32|mem|r32}
3388 ROW(2, 1, 1, 0, 174, 106, 0 , 0 , 0 , 0 ), // #492 {xmm|ymm|zmm, k}
3389 ROW(2, 1, 1, 0, 174, 178, 0 , 0 , 0 , 0 ), // #493 {xmm|ymm|zmm, xmm|m16|mem|r32}
3390 ROW(3, 1, 1, 0, 135, 50 , 10 , 0 , 0 , 0 ), // #494 {r32|m16|mem, xmm, i8|u8}
3391 ROW(4, 1, 1, 0, 50 , 50 , 131, 10 , 0 , 0 ), // #495 {xmm, xmm, r32|m8|mem, i8|u8}
3392 ROW(4, 1, 1, 0, 50 , 50 , 28 , 10 , 0 , 0 ), // #496 {xmm, xmm, r32|m32|mem, i8|u8}
3393 ROW(4, 0, 1, 0, 50 , 50 , 15 , 10 , 0 , 0 ), // #497 {xmm, xmm, r64|m64|mem, i8|u8}
3394 ROW(4, 1, 1, 0, 50 , 50 , 135, 10 , 0 , 0 ), // #498 {xmm, xmm, r32|m16|mem, i8|u8}
3395 ROW(2, 1, 1, 0, 106, 174, 0 , 0 , 0 , 0 ), // #499 {k, xmm|ymm|zmm}
3396 ROW(1, 1, 1, 0, 124, 0 , 0 , 0 , 0 , 0 ), // #500 {rel16|rel32}
3397 ROW(3, 1, 1, 2, 113, 35 , 36 , 0 , 0 , 0 ), // #501 {mem, <edx>, <eax>}
3398 ROW(3, 0, 1, 2, 113, 35 , 36 , 0 , 0 , 0 ) // #502 {mem, <edx>, <eax>}
3399 };
3400 #undef ROW
3401
3402 #define ROW(flags, mFlags, extFlags, regId) { uint32_t(flags), uint16_t(mFlags), uint8_t(extFlags), uint8_t(regId) }
3403 #define F(VAL) InstDB::kOp##VAL
3404 #define M(VAL) InstDB::kMemOp##VAL
3405 const InstDB::OpSignature InstDB::_opSignatureTable[] = {
3406 ROW(0, 0, 0, 0xFF),
3407 ROW(F(GpbLo) | F(GpbHi) | F(Mem), M(M8) | M(Any), 0, 0x00),
3408 ROW(F(GpbLo) | F(GpbHi), 0, 0, 0x00),
3409 ROW(F(Gpw) | F(SReg) | F(Mem), M(M16) | M(Any), 0, 0x00),
3410 ROW(F(Gpw), 0, 0, 0x00),
3411 ROW(F(Gpd) | F(SReg) | F(Mem), M(M32) | M(Any), 0, 0x00),
3412 ROW(F(Gpd), 0, 0, 0x00),
3413 ROW(F(Gpq) | F(SReg) | F(CReg) | F(DReg) | F(Mem), M(M64) | M(Any), 0, 0x00),
3414 ROW(F(Gpq), 0, 0, 0x00),
3415 ROW(F(GpbLo) | F(GpbHi) | F(Mem), M(M8), 0, 0x00),
3416 ROW(F(I8) | F(U8), 0, 0, 0x00),
3417 ROW(F(Gpw) | F(Mem), M(M16), 0, 0x00),
3418 ROW(F(I16) | F(U16), 0, 0, 0x00),
3419 ROW(F(Gpd) | F(Mem), M(M32), 0, 0x00),
3420 ROW(F(I32) | F(U32), 0, 0, 0x00),
3421 ROW(F(Gpq) | F(Mem), M(M64) | M(Any), 0, 0x00),
3422 ROW(F(I32), 0, 0, 0x00),
3423 ROW(F(SReg) | F(CReg) | F(DReg) | F(Mem) | F(I64) | F(U64), M(M64) | M(Any), 0, 0x00),
3424 ROW(F(Mem), M(M8) | M(Any), 0, 0x00),
3425 ROW(F(SReg) | F(Mem), M(M16) | M(Any), 0, 0x00),
3426 ROW(F(SReg) | F(Mem), M(M32) | M(Any), 0, 0x00),
3427 ROW(F(Mem), M(M16) | M(Any), 0, 0x00),
3428 ROW(F(SReg), 0, 0, 0x00),
3429 ROW(F(CReg) | F(DReg), 0, 0, 0x00),
3430 ROW(F(Gpq) | F(I32), 0, 0, 0x00),
3431 ROW(F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M16) | M(M32) | M(M64) | M(Any), 0, 0x00),
3432 ROW(F(I8), 0, 0, 0x00),
3433 ROW(F(Gpw) | F(Mem), M(M16) | M(Any), 0, 0x00),
3434 ROW(F(Gpd) | F(Mem), M(M32) | M(Any), 0, 0x00),
3435 ROW(F(Mem), M(M32) | M(Any), 0, 0x00),
3436 ROW(F(Mem), M(M64) | M(Any), 0, 0x00),
3437 ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M8) | M(M16) | M(M32) | M(M64) | M(Any), 0, 0x00),
3438 ROW(F(Gpq) | F(Mem) | F(I32) | F(U32), M(M64) | M(Any), 0, 0x00),
3439 ROW(F(Gpw) | F(Implicit), 0, 0, 0x01),
3440 ROW(F(Gpw) | F(Implicit), 0, 0, 0x04),
3441 ROW(F(Gpd) | F(Implicit), 0, 0, 0x04),
3442 ROW(F(Gpd) | F(Implicit), 0, 0, 0x01),
3443 ROW(F(Gpq) | F(Implicit), 0, 0, 0x04),
3444 ROW(F(Gpq) | F(Implicit), 0, 0, 0x01),
3445 ROW(F(Gpw) | F(Mem) | F(I8) | F(I16), M(M16) | M(Any), 0, 0x00),
3446 ROW(F(Gpd) | F(Mem) | F(I8) | F(I32), M(M32) | M(Any), 0, 0x00),
3447 ROW(F(Gpq) | F(Mem) | F(I8) | F(I32), M(M64) | M(Any), 0, 0x00),
3448 ROW(F(I8) | F(I16) | F(U16), 0, 0, 0x00),
3449 ROW(F(I8) | F(I32) | F(U32), 0, 0, 0x00),
3450 ROW(F(I8) | F(I32), 0, 0, 0x00),
3451 ROW(F(I64) | F(U64), 0, 0, 0x00),
3452 ROW(F(GpbLo), 0, 0, 0x01),
3453 ROW(F(Gpw), 0, 0, 0x01),
3454 ROW(F(Gpd), 0, 0, 0x01),
3455 ROW(F(Gpq), 0, 0, 0x01),
3456 ROW(F(Xmm), 0, 0, 0x00),
3457 ROW(F(Xmm) | F(Mem), M(M128) | M(Any), 0, 0x00),
3458 ROW(F(Mem), M(M128) | M(Any), 0, 0x00),
3459 ROW(F(Ymm), 0, 0, 0x00),
3460 ROW(F(Ymm) | F(Mem), M(M256) | M(Any), 0, 0x00),
3461 ROW(F(Mem), M(M256) | M(Any), 0, 0x00),
3462 ROW(F(Zmm), 0, 0, 0x00),
3463 ROW(F(Zmm) | F(Mem), M(M512) | M(Any), 0, 0x00),
3464 ROW(F(Mem), M(M512) | M(Any), 0, 0x00),
3465 ROW(F(Xmm) | F(Mem) | F(I8) | F(U8), M(M128) | M(Any), 0, 0x00),
3466 ROW(F(Ymm) | F(Mem) | F(I8) | F(U8), M(M256) | M(Any), 0, 0x00),
3467 ROW(F(Zmm) | F(Mem) | F(I8) | F(U8), M(M512) | M(Any), 0, 0x00),
3468 ROW(F(Mm), 0, 0, 0x00),
3469 ROW(F(Gpq) | F(Mm) | F(Mem), M(M64) | M(Any), 0, 0x00),
3470 ROW(F(Xmm) | F(Mm), 0, 0, 0x00),
3471 ROW(F(Xmm) | F(Mem), M(M64) | M(Any), 0, 0x00),
3472 ROW(F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M16) | M(M32) | M(M64), 0, 0x00),
3473 ROW(F(Vm), M(Vm32x), 0, 0x00),
3474 ROW(F(Vm), M(Vm32y), 0, 0x00),
3475 ROW(F(Vm), M(Vm32z), 0, 0x00),
3476 ROW(F(Vm), M(Vm64x), 0, 0x00),
3477 ROW(F(Vm), M(Vm64y), 0, 0x00),
3478 ROW(F(Vm), M(Vm64z), 0, 0x00),
3479 ROW(F(Mem) | F(Implicit), M(M8) | M(BaseOnly) | M(Ds), 0, 0x40),
3480 ROW(F(Mem) | F(Implicit), M(M8) | M(BaseOnly) | M(Es), 0, 0x80),
3481 ROW(F(Mem) | F(Implicit), M(M16) | M(BaseOnly) | M(Ds), 0, 0x40),
3482 ROW(F(Mem) | F(Implicit), M(M16) | M(BaseOnly) | M(Es), 0, 0x80),
3483 ROW(F(Mem) | F(Implicit), M(M32) | M(BaseOnly) | M(Ds), 0, 0x40),
3484 ROW(F(Mem) | F(Implicit), M(M32) | M(BaseOnly) | M(Es), 0, 0x80),
3485 ROW(F(Mem) | F(Implicit), M(M64) | M(BaseOnly) | M(Ds), 0, 0x40),
3486 ROW(F(Mem) | F(Implicit), M(M64) | M(BaseOnly) | M(Es), 0, 0x80),
3487 ROW(F(GpbLo) | F(Implicit), 0, 0, 0x01),
3488 ROW(F(Mem) | F(Implicit), M(M8) | M(BaseOnly) | M(Ds) | M(Any), 0, 0x40),
3489 ROW(F(Mem) | F(Implicit), M(M16) | M(BaseOnly) | M(Ds) | M(Any), 0, 0x40),
3490 ROW(F(Mem) | F(Implicit), M(M32) | M(BaseOnly) | M(Ds) | M(Any), 0, 0x40),
3491 ROW(F(Mem) | F(Implicit), M(M64) | M(BaseOnly) | M(Ds) | M(Any), 0, 0x40),
3492 ROW(F(Gpw) | F(Gpq) | F(Mem), M(M16) | M(M64), 0, 0x00),
3493 ROW(F(SReg), 0, 0, 0x1A),
3494 ROW(F(SReg), 0, 0, 0x60),
3495 ROW(F(Gpw) | F(Gpq) | F(Mem) | F(I8) | F(I16) | F(I32), M(M16) | M(M64), 0, 0x00),
3496 ROW(F(Gpd) | F(Mem) | F(I32) | F(U32), M(M32), 0, 0x00),
3497 ROW(F(SReg), 0, 0, 0x1E),
3498 ROW(F(Mem) | F(Implicit), M(M8) | M(BaseOnly) | M(Es) | M(Any), 0, 0x80),
3499 ROW(F(Mem) | F(Implicit), M(M16) | M(BaseOnly) | M(Es) | M(Any), 0, 0x80),
3500 ROW(F(Mem) | F(Implicit), M(M32) | M(BaseOnly) | M(Es) | M(Any), 0, 0x80),
3501 ROW(F(Mem) | F(Implicit), M(M64) | M(BaseOnly) | M(Es) | M(Any), 0, 0x80),
3502 ROW(F(Xmm) | F(Ymm), 0, 0, 0x00),
3503 ROW(F(I4) | F(U4), 0, 0, 0x00),
3504 ROW(F(Mem), M(M32) | M(M64), 0, 0x00),
3505 ROW(F(St), 0, 0, 0x01),
3506 ROW(F(St), 0, 0, 0x00),
3507 ROW(F(Mem), M(M48) | M(Any), 0, 0x00),
3508 ROW(F(Mem), M(M80) | M(Any), 0, 0x00),
3509 ROW(F(GpbLo) | F(I8) | F(U8), 0, 0, 0x02),
3510 ROW(F(Xmm) | F(KReg), 0, 0, 0x00),
3511 ROW(F(Ymm) | F(KReg), 0, 0, 0x00),
3512 ROW(F(KReg), 0, 0, 0x00),
3513 ROW(F(Vm), M(Vm64x) | M(Vm64y), 0, 0x00),
3514 ROW(F(Gpq) | F(Xmm) | F(Mem), M(M64) | M(Any), 0, 0x00),
3515 ROW(F(Xmm) | F(Mem), M(M32) | M(Any), 0, 0x00),
3516 ROW(F(Xmm) | F(Mem), M(M16) | M(Any), 0, 0x00),
3517 ROW(F(Bnd), 0, 0, 0x00),
3518 ROW(F(Bnd) | F(Mem), M(Any), 0, 0x00),
3519 ROW(F(Mem), M(Any), 0, 0x00),
3520 ROW(F(Gpw) | F(Gpd) | F(Mem) | F(I32) | F(I64) | F(Rel32), M(M16) | M(M32), 0, 0x00),
3521 ROW(F(Gpq) | F(Mem) | F(I32) | F(I64) | F(Rel32), M(M64) | M(Any), 0, 0x00),
3522 ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Gpd) | F(Mem), M(M8) | M(M16) | M(M32), 0, 0x00),
3523 ROW(F(GpbLo) | F(GpbHi) | F(Gpq) | F(Mem), M(M8) | M(M64), 0, 0x00),
3524 ROW(F(Gpw) | F(Gpd), 0, 0, 0x00),
3525 ROW(F(Mem), M(M512) | M(BaseOnly) | M(Es) | M(Any), 0, 0x00),
3526 ROW(F(St) | F(Mem), M(M32) | M(M64), 0, 0x00),
3527 ROW(F(Gpd) | F(Implicit), 0, 0, 0x02),
3528 ROW(F(Gpd) | F(Gpq) | F(Implicit), 0, 0, 0x01),
3529 ROW(F(I32) | F(I64) | F(Rel8) | F(Rel32), 0, 0, 0x00),
3530 ROW(F(I32) | F(I64) | F(Rel32), 0, 0, 0x00),
3531 ROW(F(Gpw) | F(Gpd) | F(Implicit), 0, 0, 0x02),
3532 ROW(F(I32) | F(I64) | F(Rel8), 0, 0, 0x00),
3533 ROW(F(Gpd) | F(Gpq) | F(Implicit), 0, 0, 0x02),
3534 ROW(F(Gpq) | F(Mem) | F(I32) | F(I64) | F(Rel8) | F(Rel32), M(M64) | M(Any), 0, 0x00),
3535 ROW(F(Gpd) | F(Mem) | F(I32) | F(I64) | F(Rel32), M(M32) | M(Any), 0, 0x00),
3536 ROW(F(Gpd) | F(KReg) | F(Mem), M(M8) | M(Any), 0, 0x00),
3537 ROW(F(Gpd) | F(Mem), M(M8) | M(Any), 0, 0x00),
3538 ROW(F(Gpd) | F(KReg) | F(Mem), M(M32) | M(Any), 0, 0x00),
3539 ROW(F(Gpq) | F(KReg) | F(Mem), M(M64) | M(Any), 0, 0x00),
3540 ROW(F(Gpd) | F(KReg) | F(Mem), M(M16) | M(Any), 0, 0x00),
3541 ROW(F(Gpd) | F(Mem), M(M16) | M(Any), 0, 0x00),
3542 ROW(F(I16), 0, 0, 0x00),
3543 ROW(F(I16) | F(I32), 0, 0, 0x00),
3544 ROW(F(Mem), M(M32) | M(M48) | M(M80) | M(Any), 0, 0x00),
3545 ROW(F(Gpd) | F(Gpq), 0, 0, 0x00),
3546 ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Mem), M(M8) | M(M16), 0, 0x00),
3547 ROW(F(Mm) | F(Mem), M(M64) | M(Any), 0, 0x00),
3548 ROW(F(Mm) | F(Mem) | F(I8) | F(U8), M(M64) | M(Any), 0, 0x00),
3549 ROW(F(Mm) | F(Mem), M(M32) | M(Any), 0, 0x00),
3550 ROW(F(U16), 0, 0, 0x00),
3551 ROW(F(Xmm) | F(Ymm) | F(Mem), M(M128) | M(M256), 0, 0x00),
3552 ROW(F(Xmm) | F(I8) | F(U8), 0, 0, 0x00),
3553 ROW(F(Xmm) | F(Implicit), 0, 0, 0x01),
3554 ROW(F(Mem), M(Mib), 0, 0x00),
3555 ROW(F(Gpw) | F(Gpd) | F(Gpq), 0, 0, 0x00),
3556 ROW(F(Mem) | F(Implicit), M(M512) | M(BaseOnly) | M(Ds) | M(Any), 0, 0x01),
3557 ROW(F(Gpq) | F(Implicit), 0, 0, 0x02),
3558 ROW(F(Gpq) | F(Implicit), 0, 0, 0x08),
3559 ROW(F(Gpd) | F(Implicit), 0, 0, 0x08),
3560 ROW(F(Gpd) | F(Gpq) | F(Mem), M(M32) | M(M64) | M(Any), 0, 0x00),
3561 ROW(F(Mem), M(M16) | M(M32), 0, 0x00),
3562 ROW(F(Mem), M(M16) | M(M32) | M(M64), 0, 0x00),
3563 ROW(F(St) | F(Mem), M(M32) | M(M64) | M(M80), 0, 0x00),
3564 ROW(F(Gpw) | F(Mem), M(M16) | M(Any), 0, 0x01),
3565 ROW(F(GpbLo) | F(Gpw) | F(Gpd), 0, 0, 0x01),
3566 ROW(F(Gpw) | F(I8) | F(U8), 0, 0, 0x04),
3567 ROW(F(Mem), M(M8) | M(M16) | M(M32) | M(BaseOnly) | M(Es), 0, 0x80),
3568 ROW(F(Gpw), 0, 0, 0x04),
3569 ROW(F(GpbHi) | F(Implicit), 0, 0, 0x01),
3570 ROW(F(Mem), M(M8) | M(M16) | M(M32) | M(M48) | M(M64) | M(M80) | M(M128) | M(M256) | M(M512) | M(M1024) | M(Any), 0, 0x00),
3571 ROW(F(Mem) | F(Implicit), M(M128) | M(BaseOnly) | M(Ds) | M(Any), 0, 0x80),
3572 ROW(F(Mem) | F(Implicit), M(M64) | M(BaseOnly) | M(Ds) | M(Any), 0, 0x80),
3573 ROW(F(Mem) | F(Implicit), M(BaseOnly) | M(Ds) | M(Any), 0, 0x01),
3574 ROW(F(Gpw) | F(U8), 0, 0, 0x04),
3575 ROW(F(Mem), M(M8) | M(M16) | M(M32) | M(BaseOnly) | M(Ds), 0, 0x40),
3576 ROW(F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M16) | M(Any), 0, 0x00),
3577 ROW(F(Tmm), 0, 0, 0x00),
3578 ROW(F(Mem), M(BaseOnly) | M(Ds) | M(Any), 0, 0x00),
3579 ROW(F(Ymm) | F(Zmm), 0, 0, 0x00),
3580 ROW(F(Xmm) | F(Ymm) | F(Zmm), 0, 0, 0x00),
3581 ROW(F(Xmm) | F(Ymm) | F(Zmm) | F(Mem), M(M128) | M(M256) | M(M512), 0, 0x00),
3582 ROW(F(Gpd) | F(Xmm) | F(Mem), M(M8) | M(Any), 0, 0x00),
3583 ROW(F(Gpd) | F(Xmm) | F(Mem), M(M32) | M(Any), 0, 0x00),
3584 ROW(F(Gpd) | F(Xmm) | F(Mem), M(M16) | M(Any), 0, 0x00)
3585 };
3586 #undef M
3587 #undef F
3588 #undef ROW
3589 // ----------------------------------------------------------------------------
3590 // ${InstSignatureTable:End}
3591 #endif // !ASMJIT_NO_VALIDATION
3592
3593 // ============================================================================
3594 // [asmjit::x86::InstInternal - QueryRWInfo]
3595 // ============================================================================
3596
3597 // ${InstRWInfoTable:Begin}
3598 // ------------------- Automatically generated, do not edit -------------------
3599 const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = {
3600 0, 0, 1, 1, 0, 2, 3, 2, 4, 4, 5, 6, 4, 4, 3, 4, 4, 4, 4, 7, 0, 2, 0, 4, 4, 4,
3601 4, 8, 0, 9, 9, 9, 9, 9, 0, 0, 0, 0, 9, 9, 9, 9, 9, 10, 10, 10, 11, 11, 12, 13,
3602 14, 9, 9, 0, 15, 16, 16, 16, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3603 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3604 3, 3, 3, 3, 3, 3, 3, 18, 0, 0, 19, 0, 0, 0, 0, 0, 20, 21, 0, 22, 23, 24, 7, 25,
3605 25, 25, 24, 26, 7, 24, 27, 28, 29, 30, 31, 32, 33, 25, 25, 7, 27, 28, 33, 34,
3606 0, 0, 0, 0, 35, 4, 4, 5, 6, 0, 0, 0, 0, 0, 36, 36, 0, 0, 37, 0, 0, 38, 0, 0,
3607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38, 0, 0, 0, 0,
3608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 0,
3609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38,
3610 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 4, 0, 39, 4,
3611 4, 35, 40, 41, 0, 0, 0, 42, 0, 37, 0, 0, 0, 0, 43, 0, 44, 43, 43, 0, 0, 0, 0,
3612 0, 0, 0, 0, 0, 45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3613 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 46, 47, 48, 49, 50, 51,
3614 52, 53, 0, 0, 0, 54, 55, 56, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 0,
3615 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 58, 0, 59, 0, 60, 0, 61, 0, 60, 0, 60, 0, 60,
3616 0, 0, 0, 0, 0, 62, 63, 63, 63, 58, 60, 0, 0, 0, 9, 0, 0, 4, 4, 5, 6, 0, 0, 4,
3617 4, 5, 6, 0, 0, 64, 65, 66, 66, 67, 47, 24, 36, 67, 52, 66, 66, 68, 69, 69, 70,
3618 71, 71, 72, 72, 59, 59, 67, 59, 59, 71, 71, 73, 48, 52, 74, 48, 7, 7, 47, 75,
3619 33, 66, 66, 75, 0, 35, 4, 4, 5, 6, 0, 76, 0, 0, 77, 0, 2, 4, 4, 78, 79, 9,
3620 9, 9, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 3, 3, 0, 3, 80, 3, 0, 0, 0, 3, 3,
3621 4, 3, 0, 0, 3, 3, 4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 27, 80, 80, 80, 80, 80,
3622 80, 80, 80, 80, 80, 27, 80, 80, 80, 27, 27, 80, 80, 80, 3, 3, 3, 81, 3, 3, 3,
3623 27, 27, 0, 0, 0, 0, 3, 3, 4, 4, 3, 3, 4, 4, 4, 4, 3, 3, 4, 4, 82, 83, 84, 24,
3624 24, 24, 83, 83, 84, 24, 24, 24, 83, 4, 3, 80, 3, 3, 4, 3, 3, 0, 0, 0, 9, 0,
3625 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 85, 3, 3, 0, 3, 3,
3626 3, 85, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 27, 86, 0, 3, 3, 4, 3, 87, 87, 4, 87, 0,
3627 0, 0, 0, 0, 0, 0, 3, 88, 7, 89, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 90, 0, 0,
3628 0, 0, 0, 88, 88, 0, 0, 0, 0, 0, 0, 7, 89, 0, 0, 88, 88, 0, 0, 2, 91, 0, 0, 0,
3629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3630 0, 0, 0, 0, 0, 0, 4, 4, 4, 0, 4, 4, 0, 88, 0, 0, 88, 0, 0, 0, 0, 0, 0, 0, 0,
3631 0, 7, 7, 26, 89, 0, 0, 0, 0, 0, 0, 92, 0, 0, 0, 2, 4, 4, 5, 6, 0, 0, 0, 0, 0,
3632 0, 0, 9, 0, 0, 0, 0, 0, 15, 0, 93, 93, 0, 94, 0, 0, 9, 9, 20, 21, 95, 95, 0,
3633 0, 0, 0, 4, 4, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0,
3634 0, 0, 0, 0, 0, 0, 0, 0, 0, 96, 28, 97, 98, 97, 98, 96, 28, 97, 98, 97, 98, 99,
3635 100, 0, 0, 0, 0, 20, 21, 101, 101, 102, 9, 0, 75, 103, 103, 9, 103, 9, 102, 9,
3636 102, 0, 102, 9, 102, 9, 103, 28, 0, 28, 0, 0, 0, 33, 33, 103, 9, 103, 9, 9,
3637 102, 9, 102, 28, 28, 33, 33, 102, 9, 9, 103, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3638 0, 104, 104, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3639 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3642 0, 9, 9, 27, 105, 60, 60, 0, 0, 0, 0, 0, 0, 0, 0, 60, 106, 9, 9, 0, 0, 0, 0,
3643 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 67, 0, 0, 0, 0, 0,
3644 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 107, 107, 47, 108, 107, 107, 107, 107,
3645 107, 107, 107, 107, 0, 109, 109, 0, 71, 71, 110, 111, 67, 67, 67, 67, 112, 71,
3646 9, 9, 73, 107, 107, 0, 0, 0, 101, 0, 0, 0, 0, 0, 0, 0, 113, 0, 0, 0, 0, 0, 0,
3647 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3648 0, 0, 0, 0, 0, 0, 0, 114, 33, 115, 115, 28, 116, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3649 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, 101, 101, 101, 0, 0, 0, 0, 0,
3650 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3651 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 60, 60, 106, 60, 7, 7, 7, 0, 7, 0, 7,
3652 7, 7, 7, 7, 7, 0, 7, 7, 81, 7, 0, 7, 0, 0, 7, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0,
3653 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3654 0, 0, 0, 117, 117, 118, 119, 115, 115, 115, 115, 82, 117, 120, 119, 118, 118,
3655 119, 120, 119, 118, 119, 121, 122, 102, 102, 102, 121, 118, 119, 120, 119, 118,
3656 119, 117, 119, 121, 122, 102, 102, 102, 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9,
3657 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 67, 67, 123, 67,
3658 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3659 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3660 0, 0, 0, 0, 0, 0, 113, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3661 0, 0, 0, 0, 9, 9, 0, 0, 104, 104, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3662 0, 0, 9, 9, 0, 0, 104, 104, 0, 0, 9, 0, 0, 0, 0, 0, 67, 67, 0, 0, 0, 0, 0, 0,
3663 0, 0, 67, 123, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 113, 113, 20, 21,
3664 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 124, 125, 124, 125, 0, 126, 0, 127, 0,
3665 0, 0, 2, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
3666 };
3667
3668 const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = {
3669 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 3, 0, 0, 0,
3670 0, 0, 4, 0, 0, 0, 0, 0, 5, 5, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3671 0, 7, 0, 0, 0, 0, 4, 8, 1, 0, 9, 0, 0, 0, 10, 10, 10, 0, 0, 11, 0, 0, 10, 12,
3672 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3673 0, 0, 0, 0, 0, 0, 5, 5, 0, 13, 14, 15, 16, 17, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0,
3674 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 1, 1, 20, 21, 0, 0,
3675 0, 0, 5, 5, 0, 0, 0, 0, 0, 0, 22, 23, 0, 0, 24, 25, 26, 27, 0, 0, 25, 25, 25,
3676 25, 25, 25, 25, 25, 28, 29, 29, 28, 0, 0, 0, 24, 25, 24, 25, 0, 25, 24, 24, 24,
3677 24, 24, 24, 24, 0, 0, 30, 30, 30, 24, 24, 28, 0, 31, 10, 0, 0, 0, 0, 0, 0, 24,
3678 25, 0, 0, 0, 32, 33, 32, 34, 0, 0, 0, 0, 0, 10, 32, 0, 0, 0, 0, 35, 33, 32,
3679 35, 34, 24, 25, 24, 25, 0, 29, 29, 29, 29, 0, 0, 0, 25, 10, 10, 32, 32, 0, 0,
3680 0, 0, 5, 5, 0, 0, 0, 0, 0, 0, 0, 21, 36, 0, 20, 37, 38, 0, 39, 40, 0, 0, 0, 0,
3681 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0,
3682 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 44, 41, 42, 41, 42, 43,
3683 44, 43, 44, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 0, 0, 0, 0, 44, 45, 46, 47,
3684 48, 45, 46, 47, 48, 0, 0, 0, 0, 49, 50, 51, 41, 42, 43, 44, 41, 42, 43, 44, 52,
3685 0, 24, 0, 53, 0, 54, 0, 0, 0, 0, 0, 10, 0, 10, 24, 55, 56, 55, 0, 0, 0, 0,
3686 0, 0, 55, 57, 57, 0, 58, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 60, 60, 0, 0, 0, 0,
3687 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3688 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 61, 0, 0, 0, 0, 62, 0, 63, 20, 64, 20, 0, 0,
3689 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 6,
3690 5, 5, 0, 0, 0, 0, 66, 67, 0, 0, 0, 0, 68, 69, 0, 3, 3, 70, 22, 71, 72, 0, 0,
3691 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3692 0, 0, 73, 39, 74, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3693 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 0, 0, 0, 0, 0, 0, 0, 10,
3694 10, 10, 10, 10, 10, 10, 0, 0, 2, 2, 2, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3695 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 78, 0, 0, 0,
3696 0, 0, 0, 0, 0, 0, 0, 0, 79, 79, 80, 79, 80, 80, 80, 79, 79, 81, 82, 0, 83, 0,
3697 0, 0, 0, 0, 0, 84, 2, 2, 85, 86, 0, 0, 0, 11, 87, 0, 0, 4, 0, 0, 0, 88, 0, 89,
3698 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89, 89,
3699 89, 89, 89, 89, 89, 89, 89, 89, 89, 0, 89, 0, 32, 0, 0, 0, 5, 0, 0, 6, 0, 90,
3700 4, 0, 90, 4, 5, 5, 32, 19, 91, 79, 91, 0, 0, 0, 0, 0, 0, 0, 0, 0, 92, 0, 91, 93,
3701 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 94, 94, 94, 94, 94, 0, 0, 0, 0, 0,
3702 0, 95, 96, 0, 0, 0, 0, 0, 0, 0, 0, 56, 96, 0, 0, 0, 0, 97, 98, 97, 98, 3, 3,
3703 99, 100, 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 101, 101, 0, 0,
3704 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 102, 103, 0, 0, 0, 0, 0, 0, 3, 0,
3705 0, 0, 0, 0, 0, 0, 0, 0, 104, 0, 0, 0, 0, 0, 0, 105, 0, 106, 107, 108, 0, 0, 0,
3706 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 107, 3, 3, 3, 99, 100, 3, 109,
3707 3, 55, 55, 0, 0, 0, 0, 110, 111, 112, 111, 112, 110, 111, 112, 111, 112, 22,
3708 113, 113, 114, 115, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 116,
3709 117, 118, 118, 119, 120, 113, 113, 113, 113, 113, 113, 118, 118, 113, 113, 116,
3710 117, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 113, 113, 113, 113, 118,
3711 118, 118, 118, 119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113,
3712 116, 117, 118, 118, 119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113,
3713 121, 122, 118, 118, 119, 120, 123, 123, 77, 124, 0, 0, 0, 0, 125, 126, 10,
3714 10, 10, 10, 10, 10, 10, 10, 126, 127, 0, 0, 128, 129, 84, 84, 128, 129, 3, 3,
3715 3, 3, 3, 3, 3, 130, 131, 132, 131, 132, 130, 131, 132, 131, 132, 100, 0, 53, 58,
3716 133, 133, 3, 3, 99, 100, 0, 134, 0, 3, 3, 99, 100, 0, 135, 0, 0, 0, 0, 0, 0,
3717 0, 0, 0, 0, 0, 0, 0, 136, 137, 137, 138, 139, 139, 0, 0, 0, 0, 0, 0, 0, 140,
3718 0, 0, 141, 0, 0, 3, 11, 134, 0, 0, 142, 135, 3, 3, 99, 100, 0, 11, 3, 3, 143,
3719 143, 144, 144, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3720 3, 3, 3, 3, 3, 3, 3, 3, 3, 101, 3, 0, 0, 0, 0, 0, 0, 3, 118, 145, 145, 3, 3,
3721 3, 3, 66, 67, 3, 3, 3, 3, 68, 69, 145, 145, 145, 145, 145, 145, 109, 109, 0, 0,
3722 0, 0, 109, 109, 109, 109, 109, 109, 0, 0, 113, 113, 113, 113, 146, 146, 3, 3,
3723 3, 113, 3, 3, 113, 113, 118, 118, 147, 147, 147, 3, 147, 3, 113, 113, 113, 113,
3724 113, 3, 0, 0, 0, 0, 70, 22, 71, 148, 126, 125, 127, 126, 0, 0, 0, 3, 0, 3,
3725 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 3, 0, 3, 3, 0, 149, 100, 99, 150, 0, 0, 151,
3726 151, 151, 151, 151, 151, 151, 151, 151, 151, 151, 151, 113, 113, 3, 3, 133, 133,
3727 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3728 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3729 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 3, 3, 3, 152, 84, 84, 3, 3,
3730 84, 84, 3, 3, 153, 153, 153, 153, 3, 0, 0, 0, 0, 153, 153, 153, 153, 153, 153,
3731 3, 3, 113, 113, 113, 3, 153, 153, 3, 3, 113, 113, 113, 3, 3, 145, 84, 84, 84,
3732 3, 3, 3, 154, 155, 154, 3, 3, 3, 154, 154, 154, 3, 3, 3, 154, 154, 155, 154,
3733 3, 3, 3, 154, 3, 3, 3, 3, 3, 3, 3, 3, 113, 113, 0, 145, 145, 145, 145, 145,
3734 145, 145, 145, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 128, 129, 0, 0, 128, 129,
3735 0, 0, 128, 129, 0, 129, 84, 84, 128, 129, 84, 84, 128, 129, 84, 84, 128, 129,
3736 0, 0, 128, 129, 0, 0, 128, 129, 0, 129, 3, 3, 99, 100, 0, 0, 10, 10, 10, 10,
3737 10, 10, 10, 10, 0, 0, 3, 3, 3, 3, 3, 3, 0, 0, 128, 129, 92, 3, 3, 99, 100, 0,
3738 0, 0, 0, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 56, 56, 156, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3739 80, 0, 0, 0, 0, 0, 157, 157, 157, 157, 158, 158, 158, 158, 158, 158, 158, 158,
3740 156, 0, 0
3741 };
3742
3743 const InstDB::RWInfo InstDB::rwInfoA[] = {
3744 { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=936x]
3745 { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=2x]
3746 { InstDB::RWInfo::kCategoryGeneric , 1 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #2 [ref=7x]
3747 { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #3 [ref=96x]
3748 { InstDB::RWInfo::kCategoryGeneric , 3 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #4 [ref=55x]
3749 { InstDB::RWInfo::kCategoryGeneric , 4 , { 6 , 7 , 0 , 0 , 0 , 0 } }, // #5 [ref=6x]
3750 { InstDB::RWInfo::kCategoryGeneric , 5 , { 8 , 9 , 0 , 0 , 0 , 0 } }, // #6 [ref=6x]
3751 { InstDB::RWInfo::kCategoryGeneric , 3 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #7 [ref=26x]
3752 { InstDB::RWInfo::kCategoryGeneric , 7 , { 12, 13, 0 , 0 , 0 , 0 } }, // #8 [ref=1x]
3753 { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #9 [ref=64x]
3754 { InstDB::RWInfo::kCategoryGeneric , 2 , { 5 , 3 , 0 , 0 , 0 , 0 } }, // #10 [ref=3x]
3755 { InstDB::RWInfo::kCategoryGeneric , 8 , { 10, 3 , 0 , 0 , 0 , 0 } }, // #11 [ref=2x]
3756 { InstDB::RWInfo::kCategoryGeneric , 9 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #12 [ref=1x]
3757 { InstDB::RWInfo::kCategoryGeneric , 8 , { 15, 5 , 0 , 0 , 0 , 0 } }, // #13 [ref=1x]
3758 { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #14 [ref=1x]
3759 { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 3 , 0 , 0 , 0 , 0 } }, // #15 [ref=2x]
3760 { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 3 , 0 , 0 , 0 , 0 } }, // #16 [ref=3x]
3761 { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 17, 0 , 0 , 0 , 0 } }, // #17 [ref=1x]
3762 { InstDB::RWInfo::kCategoryGeneric , 1 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #18 [ref=1x]
3763 { InstDB::RWInfo::kCategoryGeneric , 0 , { 20, 21, 0 , 0 , 0 , 0 } }, // #19 [ref=1x]
3764 { InstDB::RWInfo::kCategoryGeneric , 4 , { 7 , 7 , 0 , 0 , 0 , 0 } }, // #20 [ref=4x]
3765 { InstDB::RWInfo::kCategoryGeneric , 5 , { 9 , 9 , 0 , 0 , 0 , 0 } }, // #21 [ref=4x]
3766 { InstDB::RWInfo::kCategoryGeneric , 0 , { 33, 34, 0 , 0 , 0 , 0 } }, // #22 [ref=1x]
3767 { InstDB::RWInfo::kCategoryGeneric , 14, { 2 , 3 , 0 , 0 , 0 , 0 } }, // #23 [ref=1x]
3768 { InstDB::RWInfo::kCategoryGeneric , 4 , { 10, 7 , 0 , 0 , 0 , 0 } }, // #24 [ref=10x]
3769 { InstDB::RWInfo::kCategoryGeneric , 3 , { 35, 5 , 0 , 0 , 0 , 0 } }, // #25 [ref=5x]
3770 { InstDB::RWInfo::kCategoryGeneric , 4 , { 36, 7 , 0 , 0 , 0 , 0 } }, // #26 [ref=2x]
3771 { InstDB::RWInfo::kCategoryGeneric , 4 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #27 [ref=11x]
3772 { InstDB::RWInfo::kCategoryGeneric , 4 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #28 [ref=9x]
3773 { InstDB::RWInfo::kCategoryGeneric , 4 , { 37, 7 , 0 , 0 , 0 , 0 } }, // #29 [ref=1x]
3774 { InstDB::RWInfo::kCategoryGeneric , 14, { 36, 3 , 0 , 0 , 0 , 0 } }, // #30 [ref=1x]
3775 { InstDB::RWInfo::kCategoryGeneric , 14, { 37, 3 , 0 , 0 , 0 , 0 } }, // #31 [ref=1x]
3776 { InstDB::RWInfo::kCategoryGeneric , 5 , { 36, 9 , 0 , 0 , 0 , 0 } }, // #32 [ref=1x]
3777 { InstDB::RWInfo::kCategoryGeneric , 5 , { 11, 9 , 0 , 0 , 0 , 0 } }, // #33 [ref=8x]
3778 { InstDB::RWInfo::kCategoryGeneric , 0 , { 38, 39, 0 , 0 , 0 , 0 } }, // #34 [ref=1x]
3779 { InstDB::RWInfo::kCategoryGeneric , 15, { 1 , 40, 0 , 0 , 0 , 0 } }, // #35 [ref=3x]
3780 { InstDB::RWInfo::kCategoryGeneric , 16, { 11, 43, 0 , 0 , 0 , 0 } }, // #36 [ref=3x]
3781 { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #37 [ref=2x]
3782 { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 46, 0 , 0 , 0 , 0 } }, // #38 [ref=6x]
3783 { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 50, 0 , 0 , 0 , 0 } }, // #39 [ref=1x]
3784 { InstDB::RWInfo::kCategoryImul , 2 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #40 [ref=1x]
3785 { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 52, 0 , 0 , 0 , 0 } }, // #41 [ref=1x]
3786 { InstDB::RWInfo::kCategoryGeneric , 0 , { 54, 52, 0 , 0 , 0 , 0 } }, // #42 [ref=1x]
3787 { InstDB::RWInfo::kCategoryGeneric , 13, { 3 , 5 , 0 , 0 , 0 , 0 } }, // #43 [ref=3x]
3788 { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 29, 0 , 0 , 0 , 0 } }, // #44 [ref=1x]
3789 { InstDB::RWInfo::kCategoryGeneric , 0 , { 55, 0 , 0 , 0 , 0 , 0 } }, // #45 [ref=1x]
3790 { InstDB::RWInfo::kCategoryGeneric , 23, { 56, 40, 0 , 0 , 0 , 0 } }, // #46 [ref=1x]
3791 { InstDB::RWInfo::kCategoryGeneric , 24, { 44, 9 , 0 , 0 , 0 , 0 } }, // #47 [ref=4x]
3792 { InstDB::RWInfo::kCategoryGeneric , 25, { 35, 7 , 0 , 0 , 0 , 0 } }, // #48 [ref=3x]
3793 { InstDB::RWInfo::kCategoryGeneric , 26, { 48, 13, 0 , 0 , 0 , 0 } }, // #49 [ref=1x]
3794 { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 40, 0 , 0 , 0 , 0 } }, // #50 [ref=1x]
3795 { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 9 , 0 , 0 , 0 , 0 } }, // #51 [ref=1x]
3796 { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #52 [ref=3x]
3797 { InstDB::RWInfo::kCategoryGeneric , 0 , { 48, 13, 0 , 0 , 0 , 0 } }, // #53 [ref=1x]
3798 { InstDB::RWInfo::kCategoryGeneric , 0 , { 40, 40, 0 , 0 , 0 , 0 } }, // #54 [ref=2x]
3799 { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 9 , 0 , 0 , 0 , 0 } }, // #55 [ref=2x]
3800 { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 0 , 0 , 0 , 0 } }, // #56 [ref=2x]
3801 { InstDB::RWInfo::kCategoryGeneric , 0 , { 13, 13, 0 , 0 , 0 , 0 } }, // #57 [ref=2x]
3802 { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 3 , 0 , 0 , 0 , 0 } }, // #58 [ref=2x]
3803 { InstDB::RWInfo::kCategoryGeneric , 13, { 10, 5 , 0 , 0 , 0 , 0 } }, // #59 [ref=5x]
3804 { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #60 [ref=11x]
3805 { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #61 [ref=1x]
3806 { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 20, 0 , 0 , 0 , 0 } }, // #62 [ref=1x]
3807 { InstDB::RWInfo::kCategoryGeneric , 0 , { 58, 0 , 0 , 0 , 0 , 0 } }, // #63 [ref=3x]
3808 { InstDB::RWInfo::kCategoryMov , 29, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #64 [ref=1x]
3809 { InstDB::RWInfo::kCategoryMovabs , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #65 [ref=1x]
3810 { InstDB::RWInfo::kCategoryGeneric , 30, { 10, 5 , 0 , 0 , 0 , 0 } }, // #66 [ref=6x]
3811 { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #67 [ref=14x]
3812 { InstDB::RWInfo::kCategoryGeneric , 0 , { 36, 61, 0 , 0 , 0 , 0 } }, // #68 [ref=1x]
3813 { InstDB::RWInfo::kCategoryMovh64 , 12, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #69 [ref=2x]
3814 { InstDB::RWInfo::kCategoryGeneric , 0 , { 62, 7 , 0 , 0 , 0 , 0 } }, // #70 [ref=1x]
3815 { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 7 , 0 , 0 , 0 , 0 } }, // #71 [ref=7x]
3816 { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 5 , 0 , 0 , 0 , 0 } }, // #72 [ref=2x]
3817 { InstDB::RWInfo::kCategoryGeneric , 28, { 44, 9 , 0 , 0 , 0 , 0 } }, // #73 [ref=2x]
3818 { InstDB::RWInfo::kCategoryGeneric , 0 , { 63, 20, 0 , 0 , 0 , 0 } }, // #74 [ref=1x]
3819 { InstDB::RWInfo::kCategoryGeneric , 14, { 11, 3 , 0 , 0 , 0 , 0 } }, // #75 [ref=3x]
3820 { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 29, 0 , 0 , 0 , 0 } }, // #76 [ref=1x]
3821 { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 3 , 0 , 0 , 0 , 0 } }, // #77 [ref=1x]
3822 { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 22, 0 , 0 , 0 , 0 } }, // #78 [ref=1x]
3823 { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 66, 0 , 0 , 0 , 0 } }, // #79 [ref=1x]
3824 { InstDB::RWInfo::kCategoryGeneric , 4 , { 26, 7 , 0 , 0 , 0 , 0 } }, // #80 [ref=18x]
3825 { InstDB::RWInfo::kCategoryGeneric , 3 , { 69, 5 , 0 , 0 , 0 , 0 } }, // #81 [ref=2x]
3826 { InstDB::RWInfo::kCategoryVmov1_8 , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #82 [ref=2x]
3827 { InstDB::RWInfo::kCategoryGeneric , 5 , { 10, 9 , 0 , 0 , 0 , 0 } }, // #83 [ref=4x]
3828 { InstDB::RWInfo::kCategoryGeneric , 27, { 10, 13, 0 , 0 , 0 , 0 } }, // #84 [ref=2x]
3829 { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #85 [ref=2x]
3830 { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 0 , 0 , 0 } }, // #86 [ref=1x]
3831 { InstDB::RWInfo::kCategoryPunpcklxx , 34, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #87 [ref=3x]
3832 { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 71, 0 , 0 , 0 , 0 } }, // #88 [ref=8x]
3833 { InstDB::RWInfo::kCategoryGeneric , 5 , { 37, 9 , 0 , 0 , 0 , 0 } }, // #89 [ref=3x]
3834 { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 50, 0 , 0 , 0 , 0 } }, // #90 [ref=1x]
3835 { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 21, 0 , 0 , 0 , 0 } }, // #91 [ref=1x]
3836 { InstDB::RWInfo::kCategoryGeneric , 0 , { 63, 22, 0 , 0 , 0 , 0 } }, // #92 [ref=1x]
3837 { InstDB::RWInfo::kCategoryGeneric , 8 , { 74, 3 , 0 , 0 , 0 , 0 } }, // #93 [ref=2x]
3838 { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 43, 0 , 0 , 0 , 0 } }, // #94 [ref=1x]
3839 { InstDB::RWInfo::kCategoryGeneric , 5 , { 53, 9 , 0 , 0 , 0 , 0 } }, // #95 [ref=2x]
3840 { InstDB::RWInfo::kCategoryGeneric , 13, { 76, 5 , 0 , 0 , 0 , 0 } }, // #96 [ref=2x]
3841 { InstDB::RWInfo::kCategoryGeneric , 13, { 11, 5 , 0 , 0 , 0 , 0 } }, // #97 [ref=4x]
3842 { InstDB::RWInfo::kCategoryGeneric , 38, { 74, 77, 0 , 0 , 0 , 0 } }, // #98 [ref=4x]
3843 { InstDB::RWInfo::kCategoryGeneric , 39, { 11, 7 , 0 , 0 , 0 , 0 } }, // #99 [ref=1x]
3844 { InstDB::RWInfo::kCategoryGeneric , 40, { 11, 9 , 0 , 0 , 0 , 0 } }, // #100 [ref=1x]
3845 { InstDB::RWInfo::kCategoryGeneric , 11, { 11, 3 , 0 , 0 , 0 , 0 } }, // #101 [ref=7x]
3846 { InstDB::RWInfo::kCategoryVmov2_1 , 41, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #102 [ref=14x]
3847 { InstDB::RWInfo::kCategoryVmov1_2 , 14, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #103 [ref=7x]
3848 { InstDB::RWInfo::kCategoryGeneric , 45, { 74, 43, 0 , 0 , 0 , 0 } }, // #104 [ref=6x]
3849 { InstDB::RWInfo::kCategoryGeneric , 5 , { 44, 9 , 0 , 0 , 0 , 0 } }, // #105 [ref=1x]
3850 { InstDB::RWInfo::kCategoryGeneric , 18, { 2 , 3 , 0 , 0 , 0 , 0 } }, // #106 [ref=2x]
3851 { InstDB::RWInfo::kCategoryGeneric , 52, { 11, 3 , 0 , 0 , 0 , 0 } }, // #107 [ref=12x]
3852 { InstDB::RWInfo::kCategoryVmovddup , 34, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #108 [ref=1x]
3853 { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 61, 0 , 0 , 0 , 0 } }, // #109 [ref=2x]
3854 { InstDB::RWInfo::kCategoryVmovmskpd , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #110 [ref=1x]
3855 { InstDB::RWInfo::kCategoryVmovmskps , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #111 [ref=1x]
3856 { InstDB::RWInfo::kCategoryGeneric , 53, { 35, 7 , 0 , 0 , 0 , 0 } }, // #112 [ref=1x]
3857 { InstDB::RWInfo::kCategoryGeneric , 2 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #113 [ref=4x]
3858 { InstDB::RWInfo::kCategoryGeneric , 15, { 11, 40, 0 , 0 , 0 , 0 } }, // #114 [ref=1x]
3859 { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #115 [ref=6x]
3860 { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 13, 0 , 0 , 0 , 0 } }, // #116 [ref=1x]
3861 { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 3 , 0 , 0 , 0 , 0 } }, // #117 [ref=4x]
3862 { InstDB::RWInfo::kCategoryVmov1_4 , 57, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #118 [ref=6x]
3863 { InstDB::RWInfo::kCategoryVmov1_2 , 42, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #119 [ref=9x]
3864 { InstDB::RWInfo::kCategoryVmov1_8 , 58, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #120 [ref=3x]
3865 { InstDB::RWInfo::kCategoryVmov4_1 , 59, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #121 [ref=4x]
3866 { InstDB::RWInfo::kCategoryVmov8_1 , 60, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #122 [ref=2x]
3867 { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 3 , 0 , 0 , 0 , 0 } }, // #123 [ref=2x]
3868 { InstDB::RWInfo::kCategoryGeneric , 17, { 44, 9 , 0 , 0 , 0 , 0 } }, // #124 [ref=2x]
3869 { InstDB::RWInfo::kCategoryGeneric , 32, { 35, 7 , 0 , 0 , 0 , 0 } }, // #125 [ref=2x]
3870 { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #126 [ref=1x]
3871 { InstDB::RWInfo::kCategoryGeneric , 52, { 2 , 2 , 0 , 0 , 0 , 0 } } // #127 [ref=1x]
3872 };
3873
3874 const InstDB::RWInfo InstDB::rwInfoB[] = {
3875 { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=742x]
3876 { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=5x]
3877 { InstDB::RWInfo::kCategoryGeneric , 3 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #2 [ref=7x]
3878 { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 0 , 0 , 0 } }, // #3 [ref=186x]
3879 { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 3 , 0 , 0 , 0 } }, // #4 [ref=5x]
3880 { InstDB::RWInfo::kCategoryGeneric , 3 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #5 [ref=14x]
3881 { InstDB::RWInfo::kCategoryGeneric , 3 , { 4 , 5 , 14, 0 , 0 , 0 } }, // #6 [ref=4x]
3882 { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 0 , 0 , 0 , 0 , 0 } }, // #7 [ref=1x]
3883 { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #8 [ref=2x]
3884 { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 0 , 0 , 0 , 0 , 0 } }, // #9 [ref=1x]
3885 { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #10 [ref=34x]
3886 { InstDB::RWInfo::kCategoryGeneric , 12, { 7 , 0 , 0 , 0 , 0 , 0 } }, // #11 [ref=4x]
3887 { InstDB::RWInfo::kCategoryGeneric , 0 , { 19, 0 , 0 , 0 , 0 , 0 } }, // #12 [ref=1x]
3888 { InstDB::RWInfo::kCategoryGeneric , 4 , { 6 , 7 , 0 , 0 , 0 , 0 } }, // #13 [ref=1x]
3889 { InstDB::RWInfo::kCategoryGeneric , 5 , { 8 , 9 , 0 , 0 , 0 , 0 } }, // #14 [ref=1x]
3890 { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 22, 0 , 0 , 0 } }, // #15 [ref=1x]
3891 { InstDB::RWInfo::kCategoryGeneric , 13, { 4 , 23, 18, 24, 25, 0 } }, // #16 [ref=1x]
3892 { InstDB::RWInfo::kCategoryGeneric , 12, { 26, 27, 28, 29, 30, 0 } }, // #17 [ref=1x]
3893 { InstDB::RWInfo::kCategoryGeneric , 0 , { 28, 31, 32, 16, 0 , 0 } }, // #18 [ref=1x]
3894 { InstDB::RWInfo::kCategoryGeneric , 0 , { 28, 0 , 0 , 0 , 0 , 0 } }, // #19 [ref=2x]
3895 { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 0 , 0 , 0 , 0 , 0 } }, // #20 [ref=4x]
3896 { InstDB::RWInfo::kCategoryGeneric , 6 , { 41, 42, 3 , 0 , 0 , 0 } }, // #21 [ref=2x]
3897 { InstDB::RWInfo::kCategoryGeneric , 17, { 44, 5 , 0 , 0 , 0 , 0 } }, // #22 [ref=4x]
3898 { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #23 [ref=1x]
3899 { InstDB::RWInfo::kCategoryGeneric , 18, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #24 [ref=17x]
3900 { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 0 , 0 , 0 , 0 , 0 } }, // #25 [ref=16x]
3901 { InstDB::RWInfo::kCategoryGeneric , 19, { 46, 0 , 0 , 0 , 0 , 0 } }, // #26 [ref=1x]
3902 { InstDB::RWInfo::kCategoryGeneric , 19, { 47, 0 , 0 , 0 , 0 , 0 } }, // #27 [ref=1x]
3903 { InstDB::RWInfo::kCategoryGeneric , 20, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #28 [ref=3x]
3904 { InstDB::RWInfo::kCategoryGeneric , 0 , { 46, 0 , 0 , 0 , 0 , 0 } }, // #29 [ref=6x]
3905 { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 0 , 0 , 0 , 0 , 0 } }, // #30 [ref=3x]
3906 { InstDB::RWInfo::kCategoryGeneric , 21, { 13, 0 , 0 , 0 , 0 , 0 } }, // #31 [ref=1x]
3907 { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #32 [ref=8x]
3908 { InstDB::RWInfo::kCategoryGeneric , 21, { 48, 0 , 0 , 0 , 0 , 0 } }, // #33 [ref=2x]
3909 { InstDB::RWInfo::kCategoryGeneric , 7 , { 49, 0 , 0 , 0 , 0 , 0 } }, // #34 [ref=2x]
3910 { InstDB::RWInfo::kCategoryGeneric , 20, { 11, 0 , 0 , 0 , 0 , 0 } }, // #35 [ref=2x]
3911 { InstDB::RWInfo::kCategoryImul , 22, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #36 [ref=1x]
3912 { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 0 , 0 , 0 , 0 , 0 } }, // #37 [ref=1x]
3913 { InstDB::RWInfo::kCategoryGeneric , 0 , { 26, 0 , 0 , 0 , 0 , 0 } }, // #38 [ref=1x]
3914 { InstDB::RWInfo::kCategoryGeneric , 5 , { 4 , 9 , 0 , 0 , 0 , 0 } }, // #39 [ref=2x]
3915 { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #40 [ref=1x]
3916 { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 40, 40, 0 , 0 , 0 } }, // #41 [ref=6x]
3917 { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 9 , 9 , 0 , 0 , 0 } }, // #42 [ref=6x]
3918 { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 7 , 7 , 0 , 0 , 0 } }, // #43 [ref=6x]
3919 { InstDB::RWInfo::kCategoryGeneric , 0 , { 48, 13, 13, 0 , 0 , 0 } }, // #44 [ref=6x]
3920 { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 40, 0 , 0 , 0 , 0 } }, // #45 [ref=2x]
3921 { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 9 , 0 , 0 , 0 , 0 } }, // #46 [ref=2x]
3922 { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #47 [ref=2x]
3923 { InstDB::RWInfo::kCategoryGeneric , 0 , { 48, 13, 0 , 0 , 0 , 0 } }, // #48 [ref=2x]
3924 { InstDB::RWInfo::kCategoryGeneric , 0 , { 48, 40, 40, 0 , 0 , 0 } }, // #49 [ref=1x]
3925 { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 9 , 9 , 0 , 0 , 0 } }, // #50 [ref=1x]
3926 { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 13, 13, 0 , 0 , 0 } }, // #51 [ref=1x]
3927 { InstDB::RWInfo::kCategoryGeneric , 0 , { 57, 0 , 0 , 0 , 0 , 0 } }, // #52 [ref=1x]
3928 { InstDB::RWInfo::kCategoryGeneric , 28, { 9 , 0 , 0 , 0 , 0 , 0 } }, // #53 [ref=2x]
3929 { InstDB::RWInfo::kCategoryGeneric , 16, { 43, 0 , 0 , 0 , 0 , 0 } }, // #54 [ref=1x]
3930 { InstDB::RWInfo::kCategoryGeneric , 7 , { 13, 0 , 0 , 0 , 0 , 0 } }, // #55 [ref=5x]
3931 { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #56 [ref=4x]
3932 { InstDB::RWInfo::kCategoryGeneric , 5 , { 3 , 9 , 0 , 0 , 0 , 0 } }, // #57 [ref=2x]
3933 { InstDB::RWInfo::kCategoryGeneric , 0 , { 5 , 5 , 59, 0 , 0 , 0 } }, // #58 [ref=2x]
3934 { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 59, 0 , 0 , 0 } }, // #59 [ref=1x]
3935 { InstDB::RWInfo::kCategoryGeneric , 0 , { 19, 29, 60, 0 , 0 , 0 } }, // #60 [ref=2x]
3936 { InstDB::RWInfo::kCategoryGeneric , 6 , { 64, 42, 3 , 0 , 0 , 0 } }, // #61 [ref=1x]
3937 { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 11, 3 , 65, 0 , 0 } }, // #62 [ref=1x]
3938 { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 29, 30, 0 , 0 , 0 } }, // #63 [ref=1x]
3939 { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #64 [ref=2x]
3940 { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #65 [ref=1x]
3941 { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 67, 17, 60 } }, // #66 [ref=2x]
3942 { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 68, 17, 60 } }, // #67 [ref=2x]
3943 { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 67, 0 , 0 } }, // #68 [ref=2x]
3944 { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 68, 0 , 0 } }, // #69 [ref=2x]
3945 { InstDB::RWInfo::kCategoryGeneric , 31, { 56, 5 , 0 , 0 , 0 , 0 } }, // #70 [ref=2x]
3946 { InstDB::RWInfo::kCategoryGeneric , 32, { 35, 5 , 0 , 0 , 0 , 0 } }, // #71 [ref=2x]
3947 { InstDB::RWInfo::kCategoryGeneric , 33, { 48, 3 , 0 , 0 , 0 , 0 } }, // #72 [ref=1x]
3948 { InstDB::RWInfo::kCategoryGeneric , 15, { 4 , 40, 0 , 0 , 0 , 0 } }, // #73 [ref=1x]
3949 { InstDB::RWInfo::kCategoryGeneric , 4 , { 4 , 7 , 0 , 0 , 0 , 0 } }, // #74 [ref=1x]
3950 { InstDB::RWInfo::kCategoryGeneric , 27, { 2 , 13, 0 , 0 , 0 , 0 } }, // #75 [ref=1x]
3951 { InstDB::RWInfo::kCategoryGeneric , 10, { 70, 0 , 0 , 0 , 0 , 0 } }, // #76 [ref=1x]
3952 { InstDB::RWInfo::kCategoryGeneric , 4 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #77 [ref=2x]
3953 { InstDB::RWInfo::kCategoryGeneric , 10, { 65, 0 , 0 , 0 , 0 , 0 } }, // #78 [ref=1x]
3954 { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #79 [ref=6x]
3955 { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 50, 29, 0 , 0 , 0 } }, // #80 [ref=5x]
3956 { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 0 , 0 , 0 , 0 , 0 } }, // #81 [ref=1x]
3957 { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 0 , 0 , 0 , 0 , 0 } }, // #82 [ref=1x]
3958 { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 50, 67, 0 , 0 , 0 } }, // #83 [ref=1x]
3959 { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #84 [ref=16x]
3960 { InstDB::RWInfo::kCategoryGeneric , 4 , { 36, 7 , 0 , 0 , 0 , 0 } }, // #85 [ref=1x]
3961 { InstDB::RWInfo::kCategoryGeneric , 5 , { 37, 9 , 0 , 0 , 0 , 0 } }, // #86 [ref=1x]
3962 { InstDB::RWInfo::kCategoryGeneric , 0 , { 72, 0 , 0 , 0 , 0 , 0 } }, // #87 [ref=1x]
3963 { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 0 , 0 , 0 , 0 , 0 } }, // #88 [ref=1x]
3964 { InstDB::RWInfo::kCategoryGeneric , 31, { 73, 0 , 0 , 0 , 0 , 0 } }, // #89 [ref=30x]
3965 { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 71, 0 , 0 , 0 } }, // #90 [ref=2x]
3966 { InstDB::RWInfo::kCategoryGeneric , 35, { 11, 0 , 0 , 0 , 0 , 0 } }, // #91 [ref=3x]
3967 { InstDB::RWInfo::kCategoryGeneric , 28, { 44, 0 , 0 , 0 , 0 , 0 } }, // #92 [ref=2x]
3968 { InstDB::RWInfo::kCategoryGeneric , 16, { 74, 0 , 0 , 0 , 0 , 0 } }, // #93 [ref=1x]
3969 { InstDB::RWInfo::kCategoryGeneric , 0 , { 75, 43, 43, 0 , 0 , 0 } }, // #94 [ref=5x]
3970 { InstDB::RWInfo::kCategoryGeneric , 0 , { 74, 0 , 0 , 0 , 0 , 0 } }, // #95 [ref=1x]
3971 { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 60, 17, 0 , 0 , 0 } }, // #96 [ref=2x]
3972 { InstDB::RWInfo::kCategoryGeneric , 13, { 75, 43, 43, 43, 43, 5 } }, // #97 [ref=2x]
3973 { InstDB::RWInfo::kCategoryGeneric , 13, { 4 , 5 , 5 , 5 , 5 , 5 } }, // #98 [ref=2x]
3974 { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 5 , 7 , 0 , 0 , 0 } }, // #99 [ref=8x]
3975 { InstDB::RWInfo::kCategoryGeneric , 37, { 10, 5 , 9 , 0 , 0 , 0 } }, // #100 [ref=9x]
3976 { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 3 , 0 , 0 } }, // #101 [ref=3x]
3977 { InstDB::RWInfo::kCategoryGeneric , 36, { 11, 5 , 7 , 0 , 0 , 0 } }, // #102 [ref=1x]
3978 { InstDB::RWInfo::kCategoryGeneric , 37, { 11, 5 , 9 , 0 , 0 , 0 } }, // #103 [ref=1x]
3979 { InstDB::RWInfo::kCategoryVmov1_2 , 42, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #104 [ref=1x]
3980 { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 78, 7 , 0 , 0 , 0 } }, // #105 [ref=1x]
3981 { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 61, 3 , 0 , 0 , 0 } }, // #106 [ref=2x]
3982 { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 78, 3 , 0 , 0 , 0 } }, // #107 [ref=2x]
3983 { InstDB::RWInfo::kCategoryGeneric , 37, { 10, 61, 9 , 0 , 0 , 0 } }, // #108 [ref=1x]
3984 { InstDB::RWInfo::kCategoryGeneric , 44, { 10, 5 , 5 , 0 , 0 , 0 } }, // #109 [ref=9x]
3985 { InstDB::RWInfo::kCategoryGeneric , 46, { 10, 77, 0 , 0 , 0 , 0 } }, // #110 [ref=2x]
3986 { InstDB::RWInfo::kCategoryGeneric , 46, { 10, 3 , 0 , 0 , 0 , 0 } }, // #111 [ref=4x]
3987 { InstDB::RWInfo::kCategoryGeneric , 47, { 76, 43, 0 , 0 , 0 , 0 } }, // #112 [ref=4x]
3988 { InstDB::RWInfo::kCategoryGeneric , 6 , { 2 , 3 , 3 , 0 , 0 , 0 } }, // #113 [ref=60x]
3989 { InstDB::RWInfo::kCategoryGeneric , 36, { 4 , 61, 7 , 0 , 0 , 0 } }, // #114 [ref=1x]
3990 { InstDB::RWInfo::kCategoryGeneric , 37, { 4 , 78, 9 , 0 , 0 , 0 } }, // #115 [ref=1x]
3991 { InstDB::RWInfo::kCategoryGeneric , 36, { 6 , 7 , 7 , 0 , 0 , 0 } }, // #116 [ref=11x]
3992 { InstDB::RWInfo::kCategoryGeneric , 37, { 8 , 9 , 9 , 0 , 0 , 0 } }, // #117 [ref=11x]
3993 { InstDB::RWInfo::kCategoryGeneric , 48, { 11, 3 , 3 , 3 , 0 , 0 } }, // #118 [ref=15x]
3994 { InstDB::RWInfo::kCategoryGeneric , 49, { 35, 7 , 7 , 7 , 0 , 0 } }, // #119 [ref=4x]
3995 { InstDB::RWInfo::kCategoryGeneric , 50, { 44, 9 , 9 , 9 , 0 , 0 } }, // #120 [ref=4x]
3996 { InstDB::RWInfo::kCategoryGeneric , 36, { 26, 7 , 7 , 0 , 0 , 0 } }, // #121 [ref=1x]
3997 { InstDB::RWInfo::kCategoryGeneric , 37, { 53, 9 , 9 , 0 , 0 , 0 } }, // #122 [ref=1x]
3998 { InstDB::RWInfo::kCategoryGeneric , 14, { 35, 3 , 0 , 0 , 0 , 0 } }, // #123 [ref=2x]
3999 { InstDB::RWInfo::kCategoryGeneric , 5 , { 35, 9 , 0 , 0 , 0 , 0 } }, // #124 [ref=1x]
4000 { InstDB::RWInfo::kCategoryGeneric , 8 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #125 [ref=2x]
4001 { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #126 [ref=4x]
4002 { InstDB::RWInfo::kCategoryGeneric , 18, { 4 , 3 , 4 , 0 , 0 , 0 } }, // #127 [ref=2x]
4003 { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 61, 7 , 0 , 0 , 0 } }, // #128 [ref=11x]
4004 { InstDB::RWInfo::kCategoryGeneric , 37, { 10, 78, 9 , 0 , 0 , 0 } }, // #129 [ref=13x]
4005 { InstDB::RWInfo::kCategoryGeneric , 44, { 76, 77, 5 , 0 , 0 , 0 } }, // #130 [ref=2x]
4006 { InstDB::RWInfo::kCategoryGeneric , 44, { 11, 3 , 5 , 0 , 0 , 0 } }, // #131 [ref=4x]
4007 { InstDB::RWInfo::kCategoryGeneric , 51, { 74, 43, 77, 0 , 0 , 0 } }, // #132 [ref=4x]
4008 { InstDB::RWInfo::kCategoryVmaskmov , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #133 [ref=4x]
4009 { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 0 , 0 , 0 , 0 , 0 } }, // #134 [ref=2x]
4010 { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 0 , 0 , 0 , 0 , 0 } }, // #135 [ref=2x]
4011 { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 61, 61, 0 , 0 , 0 } }, // #136 [ref=1x]
4012 { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 7 , 7 , 0 , 0 , 0 } }, // #137 [ref=2x]
4013 { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 7 , 7 , 0 , 0 , 0 } }, // #138 [ref=1x]
4014 { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 61, 7 , 0 , 0 , 0 } }, // #139 [ref=2x]
4015 { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 61, 7 , 0 , 0 , 0 } }, // #140 [ref=1x]
4016 { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 78, 9 , 0 , 0 , 0 } }, // #141 [ref=1x]
4017 { InstDB::RWInfo::kCategoryGeneric , 0 , { 79, 0 , 0 , 0 , 0 , 0 } }, // #142 [ref=1x]
4018 { InstDB::RWInfo::kCategoryGeneric , 54, { 35, 11, 3 , 3 , 0 , 0 } }, // #143 [ref=2x]
4019 { InstDB::RWInfo::kCategoryGeneric , 13, { 74, 43, 43, 43, 43, 5 } }, // #144 [ref=2x]
4020 { InstDB::RWInfo::kCategoryGeneric , 6 , { 35, 3 , 3 , 0 , 0 , 0 } }, // #145 [ref=17x]
4021 { InstDB::RWInfo::kCategoryGeneric , 51, { 76, 77, 77, 0 , 0 , 0 } }, // #146 [ref=2x]
4022 { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 3 , 0 , 0 , 0 } }, // #147 [ref=4x]
4023 { InstDB::RWInfo::kCategoryGeneric , 7 , { 48, 5 , 0 , 0 , 0 , 0 } }, // #148 [ref=1x]
4024 { InstDB::RWInfo::kCategoryGeneric , 55, { 10, 5 , 40, 0 , 0 , 0 } }, // #149 [ref=1x]
4025 { InstDB::RWInfo::kCategoryGeneric , 56, { 10, 5 , 13, 0 , 0 , 0 } }, // #150 [ref=1x]
4026 { InstDB::RWInfo::kCategoryGeneric , 44, { 10, 5 , 5 , 5 , 0 , 0 } }, // #151 [ref=12x]
4027 { InstDB::RWInfo::kCategoryGeneric , 61, { 10, 5 , 5 , 5 , 0 , 0 } }, // #152 [ref=1x]
4028 { InstDB::RWInfo::kCategoryGeneric , 62, { 10, 5 , 5 , 0 , 0 , 0 } }, // #153 [ref=12x]
4029 { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 5 , 0 , 0 , 0 } }, // #154 [ref=9x]
4030 { InstDB::RWInfo::kCategoryGeneric , 63, { 11, 3 , 0 , 0 , 0 , 0 } }, // #155 [ref=2x]
4031 { InstDB::RWInfo::kCategoryGeneric , 0 , { 60, 17, 29, 0 , 0 , 0 } }, // #156 [ref=2x]
4032 { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 60, 17, 0 , 0 , 0 } }, // #157 [ref=4x]
4033 { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 60, 17, 0 , 0 , 0 } } // #158 [ref=8x]
4034 };
4035
4036 const InstDB::RWInfoOp InstDB::rwInfoOp[] = {
4037 { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, 0 }, // #0 [ref=15529x]
4038 { 0x0000000000000003u, 0x0000000000000003u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId }, // #1 [ref=10x]
4039 { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #2 [ref=214x]
4040 { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #3 [ref=987x]
4041 { 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #4 [ref=92x]
4042 { 0x000000000000FFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #5 [ref=305x]
4043 { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kRW }, // #6 [ref=18x]
4044 { 0x00000000000000FFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #7 [ref=186x]
4045 { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kRW }, // #8 [ref=18x]
4046 { 0x000000000000000Fu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #9 [ref=136x]
4047 { 0x0000000000000000u, 0x000000000000FFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #10 [ref=160x]
4048 { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #11 [ref=420x]
4049 { 0x0000000000000003u, 0x0000000000000003u, 0xFF, { 0 }, OpRWInfo::kRW }, // #12 [ref=1x]
4050 { 0x0000000000000003u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #13 [ref=34x]
4051 { 0x000000000000FFFFu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #14 [ref=4x]
4052 { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kMemBaseWrite | OpRWInfo::kMemIndexWrite }, // #15 [ref=1x]
4053 { 0x0000000000000000u, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #16 [ref=9x]
4054 { 0x000000000000000Fu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #17 [ref=23x]
4055 { 0x00000000000000FFu, 0x00000000000000FFu, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #18 [ref=2x]
4056 { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemPhysId }, // #19 [ref=3x]
4057 { 0x0000000000000000u, 0x0000000000000000u, 0x06, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemBaseRW | OpRWInfo::kMemBasePostModify | OpRWInfo::kMemPhysId }, // #20 [ref=3x]
4058 { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemBaseRW | OpRWInfo::kMemBasePostModify | OpRWInfo::kMemPhysId }, // #21 [ref=2x]
4059 { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #22 [ref=7x]
4060 { 0x00000000000000FFu, 0x00000000000000FFu, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #23 [ref=1x]
4061 { 0x00000000000000FFu, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #24 [ref=1x]
4062 { 0x00000000000000FFu, 0x0000000000000000u, 0x03, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #25 [ref=1x]
4063 { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #26 [ref=21x]
4064 { 0x000000000000000Fu, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #27 [ref=1x]
4065 { 0x000000000000000Fu, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #28 [ref=4x]
4066 { 0x000000000000000Fu, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #29 [ref=13x]
4067 { 0x000000000000000Fu, 0x0000000000000000u, 0x03, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #30 [ref=2x]
4068 { 0x0000000000000000u, 0x000000000000000Fu, 0x03, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #31 [ref=1x]
4069 { 0x000000000000000Fu, 0x000000000000000Fu, 0x01, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #32 [ref=1x]
4070 { 0x0000000000000000u, 0x00000000000000FFu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #33 [ref=1x]
4071 { 0x00000000000000FFu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #34 [ref=1x]
4072 { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #35 [ref=80x]
4073 { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite }, // #36 [ref=6x]
4074 { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite }, // #37 [ref=6x]
4075 { 0x0000000000000000u, 0x0000000000000003u, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId }, // #38 [ref=1x]
4076 { 0x0000000000000003u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #39 [ref=1x]
4077 { 0x0000000000000001u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #40 [ref=28x]
4078 { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #41 [ref=2x]
4079 { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #42 [ref=3x]
4080 { 0xFFFFFFFFFFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #43 [ref=45x]
4081 { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #44 [ref=30x]
4082 { 0x00000000000003FFu, 0x00000000000003FFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #45 [ref=22x]
4083 { 0x00000000000003FFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #46 [ref=13x]
4084 { 0x0000000000000000u, 0x00000000000003FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #47 [ref=1x]
4085 { 0x0000000000000000u, 0x0000000000000003u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #48 [ref=15x]
4086 { 0x0000000000000000u, 0x0000000000000003u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #49 [ref=2x]
4087 { 0x0000000000000000u, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #50 [ref=8x]
4088 { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #51 [ref=2x]
4089 { 0x0000000000000003u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #52 [ref=4x]
4090 { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #53 [ref=4x]
4091 { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kMemPhysId }, // #54 [ref=1x]
4092 { 0x0000000000000000u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #55 [ref=1x]
4093 { 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #56 [ref=14x]
4094 { 0x0000000000000000u, 0x0000000000000001u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId }, // #57 [ref=1x]
4095 { 0x0000000000000000u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #58 [ref=3x]
4096 { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kMemPhysId }, // #59 [ref=3x]
4097 { 0x000000000000000Fu, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #60 [ref=22x]
4098 { 0x000000000000FF00u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #61 [ref=23x]
4099 { 0x0000000000000000u, 0x000000000000FF00u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #62 [ref=1x]
4100 { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kMemBaseRW | OpRWInfo::kMemBasePostModify | OpRWInfo::kMemPhysId }, // #63 [ref=2x]
4101 { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #64 [ref=1x]
4102 { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #65 [ref=2x]
4103 { 0x0000000000000000u, 0x0000000000000000u, 0x06, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemPhysId }, // #66 [ref=1x]
4104 { 0x0000000000000000u, 0x000000000000000Fu, 0x01, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #67 [ref=5x]
4105 { 0x0000000000000000u, 0x000000000000FFFFu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #68 [ref=4x]
4106 { 0x0000000000000000u, 0x0000000000000007u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #69 [ref=2x]
4107 { 0x0000000000000000u, 0x0000000000000000u, 0x04, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #70 [ref=1x]
4108 { 0x0000000000000001u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #71 [ref=10x]
4109 { 0x0000000000000001u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #72 [ref=1x]
4110 { 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #73 [ref=30x]
4111 { 0x0000000000000000u, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #74 [ref=20x]
4112 { 0xFFFFFFFFFFFFFFFFu, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #75 [ref=7x]
4113 { 0x0000000000000000u, 0x00000000FFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #76 [ref=10x]
4114 { 0x00000000FFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #77 [ref=16x]
4115 { 0x000000000000FFF0u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #78 [ref=18x]
4116 { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId } // #79 [ref=1x]
4117 };
4118
4119 const InstDB::RWInfoRm InstDB::rwInfoRm[] = {
4120 { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , 0, 0 }, // #0 [ref=1894x]
4121 { InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #1 [ref=8x]
4122 { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, 0 }, // #2 [ref=190x]
4123 { InstDB::RWInfoRm::kCategoryFixed , 0x02, 16, 0, 0 }, // #3 [ref=122x]
4124 { InstDB::RWInfoRm::kCategoryFixed , 0x02, 8 , 0, 0 }, // #4 [ref=66x]
4125 { InstDB::RWInfoRm::kCategoryFixed , 0x02, 4 , 0, 0 }, // #5 [ref=36x]
4126 { InstDB::RWInfoRm::kCategoryConsistent, 0x04, 0 , 0, 0 }, // #6 [ref=270x]
4127 { InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , 0, 0 }, // #7 [ref=9x]
4128 { InstDB::RWInfoRm::kCategoryFixed , 0x00, 0 , 0, 0 }, // #8 [ref=63x]
4129 { InstDB::RWInfoRm::kCategoryFixed , 0x03, 0 , 0, 0 }, // #9 [ref=1x]
4130 { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #10 [ref=21x]
4131 { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , 0, 0 }, // #11 [ref=14x]
4132 { InstDB::RWInfoRm::kCategoryFixed , 0x00, 8 , 0, 0 }, // #12 [ref=22x]
4133 { InstDB::RWInfoRm::kCategoryFixed , 0x00, 16, 0, 0 }, // #13 [ref=21x]
4134 { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #14 [ref=15x]
4135 { InstDB::RWInfoRm::kCategoryFixed , 0x02, 1 , 0, 0 }, // #15 [ref=5x]
4136 { InstDB::RWInfoRm::kCategoryFixed , 0x00, 64, 0, 0 }, // #16 [ref=5x]
4137 { InstDB::RWInfoRm::kCategoryFixed , 0x01, 4 , 0, 0 }, // #17 [ref=6x]
4138 { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #18 [ref=26x]
4139 { InstDB::RWInfoRm::kCategoryFixed , 0x00, 10, 0, 0 }, // #19 [ref=2x]
4140 { InstDB::RWInfoRm::kCategoryNone , 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #20 [ref=5x]
4141 { InstDB::RWInfoRm::kCategoryFixed , 0x00, 2 , 0, 0 }, // #21 [ref=3x]
4142 { InstDB::RWInfoRm::kCategoryConsistent, 0x06, 0 , 0, 0 }, // #22 [ref=14x]
4143 { InstDB::RWInfoRm::kCategoryFixed , 0x03, 1 , 0, 0 }, // #23 [ref=1x]
4144 { InstDB::RWInfoRm::kCategoryFixed , 0x03, 4 , 0, 0 }, // #24 [ref=4x]
4145 { InstDB::RWInfoRm::kCategoryFixed , 0x03, 8 , 0, 0 }, // #25 [ref=3x]
4146 { InstDB::RWInfoRm::kCategoryFixed , 0x03, 2 , 0, 0 }, // #26 [ref=1x]
4147 { InstDB::RWInfoRm::kCategoryFixed , 0x02, 2 , 0, 0 }, // #27 [ref=6x]
4148 { InstDB::RWInfoRm::kCategoryFixed , 0x00, 4 , 0, 0 }, // #28 [ref=6x]
4149 { InstDB::RWInfoRm::kCategoryNone , 0x03, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #29 [ref=1x]
4150 { InstDB::RWInfoRm::kCategoryFixed , 0x03, 16, 0, 0 }, // #30 [ref=6x]
4151 { InstDB::RWInfoRm::kCategoryFixed , 0x01, 1 , 0, 0 }, // #31 [ref=32x]
4152 { InstDB::RWInfoRm::kCategoryFixed , 0x01, 8 , 0, 0 }, // #32 [ref=4x]
4153 { InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , 0, Features::kSSE4_1 }, // #33 [ref=1x]
4154 { InstDB::RWInfoRm::kCategoryNone , 0x02, 0 , 0, 0 }, // #34 [ref=4x]
4155 { InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #35 [ref=3x]
4156 { InstDB::RWInfoRm::kCategoryFixed , 0x04, 8 , 0, 0 }, // #36 [ref=34x]
4157 { InstDB::RWInfoRm::kCategoryFixed , 0x04, 4 , 0, 0 }, // #37 [ref=37x]
4158 { InstDB::RWInfoRm::kCategoryFixed , 0x00, 32, 0, 0 }, // #38 [ref=4x]
4159 { InstDB::RWInfoRm::kCategoryFixed , 0x02, 8 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #39 [ref=1x]
4160 { InstDB::RWInfoRm::kCategoryFixed , 0x02, 4 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #40 [ref=1x]
4161 { InstDB::RWInfoRm::kCategoryHalf , 0x02, 0 , 0, 0 }, // #41 [ref=14x]
4162 { InstDB::RWInfoRm::kCategoryHalf , 0x01, 0 , 0, 0 }, // #42 [ref=10x]
4163 { InstDB::RWInfoRm::kCategoryConsistent, 0x04, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #43 [ref=4x]
4164 { InstDB::RWInfoRm::kCategoryFixed , 0x04, 16, 0, 0 }, // #44 [ref=27x]
4165 { InstDB::RWInfoRm::kCategoryFixed , 0x02, 64, 0, 0 }, // #45 [ref=6x]
4166 { InstDB::RWInfoRm::kCategoryFixed , 0x01, 16, 0, 0 }, // #46 [ref=6x]
4167 { InstDB::RWInfoRm::kCategoryFixed , 0x01, 32, 0, 0 }, // #47 [ref=4x]
4168 { InstDB::RWInfoRm::kCategoryConsistent, 0x0C, 0 , 0, 0 }, // #48 [ref=15x]
4169 { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 8 , 0, 0 }, // #49 [ref=4x]
4170 { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 4 , 0, 0 }, // #50 [ref=4x]
4171 { InstDB::RWInfoRm::kCategoryFixed , 0x04, 32, 0, 0 }, // #51 [ref=6x]
4172 { InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , 0, 0 }, // #52 [ref=13x]
4173 { InstDB::RWInfoRm::kCategoryFixed , 0x03, 8 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #53 [ref=1x]
4174 { InstDB::RWInfoRm::kCategoryConsistent, 0x08, 0 , 0, 0 }, // #54 [ref=2x]
4175 { InstDB::RWInfoRm::kCategoryFixed , 0x04, 1 , 0, 0 }, // #55 [ref=1x]
4176 { InstDB::RWInfoRm::kCategoryFixed , 0x04, 2 , 0, 0 }, // #56 [ref=1x]
4177 { InstDB::RWInfoRm::kCategoryQuarter , 0x01, 0 , 0, 0 }, // #57 [ref=6x]
4178 { InstDB::RWInfoRm::kCategoryEighth , 0x01, 0 , 0, 0 }, // #58 [ref=3x]
4179 { InstDB::RWInfoRm::kCategoryQuarter , 0x02, 0 , 0, 0 }, // #59 [ref=4x]
4180 { InstDB::RWInfoRm::kCategoryEighth , 0x02, 0 , 0, 0 }, // #60 [ref=2x]
4181 { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 16, 0, 0 }, // #61 [ref=1x]
4182 { InstDB::RWInfoRm::kCategoryFixed , 0x06, 16, 0, 0 }, // #62 [ref=12x]
4183 { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, Features::kAVX512_BW } // #63 [ref=2x]
4184 };
4185 // ----------------------------------------------------------------------------
4186 // ${InstRWInfoTable:End}
4187
4188 // ============================================================================
4189 // [asmjit::x86::InstDB - Unit]
4190 // ============================================================================
4191
4192 #if defined(ASMJIT_TEST)
UNIT(x86_inst_db)4193 UNIT(x86_inst_db) {
4194 INFO("Checking validity of Inst enums");
4195
4196 // Cross-validate prefixes.
4197 EXPECT(Inst::kOptionRex == 0x40000000u, "REX prefix must be at 0x40000000");
4198 EXPECT(Inst::kOptionVex3 == 0x00000400u, "VEX3 prefix must be at 0x00000400");
4199 EXPECT(Inst::kOptionEvex == 0x00001000u, "EVEX prefix must be at 0x00001000");
4200
4201 // These could be combined together to form a valid REX prefix, they must match.
4202 EXPECT(uint32_t(Inst::kOptionOpCodeB) == uint32_t(Opcode::kB), "Opcode::kB must match Inst::kOptionOpCodeB");
4203 EXPECT(uint32_t(Inst::kOptionOpCodeX) == uint32_t(Opcode::kX), "Opcode::kX must match Inst::kOptionOpCodeX");
4204 EXPECT(uint32_t(Inst::kOptionOpCodeR) == uint32_t(Opcode::kR), "Opcode::kR must match Inst::kOptionOpCodeR");
4205 EXPECT(uint32_t(Inst::kOptionOpCodeW) == uint32_t(Opcode::kW), "Opcode::kW must match Inst::kOptionOpCodeW");
4206
4207 uint32_t rex_rb = (Opcode::kR >> Opcode::kREX_Shift) | (Opcode::kB >> Opcode::kREX_Shift) | 0x40;
4208 uint32_t rex_rw = (Opcode::kR >> Opcode::kREX_Shift) | (Opcode::kW >> Opcode::kREX_Shift) | 0x40;
4209
4210 EXPECT(rex_rb == 0x45, "Opcode::kR|B must form a valid REX prefix (0x45) if combined with 0x40");
4211 EXPECT(rex_rw == 0x4C, "Opcode::kR|W must form a valid REX prefix (0x4C) if combined with 0x40");
4212 }
4213 #endif
4214
4215 ASMJIT_END_SUB_NAMESPACE
4216
4217 #endif // ASMJIT_BUILD_X86
4218