1 { 2 This file is part of the Free Pascal run time library. 3 4 A file in Amiga system run time library. 5 Copyright (c) 1998 by Nils Sjoholm 6 member of the Amiga RTL development team. 7 8 See the file COPYING.FPC, included in this distribution, 9 for details about the copyright. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 14 15 **********************************************************************} 16 17 { 18 registers and bits in the Complex Interface Adapter (CIA) chip 19 } 20 21 {$PACKRECORDS 2} 22 unit hardware; 23 24 INTERFACE 25 uses exec; 26 27 { 28 * ciaa is on an ODD Pointer (e.g. the low Byte) -- $bfe001 29 * ciab is on an EVEN Pointer (e.g. the high Byte) -- $bfd000 30 * 31 * do this to get the definitions: 32 * extern struct CIA ciaa, ciab; 33 } 34 35 Type 36 37 pCIA = ^tCIA; 38 tCIA = record 39 ciapra : Byte; 40 pad0 : Array [0..254] of Byte; 41 ciaprb : Byte; 42 pad1 : Array [0..254] of Byte; 43 ciaddra : Byte; 44 pad2 : Array [0..254] of Byte; 45 ciaddrb : Byte; 46 pad3 : Array [0..254] of Byte; 47 ciatalo : Byte; 48 pad4 : Array [0..254] of Byte; 49 ciatahi : Byte; 50 pad5 : Array [0..254] of Byte; 51 ciatblo : Byte; 52 pad6 : Array [0..254] of Byte; 53 ciatbhi : Byte; 54 pad7 : Array [0..254] of Byte; 55 ciatodlow : Byte; 56 pad8 : Array [0..254] of Byte; 57 ciatodmid : Byte; 58 pad9 : Array [0..254] of Byte; 59 ciatodhi : Byte; 60 pad10 : Array [0..254] of Byte; 61 unusedreg : Byte; 62 pad11 : Array [0..254] of Byte; 63 ciasdr : Byte; 64 pad12 : Array [0..254] of Byte; 65 ciaicr : Byte; 66 pad13 : Array [0..254] of Byte; 67 ciacra : Byte; 68 pad14 : Array [0..254] of Byte; 69 ciacrb : Byte; 70 end; 71 72 73 Const 74 75 { interrupt control register bit numbers } 76 77 CIAICRB_TA = 0; 78 CIAICRB_TB = 1; 79 CIAICRB_ALRM = 2; 80 CIAICRB_SP = 3; 81 CIAICRB_FLG = 4; 82 CIAICRB_IR = 7; 83 CIAICRB_SETCLR = 7; 84 85 { control register A bit numbers } 86 87 CIACRAB_START = 0; 88 CIACRAB_PBON = 1; 89 CIACRAB_OUTMODE = 2; 90 CIACRAB_RUNMODE = 3; 91 CIACRAB_LOAD = 4; 92 CIACRAB_INMODE = 5; 93 CIACRAB_SPMODE = 6; 94 CIACRAB_TODIN = 7; 95 96 { control register B bit numbers } 97 98 CIACRBB_START = 0; 99 CIACRBB_PBON = 1; 100 CIACRBB_OUTMODE = 2; 101 CIACRBB_RUNMODE = 3; 102 CIACRBB_LOAD = 4; 103 CIACRBB_INMODE0 = 5; 104 CIACRBB_INMODE1 = 6; 105 CIACRBB_ALARM = 7; 106 107 { interrupt control register masks } 108 109 CIAICRF_TA = $01; 110 CIAICRF_TB = $02; 111 CIAICRF_ALRM = $04; 112 CIAICRF_SP = $08; 113 CIAICRF_FLG = $10; 114 CIAICRF_IR = $80; 115 CIAICRF_SETCLR = $80; 116 117 { control register A register masks } 118 119 CIACRAF_START = $01; 120 CIACRAF_PBON = $02; 121 CIACRAF_OUTMODE = $04; 122 CIACRAF_RUNMODE = $08; 123 CIACRAF_LOAD = $10; 124 CIACRAF_INMODE = $20; 125 CIACRAF_SPMODE = $40; 126 CIACRAF_TODIN = $80; 127 128 { control register B register masks } 129 130 CIACRBF_START = $01; 131 CIACRBF_PBON = $02; 132 CIACRBF_OUTMODE = $04; 133 CIACRBF_RUNMODE = $08; 134 CIACRBF_LOAD = $10; 135 CIACRBF_INMODE0 = $20; 136 CIACRBF_INMODE1 = $40; 137 CIACRBF_ALARM = $80; 138 139 { control register B INMODE masks } 140 141 CIACRBF_IN_PHI2 = 0; 142 CIACRBF_IN_CNT = CIACRBF_INMODE0; 143 CIACRBF_IN_TA = CIACRBF_INMODE1; 144 CIACRBF_IN_CNT_TA = CIACRBF_INMODE0 + CIACRBF_INMODE1; 145 146 { 147 * Port definitions -- what each bit in a cia peripheral register is tied to 148 } 149 150 { ciaa port A (0xbfe001) } 151 152 CIAB_GAMEPORT1 = 7; { gameport 1, pin 6 (fire button*) } 153 CIAB_GAMEPORT0 = 6; { gameport 0, pin 6 (fire button*) } 154 CIAB_DSKRDY = 5; { disk ready* } 155 CIAB_DSKTRACK0 = 4; { disk on track 00* } 156 CIAB_DSKPROT = 3; { disk write protect* } 157 CIAB_DSKCHANGE = 2; { disk change* } 158 CIAB_LED = 1; { led light control (0==>bright) } 159 CIAB_OVERLAY = 0; { memory overlay bit } 160 161 { ciaa port B (0xbfe101) -- parallel port } 162 163 { ciab port A (0xbfd000) -- serial and printer control } 164 165 CIAB_COMDTR = 7; { serial Data Terminal Ready* } 166 CIAB_COMRTS = 6; { serial Request to Send* } 167 CIAB_COMCD = 5; { serial Carrier Detect* } 168 CIAB_COMCTS = 4; { serial Clear to Send* } 169 CIAB_COMDSR = 3; { serial Data Set Ready* } 170 CIAB_PRTRSEL = 2; { printer SELECT } 171 CIAB_PRTRPOUT = 1; { printer paper out } 172 CIAB_PRTRBUSY = 0; { printer busy } 173 174 { ciab port B (0xbfd100) -- disk control } 175 176 CIAB_DSKMOTOR = 7; { disk motorr* } 177 CIAB_DSKSEL3 = 6; { disk select unit 3* } 178 CIAB_DSKSEL2 = 5; { disk select unit 2* } 179 CIAB_DSKSEL1 = 4; { disk select unit 1* } 180 CIAB_DSKSEL0 = 3; { disk select unit 0* } 181 CIAB_DSKSIDE = 2; { disk side select* } 182 CIAB_DSKDIREC = 1; { disk direction of seek* } 183 CIAB_DSKSTEP = 0; { disk step heads* } 184 185 { ciaa port A (0xbfe001) } 186 187 CIAF_GAMEPORT1 = 128; 188 CIAF_GAMEPORT0 = 64; 189 CIAF_DSKRDY = 32; 190 CIAF_DSKTRACK0 = 16; 191 CIAF_DSKPROT = 8; 192 CIAF_DSKCHANGE = 4; 193 CIAF_LED = 2; 194 CIAF_OVERLAY = 1; 195 196 { ciaa port B (0xbfe101) -- parallel port } 197 198 { ciab port A (0xbfd000) -- serial and printer control } 199 200 CIAF_COMDTR = 128; 201 CIAF_COMRTS = 64; 202 CIAF_COMCD = 32; 203 CIAF_COMCTS = 16; 204 CIAF_COMDSR = 8; 205 CIAF_PRTRSEL = 4; 206 CIAF_PRTRPOUT = 2; 207 CIAF_PRTRBUSY = 1; 208 209 { ciab port B (0xbfd100) -- disk control } 210 211 CIAF_DSKMOTOR = 128; 212 CIAF_DSKSEL3 = 64; 213 CIAF_DSKSEL2 = 32; 214 CIAF_DSKSEL1 = 16; 215 CIAF_DSKSEL0 = 8; 216 CIAF_DSKSIDE = 4; 217 CIAF_DSKDIREC = 2; 218 CIAF_DSKSTEP = 1; 219 220 221 Type 222 223 pAudChannel = ^tAudChannel; 224 tAudChannel = record 225 ac_ptr : Pointer; { ptr to start of waveform data } 226 ac_len : Word; { length of waveform in words } 227 ac_per : Word; { sample period } 228 ac_vol : Word; { volume } 229 ac_dat : Word; { sample pair } 230 ac_pad : Array [0..1] of Word; { unused } 231 end; 232 233 pSpriteDef = ^tSpriteDef; 234 tSpriteDef = record 235 pos : Word; 236 ctl : Word; 237 dataa : Word; 238 datab : Word; 239 end; 240 241 pCustom = ^tCustom; 242 tCustom = record 243 bltddat : Word; 244 dmaconr : Word; 245 vposr : Word; 246 vhposr : Word; 247 dskdatr : Word; 248 joy0dat : Word; 249 joy1dat : Word; 250 clxdat : Word; 251 adkconr : Word; 252 pot0dat : Word; 253 pot1dat : Word; 254 potinp : Word; 255 serdatr : Word; 256 dskbytr : Word; 257 intenar : Word; 258 intreqr : Word; 259 dskpt : Pointer; 260 dsklen : Word; 261 dskdat : Word; 262 refptr : Word; 263 vposw : Word; 264 vhposw : Word; 265 copcon : Word; 266 serdat : Word; 267 serper : Word; 268 potgo : Word; 269 joytest : Word; 270 strequ : Word; 271 strvbl : Word; 272 strhor : Word; 273 strlong : Word; 274 bltcon0 : Word; 275 bltcon1 : Word; 276 bltafwm : Word; 277 bltalwm : Word; 278 bltcpt : Pointer; 279 bltbpt : Pointer; 280 bltapt : Pointer; 281 bltdpt : Pointer; 282 bltsize : Word; 283 pad2d : Byte; 284 bltcon0l : Byte; 285 bltsizv : Word; 286 bltsizh : Word; 287 bltcmod : Word; 288 bltbmod : Word; 289 bltamod : Word; 290 bltdmod : Word; 291 pad34 : Array [0..3] of Word; 292 bltcdat : Word; 293 bltbdat : Word; 294 bltadat : Word; 295 pad3b : Array [0..2] of Word; 296 deniseid : Word; 297 dsksync : Word; 298 cop1lc : Longint; 299 cop2lc : Longint; 300 copjmp1 : Word; 301 copjmp2 : Word; 302 copins : Word; 303 diwstrt : Word; 304 diwstop : Word; 305 ddfstrt : Word; 306 ddfstop : Word; 307 dmacon : Word; 308 clxcon : Word; 309 intena : Word; 310 intreq : Word; 311 adkcon : Word; 312 aud : Array [0..3] of tAudChannel; 313 bplpt : Array [0..7] of Pointer; 314 bplcon0 : Word; 315 bplcon1 : Word; 316 bplcon2 : Word; 317 bplcon3 : Word; 318 bpl1mod : Word; 319 bpl2mod : Word; 320 bplcon4 : Word; 321 clxcon2 : Word; 322 bpldat : Array [0..7] of Word; 323 sprpt : Array [0..7] of Pointer; 324 spr : Array [0..7] of tSpriteDef; 325 color : Array [0..31] of Word; 326 htotal : Word; 327 hsstop : Word; 328 hbstrt : Word; 329 hbstop : Word; 330 vtotal : Word; 331 vsstop : Word; 332 vbstrt : Word; 333 vbstop : Word; 334 sprhstrt : Word; 335 sprhstop : Word; 336 bplhstrt : Word; 337 bplhstop : Word; 338 hhposw : Word; 339 hhposr : Word; 340 beamcon0 : Word; 341 hsstrt : Word; 342 vsstrt : Word; 343 hcenter : Word; 344 diwhigh : Word; 345 padf3 : Array [0..10] of Word; 346 fmode : Word; 347 end; 348 349 CONST 350 { defines for beamcon register } 351 VARVBLANK = $1000; { Variable vertical blank enable } 352 LOLDIS = $0800; { long line disable } 353 CSCBLANKEN = $0400; { redirect composite sync } 354 VARVSYNC = $0200; { Variable vertical sync enable } 355 VARHSYNC = $0100; { Variable horizontal sync enable } 356 VARBEAM = $0080; { variable beam counter enable } 357 DISPLAYDUAL = $0040; { use UHRES pointer AND standard pointers } 358 DISPLAYPAL = $0020; { set decodes to generate PAL display } 359 VARCSYNC = $0010; { Variable composite sync enable } 360 CSBLANK = $0008; { Composite blank out to CSY* pin } 361 CSYNCTRUE = $0004; { composite sync TRUE signal } 362 VSYNCTRUE = $0002; { vertical sync TRUE } 363 HSYNCTRUE = $0001; { horizontal sync TRUE } 364 365 { new defines for bplcon0 } 366 USE_BPLCON3 = 1; 367 368 { new defines for bplcon2 } 369 BPLCON2_ZDCTEN = 1024; { colormapped genlock bit } 370 BPLCON2_ZDBPEN = 2048; { use bitplane as genlock bits } 371 BPLCON2_ZDBPSEL0 = 4096; { three bits to select one } 372 BPLCON2_ZDBPSEL1 = 8192; { of 8 bitplanes in } 373 BPLCON2_ZDBPSEL2 = 16384; { ZDBPEN genlock mode } 374 375 { defines for bplcon3 register } 376 BPLCON3_EXTBLNKEN = 1; { external blank enable } 377 BPLCON3_EXTBLKZD = 2; { external blank ored into trnsprncy } 378 BPLCON3_ZDCLKEN = 4; { zd pin outputs a 14mhz clock} 379 BPLCON3_BRDNTRAN = 16; { border is opaque } 380 BPLCON3_BRDNBLNK = 32; { border is opaque } 381 382 383 Const 384 385 ADKB_SETCLR = 15; { standard set/clear bit } 386 ADKB_PRECOMP1 = 14; { two bits of precompensation } 387 ADKB_PRECOMP0 = 13; 388 ADKB_MFMPREC = 12; { use mfm style precompensation } 389 ADKB_UARTBRK = 11; { force uart output to zero } 390 ADKB_WORDSYNC = 10; { enable DSKSYNC register matching } 391 ADKB_MSBSYNC = 9; { (Apple GCR Only) sync on MSB for reading } 392 ADKB_FAST = 8; { 1 -> 2 us/bit (mfm), 2 -> 4 us/bit (gcr) } 393 ADKB_USE3PN = 7; { use aud chan 3 to modulate period of ?? } 394 ADKB_USE2P3 = 6; { use aud chan 2 to modulate period of 3 } 395 ADKB_USE1P2 = 5; { use aud chan 1 to modulate period of 2 } 396 ADKB_USE0P1 = 4; { use aud chan 0 to modulate period of 1 } 397 ADKB_USE3VN = 3; { use aud chan 3 to modulate volume of ?? } 398 ADKB_USE2V3 = 2; { use aud chan 2 to modulate volume of 3 } 399 ADKB_USE1V2 = 1; { use aud chan 1 to modulate volume of 2 } 400 ADKB_USE0V1 = 0; { use aud chan 0 to modulate volume of 1 } 401 402 ADKF_SETCLR = $8000; 403 ADKF_PRECOMP1 = $4000; 404 ADKF_PRECOMP0 = $2000; 405 ADKF_MFMPREC = $1000; 406 ADKF_UARTBRK = $0800; 407 ADKF_WORDSYNC = $0400; 408 ADKF_MSBSYNC = $0200; 409 ADKF_FAST = $0100; 410 ADKF_USE3PN = $0080; 411 ADKF_USE2P3 = $0040; 412 ADKF_USE1P2 = $0020; 413 ADKF_USE0P1 = $0010; 414 ADKF_USE3VN = $0008; 415 ADKF_USE2V3 = $0004; 416 ADKF_USE1V2 = $0002; 417 ADKF_USE0V1 = $0001; 418 419 ADKF_PRE000NS = 0; { 000 ns of precomp } 420 ADKF_PRE140NS = ADKF_PRECOMP0; { 140 ns of precomp } 421 ADKF_PRE280NS = ADKF_PRECOMP1; { 280 ns of precomp } 422 ADKF_PRE560NS = ADKF_PRECOMP0 + ADKF_PRECOMP1; { 560 ns of precomp } 423 424 425 Const 426 427 HSIZEBITS = 6; 428 VSIZEBITS = 16 - HSIZEBITS; 429 HSIZEMASK = $3F; { 2^6 - 1 } 430 VSIZEMASK = $3FF; { 2^10 - 1 } 431 432 MAXBYTESPERROW = 128; 433 434 { definitions for blitter control register 0 } 435 436 ABC = $80; 437 ABNC = $40; 438 ANBC = $20; 439 ANBNC = $10; 440 NABC = $08; 441 NABNC = $04; 442 NANBC = $02; 443 NANBNC = $01; 444 445 { some commonly used operations } 446 447 A_OR_B = ABC + ANBC + NABC + ABNC + ANBNC + NABNC; 448 A_OR_C = ABC + NABC + ABNC + ANBC + NANBC + ANBNC; 449 A_XOR_C = NABC + ABNC + NANBC + ANBNC; 450 A_TO_D = ABC + ANBC + ABNC + ANBNC; 451 452 BC0B_DEST = 8; 453 BC0B_SRCC = 9; 454 BC0B_SRCB = 10; 455 BC0B_SRCA = 11; 456 BC0F_DEST = $100; 457 BC0F_SRCC = $200; 458 BC0F_SRCB = $400; 459 BC0F_SRCA = $800; 460 461 BC1F_DESC = 2; { blitter descend direction } 462 463 DEST = $100; 464 SRCC = $200; 465 SRCB = $400; 466 SRCA = $800; 467 468 ASHIFTSHIFT = 12; { bits to right align ashift value } 469 BSHIFTSHIFT = 12; { bits to right align bshift value } 470 471 { definations for blitter control register 1 } 472 473 LINEMODE = $01; 474 FILL_OR = $08; 475 FILL_XOR = $10; 476 FILL_CARRYIN = $04; 477 ONEDOT = $02; { one dot per horizontal line } 478 OVFLAG = $20; 479 SIGNFLAG = $40; 480 BLITREVERSE = $02; 481 482 SUD = $10; 483 SUL = $08; 484 AUL = $04; 485 486 OCTANT8 = 24; 487 OCTANT7 = 4; 488 OCTANT6 = 12; 489 OCTANT5 = 28; 490 OCTANT4 = 20; 491 OCTANT3 = 8; 492 OCTANT2 = 0; 493 OCTANT1 = 16; 494 495 type 496 pbltnode = ^tbltnode; 497 tbltnode = record 498 n : pbltnode; 499 _function : Pointer; 500 stat : Byte; 501 blitsize : smallint; 502 beamsync : smallint; 503 cleanup : Pointer; 504 end; 505 506 Const 507 508 { write definitions for dmaconw } 509 510 DMAF_SETCLR = $8000; 511 DMAF_AUDIO = $000F; { 4 bit mask } 512 DMAF_AUD0 = $0001; 513 DMAF_AUD1 = $0002; 514 DMAF_AUD2 = $0004; 515 DMAF_AUD3 = $0008; 516 DMAF_DISK = $0010; 517 DMAF_SPRITE = $0020; 518 DMAF_BLITTER = $0040; 519 DMAF_COPPER = $0080; 520 DMAF_RASTER = $0100; 521 DMAF_MASTER = $0200; 522 DMAF_BLITHOG = $0400; 523 DMAF_ALL = $01FF; { all dma channels } 524 525 { read definitions for dmaconr } 526 { bits 0-8 correspnd to dmaconw definitions } 527 528 DMAF_BLTDONE = $4000; 529 DMAF_BLTNZERO = $2000; 530 531 DMAB_SETCLR = 15; 532 DMAB_AUD0 = 0; 533 DMAB_AUD1 = 1; 534 DMAB_AUD2 = 2; 535 DMAB_AUD3 = 3; 536 DMAB_DISK = 4; 537 DMAB_SPRITE = 5; 538 DMAB_BLITTER = 6; 539 DMAB_COPPER = 7; 540 DMAB_RASTER = 8; 541 DMAB_MASTER = 9; 542 DMAB_BLITHOG = 10; 543 DMAB_BLTDONE = 14; 544 DMAB_BLTNZERO = 13; 545 546 547 Const 548 549 INTB_SETCLR = 15; { Set/Clear control bit. Determines if bits } 550 { written with a 1 get set or cleared. Bits } 551 { written with a zero are allways unchanged } 552 INTB_INTEN = 14; { Master interrupt (enable only ) } 553 INTB_EXTER = 13; { External interrupt } 554 INTB_DSKSYNC = 12; { Disk re-SYNChronized } 555 INTB_RBF = 11; { serial port Receive Buffer Full } 556 INTB_AUD3 = 10; { Audio channel 3 block finished } 557 INTB_AUD2 = 9; { Audio channel 2 block finished } 558 INTB_AUD1 = 8; { Audio channel 1 block finished } 559 INTB_AUD0 = 7; { Audio channel 0 block finished } 560 INTB_BLIT = 6; { Blitter finished } 561 INTB_VERTB = 5; { start of Vertical Blank } 562 INTB_COPER = 4; { Coprocessor } 563 INTB_PORTS = 3; { I/O Ports and timers } 564 INTB_SOFTINT = 2; { software interrupt request } 565 INTB_DSKBLK = 1; { Disk Block done } 566 INTB_TBE = 0; { serial port Transmit Buffer Empty } 567 568 569 INTF_SETCLR = $8000; 570 INTF_INTEN = $4000; 571 INTF_EXTER = $2000; 572 INTF_DSKSYNC = $1000; 573 INTF_RBF = $0800; 574 INTF_AUD3 = $0400; 575 INTF_AUD2 = $0200; 576 INTF_AUD1 = $0100; 577 INTF_AUD0 = $0080; 578 INTF_BLIT = $0040; 579 INTF_VERTB = $0020; 580 INTF_COPER = $0010; 581 INTF_PORTS = $0008; 582 INTF_SOFTINT = $0004; 583 INTF_DSKBLK = $0002; 584 INTF_TBE = $0001; 585 586 IMPLEMENTATION 587 588 end. 589