1unit ATmega32C1; 2 3{$goto on} 4 5interface 6 7var 8 // PORTB 9 PORTB : byte absolute $00+$25; // Port B Data Register 10 DDRB : byte absolute $00+$24; // Port B Data Direction Register 11 PINB : byte absolute $00+$23; // Port B Input Pins 12 // PORTC 13 PORTC : byte absolute $00+$28; // Port C Data Register 14 DDRC : byte absolute $00+$27; // Port C Data Direction Register 15 PINC : byte absolute $00+$26; // Port C Input Pins 16 // PORTD 17 PORTD : byte absolute $00+$2B; // Port D Data Register 18 DDRD : byte absolute $00+$2A; // Port D Data Direction Register 19 PIND : byte absolute $00+$29; // Port D Input Pins 20 // CAN 21 CANGCON : byte absolute $00+$D8; // CAN General Control Register 22 CANGSTA : byte absolute $00+$D9; // CAN General Status Register 23 CANGIT : byte absolute $00+$DA; // CAN General Interrupt Register Flags 24 CANGIE : byte absolute $00+$DB; // CAN General Interrupt Enable Register 25 CANEN2 : byte absolute $00+$DC; // Enable MOb Register 2 26 CANEN1 : byte absolute $00+$DD; // Enable MOb Register 1(empty) 27 CANIE2 : byte absolute $00+$DE; // Enable Interrupt MOb Register 2 28 CANIE1 : byte absolute $00+$DF; // Enable Interrupt MOb Register 1 (empty) 29 CANSIT2 : byte absolute $00+$E0; // CAN Status Interrupt MOb Register 2 30 CANSIT1 : byte absolute $00+$E1; // CAN Status Interrupt MOb Register 1 (empty) 31 CANBT1 : byte absolute $00+$E2; // CAN Bit Timing Register 1 32 CANBT2 : byte absolute $00+$E3; // CAN Bit Timing Register 2 33 CANBT3 : byte absolute $00+$E4; // CAN Bit Timing Register 3 34 CANTCON : byte absolute $00+$E5; // Timer Control Register 35 CANTIML : byte absolute $00+$E6; // Timer Register Low 36 CANTIMH : byte absolute $00+$E7; // Timer Register High 37 CANTTCL : byte absolute $00+$E8; // TTC Timer Register Low 38 CANTTCH : byte absolute $00+$E9; // TTC Timer Register High 39 CANTEC : byte absolute $00+$EA; // Transmit Error Counter Register 40 CANREC : byte absolute $00+$EB; // Receive Error Counter Register 41 CANHPMOB : byte absolute $00+$EC; // Highest Priority MOb Register 42 CANPAGE : byte absolute $00+$ED; // Page MOb Register 43 CANSTMOB : byte absolute $00+$EE; // MOb Status Register 44 CANCDMOB : byte absolute $00+$EF; // MOb Control and DLC Register 45 CANIDT4 : byte absolute $00+$F0; // Identifier Tag Register 4 46 CANIDT3 : byte absolute $00+$F1; // Identifier Tag Register 3 47 CANIDT2 : byte absolute $00+$F2; // Identifier Tag Register 2 48 CANIDT1 : byte absolute $00+$F3; // Identifier Tag Register 1 49 CANIDM4 : byte absolute $00+$F4; // Identifier Mask Register 4 50 CANIDM3 : byte absolute $00+$F5; // Identifier Mask Register 3 51 CANIDM2 : byte absolute $00+$F6; // Identifier Mask Register 2 52 CANIDM1 : byte absolute $00+$F7; // Identifier Mask Register 1 53 CANSTML : byte absolute $00+$F8; // Time Stamp Register Low 54 CANSTMH : byte absolute $00+$F9; // Time Stamp Register High 55 CANMSG : byte absolute $00+$FA; // Message Data Register 56 // ANALOG_COMPARATOR 57 AC0CON : byte absolute $00+$94; // Analog Comparator 0 Control Register 58 AC1CON : byte absolute $00+$95; // Analog Comparator 1 Control Register 59 AC2CON : byte absolute $00+$96; // Analog Comparator 2 Control Register 60 AC3CON : byte absolute $00+$97; // Analog Comparator 3 Control Register 61 ACSR : byte absolute $00+$50; // Analog Comparator Status Register 62 // DA_CONVERTER 63 DACH : byte absolute $00+$92; // DAC Data Register High Byte 64 DACL : byte absolute $00+$91; // DAC Data Register Low Byte 65 DACON : byte absolute $00+$90; // DAC Control Register 66 // CPU 67 SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register 68 SREG : byte absolute $00+$5F; // Status Register 69 SP : word absolute $00+$5D; // Stack Pointer 70 SPL : byte absolute $00+$5D; // Stack Pointer 71 SPH : byte absolute $00+$5D+1; // Stack Pointer 72 MCUCR : byte absolute $00+$55; // MCU Control Register 73 MCUSR : byte absolute $00+$54; // MCU Status Register 74 OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value 75 CLKPR : byte absolute $00+$61; // 76 SMCR : byte absolute $00+$53; // Sleep Mode Control Register 77 GPIOR2 : byte absolute $00+$3A; // General Purpose IO Register 2 78 GPIOR1 : byte absolute $00+$39; // General Purpose IO Register 1 79 GPIOR0 : byte absolute $00+$3E; // General Purpose IO Register 0 80 PLLCSR : byte absolute $00+$49; // PLL Control And Status Register 81 PRR : byte absolute $00+$64; // Power Reduction Register 82 // PORTE 83 PORTE : byte absolute $00+$2E; // Port E Data Register 84 DDRE : byte absolute $00+$2D; // Port E Data Direction Register 85 PINE : byte absolute $00+$2C; // Port E Input Pins 86 // TIMER_COUNTER_0 87 TIMSK0 : byte absolute $00+$6E; // Timer/Counter0 Interrupt Mask Register 88 TIFR0 : byte absolute $00+$35; // Timer/Counter0 Interrupt Flag register 89 TCCR0A : byte absolute $00+$44; // Timer/Counter Control Register A 90 TCCR0B : byte absolute $00+$45; // Timer/Counter Control Register B 91 TCNT0 : byte absolute $00+$46; // Timer/Counter0 92 OCR0A : byte absolute $00+$47; // Timer/Counter0 Output Compare Register 93 OCR0B : byte absolute $00+$48; // Timer/Counter0 Output Compare Register 94 GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register 95 // TIMER_COUNTER_1 96 TIMSK1 : byte absolute $00+$6F; // Timer/Counter Interrupt Mask Register 97 TIFR1 : byte absolute $00+$36; // Timer/Counter Interrupt Flag register 98 TCCR1A : byte absolute $00+$80; // Timer/Counter1 Control Register A 99 TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B 100 TCCR1C : byte absolute $00+$82; // Timer/Counter1 Control Register C 101 TCNT1 : word absolute $00+$84; // Timer/Counter1 Bytes 102 TCNT1L : byte absolute $00+$84; // Timer/Counter1 Bytes 103 TCNT1H : byte absolute $00+$84+1; // Timer/Counter1 Bytes 104 OCR1A : word absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes 105 OCR1AL : byte absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes 106 OCR1AH : byte absolute $00+$88+1; // Timer/Counter1 Output Compare Register Bytes 107 OCR1B : word absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes 108 OCR1BL : byte absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes 109 OCR1BH : byte absolute $00+$8A+1; // Timer/Counter1 Output Compare Register Bytes 110 ICR1 : word absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 111 ICR1L : byte absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 112 ICR1H : byte absolute $00+$86+1; // Timer/Counter1 Input Capture Register Bytes 113 // AD_CONVERTER 114 ADMUX : byte absolute $00+$7C; // The ADC multiplexer Selection Register 115 ADCSRA : byte absolute $00+$7A; // The ADC Control and Status register 116 ADC : word absolute $00+$78; // ADC Data Register Bytes 117 ADCL : byte absolute $00+$78; // ADC Data Register Bytes 118 ADCH : byte absolute $00+$78+1; // ADC Data Register Bytes 119 ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B 120 DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0 121 DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 0 122 AMP0CSR : byte absolute $00+$75; // 123 AMP1CSR : byte absolute $00+$76; // 124 AMP2CSR : byte absolute $00+$77; // 125 // LINUART 126 LINCR : byte absolute $00+$C8; // LIN Control Register 127 LINSIR : byte absolute $00+$C9; // LIN Status and Interrupt Register 128 LINENIR : byte absolute $00+$CA; // LIN Enable Interrupt Register 129 LINERR : byte absolute $00+$CB; // LIN Error Register 130 LINBTR : byte absolute $00+$CC; // LIN Bit Timing Register 131 LINBRRL : byte absolute $00+$CD; // LIN Baud Rate Low Register 132 LINBRRH : byte absolute $00+$CE; // LIN Baud Rate High Register 133 LINDLR : byte absolute $00+$CF; // LIN Data Length Register 134 LINIDR : byte absolute $00+$D0; // LIN Identifier Register 135 LINSEL : byte absolute $00+$D1; // LIN Data Buffer Selection Register 136 LINDAT : byte absolute $00+$D2; // LIN Data Register 137 // SPI 138 SPCR : byte absolute $00+$4C; // SPI Control Register 139 SPSR : byte absolute $00+$4D; // SPI Status Register 140 SPDR : byte absolute $00+$4E; // SPI Data Register 141 // WATCHDOG 142 WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register 143 // EXTERNAL_INTERRUPT 144 EICRA : byte absolute $00+$69; // External Interrupt Control Register 145 EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register 146 EIFR : byte absolute $00+$3C; // External Interrupt Flag Register 147 PCICR : byte absolute $00+$68; // Pin Change Interrupt Control Register 148 PCMSK3 : byte absolute $00+$6D; // Pin Change Mask Register 3 149 PCMSK2 : byte absolute $00+$6C; // Pin Change Mask Register 2 150 PCMSK1 : byte absolute $00+$6B; // Pin Change Mask Register 1 151 PCMSK0 : byte absolute $00+$6A; // Pin Change Mask Register 0 152 PCIFR : byte absolute $00+$3B; // Pin Change Interrupt Flag Register 153 // EEPROM 154 EEAR : word absolute $00+$41; // EEPROM Read/Write Access 155 EEARL : byte absolute $00+$41; // EEPROM Read/Write Access 156 EEARH : byte absolute $00+$41+1; // EEPROM Read/Write Access 157 EEDR : byte absolute $00+$40; // EEPROM Data Register 158 EECR : byte absolute $00+$3F; // EEPROM Control Register 159 160const 161 // CANGCON 162 ABRQ = 7; // Abort Request 163 OVRQ = 6; // Overload Frame Request 164 TTC = 5; // Time Trigger Communication 165 SYNTTC = 4; // Synchronization of TTC 166 LISTEN = 3; // Listening Mode 167 TEST = 2; // Test Mode 168 ENASTB = 1; // Enable / Standby 169 SWRES = 0; // Software Reset Request 170 // CANGSTA 171 OVFG = 6; // Overload Frame Flag 172 TXBSY = 4; // Transmitter Busy 173 RXBSY = 3; // Receiver Busy 174 ENFG = 2; // Enable Flag 175 BOFF = 1; // Bus Off Mode 176 ERRP = 0; // Error Passive Mode 177 // CANGIT 178 CANIT = 7; // General Interrupt Flag 179 BOFFIT = 6; // Bus Off Interrupt Flag 180 OVRTIM = 5; // Overrun CAN Timer Flag 181 BXOK = 4; // Burst Receive Interrupt Flag 182 SERG = 3; // Stuff Error General Flag 183 CERG = 2; // CRC Error General Flag 184 FERG = 1; // Form Error General Flag 185 AERG = 0; // Ackknowledgement Error General Flag 186 // CANGIE 187 ENIT = 7; // Enable all Interrupts 188 ENBOFF = 6; // Enable Bus Off Interrupt 189 ENRX = 5; // Enable Receive Interrupt 190 ENTX = 4; // Enable Transmitt Interrupt 191 ENERR = 3; // Enable MOb Error Interrupt 192 ENBX = 2; // Enable Burst Receive Interrupt 193 ENERG = 1; // Enable General Error Interrupt 194 ENOVRT = 0; // Enable CAN Timer Overrun Interrupt 195 // CANEN2 196 ENMOB = 0; // Enable MObs 197 // CANIE2 198 IEMOB = 0; // Interrupt Enable MObs 199 // CANSIT2 200 SIT = 0; // Status of Interrupt MObs 201 // CANBT1 202 BRP = 1; // Baud Rate Prescaler bits 203 // CANBT2 204 SJW = 5; // Re-Sync Jump Width bits 205 PRS = 1; // Propagation Time Segment bits 206 // CANBT3 207 PHS2 = 4; // Phase Segment 2 bits 208 PHS1 = 1; // Phase Segment 1 bits 209 SMP = 0; // Sample Type 210 // CANHPMOB 211 HPMOB = 4; // Highest Priority MOb Number bits 212 CGP = 0; // CAN General Purpose bits 213 // CANPAGE 214 MOBNB = 4; // MOb Number bits 215 AINC = 3; // MOb Data Buffer Auto Increment (Active Low) 216 INDX = 0; // Data Buffer Index bits 217 // CANSTMOB 218 DLCW = 7; // Data Length Code Warning on MOb 219 TXOK = 6; // Transmit OK on MOb 220 RXOK = 5; // Receive OK on MOb 221 BERR = 4; // Bit Error on MOb 222 SERR = 3; // Stuff Error on MOb 223 CERR = 2; // CRC Error on MOb 224 FERR = 1; // Form Error on MOb 225 AERR = 0; // Ackknowledgement Error on MOb 226 // CANCDMOB 227 CONMOB = 6; // MOb Config bits 228 RPLV = 5; // Reply Valid 229 IDE = 4; // Identifier Extension 230 DLC = 0; // Data Length Code bits 231 // CANIDT4 232 IDT = 3; // 233 RTRTAG = 2; // 234 RB1TAG = 1; // 235 RB0TAG = 0; // 236 // AC0CON 237 AC0EN = 7; // Analog Comparator 0 Enable Bit 238 AC0IE = 6; // Analog Comparator 0 Interrupt Enable Bit 239 AC0IS = 4; // Analog Comparator 0 Interrupt Select Bits 240 ACCKSEL = 3; // Analog Comparator Clock Select 241 AC0M = 0; // Analog Comparator 0 Multiplexer Register 242 // AC1CON 243 AC1EN = 7; // Analog Comparator 1 Enable Bit 244 AC1IE = 6; // Analog Comparator 1 Interrupt Enable Bit 245 AC1IS = 4; // Analog Comparator 1 Interrupt Select Bit 246 AC1ICE = 3; // Analog Comparator 1 Interrupt Capture Enable Bit 247 AC1M = 0; // Analog Comparator 1 Multiplexer Register 248 // AC2CON 249 AC2EN = 7; // Analog Comparator 2 Enable Bit 250 AC2IE = 6; // Analog Comparator 2 Interrupt Enable Bit 251 AC2IS = 4; // Analog Comparator 2 Interrupt Select Bit 252 AC2M = 0; // Analog Comparator 2 Multiplexer Register 253 // AC3CON 254 AC3EN = 7; // Analog Comparator 3 Enable Bit 255 AC3IE = 6; // Analog Comparator 3 Interrupt Enable Bit 256 AC3IS = 4; // Analog Comparator 3 Interrupt Select Bit 257 AC3M = 0; // Analog Comparator 3 Multiplexer Register 258 // ACSR 259 AC3IF = 7; // Analog Comparator 3 Interrupt Flag Bit 260 AC2IF = 6; // Analog Comparator 2 Interrupt Flag Bit 261 AC1IF = 5; // Analog Comparator 1 Interrupt Flag Bit 262 AC0IF = 4; // Analog Comparator 0 Interrupt Flag Bit 263 AC3O = 3; // Analog Comparator 3 Output Bit 264 AC2O = 2; // Analog Comparator 2 Output Bit 265 AC1O = 1; // Analog Comparator 1 Output Bit 266 AC0O = 0; // Analog Comparator 0 Output Bit 267 // DACH 268 // DACL 269 // DACON 270 DAATE = 7; // DAC Auto Trigger Enable Bit 271 DATS = 4; // DAC Trigger Selection Bits 272 DALA = 2; // DAC Left Adjust 273 DAEN = 0; // DAC Enable Bit 274 // SPMCSR 275 SPMIE = 7; // SPM Interrupt Enable 276 RWWSB = 6; // Read While Write Section Busy 277 SIGRD = 5; // Signature Row Read 278 RWWSRE = 4; // Read While Write section read enable 279 BLBSET = 3; // Boot Lock Bit Set 280 PGWRT = 2; // Page Write 281 PGERS = 1; // Page Erase 282 SPMEN = 0; // Store Program Memory Enable 283 // SREG 284 I = 7; // Global Interrupt Enable 285 T = 6; // Bit Copy Storage 286 H = 5; // Half Carry Flag 287 S = 4; // Sign Bit 288 V = 3; // Two's Complement Overflow Flag 289 N = 2; // Negative Flag 290 Z = 1; // Zero Flag 291 C = 0; // Carry Flag 292 // MCUCR 293 SPIPS = 7; // SPI Pin Select 294 PUD = 4; // Pull-up disable 295 IVSEL = 1; // Interrupt Vector Select 296 IVCE = 0; // Interrupt Vector Change Enable 297 // MCUSR 298 WDRF = 3; // Watchdog Reset Flag 299 BORF = 2; // Brown-out Reset Flag 300 EXTRF = 1; // External Reset Flag 301 PORF = 0; // Power-on reset flag 302 // CLKPR 303 CLKPCE = 7; // 304 CLKPS = 0; // 305 // SMCR 306 SM = 1; // Sleep Mode Select bits 307 SE = 0; // Sleep Enable 308 // GPIOR2 309 GPIOR = 0; // General Purpose IO Register 2 bis 310 // GPIOR1 311 // GPIOR0 312 GPIOR07 = 7; // General Purpose IO Register 0 bit 7 313 GPIOR06 = 6; // General Purpose IO Register 0 bit 6 314 GPIOR05 = 5; // General Purpose IO Register 0 bit 5 315 GPIOR04 = 4; // General Purpose IO Register 0 bit 4 316 GPIOR03 = 3; // General Purpose IO Register 0 bit 3 317 GPIOR02 = 2; // General Purpose IO Register 0 bit 2 318 GPIOR01 = 1; // General Purpose IO Register 0 bit 1 319 GPIOR00 = 0; // General Purpose IO Register 0 bit 0 320 // PLLCSR 321 PLLF = 2; // PLL Factor 322 PLLE = 1; // PLL Enable 323 PLOCK = 0; // PLL Lock Detector 324 // PRR 325 PRCAN = 6; // Power Reduction CAN 326 PRPSC = 5; // Power Reduction PSC 327 PRTIM1 = 4; // Power Reduction Timer/Counter1 328 PRTIM0 = 3; // Power Reduction Timer/Counter0 329 PRSPI = 2; // Power Reduction Serial Peripheral Interface 330 PRLIN = 1; // Power Reduction LIN UART 331 PRADC = 0; // Power Reduction ADC 332 // TIMSK0 333 OCIE0B = 2; // Timer/Counter0 Output Compare Match B Interrupt Enable 334 OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable 335 TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable 336 // TIFR0 337 OCF0B = 2; // Timer/Counter0 Output Compare Flag 0B 338 OCF0A = 1; // Timer/Counter0 Output Compare Flag 0A 339 TOV0 = 0; // Timer/Counter0 Overflow Flag 340 // TCCR0A 341 COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode 342 COM0B = 4; // Compare Output Mode, Fast PWm 343 WGM0 = 0; // Waveform Generation Mode 344 // TCCR0B 345 FOC0A = 7; // Force Output Compare A 346 FOC0B = 6; // Force Output Compare B 347 WGM02 = 3; // 348 CS0 = 0; // Clock Select 349 // GTCCR 350 TSM = 7; // Timer/Counter Synchronization Mode 351 ICPSEL1 = 6; // Timer1 Input Capture Selection Bit 352 PSR10 = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0 353 // TIMSK1 354 ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable 355 OCIE1B = 2; // Timer/Counter1 Output CompareB Match Interrupt Enable 356 OCIE1A = 1; // Timer/Counter1 Output CompareA Match Interrupt Enable 357 TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable 358 // TIFR1 359 ICF1 = 5; // Input Capture Flag 1 360 OCF1B = 2; // Output Compare Flag 1B 361 OCF1A = 1; // Output Compare Flag 1A 362 TOV1 = 0; // Timer/Counter1 Overflow Flag 363 // TCCR1A 364 COM1A = 6; // Compare Output Mode 1A, bits 365 COM1B = 4; // Compare Output Mode 1B, bits 366 WGM1 = 0; // Waveform Generation Mode 367 // TCCR1B 368 ICNC1 = 7; // Input Capture 1 Noise Canceler 369 ICES1 = 6; // Input Capture 1 Edge Select 370 CS1 = 0; // Prescaler source of Timer/Counter 1 371 // TCCR1C 372 FOC1A = 7; // 373 FOC1B = 6; // 374 // GTCCR 375 PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0 376 // ADMUX 377 REFS = 6; // Reference Selection Bits 378 ADLAR = 5; // Left Adjust Result 379 MUX = 0; // Analog Channel and Gain Selection Bits 380 // ADCSRA 381 ADEN = 7; // ADC Enable 382 ADSC = 6; // ADC Start Conversion 383 ADATE = 5; // ADC Auto Trigger Enable 384 ADIF = 4; // ADC Interrupt Flag 385 ADIE = 3; // ADC Interrupt Enable 386 ADPS = 0; // ADC Prescaler Select Bits 387 // ADCSRB 388 ADHSM = 7; // ADC High Speed Mode 389 ISRCEN = 6; // Current Source Enable 390 AREFEN = 5; // Analog Reference pin Enable 391 ADTS = 0; // ADC Auto Trigger Sources 392 // DIDR0 393 ADC7D = 7; // ADC7 Digital input Disable 394 ADC6D = 6; // ADC6 Digital input Disable 395 ADC5D = 5; // ADC5 Digital input Disable 396 ADC4D = 4; // ADC4 Digital input Disable 397 ADC3D = 3; // ADC3 Digital input Disable 398 ADC2D = 2; // ADC2 Digital input Disable 399 ADC1D = 1; // ADC1 Digital input Disable 400 ADC0D = 0; // ADC0 Digital input Disable 401 // DIDR1 402 AMP2PD = 6; // AMP2P Pin Digital input Disable 403 ACMP0D = 5; // ACMP0 Pin Digital input Disable 404 AMP0PD = 4; // AMP0P Pin Digital input Disable 405 AMP0ND = 3; // AMP0N Pin Digital input Disable 406 ADC10D = 2; // ADC10 Pin Digital input Disable 407 ADC9D = 1; // ADC9 Pin Digital input Disable 408 ADC8D = 0; // ADC8 Pin Digital input Disable 409 // AMP0CSR 410 AMP0EN = 7; // 411 AMP0IS = 6; // 412 AMP0G = 4; // 413 AMPCMP0 = 3; // Amplifier 0 - Comparator 0 Connection 414 AMP0TS = 0; // 415 // AMP1CSR 416 AMP1EN = 7; // 417 AMP1IS = 6; // 418 AMP1G = 4; // 419 AMPCMP1 = 3; // Amplifier 1 - Comparator 1 Connection 420 AMP1TS = 0; // 421 // AMP2CSR 422 AMP2EN = 7; // 423 AMP2IS = 6; // 424 AMP2G = 4; // 425 AMPCMP2 = 3; // Amplifier 2 - Comparator 2 Connection 426 AMP2TS = 0; // 427 // LINCR 428 LSWRES = 7; // Software Reset 429 LIN13 = 6; // LIN Standard 430 LCONF = 4; // LIN Configuration bits 431 LENA = 3; // LIN or UART Enable 432 LCMD = 0; // LIN Command and Mode bits 433 // LINSIR 434 LIDST = 5; // Identifier Status bits 435 LBUSY = 4; // Busy Signal 436 LERR = 3; // Error Interrupt 437 LIDOK = 2; // Identifier Interrupt 438 LTXOK = 1; // Transmit Performed Interrupt 439 LRXOK = 0; // Receive Performed Interrupt 440 // LINENIR 441 LENERR = 3; // Enable Error Interrupt 442 LENIDOK = 2; // Enable Identifier Interrupt 443 LENTXOK = 1; // Enable Transmit Performed Interrupt 444 LENRXOK = 0; // Enable Receive Performed Interrupt 445 // LINERR 446 LABORT = 7; // Abort Flag 447 LTOERR = 6; // Frame Time Out Error Flag 448 LOVERR = 5; // Overrun Error Flag 449 LFERR = 4; // Framing Error Flag 450 LSERR = 3; // Synchronization Error Flag 451 LPERR = 2; // Parity Error Flag 452 LCERR = 1; // Checksum Error Flag 453 LBERR = 0; // Bit Error Flag 454 // LINBTR 455 LDISR = 7; // Disable Bit Timing Resynchronization 456 LBT = 0; // LIN Bit Timing bits 457 // LINBRRL 458 LDIV = 0; // 459 // LINBRRH 460 // LINDLR 461 LTXDL = 4; // LIN Transmit Data Length bits 462 LRXDL = 0; // LIN Receive Data Length bits 463 // LINIDR 464 LP = 6; // Parity bits 465 LID = 0; // Identifier bit 5 or Data Length bits 466 // LINSEL 467 LAINC = 3; // Auto Increment of Data Buffer Index (Active Low) 468 LINDX = 0; // FIFO LIN Data Buffer Index bits 469 // LINDAT 470 LDATA = 0; // 471 // SPCR 472 SPIE = 7; // SPI Interrupt Enable 473 SPE = 6; // SPI Enable 474 DORD = 5; // Data Order 475 MSTR = 4; // Master/Slave Select 476 CPOL = 3; // Clock polarity 477 CPHA = 2; // Clock Phase 478 SPR = 0; // SPI Clock Rate Selects 479 // SPSR 480 SPIF = 7; // SPI Interrupt Flag 481 WCOL = 6; // Write Collision Flag 482 SPI2X = 0; // Double SPI Speed Bit 483 // WDTCSR 484 WDIF = 7; // Watchdog Timeout Interrupt Flag 485 WDIE = 6; // Watchdog Timeout Interrupt Enable 486 WDP = 0; // Watchdog Timer Prescaler Bits 487 WDCE = 4; // Watchdog Change Enable 488 WDE = 3; // Watch Dog Enable 489 // EICRA 490 ISC3 = 6; // External Interrupt Sense Control Bit 491 ISC2 = 4; // External Interrupt Sense Control Bit 492 ISC1 = 2; // External Interrupt Sense Control 1 Bits 493 ISC0 = 0; // External Interrupt Sense Control 0 Bits 494 // EIMSK 495 INT = 0; // External Interrupt Request 3 Enable 496 // EIFR 497 INTF = 0; // External Interrupt Flags 498 // PCICR 499 PCIE = 0; // Pin Change Interrupt Enables 500 // PCMSK3 501 PCINT = 0; // Pin Change Enable Masks 502 // PCMSK2 503 // PCMSK1 504 // PCMSK0 505 // PCIFR 506 PCIF = 0; // Pin Change Interrupt Flags 507 // EECR 508 EEPM = 4; // 509 EERIE = 3; // EEProm Ready Interrupt Enable 510 EEMWE = 2; // EEPROM Master Write Enable 511 EEWE = 1; // EEPROM Write Enable 512 EERE = 0; // EEPROM Read Enable 513 514implementation 515 516{$i avrcommon.inc} 517 518procedure ANACOMP0_ISR; external name 'ANACOMP0_ISR'; // Interrupt 1 Analog Comparator 0 519procedure ANACOMP1_ISR; external name 'ANACOMP1_ISR'; // Interrupt 2 Analog Comparator 1 520procedure ANACOMP2_ISR; external name 'ANACOMP2_ISR'; // Interrupt 3 Analog Comparator 2 521procedure ANACOMP3_ISR; external name 'ANACOMP3_ISR'; // Interrupt 4 Analog Comparator 3 522procedure PSC_FAULT_ISR; external name 'PSC_FAULT_ISR'; // Interrupt 5 PSC Fault 523procedure PSC_EC_ISR; external name 'PSC_EC_ISR'; // Interrupt 6 PSC End of Cycle 524procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 7 External Interrupt Request 0 525procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 8 External Interrupt Request 1 526procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 9 External Interrupt Request 2 527procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 10 External Interrupt Request 3 528procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event 529procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A 530procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter1 Compare Match B 531procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 14 Timer1/Counter1 Overflow 532procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 15 Timer/Counter0 Compare Match A 533procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 16 Timer/Counter0 Compare Match B 534procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow 535procedure CAN_INT_ISR; external name 'CAN_INT_ISR'; // Interrupt 18 CAN MOB, Burst, General Errors 536procedure CAN_TOVF_ISR; external name 'CAN_TOVF_ISR'; // Interrupt 19 CAN Timer Overflow 537procedure LIN_TC_ISR; external name 'LIN_TC_ISR'; // Interrupt 20 LIN Transfer Complete 538procedure LIN_ERR_ISR; external name 'LIN_ERR_ISR'; // Interrupt 21 LIN Error 539procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 22 Pin Change Interrupt Request 0 540procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 23 Pin Change Interrupt Request 1 541procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 24 Pin Change Interrupt Request 2 542procedure PCINT3_ISR; external name 'PCINT3_ISR'; // Interrupt 25 Pin Change Interrupt Request 3 543procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 26 SPI Serial Transfer Complete 544procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 27 ADC Conversion Complete 545procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 28 Watchdog Time-Out Interrupt 546procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 29 EEPROM Ready 547procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 30 Store Program Memory Read 548 549procedure _FPC_start; assembler; nostackframe; 550label 551 _start; 552 asm 553 .init 554 .globl _start 555 556 jmp _start 557 jmp ANACOMP0_ISR 558 jmp ANACOMP1_ISR 559 jmp ANACOMP2_ISR 560 jmp ANACOMP3_ISR 561 jmp PSC_FAULT_ISR 562 jmp PSC_EC_ISR 563 jmp INT0_ISR 564 jmp INT1_ISR 565 jmp INT2_ISR 566 jmp INT3_ISR 567 jmp TIMER1_CAPT_ISR 568 jmp TIMER1_COMPA_ISR 569 jmp TIMER1_COMPB_ISR 570 jmp TIMER1_OVF_ISR 571 jmp TIMER0_COMPA_ISR 572 jmp TIMER0_COMPB_ISR 573 jmp TIMER0_OVF_ISR 574 jmp CAN_INT_ISR 575 jmp CAN_TOVF_ISR 576 jmp LIN_TC_ISR 577 jmp LIN_ERR_ISR 578 jmp PCINT0_ISR 579 jmp PCINT1_ISR 580 jmp PCINT2_ISR 581 jmp PCINT3_ISR 582 jmp SPI__STC_ISR 583 jmp ADC_ISR 584 jmp WDT_ISR 585 jmp EE_READY_ISR 586 jmp SPM_READY_ISR 587 588 {$i start.inc} 589 590 .weak ANACOMP0_ISR 591 .weak ANACOMP1_ISR 592 .weak ANACOMP2_ISR 593 .weak ANACOMP3_ISR 594 .weak PSC_FAULT_ISR 595 .weak PSC_EC_ISR 596 .weak INT0_ISR 597 .weak INT1_ISR 598 .weak INT2_ISR 599 .weak INT3_ISR 600 .weak TIMER1_CAPT_ISR 601 .weak TIMER1_COMPA_ISR 602 .weak TIMER1_COMPB_ISR 603 .weak TIMER1_OVF_ISR 604 .weak TIMER0_COMPA_ISR 605 .weak TIMER0_COMPB_ISR 606 .weak TIMER0_OVF_ISR 607 .weak CAN_INT_ISR 608 .weak CAN_TOVF_ISR 609 .weak LIN_TC_ISR 610 .weak LIN_ERR_ISR 611 .weak PCINT0_ISR 612 .weak PCINT1_ISR 613 .weak PCINT2_ISR 614 .weak PCINT3_ISR 615 .weak SPI__STC_ISR 616 .weak ADC_ISR 617 .weak WDT_ISR 618 .weak EE_READY_ISR 619 .weak SPM_READY_ISR 620 621 .set ANACOMP0_ISR, Default_IRQ_handler 622 .set ANACOMP1_ISR, Default_IRQ_handler 623 .set ANACOMP2_ISR, Default_IRQ_handler 624 .set ANACOMP3_ISR, Default_IRQ_handler 625 .set PSC_FAULT_ISR, Default_IRQ_handler 626 .set PSC_EC_ISR, Default_IRQ_handler 627 .set INT0_ISR, Default_IRQ_handler 628 .set INT1_ISR, Default_IRQ_handler 629 .set INT2_ISR, Default_IRQ_handler 630 .set INT3_ISR, Default_IRQ_handler 631 .set TIMER1_CAPT_ISR, Default_IRQ_handler 632 .set TIMER1_COMPA_ISR, Default_IRQ_handler 633 .set TIMER1_COMPB_ISR, Default_IRQ_handler 634 .set TIMER1_OVF_ISR, Default_IRQ_handler 635 .set TIMER0_COMPA_ISR, Default_IRQ_handler 636 .set TIMER0_COMPB_ISR, Default_IRQ_handler 637 .set TIMER0_OVF_ISR, Default_IRQ_handler 638 .set CAN_INT_ISR, Default_IRQ_handler 639 .set CAN_TOVF_ISR, Default_IRQ_handler 640 .set LIN_TC_ISR, Default_IRQ_handler 641 .set LIN_ERR_ISR, Default_IRQ_handler 642 .set PCINT0_ISR, Default_IRQ_handler 643 .set PCINT1_ISR, Default_IRQ_handler 644 .set PCINT2_ISR, Default_IRQ_handler 645 .set PCINT3_ISR, Default_IRQ_handler 646 .set SPI__STC_ISR, Default_IRQ_handler 647 .set ADC_ISR, Default_IRQ_handler 648 .set WDT_ISR, Default_IRQ_handler 649 .set EE_READY_ISR, Default_IRQ_handler 650 .set SPM_READY_ISR, Default_IRQ_handler 651 end; 652 653end. 654