1unit lpc8xx; 2{$goto on} 3{$define lpc8xx} 4 5interface 6{$PACKRECORDS 2} 7 8const 9 //------------------------- Cortex-M0 Processor Exceptions Numbers ------------------------- 10 Reset_IRQn = -15; // 1 Reset Vector, invoked on Power up and warm reset 11 NonMaskableInt_IRQn = -14; // 2 Non Maskable Interrupt 12 HardFault_IRQn = -13; // 3 Cortex-M0 Hard Fault Interrupt 13 SVCall_IRQn = -5; // 11 Cortex-M0 SV Call Interrupt 14 PendSV_IRQn = -2; // 14 Cortex-M0 Pend SV Interrupt 15 SysTick_IRQn = -1; // 15 Cortex-M0 System Tick Interrupt 16 17 //------------------------- LPC8xx Specific Interrupt Numbers ------------------------- 18 SPI0_IRQn = 0; // SPI0 19 SPI1_IRQn = 1; // SPI1 20 UART0_IRQn = 3; // USART0 21 UART1_IRQn = 4; // USART1 22 UART2_IRQn = 5; // USART2 23 I2C_IRQn = 8; // I2C 24 SCT_IRQn = 9; // SCT 25 MRT_IRQn = 10; // MRT 26 CMP_IRQn = 11; // CMP 27 WDT_IRQn = 12; // WDT 28 BOD_IRQn = 13; // BOD 29 WKT_IRQn = 15; // WKT Interrupt 30 PININT0_IRQn = 24; // External Interrupt 0 31 PININT1_IRQn = 25; // External Interrupt 1 32 PININT2_IRQn = 26; // External Interrupt 2 33 PININT3_IRQn = 27; // External Interrupt 3 34 PININT4_IRQn = 28; // External Interrupt 4 35 PININT5_IRQn = 29; // External Interrupt 5 36 PININT6_IRQn = 30; // External Interrupt 6 37 PININT7_IRQn = 31; // External Interrupt 7 38 39type 40 { ------------- System Control (SYSCON) ------------- } 41 TSYSCON_Registers = record 42 SYSMEMREMAP : longword; 43 PRESETCTRL : longword; 44 SYSPLLCTRL : longword; 45 SYSPLLSTAT : longword; 46 RESERVED0 : array [0 .. 3] of longword; 47 SYSOSCCTRL : longword; 48 WDTOSCCTRL : longword; 49 RESERVED1 : array [0 .. 1] of longword; 50 SYSRSTSTAT : longword; 51 RESERVED2 : array [0 .. 2] of longword; 52 SYSPLLCLKSEL : longword; 53 SYSPLLCLKUEN : longword; 54 RESERVED3 : array [0 .. 9] of longword; 55 MAINCLKSEL : longword; 56 MAINCLKUEN : longword; 57 SYSAHBCLKDIV : longword; 58 RESERVED4 : longword; 59 SYSAHBCLKCTRL: longword; 60 RESERVED5 : array [0 .. 3] of longword; 61 UARTCLKDIV : longword; 62 RESERVED6 : array [0 .. 17] of longword; 63 CLKOUTSEL : longword; 64 CLKOUTUEN : longword; 65 CLKOUTDIV : longword; 66 RESERVED7 : longword; 67 UARTFRGDIV : longword; 68 UARTFRGMULT : longword; 69 RESERVED8 : longword; 70 EXTTRACECMD : longword; 71 PIOPORCAP0 : longword; 72 RESERVED9 : array [0 .. 11] of longword; 73 IOCONCLKDIV : array [0 .. 6] of longword; 74 BODCTRL : longword; 75 SYSTCKCAL : longword; 76 RESERVED10 : array [0 .. 5] of longword; 77 IRQLATENCY : longword; 78 NMISRC : longword; 79 PINTSEL : array [0 .. 7] of longword; 80 RESERVED11 : array [0 .. 26] of longword; 81 STARTERP0 : longword; 82 RESERVED12 : array [0 .. 2] of longword; 83 STARTERP1 : longword; 84 RESERVED13 : array [0 .. 5] of longword; 85 PDSLEEPCFG : longword; 86 PDAWAKECFG : longword; 87 PDRUNCFG : longword; 88 RESERVED14 : array [0 .. 109] of longword; 89 DEVICE_ID : longword; 90 end; 91 92 { ------------- Pin Connect Block (IOCON) ------------- } 93 TIOCON_Registers = record 94 PIO0_17 : longword; 95 PIO0_13 : longword; 96 PIO0_12 : longword; 97 PIO0_5 : longword; 98 PIO0_4 : longword; 99 PIO0_3 : longword; 100 PIO0_2 : longword; 101 PIO0_11 : longword; 102 PIO0_10 : longword; 103 PIO0_16 : longword; 104 PIO0_15 : longword; 105 PIO0_1 : longword; 106 RESERVED0: longword; 107 PIO0_9 : longword; 108 PIO0_8 : longword; 109 PIO0_7 : longword; 110 PIO0_6 : longword; 111 PIO0_0 : longword; 112 PIO0_14 : longword; 113 end; 114 115 { ------------- Flash Controller (FLASHCTRL) ------------- } 116 TFLASHCTRL_Registers = record 117 RESERVED0: array [0 .. 3] of longword; 118 FLASHCFG : longword; 119 RESERVED1: array [0 .. 2] of longword; 120 FMSSTART : longword; 121 FMSSTOP : longword; 122 RESERVED2: longword; 123 FMSW0 : longword; 124 end; 125 126 { ------------- Power Management Unit (PMU) ------------- } 127 TPMU_Registers = record 128 PCON : longword; 129 GPREG0 : longword; 130 GPREG1 : longword; 131 GPREG2 : longword; 132 GPREG3 : longword; 133 DPDCTRL: longword; 134 end; 135 136 { ------------- Switch Matrix Register (SWM) ------------- } 137 TSWM_Registers = record 138 PINASSIGN : array [0 .. 8] of longword; 139 RESERVED0 : array [0 .. 102] of longword; 140 PINENABLE0: longword; 141 end; 142 143 { ------------- General Purpose Input/Output (GPIO) ------------- } 144 TGPIOPORT_Registers = record 145 B0 : array [0 .. 17] of byte; 146 RESERVED0: array [0 .. 2038] of word; 147 W0 : array [0 .. 17] of longword; 148 RESERVED1: array [0 .. 1005] of longword; 149 DIR0 : longword; 150 RESERVED2: array [0 .. 30] of longword; 151 MASK0 : longword; 152 RESERVED3: array [0 .. 30] of longword; 153 PIN0 : longword; 154 RESERVED4: array [0 .. 30] of longword; 155 MPIN0 : longword; 156 RESERVED5: array [0 .. 30] of longword; 157 SET0 : longword; 158 RESERVED6: array [0 .. 30] of longword; 159 CLR0 : longword; 160 RESERVED7: array [0 .. 30] of longword; 161 NOT0 : longword; 162 end; 163 164 { ------------- Pin interrupts/pattern match engine (PIN_INT) ------------- } 165 TPININT_Registers = record 166 ISEL : longword; 167 IENR : longword; 168 SIENR : longword; 169 CIENR : longword; 170 IENF : longword; 171 SIENF : longword; 172 CIENF : longword; 173 RISE : longword; 174 FALL : longword; 175 IST : longword; 176 PMCTRL: longword; 177 PMSRC : longword; 178 PMCFG : longword; 179 end; 180 181 { ------------- CRC Engine (CRC) ------------- } 182 TCRC_Registers = record 183 MODE: longword; 184 SEED: longword; 185 SUM : longword; 186 end; 187 188 { ------------- Comparator (CMP) ------------- } 189 TCMP_Registers = record 190 CTRL: longword; 191 LAD : longword; 192 end; 193 194 { ------------- Wakeup Timer (WKT) ------------- } 195 TWKT_Registers = record 196 CTRL : longword; 197 RESERVED0: array [0 .. 1] of longword; 198 COUNT : longword; 199 end; 200 201 { ------------- Multi-Rate Timer(MRT) ------------- } 202 TMRTChannel = record 203 INTVAL: longword; 204 TIMER : longword; 205 CTRL : longword; 206 STAT : longword; 207 end; 208 209 TMRT_Registers = record 210 CHANNEL : array [0 .. 3] of TMRTChannel; 211 RESERVED0: array [0 .. 0] of longword; 212 IDLE_CH : longword; 213 IRQ_FLAG : longword; 214 end; 215 216 { ------------- Universal Asynchronous Receiver Transmitter (USART) ------------- } 217 TUSART_Registers = record 218 CFG : longword; 219 CTRL : longword; 220 STAT : longword; 221 INTENSET : longword; 222 INTENCLR : longword; 223 RXDATA : longword; 224 RXDATA_STAT: longword; 225 TXDATA : longword; 226 BRG : longword; 227 INTSTAT : longword; 228 end; 229 230 { ------------- Synchronous Serial Interface Controller (SPI) ------------- } 231 TSPI_Registers = record 232 CFG : longword; 233 DLY : longword; 234 STAT : longword; 235 INTENSET: longword; 236 INTENCLR: longword; 237 RXDAT : longword; 238 TXDATCTL: longword; 239 TXDAT : longword; 240 TXCTRL : longword; 241 _DIV : longword; 242 INTSTAT : longword; 243 end; 244 245 { ------------- Inter-Integrated Circuit (I2C) ------------- } 246 TI2C_Registers = record 247 CFG : longword; 248 STAT : longword; 249 INTENSET : longword; 250 INTENCLR : longword; 251 TIMEOUT : longword; 252 _DIV : longword; 253 INTSTAT : longword; 254 RESERVED0: longword; 255 MSTCTL : longword; 256 MSTTIME : longword; 257 MSTDAT : longword; 258 RESERVED1: array [0 .. 4] of longword; 259 SLVCTL : longword; 260 SLVDAT : longword; 261 SLVADR0 : longword; 262 SLVADR1 : longword; 263 SLVADR2 : longword; 264 SLVADR3 : longword; 265 SLVQUAL0 : longword; 266 RESERVED2: array [0 .. 8] of longword; 267 MONRXDAT : longword; 268 end; 269 270 { ------------- State Configurable Timer (SCT) ------------- } 271const 272 CONFIG_SCT_nEV = 6; 273 { Number of match/compare registers } 274 CONFIG_SCT_nRG = 5; 275 { Number of outputs } 276 CONFIG_SCT_nOU = 4; 277 278type 279 TSCTState = record 280 STATE : longword; 281 CTRL : longword; 282 end; 283 TSCTSet = record 284 _SET : longword; 285 CLR : longword; 286 end; 287 288type 289 TSCT_Registers = record 290 CONFIG : longword; 291 CTRL : longword; 292 LIMIT : longword; 293 HALT : longword; 294 STOP : longword; 295 START : longword; 296 RESERVED1 : array [0 .. 9] of longword; 297 COUNT : longword; 298 STATE : longword; 299 INPUT : longword; 300 REGMODE : longword; 301 OUTPUT : longword; 302 OUTPUTDIRCTRL : longword; 303 RES : longword; 304 RESERVED2 : array [0 .. 36] of longword; 305 EVEN : longword; 306 EVFLAG : longword; 307 CONEN : longword; 308 CONFLAG : longword; 309 MATCH_CAP : array [0 .. (CONFIG_SCT_nRG) - 1] of longword; 310 RESERVED3 : array [0 .. (32 - CONFIG_SCT_nRG) - 1] of longword; 311 MATCHREL_CAPCTRL: array [0 .. (CONFIG_SCT_nRG) - 1] of longword; 312 RESERVED6 : array [0 .. (32 - CONFIG_SCT_nRG) - 1] of longword; 313 EVENT : array [0 .. (CONFIG_SCT_nEV) - 1] of TSCTState; 314 RESERVED9 : array [0 .. (128 - (2 * CONFIG_SCT_nEV)) - 1] of longword; 315 _OUT : array [0 .. (CONFIG_SCT_nOU) - 1] of TSCTSet; 316 end; 317 318 { ------------- Watchdog Timer (WDT) ------------- } 319 TWDT_Registers = record 320 _MOD : longword; 321 TC : longword; 322 FEED : longword; 323 TV : longword; 324 RESERVED0: longword; 325 WARNINT : longword; 326 WINDOW : longword; 327 end; 328 329{ **************************************************************************** } 330{ Peripheral memory map } 331{ **************************************************************************** } 332 333const 334 { Base addresses } 335 LPC_FLASH_BASE = $00000000; 336 LPC_RAM_BASE = $10000000; 337 LPC_ROM_BASE = $1FFF0000; 338 LPC_APB0_BASE = $40000000; 339 LPC_AHB_BASE = $50000000; 340 { APB0 peripherals } 341 LPC_WDT_BASE = LPC_APB0_BASE + $00000; 342 LPC_MRT_BASE = LPC_APB0_BASE + $04000; 343 LPC_WKT_BASE = LPC_APB0_BASE + $08000; 344 LPC_SWM_BASE = LPC_APB0_BASE + $0C000; 345 LPC_PMU_BASE = LPC_APB0_BASE + $20000; 346 LPC_CMP_BASE = LPC_APB0_BASE + $24000; 347 LPC_FLASHCTRL_BASE = LPC_APB0_BASE + $40000; 348 LPC_IOCON_BASE = LPC_APB0_BASE + $44000; 349 LPC_SYSCON_BASE = LPC_APB0_BASE + $48000; 350 LPC_I2C_BASE = LPC_APB0_BASE + $50000; 351 LPC_SPI0_BASE = LPC_APB0_BASE + $58000; 352 LPC_SPI1_BASE = LPC_APB0_BASE + $5C000; 353 LPC_USART0_BASE = LPC_APB0_BASE + $64000; 354 LPC_USART1_BASE = LPC_APB0_BASE + $68000; 355 LPC_USART2_BASE = LPC_APB0_BASE + $6C000; 356 { AHB peripherals } 357 LPC_CRC_BASE = LPC_AHB_BASE + $00000; 358 LPC_SCT_BASE = LPC_AHB_BASE + $04000; 359 LPC_GPIO_PORT_BASE = $A0000000; 360 LPC_PIN_INT_BASE = LPC_GPIO_PORT_BASE + $4000; 361 362// **************************************************************************** 363// Peripheral declaration 364// **************************************************************************** 365{$ALIGN 2} 366 367var 368 WDT : TWDT_Registers absolute LPC_WDT_BASE; 369 MRT : TMRT_Registers absolute LPC_MRT_BASE; 370 WKT : TWKT_Registers absolute LPC_WKT_BASE; 371 SWM : TSWM_Registers absolute LPC_SWM_BASE; 372 PMU : TPMU_Registers absolute LPC_PMU_BASE; 373 CMP : TCMP_Registers absolute LPC_CMP_BASE; 374 FLASHCTRL: TFLASHCTRL_Registers absolute LPC_FLASHCTRL_BASE; 375 IOCON : TIOCON_Registers absolute LPC_IOCON_BASE; 376 SYSCON : TSysCon_Registers absolute LPC_SYSCON_BASE; 377 I2C : TI2C_Registers absolute LPC_I2C_BASE; 378 SPI0 : TSPI_Registers absolute LPC_SPI0_BASE; 379 SPI1 : TSPI_Registers absolute LPC_SPI1_BASE; 380 USART0 : TUSART_Registers absolute LPC_USART0_BASE; 381 USART1 : TUSART_Registers absolute LPC_USART0_BASE; 382 USART2 : TUSART_Registers absolute LPC_USART0_BASE; 383 CRC : TCRC_Registers absolute LPC_CRC_BASE; 384 SCT : TSCT_Registers absolute LPC_SCT_BASE; 385 GPIO_PORT: TGPIOPort_Registers absolute LPC_GPIO_PORT_BASE; 386 PIN_INT : TPININT_Registers absolute LPC_PIN_INT_BASE; 387 388implementation 389 390procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt'; 391procedure Hardfault_interrupt; external name 'Hardfault_interrupt'; 392procedure Startup_Checksum; external name 'Startup_Checksum'; 393procedure SVCall_interrupt; external name 'SVCall_interrupt'; 394procedure PendSV_interrupt; external name 'PendSV_interrupt'; 395procedure SysTick_interrupt; external name 'SysTick_interrupt'; 396 397procedure SPI0_Interrupt; external name 'SPI0_Interrupt'; 398procedure SPI1_Interrupt; external name 'SPI1_Interrupt'; 399procedure UART0_Interrupt; external name 'UART0_Interrupt'; 400procedure UART1_Interrupt; external name 'UART1_Interrupt'; 401procedure UART2_Interrupt; external name 'UART2_Interrupt'; 402procedure I2C_Interrupt; external name 'I2C_Interrupt'; 403procedure SCT_Interrupt; external name 'SCT_Interrupt'; 404procedure MRT_Interrupt; external name 'MRT_Interrupt'; 405procedure CMP_Interrupt; external name 'CMP_Interrupt'; 406procedure WDT_Interrupt; external name 'WDT_Interrupt'; 407procedure BOD_Interrupt; external name 'BOD_Interrupt'; 408procedure WKT_Interrupt; external name 'WKT_Interrupt'; 409procedure PINIT0_Interrupt; external name 'PINIT0_Interrupt'; 410procedure PINIT1_Interrupt; external name 'PINIT1_Interrupt'; 411procedure PINIT2_Interrupt; external name 'PINIT2_Interrupt'; 412procedure PINIT3_Interrupt; external name 'PINIT3_Interrupt'; 413procedure PINIT4_Interrupt; external name 'PINIT4_Interrupt'; 414procedure PINIT5_Interrupt; external name 'PINIT5_Interrupt'; 415procedure PINIT6_Interrupt; external name 'PINIT6_Interrupt'; 416procedure PINIT7_Interrupt; external name 'PINIT7_Interrupt'; 417 418{$I cortexm0_start.inc} 419 420procedure Vectors; assembler; 421nostackframe; 422label interrupt_vectors; 423asm 424 .section ".init.interrupt_vectors" 425 interrupt_vectors: 426 .long _stack_top 427 .long Startup 428 .long NonMaskableInt_interrupt 429 .long Hardfault_interrupt 430 .long 0 431 .long 0 432 .long 0 433 .long Startup_Checksum 434 .long 0 435 .long 0 436 .long 0 437 .long SVCall_interrupt 438 .long 0 439 .long 0 440 .long PendSV_interrupt 441 .long SysTick_interrupt 442 443 .long SPI0_Interrupt 444 .long SPI1_Interrupt 445 .long 0 446 .long UART0_Interrupt 447 .long UART1_Interrupt 448 .long UART2_Interrupt 449 .long 0 450 .long 0 451 .long I2C_Interrupt 452 .long SCT_Interrupt 453 .long MRT_Interrupt 454 .long CMP_Interrupt 455 .long WDT_Interrupt 456 .long BOD_Interrupt 457 .long 0 458 .long WKT_Interrupt 459 .long 0 460 .long 0 461 .long 0 462 .long 0 463 .long 0 464 .long 0 465 .long 0 466 .long 0 467 .long PINIT0_Interrupt 468 .long PINIT1_Interrupt 469 .long PINIT2_Interrupt 470 .long PINIT3_Interrupt 471 .long PINIT4_Interrupt 472 .long PINIT5_Interrupt 473 .long PINIT6_Interrupt 474 .long PINIT7_Interrupt 475 476 .weak NonMaskableInt_interrupt 477 .weak Hardfault_interrupt 478 .weak Startup_Checksum 479 .weak SVCall_interrupt 480 .weak PendSV_interrupt 481 .weak SysTick_interrupt 482 483 .weak SPI0_Interrupt 484 .weak SPI1_Interrupt 485 .weak UART0_Interrupt 486 .weak UART1_Interrupt 487 .weak UART2_Interrupt 488 .weak I2C_Interrupt 489 .weak SCT_Interrupt 490 .weak MRT_Interrupt 491 .weak CMP_Interrupt 492 .weak WDT_Interrupt 493 .weak BOD_Interrupt 494 .weak WKT_Interrupt 495 .weak PINIT0_Interrupt 496 .weak PINIT1_Interrupt 497 .weak PINIT2_Interrupt 498 .weak PINIT3_Interrupt 499 .weak PINIT4_Interrupt 500 .weak PINIT5_Interrupt 501 .weak PINIT6_Interrupt 502 .weak PINIT7_Interrupt 503 504 .set NonMaskableInt_interrupt, Startup 505 .set Hardfault_interrupt , Startup 506 .set SVCall_interrupt , Startup 507 .set PendSV_interrupt , Startup 508 .set SysTick_interrupt , Startup 509 510 .set SPI0_Interrupt , Startup 511 .set SPI1_Interrupt , Startup 512 .set UART0_Interrupt , Startup 513 .set UART1_Interrupt , Startup 514 .set UART2_Interrupt , Startup 515 .set I2C_Interrupt , Startup 516 .set SCT_Interrupt , Startup 517 .set MRT_Interrupt , Startup 518 .set CMP_Interrupt , Startup 519 .set WDT_Interrupt , Startup 520 .set BOD_Interrupt , Startup 521 .set WKT_Interrupt , Startup 522 .set PINIT0_Interrupt, Startup 523 .set PINIT1_Interrupt, Startup 524 .set PINIT2_Interrupt, Startup 525 .set PINIT3_Interrupt, Startup 526 .set PINIT4_Interrupt, Startup 527 .set PINIT5_Interrupt, Startup 528 .set PINIT6_Interrupt, Startup 529 .set PINIT7_Interrupt, Startup 530 531 .text 532end; 533 534end. 535