1unit ATmega128RFA1; 2 3{$goto on} 4 5interface 6 7var 8 // ANALOG_COMPARATOR 9 ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B 10 ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register 11 DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 1 12 // USART0 13 UDR0 : byte absolute $00+$C6; // USART0 I/O Data Register 14 UCSR0A : byte absolute $00+$C0; // USART0 Control and Status Register A 15 UCSR0B : byte absolute $00+$C1; // USART0 Control and Status Register B 16 UCSR0C : byte absolute $00+$C2; // USART0 Control and Status Register C 17 UBRR0 : word absolute $00+$C4; // USART0 Baud Rate Register Bytes 18 UBRR0L : byte absolute $00+$C4; // USART0 Baud Rate Register Bytes 19 UBRR0H : byte absolute $00+$C4+1; // USART0 Baud Rate Register Bytes 20 // USART1 21 UDR1 : byte absolute $00+$CE; // USART1 I/O Data Register 22 UCSR1A : byte absolute $00+$C8; // USART1 Control and Status Register A 23 UCSR1B : byte absolute $00+$C9; // USART1 Control and Status Register B 24 UCSR1C : byte absolute $00+$CA; // USART1 Control and Status Register C 25 UBRR1 : word absolute $00+$CC; // USART1 Baud Rate Register Bytes 26 UBRR1L : byte absolute $00+$CC; // USART1 Baud Rate Register Bytes 27 UBRR1H : byte absolute $00+$CC+1; // USART1 Baud Rate Register Bytes 28 // TWI 29 TWAMR : byte absolute $00+$BD; // TWI (Slave) Address Mask Register 30 TWBR : byte absolute $00+$B8; // TWI Bit Rate Register 31 TWCR : byte absolute $00+$BC; // TWI Control Register 32 TWSR : byte absolute $00+$B9; // TWI Status Register 33 TWDR : byte absolute $00+$BB; // TWI Data Register 34 TWAR : byte absolute $00+$BA; // TWI (Slave) Address Register 35 // SPI 36 SPCR : byte absolute $00+$4C; // SPI Control Register 37 SPSR : byte absolute $00+$4D; // SPI Status Register 38 SPDR : byte absolute $00+$4E; // SPI Data Register 39 // PORTA 40 PORTA : byte absolute $00+$22; // Port A Data Register 41 DDRA : byte absolute $00+$21; // Port A Data Direction Register 42 PINA : byte absolute $00+$20; // Port A Input Pins Address 43 // PORTB 44 PORTB : byte absolute $00+$25; // Port B Data Register 45 DDRB : byte absolute $00+$24; // Port B Data Direction Register 46 PINB : byte absolute $00+$23; // Port B Input Pins Address 47 // PORTC 48 PORTC : byte absolute $00+$28; // Port C Data Register 49 DDRC : byte absolute $00+$27; // Port C Data Direction Register 50 PINC : byte absolute $00+$26; // Port C Input Pins Address 51 // PORTD 52 PORTD : byte absolute $00+$2B; // Port D Data Register 53 DDRD : byte absolute $00+$2A; // Port D Data Direction Register 54 PIND : byte absolute $00+$29; // Port D Input Pins Address 55 // PORTE 56 PORTE : byte absolute $00+$2E; // Port E Data Register 57 DDRE : byte absolute $00+$2D; // Port E Data Direction Register 58 PINE : byte absolute $00+$2C; // Port E Input Pins Address 59 // PORTF 60 PORTF : byte absolute $00+$31; // Port F Data Register 61 DDRF : byte absolute $00+$30; // Port F Data Direction Register 62 PINF : byte absolute $00+$2F; // Port F Input Pins Address 63 // PORTG 64 PORTG : byte absolute $00+$34; // Port G Data Register 65 DDRG : byte absolute $00+$33; // Port G Data Direction Register 66 PING : byte absolute $00+$32; // Port G Input Pins Address 67 // TIMER_COUNTER_0 68 OCR0B : byte absolute $00+$48; // Timer/Counter0 Output Compare Register B 69 OCR0A : byte absolute $00+$47; // Timer/Counter0 Output Compare Register 70 TCNT0 : byte absolute $00+$46; // Timer/Counter0 Register 71 TCCR0B : byte absolute $00+$45; // Timer/Counter0 Control Register B 72 TCCR0A : byte absolute $00+$44; // Timer/Counter0 Control Register A 73 TIMSK0 : byte absolute $00+$6E; // Timer/Counter0 Interrupt Mask Register 74 TIFR0 : byte absolute $00+$35; // Timer/Counter0 Interrupt Flag Register 75 GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register 76 // TIMER_COUNTER_2 77 TIMSK2 : byte absolute $00+$70; // Timer/Counter Interrupt Mask register 78 TIFR2 : byte absolute $00+$37; // Timer/Counter Interrupt Flag Register 79 TCCR2A : byte absolute $00+$B0; // Timer/Counter2 Control Register A 80 TCCR2B : byte absolute $00+$B1; // Timer/Counter2 Control Register B 81 TCNT2 : byte absolute $00+$B2; // Timer/Counter2 82 OCR2B : byte absolute $00+$B4; // Timer/Counter2 Output Compare Register B 83 OCR2A : byte absolute $00+$B3; // Timer/Counter2 Output Compare Register A 84 ASSR : byte absolute $00+$B6; // Asynchronous Status Register 85 // WATCHDOG 86 WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register 87 // TIMER_COUNTER_5 88 TCCR5A : byte absolute $00+$120; // Timer/Counter5 Control Register A 89 TCCR5B : byte absolute $00+$121; // Timer/Counter5 Control Register B 90 TCCR5C : byte absolute $00+$122; // Timer/Counter5 Control Register C 91 TCNT5 : word absolute $00+$124; // Timer/Counter5 Bytes 92 TCNT5L : byte absolute $00+$124; // Timer/Counter5 Bytes 93 TCNT5H : byte absolute $00+$124+1; // Timer/Counter5 Bytes 94 OCR5A : word absolute $00+$128; // Timer/Counter5 Output Compare Register A Bytes 95 OCR5AL : byte absolute $00+$128; // Timer/Counter5 Output Compare Register A Bytes 96 OCR5AH : byte absolute $00+$128+1; // Timer/Counter5 Output Compare Register A Bytes 97 OCR5B : word absolute $00+$12A; // Timer/Counter5 Output Compare Register B Bytes 98 OCR5BL : byte absolute $00+$12A; // Timer/Counter5 Output Compare Register B Bytes 99 OCR5BH : byte absolute $00+$12A+1; // Timer/Counter5 Output Compare Register B Bytes 100 OCR5C : word absolute $00+$12C; // Timer/Counter5 Output Compare Register C Bytes 101 OCR5CL : byte absolute $00+$12C; // Timer/Counter5 Output Compare Register C Bytes 102 OCR5CH : byte absolute $00+$12C+1; // Timer/Counter5 Output Compare Register C Bytes 103 ICR5 : word absolute $00+$126; // Timer/Counter5 Input Capture Register Bytes 104 ICR5L : byte absolute $00+$126; // Timer/Counter5 Input Capture Register Bytes 105 ICR5H : byte absolute $00+$126+1; // Timer/Counter5 Input Capture Register Bytes 106 TIMSK5 : byte absolute $00+$73; // Timer/Counter5 Interrupt Mask Register 107 TIFR5 : byte absolute $00+$3A; // Timer/Counter5 Interrupt Flag Register 108 // TIMER_COUNTER_4 109 TCCR4A : byte absolute $00+$A0; // Timer/Counter4 Control Register A 110 TCCR4B : byte absolute $00+$A1; // Timer/Counter4 Control Register B 111 TCCR4C : byte absolute $00+$A2; // Timer/Counter4 Control Register C 112 TCNT4 : word absolute $00+$A4; // Timer/Counter4 Bytes 113 TCNT4L : byte absolute $00+$A4; // Timer/Counter4 Bytes 114 TCNT4H : byte absolute $00+$A4+1; // Timer/Counter4 Bytes 115 OCR4A : word absolute $00+$A8; // Timer/Counter4 Output Compare Register A Bytes 116 OCR4AL : byte absolute $00+$A8; // Timer/Counter4 Output Compare Register A Bytes 117 OCR4AH : byte absolute $00+$A8+1; // Timer/Counter4 Output Compare Register A Bytes 118 OCR4B : word absolute $00+$AA; // Timer/Counter4 Output Compare Register B Bytes 119 OCR4BL : byte absolute $00+$AA; // Timer/Counter4 Output Compare Register B Bytes 120 OCR4BH : byte absolute $00+$AA+1; // Timer/Counter4 Output Compare Register B Bytes 121 OCR4C : word absolute $00+$AC; // Timer/Counter4 Output Compare Register C Bytes 122 OCR4CL : byte absolute $00+$AC; // Timer/Counter4 Output Compare Register C Bytes 123 OCR4CH : byte absolute $00+$AC+1; // Timer/Counter4 Output Compare Register C Bytes 124 ICR4 : word absolute $00+$A6; // Timer/Counter4 Input Capture Register Bytes 125 ICR4L : byte absolute $00+$A6; // Timer/Counter4 Input Capture Register Bytes 126 ICR4H : byte absolute $00+$A6+1; // Timer/Counter4 Input Capture Register Bytes 127 TIMSK4 : byte absolute $00+$72; // Timer/Counter4 Interrupt Mask Register 128 TIFR4 : byte absolute $00+$39; // Timer/Counter4 Interrupt Flag Register 129 // TIMER_COUNTER_3 130 TCCR3A : byte absolute $00+$90; // Timer/Counter3 Control Register A 131 TCCR3B : byte absolute $00+$91; // Timer/Counter3 Control Register B 132 TCCR3C : byte absolute $00+$92; // Timer/Counter3 Control Register C 133 TCNT3 : word absolute $00+$94; // Timer/Counter3 Bytes 134 TCNT3L : byte absolute $00+$94; // Timer/Counter3 Bytes 135 TCNT3H : byte absolute $00+$94+1; // Timer/Counter3 Bytes 136 OCR3A : word absolute $00+$98; // Timer/Counter3 Output Compare Register A Bytes 137 OCR3AL : byte absolute $00+$98; // Timer/Counter3 Output Compare Register A Bytes 138 OCR3AH : byte absolute $00+$98+1; // Timer/Counter3 Output Compare Register A Bytes 139 OCR3B : word absolute $00+$9A; // Timer/Counter3 Output Compare Register B Bytes 140 OCR3BL : byte absolute $00+$9A; // Timer/Counter3 Output Compare Register B Bytes 141 OCR3BH : byte absolute $00+$9A+1; // Timer/Counter3 Output Compare Register B Bytes 142 OCR3C : word absolute $00+$9C; // Timer/Counter3 Output Compare Register C Bytes 143 OCR3CL : byte absolute $00+$9C; // Timer/Counter3 Output Compare Register C Bytes 144 OCR3CH : byte absolute $00+$9C+1; // Timer/Counter3 Output Compare Register C Bytes 145 ICR3 : word absolute $00+$96; // Timer/Counter3 Input Capture Register Bytes 146 ICR3L : byte absolute $00+$96; // Timer/Counter3 Input Capture Register Bytes 147 ICR3H : byte absolute $00+$96+1; // Timer/Counter3 Input Capture Register Bytes 148 TIMSK3 : byte absolute $00+$71; // Timer/Counter3 Interrupt Mask Register 149 TIFR3 : byte absolute $00+$38; // Timer/Counter3 Interrupt Flag Register 150 // TIMER_COUNTER_1 151 TCCR1A : byte absolute $00+$80; // Timer/Counter1 Control Register A 152 TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B 153 TCCR1C : byte absolute $00+$82; // Timer/Counter1 Control Register C 154 TCNT1 : word absolute $00+$84; // Timer/Counter1 Bytes 155 TCNT1L : byte absolute $00+$84; // Timer/Counter1 Bytes 156 TCNT1H : byte absolute $00+$84+1; // Timer/Counter1 Bytes 157 OCR1A : word absolute $00+$88; // Timer/Counter1 Output Compare Register A Bytes 158 OCR1AL : byte absolute $00+$88; // Timer/Counter1 Output Compare Register A Bytes 159 OCR1AH : byte absolute $00+$88+1; // Timer/Counter1 Output Compare Register A Bytes 160 OCR1B : word absolute $00+$8A; // Timer/Counter1 Output Compare Register B Bytes 161 OCR1BL : byte absolute $00+$8A; // Timer/Counter1 Output Compare Register B Bytes 162 OCR1BH : byte absolute $00+$8A+1; // Timer/Counter1 Output Compare Register B Bytes 163 OCR1C : word absolute $00+$8C; // Timer/Counter1 Output Compare Register C Bytes 164 OCR1CL : byte absolute $00+$8C; // Timer/Counter1 Output Compare Register C Bytes 165 OCR1CH : byte absolute $00+$8C+1; // Timer/Counter1 Output Compare Register C Bytes 166 ICR1 : word absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 167 ICR1L : byte absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 168 ICR1H : byte absolute $00+$86+1; // Timer/Counter1 Input Capture Register Bytes 169 TIMSK1 : byte absolute $00+$6F; // Timer/Counter1 Interrupt Mask Register 170 TIFR1 : byte absolute $00+$36; // Timer/Counter1 Interrupt Flag Register 171 // TRX24 172 AES_CTRL : byte absolute $00+$13C; // AES Control Register 173 AES_STATUS : byte absolute $00+$13D; // AES Status Register 174 AES_STATE : byte absolute $00+$13E; // AES Plain and Cipher Text Buffer Register 175 AES_KEY : byte absolute $00+$13F; // AES Encryption and Decryption Key Buffer Register 176 TRX_STATUS : byte absolute $00+$141; // Transceiver Status Register 177 TRX_STATE : byte absolute $00+$142; // Transceiver State Control Register 178 TRX_CTRL_0 : byte absolute $00+$143; // Reserved 179 TRX_CTRL_1 : byte absolute $00+$144; // Transceiver Control Register 1 180 PHY_TX_PWR : byte absolute $00+$145; // Transceiver Transmit Power Control Register 181 PHY_RSSI : byte absolute $00+$146; // Receiver Signal Strength Indicator Register 182 PHY_ED_LEVEL : byte absolute $00+$147; // Transceiver Energy Detection Level Register 183 PHY_CC_CCA : byte absolute $00+$148; // Transceiver Clear Channel Assessment (CCA) Control Register 184 CCA_THRES : byte absolute $00+$149; // Transceiver CCA Threshold Setting Register 185 RX_CTRL : byte absolute $00+$14A; // Transceiver Receive Control Register 186 SFD_VALUE : byte absolute $00+$14B; // Start of Frame Delimiter Value Register 187 TRX_CTRL_2 : byte absolute $00+$14C; // Transceiver Control Register 2 188 ANT_DIV : byte absolute $00+$14D; // Antenna Diversity Control Register 189 IRQ_MASK : byte absolute $00+$14E; // Transceiver Interrupt Enable Register 190 IRQ_STATUS : byte absolute $00+$14F; // Transceiver Interrupt Status Register 191 VREG_CTRL : byte absolute $00+$150; // Voltage Regulator Control and Status Register 192 BATMON : byte absolute $00+$151; // Battery Monitor Control and Status Register 193 XOSC_CTRL : byte absolute $00+$152; // Crystal Oscillator Control Register 194 RX_SYN : byte absolute $00+$155; // Transceiver Receiver Sensitivity Control Register 195 XAH_CTRL_1 : byte absolute $00+$157; // Transceiver Acknowledgment Frame Control Register 1 196 FTN_CTRL : byte absolute $00+$158; // Transceiver Filter Tuning Control Register 197 PLL_CF : byte absolute $00+$15A; // Transceiver Center Frequency Calibration Control Register 198 PLL_DCU : byte absolute $00+$15B; // Transceiver Delay Cell Calibration Control Register 199 PART_NUM : byte absolute $00+$15C; // Device Identification Register (Part Number) 200 VERSION_NUM : byte absolute $00+$15D; // Device Identification Register (Version Number) 201 MAN_ID_0 : byte absolute $00+$15E; // Device Identification Register (Manufacture ID Low Byte) 202 MAN_ID_1 : byte absolute $00+$15F; // Device Identification Register (Manufacture ID High Byte) 203 SHORT_ADDR_0 : byte absolute $00+$160; // Transceiver MAC Short Address Register (Low Byte) 204 SHORT_ADDR_1 : byte absolute $00+$161; // Transceiver MAC Short Address Register (High Byte) 205 PAN_ID_0 : byte absolute $00+$162; // Transceiver Personal Area Network ID Register (Low Byte) 206 PAN_ID_1 : byte absolute $00+$163; // Transceiver Personal Area Network ID Register (High Byte) 207 IEEE_ADDR_0 : byte absolute $00+$164; // Transceiver MAC IEEE Address Register 0 208 IEEE_ADDR_1 : byte absolute $00+$165; // Transceiver MAC IEEE Address Register 1 209 IEEE_ADDR_2 : byte absolute $00+$166; // Transceiver MAC IEEE Address Register 2 210 IEEE_ADDR_3 : byte absolute $00+$167; // Transceiver MAC IEEE Address Register 3 211 IEEE_ADDR_4 : byte absolute $00+$168; // Transceiver MAC IEEE Address Register 4 212 IEEE_ADDR_5 : byte absolute $00+$169; // Transceiver MAC IEEE Address Register 5 213 IEEE_ADDR_6 : byte absolute $00+$16A; // Transceiver MAC IEEE Address Register 6 214 IEEE_ADDR_7 : byte absolute $00+$16B; // Transceiver MAC IEEE Address Register 7 215 XAH_CTRL_0 : byte absolute $00+$16C; // Transceiver Extended Operating Mode Control Register 216 CSMA_SEED_0 : byte absolute $00+$16D; // Transceiver CSMA-CA Random Number Generator Seed Register 217 CSMA_SEED_1 : byte absolute $00+$16E; // Transceiver Acknowledgment Frame Control Register 2 218 CSMA_BE : byte absolute $00+$16F; // Transceiver CSMA-CA Back-off Exponent Control Register 219 TST_CTRL_DIGI : byte absolute $00+$176; // Transceiver Digital Test Control Register 220 TST_RX_LENGTH : byte absolute $00+$17B; // Transceiver Received Frame Length Register 221 TRXFBST : byte absolute $00+$180; // Start of frame buffer 222 TRXFBEND : byte absolute $00+$1FF; // End of frame buffer 223 // SYMCNT 224 SCOCR1HH : byte absolute $00+$F8; // Symbol Counter Output Compare Register 1 HH-Byte 225 SCOCR1HL : byte absolute $00+$F7; // Symbol Counter Output Compare Register 1 HL-Byte 226 SCOCR1LH : byte absolute $00+$F6; // Symbol Counter Output Compare Register 1 LH-Byte 227 SCOCR1LL : byte absolute $00+$F5; // Symbol Counter Output Compare Register 1 LL-Byte 228 SCOCR2HH : byte absolute $00+$F4; // Symbol Counter Output Compare Register 2 HH-Byte 229 SCOCR2HL : byte absolute $00+$F3; // Symbol Counter Output Compare Register 2 HL-Byte 230 SCOCR2LH : byte absolute $00+$F2; // Symbol Counter Output Compare Register 2 LH-Byte 231 SCOCR2LL : byte absolute $00+$F1; // Symbol Counter Output Compare Register 2 LL-Byte 232 SCOCR3HH : byte absolute $00+$F0; // Symbol Counter Output Compare Register 3 HH-Byte 233 SCOCR3HL : byte absolute $00+$EF; // Symbol Counter Output Compare Register 3 HL-Byte 234 SCOCR3LH : byte absolute $00+$EE; // Symbol Counter Output Compare Register 3 LH-Byte 235 SCOCR3LL : byte absolute $00+$ED; // Symbol Counter Output Compare Register 3 LL-Byte 236 SCTSRHH : byte absolute $00+$EC; // Symbol Counter Frame Timestamp Register HH-Byte 237 SCTSRHL : byte absolute $00+$EB; // Symbol Counter Frame Timestamp Register HL-Byte 238 SCTSRLH : byte absolute $00+$EA; // Symbol Counter Frame Timestamp Register LH-Byte 239 SCTSRLL : byte absolute $00+$E9; // Symbol Counter Frame Timestamp Register LL-Byte 240 SCBTSRHH : byte absolute $00+$E8; // Symbol Counter Beacon Timestamp Register HH-Byte 241 SCBTSRHL : byte absolute $00+$E7; // Symbol Counter Beacon Timestamp Register HL-Byte 242 SCBTSRLH : byte absolute $00+$E6; // Symbol Counter Beacon Timestamp Register LH-Byte 243 SCBTSRLL : byte absolute $00+$E5; // Symbol Counter Beacon Timestamp Register LL-Byte 244 SCCNTHH : byte absolute $00+$E4; // Symbol Counter Register HH-Byte 245 SCCNTHL : byte absolute $00+$E3; // Symbol Counter Register HL-Byte 246 SCCNTLH : byte absolute $00+$E2; // Symbol Counter Register LH-Byte 247 SCCNTLL : byte absolute $00+$E1; // Symbol Counter Register LL-Byte 248 SCIRQS : byte absolute $00+$E0; // Symbol Counter Interrupt Status Register 249 SCIRQM : byte absolute $00+$DF; // Symbol Counter Interrupt Mask Register 250 SCSR : byte absolute $00+$DE; // Symbol Counter Status Register 251 SCCR1 : byte absolute $00+$DD; // Symbol Counter Control Register 1 252 SCCR0 : byte absolute $00+$DC; // Symbol Counter Control Register 0 253 // EEPROM 254 EEAR : word absolute $00+$41; // EEPROM Address Register Bytes 255 EEARL : byte absolute $00+$41; // EEPROM Address Register Bytes 256 EEARH : byte absolute $00+$41+1; // EEPROM Address Register Bytes 257 EEDR : byte absolute $00+$40; // EEPROM Data Register 258 EECR : byte absolute $00+$3F; // EEPROM Control Register 259 // JTAG 260 OCDR : byte absolute $00+$51; // On-Chip Debug Register 261 MCUCR : byte absolute $00+$55; // MCU Control Register 262 MCUSR : byte absolute $00+$54; // MCU Status Register 263 // EXTERNAL_INTERRUPT 264 EICRA : byte absolute $00+$69; // External Interrupt Control Register A 265 EICRB : byte absolute $00+$6A; // External Interrupt Control Register B 266 EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register 267 EIFR : byte absolute $00+$3C; // External Interrupt Flag Register 268 PCMSK2 : byte absolute $00+$6D; // Pin Change Mask Register 2 269 PCMSK1 : byte absolute $00+$6C; // Pin Change Mask Register 1 270 PCMSK0 : byte absolute $00+$6B; // Pin Change Mask Register 0 271 PCIFR : byte absolute $00+$3B; // Pin Change Interrupt Flag Register 272 PCICR : byte absolute $00+$68; // Pin Change Interrupt Control Register 273 // AD_CONVERTER 274 ADMUX : byte absolute $00+$7C; // The ADC Multiplexer Selection Register 275 ADC : word absolute $00+$78; // ADC Data Register Bytes 276 ADCL : byte absolute $00+$78; // ADC Data Register Bytes 277 ADCH : byte absolute $00+$78+1; // ADC Data Register Bytes 278 ADCSRA : byte absolute $00+$7A; // The ADC Control and Status Register A 279 ADCSRC : byte absolute $00+$77; // The ADC Control and Status Register C 280 DIDR2 : byte absolute $00+$7D; // Digital Input Disable Register 2 281 DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0 282 // BOOT_LOAD 283 SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register 284 // CPU 285 SREG : byte absolute $00+$5F; // Status Register 286 SP : word absolute $00+$5D; // Stack Pointer 287 SPL : byte absolute $00+$5D; // Stack Pointer 288 SPH : byte absolute $00+$5D+1; // Stack Pointer 289 OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value 290 CLKPR : byte absolute $00+$61; // Clock Prescale Register 291 SMCR : byte absolute $00+$53; // Sleep Mode Control Register 292 RAMPZ : byte absolute $00+$5B; // Extended Z-pointer Register for ELPM/SPM 293 GPIOR2 : byte absolute $00+$4B; // General Purpose I/O Register 2 294 GPIOR1 : byte absolute $00+$4A; // General Purpose IO Register 1 295 GPIOR0 : byte absolute $00+$3E; // General Purpose IO Register 0 296 PRR2 : byte absolute $00+$63; // Power Reduction Register 2 297 PRR1 : byte absolute $00+$65; // Power Reduction Register 1 298 PRR0 : byte absolute $00+$64; // Power Reduction Register0 299 // FLASH 300 NEMCR : byte absolute $00+$75; // Flash Extended-Mode Control-Register 301 BGCR : byte absolute $00+$67; // Reference Voltage Calibration Register 302 // PWRCTRL 303 TRXPR : byte absolute $00+$139; // Transceiver Pin Register 304 DRTRAM0 : byte absolute $00+$135; // Data Retention Configuration Register of SRAM 0 305 DRTRAM1 : byte absolute $00+$134; // Data Retention Configuration Register of SRAM 1 306 DRTRAM2 : byte absolute $00+$133; // Data Retention Configuration Register of SRAM 2 307 DRTRAM3 : byte absolute $00+$132; // Data Retention Configuration Register of SRAM 3 308 LLDRL : byte absolute $00+$130; // Low Leakage Voltage Regulator Data Register (Low-Byte) 309 LLDRH : byte absolute $00+$131; // Low Leakage Voltage Regulator Data Register (High-Byte) 310 LLCR : byte absolute $00+$12F; // Low Leakage Voltage Regulator Control Register 311 DPDS0 : byte absolute $00+$136; // Port Driver Strength Register 0 312 DPDS1 : byte absolute $00+$137; // Port Driver Strength Register 1 313 // USART0_SPI 314 // USART1_SPI 315 316const 317 // ADCSRB 318 ACME = 6; // Analog Comparator Multiplexer Enable 319 // ACSR 320 ACD = 7; // Analog Comparator Disable 321 ACBG = 6; // Analog Comparator Bandgap Select 322 ACO = 5; // Analog Compare Output 323 ACI = 4; // Analog Comparator Interrupt Flag 324 ACIE = 3; // Analog Comparator Interrupt Enable 325 ACIC = 2; // Analog Comparator Input Capture Enable 326 ACIS = 0; // Analog Comparator Interrupt Mode Select 327 // DIDR1 328 AIN1D = 1; // AIN1 Digital Input Disable 329 AIN0D = 0; // AIN0 Digital Input Disable 330 // UCSR0A 331 RXC0 = 7; // USART Receive Complete 332 TXC0 = 6; // USART Transmit Complete 333 UDRE0 = 5; // USART Data Register Empty 334 FE0 = 4; // Frame Error 335 DOR0 = 3; // Data OverRun 336 UPE0 = 2; // USART Parity Error 337 U2X0 = 1; // Double the USART Transmission Speed 338 MPCM0 = 0; // Multi-processor Communication Mode 339 // UCSR0B 340 RXCIE0 = 7; // RX Complete Interrupt Enable 341 TXCIE0 = 6; // TX Complete Interrupt Enable 342 UDRIE0 = 5; // USART Data Register Empty Interrupt Enable 343 RXEN0 = 4; // Receiver Enable 344 TXEN0 = 3; // Transmitter Enable 345 UCSZ02 = 2; // Character Size 346 RXB80 = 1; // Receive Data Bit 8 347 TXB80 = 0; // Transmit Data Bit 8 348 // UCSR0C 349 UMSEL0 = 6; // USART Mode Select 350 UPM0 = 4; // Parity Mode 351 USBS0 = 3; // Stop Bit Select 352 UCSZ0 = 1; // Character Size 353 UCPOL0 = 0; // Clock Polarity 354 // UCSR1A 355 RXC1 = 7; // USART Receive Complete 356 TXC1 = 6; // USART Transmit Complete 357 UDRE1 = 5; // USART Data Register Empty 358 FE1 = 4; // Frame Error 359 DOR1 = 3; // Data OverRun 360 UPE1 = 2; // USART Parity Error 361 U2X1 = 1; // Double the USART Transmission Speed 362 MPCM1 = 0; // Multi-processor Communication Mode 363 // UCSR1B 364 RXCIE1 = 7; // RX Complete Interrupt Enable 365 TXCIE1 = 6; // TX Complete Interrupt Enable 366 UDRIE1 = 5; // USART Data Register Empty Interrupt Enable 367 RXEN1 = 4; // Receiver Enable 368 TXEN1 = 3; // Transmitter Enable 369 UCSZ12 = 2; // Character Size 370 RXB81 = 1; // Receive Data Bit 8 371 TXB81 = 0; // Transmit Data Bit 8 372 // UCSR1C 373 UMSEL1 = 6; // USART Mode Select 374 UPM1 = 4; // Parity Mode 375 USBS1 = 3; // Stop Bit Select 376 UCSZ1 = 1; // Character Size 377 UCPOL1 = 0; // Clock Polarity 378 // TWAMR 379 TWAM = 1; // TWI Address Mask 380 Res = 0; // Reserved Bit 381 // TWCR 382 TWINT = 7; // TWI Interrupt Flag 383 TWEA = 6; // TWI Enable Acknowledge Bit 384 TWSTA = 5; // TWI START Condition Bit 385 TWSTO = 4; // TWI STOP Condition Bit 386 TWWC = 3; // TWI Write Collision Flag 387 TWEN = 2; // TWI Enable Bit 388 TWIE = 0; // TWI Interrupt Enable 389 // TWSR 390 TWS = 3; // TWI Status 391 TWPS = 0; // TWI Prescaler Bits 392 // TWAR 393 TWA = 1; // TWI (Slave) Address 394 TWGCE = 0; // TWI General Call Recognition Enable Bit 395 // SPCR 396 SPIE = 7; // SPI Interrupt Enable 397 SPE = 6; // SPI Enable 398 DORD = 5; // Data Order 399 MSTR = 4; // Master/Slave Select 400 CPOL = 3; // Clock polarity 401 CPHA = 2; // Clock Phase 402 SPR = 0; // SPI Clock Rate Select 1 and 0 403 // SPSR 404 SPIF = 7; // SPI Interrupt Flag 405 WCOL = 6; // Write Collision Flag 406 SPI2X = 0; // Double SPI Speed Bit 407 // TCCR0B 408 FOC0A = 7; // Force Output Compare A 409 FOC0B = 6; // Force Output Compare B 410 WGM02 = 3; // 411 CS0 = 0; // Clock Select 412 // TCCR0A 413 COM0A = 6; // Compare Match Output A Mode 414 COM0B = 4; // Compare Match Output B Mode 415 WGM0 = 0; // Waveform Generation Mode 416 // TIMSK0 417 OCIE0B = 2; // Timer/Counter0 Output Compare Match B Interrupt Enable 418 OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable 419 TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable 420 // TIFR0 421 OCF0B = 2; // Timer/Counter0 Output Compare B Match Flag 422 OCF0A = 1; // Timer/Counter0 Output Compare A Match Flag 423 TOV0 = 0; // Timer/Counter0 Overflow Flag 424 // GTCCR 425 TSM = 7; // Timer/Counter Synchronization Mode 426 PSRASY = 1; // Prescaler Reset Timer/Counter2 427 PSRSYNC = 0; // Prescaler Reset for Synchronous Timer/Counters 428 // TIMSK2 429 OCIE2B = 2; // Timer/Counter2 Output Compare Match B Interrupt Enable 430 OCIE2A = 1; // Timer/Counter2 Output Compare Match A Interrupt Enable 431 TOIE2 = 0; // Timer/Counter2 Overflow Interrupt Enable 432 // TIFR2 433 OCF2B = 2; // Output Compare Flag 2 B 434 OCF2A = 1; // Output Compare Flag 2 A 435 TOV2 = 0; // Timer/Counter2 Overflow Flag 436 // TCCR2A 437 COM2A = 6; // Compare Match Output A Mode 438 COM2B = 4; // Compare Match Output B Mode 439 WGM2 = 0; // Waveform Generation Mode 440 // TCCR2B 441 FOC2A = 7; // Force Output Compare A 442 FOC2B = 6; // Force Output Compare B 443 WGM22 = 3; // Waveform Generation Mode 444 CS2 = 0; // Clock Select 445 // ASSR 446 EXCLKAMR = 7; // Enable External Clock Input for AMR 447 EXCLK = 6; // Enable External Clock Input 448 AS2 = 5; // Timer/Counter2 Asynchronous Mode 449 TCN2UB = 4; // Timer/Counter2 Update Busy 450 OCR2AUB = 3; // Timer/Counter2 Output Compare Register A Update Busy 451 OCR2BUB = 2; // Timer/Counter2 Output Compare Register B Update Busy 452 TCR2AUB = 1; // Timer/Counter2 Control Register A Update Busy 453 TCR2BUB = 0; // Timer/Counter2 Control Register B Update Busy 454 // GTCCR 455 // WDTCSR 456 WDIF = 7; // Watchdog Timeout Interrupt Flag 457 WDIE = 6; // Watchdog Timeout Interrupt Enable 458 WDP = 0; // Watchdog Timer Prescaler Bits 459 WDCE = 4; // Watchdog Change Enable 460 WDE = 3; // Watch Dog Enable 461 // TCCR5A 462 COM5A = 6; // Compare Output Mode for Channel A 463 COM5B = 4; // Compare Output Mode for Channel B 464 COM5C = 2; // Compare Output Mode for Channel C 465 WGM5 = 0; // Waveform Generation Mode 466 // TCCR5B 467 ICNC5 = 7; // Input Capture 5 Noise Canceller 468 ICES5 = 6; // Input Capture 5 Edge Select 469 CS5 = 0; // Clock Select 470 // TCCR5C 471 FOC5A = 7; // Force Output Compare for Channel A 472 FOC5B = 6; // Force Output Compare for Channel B 473 FOC5C = 5; // Force Output Compare for Channel C 474 // TIMSK5 475 ICIE5 = 5; // Timer/Counter5 Input Capture Interrupt Enable 476 OCIE5C = 3; // Timer/Counter5 Output Compare C Match Interrupt Enable 477 OCIE5B = 2; // Timer/Counter5 Output Compare B Match Interrupt Enable 478 OCIE5A = 1; // Timer/Counter5 Output Compare A Match Interrupt Enable 479 TOIE5 = 0; // Timer/Counter5 Overflow Interrupt Enable 480 // TIFR5 481 ICF5 = 5; // Timer/Counter5 Input Capture Flag 482 OCF5C = 3; // Timer/Counter5 Output Compare C Match Flag 483 OCF5B = 2; // Timer/Counter5 Output Compare B Match Flag 484 OCF5A = 1; // Timer/Counter5 Output Compare A Match Flag 485 TOV5 = 0; // Timer/Counter5 Overflow Flag 486 // TCCR4A 487 COM4A = 6; // Compare Output Mode for Channel A 488 COM4B = 4; // Compare Output Mode for Channel B 489 COM4C = 2; // Compare Output Mode for Channel C 490 WGM4 = 0; // Waveform Generation Mode 491 // TCCR4B 492 ICNC4 = 7; // Input Capture 4 Noise Canceller 493 ICES4 = 6; // Input Capture 4 Edge Select 494 CS4 = 0; // Clock Select 495 // TCCR4C 496 FOC4A = 7; // Force Output Compare for Channel A 497 FOC4B = 6; // Force Output Compare for Channel B 498 FOC4C = 5; // Force Output Compare for Channel C 499 // TIMSK4 500 ICIE4 = 5; // Timer/Counter4 Input Capture Interrupt Enable 501 OCIE4C = 3; // Timer/Counter4 Output Compare C Match Interrupt Enable 502 OCIE4B = 2; // Timer/Counter4 Output Compare B Match Interrupt Enable 503 OCIE4A = 1; // Timer/Counter4 Output Compare A Match Interrupt Enable 504 TOIE4 = 0; // Timer/Counter4 Overflow Interrupt Enable 505 // TIFR4 506 ICF4 = 5; // Timer/Counter4 Input Capture Flag 507 OCF4C = 3; // Timer/Counter4 Output Compare C Match Flag 508 OCF4B = 2; // Timer/Counter4 Output Compare B Match Flag 509 OCF4A = 1; // Timer/Counter4 Output Compare A Match Flag 510 TOV4 = 0; // Timer/Counter4 Overflow Flag 511 // TCCR3A 512 COM3A = 6; // Compare Output Mode for Channel A 513 COM3B = 4; // Compare Output Mode for Channel B 514 COM3C = 2; // Compare Output Mode for Channel C 515 WGM3 = 0; // Waveform Generation Mode 516 // TCCR3B 517 ICNC3 = 7; // Input Capture 3 Noise Canceller 518 ICES3 = 6; // Input Capture 3 Edge Select 519 CS3 = 0; // Clock Select 520 // TCCR3C 521 FOC3A = 7; // Force Output Compare for Channel A 522 FOC3B = 6; // Force Output Compare for Channel B 523 FOC3C = 5; // Force Output Compare for Channel C 524 // TIMSK3 525 ICIE3 = 5; // Timer/Counter3 Input Capture Interrupt Enable 526 OCIE3C = 3; // Timer/Counter3 Output Compare C Match Interrupt Enable 527 OCIE3B = 2; // Timer/Counter3 Output Compare B Match Interrupt Enable 528 OCIE3A = 1; // Timer/Counter3 Output Compare A Match Interrupt Enable 529 TOIE3 = 0; // Timer/Counter3 Overflow Interrupt Enable 530 // TIFR3 531 ICF3 = 5; // Timer/Counter3 Input Capture Flag 532 OCF3C = 3; // Timer/Counter3 Output Compare C Match Flag 533 OCF3B = 2; // Timer/Counter3 Output Compare B Match Flag 534 OCF3A = 1; // Timer/Counter3 Output Compare A Match Flag 535 TOV3 = 0; // Timer/Counter3 Overflow Flag 536 // TCCR1A 537 COM1A = 6; // Compare Output Mode for Channel A 538 COM1B = 4; // Compare Output Mode for Channel B 539 COM1C = 2; // Compare Output Mode for Channel C 540 WGM1 = 0; // Waveform Generation Mode 541 // TCCR1B 542 ICNC1 = 7; // Input Capture 1 Noise Canceller 543 ICES1 = 6; // Input Capture 1 Edge Select 544 CS1 = 0; // Clock Select 545 // TCCR1C 546 FOC1A = 7; // Force Output Compare for Channel A 547 FOC1B = 6; // Force Output Compare for Channel B 548 FOC1C = 5; // Force Output Compare for Channel C 549 // TIMSK1 550 ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable 551 OCIE1C = 3; // Timer/Counter1 Output Compare C Match Interrupt Enable 552 OCIE1B = 2; // Timer/Counter1 Output Compare B Match Interrupt Enable 553 OCIE1A = 1; // Timer/Counter1 Output Compare A Match Interrupt Enable 554 TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable 555 // TIFR1 556 ICF1 = 5; // Timer/Counter1 Input Capture Flag 557 OCF1C = 3; // Timer/Counter1 Output Compare C Match Flag 558 OCF1B = 2; // Timer/Counter1 Output Compare B Match Flag 559 OCF1A = 1; // Timer/Counter1 Output Compare A Match Flag 560 TOV1 = 0; // Timer/Counter1 Overflow Flag 561 // AES_CTRL 562 AES_REQUEST = 7; // Request AES Operation. 563 AES_MODE = 5; // Set AES Operation Mode 564 AES_DIR = 3; // Set AES Operation Direction 565 AES_IM = 2; // AES Interrupt Enable 566 // AES_STATUS 567 AES_ER = 7; // AES Operation Finished with Error 568 AES_DONE = 0; // AES Operation Finished with Success 569 // AES_STATE 570 // AES_KEY 571 // TRX_STATUS 572 CCA_DONE = 7; // CCA Algorithm Status 573 CCA_STATUS = 6; // CCA Status Result 574 TST_STATUS = 5; // Test mode status 575 // TRX_STATE 576 TRAC_STATUS = 5; // Transaction Status 577 TRX_CMD = 0; // State Control Command 578 // TRX_CTRL_0 579 // TRX_CTRL_1 580 PA_EXT_EN = 7; // External PA support enable 581 IRQ_2_EXT_EN = 6; // Connect Frame Start IRQ to TC1 582 TX_AUTO_CRC_ON = 5; // Enable Automatic CRC Calculation 583 // PHY_TX_PWR 584 PA_BUF_LT = 6; // Power Amplifier Buffer Lead Time 585 PA_LT = 4; // Power Amplifier Lead Time 586 TX_PWR = 0; // Transmit Power Setting 587 // PHY_RSSI 588 RX_CRC_VALID = 7; // Received Frame CRC Status 589 RND_VALUE = 5; // Random Value 590 RSSI = 0; // Receiver Signal Strength Indicator 591 // PHY_ED_LEVEL 592 ED_LEVEL = 0; // Energy Detection Level 593 // PHY_CC_CCA 594 CCA_REQUEST = 7; // Manual CCA Measurement Request 595 CCA_MODE = 5; // Select CCA Measurement Mode 596 CHANNEL = 0; // RX/TX Channel Selection 597 // CCA_THRES 598 CCA_CS_THRES = 4; // CS Threshold Level for CCA Measurement 599 CCA_ED_THRES = 0; // ED Threshold Level for CCA Measurement 600 // RX_CTRL 601 PDT_THRES = 0; // Receiver Sensitivity Control 602 // SFD_VALUE 603 // TRX_CTRL_2 604 RX_SAFE_MODE = 7; // RX Safe Mode 605 OQPSK_DATA_RATE = 0; // Data Rate Selection 606 // ANT_DIV 607 ANT_SEL = 7; // Antenna Diversity Antenna Status 608 ANT_DIV_EN = 3; // Enable Antenna Diversity 609 ANT_EXT_SW_EN = 2; // Enable External Antenna Switch Control 610 ANT_CTRL = 0; // Static Antenna Diversity Switch Control 611 // IRQ_MASK 612 AWAKE_EN = 7; // Awake Interrupt Enable 613 TX_END_EN = 6; // TX_END Interrupt Enable 614 AMI_EN = 5; // Address Match Interrupt Enable 615 CCA_ED_DONE_EN = 4; // End of ED Measurement Interrupt Enable 616 RX_END_EN = 3; // RX_END Interrupt Enable 617 RX_START_EN = 2; // RX_START Interrupt Enable 618 PLL_UNLOCK_EN = 1; // PLL Unlock Interrupt Enable 619 PLL_LOCK_EN = 0; // PLL Lock Interrupt Enable 620 // IRQ_STATUS 621 AWAKE = 7; // Awake Interrupt Status 622 TX_END = 6; // TX_END Interrupt Status 623 AMI = 5; // Address Match Interrupt Status 624 CCA_ED_DONE = 4; // End of ED Measurement Interrupt Status 625 RX_END = 3; // RX_END Interrupt Status 626 RX_START = 2; // RX_START Interrupt Status 627 PLL_UNLOCK = 1; // PLL Unlock Interrupt Status 628 PLL_LOCK = 0; // PLL Lock Interrupt Status 629 // VREG_CTRL 630 AVREG_EXT = 7; // Use External AVDD Regulator 631 AVDD_OK = 6; // AVDD Supply Voltage Valid 632 DVREG_EXT = 3; // Use External DVDD Regulator 633 DVDD_OK = 2; // DVDD Supply Voltage Valid 634 // BATMON 635 BAT_LOW = 7; // Battery Monitor Interrupt Status 636 BAT_LOW_EN = 6; // Battery Monitor Interrupt Enable 637 BATMON_OK = 5; // Battery Monitor Status 638 BATMON_HR = 4; // Battery Monitor Voltage Range 639 BATMON_VTH = 0; // Battery Monitor Threshold Voltage 640 // XOSC_CTRL 641 XTAL_MODE = 4; // Crystal Oscillator Operating Mode 642 XTAL_TRIM = 0; // Crystal Oscillator Load Capacitance Trimming 643 // RX_SYN 644 RX_PDT_DIS = 7; // Prevent Frame Reception 645 RX_PDT_LEVEL = 0; // Reduce Receiver Sensitivity 646 // XAH_CTRL_1 647 AACK_FLTR_RES_FT = 5; // Filter Reserved Frames 648 AACK_UPLD_RES_FT = 4; // Process Reserved Frames 649 AACK_ACK_TIME = 2; // Reduce Acknowledgment Time 650 AACK_PROM_MODE = 1; // Enable Promiscuous Mode 651 // FTN_CTRL 652 FTN_START = 7; // Start Calibration Loop of Filter Tuning Network 653 // PLL_CF 654 PLL_CF_START = 7; // Start Center Frequency Calibration 655 // PLL_DCU 656 PLL_DCU_START = 7; // Start Delay Cell Calibration 657 // PART_NUM 658 // VERSION_NUM 659 // MAN_ID_0 660 MAN_ID_07 = 7; // Manufacturer ID (Low Byte) 661 MAN_ID_06 = 6; // Manufacturer ID (Low Byte) 662 MAN_ID_05 = 5; // Manufacturer ID (Low Byte) 663 MAN_ID_04 = 4; // Manufacturer ID (Low Byte) 664 MAN_ID_03 = 3; // Manufacturer ID (Low Byte) 665 MAN_ID_02 = 2; // Manufacturer ID (Low Byte) 666 MAN_ID_01 = 1; // Manufacturer ID (Low Byte) 667 MAN_ID_00 = 0; // Manufacturer ID (Low Byte) 668 // MAN_ID_1 669 MAN_ID_ = 0; // Manufacturer ID (High Byte) 670 // SHORT_ADDR_0 671 SHORT_ADDR_07 = 7; // MAC Short Address 672 SHORT_ADDR_06 = 6; // MAC Short Address 673 SHORT_ADDR_05 = 5; // MAC Short Address 674 SHORT_ADDR_04 = 4; // MAC Short Address 675 SHORT_ADDR_03 = 3; // MAC Short Address 676 SHORT_ADDR_02 = 2; // MAC Short Address 677 SHORT_ADDR_01 = 1; // MAC Short Address 678 SHORT_ADDR_00 = 0; // MAC Short Address 679 // SHORT_ADDR_1 680 SHORT_ADDR_ = 0; // MAC Short Address 681 // PAN_ID_0 682 PAN_ID_07 = 7; // MAC Personal Area Network ID 683 PAN_ID_06 = 6; // MAC Personal Area Network ID 684 PAN_ID_05 = 5; // MAC Personal Area Network ID 685 PAN_ID_04 = 4; // MAC Personal Area Network ID 686 PAN_ID_03 = 3; // MAC Personal Area Network ID 687 PAN_ID_02 = 2; // MAC Personal Area Network ID 688 PAN_ID_01 = 1; // MAC Personal Area Network ID 689 PAN_ID_00 = 0; // MAC Personal Area Network ID 690 // PAN_ID_1 691 PAN_ID_ = 0; // MAC Personal Area Network ID 692 // IEEE_ADDR_0 693 IEEE_ADDR_07 = 7; // MAC IEEE Address 694 IEEE_ADDR_06 = 6; // MAC IEEE Address 695 IEEE_ADDR_05 = 5; // MAC IEEE Address 696 IEEE_ADDR_04 = 4; // MAC IEEE Address 697 IEEE_ADDR_03 = 3; // MAC IEEE Address 698 IEEE_ADDR_02 = 2; // MAC IEEE Address 699 IEEE_ADDR_01 = 1; // MAC IEEE Address 700 IEEE_ADDR_00 = 0; // MAC IEEE Address 701 // IEEE_ADDR_1 702 IEEE_ADDR_ = 0; // MAC IEEE Address 703 // IEEE_ADDR_2 704 // IEEE_ADDR_3 705 // IEEE_ADDR_4 706 // IEEE_ADDR_5 707 // IEEE_ADDR_6 708 // IEEE_ADDR_7 709 // XAH_CTRL_0 710 MAX_FRAME_RETRIES = 4; // Maximum Number of Frame Re-transmission Attempts 711 MAX_CSMA_RETRIES = 1; // Maximum Number of CSMA-CA Procedure Repetition Attempts 712 SLOTTED_OPERATION = 0; // Set Slotted Acknowledgment 713 // CSMA_SEED_0 714 CSMA_SEED_07 = 7; // Seed Value for CSMA Random Number Generator 715 CSMA_SEED_06 = 6; // Seed Value for CSMA Random Number Generator 716 CSMA_SEED_05 = 5; // Seed Value for CSMA Random Number Generator 717 CSMA_SEED_04 = 4; // Seed Value for CSMA Random Number Generator 718 CSMA_SEED_03 = 3; // Seed Value for CSMA Random Number Generator 719 CSMA_SEED_02 = 2; // Seed Value for CSMA Random Number Generator 720 CSMA_SEED_01 = 1; // Seed Value for CSMA Random Number Generator 721 CSMA_SEED_00 = 0; // Seed Value for CSMA Random Number Generator 722 // CSMA_SEED_1 723 AACK_FVN_MODE = 6; // Acknowledgment Frame Filter Mode 724 AACK_SET_PD = 5; // Set Frame Pending Sub-field 725 AACK_DIS_ACK = 4; // Disable Acknowledgment Frame Transmission 726 AACK_I_AM_COORD = 3; // Set Personal Area Network Coordinator 727 // CSMA_BE 728 MAX_BE = 4; // Maximum Back-off Exponent 729 MIN_BE = 0; // Minimum Back-off Exponent 730 // TST_CTRL_DIGI 731 TST_CTRL_DIG = 0; // Digital Test Controller Register 732 // TST_RX_LENGTH 733 RX_LENGTH = 0; // Received Frame Length 734 // SCOCR1HH 735 // SCOCR1HL 736 // SCOCR1LH 737 // SCOCR1LL 738 // SCOCR2HH 739 // SCOCR2HL 740 // SCOCR2LH 741 // SCOCR2LL 742 // SCOCR3HH 743 // SCOCR3HL 744 // SCOCR3LH 745 // SCOCR3LL 746 // SCTSRHH 747 // SCTSRHL 748 // SCTSRLH 749 // SCTSRLL 750 // SCBTSRHH 751 // SCBTSRHL 752 // SCBTSRLH 753 // SCBTSRLL 754 // SCCNTHH 755 // SCCNTHL 756 // SCCNTLH 757 // SCCNTLL 758 // SCIRQS 759 IRQSBO = 4; // Backoff Slot Counter IRQ 760 IRQSOF = 3; // Symbol Counter Overflow IRQ 761 IRQSCP = 0; // Compare Unit 3 Compare Match IRQ 762 // SCIRQM 763 IRQMBO = 4; // Backoff Slot Counter IRQ enable 764 IRQMOF = 3; // Symbol Counter Overflow IRQ enable 765 IRQMCP = 0; // Symbol Counter Compare Match 3 IRQ enable 766 // SCSR 767 SCBSY = 0; // Symbol Counter busy 768 // SCCR1 769 SCENBO = 0; // Backoff Slot Counter enable 770 // SCCR0 771 SCRES = 7; // Symbol Counter Synchronization 772 SCMBTS = 6; // Manual Beacon Timestamp 773 SCEN = 5; // Symbol Counter enable 774 SCCKSEL = 4; // Symbol Counter Clock Source select 775 SCTSE = 3; // Symbol Counter Automatic Timestamping enable 776 SCCMP = 0; // Symbol Counter Compare Unit 3 Mode select 777 // EECR 778 EEPM = 4; // EEPROM Programming Mode 779 EERIE = 3; // EEPROM Ready Interrupt Enable 780 EEMPE = 2; // EEPROM Master Write Enable 781 EEPE = 1; // EEPROM Programming Enable 782 EERE = 0; // EEPROM Read Enable 783 // OCDR 784 // MCUCR 785 JTD = 7; // JTAG Interface Disable 786 // MCUSR 787 JTRF = 4; // JTAG Reset Flag 788 // EICRA 789 ISC3 = 6; // External Interrupt 3 Sense Control Bit 790 ISC2 = 4; // External Interrupt 2 Sense Control Bit 791 ISC1 = 2; // External Interrupt 1 Sense Control Bit 792 ISC0 = 0; // External Interrupt 0 Sense Control Bit 793 // EICRB 794 ISC7 = 6; // External Interrupt 7 Sense Control Bit 795 ISC6 = 4; // External Interrupt 6 Sense Control Bit 796 ISC5 = 2; // External Interrupt 5 Sense Control Bit 797 ISC4 = 0; // External Interrupt 4 Sense Control Bit 798 // EIMSK 799 INT = 0; // External Interrupt Request Enable 800 // EIFR 801 INTF = 0; // External Interrupt Flag 802 // PCMSK2 803 PCINT = 0; // Pin Change Enable Mask 804 // PCMSK1 805 // PCIFR 806 PCIF = 0; // Pin Change Interrupt Flags 807 // PCICR 808 PCIE = 0; // Pin Change Interrupt Enables 809 // ADMUX 810 REFS = 6; // Reference Selection Bits 811 ADLAR = 5; // ADC Left Adjust Result 812 MUX = 0; // Analog Channel and Gain Selection Bits 813 // ADCSRA 814 ADEN = 7; // ADC Enable 815 ADSC = 6; // ADC Start Conversion 816 ADATE = 5; // ADC Auto Trigger Enable 817 ADIF = 4; // ADC Interrupt Flag 818 ADIE = 3; // ADC Interrupt Enable 819 ADPS = 0; // ADC Prescaler Select Bits 820 // ADCSRB 821 AVDDOK = 7; // AVDD Supply Voltage OK 822 REFOK = 5; // Reference Voltage OK 823 ACCH = 4; // Analog Channel Change 824 MUX5 = 3; // Analog Channel and Gain Selection Bits 825 ADTS = 0; // ADC Auto Trigger Source 826 // ADCSRC 827 ADTHT = 6; // ADC Track-and-Hold Time 828 Res0 = 5; // Reserved 829 ADSUT = 0; // ADC Start-up Time 830 // DIDR2 831 ADC15D = 7; // Reserved Bits 832 ADC14D = 6; // Reserved Bits 833 ADC13D = 5; // Reserved Bits 834 ADC12D = 4; // Reserved Bits 835 ADC11D = 3; // Reserved Bits 836 ADC10D = 2; // Reserved Bits 837 ADC9D = 1; // Reserved Bits 838 ADC8D = 0; // Reserved Bits 839 // DIDR0 840 ADC7D = 7; // Disable ADC7:0 Digital Input 841 ADC6D = 6; // Disable ADC7:0 Digital Input 842 ADC5D = 5; // Disable ADC7:0 Digital Input 843 ADC4D = 4; // Disable ADC7:0 Digital Input 844 ADC3D = 3; // Disable ADC7:0 Digital Input 845 ADC2D = 2; // Disable ADC7:0 Digital Input 846 ADC1D = 1; // Disable ADC7:0 Digital Input 847 ADC0D = 0; // Disable ADC7:0 Digital Input 848 // SPMCSR 849 SPMIE = 7; // SPM Interrupt Enable 850 RWWSB = 6; // Read While Write Section Busy 851 SIGRD = 5; // Signature Row Read 852 RWWSRE = 4; // Read While Write Section Read Enable 853 BLBSET = 3; // Boot Lock Bit Set 854 PGWRT = 2; // Page Write 855 PGERS = 1; // Page Erase 856 SPMEN = 0; // Store Program Memory Enable 857 // SREG 858 I = 7; // Global Interrupt Enable 859 T = 6; // Bit Copy Storage 860 H = 5; // Half Carry Flag 861 S = 4; // Sign Bit 862 V = 3; // Two's Complement Overflow Flag 863 N = 2; // Negative Flag 864 Z = 1; // Zero Flag 865 C = 0; // Carry Flag 866 // MCUCR 867 PUD = 4; // Pull-up Disable 868 IVSEL = 1; // Interrupt Vector Select 869 IVCE = 0; // Interrupt Vector Change Enable 870 // MCUSR 871 WDRF = 3; // Watchdog Reset Flag 872 BORF = 2; // Brown-out Reset Flag 873 EXTRF = 1; // External Reset Flag 874 PORF = 0; // Power-on Reset Flag 875 // OSCCAL 876 CAL = 0; // Oscillator Calibration Tuning Value 877 // CLKPR 878 CLKPCE = 7; // Clock Prescaler Change Enable 879 CLKPS = 0; // Clock Prescaler Select Bits 880 // SMCR 881 SM = 1; // Sleep Mode Select bits 882 SE = 0; // Sleep Enable 883 // RAMPZ 884 // GPIOR2 885 GPIOR = 0; // General Purpose I/O Register 2 Value 886 // GPIOR1 887 // GPIOR0 888 GPIOR07 = 7; // General Purpose I/O Register 0 Value 889 GPIOR06 = 6; // General Purpose I/O Register 0 Value 890 GPIOR05 = 5; // General Purpose I/O Register 0 Value 891 GPIOR04 = 4; // General Purpose I/O Register 0 Value 892 GPIOR03 = 3; // General Purpose I/O Register 0 Value 893 GPIOR02 = 2; // General Purpose I/O Register 0 Value 894 GPIOR01 = 1; // General Purpose I/O Register 0 Value 895 GPIOR00 = 0; // General Purpose I/O Register 0 Value 896 // PRR2 897 PRRAM = 0; // Power Reduction SRAMs 898 // PRR1 899 PRTRX24 = 6; // Power Reduction Transceiver 900 PRTIM5 = 5; // Power Reduction Timer/Counter5 901 PRTIM4 = 4; // Power Reduction Timer/Counter4 902 PRTIM3 = 3; // Power Reduction Timer/Counter3 903 PRUSART = 0; // Reserved 904 // PRR0 905 PRTWI = 7; // Power Reduction TWI 906 PRTIM2 = 6; // Power Reduction Timer/Counter2 907 PRTIM0 = 5; // Power Reduction Timer/Counter0 908 PRPGA = 4; // Power Reduction PGA 909 PRTIM1 = 3; // Power Reduction Timer/Counter1 910 PRSPI = 2; // Power Reduction Serial Peripheral Interface 911 PRUSART0 = 1; // Power Reduction USART 912 PRADC = 0; // Power Reduction ADC 913 // NEMCR 914 ENEAM = 6; // Enable Extended Address Mode for Extra Rows 915 AEAM = 4; // Address for Extended Address Mode of Extra Rows 916 // BGCR 917 BGCAL_FINE = 3; // Fine Calibration Bits 918 BGCAL = 0; // Coarse Calibration Bits 919 // TRXPR 920 SLPTR = 1; // Multi-purpose Transceiver Control Bit 921 TRXRST = 0; // Force Transceiver Reset 922 // DRTRAM0 923 DRTSWOK = 5; // DRT Switch OK 924 ENDRT = 4; // Enable SRAM Data Retention 925 // DRTRAM1 926 // DRTRAM2 927 // DRTRAM3 928 // LLDRL 929 // LLDRH 930 // LLCR 931 LLDONE = 5; // Calibration Done 932 LLCOMP = 4; // Comparator Output 933 LLCAL = 3; // Calibration Active 934 LLTCO = 2; // Temperature Coefficient of Current Source 935 LLSHORT = 1; // Short Lower Calibration Circuit 936 LLENCAL = 0; // Enable Automatic Calibration 937 // DPDS0 938 PFDRV = 6; // Driver Strength Port F 939 PEDRV = 4; // Driver Strength Port E 940 PDDRV = 2; // Driver Strength Port D 941 PBDRV = 0; // Driver Strength Port B 942 // DPDS1 943 PGDRV = 0; // Driver Strength Port G 944 // MCUCR 945 // UCSR0A 946 // UCSR0B 947 // UCSR0C 948 UDORD0 = 2; // Data Order 949 UCPHA0 = 1; // Clock Phase 950 // UCSR1A 951 // UCSR1B 952 // UCSR1C 953 UDORD1 = 2; // Data Order 954 UCPHA1 = 1; // Clock Phase 955 956implementation 957 958{$i avrcommon.inc} 959 960procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0 961procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1 962procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2 963procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 4 External Interrupt Request 3 964procedure INT4_ISR; external name 'INT4_ISR'; // Interrupt 5 External Interrupt Request 4 965procedure INT5_ISR; external name 'INT5_ISR'; // Interrupt 6 External Interrupt Request 5 966procedure INT6_ISR; external name 'INT6_ISR'; // Interrupt 7 External Interrupt Request 6 967procedure INT7_ISR; external name 'INT7_ISR'; // Interrupt 8 External Interrupt Request 7 968procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 9 Pin Change Interrupt Request 0 969procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 10 Pin Change Interrupt Request 1 970procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 11 Pin Change Interrupt Request 2 971procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-out Interrupt 972procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 13 Timer/Counter2 Compare Match A 973procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 14 Timer/Counter2 Compare Match B 974procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 15 Timer/Counter2 Overflow 975procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 16 Timer/Counter1 Capture Event 976procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 17 Timer/Counter1 Compare Match A 977procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 18 Timer/Counter1 Compare Match B 978procedure TIMER1_COMPC_ISR; external name 'TIMER1_COMPC_ISR'; // Interrupt 19 Timer/Counter1 Compare Match C 979procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 20 Timer/Counter1 Overflow 980procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 21 Timer/Counter0 Compare Match A 981procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 22 Timer/Counter0 Compare Match B 982procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 23 Timer/Counter0 Overflow 983procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 24 SPI Serial Transfer Complete 984procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 25 USART0, Rx Complete 985procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 26 USART0 Data register Empty 986procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 27 USART0, Tx Complete 987procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 28 Analog Comparator 988procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 29 ADC Conversion Complete 989procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 30 EEPROM Ready 990procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event 991procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A 992procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B 993procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C 994procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow 995procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 36 USART1, Rx Complete 996procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 37 USART1 Data register Empty 997procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 38 USART1, Tx Complete 998procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 39 2-wire Serial Interface 999procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 40 Store Program Memory Read 1000procedure TIMER4_CAPT_ISR; external name 'TIMER4_CAPT_ISR'; // Interrupt 41 Timer/Counter4 Capture Event 1001procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 42 Timer/Counter4 Compare Match A 1002procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 43 Timer/Counter4 Compare Match B 1003procedure TIMER4_COMPC_ISR; external name 'TIMER4_COMPC_ISR'; // Interrupt 44 Timer/Counter4 Compare Match C 1004procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 45 Timer/Counter4 Overflow 1005procedure TIMER5_CAPT_ISR; external name 'TIMER5_CAPT_ISR'; // Interrupt 46 Timer/Counter5 Capture Event 1006procedure TIMER5_COMPA_ISR; external name 'TIMER5_COMPA_ISR'; // Interrupt 47 Timer/Counter5 Compare Match A 1007procedure TIMER5_COMPB_ISR; external name 'TIMER5_COMPB_ISR'; // Interrupt 48 Timer/Counter5 Compare Match B 1008procedure TIMER5_COMPC_ISR; external name 'TIMER5_COMPC_ISR'; // Interrupt 49 Timer/Counter5 Compare Match C 1009procedure TIMER5_OVF_ISR; external name 'TIMER5_OVF_ISR'; // Interrupt 50 Timer/Counter5 Overflow 1010procedure USART2_RX_ISR; external name 'USART2_RX_ISR'; // Interrupt 51 USART2, Rx Complete 1011procedure USART2_UDRE_ISR; external name 'USART2_UDRE_ISR'; // Interrupt 52 USART2 Data register Empty 1012procedure USART2_TX_ISR; external name 'USART2_TX_ISR'; // Interrupt 53 USART2, Tx Complete 1013procedure USART3_RX_ISR; external name 'USART3_RX_ISR'; // Interrupt 54 USART3, Rx Complete 1014procedure USART3_UDRE_ISR; external name 'USART3_UDRE_ISR'; // Interrupt 55 USART3 Data register Empty 1015procedure USART3_TX_ISR; external name 'USART3_TX_ISR'; // Interrupt 56 USART3, Tx Complete 1016procedure TRX24_PLL_LOCK_ISR; external name 'TRX24_PLL_LOCK_ISR'; // Interrupt 57 TRX24 - PLL lock interrupt 1017procedure TRX24_PLL_UNLOCK_ISR; external name 'TRX24_PLL_UNLOCK_ISR'; // Interrupt 58 TRX24 - PLL unlock interrupt 1018procedure TRX24_RX_START_ISR; external name 'TRX24_RX_START_ISR'; // Interrupt 59 TRX24 - Receive start interrupt 1019procedure TRX24_RX_END_ISR; external name 'TRX24_RX_END_ISR'; // Interrupt 60 TRX24 - RX_END interrupt 1020procedure TRX24_CCA_ED_DONE_ISR; external name 'TRX24_CCA_ED_DONE_ISR'; // Interrupt 61 TRX24 - CCA/ED done interrupt 1021procedure TRX24_XAH_AMI_ISR; external name 'TRX24_XAH_AMI_ISR'; // Interrupt 62 TRX24 - XAH - AMI 1022procedure TRX24_TX_END_ISR; external name 'TRX24_TX_END_ISR'; // Interrupt 63 TRX24 - TX_END interrupt 1023procedure TRX24_AWAKE_ISR; external name 'TRX24_AWAKE_ISR'; // Interrupt 64 TRX24 AWAKE - tranceiver is reaching state TRX_OFF 1024procedure SCNT_CMP1_ISR; external name 'SCNT_CMP1_ISR'; // Interrupt 65 Symbol counter - compare match 1 interrupt 1025procedure SCNT_CMP2_ISR; external name 'SCNT_CMP2_ISR'; // Interrupt 66 Symbol counter - compare match 2 interrupt 1026procedure SCNT_CMP3_ISR; external name 'SCNT_CMP3_ISR'; // Interrupt 67 Symbol counter - compare match 3 interrupt 1027procedure SCNT_OVFL_ISR; external name 'SCNT_OVFL_ISR'; // Interrupt 68 Symbol counter - overflow interrupt 1028procedure SCNT_BACKOFF_ISR; external name 'SCNT_BACKOFF_ISR'; // Interrupt 69 Symbol counter - backoff interrupt 1029procedure AES_READY_ISR; external name 'AES_READY_ISR'; // Interrupt 70 AES engine ready interrupt 1030procedure BAT_LOW_ISR; external name 'BAT_LOW_ISR'; // Interrupt 71 Battery monitor indicates supply voltage below threshold 1031 1032procedure _FPC_start; assembler; nostackframe; 1033label 1034 _start; 1035 asm 1036 .init 1037 .globl _start 1038 1039 jmp _start 1040 jmp INT0_ISR 1041 jmp INT1_ISR 1042 jmp INT2_ISR 1043 jmp INT3_ISR 1044 jmp INT4_ISR 1045 jmp INT5_ISR 1046 jmp INT6_ISR 1047 jmp INT7_ISR 1048 jmp PCINT0_ISR 1049 jmp PCINT1_ISR 1050 jmp PCINT2_ISR 1051 jmp WDT_ISR 1052 jmp TIMER2_COMPA_ISR 1053 jmp TIMER2_COMPB_ISR 1054 jmp TIMER2_OVF_ISR 1055 jmp TIMER1_CAPT_ISR 1056 jmp TIMER1_COMPA_ISR 1057 jmp TIMER1_COMPB_ISR 1058 jmp TIMER1_COMPC_ISR 1059 jmp TIMER1_OVF_ISR 1060 jmp TIMER0_COMPA_ISR 1061 jmp TIMER0_COMPB_ISR 1062 jmp TIMER0_OVF_ISR 1063 jmp SPI_STC_ISR 1064 jmp USART0_RX_ISR 1065 jmp USART0_UDRE_ISR 1066 jmp USART0_TX_ISR 1067 jmp ANALOG_COMP_ISR 1068 jmp ADC_ISR 1069 jmp EE_READY_ISR 1070 jmp TIMER3_CAPT_ISR 1071 jmp TIMER3_COMPA_ISR 1072 jmp TIMER3_COMPB_ISR 1073 jmp TIMER3_COMPC_ISR 1074 jmp TIMER3_OVF_ISR 1075 jmp USART1_RX_ISR 1076 jmp USART1_UDRE_ISR 1077 jmp USART1_TX_ISR 1078 jmp TWI_ISR 1079 jmp SPM_READY_ISR 1080 jmp TIMER4_CAPT_ISR 1081 jmp TIMER4_COMPA_ISR 1082 jmp TIMER4_COMPB_ISR 1083 jmp TIMER4_COMPC_ISR 1084 jmp TIMER4_OVF_ISR 1085 jmp TIMER5_CAPT_ISR 1086 jmp TIMER5_COMPA_ISR 1087 jmp TIMER5_COMPB_ISR 1088 jmp TIMER5_COMPC_ISR 1089 jmp TIMER5_OVF_ISR 1090 jmp USART2_RX_ISR 1091 jmp USART2_UDRE_ISR 1092 jmp USART2_TX_ISR 1093 jmp USART3_RX_ISR 1094 jmp USART3_UDRE_ISR 1095 jmp USART3_TX_ISR 1096 jmp TRX24_PLL_LOCK_ISR 1097 jmp TRX24_PLL_UNLOCK_ISR 1098 jmp TRX24_RX_START_ISR 1099 jmp TRX24_RX_END_ISR 1100 jmp TRX24_CCA_ED_DONE_ISR 1101 jmp TRX24_XAH_AMI_ISR 1102 jmp TRX24_TX_END_ISR 1103 jmp TRX24_AWAKE_ISR 1104 jmp SCNT_CMP1_ISR 1105 jmp SCNT_CMP2_ISR 1106 jmp SCNT_CMP3_ISR 1107 jmp SCNT_OVFL_ISR 1108 jmp SCNT_BACKOFF_ISR 1109 jmp AES_READY_ISR 1110 jmp BAT_LOW_ISR 1111 1112 {$i start.inc} 1113 1114 .weak INT0_ISR 1115 .weak INT1_ISR 1116 .weak INT2_ISR 1117 .weak INT3_ISR 1118 .weak INT4_ISR 1119 .weak INT5_ISR 1120 .weak INT6_ISR 1121 .weak INT7_ISR 1122 .weak PCINT0_ISR 1123 .weak PCINT1_ISR 1124 .weak PCINT2_ISR 1125 .weak WDT_ISR 1126 .weak TIMER2_COMPA_ISR 1127 .weak TIMER2_COMPB_ISR 1128 .weak TIMER2_OVF_ISR 1129 .weak TIMER1_CAPT_ISR 1130 .weak TIMER1_COMPA_ISR 1131 .weak TIMER1_COMPB_ISR 1132 .weak TIMER1_COMPC_ISR 1133 .weak TIMER1_OVF_ISR 1134 .weak TIMER0_COMPA_ISR 1135 .weak TIMER0_COMPB_ISR 1136 .weak TIMER0_OVF_ISR 1137 .weak SPI_STC_ISR 1138 .weak USART0_RX_ISR 1139 .weak USART0_UDRE_ISR 1140 .weak USART0_TX_ISR 1141 .weak ANALOG_COMP_ISR 1142 .weak ADC_ISR 1143 .weak EE_READY_ISR 1144 .weak TIMER3_CAPT_ISR 1145 .weak TIMER3_COMPA_ISR 1146 .weak TIMER3_COMPB_ISR 1147 .weak TIMER3_COMPC_ISR 1148 .weak TIMER3_OVF_ISR 1149 .weak USART1_RX_ISR 1150 .weak USART1_UDRE_ISR 1151 .weak USART1_TX_ISR 1152 .weak TWI_ISR 1153 .weak SPM_READY_ISR 1154 .weak TIMER4_CAPT_ISR 1155 .weak TIMER4_COMPA_ISR 1156 .weak TIMER4_COMPB_ISR 1157 .weak TIMER4_COMPC_ISR 1158 .weak TIMER4_OVF_ISR 1159 .weak TIMER5_CAPT_ISR 1160 .weak TIMER5_COMPA_ISR 1161 .weak TIMER5_COMPB_ISR 1162 .weak TIMER5_COMPC_ISR 1163 .weak TIMER5_OVF_ISR 1164 .weak USART2_RX_ISR 1165 .weak USART2_UDRE_ISR 1166 .weak USART2_TX_ISR 1167 .weak USART3_RX_ISR 1168 .weak USART3_UDRE_ISR 1169 .weak USART3_TX_ISR 1170 .weak TRX24_PLL_LOCK_ISR 1171 .weak TRX24_PLL_UNLOCK_ISR 1172 .weak TRX24_RX_START_ISR 1173 .weak TRX24_RX_END_ISR 1174 .weak TRX24_CCA_ED_DONE_ISR 1175 .weak TRX24_XAH_AMI_ISR 1176 .weak TRX24_TX_END_ISR 1177 .weak TRX24_AWAKE_ISR 1178 .weak SCNT_CMP1_ISR 1179 .weak SCNT_CMP2_ISR 1180 .weak SCNT_CMP3_ISR 1181 .weak SCNT_OVFL_ISR 1182 .weak SCNT_BACKOFF_ISR 1183 .weak AES_READY_ISR 1184 .weak BAT_LOW_ISR 1185 1186 .set INT0_ISR, Default_IRQ_handler 1187 .set INT1_ISR, Default_IRQ_handler 1188 .set INT2_ISR, Default_IRQ_handler 1189 .set INT3_ISR, Default_IRQ_handler 1190 .set INT4_ISR, Default_IRQ_handler 1191 .set INT5_ISR, Default_IRQ_handler 1192 .set INT6_ISR, Default_IRQ_handler 1193 .set INT7_ISR, Default_IRQ_handler 1194 .set PCINT0_ISR, Default_IRQ_handler 1195 .set PCINT1_ISR, Default_IRQ_handler 1196 .set PCINT2_ISR, Default_IRQ_handler 1197 .set WDT_ISR, Default_IRQ_handler 1198 .set TIMER2_COMPA_ISR, Default_IRQ_handler 1199 .set TIMER2_COMPB_ISR, Default_IRQ_handler 1200 .set TIMER2_OVF_ISR, Default_IRQ_handler 1201 .set TIMER1_CAPT_ISR, Default_IRQ_handler 1202 .set TIMER1_COMPA_ISR, Default_IRQ_handler 1203 .set TIMER1_COMPB_ISR, Default_IRQ_handler 1204 .set TIMER1_COMPC_ISR, Default_IRQ_handler 1205 .set TIMER1_OVF_ISR, Default_IRQ_handler 1206 .set TIMER0_COMPA_ISR, Default_IRQ_handler 1207 .set TIMER0_COMPB_ISR, Default_IRQ_handler 1208 .set TIMER0_OVF_ISR, Default_IRQ_handler 1209 .set SPI_STC_ISR, Default_IRQ_handler 1210 .set USART0_RX_ISR, Default_IRQ_handler 1211 .set USART0_UDRE_ISR, Default_IRQ_handler 1212 .set USART0_TX_ISR, Default_IRQ_handler 1213 .set ANALOG_COMP_ISR, Default_IRQ_handler 1214 .set ADC_ISR, Default_IRQ_handler 1215 .set EE_READY_ISR, Default_IRQ_handler 1216 .set TIMER3_CAPT_ISR, Default_IRQ_handler 1217 .set TIMER3_COMPA_ISR, Default_IRQ_handler 1218 .set TIMER3_COMPB_ISR, Default_IRQ_handler 1219 .set TIMER3_COMPC_ISR, Default_IRQ_handler 1220 .set TIMER3_OVF_ISR, Default_IRQ_handler 1221 .set USART1_RX_ISR, Default_IRQ_handler 1222 .set USART1_UDRE_ISR, Default_IRQ_handler 1223 .set USART1_TX_ISR, Default_IRQ_handler 1224 .set TWI_ISR, Default_IRQ_handler 1225 .set SPM_READY_ISR, Default_IRQ_handler 1226 .set TIMER4_CAPT_ISR, Default_IRQ_handler 1227 .set TIMER4_COMPA_ISR, Default_IRQ_handler 1228 .set TIMER4_COMPB_ISR, Default_IRQ_handler 1229 .set TIMER4_COMPC_ISR, Default_IRQ_handler 1230 .set TIMER4_OVF_ISR, Default_IRQ_handler 1231 .set TIMER5_CAPT_ISR, Default_IRQ_handler 1232 .set TIMER5_COMPA_ISR, Default_IRQ_handler 1233 .set TIMER5_COMPB_ISR, Default_IRQ_handler 1234 .set TIMER5_COMPC_ISR, Default_IRQ_handler 1235 .set TIMER5_OVF_ISR, Default_IRQ_handler 1236 .set USART2_RX_ISR, Default_IRQ_handler 1237 .set USART2_UDRE_ISR, Default_IRQ_handler 1238 .set USART2_TX_ISR, Default_IRQ_handler 1239 .set USART3_RX_ISR, Default_IRQ_handler 1240 .set USART3_UDRE_ISR, Default_IRQ_handler 1241 .set USART3_TX_ISR, Default_IRQ_handler 1242 .set TRX24_PLL_LOCK_ISR, Default_IRQ_handler 1243 .set TRX24_PLL_UNLOCK_ISR, Default_IRQ_handler 1244 .set TRX24_RX_START_ISR, Default_IRQ_handler 1245 .set TRX24_RX_END_ISR, Default_IRQ_handler 1246 .set TRX24_CCA_ED_DONE_ISR, Default_IRQ_handler 1247 .set TRX24_XAH_AMI_ISR, Default_IRQ_handler 1248 .set TRX24_TX_END_ISR, Default_IRQ_handler 1249 .set TRX24_AWAKE_ISR, Default_IRQ_handler 1250 .set SCNT_CMP1_ISR, Default_IRQ_handler 1251 .set SCNT_CMP2_ISR, Default_IRQ_handler 1252 .set SCNT_CMP3_ISR, Default_IRQ_handler 1253 .set SCNT_OVFL_ISR, Default_IRQ_handler 1254 .set SCNT_BACKOFF_ISR, Default_IRQ_handler 1255 .set AES_READY_ISR, Default_IRQ_handler 1256 .set BAT_LOW_ISR, Default_IRQ_handler 1257 end; 1258 1259end. 1260