1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
23
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
29
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
35
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
41
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
44
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
51
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
55
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
64
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
68
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
77
78 #include "config.h"
79 #include "system.h"
80 #include "coretypes.h"
81 #include "backend.h"
82 #include "target.h"
83 #include "rtl.h"
84 #include "tree.h"
85 #include "cfghooks.h"
86 #include "predict.h"
87 #include "df.h"
88 #include "memmodel.h"
89 #include "tm_p.h"
90 #include "optabs.h"
91 #include "regs.h"
92 #include "emit-rtl.h"
93 #include "recog.h"
94 #include "cgraph.h"
95 #include "stor-layout.h"
96 #include "cfgrtl.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
99 #include "explow.h"
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
102 #include "expr.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
107 #include "function-abi.h"
108
109 /* Number of attempts to combine instructions in this function. */
110
111 static int combine_attempts;
112
113 /* Number of attempts that got as far as substitution in this function. */
114
115 static int combine_merges;
116
117 /* Number of instructions combined with added SETs in this function. */
118
119 static int combine_extras;
120
121 /* Number of instructions combined in this function. */
122
123 static int combine_successes;
124
125 /* Totals over entire compilation. */
126
127 static int total_attempts, total_merges, total_extras, total_successes;
128
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
135
136 static rtx_insn *i2mod;
137
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139
140 static rtx i2mod_old_rhs;
141
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143
144 static rtx i2mod_new_rhs;
145
146 struct reg_stat_type {
147 /* Record last point of death of (hard or pseudo) register n. */
148 rtx_insn *last_death;
149
150 /* Record last point of modification of (hard or pseudo) register n. */
151 rtx_insn *last_set;
152
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
158
159 We use an approach similar to that used by cse, but change it in the
160 following ways:
161
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
165
166 Therefore, we maintain the following fields:
167
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
175 register's value
176
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
180 table.
181
182 (The next two parameters are out of date).
183
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
195
196 /* Record last value assigned to (hard or pseudo) register n. */
197
198 rtx last_set_value;
199
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
202
203 int last_set_table_tick;
204
205 /* Record the value of label_tick when the value for register n is placed in
206 last_set_value. */
207
208 int last_set_label;
209
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
214
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
222
223 char last_set_invalid;
224
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
229
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
233 zero.
234
235 If an entry is zero, it means that we don't know anything special. */
236
237 unsigned char sign_bit_copies;
238
239 unsigned HOST_WIDE_INT nonzero_bits;
240
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
244
245 int truncation_label;
246
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
250 value. */
251
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
253 };
254
255
256 static vec<reg_stat_type> reg_stat;
257
258 /* One plus the highest pseudo for which we track REG_N_SETS.
259 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
260 but during combine_split_insns new pseudos can be created. As we don't have
261 updated DF information in that case, it is hard to initialize the array
262 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
263 so instead of growing the arrays, just assume all newly created pseudos
264 during combine might be set multiple times. */
265
266 static unsigned int reg_n_sets_max;
267
268 /* Record the luid of the last insn that invalidated memory
269 (anything that writes memory, and subroutine calls, but not pushes). */
270
271 static int mem_last_set;
272
273 /* Record the luid of the last CALL_INSN
274 so we can tell whether a potential combination crosses any calls. */
275
276 static int last_call_luid;
277
278 /* When `subst' is called, this is the insn that is being modified
279 (by combining in a previous insn). The PATTERN of this insn
280 is still the old pattern partially modified and it should not be
281 looked at, but this may be used to examine the successors of the insn
282 to judge whether a simplification is valid. */
283
284 static rtx_insn *subst_insn;
285
286 /* This is the lowest LUID that `subst' is currently dealing with.
287 get_last_value will not return a value if the register was set at or
288 after this LUID. If not for this mechanism, we could get confused if
289 I2 or I1 in try_combine were an insn that used the old value of a register
290 to obtain a new value. In that case, we might erroneously get the
291 new value of the register when we wanted the old one. */
292
293 static int subst_low_luid;
294
295 /* This contains any hard registers that are used in newpat; reg_dead_at_p
296 must consider all these registers to be always live. */
297
298 static HARD_REG_SET newpat_used_regs;
299
300 /* This is an insn to which a LOG_LINKS entry has been added. If this
301 insn is the earlier than I2 or I3, combine should rescan starting at
302 that location. */
303
304 static rtx_insn *added_links_insn;
305
306 /* And similarly, for notes. */
307
308 static rtx_insn *added_notes_insn;
309
310 /* Basic block in which we are performing combines. */
311 static basic_block this_basic_block;
312 static bool optimize_this_for_speed_p;
313
314
315 /* Length of the currently allocated uid_insn_cost array. */
316
317 static int max_uid_known;
318
319 /* The following array records the insn_cost for every insn
320 in the instruction stream. */
321
322 static int *uid_insn_cost;
323
324 /* The following array records the LOG_LINKS for every insn in the
325 instruction stream as struct insn_link pointers. */
326
327 struct insn_link {
328 rtx_insn *insn;
329 unsigned int regno;
330 struct insn_link *next;
331 };
332
333 static struct insn_link **uid_log_links;
334
335 static inline int
insn_uid_check(const_rtx insn)336 insn_uid_check (const_rtx insn)
337 {
338 int uid = INSN_UID (insn);
339 gcc_checking_assert (uid <= max_uid_known);
340 return uid;
341 }
342
343 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
344 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
345
346 #define FOR_EACH_LOG_LINK(L, INSN) \
347 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
348
349 /* Links for LOG_LINKS are allocated from this obstack. */
350
351 static struct obstack insn_link_obstack;
352
353 /* Allocate a link. */
354
355 static inline struct insn_link *
alloc_insn_link(rtx_insn * insn,unsigned int regno,struct insn_link * next)356 alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
357 {
358 struct insn_link *l
359 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
360 sizeof (struct insn_link));
361 l->insn = insn;
362 l->regno = regno;
363 l->next = next;
364 return l;
365 }
366
367 /* Incremented for each basic block. */
368
369 static int label_tick;
370
371 /* Reset to label_tick for each extended basic block in scanning order. */
372
373 static int label_tick_ebb_start;
374
375 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
376 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
377
378 static scalar_int_mode nonzero_bits_mode;
379
380 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
381 be safely used. It is zero while computing them and after combine has
382 completed. This former test prevents propagating values based on
383 previously set values, which can be incorrect if a variable is modified
384 in a loop. */
385
386 static int nonzero_sign_valid;
387
388
389 /* Record one modification to rtl structure
390 to be undone by storing old_contents into *where. */
391
392 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
393
394 struct undo
395 {
396 struct undo *next;
397 enum undo_kind kind;
398 union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
399 union { rtx *r; int *i; struct insn_link **l; } where;
400 };
401
402 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
403 num_undo says how many are currently recorded.
404
405 other_insn is nonzero if we have modified some other insn in the process
406 of working on subst_insn. It must be verified too. */
407
408 struct undobuf
409 {
410 struct undo *undos;
411 struct undo *frees;
412 rtx_insn *other_insn;
413 };
414
415 static struct undobuf undobuf;
416
417 /* Number of times the pseudo being substituted for
418 was found and replaced. */
419
420 static int n_occurrences;
421
422 static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
423 scalar_int_mode,
424 unsigned HOST_WIDE_INT *);
425 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
426 scalar_int_mode,
427 unsigned int *);
428 static void do_SUBST (rtx *, rtx);
429 static void do_SUBST_INT (int *, int);
430 static void init_reg_last (void);
431 static void setup_incoming_promotions (rtx_insn *);
432 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
433 static int cant_combine_insn_p (rtx_insn *);
434 static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
435 rtx_insn *, rtx_insn *, rtx *, rtx *);
436 static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *);
437 static int contains_muldiv (rtx);
438 static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
439 int *, rtx_insn *);
440 static void undo_all (void);
441 static void undo_commit (void);
442 static rtx *find_split_point (rtx *, rtx_insn *, bool);
443 static rtx subst (rtx, rtx, rtx, int, int, int);
444 static rtx combine_simplify_rtx (rtx, machine_mode, int, int);
445 static rtx simplify_if_then_else (rtx);
446 static rtx simplify_set (rtx);
447 static rtx simplify_logical (rtx);
448 static rtx expand_compound_operation (rtx);
449 static const_rtx expand_field_assignment (const_rtx);
450 static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT,
451 rtx, unsigned HOST_WIDE_INT, int, int, int);
452 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
453 unsigned HOST_WIDE_INT *);
454 static rtx canon_reg_for_combine (rtx, rtx);
455 static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
456 scalar_int_mode, unsigned HOST_WIDE_INT, int);
457 static rtx force_to_mode (rtx, machine_mode,
458 unsigned HOST_WIDE_INT, int);
459 static rtx if_then_else_cond (rtx, rtx *, rtx *);
460 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
461 static int rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
462 static rtx make_field_assignment (rtx);
463 static rtx apply_distributive_law (rtx);
464 static rtx distribute_and_simplify_rtx (rtx, int);
465 static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
466 unsigned HOST_WIDE_INT);
467 static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
468 unsigned HOST_WIDE_INT);
469 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
470 HOST_WIDE_INT, machine_mode, int *);
471 static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
472 static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
473 int);
474 static int recog_for_combine (rtx *, rtx_insn *, rtx *);
475 static rtx gen_lowpart_for_combine (machine_mode, rtx);
476 static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
477 rtx, rtx *);
478 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
479 static void update_table_tick (rtx);
480 static void record_value_for_reg (rtx, rtx_insn *, rtx);
481 static void check_promoted_subreg (rtx_insn *, rtx);
482 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
483 static void record_dead_and_set_regs (rtx_insn *);
484 static int get_last_value_validate (rtx *, rtx_insn *, int, int);
485 static rtx get_last_value (const_rtx);
486 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
487 static int reg_dead_at_p (rtx, rtx_insn *);
488 static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
489 static int reg_bitfield_target_p (rtx, rtx);
490 static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx);
491 static void distribute_links (struct insn_link *);
492 static void mark_used_regs_combine (rtx);
493 static void record_promoted_value (rtx_insn *, rtx);
494 static bool unmentioned_reg_p (rtx, rtx);
495 static void record_truncated_values (rtx *, void *);
496 static bool reg_truncated_to_mode (machine_mode, const_rtx);
497 static rtx gen_lowpart_or_truncate (machine_mode, rtx);
498
499
500 /* It is not safe to use ordinary gen_lowpart in combine.
501 See comments in gen_lowpart_for_combine. */
502 #undef RTL_HOOKS_GEN_LOWPART
503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
504
505 /* Our implementation of gen_lowpart never emits a new pseudo. */
506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
508
509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
511
512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
514
515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
517
518 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
519
520
521 /* Convenience wrapper for the canonicalize_comparison target hook.
522 Target hooks cannot use enum rtx_code. */
523 static inline void
target_canonicalize_comparison(enum rtx_code * code,rtx * op0,rtx * op1,bool op0_preserve_value)524 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
525 bool op0_preserve_value)
526 {
527 int code_int = (int)*code;
528 targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
529 *code = (enum rtx_code)code_int;
530 }
531
532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
533 PATTERN cannot be split. Otherwise, it returns an insn sequence.
534 This is a wrapper around split_insns which ensures that the
535 reg_stat vector is made larger if the splitter creates a new
536 register. */
537
538 static rtx_insn *
combine_split_insns(rtx pattern,rtx_insn * insn)539 combine_split_insns (rtx pattern, rtx_insn *insn)
540 {
541 rtx_insn *ret;
542 unsigned int nregs;
543
544 ret = split_insns (pattern, insn);
545 nregs = max_reg_num ();
546 if (nregs > reg_stat.length ())
547 reg_stat.safe_grow_cleared (nregs);
548 return ret;
549 }
550
551 /* This is used by find_single_use to locate an rtx in LOC that
552 contains exactly one use of DEST, which is typically either a REG
553 or CC0. It returns a pointer to the innermost rtx expression
554 containing DEST. Appearances of DEST that are being used to
555 totally replace it are not counted. */
556
557 static rtx *
find_single_use_1(rtx dest,rtx * loc)558 find_single_use_1 (rtx dest, rtx *loc)
559 {
560 rtx x = *loc;
561 enum rtx_code code = GET_CODE (x);
562 rtx *result = NULL;
563 rtx *this_result;
564 int i;
565 const char *fmt;
566
567 switch (code)
568 {
569 case CONST:
570 case LABEL_REF:
571 case SYMBOL_REF:
572 CASE_CONST_ANY:
573 case CLOBBER:
574 return 0;
575
576 case SET:
577 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
578 of a REG that occupies all of the REG, the insn uses DEST if
579 it is mentioned in the destination or the source. Otherwise, we
580 need just check the source. */
581 if (GET_CODE (SET_DEST (x)) != CC0
582 && GET_CODE (SET_DEST (x)) != PC
583 && !REG_P (SET_DEST (x))
584 && ! (GET_CODE (SET_DEST (x)) == SUBREG
585 && REG_P (SUBREG_REG (SET_DEST (x)))
586 && !read_modify_subreg_p (SET_DEST (x))))
587 break;
588
589 return find_single_use_1 (dest, &SET_SRC (x));
590
591 case MEM:
592 case SUBREG:
593 return find_single_use_1 (dest, &XEXP (x, 0));
594
595 default:
596 break;
597 }
598
599 /* If it wasn't one of the common cases above, check each expression and
600 vector of this code. Look for a unique usage of DEST. */
601
602 fmt = GET_RTX_FORMAT (code);
603 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
604 {
605 if (fmt[i] == 'e')
606 {
607 if (dest == XEXP (x, i)
608 || (REG_P (dest) && REG_P (XEXP (x, i))
609 && REGNO (dest) == REGNO (XEXP (x, i))))
610 this_result = loc;
611 else
612 this_result = find_single_use_1 (dest, &XEXP (x, i));
613
614 if (result == NULL)
615 result = this_result;
616 else if (this_result)
617 /* Duplicate usage. */
618 return NULL;
619 }
620 else if (fmt[i] == 'E')
621 {
622 int j;
623
624 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
625 {
626 if (XVECEXP (x, i, j) == dest
627 || (REG_P (dest)
628 && REG_P (XVECEXP (x, i, j))
629 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
630 this_result = loc;
631 else
632 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
633
634 if (result == NULL)
635 result = this_result;
636 else if (this_result)
637 return NULL;
638 }
639 }
640 }
641
642 return result;
643 }
644
645
646 /* See if DEST, produced in INSN, is used only a single time in the
647 sequel. If so, return a pointer to the innermost rtx expression in which
648 it is used.
649
650 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651
652 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
653 care about REG_DEAD notes or LOG_LINKS.
654
655 Otherwise, we find the single use by finding an insn that has a
656 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
657 only referenced once in that insn, we know that it must be the first
658 and last insn referencing DEST. */
659
660 static rtx *
find_single_use(rtx dest,rtx_insn * insn,rtx_insn ** ploc)661 find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
662 {
663 basic_block bb;
664 rtx_insn *next;
665 rtx *result;
666 struct insn_link *link;
667
668 if (dest == cc0_rtx)
669 {
670 next = NEXT_INSN (insn);
671 if (next == 0
672 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
673 return 0;
674
675 result = find_single_use_1 (dest, &PATTERN (next));
676 if (result && ploc)
677 *ploc = next;
678 return result;
679 }
680
681 if (!REG_P (dest))
682 return 0;
683
684 bb = BLOCK_FOR_INSN (insn);
685 for (next = NEXT_INSN (insn);
686 next && BLOCK_FOR_INSN (next) == bb;
687 next = NEXT_INSN (next))
688 if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
689 {
690 FOR_EACH_LOG_LINK (link, next)
691 if (link->insn == insn && link->regno == REGNO (dest))
692 break;
693
694 if (link)
695 {
696 result = find_single_use_1 (dest, &PATTERN (next));
697 if (ploc)
698 *ploc = next;
699 return result;
700 }
701 }
702
703 return 0;
704 }
705
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
710 the undo table. */
711
712 static void
do_SUBST(rtx * into,rtx newval)713 do_SUBST (rtx *into, rtx newval)
714 {
715 struct undo *buf;
716 rtx oldval = *into;
717
718 if (oldval == newval)
719 return;
720
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
726 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
727 && CONST_INT_P (newval))
728 {
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
731 gcc_assert (INTVAL (newval)
732 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
733
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
740 gcc_assert (!(GET_CODE (oldval) == SUBREG
741 && CONST_INT_P (SUBREG_REG (oldval))));
742 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
743 && CONST_INT_P (XEXP (oldval, 0))));
744 }
745
746 if (undobuf.frees)
747 buf = undobuf.frees, undobuf.frees = buf->next;
748 else
749 buf = XNEW (struct undo);
750
751 buf->kind = UNDO_RTX;
752 buf->where.r = into;
753 buf->old_contents.r = oldval;
754 *into = newval;
755
756 buf->next = undobuf.undos, undobuf.undos = buf;
757 }
758
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
763 not safe. */
764
765 static void
do_SUBST_INT(int * into,int newval)766 do_SUBST_INT (int *into, int newval)
767 {
768 struct undo *buf;
769 int oldval = *into;
770
771 if (oldval == newval)
772 return;
773
774 if (undobuf.frees)
775 buf = undobuf.frees, undobuf.frees = buf->next;
776 else
777 buf = XNEW (struct undo);
778
779 buf->kind = UNDO_INT;
780 buf->where.i = into;
781 buf->old_contents.i = oldval;
782 *into = newval;
783
784 buf->next = undobuf.undos, undobuf.undos = buf;
785 }
786
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
792 well. */
793
794 static void
do_SUBST_MODE(rtx * into,machine_mode newval)795 do_SUBST_MODE (rtx *into, machine_mode newval)
796 {
797 struct undo *buf;
798 machine_mode oldval = GET_MODE (*into);
799
800 if (oldval == newval)
801 return;
802
803 if (undobuf.frees)
804 buf = undobuf.frees, undobuf.frees = buf->next;
805 else
806 buf = XNEW (struct undo);
807
808 buf->kind = UNDO_MODE;
809 buf->where.r = into;
810 buf->old_contents.m = oldval;
811 adjust_reg_mode (*into, newval);
812
813 buf->next = undobuf.undos, undobuf.undos = buf;
814 }
815
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817
818 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819
820 static void
do_SUBST_LINK(struct insn_link ** into,struct insn_link * newval)821 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
822 {
823 struct undo *buf;
824 struct insn_link * oldval = *into;
825
826 if (oldval == newval)
827 return;
828
829 if (undobuf.frees)
830 buf = undobuf.frees, undobuf.frees = buf->next;
831 else
832 buf = XNEW (struct undo);
833
834 buf->kind = UNDO_LINKS;
835 buf->where.l = into;
836 buf->old_contents.l = oldval;
837 *into = newval;
838
839 buf->next = undobuf.undos, undobuf.undos = buf;
840 }
841
842 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843
844 /* Subroutine of try_combine. Determine whether the replacement patterns
845 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
846 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
847 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
848 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
849 of all the instructions can be estimated and the replacements are more
850 expensive than the original sequence. */
851
852 static bool
combine_validate_cost(rtx_insn * i0,rtx_insn * i1,rtx_insn * i2,rtx_insn * i3,rtx newpat,rtx newi2pat,rtx newotherpat)853 combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
854 rtx newpat, rtx newi2pat, rtx newotherpat)
855 {
856 int i0_cost, i1_cost, i2_cost, i3_cost;
857 int new_i2_cost, new_i3_cost;
858 int old_cost, new_cost;
859
860 /* Lookup the original insn_costs. */
861 i2_cost = INSN_COST (i2);
862 i3_cost = INSN_COST (i3);
863
864 if (i1)
865 {
866 i1_cost = INSN_COST (i1);
867 if (i0)
868 {
869 i0_cost = INSN_COST (i0);
870 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
871 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
872 }
873 else
874 {
875 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
876 ? i1_cost + i2_cost + i3_cost : 0);
877 i0_cost = 0;
878 }
879 }
880 else
881 {
882 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
883 i1_cost = i0_cost = 0;
884 }
885
886 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 correct that. */
888 if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2))
889 old_cost -= i1_cost;
890
891
892 /* Calculate the replacement insn_costs. */
893 rtx tmp = PATTERN (i3);
894 PATTERN (i3) = newpat;
895 int tmpi = INSN_CODE (i3);
896 INSN_CODE (i3) = -1;
897 new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
898 PATTERN (i3) = tmp;
899 INSN_CODE (i3) = tmpi;
900 if (newi2pat)
901 {
902 tmp = PATTERN (i2);
903 PATTERN (i2) = newi2pat;
904 tmpi = INSN_CODE (i2);
905 INSN_CODE (i2) = -1;
906 new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
907 PATTERN (i2) = tmp;
908 INSN_CODE (i2) = tmpi;
909 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
910 ? new_i2_cost + new_i3_cost : 0;
911 }
912 else
913 {
914 new_cost = new_i3_cost;
915 new_i2_cost = 0;
916 }
917
918 if (undobuf.other_insn)
919 {
920 int old_other_cost, new_other_cost;
921
922 old_other_cost = INSN_COST (undobuf.other_insn);
923 tmp = PATTERN (undobuf.other_insn);
924 PATTERN (undobuf.other_insn) = newotherpat;
925 tmpi = INSN_CODE (undobuf.other_insn);
926 INSN_CODE (undobuf.other_insn) = -1;
927 new_other_cost = insn_cost (undobuf.other_insn,
928 optimize_this_for_speed_p);
929 PATTERN (undobuf.other_insn) = tmp;
930 INSN_CODE (undobuf.other_insn) = tmpi;
931 if (old_other_cost > 0 && new_other_cost > 0)
932 {
933 old_cost += old_other_cost;
934 new_cost += new_other_cost;
935 }
936 else
937 old_cost = 0;
938 }
939
940 /* Disallow this combination if both new_cost and old_cost are greater than
941 zero, and new_cost is greater than old cost. */
942 int reject = old_cost > 0 && new_cost > old_cost;
943
944 if (dump_file)
945 {
946 fprintf (dump_file, "%s combination of insns ",
947 reject ? "rejecting" : "allowing");
948 if (i0)
949 fprintf (dump_file, "%d, ", INSN_UID (i0));
950 if (i1 && INSN_UID (i1) != INSN_UID (i2))
951 fprintf (dump_file, "%d, ", INSN_UID (i1));
952 fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
953
954 fprintf (dump_file, "original costs ");
955 if (i0)
956 fprintf (dump_file, "%d + ", i0_cost);
957 if (i1 && INSN_UID (i1) != INSN_UID (i2))
958 fprintf (dump_file, "%d + ", i1_cost);
959 fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
960
961 if (newi2pat)
962 fprintf (dump_file, "replacement costs %d + %d = %d\n",
963 new_i2_cost, new_i3_cost, new_cost);
964 else
965 fprintf (dump_file, "replacement cost %d\n", new_cost);
966 }
967
968 if (reject)
969 return false;
970
971 /* Update the uid_insn_cost array with the replacement costs. */
972 INSN_COST (i2) = new_i2_cost;
973 INSN_COST (i3) = new_i3_cost;
974 if (i1)
975 {
976 INSN_COST (i1) = 0;
977 if (i0)
978 INSN_COST (i0) = 0;
979 }
980
981 return true;
982 }
983
984
985 /* Delete any insns that copy a register to itself.
986 Return true if the CFG was changed. */
987
988 static bool
delete_noop_moves(void)989 delete_noop_moves (void)
990 {
991 rtx_insn *insn, *next;
992 basic_block bb;
993
994 bool edges_deleted = false;
995
996 FOR_EACH_BB_FN (bb, cfun)
997 {
998 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
999 {
1000 next = NEXT_INSN (insn);
1001 if (INSN_P (insn) && noop_move_p (insn))
1002 {
1003 if (dump_file)
1004 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
1005
1006 edges_deleted |= delete_insn_and_edges (insn);
1007 }
1008 }
1009 }
1010
1011 return edges_deleted;
1012 }
1013
1014
1015 /* Return false if we do not want to (or cannot) combine DEF. */
1016 static bool
can_combine_def_p(df_ref def)1017 can_combine_def_p (df_ref def)
1018 {
1019 /* Do not consider if it is pre/post modification in MEM. */
1020 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1021 return false;
1022
1023 unsigned int regno = DF_REF_REGNO (def);
1024
1025 /* Do not combine frame pointer adjustments. */
1026 if ((regno == FRAME_POINTER_REGNUM
1027 && (!reload_completed || frame_pointer_needed))
1028 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1029 && regno == HARD_FRAME_POINTER_REGNUM
1030 && (!reload_completed || frame_pointer_needed))
1031 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1032 && regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
1033 return false;
1034
1035 return true;
1036 }
1037
1038 /* Return false if we do not want to (or cannot) combine USE. */
1039 static bool
can_combine_use_p(df_ref use)1040 can_combine_use_p (df_ref use)
1041 {
1042 /* Do not consider the usage of the stack pointer by function call. */
1043 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1044 return false;
1045
1046 return true;
1047 }
1048
1049 /* Fill in log links field for all insns. */
1050
1051 static void
create_log_links(void)1052 create_log_links (void)
1053 {
1054 basic_block bb;
1055 rtx_insn **next_use;
1056 rtx_insn *insn;
1057 df_ref def, use;
1058
1059 next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1060
1061 /* Pass through each block from the end, recording the uses of each
1062 register and establishing log links when def is encountered.
1063 Note that we do not clear next_use array in order to save time,
1064 so we have to test whether the use is in the same basic block as def.
1065
1066 There are a few cases below when we do not consider the definition or
1067 usage -- these are taken from original flow.c did. Don't ask me why it is
1068 done this way; I don't know and if it works, I don't want to know. */
1069
1070 FOR_EACH_BB_FN (bb, cfun)
1071 {
1072 FOR_BB_INSNS_REVERSE (bb, insn)
1073 {
1074 if (!NONDEBUG_INSN_P (insn))
1075 continue;
1076
1077 /* Log links are created only once. */
1078 gcc_assert (!LOG_LINKS (insn));
1079
1080 FOR_EACH_INSN_DEF (def, insn)
1081 {
1082 unsigned int regno = DF_REF_REGNO (def);
1083 rtx_insn *use_insn;
1084
1085 if (!next_use[regno])
1086 continue;
1087
1088 if (!can_combine_def_p (def))
1089 continue;
1090
1091 use_insn = next_use[regno];
1092 next_use[regno] = NULL;
1093
1094 if (BLOCK_FOR_INSN (use_insn) != bb)
1095 continue;
1096
1097 /* flow.c claimed:
1098
1099 We don't build a LOG_LINK for hard registers contained
1100 in ASM_OPERANDs. If these registers get replaced,
1101 we might wind up changing the semantics of the insn,
1102 even if reload can make what appear to be valid
1103 assignments later. */
1104 if (regno < FIRST_PSEUDO_REGISTER
1105 && asm_noperands (PATTERN (use_insn)) >= 0)
1106 continue;
1107
1108 /* Don't add duplicate links between instructions. */
1109 struct insn_link *links;
1110 FOR_EACH_LOG_LINK (links, use_insn)
1111 if (insn == links->insn && regno == links->regno)
1112 break;
1113
1114 if (!links)
1115 LOG_LINKS (use_insn)
1116 = alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1117 }
1118
1119 FOR_EACH_INSN_USE (use, insn)
1120 if (can_combine_use_p (use))
1121 next_use[DF_REF_REGNO (use)] = insn;
1122 }
1123 }
1124
1125 free (next_use);
1126 }
1127
1128 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1129 true if we found a LOG_LINK that proves that A feeds B. This only works
1130 if there are no instructions between A and B which could have a link
1131 depending on A, since in that case we would not record a link for B.
1132 We also check the implicit dependency created by a cc0 setter/user
1133 pair. */
1134
1135 static bool
insn_a_feeds_b(rtx_insn * a,rtx_insn * b)1136 insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1137 {
1138 struct insn_link *links;
1139 FOR_EACH_LOG_LINK (links, b)
1140 if (links->insn == a)
1141 return true;
1142 if (HAVE_cc0 && sets_cc0_p (a))
1143 return true;
1144 return false;
1145 }
1146
1147 /* Main entry point for combiner. F is the first insn of the function.
1148 NREGS is the first unused pseudo-reg number.
1149
1150 Return nonzero if the CFG was changed (e.g. if the combiner has
1151 turned an indirect jump instruction into a direct jump). */
1152 static int
combine_instructions(rtx_insn * f,unsigned int nregs)1153 combine_instructions (rtx_insn *f, unsigned int nregs)
1154 {
1155 rtx_insn *insn, *next;
1156 rtx_insn *prev;
1157 struct insn_link *links, *nextlinks;
1158 rtx_insn *first;
1159 basic_block last_bb;
1160
1161 int new_direct_jump_p = 0;
1162
1163 for (first = f; first && !NONDEBUG_INSN_P (first); )
1164 first = NEXT_INSN (first);
1165 if (!first)
1166 return 0;
1167
1168 combine_attempts = 0;
1169 combine_merges = 0;
1170 combine_extras = 0;
1171 combine_successes = 0;
1172
1173 rtl_hooks = combine_rtl_hooks;
1174
1175 reg_stat.safe_grow_cleared (nregs);
1176
1177 init_recog_no_volatile ();
1178
1179 /* Allocate array for insn info. */
1180 max_uid_known = get_max_uid ();
1181 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1182 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1183 gcc_obstack_init (&insn_link_obstack);
1184
1185 nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();
1186
1187 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1188 problems when, for example, we have j <<= 1 in a loop. */
1189
1190 nonzero_sign_valid = 0;
1191 label_tick = label_tick_ebb_start = 1;
1192
1193 /* Scan all SETs and see if we can deduce anything about what
1194 bits are known to be zero for some registers and how many copies
1195 of the sign bit are known to exist for those registers.
1196
1197 Also set any known values so that we can use it while searching
1198 for what bits are known to be set. */
1199
1200 setup_incoming_promotions (first);
1201 /* Allow the entry block and the first block to fall into the same EBB.
1202 Conceptually the incoming promotions are assigned to the entry block. */
1203 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1204
1205 create_log_links ();
1206 FOR_EACH_BB_FN (this_basic_block, cfun)
1207 {
1208 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1209 last_call_luid = 0;
1210 mem_last_set = -1;
1211
1212 label_tick++;
1213 if (!single_pred_p (this_basic_block)
1214 || single_pred (this_basic_block) != last_bb)
1215 label_tick_ebb_start = label_tick;
1216 last_bb = this_basic_block;
1217
1218 FOR_BB_INSNS (this_basic_block, insn)
1219 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1220 {
1221 rtx links;
1222
1223 subst_low_luid = DF_INSN_LUID (insn);
1224 subst_insn = insn;
1225
1226 note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
1227 record_dead_and_set_regs (insn);
1228
1229 if (AUTO_INC_DEC)
1230 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1231 if (REG_NOTE_KIND (links) == REG_INC)
1232 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1233 insn);
1234
1235 /* Record the current insn_cost of this instruction. */
1236 INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
1237 if (dump_file)
1238 {
1239 fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn));
1240 dump_insn_slim (dump_file, insn);
1241 }
1242 }
1243 }
1244
1245 nonzero_sign_valid = 1;
1246
1247 /* Now scan all the insns in forward order. */
1248 label_tick = label_tick_ebb_start = 1;
1249 init_reg_last ();
1250 setup_incoming_promotions (first);
1251 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1252 int max_combine = param_max_combine_insns;
1253
1254 FOR_EACH_BB_FN (this_basic_block, cfun)
1255 {
1256 rtx_insn *last_combined_insn = NULL;
1257
1258 /* Ignore instruction combination in basic blocks that are going to
1259 be removed as unreachable anyway. See PR82386. */
1260 if (EDGE_COUNT (this_basic_block->preds) == 0)
1261 continue;
1262
1263 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1264 last_call_luid = 0;
1265 mem_last_set = -1;
1266
1267 label_tick++;
1268 if (!single_pred_p (this_basic_block)
1269 || single_pred (this_basic_block) != last_bb)
1270 label_tick_ebb_start = label_tick;
1271 last_bb = this_basic_block;
1272
1273 rtl_profile_for_bb (this_basic_block);
1274 for (insn = BB_HEAD (this_basic_block);
1275 insn != NEXT_INSN (BB_END (this_basic_block));
1276 insn = next ? next : NEXT_INSN (insn))
1277 {
1278 next = 0;
1279 if (!NONDEBUG_INSN_P (insn))
1280 continue;
1281
1282 while (last_combined_insn
1283 && (!NONDEBUG_INSN_P (last_combined_insn)
1284 || last_combined_insn->deleted ()))
1285 last_combined_insn = PREV_INSN (last_combined_insn);
1286 if (last_combined_insn == NULL_RTX
1287 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1288 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1289 last_combined_insn = insn;
1290
1291 /* See if we know about function return values before this
1292 insn based upon SUBREG flags. */
1293 check_promoted_subreg (insn, PATTERN (insn));
1294
1295 /* See if we can find hardregs and subreg of pseudos in
1296 narrower modes. This could help turning TRUNCATEs
1297 into SUBREGs. */
1298 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1299
1300 /* Try this insn with each insn it links back to. */
1301
1302 FOR_EACH_LOG_LINK (links, insn)
1303 if ((next = try_combine (insn, links->insn, NULL,
1304 NULL, &new_direct_jump_p,
1305 last_combined_insn)) != 0)
1306 {
1307 statistics_counter_event (cfun, "two-insn combine", 1);
1308 goto retry;
1309 }
1310
1311 /* Try each sequence of three linked insns ending with this one. */
1312
1313 if (max_combine >= 3)
1314 FOR_EACH_LOG_LINK (links, insn)
1315 {
1316 rtx_insn *link = links->insn;
1317
1318 /* If the linked insn has been replaced by a note, then there
1319 is no point in pursuing this chain any further. */
1320 if (NOTE_P (link))
1321 continue;
1322
1323 FOR_EACH_LOG_LINK (nextlinks, link)
1324 if ((next = try_combine (insn, link, nextlinks->insn,
1325 NULL, &new_direct_jump_p,
1326 last_combined_insn)) != 0)
1327 {
1328 statistics_counter_event (cfun, "three-insn combine", 1);
1329 goto retry;
1330 }
1331 }
1332
1333 /* Try to combine a jump insn that uses CC0
1334 with a preceding insn that sets CC0, and maybe with its
1335 logical predecessor as well.
1336 This is how we make decrement-and-branch insns.
1337 We need this special code because data flow connections
1338 via CC0 do not get entered in LOG_LINKS. */
1339
1340 if (HAVE_cc0
1341 && JUMP_P (insn)
1342 && (prev = prev_nonnote_insn (insn)) != 0
1343 && NONJUMP_INSN_P (prev)
1344 && sets_cc0_p (PATTERN (prev)))
1345 {
1346 if ((next = try_combine (insn, prev, NULL, NULL,
1347 &new_direct_jump_p,
1348 last_combined_insn)) != 0)
1349 goto retry;
1350
1351 FOR_EACH_LOG_LINK (nextlinks, prev)
1352 if ((next = try_combine (insn, prev, nextlinks->insn,
1353 NULL, &new_direct_jump_p,
1354 last_combined_insn)) != 0)
1355 goto retry;
1356 }
1357
1358 /* Do the same for an insn that explicitly references CC0. */
1359 if (HAVE_cc0 && NONJUMP_INSN_P (insn)
1360 && (prev = prev_nonnote_insn (insn)) != 0
1361 && NONJUMP_INSN_P (prev)
1362 && sets_cc0_p (PATTERN (prev))
1363 && GET_CODE (PATTERN (insn)) == SET
1364 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1365 {
1366 if ((next = try_combine (insn, prev, NULL, NULL,
1367 &new_direct_jump_p,
1368 last_combined_insn)) != 0)
1369 goto retry;
1370
1371 FOR_EACH_LOG_LINK (nextlinks, prev)
1372 if ((next = try_combine (insn, prev, nextlinks->insn,
1373 NULL, &new_direct_jump_p,
1374 last_combined_insn)) != 0)
1375 goto retry;
1376 }
1377
1378 /* Finally, see if any of the insns that this insn links to
1379 explicitly references CC0. If so, try this insn, that insn,
1380 and its predecessor if it sets CC0. */
1381 if (HAVE_cc0)
1382 {
1383 FOR_EACH_LOG_LINK (links, insn)
1384 if (NONJUMP_INSN_P (links->insn)
1385 && GET_CODE (PATTERN (links->insn)) == SET
1386 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1387 && (prev = prev_nonnote_insn (links->insn)) != 0
1388 && NONJUMP_INSN_P (prev)
1389 && sets_cc0_p (PATTERN (prev))
1390 && (next = try_combine (insn, links->insn,
1391 prev, NULL, &new_direct_jump_p,
1392 last_combined_insn)) != 0)
1393 goto retry;
1394 }
1395
1396 /* Try combining an insn with two different insns whose results it
1397 uses. */
1398 if (max_combine >= 3)
1399 FOR_EACH_LOG_LINK (links, insn)
1400 for (nextlinks = links->next; nextlinks;
1401 nextlinks = nextlinks->next)
1402 if ((next = try_combine (insn, links->insn,
1403 nextlinks->insn, NULL,
1404 &new_direct_jump_p,
1405 last_combined_insn)) != 0)
1406
1407 {
1408 statistics_counter_event (cfun, "three-insn combine", 1);
1409 goto retry;
1410 }
1411
1412 /* Try four-instruction combinations. */
1413 if (max_combine >= 4)
1414 FOR_EACH_LOG_LINK (links, insn)
1415 {
1416 struct insn_link *next1;
1417 rtx_insn *link = links->insn;
1418
1419 /* If the linked insn has been replaced by a note, then there
1420 is no point in pursuing this chain any further. */
1421 if (NOTE_P (link))
1422 continue;
1423
1424 FOR_EACH_LOG_LINK (next1, link)
1425 {
1426 rtx_insn *link1 = next1->insn;
1427 if (NOTE_P (link1))
1428 continue;
1429 /* I0 -> I1 -> I2 -> I3. */
1430 FOR_EACH_LOG_LINK (nextlinks, link1)
1431 if ((next = try_combine (insn, link, link1,
1432 nextlinks->insn,
1433 &new_direct_jump_p,
1434 last_combined_insn)) != 0)
1435 {
1436 statistics_counter_event (cfun, "four-insn combine", 1);
1437 goto retry;
1438 }
1439 /* I0, I1 -> I2, I2 -> I3. */
1440 for (nextlinks = next1->next; nextlinks;
1441 nextlinks = nextlinks->next)
1442 if ((next = try_combine (insn, link, link1,
1443 nextlinks->insn,
1444 &new_direct_jump_p,
1445 last_combined_insn)) != 0)
1446 {
1447 statistics_counter_event (cfun, "four-insn combine", 1);
1448 goto retry;
1449 }
1450 }
1451
1452 for (next1 = links->next; next1; next1 = next1->next)
1453 {
1454 rtx_insn *link1 = next1->insn;
1455 if (NOTE_P (link1))
1456 continue;
1457 /* I0 -> I2; I1, I2 -> I3. */
1458 FOR_EACH_LOG_LINK (nextlinks, link)
1459 if ((next = try_combine (insn, link, link1,
1460 nextlinks->insn,
1461 &new_direct_jump_p,
1462 last_combined_insn)) != 0)
1463 {
1464 statistics_counter_event (cfun, "four-insn combine", 1);
1465 goto retry;
1466 }
1467 /* I0 -> I1; I1, I2 -> I3. */
1468 FOR_EACH_LOG_LINK (nextlinks, link1)
1469 if ((next = try_combine (insn, link, link1,
1470 nextlinks->insn,
1471 &new_direct_jump_p,
1472 last_combined_insn)) != 0)
1473 {
1474 statistics_counter_event (cfun, "four-insn combine", 1);
1475 goto retry;
1476 }
1477 }
1478 }
1479
1480 /* Try this insn with each REG_EQUAL note it links back to. */
1481 FOR_EACH_LOG_LINK (links, insn)
1482 {
1483 rtx set, note;
1484 rtx_insn *temp = links->insn;
1485 if ((set = single_set (temp)) != 0
1486 && (note = find_reg_equal_equiv_note (temp)) != 0
1487 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1488 && ! side_effects_p (SET_SRC (set))
1489 /* Avoid using a register that may already been marked
1490 dead by an earlier instruction. */
1491 && ! unmentioned_reg_p (note, SET_SRC (set))
1492 && (GET_MODE (note) == VOIDmode
1493 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1494 : (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1495 && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1496 || (GET_MODE (XEXP (SET_DEST (set), 0))
1497 == GET_MODE (note))))))
1498 {
1499 /* Temporarily replace the set's source with the
1500 contents of the REG_EQUAL note. The insn will
1501 be deleted or recognized by try_combine. */
1502 rtx orig_src = SET_SRC (set);
1503 rtx orig_dest = SET_DEST (set);
1504 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1505 SET_DEST (set) = XEXP (SET_DEST (set), 0);
1506 SET_SRC (set) = note;
1507 i2mod = temp;
1508 i2mod_old_rhs = copy_rtx (orig_src);
1509 i2mod_new_rhs = copy_rtx (note);
1510 next = try_combine (insn, i2mod, NULL, NULL,
1511 &new_direct_jump_p,
1512 last_combined_insn);
1513 i2mod = NULL;
1514 if (next)
1515 {
1516 statistics_counter_event (cfun, "insn-with-note combine", 1);
1517 goto retry;
1518 }
1519 SET_SRC (set) = orig_src;
1520 SET_DEST (set) = orig_dest;
1521 }
1522 }
1523
1524 if (!NOTE_P (insn))
1525 record_dead_and_set_regs (insn);
1526
1527 retry:
1528 ;
1529 }
1530 }
1531
1532 default_rtl_profile ();
1533 clear_bb_flags ();
1534 new_direct_jump_p |= purge_all_dead_edges ();
1535 new_direct_jump_p |= delete_noop_moves ();
1536
1537 /* Clean up. */
1538 obstack_free (&insn_link_obstack, NULL);
1539 free (uid_log_links);
1540 free (uid_insn_cost);
1541 reg_stat.release ();
1542
1543 {
1544 struct undo *undo, *next;
1545 for (undo = undobuf.frees; undo; undo = next)
1546 {
1547 next = undo->next;
1548 free (undo);
1549 }
1550 undobuf.frees = 0;
1551 }
1552
1553 total_attempts += combine_attempts;
1554 total_merges += combine_merges;
1555 total_extras += combine_extras;
1556 total_successes += combine_successes;
1557
1558 nonzero_sign_valid = 0;
1559 rtl_hooks = general_rtl_hooks;
1560
1561 /* Make recognizer allow volatile MEMs again. */
1562 init_recog ();
1563
1564 return new_direct_jump_p;
1565 }
1566
1567 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1568
1569 static void
init_reg_last(void)1570 init_reg_last (void)
1571 {
1572 unsigned int i;
1573 reg_stat_type *p;
1574
1575 FOR_EACH_VEC_ELT (reg_stat, i, p)
1576 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1577 }
1578
1579 /* Set up any promoted values for incoming argument registers. */
1580
1581 static void
setup_incoming_promotions(rtx_insn * first)1582 setup_incoming_promotions (rtx_insn *first)
1583 {
1584 tree arg;
1585 bool strictly_local = false;
1586
1587 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1588 arg = DECL_CHAIN (arg))
1589 {
1590 rtx x, reg = DECL_INCOMING_RTL (arg);
1591 int uns1, uns3;
1592 machine_mode mode1, mode2, mode3, mode4;
1593
1594 /* Only continue if the incoming argument is in a register. */
1595 if (!REG_P (reg))
1596 continue;
1597
1598 /* Determine, if possible, whether all call sites of the current
1599 function lie within the current compilation unit. (This does
1600 take into account the exporting of a function via taking its
1601 address, and so forth.) */
1602 strictly_local
1603 = cgraph_node::local_info_node (current_function_decl)->local;
1604
1605 /* The mode and signedness of the argument before any promotions happen
1606 (equal to the mode of the pseudo holding it at that stage). */
1607 mode1 = TYPE_MODE (TREE_TYPE (arg));
1608 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1609
1610 /* The mode and signedness of the argument after any source language and
1611 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1612 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1613 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1614
1615 /* The mode and signedness of the argument as it is actually passed,
1616 see assign_parm_setup_reg in function.c. */
1617 mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1618 TREE_TYPE (cfun->decl), 0);
1619
1620 /* The mode of the register in which the argument is being passed. */
1621 mode4 = GET_MODE (reg);
1622
1623 /* Eliminate sign extensions in the callee when:
1624 (a) A mode promotion has occurred; */
1625 if (mode1 == mode3)
1626 continue;
1627 /* (b) The mode of the register is the same as the mode of
1628 the argument as it is passed; */
1629 if (mode3 != mode4)
1630 continue;
1631 /* (c) There's no language level extension; */
1632 if (mode1 == mode2)
1633 ;
1634 /* (c.1) All callers are from the current compilation unit. If that's
1635 the case we don't have to rely on an ABI, we only have to know
1636 what we're generating right now, and we know that we will do the
1637 mode1 to mode2 promotion with the given sign. */
1638 else if (!strictly_local)
1639 continue;
1640 /* (c.2) The combination of the two promotions is useful. This is
1641 true when the signs match, or if the first promotion is unsigned.
1642 In the later case, (sign_extend (zero_extend x)) is the same as
1643 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1644 else if (uns1)
1645 uns3 = true;
1646 else if (uns3)
1647 continue;
1648
1649 /* Record that the value was promoted from mode1 to mode3,
1650 so that any sign extension at the head of the current
1651 function may be eliminated. */
1652 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1653 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1654 record_value_for_reg (reg, first, x);
1655 }
1656 }
1657
1658 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1659 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1660 because some machines (maybe most) will actually do the sign-extension and
1661 this is the conservative approach.
1662
1663 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1664 kludge. */
1665
1666 static rtx
sign_extend_short_imm(rtx src,machine_mode mode,unsigned int prec)1667 sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1668 {
1669 scalar_int_mode int_mode;
1670 if (CONST_INT_P (src)
1671 && is_a <scalar_int_mode> (mode, &int_mode)
1672 && GET_MODE_PRECISION (int_mode) < prec
1673 && INTVAL (src) > 0
1674 && val_signbit_known_set_p (int_mode, INTVAL (src)))
1675 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode));
1676
1677 return src;
1678 }
1679
1680 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1681 and SET. */
1682
1683 static void
update_rsp_from_reg_equal(reg_stat_type * rsp,rtx_insn * insn,const_rtx set,rtx x)1684 update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1685 rtx x)
1686 {
1687 rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1688 unsigned HOST_WIDE_INT bits = 0;
1689 rtx reg_equal = NULL, src = SET_SRC (set);
1690 unsigned int num = 0;
1691
1692 if (reg_equal_note)
1693 reg_equal = XEXP (reg_equal_note, 0);
1694
1695 if (SHORT_IMMEDIATES_SIGN_EXTEND)
1696 {
1697 src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1698 if (reg_equal)
1699 reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
1700 }
1701
1702 /* Don't call nonzero_bits if it cannot change anything. */
1703 if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
1704 {
1705 machine_mode mode = GET_MODE (x);
1706 if (GET_MODE_CLASS (mode) == MODE_INT
1707 && HWI_COMPUTABLE_MODE_P (mode))
1708 mode = nonzero_bits_mode;
1709 bits = nonzero_bits (src, mode);
1710 if (reg_equal && bits)
1711 bits &= nonzero_bits (reg_equal, mode);
1712 rsp->nonzero_bits |= bits;
1713 }
1714
1715 /* Don't call num_sign_bit_copies if it cannot change anything. */
1716 if (rsp->sign_bit_copies != 1)
1717 {
1718 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1719 if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x))))
1720 {
1721 unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1722 if (num == 0 || numeq > num)
1723 num = numeq;
1724 }
1725 if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1726 rsp->sign_bit_copies = num;
1727 }
1728 }
1729
1730 /* Called via note_stores. If X is a pseudo that is narrower than
1731 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1732
1733 If we are setting only a portion of X and we can't figure out what
1734 portion, assume all bits will be used since we don't know what will
1735 be happening.
1736
1737 Similarly, set how many bits of X are known to be copies of the sign bit
1738 at all locations in the function. This is the smallest number implied
1739 by any set of X. */
1740
1741 static void
set_nonzero_bits_and_sign_copies(rtx x,const_rtx set,void * data)1742 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1743 {
1744 rtx_insn *insn = (rtx_insn *) data;
1745 scalar_int_mode mode;
1746
1747 if (REG_P (x)
1748 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1749 /* If this register is undefined at the start of the file, we can't
1750 say what its contents were. */
1751 && ! REGNO_REG_SET_P
1752 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1753 && is_a <scalar_int_mode> (GET_MODE (x), &mode)
1754 && HWI_COMPUTABLE_MODE_P (mode))
1755 {
1756 reg_stat_type *rsp = ®_stat[REGNO (x)];
1757
1758 if (set == 0 || GET_CODE (set) == CLOBBER)
1759 {
1760 rsp->nonzero_bits = GET_MODE_MASK (mode);
1761 rsp->sign_bit_copies = 1;
1762 return;
1763 }
1764
1765 /* If this register is being initialized using itself, and the
1766 register is uninitialized in this basic block, and there are
1767 no LOG_LINKS which set the register, then part of the
1768 register is uninitialized. In that case we can't assume
1769 anything about the number of nonzero bits.
1770
1771 ??? We could do better if we checked this in
1772 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1773 could avoid making assumptions about the insn which initially
1774 sets the register, while still using the information in other
1775 insns. We would have to be careful to check every insn
1776 involved in the combination. */
1777
1778 if (insn
1779 && reg_referenced_p (x, PATTERN (insn))
1780 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1781 REGNO (x)))
1782 {
1783 struct insn_link *link;
1784
1785 FOR_EACH_LOG_LINK (link, insn)
1786 if (dead_or_set_p (link->insn, x))
1787 break;
1788 if (!link)
1789 {
1790 rsp->nonzero_bits = GET_MODE_MASK (mode);
1791 rsp->sign_bit_copies = 1;
1792 return;
1793 }
1794 }
1795
1796 /* If this is a complex assignment, see if we can convert it into a
1797 simple assignment. */
1798 set = expand_field_assignment (set);
1799
1800 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1801 set what we know about X. */
1802
1803 if (SET_DEST (set) == x
1804 || (paradoxical_subreg_p (SET_DEST (set))
1805 && SUBREG_REG (SET_DEST (set)) == x))
1806 update_rsp_from_reg_equal (rsp, insn, set, x);
1807 else
1808 {
1809 rsp->nonzero_bits = GET_MODE_MASK (mode);
1810 rsp->sign_bit_copies = 1;
1811 }
1812 }
1813 }
1814
1815 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1816 optionally insns that were previously combined into I3 or that will be
1817 combined into the merger of INSN and I3. The order is PRED, PRED2,
1818 INSN, SUCC, SUCC2, I3.
1819
1820 Return 0 if the combination is not allowed for any reason.
1821
1822 If the combination is allowed, *PDEST will be set to the single
1823 destination of INSN and *PSRC to the single source, and this function
1824 will return 1. */
1825
1826 static int
can_combine_p(rtx_insn * insn,rtx_insn * i3,rtx_insn * pred ATTRIBUTE_UNUSED,rtx_insn * pred2 ATTRIBUTE_UNUSED,rtx_insn * succ,rtx_insn * succ2,rtx * pdest,rtx * psrc)1827 can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1828 rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1829 rtx *pdest, rtx *psrc)
1830 {
1831 int i;
1832 const_rtx set = 0;
1833 rtx src, dest;
1834 rtx_insn *p;
1835 rtx link;
1836 bool all_adjacent = true;
1837 int (*is_volatile_p) (const_rtx);
1838
1839 if (succ)
1840 {
1841 if (succ2)
1842 {
1843 if (next_active_insn (succ2) != i3)
1844 all_adjacent = false;
1845 if (next_active_insn (succ) != succ2)
1846 all_adjacent = false;
1847 }
1848 else if (next_active_insn (succ) != i3)
1849 all_adjacent = false;
1850 if (next_active_insn (insn) != succ)
1851 all_adjacent = false;
1852 }
1853 else if (next_active_insn (insn) != i3)
1854 all_adjacent = false;
1855
1856 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1857 or a PARALLEL consisting of such a SET and CLOBBERs.
1858
1859 If INSN has CLOBBER parallel parts, ignore them for our processing.
1860 By definition, these happen during the execution of the insn. When it
1861 is merged with another insn, all bets are off. If they are, in fact,
1862 needed and aren't also supplied in I3, they may be added by
1863 recog_for_combine. Otherwise, it won't match.
1864
1865 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1866 note.
1867
1868 Get the source and destination of INSN. If more than one, can't
1869 combine. */
1870
1871 if (GET_CODE (PATTERN (insn)) == SET)
1872 set = PATTERN (insn);
1873 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1874 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1875 {
1876 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1877 {
1878 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1879
1880 switch (GET_CODE (elt))
1881 {
1882 /* This is important to combine floating point insns
1883 for the SH4 port. */
1884 case USE:
1885 /* Combining an isolated USE doesn't make sense.
1886 We depend here on combinable_i3pat to reject them. */
1887 /* The code below this loop only verifies that the inputs of
1888 the SET in INSN do not change. We call reg_set_between_p
1889 to verify that the REG in the USE does not change between
1890 I3 and INSN.
1891 If the USE in INSN was for a pseudo register, the matching
1892 insn pattern will likely match any register; combining this
1893 with any other USE would only be safe if we knew that the
1894 used registers have identical values, or if there was
1895 something to tell them apart, e.g. different modes. For
1896 now, we forgo such complicated tests and simply disallow
1897 combining of USES of pseudo registers with any other USE. */
1898 if (REG_P (XEXP (elt, 0))
1899 && GET_CODE (PATTERN (i3)) == PARALLEL)
1900 {
1901 rtx i3pat = PATTERN (i3);
1902 int i = XVECLEN (i3pat, 0) - 1;
1903 unsigned int regno = REGNO (XEXP (elt, 0));
1904
1905 do
1906 {
1907 rtx i3elt = XVECEXP (i3pat, 0, i);
1908
1909 if (GET_CODE (i3elt) == USE
1910 && REG_P (XEXP (i3elt, 0))
1911 && (REGNO (XEXP (i3elt, 0)) == regno
1912 ? reg_set_between_p (XEXP (elt, 0),
1913 PREV_INSN (insn), i3)
1914 : regno >= FIRST_PSEUDO_REGISTER))
1915 return 0;
1916 }
1917 while (--i >= 0);
1918 }
1919 break;
1920
1921 /* We can ignore CLOBBERs. */
1922 case CLOBBER:
1923 break;
1924
1925 case SET:
1926 /* Ignore SETs whose result isn't used but not those that
1927 have side-effects. */
1928 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1929 && insn_nothrow_p (insn)
1930 && !side_effects_p (elt))
1931 break;
1932
1933 /* If we have already found a SET, this is a second one and
1934 so we cannot combine with this insn. */
1935 if (set)
1936 return 0;
1937
1938 set = elt;
1939 break;
1940
1941 default:
1942 /* Anything else means we can't combine. */
1943 return 0;
1944 }
1945 }
1946
1947 if (set == 0
1948 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1949 so don't do anything with it. */
1950 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1951 return 0;
1952 }
1953 else
1954 return 0;
1955
1956 if (set == 0)
1957 return 0;
1958
1959 /* The simplification in expand_field_assignment may call back to
1960 get_last_value, so set safe guard here. */
1961 subst_low_luid = DF_INSN_LUID (insn);
1962
1963 set = expand_field_assignment (set);
1964 src = SET_SRC (set), dest = SET_DEST (set);
1965
1966 /* Do not eliminate user-specified register if it is in an
1967 asm input because we may break the register asm usage defined
1968 in GCC manual if allow to do so.
1969 Be aware that this may cover more cases than we expect but this
1970 should be harmless. */
1971 if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1972 && extract_asm_operands (PATTERN (i3)))
1973 return 0;
1974
1975 /* Don't eliminate a store in the stack pointer. */
1976 if (dest == stack_pointer_rtx
1977 /* Don't combine with an insn that sets a register to itself if it has
1978 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1979 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1980 /* Can't merge an ASM_OPERANDS. */
1981 || GET_CODE (src) == ASM_OPERANDS
1982 /* Can't merge a function call. */
1983 || GET_CODE (src) == CALL
1984 /* Don't eliminate a function call argument. */
1985 || (CALL_P (i3)
1986 && (find_reg_fusage (i3, USE, dest)
1987 || (REG_P (dest)
1988 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1989 && global_regs[REGNO (dest)])))
1990 /* Don't substitute into an incremented register. */
1991 || FIND_REG_INC_NOTE (i3, dest)
1992 || (succ && FIND_REG_INC_NOTE (succ, dest))
1993 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1994 /* Don't substitute into a non-local goto, this confuses CFG. */
1995 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1996 /* Make sure that DEST is not used after INSN but before SUCC, or
1997 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1998 || (!all_adjacent
1999 && ((succ2
2000 && (reg_used_between_p (dest, succ2, i3)
2001 || reg_used_between_p (dest, succ, succ2)))
2002 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))
2003 || (!succ2 && !succ && reg_used_between_p (dest, insn, i3))
2004 || (succ
2005 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
2006 that case SUCC is not in the insn stream, so use SUCC2
2007 instead for this test. */
2008 && reg_used_between_p (dest, insn,
2009 succ2
2010 && INSN_UID (succ) == INSN_UID (succ2)
2011 ? succ2 : succ))))
2012 /* Make sure that the value that is to be substituted for the register
2013 does not use any registers whose values alter in between. However,
2014 If the insns are adjacent, a use can't cross a set even though we
2015 think it might (this can happen for a sequence of insns each setting
2016 the same destination; last_set of that register might point to
2017 a NOTE). If INSN has a REG_EQUIV note, the register is always
2018 equivalent to the memory so the substitution is valid even if there
2019 are intervening stores. Also, don't move a volatile asm or
2020 UNSPEC_VOLATILE across any other insns. */
2021 || (! all_adjacent
2022 && (((!MEM_P (src)
2023 || ! find_reg_note (insn, REG_EQUIV, src))
2024 && modified_between_p (src, insn, i3))
2025 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
2026 || GET_CODE (src) == UNSPEC_VOLATILE))
2027 /* Don't combine across a CALL_INSN, because that would possibly
2028 change whether the life span of some REGs crosses calls or not,
2029 and it is a pain to update that information.
2030 Exception: if source is a constant, moving it later can't hurt.
2031 Accept that as a special case. */
2032 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
2033 return 0;
2034
2035 /* DEST must either be a REG or CC0. */
2036 if (REG_P (dest))
2037 {
2038 /* If register alignment is being enforced for multi-word items in all
2039 cases except for parameters, it is possible to have a register copy
2040 insn referencing a hard register that is not allowed to contain the
2041 mode being copied and which would not be valid as an operand of most
2042 insns. Eliminate this problem by not combining with such an insn.
2043
2044 Also, on some machines we don't want to extend the life of a hard
2045 register. */
2046
2047 if (REG_P (src)
2048 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
2049 && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
2050 /* Don't extend the life of a hard register unless it is
2051 user variable (if we have few registers) or it can't
2052 fit into the desired register (meaning something special
2053 is going on).
2054 Also avoid substituting a return register into I3, because
2055 reload can't handle a conflict with constraints of other
2056 inputs. */
2057 || (REGNO (src) < FIRST_PSEUDO_REGISTER
2058 && !targetm.hard_regno_mode_ok (REGNO (src),
2059 GET_MODE (src)))))
2060 return 0;
2061 }
2062 else if (GET_CODE (dest) != CC0)
2063 return 0;
2064
2065
2066 if (GET_CODE (PATTERN (i3)) == PARALLEL)
2067 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
2068 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
2069 {
2070 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
2071
2072 /* If the clobber represents an earlyclobber operand, we must not
2073 substitute an expression containing the clobbered register.
2074 As we do not analyze the constraint strings here, we have to
2075 make the conservative assumption. However, if the register is
2076 a fixed hard reg, the clobber cannot represent any operand;
2077 we leave it up to the machine description to either accept or
2078 reject use-and-clobber patterns. */
2079 if (!REG_P (reg)
2080 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
2081 || !fixed_regs[REGNO (reg)])
2082 if (reg_overlap_mentioned_p (reg, src))
2083 return 0;
2084 }
2085
2086 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2087 or not), reject, unless nothing volatile comes between it and I3 */
2088
2089 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
2090 {
2091 /* Make sure neither succ nor succ2 contains a volatile reference. */
2092 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
2093 return 0;
2094 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
2095 return 0;
2096 /* We'll check insns between INSN and I3 below. */
2097 }
2098
2099 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2100 to be an explicit register variable, and was chosen for a reason. */
2101
2102 if (GET_CODE (src) == ASM_OPERANDS
2103 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2104 return 0;
2105
2106 /* If INSN contains volatile references (specifically volatile MEMs),
2107 we cannot combine across any other volatile references.
2108 Even if INSN doesn't contain volatile references, any intervening
2109 volatile insn might affect machine state. */
2110
2111 is_volatile_p = volatile_refs_p (PATTERN (insn))
2112 ? volatile_refs_p
2113 : volatile_insn_p;
2114
2115 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2116 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2117 return 0;
2118
2119 /* If INSN contains an autoincrement or autodecrement, make sure that
2120 register is not used between there and I3, and not already used in
2121 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2122 Also insist that I3 not be a jump if using LRA; if it were one
2123 and the incremented register were spilled, we would lose.
2124 Reload handles this correctly. */
2125
2126 if (AUTO_INC_DEC)
2127 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2128 if (REG_NOTE_KIND (link) == REG_INC
2129 && ((JUMP_P (i3) && targetm.lra_p ())
2130 || reg_used_between_p (XEXP (link, 0), insn, i3)
2131 || (pred != NULL_RTX
2132 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2133 || (pred2 != NULL_RTX
2134 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2135 || (succ != NULL_RTX
2136 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2137 || (succ2 != NULL_RTX
2138 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2139 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2140 return 0;
2141
2142 /* Don't combine an insn that follows a CC0-setting insn.
2143 An insn that uses CC0 must not be separated from the one that sets it.
2144 We do, however, allow I2 to follow a CC0-setting insn if that insn
2145 is passed as I1; in that case it will be deleted also.
2146 We also allow combining in this case if all the insns are adjacent
2147 because that would leave the two CC0 insns adjacent as well.
2148 It would be more logical to test whether CC0 occurs inside I1 or I2,
2149 but that would be much slower, and this ought to be equivalent. */
2150
2151 if (HAVE_cc0)
2152 {
2153 p = prev_nonnote_insn (insn);
2154 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2155 && ! all_adjacent)
2156 return 0;
2157 }
2158
2159 /* If we get here, we have passed all the tests and the combination is
2160 to be allowed. */
2161
2162 *pdest = dest;
2163 *psrc = src;
2164
2165 return 1;
2166 }
2167
2168 /* LOC is the location within I3 that contains its pattern or the component
2169 of a PARALLEL of the pattern. We validate that it is valid for combining.
2170
2171 One problem is if I3 modifies its output, as opposed to replacing it
2172 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2173 doing so would produce an insn that is not equivalent to the original insns.
2174
2175 Consider:
2176
2177 (set (reg:DI 101) (reg:DI 100))
2178 (set (subreg:SI (reg:DI 101) 0) <foo>)
2179
2180 This is NOT equivalent to:
2181
2182 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2183 (set (reg:DI 101) (reg:DI 100))])
2184
2185 Not only does this modify 100 (in which case it might still be valid
2186 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2187
2188 We can also run into a problem if I2 sets a register that I1
2189 uses and I1 gets directly substituted into I3 (not via I2). In that
2190 case, we would be getting the wrong value of I2DEST into I3, so we
2191 must reject the combination. This case occurs when I2 and I1 both
2192 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2193 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2194 of a SET must prevent combination from occurring. The same situation
2195 can occur for I0, in which case I0_NOT_IN_SRC is set.
2196
2197 Before doing the above check, we first try to expand a field assignment
2198 into a set of logical operations.
2199
2200 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2201 we place a register that is both set and used within I3. If more than one
2202 such register is detected, we fail.
2203
2204 Return 1 if the combination is valid, zero otherwise. */
2205
2206 static int
combinable_i3pat(rtx_insn * i3,rtx * loc,rtx i2dest,rtx i1dest,rtx i0dest,int i1_not_in_src,int i0_not_in_src,rtx * pi3dest_killed)2207 combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2208 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2209 {
2210 rtx x = *loc;
2211
2212 if (GET_CODE (x) == SET)
2213 {
2214 rtx set = x ;
2215 rtx dest = SET_DEST (set);
2216 rtx src = SET_SRC (set);
2217 rtx inner_dest = dest;
2218 rtx subdest;
2219
2220 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2221 || GET_CODE (inner_dest) == SUBREG
2222 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2223 inner_dest = XEXP (inner_dest, 0);
2224
2225 /* Check for the case where I3 modifies its output, as discussed
2226 above. We don't want to prevent pseudos from being combined
2227 into the address of a MEM, so only prevent the combination if
2228 i1 or i2 set the same MEM. */
2229 if ((inner_dest != dest &&
2230 (!MEM_P (inner_dest)
2231 || rtx_equal_p (i2dest, inner_dest)
2232 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2233 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2234 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2235 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2236 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2237
2238 /* This is the same test done in can_combine_p except we can't test
2239 all_adjacent; we don't have to, since this instruction will stay
2240 in place, thus we are not considering increasing the lifetime of
2241 INNER_DEST.
2242
2243 Also, if this insn sets a function argument, combining it with
2244 something that might need a spill could clobber a previous
2245 function argument; the all_adjacent test in can_combine_p also
2246 checks this; here, we do a more specific test for this case. */
2247
2248 || (REG_P (inner_dest)
2249 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2250 && !targetm.hard_regno_mode_ok (REGNO (inner_dest),
2251 GET_MODE (inner_dest)))
2252 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2253 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2254 return 0;
2255
2256 /* If DEST is used in I3, it is being killed in this insn, so
2257 record that for later. We have to consider paradoxical
2258 subregs here, since they kill the whole register, but we
2259 ignore partial subregs, STRICT_LOW_PART, etc.
2260 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2261 STACK_POINTER_REGNUM, since these are always considered to be
2262 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2263 subdest = dest;
2264 if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
2265 subdest = SUBREG_REG (subdest);
2266 if (pi3dest_killed
2267 && REG_P (subdest)
2268 && reg_referenced_p (subdest, PATTERN (i3))
2269 && REGNO (subdest) != FRAME_POINTER_REGNUM
2270 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2271 || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2272 && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2273 || (REGNO (subdest) != ARG_POINTER_REGNUM
2274 || ! fixed_regs [REGNO (subdest)]))
2275 && REGNO (subdest) != STACK_POINTER_REGNUM)
2276 {
2277 if (*pi3dest_killed)
2278 return 0;
2279
2280 *pi3dest_killed = subdest;
2281 }
2282 }
2283
2284 else if (GET_CODE (x) == PARALLEL)
2285 {
2286 int i;
2287
2288 for (i = 0; i < XVECLEN (x, 0); i++)
2289 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2290 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2291 return 0;
2292 }
2293
2294 return 1;
2295 }
2296
2297 /* Return 1 if X is an arithmetic expression that contains a multiplication
2298 and division. We don't count multiplications by powers of two here. */
2299
2300 static int
contains_muldiv(rtx x)2301 contains_muldiv (rtx x)
2302 {
2303 switch (GET_CODE (x))
2304 {
2305 case MOD: case DIV: case UMOD: case UDIV:
2306 return 1;
2307
2308 case MULT:
2309 return ! (CONST_INT_P (XEXP (x, 1))
2310 && pow2p_hwi (UINTVAL (XEXP (x, 1))));
2311 default:
2312 if (BINARY_P (x))
2313 return contains_muldiv (XEXP (x, 0))
2314 || contains_muldiv (XEXP (x, 1));
2315
2316 if (UNARY_P (x))
2317 return contains_muldiv (XEXP (x, 0));
2318
2319 return 0;
2320 }
2321 }
2322
2323 /* Determine whether INSN can be used in a combination. Return nonzero if
2324 not. This is used in try_combine to detect early some cases where we
2325 can't perform combinations. */
2326
2327 static int
cant_combine_insn_p(rtx_insn * insn)2328 cant_combine_insn_p (rtx_insn *insn)
2329 {
2330 rtx set;
2331 rtx src, dest;
2332
2333 /* If this isn't really an insn, we can't do anything.
2334 This can occur when flow deletes an insn that it has merged into an
2335 auto-increment address. */
2336 if (!NONDEBUG_INSN_P (insn))
2337 return 1;
2338
2339 /* Never combine loads and stores involving hard regs that are likely
2340 to be spilled. The register allocator can usually handle such
2341 reg-reg moves by tying. If we allow the combiner to make
2342 substitutions of likely-spilled regs, reload might die.
2343 As an exception, we allow combinations involving fixed regs; these are
2344 not available to the register allocator so there's no risk involved. */
2345
2346 set = single_set (insn);
2347 if (! set)
2348 return 0;
2349 src = SET_SRC (set);
2350 dest = SET_DEST (set);
2351 if (GET_CODE (src) == SUBREG)
2352 src = SUBREG_REG (src);
2353 if (GET_CODE (dest) == SUBREG)
2354 dest = SUBREG_REG (dest);
2355 if (REG_P (src) && REG_P (dest)
2356 && ((HARD_REGISTER_P (src)
2357 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2358 #ifdef LEAF_REGISTERS
2359 && ! LEAF_REGISTERS [REGNO (src)])
2360 #else
2361 )
2362 #endif
2363 || (HARD_REGISTER_P (dest)
2364 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2365 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2366 return 1;
2367
2368 return 0;
2369 }
2370
2371 struct likely_spilled_retval_info
2372 {
2373 unsigned regno, nregs;
2374 unsigned mask;
2375 };
2376
2377 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2378 hard registers that are known to be written to / clobbered in full. */
2379 static void
likely_spilled_retval_1(rtx x,const_rtx set,void * data)2380 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2381 {
2382 struct likely_spilled_retval_info *const info =
2383 (struct likely_spilled_retval_info *) data;
2384 unsigned regno, nregs;
2385 unsigned new_mask;
2386
2387 if (!REG_P (XEXP (set, 0)))
2388 return;
2389 regno = REGNO (x);
2390 if (regno >= info->regno + info->nregs)
2391 return;
2392 nregs = REG_NREGS (x);
2393 if (regno + nregs <= info->regno)
2394 return;
2395 new_mask = (2U << (nregs - 1)) - 1;
2396 if (regno < info->regno)
2397 new_mask >>= info->regno - regno;
2398 else
2399 new_mask <<= regno - info->regno;
2400 info->mask &= ~new_mask;
2401 }
2402
2403 /* Return nonzero iff part of the return value is live during INSN, and
2404 it is likely spilled. This can happen when more than one insn is needed
2405 to copy the return value, e.g. when we consider to combine into the
2406 second copy insn for a complex value. */
2407
2408 static int
likely_spilled_retval_p(rtx_insn * insn)2409 likely_spilled_retval_p (rtx_insn *insn)
2410 {
2411 rtx_insn *use = BB_END (this_basic_block);
2412 rtx reg;
2413 rtx_insn *p;
2414 unsigned regno, nregs;
2415 /* We assume here that no machine mode needs more than
2416 32 hard registers when the value overlaps with a register
2417 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2418 unsigned mask;
2419 struct likely_spilled_retval_info info;
2420
2421 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2422 return 0;
2423 reg = XEXP (PATTERN (use), 0);
2424 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2425 return 0;
2426 regno = REGNO (reg);
2427 nregs = REG_NREGS (reg);
2428 if (nregs == 1)
2429 return 0;
2430 mask = (2U << (nregs - 1)) - 1;
2431
2432 /* Disregard parts of the return value that are set later. */
2433 info.regno = regno;
2434 info.nregs = nregs;
2435 info.mask = mask;
2436 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2437 if (INSN_P (p))
2438 note_stores (p, likely_spilled_retval_1, &info);
2439 mask = info.mask;
2440
2441 /* Check if any of the (probably) live return value registers is
2442 likely spilled. */
2443 nregs --;
2444 do
2445 {
2446 if ((mask & 1 << nregs)
2447 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2448 return 1;
2449 } while (nregs--);
2450 return 0;
2451 }
2452
2453 /* Adjust INSN after we made a change to its destination.
2454
2455 Changing the destination can invalidate notes that say something about
2456 the results of the insn and a LOG_LINK pointing to the insn. */
2457
2458 static void
adjust_for_new_dest(rtx_insn * insn)2459 adjust_for_new_dest (rtx_insn *insn)
2460 {
2461 /* For notes, be conservative and simply remove them. */
2462 remove_reg_equal_equiv_notes (insn);
2463
2464 /* The new insn will have a destination that was previously the destination
2465 of an insn just above it. Call distribute_links to make a LOG_LINK from
2466 the next use of that destination. */
2467
2468 rtx set = single_set (insn);
2469 gcc_assert (set);
2470
2471 rtx reg = SET_DEST (set);
2472
2473 while (GET_CODE (reg) == ZERO_EXTRACT
2474 || GET_CODE (reg) == STRICT_LOW_PART
2475 || GET_CODE (reg) == SUBREG)
2476 reg = XEXP (reg, 0);
2477 gcc_assert (REG_P (reg));
2478
2479 distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2480
2481 df_insn_rescan (insn);
2482 }
2483
2484 /* Return TRUE if combine can reuse reg X in mode MODE.
2485 ADDED_SETS is nonzero if the original set is still required. */
2486 static bool
can_change_dest_mode(rtx x,int added_sets,machine_mode mode)2487 can_change_dest_mode (rtx x, int added_sets, machine_mode mode)
2488 {
2489 unsigned int regno;
2490
2491 if (!REG_P (x))
2492 return false;
2493
2494 /* Don't change between modes with different underlying register sizes,
2495 since this could lead to invalid subregs. */
2496 if (maybe_ne (REGMODE_NATURAL_SIZE (mode),
2497 REGMODE_NATURAL_SIZE (GET_MODE (x))))
2498 return false;
2499
2500 regno = REGNO (x);
2501 /* Allow hard registers if the new mode is legal, and occupies no more
2502 registers than the old mode. */
2503 if (regno < FIRST_PSEUDO_REGISTER)
2504 return (targetm.hard_regno_mode_ok (regno, mode)
2505 && REG_NREGS (x) >= hard_regno_nregs (regno, mode));
2506
2507 /* Or a pseudo that is only used once. */
2508 return (regno < reg_n_sets_max
2509 && REG_N_SETS (regno) == 1
2510 && !added_sets
2511 && !REG_USERVAR_P (x));
2512 }
2513
2514
2515 /* Check whether X, the destination of a set, refers to part of
2516 the register specified by REG. */
2517
2518 static bool
reg_subword_p(rtx x,rtx reg)2519 reg_subword_p (rtx x, rtx reg)
2520 {
2521 /* Check that reg is an integer mode register. */
2522 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2523 return false;
2524
2525 if (GET_CODE (x) == STRICT_LOW_PART
2526 || GET_CODE (x) == ZERO_EXTRACT)
2527 x = XEXP (x, 0);
2528
2529 return GET_CODE (x) == SUBREG
2530 && SUBREG_REG (x) == reg
2531 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2532 }
2533
2534 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2535 Note that the INSN should be deleted *after* removing dead edges, so
2536 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2537 but not for a (set (pc) (label_ref FOO)). */
2538
2539 static void
update_cfg_for_uncondjump(rtx_insn * insn)2540 update_cfg_for_uncondjump (rtx_insn *insn)
2541 {
2542 basic_block bb = BLOCK_FOR_INSN (insn);
2543 gcc_assert (BB_END (bb) == insn);
2544
2545 purge_dead_edges (bb);
2546
2547 delete_insn (insn);
2548 if (EDGE_COUNT (bb->succs) == 1)
2549 {
2550 rtx_insn *insn;
2551
2552 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2553
2554 /* Remove barriers from the footer if there are any. */
2555 for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2556 if (BARRIER_P (insn))
2557 {
2558 if (PREV_INSN (insn))
2559 SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2560 else
2561 BB_FOOTER (bb) = NEXT_INSN (insn);
2562 if (NEXT_INSN (insn))
2563 SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2564 }
2565 else if (LABEL_P (insn))
2566 break;
2567 }
2568 }
2569
2570 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2571 by an arbitrary number of CLOBBERs. */
2572 static bool
is_parallel_of_n_reg_sets(rtx pat,int n)2573 is_parallel_of_n_reg_sets (rtx pat, int n)
2574 {
2575 if (GET_CODE (pat) != PARALLEL)
2576 return false;
2577
2578 int len = XVECLEN (pat, 0);
2579 if (len < n)
2580 return false;
2581
2582 int i;
2583 for (i = 0; i < n; i++)
2584 if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2585 || !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2586 return false;
2587 for ( ; i < len; i++)
2588 switch (GET_CODE (XVECEXP (pat, 0, i)))
2589 {
2590 case CLOBBER:
2591 if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2592 return false;
2593 break;
2594 default:
2595 return false;
2596 }
2597 return true;
2598 }
2599
2600 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2601 CLOBBERs), can be split into individual SETs in that order, without
2602 changing semantics. */
2603 static bool
can_split_parallel_of_n_reg_sets(rtx_insn * insn,int n)2604 can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2605 {
2606 if (!insn_nothrow_p (insn))
2607 return false;
2608
2609 rtx pat = PATTERN (insn);
2610
2611 int i, j;
2612 for (i = 0; i < n; i++)
2613 {
2614 if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2615 return false;
2616
2617 rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2618
2619 for (j = i + 1; j < n; j++)
2620 if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2621 return false;
2622 }
2623
2624 return true;
2625 }
2626
2627 /* Return whether X is just a single set, with the source
2628 a general_operand. */
2629 static bool
is_just_move(rtx x)2630 is_just_move (rtx x)
2631 {
2632 if (INSN_P (x))
2633 x = PATTERN (x);
2634
2635 return (GET_CODE (x) == SET && general_operand (SET_SRC (x), VOIDmode));
2636 }
2637
2638 /* Callback function to count autoincs. */
2639
2640 static int
count_auto_inc(rtx,rtx,rtx,rtx,rtx,void * arg)2641 count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
2642 {
2643 (*((int *) arg))++;
2644
2645 return 0;
2646 }
2647
2648 /* Try to combine the insns I0, I1 and I2 into I3.
2649 Here I0, I1 and I2 appear earlier than I3.
2650 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2651 I3.
2652
2653 If we are combining more than two insns and the resulting insn is not
2654 recognized, try splitting it into two insns. If that happens, I2 and I3
2655 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2656 Otherwise, I0, I1 and I2 are pseudo-deleted.
2657
2658 Return 0 if the combination does not work. Then nothing is changed.
2659 If we did the combination, return the insn at which combine should
2660 resume scanning.
2661
2662 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2663 new direct jump instruction.
2664
2665 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2666 been I3 passed to an earlier try_combine within the same basic
2667 block. */
2668
2669 static rtx_insn *
try_combine(rtx_insn * i3,rtx_insn * i2,rtx_insn * i1,rtx_insn * i0,int * new_direct_jump_p,rtx_insn * last_combined_insn)2670 try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2671 int *new_direct_jump_p, rtx_insn *last_combined_insn)
2672 {
2673 /* New patterns for I3 and I2, respectively. */
2674 rtx newpat, newi2pat = 0;
2675 rtvec newpat_vec_with_clobbers = 0;
2676 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2677 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2678 dead. */
2679 int added_sets_0, added_sets_1, added_sets_2;
2680 /* Total number of SETs to put into I3. */
2681 int total_sets;
2682 /* Nonzero if I2's or I1's body now appears in I3. */
2683 int i2_is_used = 0, i1_is_used = 0;
2684 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2685 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2686 /* Contains I3 if the destination of I3 is used in its source, which means
2687 that the old life of I3 is being killed. If that usage is placed into
2688 I2 and not in I3, a REG_DEAD note must be made. */
2689 rtx i3dest_killed = 0;
2690 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2691 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2692 /* Copy of SET_SRC of I1 and I0, if needed. */
2693 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2694 /* Set if I2DEST was reused as a scratch register. */
2695 bool i2scratch = false;
2696 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2697 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2698 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2699 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2700 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2701 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2702 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2703 /* Notes that must be added to REG_NOTES in I3 and I2. */
2704 rtx new_i3_notes, new_i2_notes;
2705 /* Notes that we substituted I3 into I2 instead of the normal case. */
2706 int i3_subst_into_i2 = 0;
2707 /* Notes that I1, I2 or I3 is a MULT operation. */
2708 int have_mult = 0;
2709 int swap_i2i3 = 0;
2710 int split_i2i3 = 0;
2711 int changed_i3_dest = 0;
2712 bool i2_was_move = false, i3_was_move = false;
2713 int n_auto_inc = 0;
2714
2715 int maxreg;
2716 rtx_insn *temp_insn;
2717 rtx temp_expr;
2718 struct insn_link *link;
2719 rtx other_pat = 0;
2720 rtx new_other_notes;
2721 int i;
2722 scalar_int_mode dest_mode, temp_mode;
2723
2724 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2725 never be). */
2726 if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2727 return 0;
2728
2729 /* Only try four-insn combinations when there's high likelihood of
2730 success. Look for simple insns, such as loads of constants or
2731 binary operations involving a constant. */
2732 if (i0)
2733 {
2734 int i;
2735 int ngood = 0;
2736 int nshift = 0;
2737 rtx set0, set3;
2738
2739 if (!flag_expensive_optimizations)
2740 return 0;
2741
2742 for (i = 0; i < 4; i++)
2743 {
2744 rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2745 rtx set = single_set (insn);
2746 rtx src;
2747 if (!set)
2748 continue;
2749 src = SET_SRC (set);
2750 if (CONSTANT_P (src))
2751 {
2752 ngood += 2;
2753 break;
2754 }
2755 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2756 ngood++;
2757 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2758 || GET_CODE (src) == LSHIFTRT)
2759 nshift++;
2760 }
2761
2762 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2763 are likely manipulating its value. Ideally we'll be able to combine
2764 all four insns into a bitfield insertion of some kind.
2765
2766 Note the source in I0 might be inside a sign/zero extension and the
2767 memory modes in I0 and I3 might be different. So extract the address
2768 from the destination of I3 and search for it in the source of I0.
2769
2770 In the event that there's a match but the source/dest do not actually
2771 refer to the same memory, the worst that happens is we try some
2772 combinations that we wouldn't have otherwise. */
2773 if ((set0 = single_set (i0))
2774 /* Ensure the source of SET0 is a MEM, possibly buried inside
2775 an extension. */
2776 && (GET_CODE (SET_SRC (set0)) == MEM
2777 || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2778 || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2779 && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2780 && (set3 = single_set (i3))
2781 /* Ensure the destination of SET3 is a MEM. */
2782 && GET_CODE (SET_DEST (set3)) == MEM
2783 /* Would it be better to extract the base address for the MEM
2784 in SET3 and look for that? I don't have cases where it matters
2785 but I could envision such cases. */
2786 && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2787 ngood += 2;
2788
2789 if (ngood < 2 && nshift < 2)
2790 return 0;
2791 }
2792
2793 /* Exit early if one of the insns involved can't be used for
2794 combinations. */
2795 if (CALL_P (i2)
2796 || (i1 && CALL_P (i1))
2797 || (i0 && CALL_P (i0))
2798 || cant_combine_insn_p (i3)
2799 || cant_combine_insn_p (i2)
2800 || (i1 && cant_combine_insn_p (i1))
2801 || (i0 && cant_combine_insn_p (i0))
2802 || likely_spilled_retval_p (i3))
2803 return 0;
2804
2805 combine_attempts++;
2806 undobuf.other_insn = 0;
2807
2808 /* Reset the hard register usage information. */
2809 CLEAR_HARD_REG_SET (newpat_used_regs);
2810
2811 if (dump_file && (dump_flags & TDF_DETAILS))
2812 {
2813 if (i0)
2814 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2815 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2816 else if (i1)
2817 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2818 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2819 else
2820 fprintf (dump_file, "\nTrying %d -> %d:\n",
2821 INSN_UID (i2), INSN_UID (i3));
2822
2823 if (i0)
2824 dump_insn_slim (dump_file, i0);
2825 if (i1)
2826 dump_insn_slim (dump_file, i1);
2827 dump_insn_slim (dump_file, i2);
2828 dump_insn_slim (dump_file, i3);
2829 }
2830
2831 /* If multiple insns feed into one of I2 or I3, they can be in any
2832 order. To simplify the code below, reorder them in sequence. */
2833 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2834 std::swap (i0, i2);
2835 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2836 std::swap (i0, i1);
2837 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2838 std::swap (i1, i2);
2839
2840 added_links_insn = 0;
2841 added_notes_insn = 0;
2842
2843 /* First check for one important special case that the code below will
2844 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2845 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2846 we may be able to replace that destination with the destination of I3.
2847 This occurs in the common code where we compute both a quotient and
2848 remainder into a structure, in which case we want to do the computation
2849 directly into the structure to avoid register-register copies.
2850
2851 Note that this case handles both multiple sets in I2 and also cases
2852 where I2 has a number of CLOBBERs inside the PARALLEL.
2853
2854 We make very conservative checks below and only try to handle the
2855 most common cases of this. For example, we only handle the case
2856 where I2 and I3 are adjacent to avoid making difficult register
2857 usage tests. */
2858
2859 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2860 && REG_P (SET_SRC (PATTERN (i3)))
2861 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2862 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2863 && GET_CODE (PATTERN (i2)) == PARALLEL
2864 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2865 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2866 below would need to check what is inside (and reg_overlap_mentioned_p
2867 doesn't support those codes anyway). Don't allow those destinations;
2868 the resulting insn isn't likely to be recognized anyway. */
2869 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2870 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2871 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2872 SET_DEST (PATTERN (i3)))
2873 && next_active_insn (i2) == i3)
2874 {
2875 rtx p2 = PATTERN (i2);
2876
2877 /* Make sure that the destination of I3,
2878 which we are going to substitute into one output of I2,
2879 is not used within another output of I2. We must avoid making this:
2880 (parallel [(set (mem (reg 69)) ...)
2881 (set (reg 69) ...)])
2882 which is not well-defined as to order of actions.
2883 (Besides, reload can't handle output reloads for this.)
2884
2885 The problem can also happen if the dest of I3 is a memory ref,
2886 if another dest in I2 is an indirect memory ref.
2887
2888 Neither can this PARALLEL be an asm. We do not allow combining
2889 that usually (see can_combine_p), so do not here either. */
2890 bool ok = true;
2891 for (i = 0; ok && i < XVECLEN (p2, 0); i++)
2892 {
2893 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2894 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2895 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2896 SET_DEST (XVECEXP (p2, 0, i))))
2897 ok = false;
2898 else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2899 && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2900 ok = false;
2901 }
2902
2903 if (ok)
2904 for (i = 0; i < XVECLEN (p2, 0); i++)
2905 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2906 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2907 {
2908 combine_merges++;
2909
2910 subst_insn = i3;
2911 subst_low_luid = DF_INSN_LUID (i2);
2912
2913 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2914 i2src = SET_SRC (XVECEXP (p2, 0, i));
2915 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2916 i2dest_killed = dead_or_set_p (i2, i2dest);
2917
2918 /* Replace the dest in I2 with our dest and make the resulting
2919 insn the new pattern for I3. Then skip to where we validate
2920 the pattern. Everything was set up above. */
2921 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2922 newpat = p2;
2923 i3_subst_into_i2 = 1;
2924 goto validate_replacement;
2925 }
2926 }
2927
2928 /* If I2 is setting a pseudo to a constant and I3 is setting some
2929 sub-part of it to another constant, merge them by making a new
2930 constant. */
2931 if (i1 == 0
2932 && (temp_expr = single_set (i2)) != 0
2933 && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), &temp_mode)
2934 && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2935 && GET_CODE (PATTERN (i3)) == SET
2936 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2937 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2938 {
2939 rtx dest = SET_DEST (PATTERN (i3));
2940 rtx temp_dest = SET_DEST (temp_expr);
2941 int offset = -1;
2942 int width = 0;
2943
2944 if (GET_CODE (dest) == ZERO_EXTRACT)
2945 {
2946 if (CONST_INT_P (XEXP (dest, 1))
2947 && CONST_INT_P (XEXP (dest, 2))
2948 && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)),
2949 &dest_mode))
2950 {
2951 width = INTVAL (XEXP (dest, 1));
2952 offset = INTVAL (XEXP (dest, 2));
2953 dest = XEXP (dest, 0);
2954 if (BITS_BIG_ENDIAN)
2955 offset = GET_MODE_PRECISION (dest_mode) - width - offset;
2956 }
2957 }
2958 else
2959 {
2960 if (GET_CODE (dest) == STRICT_LOW_PART)
2961 dest = XEXP (dest, 0);
2962 if (is_a <scalar_int_mode> (GET_MODE (dest), &dest_mode))
2963 {
2964 width = GET_MODE_PRECISION (dest_mode);
2965 offset = 0;
2966 }
2967 }
2968
2969 if (offset >= 0)
2970 {
2971 /* If this is the low part, we're done. */
2972 if (subreg_lowpart_p (dest))
2973 ;
2974 /* Handle the case where inner is twice the size of outer. */
2975 else if (GET_MODE_PRECISION (temp_mode)
2976 == 2 * GET_MODE_PRECISION (dest_mode))
2977 offset += GET_MODE_PRECISION (dest_mode);
2978 /* Otherwise give up for now. */
2979 else
2980 offset = -1;
2981 }
2982
2983 if (offset >= 0)
2984 {
2985 rtx inner = SET_SRC (PATTERN (i3));
2986 rtx outer = SET_SRC (temp_expr);
2987
2988 wide_int o = wi::insert (rtx_mode_t (outer, temp_mode),
2989 rtx_mode_t (inner, dest_mode),
2990 offset, width);
2991
2992 combine_merges++;
2993 subst_insn = i3;
2994 subst_low_luid = DF_INSN_LUID (i2);
2995 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2996 i2dest = temp_dest;
2997 i2dest_killed = dead_or_set_p (i2, i2dest);
2998
2999 /* Replace the source in I2 with the new constant and make the
3000 resulting insn the new pattern for I3. Then skip to where we
3001 validate the pattern. Everything was set up above. */
3002 SUBST (SET_SRC (temp_expr),
3003 immed_wide_int_const (o, temp_mode));
3004
3005 newpat = PATTERN (i2);
3006
3007 /* The dest of I3 has been replaced with the dest of I2. */
3008 changed_i3_dest = 1;
3009 goto validate_replacement;
3010 }
3011 }
3012
3013 /* If we have no I1 and I2 looks like:
3014 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
3015 (set Y OP)])
3016 make up a dummy I1 that is
3017 (set Y OP)
3018 and change I2 to be
3019 (set (reg:CC X) (compare:CC Y (const_int 0)))
3020
3021 (We can ignore any trailing CLOBBERs.)
3022
3023 This undoes a previous combination and allows us to match a branch-and-
3024 decrement insn. */
3025
3026 if (!HAVE_cc0 && i1 == 0
3027 && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
3028 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
3029 == MODE_CC)
3030 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
3031 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
3032 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
3033 SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
3034 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
3035 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
3036 {
3037 /* We make I1 with the same INSN_UID as I2. This gives it
3038 the same DF_INSN_LUID for value tracking. Our fake I1 will
3039 never appear in the insn stream so giving it the same INSN_UID
3040 as I2 will not cause a problem. */
3041
3042 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
3043 XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
3044 -1, NULL_RTX);
3045 INSN_UID (i1) = INSN_UID (i2);
3046
3047 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
3048 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
3049 SET_DEST (PATTERN (i1)));
3050 unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
3051 SUBST_LINK (LOG_LINKS (i2),
3052 alloc_insn_link (i1, regno, LOG_LINKS (i2)));
3053 }
3054
3055 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3056 make those two SETs separate I1 and I2 insns, and make an I0 that is
3057 the original I1. */
3058 if (!HAVE_cc0 && i0 == 0
3059 && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
3060 && can_split_parallel_of_n_reg_sets (i2, 2)
3061 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
3062 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
3063 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
3064 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
3065 {
3066 /* If there is no I1, there is no I0 either. */
3067 i0 = i1;
3068
3069 /* We make I1 with the same INSN_UID as I2. This gives it
3070 the same DF_INSN_LUID for value tracking. Our fake I1 will
3071 never appear in the insn stream so giving it the same INSN_UID
3072 as I2 will not cause a problem. */
3073
3074 i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
3075 XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2),
3076 -1, NULL_RTX);
3077 INSN_UID (i1) = INSN_UID (i2);
3078
3079 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
3080 }
3081
3082 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3083 if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src))
3084 {
3085 if (dump_file && (dump_flags & TDF_DETAILS))
3086 fprintf (dump_file, "Can't combine i2 into i3\n");
3087 undo_all ();
3088 return 0;
3089 }
3090 if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src))
3091 {
3092 if (dump_file && (dump_flags & TDF_DETAILS))
3093 fprintf (dump_file, "Can't combine i1 into i3\n");
3094 undo_all ();
3095 return 0;
3096 }
3097 if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src))
3098 {
3099 if (dump_file && (dump_flags & TDF_DETAILS))
3100 fprintf (dump_file, "Can't combine i0 into i3\n");
3101 undo_all ();
3102 return 0;
3103 }
3104
3105 /* Record whether i2 and i3 are trivial moves. */
3106 i2_was_move = is_just_move (i2);
3107 i3_was_move = is_just_move (i3);
3108
3109 /* Record whether I2DEST is used in I2SRC and similarly for the other
3110 cases. Knowing this will help in register status updating below. */
3111 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
3112 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
3113 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
3114 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
3115 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
3116 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
3117 i2dest_killed = dead_or_set_p (i2, i2dest);
3118 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
3119 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
3120
3121 /* For the earlier insns, determine which of the subsequent ones they
3122 feed. */
3123 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
3124 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
3125 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
3126 : (!reg_overlap_mentioned_p (i1dest, i0dest)
3127 && reg_overlap_mentioned_p (i0dest, i2src))));
3128
3129 /* Ensure that I3's pattern can be the destination of combines. */
3130 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
3131 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3132 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3133 || (i1dest_in_i0src && !i0_feeds_i1_n)),
3134 &i3dest_killed))
3135 {
3136 undo_all ();
3137 return 0;
3138 }
3139
3140 /* See if any of the insns is a MULT operation. Unless one is, we will
3141 reject a combination that is, since it must be slower. Be conservative
3142 here. */
3143 if (GET_CODE (i2src) == MULT
3144 || (i1 != 0 && GET_CODE (i1src) == MULT)
3145 || (i0 != 0 && GET_CODE (i0src) == MULT)
3146 || (GET_CODE (PATTERN (i3)) == SET
3147 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3148 have_mult = 1;
3149
3150 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3151 We used to do this EXCEPT in one case: I3 has a post-inc in an
3152 output operand. However, that exception can give rise to insns like
3153 mov r3,(r3)+
3154 which is a famous insn on the PDP-11 where the value of r3 used as the
3155 source was model-dependent. Avoid this sort of thing. */
3156
3157 #if 0
3158 if (!(GET_CODE (PATTERN (i3)) == SET
3159 && REG_P (SET_SRC (PATTERN (i3)))
3160 && MEM_P (SET_DEST (PATTERN (i3)))
3161 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3162 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3163 /* It's not the exception. */
3164 #endif
3165 if (AUTO_INC_DEC)
3166 {
3167 rtx link;
3168 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3169 if (REG_NOTE_KIND (link) == REG_INC
3170 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
3171 || (i1 != 0
3172 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
3173 {
3174 undo_all ();
3175 return 0;
3176 }
3177 }
3178
3179 /* See if the SETs in I1 or I2 need to be kept around in the merged
3180 instruction: whenever the value set there is still needed past I3.
3181 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3182
3183 For the SET in I1, we have two cases: if I1 and I2 independently feed
3184 into I3, the set in I1 needs to be kept around unless I1DEST dies
3185 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3186 in I1 needs to be kept around unless I1DEST dies or is set in either
3187 I2 or I3. The same considerations apply to I0. */
3188
3189 added_sets_2 = !dead_or_set_p (i3, i2dest);
3190
3191 if (i1)
3192 added_sets_1 = !(dead_or_set_p (i3, i1dest)
3193 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3194 else
3195 added_sets_1 = 0;
3196
3197 if (i0)
3198 added_sets_0 = !(dead_or_set_p (i3, i0dest)
3199 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3200 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3201 && dead_or_set_p (i2, i0dest)));
3202 else
3203 added_sets_0 = 0;
3204
3205 /* We are about to copy insns for the case where they need to be kept
3206 around. Check that they can be copied in the merged instruction. */
3207
3208 if (targetm.cannot_copy_insn_p
3209 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3210 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3211 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3212 {
3213 undo_all ();
3214 return 0;
3215 }
3216
3217 /* We cannot safely duplicate volatile references in any case. */
3218
3219 if ((added_sets_2 && volatile_refs_p (PATTERN (i2)))
3220 || (added_sets_1 && volatile_refs_p (PATTERN (i1)))
3221 || (added_sets_0 && volatile_refs_p (PATTERN (i0))))
3222 {
3223 undo_all ();
3224 return 0;
3225 }
3226
3227 /* Count how many auto_inc expressions there were in the original insns;
3228 we need to have the same number in the resulting patterns. */
3229
3230 if (i0)
3231 for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc);
3232 if (i1)
3233 for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc);
3234 for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc);
3235 for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc);
3236
3237 /* If the set in I2 needs to be kept around, we must make a copy of
3238 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3239 PATTERN (I2), we are only substituting for the original I1DEST, not into
3240 an already-substituted copy. This also prevents making self-referential
3241 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3242 I2DEST. */
3243
3244 if (added_sets_2)
3245 {
3246 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3247 i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3248 else
3249 i2pat = copy_rtx (PATTERN (i2));
3250 }
3251
3252 if (added_sets_1)
3253 {
3254 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3255 i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3256 else
3257 i1pat = copy_rtx (PATTERN (i1));
3258 }
3259
3260 if (added_sets_0)
3261 {
3262 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3263 i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3264 else
3265 i0pat = copy_rtx (PATTERN (i0));
3266 }
3267
3268 combine_merges++;
3269
3270 /* Substitute in the latest insn for the regs set by the earlier ones. */
3271
3272 maxreg = max_reg_num ();
3273
3274 subst_insn = i3;
3275
3276 /* Many machines that don't use CC0 have insns that can both perform an
3277 arithmetic operation and set the condition code. These operations will
3278 be represented as a PARALLEL with the first element of the vector
3279 being a COMPARE of an arithmetic operation with the constant zero.
3280 The second element of the vector will set some pseudo to the result
3281 of the same arithmetic operation. If we simplify the COMPARE, we won't
3282 match such a pattern and so will generate an extra insn. Here we test
3283 for this case, where both the comparison and the operation result are
3284 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3285 I2SRC. Later we will make the PARALLEL that contains I2. */
3286
3287 if (!HAVE_cc0 && i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3288 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3289 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3290 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3291 {
3292 rtx newpat_dest;
3293 rtx *cc_use_loc = NULL;
3294 rtx_insn *cc_use_insn = NULL;
3295 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3296 machine_mode compare_mode, orig_compare_mode;
3297 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3298 scalar_int_mode mode;
3299
3300 newpat = PATTERN (i3);
3301 newpat_dest = SET_DEST (newpat);
3302 compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3303
3304 if (undobuf.other_insn == 0
3305 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3306 &cc_use_insn)))
3307 {
3308 compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3309 if (is_a <scalar_int_mode> (GET_MODE (i2dest), &mode))
3310 compare_code = simplify_compare_const (compare_code, mode,
3311 op0, &op1);
3312 target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
3313 }
3314
3315 /* Do the rest only if op1 is const0_rtx, which may be the
3316 result of simplification. */
3317 if (op1 == const0_rtx)
3318 {
3319 /* If a single use of the CC is found, prepare to modify it
3320 when SELECT_CC_MODE returns a new CC-class mode, or when
3321 the above simplify_compare_const() returned a new comparison
3322 operator. undobuf.other_insn is assigned the CC use insn
3323 when modifying it. */
3324 if (cc_use_loc)
3325 {
3326 #ifdef SELECT_CC_MODE
3327 machine_mode new_mode
3328 = SELECT_CC_MODE (compare_code, op0, op1);
3329 if (new_mode != orig_compare_mode
3330 && can_change_dest_mode (SET_DEST (newpat),
3331 added_sets_2, new_mode))
3332 {
3333 unsigned int regno = REGNO (newpat_dest);
3334 compare_mode = new_mode;
3335 if (regno < FIRST_PSEUDO_REGISTER)
3336 newpat_dest = gen_rtx_REG (compare_mode, regno);
3337 else
3338 {
3339 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3340 newpat_dest = regno_reg_rtx[regno];
3341 }
3342 }
3343 #endif
3344 /* Cases for modifying the CC-using comparison. */
3345 if (compare_code != orig_compare_code
3346 /* ??? Do we need to verify the zero rtx? */
3347 && XEXP (*cc_use_loc, 1) == const0_rtx)
3348 {
3349 /* Replace cc_use_loc with entire new RTX. */
3350 SUBST (*cc_use_loc,
3351 gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc),
3352 newpat_dest, const0_rtx));
3353 undobuf.other_insn = cc_use_insn;
3354 }
3355 else if (compare_mode != orig_compare_mode)
3356 {
3357 /* Just replace the CC reg with a new mode. */
3358 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3359 undobuf.other_insn = cc_use_insn;
3360 }
3361 }
3362
3363 /* Now we modify the current newpat:
3364 First, SET_DEST(newpat) is updated if the CC mode has been
3365 altered. For targets without SELECT_CC_MODE, this should be
3366 optimized away. */
3367 if (compare_mode != orig_compare_mode)
3368 SUBST (SET_DEST (newpat), newpat_dest);
3369 /* This is always done to propagate i2src into newpat. */
3370 SUBST (SET_SRC (newpat),
3371 gen_rtx_COMPARE (compare_mode, op0, op1));
3372 /* Create new version of i2pat if needed; the below PARALLEL
3373 creation needs this to work correctly. */
3374 if (! rtx_equal_p (i2src, op0))
3375 i2pat = gen_rtx_SET (i2dest, op0);
3376 i2_is_used = 1;
3377 }
3378 }
3379
3380 if (i2_is_used == 0)
3381 {
3382 /* It is possible that the source of I2 or I1 may be performing
3383 an unneeded operation, such as a ZERO_EXTEND of something
3384 that is known to have the high part zero. Handle that case
3385 by letting subst look at the inner insns.
3386
3387 Another way to do this would be to have a function that tries
3388 to simplify a single insn instead of merging two or more
3389 insns. We don't do this because of the potential of infinite
3390 loops and because of the potential extra memory required.
3391 However, doing it the way we are is a bit of a kludge and
3392 doesn't catch all cases.
3393
3394 But only do this if -fexpensive-optimizations since it slows
3395 things down and doesn't usually win.
3396
3397 This is not done in the COMPARE case above because the
3398 unmodified I2PAT is used in the PARALLEL and so a pattern
3399 with a modified I2SRC would not match. */
3400
3401 if (flag_expensive_optimizations)
3402 {
3403 /* Pass pc_rtx so no substitutions are done, just
3404 simplifications. */
3405 if (i1)
3406 {
3407 subst_low_luid = DF_INSN_LUID (i1);
3408 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3409 }
3410
3411 subst_low_luid = DF_INSN_LUID (i2);
3412 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3413 }
3414
3415 n_occurrences = 0; /* `subst' counts here */
3416 subst_low_luid = DF_INSN_LUID (i2);
3417
3418 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3419 copy of I2SRC each time we substitute it, in order to avoid creating
3420 self-referential RTL when we will be substituting I1SRC for I1DEST
3421 later. Likewise if I0 feeds into I2, either directly or indirectly
3422 through I1, and I0DEST is in I0SRC. */
3423 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3424 (i1_feeds_i2_n && i1dest_in_i1src)
3425 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3426 && i0dest_in_i0src));
3427 substed_i2 = 1;
3428
3429 /* Record whether I2's body now appears within I3's body. */
3430 i2_is_used = n_occurrences;
3431 }
3432
3433 /* If we already got a failure, don't try to do more. Otherwise, try to
3434 substitute I1 if we have it. */
3435
3436 if (i1 && GET_CODE (newpat) != CLOBBER)
3437 {
3438 /* Before we can do this substitution, we must redo the test done
3439 above (see detailed comments there) that ensures I1DEST isn't
3440 mentioned in any SETs in NEWPAT that are field assignments. */
3441 if (!combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3442 0, 0, 0))
3443 {
3444 undo_all ();
3445 return 0;
3446 }
3447
3448 n_occurrences = 0;
3449 subst_low_luid = DF_INSN_LUID (i1);
3450
3451 /* If the following substitution will modify I1SRC, make a copy of it
3452 for the case where it is substituted for I1DEST in I2PAT later. */
3453 if (added_sets_2 && i1_feeds_i2_n)
3454 i1src_copy = copy_rtx (i1src);
3455
3456 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3457 copy of I1SRC each time we substitute it, in order to avoid creating
3458 self-referential RTL when we will be substituting I0SRC for I0DEST
3459 later. */
3460 newpat = subst (newpat, i1dest, i1src, 0, 0,
3461 i0_feeds_i1_n && i0dest_in_i0src);
3462 substed_i1 = 1;
3463
3464 /* Record whether I1's body now appears within I3's body. */
3465 i1_is_used = n_occurrences;
3466 }
3467
3468 /* Likewise for I0 if we have it. */
3469
3470 if (i0 && GET_CODE (newpat) != CLOBBER)
3471 {
3472 if (!combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3473 0, 0, 0))
3474 {
3475 undo_all ();
3476 return 0;
3477 }
3478
3479 /* If the following substitution will modify I0SRC, make a copy of it
3480 for the case where it is substituted for I0DEST in I1PAT later. */
3481 if (added_sets_1 && i0_feeds_i1_n)
3482 i0src_copy = copy_rtx (i0src);
3483 /* And a copy for I0DEST in I2PAT substitution. */
3484 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3485 || (i0_feeds_i2_n)))
3486 i0src_copy2 = copy_rtx (i0src);
3487
3488 n_occurrences = 0;
3489 subst_low_luid = DF_INSN_LUID (i0);
3490 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3491 substed_i0 = 1;
3492 }
3493
3494 if (n_auto_inc)
3495 {
3496 int new_n_auto_inc = 0;
3497 for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc);
3498
3499 if (n_auto_inc != new_n_auto_inc)
3500 {
3501 if (dump_file && (dump_flags & TDF_DETAILS))
3502 fprintf (dump_file, "Number of auto_inc expressions changed\n");
3503 undo_all ();
3504 return 0;
3505 }
3506 }
3507
3508 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3509 to count all the ways that I2SRC and I1SRC can be used. */
3510 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3511 && i2_is_used + added_sets_2 > 1)
3512 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3513 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3514 > 1))
3515 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3516 && (n_occurrences + added_sets_0
3517 + (added_sets_1 && i0_feeds_i1_n)
3518 + (added_sets_2 && i0_feeds_i2_n)
3519 > 1))
3520 /* Fail if we tried to make a new register. */
3521 || max_reg_num () != maxreg
3522 /* Fail if we couldn't do something and have a CLOBBER. */
3523 || GET_CODE (newpat) == CLOBBER
3524 /* Fail if this new pattern is a MULT and we didn't have one before
3525 at the outer level. */
3526 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3527 && ! have_mult))
3528 {
3529 undo_all ();
3530 return 0;
3531 }
3532
3533 /* If the actions of the earlier insns must be kept
3534 in addition to substituting them into the latest one,
3535 we must make a new PARALLEL for the latest insn
3536 to hold additional the SETs. */
3537
3538 if (added_sets_0 || added_sets_1 || added_sets_2)
3539 {
3540 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3541 combine_extras++;
3542
3543 if (GET_CODE (newpat) == PARALLEL)
3544 {
3545 rtvec old = XVEC (newpat, 0);
3546 total_sets = XVECLEN (newpat, 0) + extra_sets;
3547 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3548 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3549 sizeof (old->elem[0]) * old->num_elem);
3550 }
3551 else
3552 {
3553 rtx old = newpat;
3554 total_sets = 1 + extra_sets;
3555 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3556 XVECEXP (newpat, 0, 0) = old;
3557 }
3558
3559 if (added_sets_0)
3560 XVECEXP (newpat, 0, --total_sets) = i0pat;
3561
3562 if (added_sets_1)
3563 {
3564 rtx t = i1pat;
3565 if (i0_feeds_i1_n)
3566 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3567
3568 XVECEXP (newpat, 0, --total_sets) = t;
3569 }
3570 if (added_sets_2)
3571 {
3572 rtx t = i2pat;
3573 if (i1_feeds_i2_n)
3574 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3575 i0_feeds_i1_n && i0dest_in_i0src);
3576 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3577 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3578
3579 XVECEXP (newpat, 0, --total_sets) = t;
3580 }
3581 }
3582
3583 validate_replacement:
3584
3585 /* Note which hard regs this insn has as inputs. */
3586 mark_used_regs_combine (newpat);
3587
3588 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3589 consider splitting this pattern, we might need these clobbers. */
3590 if (i1 && GET_CODE (newpat) == PARALLEL
3591 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3592 {
3593 int len = XVECLEN (newpat, 0);
3594
3595 newpat_vec_with_clobbers = rtvec_alloc (len);
3596 for (i = 0; i < len; i++)
3597 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3598 }
3599
3600 /* We have recognized nothing yet. */
3601 insn_code_number = -1;
3602
3603 /* See if this is a PARALLEL of two SETs where one SET's destination is
3604 a register that is unused and this isn't marked as an instruction that
3605 might trap in an EH region. In that case, we just need the other SET.
3606 We prefer this over the PARALLEL.
3607
3608 This can occur when simplifying a divmod insn. We *must* test for this
3609 case here because the code below that splits two independent SETs doesn't
3610 handle this case correctly when it updates the register status.
3611
3612 It's pointless doing this if we originally had two sets, one from
3613 i3, and one from i2. Combining then splitting the parallel results
3614 in the original i2 again plus an invalid insn (which we delete).
3615 The net effect is only to move instructions around, which makes
3616 debug info less accurate.
3617
3618 If the remaining SET came from I2 its destination should not be used
3619 between I2 and I3. See PR82024. */
3620
3621 if (!(added_sets_2 && i1 == 0)
3622 && is_parallel_of_n_reg_sets (newpat, 2)
3623 && asm_noperands (newpat) < 0)
3624 {
3625 rtx set0 = XVECEXP (newpat, 0, 0);
3626 rtx set1 = XVECEXP (newpat, 0, 1);
3627 rtx oldpat = newpat;
3628
3629 if (((REG_P (SET_DEST (set1))
3630 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3631 || (GET_CODE (SET_DEST (set1)) == SUBREG
3632 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3633 && insn_nothrow_p (i3)
3634 && !side_effects_p (SET_SRC (set1)))
3635 {
3636 newpat = set0;
3637 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3638 }
3639
3640 else if (((REG_P (SET_DEST (set0))
3641 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3642 || (GET_CODE (SET_DEST (set0)) == SUBREG
3643 && find_reg_note (i3, REG_UNUSED,
3644 SUBREG_REG (SET_DEST (set0)))))
3645 && insn_nothrow_p (i3)
3646 && !side_effects_p (SET_SRC (set0)))
3647 {
3648 rtx dest = SET_DEST (set1);
3649 if (GET_CODE (dest) == SUBREG)
3650 dest = SUBREG_REG (dest);
3651 if (!reg_used_between_p (dest, i2, i3))
3652 {
3653 newpat = set1;
3654 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3655
3656 if (insn_code_number >= 0)
3657 changed_i3_dest = 1;
3658 }
3659 }
3660
3661 if (insn_code_number < 0)
3662 newpat = oldpat;
3663 }
3664
3665 /* Is the result of combination a valid instruction? */
3666 if (insn_code_number < 0)
3667 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3668
3669 /* If we were combining three insns and the result is a simple SET
3670 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3671 insns. There are two ways to do this. It can be split using a
3672 machine-specific method (like when you have an addition of a large
3673 constant) or by combine in the function find_split_point. */
3674
3675 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3676 && asm_noperands (newpat) < 0)
3677 {
3678 rtx parallel, *split;
3679 rtx_insn *m_split_insn;
3680
3681 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3682 use I2DEST as a scratch register will help. In the latter case,
3683 convert I2DEST to the mode of the source of NEWPAT if we can. */
3684
3685 m_split_insn = combine_split_insns (newpat, i3);
3686
3687 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3688 inputs of NEWPAT. */
3689
3690 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3691 possible to try that as a scratch reg. This would require adding
3692 more code to make it work though. */
3693
3694 if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3695 {
3696 machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3697
3698 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3699 (temporarily, until we are committed to this instruction
3700 combination) does not work: for example, any call to nonzero_bits
3701 on the register (from a splitter in the MD file, for example)
3702 will get the old information, which is invalid.
3703
3704 Since nowadays we can create registers during combine just fine,
3705 we should just create a new one here, not reuse i2dest. */
3706
3707 /* First try to split using the original register as a
3708 scratch register. */
3709 parallel = gen_rtx_PARALLEL (VOIDmode,
3710 gen_rtvec (2, newpat,
3711 gen_rtx_CLOBBER (VOIDmode,
3712 i2dest)));
3713 m_split_insn = combine_split_insns (parallel, i3);
3714
3715 /* If that didn't work, try changing the mode of I2DEST if
3716 we can. */
3717 if (m_split_insn == 0
3718 && new_mode != GET_MODE (i2dest)
3719 && new_mode != VOIDmode
3720 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3721 {
3722 machine_mode old_mode = GET_MODE (i2dest);
3723 rtx ni2dest;
3724
3725 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3726 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3727 else
3728 {
3729 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3730 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3731 }
3732
3733 parallel = (gen_rtx_PARALLEL
3734 (VOIDmode,
3735 gen_rtvec (2, newpat,
3736 gen_rtx_CLOBBER (VOIDmode,
3737 ni2dest))));
3738 m_split_insn = combine_split_insns (parallel, i3);
3739
3740 if (m_split_insn == 0
3741 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3742 {
3743 struct undo *buf;
3744
3745 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3746 buf = undobuf.undos;
3747 undobuf.undos = buf->next;
3748 buf->next = undobuf.frees;
3749 undobuf.frees = buf;
3750 }
3751 }
3752
3753 i2scratch = m_split_insn != 0;
3754 }
3755
3756 /* If recog_for_combine has discarded clobbers, try to use them
3757 again for the split. */
3758 if (m_split_insn == 0 && newpat_vec_with_clobbers)
3759 {
3760 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3761 m_split_insn = combine_split_insns (parallel, i3);
3762 }
3763
3764 if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3765 {
3766 rtx m_split_pat = PATTERN (m_split_insn);
3767 insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes);
3768 if (insn_code_number >= 0)
3769 newpat = m_split_pat;
3770 }
3771 else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3772 && (next_nonnote_nondebug_insn (i2) == i3
3773 || !modified_between_p (PATTERN (m_split_insn), i2, i3)))
3774 {
3775 rtx i2set, i3set;
3776 rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3777 newi2pat = PATTERN (m_split_insn);
3778
3779 i3set = single_set (NEXT_INSN (m_split_insn));
3780 i2set = single_set (m_split_insn);
3781
3782 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3783
3784 /* If I2 or I3 has multiple SETs, we won't know how to track
3785 register status, so don't use these insns. If I2's destination
3786 is used between I2 and I3, we also can't use these insns. */
3787
3788 if (i2_code_number >= 0 && i2set && i3set
3789 && (next_nonnote_nondebug_insn (i2) == i3
3790 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3791 insn_code_number = recog_for_combine (&newi3pat, i3,
3792 &new_i3_notes);
3793 if (insn_code_number >= 0)
3794 newpat = newi3pat;
3795
3796 /* It is possible that both insns now set the destination of I3.
3797 If so, we must show an extra use of it. */
3798
3799 if (insn_code_number >= 0)
3800 {
3801 rtx new_i3_dest = SET_DEST (i3set);
3802 rtx new_i2_dest = SET_DEST (i2set);
3803
3804 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3805 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3806 || GET_CODE (new_i3_dest) == SUBREG)
3807 new_i3_dest = XEXP (new_i3_dest, 0);
3808
3809 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3810 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3811 || GET_CODE (new_i2_dest) == SUBREG)
3812 new_i2_dest = XEXP (new_i2_dest, 0);
3813
3814 if (REG_P (new_i3_dest)
3815 && REG_P (new_i2_dest)
3816 && REGNO (new_i3_dest) == REGNO (new_i2_dest)
3817 && REGNO (new_i2_dest) < reg_n_sets_max)
3818 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3819 }
3820 }
3821
3822 /* If we can split it and use I2DEST, go ahead and see if that
3823 helps things be recognized. Verify that none of the registers
3824 are set between I2 and I3. */
3825 if (insn_code_number < 0
3826 && (split = find_split_point (&newpat, i3, false)) != 0
3827 && (!HAVE_cc0 || REG_P (i2dest))
3828 /* We need I2DEST in the proper mode. If it is a hard register
3829 or the only use of a pseudo, we can change its mode.
3830 Make sure we don't change a hard register to have a mode that
3831 isn't valid for it, or change the number of registers. */
3832 && (GET_MODE (*split) == GET_MODE (i2dest)
3833 || GET_MODE (*split) == VOIDmode
3834 || can_change_dest_mode (i2dest, added_sets_2,
3835 GET_MODE (*split)))
3836 && (next_nonnote_nondebug_insn (i2) == i3
3837 || !modified_between_p (*split, i2, i3))
3838 /* We can't overwrite I2DEST if its value is still used by
3839 NEWPAT. */
3840 && ! reg_referenced_p (i2dest, newpat))
3841 {
3842 rtx newdest = i2dest;
3843 enum rtx_code split_code = GET_CODE (*split);
3844 machine_mode split_mode = GET_MODE (*split);
3845 bool subst_done = false;
3846 newi2pat = NULL_RTX;
3847
3848 i2scratch = true;
3849
3850 /* *SPLIT may be part of I2SRC, so make sure we have the
3851 original expression around for later debug processing.
3852 We should not need I2SRC any more in other cases. */
3853 if (MAY_HAVE_DEBUG_BIND_INSNS)
3854 i2src = copy_rtx (i2src);
3855 else
3856 i2src = NULL;
3857
3858 /* Get NEWDEST as a register in the proper mode. We have already
3859 validated that we can do this. */
3860 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3861 {
3862 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3863 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3864 else
3865 {
3866 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3867 newdest = regno_reg_rtx[REGNO (i2dest)];
3868 }
3869 }
3870
3871 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3872 an ASHIFT. This can occur if it was inside a PLUS and hence
3873 appeared to be a memory address. This is a kludge. */
3874 if (split_code == MULT
3875 && CONST_INT_P (XEXP (*split, 1))
3876 && INTVAL (XEXP (*split, 1)) > 0
3877 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3878 {
3879 rtx i_rtx = gen_int_shift_amount (split_mode, i);
3880 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3881 XEXP (*split, 0), i_rtx));
3882 /* Update split_code because we may not have a multiply
3883 anymore. */
3884 split_code = GET_CODE (*split);
3885 }
3886
3887 /* Similarly for (plus (mult FOO (const_int pow2))). */
3888 if (split_code == PLUS
3889 && GET_CODE (XEXP (*split, 0)) == MULT
3890 && CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3891 && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3892 && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3893 {
3894 rtx nsplit = XEXP (*split, 0);
3895 rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i);
3896 SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3897 XEXP (nsplit, 0),
3898 i_rtx));
3899 /* Update split_code because we may not have a multiply
3900 anymore. */
3901 split_code = GET_CODE (*split);
3902 }
3903
3904 #ifdef INSN_SCHEDULING
3905 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3906 be written as a ZERO_EXTEND. */
3907 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3908 {
3909 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3910 what it really is. */
3911 if (load_extend_op (GET_MODE (SUBREG_REG (*split)))
3912 == SIGN_EXTEND)
3913 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3914 SUBREG_REG (*split)));
3915 else
3916 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3917 SUBREG_REG (*split)));
3918 }
3919 #endif
3920
3921 /* Attempt to split binary operators using arithmetic identities. */
3922 if (BINARY_P (SET_SRC (newpat))
3923 && split_mode == GET_MODE (SET_SRC (newpat))
3924 && ! side_effects_p (SET_SRC (newpat)))
3925 {
3926 rtx setsrc = SET_SRC (newpat);
3927 machine_mode mode = GET_MODE (setsrc);
3928 enum rtx_code code = GET_CODE (setsrc);
3929 rtx src_op0 = XEXP (setsrc, 0);
3930 rtx src_op1 = XEXP (setsrc, 1);
3931
3932 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3933 if (rtx_equal_p (src_op0, src_op1))
3934 {
3935 newi2pat = gen_rtx_SET (newdest, src_op0);
3936 SUBST (XEXP (setsrc, 0), newdest);
3937 SUBST (XEXP (setsrc, 1), newdest);
3938 subst_done = true;
3939 }
3940 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3941 else if ((code == PLUS || code == MULT)
3942 && GET_CODE (src_op0) == code
3943 && GET_CODE (XEXP (src_op0, 0)) == code
3944 && (INTEGRAL_MODE_P (mode)
3945 || (FLOAT_MODE_P (mode)
3946 && flag_unsafe_math_optimizations)))
3947 {
3948 rtx p = XEXP (XEXP (src_op0, 0), 0);
3949 rtx q = XEXP (XEXP (src_op0, 0), 1);
3950 rtx r = XEXP (src_op0, 1);
3951 rtx s = src_op1;
3952
3953 /* Split both "((X op Y) op X) op Y" and
3954 "((X op Y) op Y) op X" as "T op T" where T is
3955 "X op Y". */
3956 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3957 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3958 {
3959 newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3960 SUBST (XEXP (setsrc, 0), newdest);
3961 SUBST (XEXP (setsrc, 1), newdest);
3962 subst_done = true;
3963 }
3964 /* Split "((X op X) op Y) op Y)" as "T op T" where
3965 T is "X op Y". */
3966 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3967 {
3968 rtx tmp = simplify_gen_binary (code, mode, p, r);
3969 newi2pat = gen_rtx_SET (newdest, tmp);
3970 SUBST (XEXP (setsrc, 0), newdest);
3971 SUBST (XEXP (setsrc, 1), newdest);
3972 subst_done = true;
3973 }
3974 }
3975 }
3976
3977 if (!subst_done)
3978 {
3979 newi2pat = gen_rtx_SET (newdest, *split);
3980 SUBST (*split, newdest);
3981 }
3982
3983 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3984
3985 /* recog_for_combine might have added CLOBBERs to newi2pat.
3986 Make sure NEWPAT does not depend on the clobbered regs. */
3987 if (GET_CODE (newi2pat) == PARALLEL)
3988 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3989 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3990 {
3991 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3992 if (reg_overlap_mentioned_p (reg, newpat))
3993 {
3994 undo_all ();
3995 return 0;
3996 }
3997 }
3998
3999 /* If the split point was a MULT and we didn't have one before,
4000 don't use one now. */
4001 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
4002 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4003 }
4004 }
4005
4006 /* Check for a case where we loaded from memory in a narrow mode and
4007 then sign extended it, but we need both registers. In that case,
4008 we have a PARALLEL with both loads from the same memory location.
4009 We can split this into a load from memory followed by a register-register
4010 copy. This saves at least one insn, more if register allocation can
4011 eliminate the copy.
4012
4013 We cannot do this if the destination of the first assignment is a
4014 condition code register or cc0. We eliminate this case by making sure
4015 the SET_DEST and SET_SRC have the same mode.
4016
4017 We cannot do this if the destination of the second assignment is
4018 a register that we have already assumed is zero-extended. Similarly
4019 for a SUBREG of such a register. */
4020
4021 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
4022 && GET_CODE (newpat) == PARALLEL
4023 && XVECLEN (newpat, 0) == 2
4024 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
4025 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
4026 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
4027 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
4028 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
4029 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
4030 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
4031 && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3)
4032 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
4033 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
4034 && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
4035 (REG_P (temp_expr)
4036 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
4037 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
4038 BITS_PER_WORD)
4039 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
4040 HOST_BITS_PER_INT)
4041 && (reg_stat[REGNO (temp_expr)].nonzero_bits
4042 != GET_MODE_MASK (word_mode))))
4043 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
4044 && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
4045 (REG_P (temp_expr)
4046 && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
4047 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
4048 BITS_PER_WORD)
4049 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
4050 HOST_BITS_PER_INT)
4051 && (reg_stat[REGNO (temp_expr)].nonzero_bits
4052 != GET_MODE_MASK (word_mode)))))
4053 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
4054 SET_SRC (XVECEXP (newpat, 0, 1)))
4055 && ! find_reg_note (i3, REG_UNUSED,
4056 SET_DEST (XVECEXP (newpat, 0, 0))))
4057 {
4058 rtx ni2dest;
4059
4060 newi2pat = XVECEXP (newpat, 0, 0);
4061 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
4062 newpat = XVECEXP (newpat, 0, 1);
4063 SUBST (SET_SRC (newpat),
4064 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
4065 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4066
4067 if (i2_code_number >= 0)
4068 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4069
4070 if (insn_code_number >= 0)
4071 swap_i2i3 = 1;
4072 }
4073
4074 /* Similarly, check for a case where we have a PARALLEL of two independent
4075 SETs but we started with three insns. In this case, we can do the sets
4076 as two separate insns. This case occurs when some SET allows two
4077 other insns to combine, but the destination of that SET is still live.
4078
4079 Also do this if we started with two insns and (at least) one of the
4080 resulting sets is a noop; this noop will be deleted later.
4081
4082 Also do this if we started with two insns neither of which was a simple
4083 move. */
4084
4085 else if (insn_code_number < 0 && asm_noperands (newpat) < 0
4086 && GET_CODE (newpat) == PARALLEL
4087 && XVECLEN (newpat, 0) == 2
4088 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
4089 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
4090 && (i1
4091 || set_noop_p (XVECEXP (newpat, 0, 0))
4092 || set_noop_p (XVECEXP (newpat, 0, 1))
4093 || (!i2_was_move && !i3_was_move))
4094 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
4095 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
4096 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
4097 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
4098 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
4099 XVECEXP (newpat, 0, 0))
4100 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
4101 XVECEXP (newpat, 0, 1))
4102 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
4103 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
4104 {
4105 rtx set0 = XVECEXP (newpat, 0, 0);
4106 rtx set1 = XVECEXP (newpat, 0, 1);
4107
4108 /* Normally, it doesn't matter which of the two is done first,
4109 but the one that references cc0 can't be the second, and
4110 one which uses any regs/memory set in between i2 and i3 can't
4111 be first. The PARALLEL might also have been pre-existing in i3,
4112 so we need to make sure that we won't wrongly hoist a SET to i2
4113 that would conflict with a death note present in there, or would
4114 have its dest modified between i2 and i3. */
4115 if (!modified_between_p (SET_SRC (set1), i2, i3)
4116 && !(REG_P (SET_DEST (set1))
4117 && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
4118 && !(GET_CODE (SET_DEST (set1)) == SUBREG
4119 && find_reg_note (i2, REG_DEAD,
4120 SUBREG_REG (SET_DEST (set1))))
4121 && !modified_between_p (SET_DEST (set1), i2, i3)
4122 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set0))
4123 /* If I3 is a jump, ensure that set0 is a jump so that
4124 we do not create invalid RTL. */
4125 && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
4126 )
4127 {
4128 newi2pat = set1;
4129 newpat = set0;
4130 }
4131 else if (!modified_between_p (SET_SRC (set0), i2, i3)
4132 && !(REG_P (SET_DEST (set0))
4133 && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
4134 && !(GET_CODE (SET_DEST (set0)) == SUBREG
4135 && find_reg_note (i2, REG_DEAD,
4136 SUBREG_REG (SET_DEST (set0))))
4137 && !modified_between_p (SET_DEST (set0), i2, i3)
4138 && (!HAVE_cc0 || !reg_referenced_p (cc0_rtx, set1))
4139 /* If I3 is a jump, ensure that set1 is a jump so that
4140 we do not create invalid RTL. */
4141 && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
4142 )
4143 {
4144 newi2pat = set0;
4145 newpat = set1;
4146 }
4147 else
4148 {
4149 undo_all ();
4150 return 0;
4151 }
4152
4153 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4154
4155 if (i2_code_number >= 0)
4156 {
4157 /* recog_for_combine might have added CLOBBERs to newi2pat.
4158 Make sure NEWPAT does not depend on the clobbered regs. */
4159 if (GET_CODE (newi2pat) == PARALLEL)
4160 {
4161 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
4162 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
4163 {
4164 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
4165 if (reg_overlap_mentioned_p (reg, newpat))
4166 {
4167 undo_all ();
4168 return 0;
4169 }
4170 }
4171 }
4172
4173 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4174
4175 if (insn_code_number >= 0)
4176 split_i2i3 = 1;
4177 }
4178 }
4179
4180 /* If it still isn't recognized, fail and change things back the way they
4181 were. */
4182 if ((insn_code_number < 0
4183 /* Is the result a reasonable ASM_OPERANDS? */
4184 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4185 {
4186 undo_all ();
4187 return 0;
4188 }
4189
4190 /* If we had to change another insn, make sure it is valid also. */
4191 if (undobuf.other_insn)
4192 {
4193 CLEAR_HARD_REG_SET (newpat_used_regs);
4194
4195 other_pat = PATTERN (undobuf.other_insn);
4196 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4197 &new_other_notes);
4198
4199 if (other_code_number < 0 && ! check_asm_operands (other_pat))
4200 {
4201 undo_all ();
4202 return 0;
4203 }
4204 }
4205
4206 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4207 they are adjacent to each other or not. */
4208 if (HAVE_cc0)
4209 {
4210 rtx_insn *p = prev_nonnote_insn (i3);
4211 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
4212 && sets_cc0_p (newi2pat))
4213 {
4214 undo_all ();
4215 return 0;
4216 }
4217 }
4218
4219 /* Only allow this combination if insn_cost reports that the
4220 replacement instructions are cheaper than the originals. */
4221 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
4222 {
4223 undo_all ();
4224 return 0;
4225 }
4226
4227 if (MAY_HAVE_DEBUG_BIND_INSNS)
4228 {
4229 struct undo *undo;
4230
4231 for (undo = undobuf.undos; undo; undo = undo->next)
4232 if (undo->kind == UNDO_MODE)
4233 {
4234 rtx reg = *undo->where.r;
4235 machine_mode new_mode = GET_MODE (reg);
4236 machine_mode old_mode = undo->old_contents.m;
4237
4238 /* Temporarily revert mode back. */
4239 adjust_reg_mode (reg, old_mode);
4240
4241 if (reg == i2dest && i2scratch)
4242 {
4243 /* If we used i2dest as a scratch register with a
4244 different mode, substitute it for the original
4245 i2src while its original mode is temporarily
4246 restored, and then clear i2scratch so that we don't
4247 do it again later. */
4248 propagate_for_debug (i2, last_combined_insn, reg, i2src,
4249 this_basic_block);
4250 i2scratch = false;
4251 /* Put back the new mode. */
4252 adjust_reg_mode (reg, new_mode);
4253 }
4254 else
4255 {
4256 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4257 rtx_insn *first, *last;
4258
4259 if (reg == i2dest)
4260 {
4261 first = i2;
4262 last = last_combined_insn;
4263 }
4264 else
4265 {
4266 first = i3;
4267 last = undobuf.other_insn;
4268 gcc_assert (last);
4269 if (DF_INSN_LUID (last)
4270 < DF_INSN_LUID (last_combined_insn))
4271 last = last_combined_insn;
4272 }
4273
4274 /* We're dealing with a reg that changed mode but not
4275 meaning, so we want to turn it into a subreg for
4276 the new mode. However, because of REG sharing and
4277 because its mode had already changed, we have to do
4278 it in two steps. First, replace any debug uses of
4279 reg, with its original mode temporarily restored,
4280 with this copy we have created; then, replace the
4281 copy with the SUBREG of the original shared reg,
4282 once again changed to the new mode. */
4283 propagate_for_debug (first, last, reg, tempreg,
4284 this_basic_block);
4285 adjust_reg_mode (reg, new_mode);
4286 propagate_for_debug (first, last, tempreg,
4287 lowpart_subreg (old_mode, reg, new_mode),
4288 this_basic_block);
4289 }
4290 }
4291 }
4292
4293 /* If we will be able to accept this, we have made a
4294 change to the destination of I3. This requires us to
4295 do a few adjustments. */
4296
4297 if (changed_i3_dest)
4298 {
4299 PATTERN (i3) = newpat;
4300 adjust_for_new_dest (i3);
4301 }
4302
4303 /* We now know that we can do this combination. Merge the insns and
4304 update the status of registers and LOG_LINKS. */
4305
4306 if (undobuf.other_insn)
4307 {
4308 rtx note, next;
4309
4310 PATTERN (undobuf.other_insn) = other_pat;
4311
4312 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4313 ensure that they are still valid. Then add any non-duplicate
4314 notes added by recog_for_combine. */
4315 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4316 {
4317 next = XEXP (note, 1);
4318
4319 if ((REG_NOTE_KIND (note) == REG_DEAD
4320 && !reg_referenced_p (XEXP (note, 0),
4321 PATTERN (undobuf.other_insn)))
4322 ||(REG_NOTE_KIND (note) == REG_UNUSED
4323 && !reg_set_p (XEXP (note, 0),
4324 PATTERN (undobuf.other_insn)))
4325 /* Simply drop equal note since it may be no longer valid
4326 for other_insn. It may be possible to record that CC
4327 register is changed and only discard those notes, but
4328 in practice it's unnecessary complication and doesn't
4329 give any meaningful improvement.
4330
4331 See PR78559. */
4332 || REG_NOTE_KIND (note) == REG_EQUAL
4333 || REG_NOTE_KIND (note) == REG_EQUIV)
4334 remove_note (undobuf.other_insn, note);
4335 }
4336
4337 distribute_notes (new_other_notes, undobuf.other_insn,
4338 undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4339 NULL_RTX);
4340 }
4341
4342 if (swap_i2i3)
4343 {
4344 /* I3 now uses what used to be its destination and which is now
4345 I2's destination. This requires us to do a few adjustments. */
4346 PATTERN (i3) = newpat;
4347 adjust_for_new_dest (i3);
4348 }
4349
4350 if (swap_i2i3 || split_i2i3)
4351 {
4352 /* We might need a LOG_LINK from I3 to I2. But then we used to
4353 have one, so we still will.
4354
4355 However, some later insn might be using I2's dest and have
4356 a LOG_LINK pointing at I3. We should change it to point at
4357 I2 instead. */
4358
4359 /* newi2pat is usually a SET here; however, recog_for_combine might
4360 have added some clobbers. */
4361 rtx x = newi2pat;
4362 if (GET_CODE (x) == PARALLEL)
4363 x = XVECEXP (newi2pat, 0, 0);
4364
4365 if (REG_P (SET_DEST (x))
4366 || (GET_CODE (SET_DEST (x)) == SUBREG
4367 && REG_P (SUBREG_REG (SET_DEST (x)))))
4368 {
4369 unsigned int regno = reg_or_subregno (SET_DEST (x));
4370
4371 bool done = false;
4372 for (rtx_insn *insn = NEXT_INSN (i3);
4373 !done
4374 && insn
4375 && NONDEBUG_INSN_P (insn)
4376 && BLOCK_FOR_INSN (insn) == this_basic_block;
4377 insn = NEXT_INSN (insn))
4378 {
4379 struct insn_link *link;
4380 FOR_EACH_LOG_LINK (link, insn)
4381 if (link->insn == i3 && link->regno == regno)
4382 {
4383 link->insn = i2;
4384 done = true;
4385 break;
4386 }
4387 }
4388 }
4389 }
4390
4391 {
4392 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4393 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4394 rtx midnotes = 0;
4395 int from_luid;
4396 /* Compute which registers we expect to eliminate. newi2pat may be setting
4397 either i3dest or i2dest, so we must check it. */
4398 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4399 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4400 || !i2dest_killed
4401 ? 0 : i2dest);
4402 /* For i1, we need to compute both local elimination and global
4403 elimination information with respect to newi2pat because i1dest
4404 may be the same as i3dest, in which case newi2pat may be setting
4405 i1dest. Global information is used when distributing REG_DEAD
4406 note for i2 and i3, in which case it does matter if newi2pat sets
4407 i1dest or not.
4408
4409 Local information is used when distributing REG_DEAD note for i1,
4410 in which case it doesn't matter if newi2pat sets i1dest or not.
4411 See PR62151, if we have four insns combination:
4412 i0: r0 <- i0src
4413 i1: r1 <- i1src (using r0)
4414 REG_DEAD (r0)
4415 i2: r0 <- i2src (using r1)
4416 i3: r3 <- i3src (using r0)
4417 ix: using r0
4418 From i1's point of view, r0 is eliminated, no matter if it is set
4419 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4420 should be discarded.
4421
4422 Note local information only affects cases in forms like "I1->I2->I3",
4423 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4424 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4425 i0dest anyway. */
4426 rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4427 || !i1dest_killed
4428 ? 0 : i1dest);
4429 rtx elim_i1 = (local_elim_i1 == 0
4430 || (newi2pat && reg_set_p (i1dest, newi2pat))
4431 ? 0 : i1dest);
4432 /* Same case as i1. */
4433 rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4434 ? 0 : i0dest);
4435 rtx elim_i0 = (local_elim_i0 == 0
4436 || (newi2pat && reg_set_p (i0dest, newi2pat))
4437 ? 0 : i0dest);
4438
4439 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4440 clear them. */
4441 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4442 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4443 if (i1)
4444 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4445 if (i0)
4446 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4447
4448 /* Ensure that we do not have something that should not be shared but
4449 occurs multiple times in the new insns. Check this by first
4450 resetting all the `used' flags and then copying anything is shared. */
4451
4452 reset_used_flags (i3notes);
4453 reset_used_flags (i2notes);
4454 reset_used_flags (i1notes);
4455 reset_used_flags (i0notes);
4456 reset_used_flags (newpat);
4457 reset_used_flags (newi2pat);
4458 if (undobuf.other_insn)
4459 reset_used_flags (PATTERN (undobuf.other_insn));
4460
4461 i3notes = copy_rtx_if_shared (i3notes);
4462 i2notes = copy_rtx_if_shared (i2notes);
4463 i1notes = copy_rtx_if_shared (i1notes);
4464 i0notes = copy_rtx_if_shared (i0notes);
4465 newpat = copy_rtx_if_shared (newpat);
4466 newi2pat = copy_rtx_if_shared (newi2pat);
4467 if (undobuf.other_insn)
4468 reset_used_flags (PATTERN (undobuf.other_insn));
4469
4470 INSN_CODE (i3) = insn_code_number;
4471 PATTERN (i3) = newpat;
4472
4473 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4474 {
4475 for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link;
4476 link = XEXP (link, 1))
4477 {
4478 if (substed_i2)
4479 {
4480 /* I2SRC must still be meaningful at this point. Some
4481 splitting operations can invalidate I2SRC, but those
4482 operations do not apply to calls. */
4483 gcc_assert (i2src);
4484 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4485 i2dest, i2src);
4486 }
4487 if (substed_i1)
4488 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4489 i1dest, i1src);
4490 if (substed_i0)
4491 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4492 i0dest, i0src);
4493 }
4494 }
4495
4496 if (undobuf.other_insn)
4497 INSN_CODE (undobuf.other_insn) = other_code_number;
4498
4499 /* We had one special case above where I2 had more than one set and
4500 we replaced a destination of one of those sets with the destination
4501 of I3. In that case, we have to update LOG_LINKS of insns later
4502 in this basic block. Note that this (expensive) case is rare.
4503
4504 Also, in this case, we must pretend that all REG_NOTEs for I2
4505 actually came from I3, so that REG_UNUSED notes from I2 will be
4506 properly handled. */
4507
4508 if (i3_subst_into_i2)
4509 {
4510 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4511 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4512 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4513 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4514 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4515 && ! find_reg_note (i2, REG_UNUSED,
4516 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4517 for (temp_insn = NEXT_INSN (i2);
4518 temp_insn
4519 && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4520 || BB_HEAD (this_basic_block) != temp_insn);
4521 temp_insn = NEXT_INSN (temp_insn))
4522 if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
4523 FOR_EACH_LOG_LINK (link, temp_insn)
4524 if (link->insn == i2)
4525 link->insn = i3;
4526
4527 if (i3notes)
4528 {
4529 rtx link = i3notes;
4530 while (XEXP (link, 1))
4531 link = XEXP (link, 1);
4532 XEXP (link, 1) = i2notes;
4533 }
4534 else
4535 i3notes = i2notes;
4536 i2notes = 0;
4537 }
4538
4539 LOG_LINKS (i3) = NULL;
4540 REG_NOTES (i3) = 0;
4541 LOG_LINKS (i2) = NULL;
4542 REG_NOTES (i2) = 0;
4543
4544 if (newi2pat)
4545 {
4546 if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch)
4547 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4548 this_basic_block);
4549 INSN_CODE (i2) = i2_code_number;
4550 PATTERN (i2) = newi2pat;
4551 }
4552 else
4553 {
4554 if (MAY_HAVE_DEBUG_BIND_INSNS && i2src)
4555 propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4556 this_basic_block);
4557 SET_INSN_DELETED (i2);
4558 }
4559
4560 if (i1)
4561 {
4562 LOG_LINKS (i1) = NULL;
4563 REG_NOTES (i1) = 0;
4564 if (MAY_HAVE_DEBUG_BIND_INSNS)
4565 propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4566 this_basic_block);
4567 SET_INSN_DELETED (i1);
4568 }
4569
4570 if (i0)
4571 {
4572 LOG_LINKS (i0) = NULL;
4573 REG_NOTES (i0) = 0;
4574 if (MAY_HAVE_DEBUG_BIND_INSNS)
4575 propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4576 this_basic_block);
4577 SET_INSN_DELETED (i0);
4578 }
4579
4580 /* Get death notes for everything that is now used in either I3 or
4581 I2 and used to die in a previous insn. If we built two new
4582 patterns, move from I1 to I2 then I2 to I3 so that we get the
4583 proper movement on registers that I2 modifies. */
4584
4585 if (i0)
4586 from_luid = DF_INSN_LUID (i0);
4587 else if (i1)
4588 from_luid = DF_INSN_LUID (i1);
4589 else
4590 from_luid = DF_INSN_LUID (i2);
4591 if (newi2pat)
4592 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4593 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4594
4595 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4596 if (i3notes)
4597 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4598 elim_i2, elim_i1, elim_i0);
4599 if (i2notes)
4600 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4601 elim_i2, elim_i1, elim_i0);
4602 if (i1notes)
4603 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4604 elim_i2, local_elim_i1, local_elim_i0);
4605 if (i0notes)
4606 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4607 elim_i2, elim_i1, local_elim_i0);
4608 if (midnotes)
4609 distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4610 elim_i2, elim_i1, elim_i0);
4611
4612 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4613 know these are REG_UNUSED and want them to go to the desired insn,
4614 so we always pass it as i3. */
4615
4616 if (newi2pat && new_i2_notes)
4617 distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4618 NULL_RTX);
4619
4620 if (new_i3_notes)
4621 distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4622 NULL_RTX);
4623
4624 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4625 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4626 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4627 in that case, it might delete I2. Similarly for I2 and I1.
4628 Show an additional death due to the REG_DEAD note we make here. If
4629 we discard it in distribute_notes, we will decrement it again. */
4630
4631 if (i3dest_killed)
4632 {
4633 rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4634 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4635 distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4636 elim_i1, elim_i0);
4637 else
4638 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4639 elim_i2, elim_i1, elim_i0);
4640 }
4641
4642 if (i2dest_in_i2src)
4643 {
4644 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4645 if (newi2pat && reg_set_p (i2dest, newi2pat))
4646 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4647 NULL_RTX, NULL_RTX);
4648 else
4649 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4650 NULL_RTX, NULL_RTX, NULL_RTX);
4651 }
4652
4653 if (i1dest_in_i1src)
4654 {
4655 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4656 if (newi2pat && reg_set_p (i1dest, newi2pat))
4657 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4658 NULL_RTX, NULL_RTX);
4659 else
4660 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4661 NULL_RTX, NULL_RTX, NULL_RTX);
4662 }
4663
4664 if (i0dest_in_i0src)
4665 {
4666 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4667 if (newi2pat && reg_set_p (i0dest, newi2pat))
4668 distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4669 NULL_RTX, NULL_RTX);
4670 else
4671 distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4672 NULL_RTX, NULL_RTX, NULL_RTX);
4673 }
4674
4675 distribute_links (i3links);
4676 distribute_links (i2links);
4677 distribute_links (i1links);
4678 distribute_links (i0links);
4679
4680 if (REG_P (i2dest))
4681 {
4682 struct insn_link *link;
4683 rtx_insn *i2_insn = 0;
4684 rtx i2_val = 0, set;
4685
4686 /* The insn that used to set this register doesn't exist, and
4687 this life of the register may not exist either. See if one of
4688 I3's links points to an insn that sets I2DEST. If it does,
4689 that is now the last known value for I2DEST. If we don't update
4690 this and I2 set the register to a value that depended on its old
4691 contents, we will get confused. If this insn is used, thing
4692 will be set correctly in combine_instructions. */
4693 FOR_EACH_LOG_LINK (link, i3)
4694 if ((set = single_set (link->insn)) != 0
4695 && rtx_equal_p (i2dest, SET_DEST (set)))
4696 i2_insn = link->insn, i2_val = SET_SRC (set);
4697
4698 record_value_for_reg (i2dest, i2_insn, i2_val);
4699
4700 /* If the reg formerly set in I2 died only once and that was in I3,
4701 zero its use count so it won't make `reload' do any work. */
4702 if (! added_sets_2
4703 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4704 && ! i2dest_in_i2src
4705 && REGNO (i2dest) < reg_n_sets_max)
4706 INC_REG_N_SETS (REGNO (i2dest), -1);
4707 }
4708
4709 if (i1 && REG_P (i1dest))
4710 {
4711 struct insn_link *link;
4712 rtx_insn *i1_insn = 0;
4713 rtx i1_val = 0, set;
4714
4715 FOR_EACH_LOG_LINK (link, i3)
4716 if ((set = single_set (link->insn)) != 0
4717 && rtx_equal_p (i1dest, SET_DEST (set)))
4718 i1_insn = link->insn, i1_val = SET_SRC (set);
4719
4720 record_value_for_reg (i1dest, i1_insn, i1_val);
4721
4722 if (! added_sets_1
4723 && ! i1dest_in_i1src
4724 && REGNO (i1dest) < reg_n_sets_max)
4725 INC_REG_N_SETS (REGNO (i1dest), -1);
4726 }
4727
4728 if (i0 && REG_P (i0dest))
4729 {
4730 struct insn_link *link;
4731 rtx_insn *i0_insn = 0;
4732 rtx i0_val = 0, set;
4733
4734 FOR_EACH_LOG_LINK (link, i3)
4735 if ((set = single_set (link->insn)) != 0
4736 && rtx_equal_p (i0dest, SET_DEST (set)))
4737 i0_insn = link->insn, i0_val = SET_SRC (set);
4738
4739 record_value_for_reg (i0dest, i0_insn, i0_val);
4740
4741 if (! added_sets_0
4742 && ! i0dest_in_i0src
4743 && REGNO (i0dest) < reg_n_sets_max)
4744 INC_REG_N_SETS (REGNO (i0dest), -1);
4745 }
4746
4747 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4748 been made to this insn. The order is important, because newi2pat
4749 can affect nonzero_bits of newpat. */
4750 if (newi2pat)
4751 note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4752 note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4753 }
4754
4755 if (undobuf.other_insn != NULL_RTX)
4756 {
4757 if (dump_file)
4758 {
4759 fprintf (dump_file, "modifying other_insn ");
4760 dump_insn_slim (dump_file, undobuf.other_insn);
4761 }
4762 df_insn_rescan (undobuf.other_insn);
4763 }
4764
4765 if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4766 {
4767 if (dump_file)
4768 {
4769 fprintf (dump_file, "modifying insn i0 ");
4770 dump_insn_slim (dump_file, i0);
4771 }
4772 df_insn_rescan (i0);
4773 }
4774
4775 if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4776 {
4777 if (dump_file)
4778 {
4779 fprintf (dump_file, "modifying insn i1 ");
4780 dump_insn_slim (dump_file, i1);
4781 }
4782 df_insn_rescan (i1);
4783 }
4784
4785 if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4786 {
4787 if (dump_file)
4788 {
4789 fprintf (dump_file, "modifying insn i2 ");
4790 dump_insn_slim (dump_file, i2);
4791 }
4792 df_insn_rescan (i2);
4793 }
4794
4795 if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4796 {
4797 if (dump_file)
4798 {
4799 fprintf (dump_file, "modifying insn i3 ");
4800 dump_insn_slim (dump_file, i3);
4801 }
4802 df_insn_rescan (i3);
4803 }
4804
4805 /* Set new_direct_jump_p if a new return or simple jump instruction
4806 has been created. Adjust the CFG accordingly. */
4807 if (returnjump_p (i3) || any_uncondjump_p (i3))
4808 {
4809 *new_direct_jump_p = 1;
4810 mark_jump_label (PATTERN (i3), i3, 0);
4811 update_cfg_for_uncondjump (i3);
4812 }
4813
4814 if (undobuf.other_insn != NULL_RTX
4815 && (returnjump_p (undobuf.other_insn)
4816 || any_uncondjump_p (undobuf.other_insn)))
4817 {
4818 *new_direct_jump_p = 1;
4819 update_cfg_for_uncondjump (undobuf.other_insn);
4820 }
4821
4822 if (GET_CODE (PATTERN (i3)) == TRAP_IF
4823 && XEXP (PATTERN (i3), 0) == const1_rtx)
4824 {
4825 basic_block bb = BLOCK_FOR_INSN (i3);
4826 gcc_assert (bb);
4827 remove_edge (split_block (bb, i3));
4828 emit_barrier_after_bb (bb);
4829 *new_direct_jump_p = 1;
4830 }
4831
4832 if (undobuf.other_insn
4833 && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF
4834 && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx)
4835 {
4836 basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn);
4837 gcc_assert (bb);
4838 remove_edge (split_block (bb, undobuf.other_insn));
4839 emit_barrier_after_bb (bb);
4840 *new_direct_jump_p = 1;
4841 }
4842
4843 /* A noop might also need cleaning up of CFG, if it comes from the
4844 simplification of a jump. */
4845 if (JUMP_P (i3)
4846 && GET_CODE (newpat) == SET
4847 && SET_SRC (newpat) == pc_rtx
4848 && SET_DEST (newpat) == pc_rtx)
4849 {
4850 *new_direct_jump_p = 1;
4851 update_cfg_for_uncondjump (i3);
4852 }
4853
4854 if (undobuf.other_insn != NULL_RTX
4855 && JUMP_P (undobuf.other_insn)
4856 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4857 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4858 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4859 {
4860 *new_direct_jump_p = 1;
4861 update_cfg_for_uncondjump (undobuf.other_insn);
4862 }
4863
4864 combine_successes++;
4865 undo_commit ();
4866
4867 rtx_insn *ret = newi2pat ? i2 : i3;
4868 if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret))
4869 ret = added_links_insn;
4870 if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret))
4871 ret = added_notes_insn;
4872
4873 return ret;
4874 }
4875
4876 /* Get a marker for undoing to the current state. */
4877
4878 static void *
get_undo_marker(void)4879 get_undo_marker (void)
4880 {
4881 return undobuf.undos;
4882 }
4883
4884 /* Undo the modifications up to the marker. */
4885
4886 static void
undo_to_marker(void * marker)4887 undo_to_marker (void *marker)
4888 {
4889 struct undo *undo, *next;
4890
4891 for (undo = undobuf.undos; undo != marker; undo = next)
4892 {
4893 gcc_assert (undo);
4894
4895 next = undo->next;
4896 switch (undo->kind)
4897 {
4898 case UNDO_RTX:
4899 *undo->where.r = undo->old_contents.r;
4900 break;
4901 case UNDO_INT:
4902 *undo->where.i = undo->old_contents.i;
4903 break;
4904 case UNDO_MODE:
4905 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4906 break;
4907 case UNDO_LINKS:
4908 *undo->where.l = undo->old_contents.l;
4909 break;
4910 default:
4911 gcc_unreachable ();
4912 }
4913
4914 undo->next = undobuf.frees;
4915 undobuf.frees = undo;
4916 }
4917
4918 undobuf.undos = (struct undo *) marker;
4919 }
4920
4921 /* Undo all the modifications recorded in undobuf. */
4922
4923 static void
undo_all(void)4924 undo_all (void)
4925 {
4926 undo_to_marker (0);
4927 }
4928
4929 /* We've committed to accepting the changes we made. Move all
4930 of the undos to the free list. */
4931
4932 static void
undo_commit(void)4933 undo_commit (void)
4934 {
4935 struct undo *undo, *next;
4936
4937 for (undo = undobuf.undos; undo; undo = next)
4938 {
4939 next = undo->next;
4940 undo->next = undobuf.frees;
4941 undobuf.frees = undo;
4942 }
4943 undobuf.undos = 0;
4944 }
4945
4946 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4947 where we have an arithmetic expression and return that point. LOC will
4948 be inside INSN.
4949
4950 try_combine will call this function to see if an insn can be split into
4951 two insns. */
4952
4953 static rtx *
find_split_point(rtx * loc,rtx_insn * insn,bool set_src)4954 find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4955 {
4956 rtx x = *loc;
4957 enum rtx_code code = GET_CODE (x);
4958 rtx *split;
4959 unsigned HOST_WIDE_INT len = 0;
4960 HOST_WIDE_INT pos = 0;
4961 int unsignedp = 0;
4962 rtx inner = NULL_RTX;
4963 scalar_int_mode mode, inner_mode;
4964
4965 /* First special-case some codes. */
4966 switch (code)
4967 {
4968 case SUBREG:
4969 #ifdef INSN_SCHEDULING
4970 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4971 point. */
4972 if (MEM_P (SUBREG_REG (x)))
4973 return loc;
4974 #endif
4975 return find_split_point (&SUBREG_REG (x), insn, false);
4976
4977 case MEM:
4978 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4979 using LO_SUM and HIGH. */
4980 if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4981 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4982 {
4983 machine_mode address_mode = get_address_mode (x);
4984
4985 SUBST (XEXP (x, 0),
4986 gen_rtx_LO_SUM (address_mode,
4987 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4988 XEXP (x, 0)));
4989 return &XEXP (XEXP (x, 0), 0);
4990 }
4991
4992 /* If we have a PLUS whose second operand is a constant and the
4993 address is not valid, perhaps we can split it up using
4994 the machine-specific way to split large constants. We use
4995 the first pseudo-reg (one of the virtual regs) as a placeholder;
4996 it will not remain in the result. */
4997 if (GET_CODE (XEXP (x, 0)) == PLUS
4998 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4999 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5000 MEM_ADDR_SPACE (x)))
5001 {
5002 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
5003 rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
5004 subst_insn);
5005
5006 /* This should have produced two insns, each of which sets our
5007 placeholder. If the source of the second is a valid address,
5008 we can put both sources together and make a split point
5009 in the middle. */
5010
5011 if (seq
5012 && NEXT_INSN (seq) != NULL_RTX
5013 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
5014 && NONJUMP_INSN_P (seq)
5015 && GET_CODE (PATTERN (seq)) == SET
5016 && SET_DEST (PATTERN (seq)) == reg
5017 && ! reg_mentioned_p (reg,
5018 SET_SRC (PATTERN (seq)))
5019 && NONJUMP_INSN_P (NEXT_INSN (seq))
5020 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
5021 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
5022 && memory_address_addr_space_p
5023 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
5024 MEM_ADDR_SPACE (x)))
5025 {
5026 rtx src1 = SET_SRC (PATTERN (seq));
5027 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
5028
5029 /* Replace the placeholder in SRC2 with SRC1. If we can
5030 find where in SRC2 it was placed, that can become our
5031 split point and we can replace this address with SRC2.
5032 Just try two obvious places. */
5033
5034 src2 = replace_rtx (src2, reg, src1);
5035 split = 0;
5036 if (XEXP (src2, 0) == src1)
5037 split = &XEXP (src2, 0);
5038 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
5039 && XEXP (XEXP (src2, 0), 0) == src1)
5040 split = &XEXP (XEXP (src2, 0), 0);
5041
5042 if (split)
5043 {
5044 SUBST (XEXP (x, 0), src2);
5045 return split;
5046 }
5047 }
5048
5049 /* If that didn't work and we have a nested plus, like:
5050 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
5051 is valid address, try to split (REG1 * CONST1). */
5052 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
5053 && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
5054 && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5055 && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
5056 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
5057 0), 0)))))
5058 {
5059 rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0);
5060 XEXP (XEXP (XEXP (x, 0), 0), 0) = reg;
5061 if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5062 MEM_ADDR_SPACE (x)))
5063 {
5064 XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
5065 return &XEXP (XEXP (XEXP (x, 0), 0), 0);
5066 }
5067 XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
5068 }
5069 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
5070 && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
5071 && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5072 && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
5073 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
5074 0), 1)))))
5075 {
5076 rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1);
5077 XEXP (XEXP (XEXP (x, 0), 0), 1) = reg;
5078 if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5079 MEM_ADDR_SPACE (x)))
5080 {
5081 XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5082 return &XEXP (XEXP (XEXP (x, 0), 0), 1);
5083 }
5084 XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5085 }
5086
5087 /* If that didn't work, perhaps the first operand is complex and
5088 needs to be computed separately, so make a split point there.
5089 This will occur on machines that just support REG + CONST
5090 and have a constant moved through some previous computation. */
5091 if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
5092 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5093 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5094 return &XEXP (XEXP (x, 0), 0);
5095 }
5096
5097 /* If we have a PLUS whose first operand is complex, try computing it
5098 separately by making a split there. */
5099 if (GET_CODE (XEXP (x, 0)) == PLUS
5100 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5101 MEM_ADDR_SPACE (x))
5102 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
5103 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5104 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5105 return &XEXP (XEXP (x, 0), 0);
5106 break;
5107
5108 case SET:
5109 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5110 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5111 we need to put the operand into a register. So split at that
5112 point. */
5113
5114 if (SET_DEST (x) == cc0_rtx
5115 && GET_CODE (SET_SRC (x)) != COMPARE
5116 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
5117 && !OBJECT_P (SET_SRC (x))
5118 && ! (GET_CODE (SET_SRC (x)) == SUBREG
5119 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
5120 return &SET_SRC (x);
5121
5122 /* See if we can split SET_SRC as it stands. */
5123 split = find_split_point (&SET_SRC (x), insn, true);
5124 if (split && split != &SET_SRC (x))
5125 return split;
5126
5127 /* See if we can split SET_DEST as it stands. */
5128 split = find_split_point (&SET_DEST (x), insn, false);
5129 if (split && split != &SET_DEST (x))
5130 return split;
5131
5132 /* See if this is a bitfield assignment with everything constant. If
5133 so, this is an IOR of an AND, so split it into that. */
5134 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5135 && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)),
5136 &inner_mode)
5137 && HWI_COMPUTABLE_MODE_P (inner_mode)
5138 && CONST_INT_P (XEXP (SET_DEST (x), 1))
5139 && CONST_INT_P (XEXP (SET_DEST (x), 2))
5140 && CONST_INT_P (SET_SRC (x))
5141 && ((INTVAL (XEXP (SET_DEST (x), 1))
5142 + INTVAL (XEXP (SET_DEST (x), 2)))
5143 <= GET_MODE_PRECISION (inner_mode))
5144 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
5145 {
5146 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
5147 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
5148 rtx dest = XEXP (SET_DEST (x), 0);
5149 unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << len) - 1;
5150 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)) & mask;
5151 rtx or_mask;
5152
5153 if (BITS_BIG_ENDIAN)
5154 pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5155
5156 or_mask = gen_int_mode (src << pos, inner_mode);
5157 if (src == mask)
5158 SUBST (SET_SRC (x),
5159 simplify_gen_binary (IOR, inner_mode, dest, or_mask));
5160 else
5161 {
5162 rtx negmask = gen_int_mode (~(mask << pos), inner_mode);
5163 SUBST (SET_SRC (x),
5164 simplify_gen_binary (IOR, inner_mode,
5165 simplify_gen_binary (AND, inner_mode,
5166 dest, negmask),
5167 or_mask));
5168 }
5169
5170 SUBST (SET_DEST (x), dest);
5171
5172 split = find_split_point (&SET_SRC (x), insn, true);
5173 if (split && split != &SET_SRC (x))
5174 return split;
5175 }
5176
5177 /* Otherwise, see if this is an operation that we can split into two.
5178 If so, try to split that. */
5179 code = GET_CODE (SET_SRC (x));
5180
5181 switch (code)
5182 {
5183 case AND:
5184 /* If we are AND'ing with a large constant that is only a single
5185 bit and the result is only being used in a context where we
5186 need to know if it is zero or nonzero, replace it with a bit
5187 extraction. This will avoid the large constant, which might
5188 have taken more than one insn to make. If the constant were
5189 not a valid argument to the AND but took only one insn to make,
5190 this is no worse, but if it took more than one insn, it will
5191 be better. */
5192
5193 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
5194 && REG_P (XEXP (SET_SRC (x), 0))
5195 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
5196 && REG_P (SET_DEST (x))
5197 && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
5198 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
5199 && XEXP (*split, 0) == SET_DEST (x)
5200 && XEXP (*split, 1) == const0_rtx)
5201 {
5202 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
5203 XEXP (SET_SRC (x), 0),
5204 pos, NULL_RTX, 1, 1, 0, 0);
5205 if (extraction != 0)
5206 {
5207 SUBST (SET_SRC (x), extraction);
5208 return find_split_point (loc, insn, false);
5209 }
5210 }
5211 break;
5212
5213 case NE:
5214 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5215 is known to be on, this can be converted into a NEG of a shift. */
5216 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
5217 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
5218 && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0),
5219 GET_MODE (XEXP (SET_SRC (x),
5220 0))))) >= 1))
5221 {
5222 machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
5223 rtx pos_rtx = gen_int_shift_amount (mode, pos);
5224 SUBST (SET_SRC (x),
5225 gen_rtx_NEG (mode,
5226 gen_rtx_LSHIFTRT (mode,
5227 XEXP (SET_SRC (x), 0),
5228 pos_rtx)));
5229
5230 split = find_split_point (&SET_SRC (x), insn, true);
5231 if (split && split != &SET_SRC (x))
5232 return split;
5233 }
5234 break;
5235
5236 case SIGN_EXTEND:
5237 inner = XEXP (SET_SRC (x), 0);
5238
5239 /* We can't optimize if either mode is a partial integer
5240 mode as we don't know how many bits are significant
5241 in those modes. */
5242 if (!is_int_mode (GET_MODE (inner), &inner_mode)
5243 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
5244 break;
5245
5246 pos = 0;
5247 len = GET_MODE_PRECISION (inner_mode);
5248 unsignedp = 0;
5249 break;
5250
5251 case SIGN_EXTRACT:
5252 case ZERO_EXTRACT:
5253 if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)),
5254 &inner_mode)
5255 && CONST_INT_P (XEXP (SET_SRC (x), 1))
5256 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
5257 {
5258 inner = XEXP (SET_SRC (x), 0);
5259 len = INTVAL (XEXP (SET_SRC (x), 1));
5260 pos = INTVAL (XEXP (SET_SRC (x), 2));
5261
5262 if (BITS_BIG_ENDIAN)
5263 pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5264 unsignedp = (code == ZERO_EXTRACT);
5265 }
5266 break;
5267
5268 default:
5269 break;
5270 }
5271
5272 if (len
5273 && known_subrange_p (pos, len,
5274 0, GET_MODE_PRECISION (GET_MODE (inner)))
5275 && is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode))
5276 {
5277 /* For unsigned, we have a choice of a shift followed by an
5278 AND or two shifts. Use two shifts for field sizes where the
5279 constant might be too large. We assume here that we can
5280 always at least get 8-bit constants in an AND insn, which is
5281 true for every current RISC. */
5282
5283 if (unsignedp && len <= 8)
5284 {
5285 unsigned HOST_WIDE_INT mask
5286 = (HOST_WIDE_INT_1U << len) - 1;
5287 rtx pos_rtx = gen_int_shift_amount (mode, pos);
5288 SUBST (SET_SRC (x),
5289 gen_rtx_AND (mode,
5290 gen_rtx_LSHIFTRT
5291 (mode, gen_lowpart (mode, inner), pos_rtx),
5292 gen_int_mode (mask, mode)));
5293
5294 split = find_split_point (&SET_SRC (x), insn, true);
5295 if (split && split != &SET_SRC (x))
5296 return split;
5297 }
5298 else
5299 {
5300 int left_bits = GET_MODE_PRECISION (mode) - len - pos;
5301 int right_bits = GET_MODE_PRECISION (mode) - len;
5302 SUBST (SET_SRC (x),
5303 gen_rtx_fmt_ee
5304 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5305 gen_rtx_ASHIFT (mode,
5306 gen_lowpart (mode, inner),
5307 gen_int_shift_amount (mode, left_bits)),
5308 gen_int_shift_amount (mode, right_bits)));
5309
5310 split = find_split_point (&SET_SRC (x), insn, true);
5311 if (split && split != &SET_SRC (x))
5312 return split;
5313 }
5314 }
5315
5316 /* See if this is a simple operation with a constant as the second
5317 operand. It might be that this constant is out of range and hence
5318 could be used as a split point. */
5319 if (BINARY_P (SET_SRC (x))
5320 && CONSTANT_P (XEXP (SET_SRC (x), 1))
5321 && (OBJECT_P (XEXP (SET_SRC (x), 0))
5322 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5323 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5324 return &XEXP (SET_SRC (x), 1);
5325
5326 /* Finally, see if this is a simple operation with its first operand
5327 not in a register. The operation might require this operand in a
5328 register, so return it as a split point. We can always do this
5329 because if the first operand were another operation, we would have
5330 already found it as a split point. */
5331 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5332 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5333 return &XEXP (SET_SRC (x), 0);
5334
5335 return 0;
5336
5337 case AND:
5338 case IOR:
5339 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5340 it is better to write this as (not (ior A B)) so we can split it.
5341 Similarly for IOR. */
5342 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5343 {
5344 SUBST (*loc,
5345 gen_rtx_NOT (GET_MODE (x),
5346 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5347 GET_MODE (x),
5348 XEXP (XEXP (x, 0), 0),
5349 XEXP (XEXP (x, 1), 0))));
5350 return find_split_point (loc, insn, set_src);
5351 }
5352
5353 /* Many RISC machines have a large set of logical insns. If the
5354 second operand is a NOT, put it first so we will try to split the
5355 other operand first. */
5356 if (GET_CODE (XEXP (x, 1)) == NOT)
5357 {
5358 rtx tem = XEXP (x, 0);
5359 SUBST (XEXP (x, 0), XEXP (x, 1));
5360 SUBST (XEXP (x, 1), tem);
5361 }
5362 break;
5363
5364 case PLUS:
5365 case MINUS:
5366 /* Canonicalization can produce (minus A (mult B C)), where C is a
5367 constant. It may be better to try splitting (plus (mult B -C) A)
5368 instead if this isn't a multiply by a power of two. */
5369 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5370 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5371 && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
5372 {
5373 machine_mode mode = GET_MODE (x);
5374 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5375 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5376 SUBST (*loc, gen_rtx_PLUS (mode,
5377 gen_rtx_MULT (mode,
5378 XEXP (XEXP (x, 1), 0),
5379 gen_int_mode (other_int,
5380 mode)),
5381 XEXP (x, 0)));
5382 return find_split_point (loc, insn, set_src);
5383 }
5384
5385 /* Split at a multiply-accumulate instruction. However if this is
5386 the SET_SRC, we likely do not have such an instruction and it's
5387 worthless to try this split. */
5388 if (!set_src
5389 && (GET_CODE (XEXP (x, 0)) == MULT
5390 || (GET_CODE (XEXP (x, 0)) == ASHIFT
5391 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5392 return loc;
5393
5394 default:
5395 break;
5396 }
5397
5398 /* Otherwise, select our actions depending on our rtx class. */
5399 switch (GET_RTX_CLASS (code))
5400 {
5401 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5402 case RTX_TERNARY:
5403 split = find_split_point (&XEXP (x, 2), insn, false);
5404 if (split)
5405 return split;
5406 /* fall through */
5407 case RTX_BIN_ARITH:
5408 case RTX_COMM_ARITH:
5409 case RTX_COMPARE:
5410 case RTX_COMM_COMPARE:
5411 split = find_split_point (&XEXP (x, 1), insn, false);
5412 if (split)
5413 return split;
5414 /* fall through */
5415 case RTX_UNARY:
5416 /* Some machines have (and (shift ...) ...) insns. If X is not
5417 an AND, but XEXP (X, 0) is, use it as our split point. */
5418 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5419 return &XEXP (x, 0);
5420
5421 split = find_split_point (&XEXP (x, 0), insn, false);
5422 if (split)
5423 return split;
5424 return loc;
5425
5426 default:
5427 /* Otherwise, we don't have a split point. */
5428 return 0;
5429 }
5430 }
5431
5432 /* Throughout X, replace FROM with TO, and return the result.
5433 The result is TO if X is FROM;
5434 otherwise the result is X, but its contents may have been modified.
5435 If they were modified, a record was made in undobuf so that
5436 undo_all will (among other things) return X to its original state.
5437
5438 If the number of changes necessary is too much to record to undo,
5439 the excess changes are not made, so the result is invalid.
5440 The changes already made can still be undone.
5441 undobuf.num_undo is incremented for such changes, so by testing that
5442 the caller can tell whether the result is valid.
5443
5444 `n_occurrences' is incremented each time FROM is replaced.
5445
5446 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5447
5448 IN_COND is nonzero if we are at the top level of a condition.
5449
5450 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5451 by copying if `n_occurrences' is nonzero. */
5452
5453 static rtx
subst(rtx x,rtx from,rtx to,int in_dest,int in_cond,int unique_copy)5454 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
5455 {
5456 enum rtx_code code = GET_CODE (x);
5457 machine_mode op0_mode = VOIDmode;
5458 const char *fmt;
5459 int len, i;
5460 rtx new_rtx;
5461
5462 /* Two expressions are equal if they are identical copies of a shared
5463 RTX or if they are both registers with the same register number
5464 and mode. */
5465
5466 #define COMBINE_RTX_EQUAL_P(X,Y) \
5467 ((X) == (Y) \
5468 || (REG_P (X) && REG_P (Y) \
5469 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5470
5471 /* Do not substitute into clobbers of regs -- this will never result in
5472 valid RTL. */
5473 if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5474 return x;
5475
5476 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5477 {
5478 n_occurrences++;
5479 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5480 }
5481
5482 /* If X and FROM are the same register but different modes, they
5483 will not have been seen as equal above. However, the log links code
5484 will make a LOG_LINKS entry for that case. If we do nothing, we
5485 will try to rerecognize our original insn and, when it succeeds,
5486 we will delete the feeding insn, which is incorrect.
5487
5488 So force this insn not to match in this (rare) case. */
5489 if (! in_dest && code == REG && REG_P (from)
5490 && reg_overlap_mentioned_p (x, from))
5491 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5492
5493 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5494 of which may contain things that can be combined. */
5495 if (code != MEM && code != LO_SUM && OBJECT_P (x))
5496 return x;
5497
5498 /* It is possible to have a subexpression appear twice in the insn.
5499 Suppose that FROM is a register that appears within TO.
5500 Then, after that subexpression has been scanned once by `subst',
5501 the second time it is scanned, TO may be found. If we were
5502 to scan TO here, we would find FROM within it and create a
5503 self-referent rtl structure which is completely wrong. */
5504 if (COMBINE_RTX_EQUAL_P (x, to))
5505 return to;
5506
5507 /* Parallel asm_operands need special attention because all of the
5508 inputs are shared across the arms. Furthermore, unsharing the
5509 rtl results in recognition failures. Failure to handle this case
5510 specially can result in circular rtl.
5511
5512 Solve this by doing a normal pass across the first entry of the
5513 parallel, and only processing the SET_DESTs of the subsequent
5514 entries. Ug. */
5515
5516 if (code == PARALLEL
5517 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5518 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5519 {
5520 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5521
5522 /* If this substitution failed, this whole thing fails. */
5523 if (GET_CODE (new_rtx) == CLOBBER
5524 && XEXP (new_rtx, 0) == const0_rtx)
5525 return new_rtx;
5526
5527 SUBST (XVECEXP (x, 0, 0), new_rtx);
5528
5529 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5530 {
5531 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5532
5533 if (!REG_P (dest)
5534 && GET_CODE (dest) != CC0
5535 && GET_CODE (dest) != PC)
5536 {
5537 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5538
5539 /* If this substitution failed, this whole thing fails. */
5540 if (GET_CODE (new_rtx) == CLOBBER
5541 && XEXP (new_rtx, 0) == const0_rtx)
5542 return new_rtx;
5543
5544 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5545 }
5546 }
5547 }
5548 else
5549 {
5550 len = GET_RTX_LENGTH (code);
5551 fmt = GET_RTX_FORMAT (code);
5552
5553 /* We don't need to process a SET_DEST that is a register, CC0,
5554 or PC, so set up to skip this common case. All other cases
5555 where we want to suppress replacing something inside a
5556 SET_SRC are handled via the IN_DEST operand. */
5557 if (code == SET
5558 && (REG_P (SET_DEST (x))
5559 || GET_CODE (SET_DEST (x)) == CC0
5560 || GET_CODE (SET_DEST (x)) == PC))
5561 fmt = "ie";
5562
5563 /* Trying to simplify the operands of a widening MULT is not likely
5564 to create RTL matching a machine insn. */
5565 if (code == MULT
5566 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5567 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5568 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5569 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5570 && REG_P (XEXP (XEXP (x, 0), 0))
5571 && REG_P (XEXP (XEXP (x, 1), 0))
5572 && from == to)
5573 return x;
5574
5575
5576 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5577 constant. */
5578 if (fmt[0] == 'e')
5579 op0_mode = GET_MODE (XEXP (x, 0));
5580
5581 for (i = 0; i < len; i++)
5582 {
5583 if (fmt[i] == 'E')
5584 {
5585 int j;
5586 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5587 {
5588 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5589 {
5590 new_rtx = (unique_copy && n_occurrences
5591 ? copy_rtx (to) : to);
5592 n_occurrences++;
5593 }
5594 else
5595 {
5596 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5597 unique_copy);
5598
5599 /* If this substitution failed, this whole thing
5600 fails. */
5601 if (GET_CODE (new_rtx) == CLOBBER
5602 && XEXP (new_rtx, 0) == const0_rtx)
5603 return new_rtx;
5604 }
5605
5606 SUBST (XVECEXP (x, i, j), new_rtx);
5607 }
5608 }
5609 else if (fmt[i] == 'e')
5610 {
5611 /* If this is a register being set, ignore it. */
5612 new_rtx = XEXP (x, i);
5613 if (in_dest
5614 && i == 0
5615 && (((code == SUBREG || code == ZERO_EXTRACT)
5616 && REG_P (new_rtx))
5617 || code == STRICT_LOW_PART))
5618 ;
5619
5620 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5621 {
5622 /* In general, don't install a subreg involving two
5623 modes not tieable. It can worsen register
5624 allocation, and can even make invalid reload
5625 insns, since the reg inside may need to be copied
5626 from in the outside mode, and that may be invalid
5627 if it is an fp reg copied in integer mode.
5628
5629 We allow two exceptions to this: It is valid if
5630 it is inside another SUBREG and the mode of that
5631 SUBREG and the mode of the inside of TO is
5632 tieable and it is valid if X is a SET that copies
5633 FROM to CC0. */
5634
5635 if (GET_CODE (to) == SUBREG
5636 && !targetm.modes_tieable_p (GET_MODE (to),
5637 GET_MODE (SUBREG_REG (to)))
5638 && ! (code == SUBREG
5639 && (targetm.modes_tieable_p
5640 (GET_MODE (x), GET_MODE (SUBREG_REG (to)))))
5641 && (!HAVE_cc0
5642 || (! (code == SET
5643 && i == 1
5644 && XEXP (x, 0) == cc0_rtx))))
5645 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5646
5647 if (code == SUBREG
5648 && REG_P (to)
5649 && REGNO (to) < FIRST_PSEUDO_REGISTER
5650 && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5651 SUBREG_BYTE (x),
5652 GET_MODE (x)) < 0)
5653 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5654
5655 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5656 n_occurrences++;
5657 }
5658 else
5659 /* If we are in a SET_DEST, suppress most cases unless we
5660 have gone inside a MEM, in which case we want to
5661 simplify the address. We assume here that things that
5662 are actually part of the destination have their inner
5663 parts in the first expression. This is true for SUBREG,
5664 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5665 things aside from REG and MEM that should appear in a
5666 SET_DEST. */
5667 new_rtx = subst (XEXP (x, i), from, to,
5668 (((in_dest
5669 && (code == SUBREG || code == STRICT_LOW_PART
5670 || code == ZERO_EXTRACT))
5671 || code == SET)
5672 && i == 0),
5673 code == IF_THEN_ELSE && i == 0,
5674 unique_copy);
5675
5676 /* If we found that we will have to reject this combination,
5677 indicate that by returning the CLOBBER ourselves, rather than
5678 an expression containing it. This will speed things up as
5679 well as prevent accidents where two CLOBBERs are considered
5680 to be equal, thus producing an incorrect simplification. */
5681
5682 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5683 return new_rtx;
5684
5685 if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5686 {
5687 machine_mode mode = GET_MODE (x);
5688
5689 x = simplify_subreg (GET_MODE (x), new_rtx,
5690 GET_MODE (SUBREG_REG (x)),
5691 SUBREG_BYTE (x));
5692 if (! x)
5693 x = gen_rtx_CLOBBER (mode, const0_rtx);
5694 }
5695 else if (CONST_SCALAR_INT_P (new_rtx)
5696 && (GET_CODE (x) == ZERO_EXTEND
5697 || GET_CODE (x) == SIGN_EXTEND
5698 || GET_CODE (x) == FLOAT
5699 || GET_CODE (x) == UNSIGNED_FLOAT))
5700 {
5701 x = simplify_unary_operation (GET_CODE (x), GET_MODE (x),
5702 new_rtx,
5703 GET_MODE (XEXP (x, 0)));
5704 if (!x)
5705 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5706 }
5707 else
5708 SUBST (XEXP (x, i), new_rtx);
5709 }
5710 }
5711 }
5712
5713 /* Check if we are loading something from the constant pool via float
5714 extension; in this case we would undo compress_float_constant
5715 optimization and degenerate constant load to an immediate value. */
5716 if (GET_CODE (x) == FLOAT_EXTEND
5717 && MEM_P (XEXP (x, 0))
5718 && MEM_READONLY_P (XEXP (x, 0)))
5719 {
5720 rtx tmp = avoid_constant_pool_reference (x);
5721 if (x != tmp)
5722 return x;
5723 }
5724
5725 /* Try to simplify X. If the simplification changed the code, it is likely
5726 that further simplification will help, so loop, but limit the number
5727 of repetitions that will be performed. */
5728
5729 for (i = 0; i < 4; i++)
5730 {
5731 /* If X is sufficiently simple, don't bother trying to do anything
5732 with it. */
5733 if (code != CONST_INT && code != REG && code != CLOBBER)
5734 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5735
5736 if (GET_CODE (x) == code)
5737 break;
5738
5739 code = GET_CODE (x);
5740
5741 /* We no longer know the original mode of operand 0 since we
5742 have changed the form of X) */
5743 op0_mode = VOIDmode;
5744 }
5745
5746 return x;
5747 }
5748
5749 /* If X is a commutative operation whose operands are not in the canonical
5750 order, use substitutions to swap them. */
5751
5752 static void
maybe_swap_commutative_operands(rtx x)5753 maybe_swap_commutative_operands (rtx x)
5754 {
5755 if (COMMUTATIVE_ARITH_P (x)
5756 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5757 {
5758 rtx temp = XEXP (x, 0);
5759 SUBST (XEXP (x, 0), XEXP (x, 1));
5760 SUBST (XEXP (x, 1), temp);
5761 }
5762 }
5763
5764 /* Simplify X, a piece of RTL. We just operate on the expression at the
5765 outer level; call `subst' to simplify recursively. Return the new
5766 expression.
5767
5768 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5769 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5770 of a condition. */
5771
5772 static rtx
combine_simplify_rtx(rtx x,machine_mode op0_mode,int in_dest,int in_cond)5773 combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
5774 int in_cond)
5775 {
5776 enum rtx_code code = GET_CODE (x);
5777 machine_mode mode = GET_MODE (x);
5778 scalar_int_mode int_mode;
5779 rtx temp;
5780 int i;
5781
5782 /* If this is a commutative operation, put a constant last and a complex
5783 expression first. We don't need to do this for comparisons here. */
5784 maybe_swap_commutative_operands (x);
5785
5786 /* Try to fold this expression in case we have constants that weren't
5787 present before. */
5788 temp = 0;
5789 switch (GET_RTX_CLASS (code))
5790 {
5791 case RTX_UNARY:
5792 if (op0_mode == VOIDmode)
5793 op0_mode = GET_MODE (XEXP (x, 0));
5794 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5795 break;
5796 case RTX_COMPARE:
5797 case RTX_COMM_COMPARE:
5798 {
5799 machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5800 if (cmp_mode == VOIDmode)
5801 {
5802 cmp_mode = GET_MODE (XEXP (x, 1));
5803 if (cmp_mode == VOIDmode)
5804 cmp_mode = op0_mode;
5805 }
5806 temp = simplify_relational_operation (code, mode, cmp_mode,
5807 XEXP (x, 0), XEXP (x, 1));
5808 }
5809 break;
5810 case RTX_COMM_ARITH:
5811 case RTX_BIN_ARITH:
5812 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5813 break;
5814 case RTX_BITFIELD_OPS:
5815 case RTX_TERNARY:
5816 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5817 XEXP (x, 1), XEXP (x, 2));
5818 break;
5819 default:
5820 break;
5821 }
5822
5823 if (temp)
5824 {
5825 x = temp;
5826 code = GET_CODE (temp);
5827 op0_mode = VOIDmode;
5828 mode = GET_MODE (temp);
5829 }
5830
5831 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5832 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5833 things. Check for cases where both arms are testing the same
5834 condition.
5835
5836 Don't do anything if all operands are very simple. */
5837
5838 if ((BINARY_P (x)
5839 && ((!OBJECT_P (XEXP (x, 0))
5840 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5841 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5842 || (!OBJECT_P (XEXP (x, 1))
5843 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5844 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5845 || (UNARY_P (x)
5846 && (!OBJECT_P (XEXP (x, 0))
5847 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5848 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5849 {
5850 rtx cond, true_rtx, false_rtx;
5851
5852 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5853 if (cond != 0
5854 /* If everything is a comparison, what we have is highly unlikely
5855 to be simpler, so don't use it. */
5856 && ! (COMPARISON_P (x)
5857 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))
5858 /* Similarly, if we end up with one of the expressions the same
5859 as the original, it is certainly not simpler. */
5860 && ! rtx_equal_p (x, true_rtx)
5861 && ! rtx_equal_p (x, false_rtx))
5862 {
5863 rtx cop1 = const0_rtx;
5864 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5865
5866 if (cond_code == NE && COMPARISON_P (cond))
5867 return x;
5868
5869 /* Simplify the alternative arms; this may collapse the true and
5870 false arms to store-flag values. Be careful to use copy_rtx
5871 here since true_rtx or false_rtx might share RTL with x as a
5872 result of the if_then_else_cond call above. */
5873 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5874 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5875
5876 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5877 is unlikely to be simpler. */
5878 if (general_operand (true_rtx, VOIDmode)
5879 && general_operand (false_rtx, VOIDmode))
5880 {
5881 enum rtx_code reversed;
5882
5883 /* Restarting if we generate a store-flag expression will cause
5884 us to loop. Just drop through in this case. */
5885
5886 /* If the result values are STORE_FLAG_VALUE and zero, we can
5887 just make the comparison operation. */
5888 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5889 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5890 cond, cop1);
5891 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5892 && ((reversed = reversed_comparison_code_parts
5893 (cond_code, cond, cop1, NULL))
5894 != UNKNOWN))
5895 x = simplify_gen_relational (reversed, mode, VOIDmode,
5896 cond, cop1);
5897
5898 /* Likewise, we can make the negate of a comparison operation
5899 if the result values are - STORE_FLAG_VALUE and zero. */
5900 else if (CONST_INT_P (true_rtx)
5901 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5902 && false_rtx == const0_rtx)
5903 x = simplify_gen_unary (NEG, mode,
5904 simplify_gen_relational (cond_code,
5905 mode, VOIDmode,
5906 cond, cop1),
5907 mode);
5908 else if (CONST_INT_P (false_rtx)
5909 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5910 && true_rtx == const0_rtx
5911 && ((reversed = reversed_comparison_code_parts
5912 (cond_code, cond, cop1, NULL))
5913 != UNKNOWN))
5914 x = simplify_gen_unary (NEG, mode,
5915 simplify_gen_relational (reversed,
5916 mode, VOIDmode,
5917 cond, cop1),
5918 mode);
5919
5920 code = GET_CODE (x);
5921 op0_mode = VOIDmode;
5922 }
5923 }
5924 }
5925
5926 /* First see if we can apply the inverse distributive law. */
5927 if (code == PLUS || code == MINUS
5928 || code == AND || code == IOR || code == XOR)
5929 {
5930 x = apply_distributive_law (x);
5931 code = GET_CODE (x);
5932 op0_mode = VOIDmode;
5933 }
5934
5935 /* If CODE is an associative operation not otherwise handled, see if we
5936 can associate some operands. This can win if they are constants or
5937 if they are logically related (i.e. (a & b) & a). */
5938 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5939 || code == AND || code == IOR || code == XOR
5940 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5941 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5942 || (flag_associative_math && FLOAT_MODE_P (mode))))
5943 {
5944 if (GET_CODE (XEXP (x, 0)) == code)
5945 {
5946 rtx other = XEXP (XEXP (x, 0), 0);
5947 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5948 rtx inner_op1 = XEXP (x, 1);
5949 rtx inner;
5950
5951 /* Make sure we pass the constant operand if any as the second
5952 one if this is a commutative operation. */
5953 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5954 std::swap (inner_op0, inner_op1);
5955 inner = simplify_binary_operation (code == MINUS ? PLUS
5956 : code == DIV ? MULT
5957 : code,
5958 mode, inner_op0, inner_op1);
5959
5960 /* For commutative operations, try the other pair if that one
5961 didn't simplify. */
5962 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5963 {
5964 other = XEXP (XEXP (x, 0), 1);
5965 inner = simplify_binary_operation (code, mode,
5966 XEXP (XEXP (x, 0), 0),
5967 XEXP (x, 1));
5968 }
5969
5970 if (inner)
5971 return simplify_gen_binary (code, mode, other, inner);
5972 }
5973 }
5974
5975 /* A little bit of algebraic simplification here. */
5976 switch (code)
5977 {
5978 case MEM:
5979 /* Ensure that our address has any ASHIFTs converted to MULT in case
5980 address-recognizing predicates are called later. */
5981 temp = make_compound_operation (XEXP (x, 0), MEM);
5982 SUBST (XEXP (x, 0), temp);
5983 break;
5984
5985 case SUBREG:
5986 if (op0_mode == VOIDmode)
5987 op0_mode = GET_MODE (SUBREG_REG (x));
5988
5989 /* See if this can be moved to simplify_subreg. */
5990 if (CONSTANT_P (SUBREG_REG (x))
5991 && known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x))
5992 /* Don't call gen_lowpart if the inner mode
5993 is VOIDmode and we cannot simplify it, as SUBREG without
5994 inner mode is invalid. */
5995 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5996 || gen_lowpart_common (mode, SUBREG_REG (x))))
5997 return gen_lowpart (mode, SUBREG_REG (x));
5998
5999 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
6000 break;
6001 {
6002 rtx temp;
6003 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
6004 SUBREG_BYTE (x));
6005 if (temp)
6006 return temp;
6007
6008 /* If op is known to have all lower bits zero, the result is zero. */
6009 scalar_int_mode int_mode, int_op0_mode;
6010 if (!in_dest
6011 && is_a <scalar_int_mode> (mode, &int_mode)
6012 && is_a <scalar_int_mode> (op0_mode, &int_op0_mode)
6013 && (GET_MODE_PRECISION (int_mode)
6014 < GET_MODE_PRECISION (int_op0_mode))
6015 && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
6016 SUBREG_BYTE (x))
6017 && HWI_COMPUTABLE_MODE_P (int_op0_mode)
6018 && ((nonzero_bits (SUBREG_REG (x), int_op0_mode)
6019 & GET_MODE_MASK (int_mode)) == 0)
6020 && !side_effects_p (SUBREG_REG (x)))
6021 return CONST0_RTX (int_mode);
6022 }
6023
6024 /* Don't change the mode of the MEM if that would change the meaning
6025 of the address. */
6026 if (MEM_P (SUBREG_REG (x))
6027 && (MEM_VOLATILE_P (SUBREG_REG (x))
6028 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
6029 MEM_ADDR_SPACE (SUBREG_REG (x)))))
6030 return gen_rtx_CLOBBER (mode, const0_rtx);
6031
6032 /* Note that we cannot do any narrowing for non-constants since
6033 we might have been counting on using the fact that some bits were
6034 zero. We now do this in the SET. */
6035
6036 break;
6037
6038 case NEG:
6039 temp = expand_compound_operation (XEXP (x, 0));
6040
6041 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6042 replaced by (lshiftrt X C). This will convert
6043 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6044
6045 if (GET_CODE (temp) == ASHIFTRT
6046 && CONST_INT_P (XEXP (temp, 1))
6047 && INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1)
6048 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
6049 INTVAL (XEXP (temp, 1)));
6050
6051 /* If X has only a single bit that might be nonzero, say, bit I, convert
6052 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6053 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6054 (sign_extract X 1 Y). But only do this if TEMP isn't a register
6055 or a SUBREG of one since we'd be making the expression more
6056 complex if it was just a register. */
6057
6058 if (!REG_P (temp)
6059 && ! (GET_CODE (temp) == SUBREG
6060 && REG_P (SUBREG_REG (temp)))
6061 && is_a <scalar_int_mode> (mode, &int_mode)
6062 && (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
6063 {
6064 rtx temp1 = simplify_shift_const
6065 (NULL_RTX, ASHIFTRT, int_mode,
6066 simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp,
6067 GET_MODE_PRECISION (int_mode) - 1 - i),
6068 GET_MODE_PRECISION (int_mode) - 1 - i);
6069
6070 /* If all we did was surround TEMP with the two shifts, we
6071 haven't improved anything, so don't use it. Otherwise,
6072 we are better off with TEMP1. */
6073 if (GET_CODE (temp1) != ASHIFTRT
6074 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
6075 || XEXP (XEXP (temp1, 0), 0) != temp)
6076 return temp1;
6077 }
6078 break;
6079
6080 case TRUNCATE:
6081 /* We can't handle truncation to a partial integer mode here
6082 because we don't know the real bitsize of the partial
6083 integer mode. */
6084 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
6085 break;
6086
6087 if (HWI_COMPUTABLE_MODE_P (mode))
6088 SUBST (XEXP (x, 0),
6089 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
6090 GET_MODE_MASK (mode), 0));
6091
6092 /* We can truncate a constant value and return it. */
6093 {
6094 poly_int64 c;
6095 if (poly_int_rtx_p (XEXP (x, 0), &c))
6096 return gen_int_mode (c, mode);
6097 }
6098
6099 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6100 whose value is a comparison can be replaced with a subreg if
6101 STORE_FLAG_VALUE permits. */
6102 if (HWI_COMPUTABLE_MODE_P (mode)
6103 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
6104 && (temp = get_last_value (XEXP (x, 0)))
6105 && COMPARISON_P (temp))
6106 return gen_lowpart (mode, XEXP (x, 0));
6107 break;
6108
6109 case CONST:
6110 /* (const (const X)) can become (const X). Do it this way rather than
6111 returning the inner CONST since CONST can be shared with a
6112 REG_EQUAL note. */
6113 if (GET_CODE (XEXP (x, 0)) == CONST)
6114 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
6115 break;
6116
6117 case LO_SUM:
6118 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6119 can add in an offset. find_split_point will split this address up
6120 again if it doesn't match. */
6121 if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
6122 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
6123 return XEXP (x, 1);
6124 break;
6125
6126 case PLUS:
6127 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6128 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6129 bit-field and can be replaced by either a sign_extend or a
6130 sign_extract. The `and' may be a zero_extend and the two
6131 <c>, -<c> constants may be reversed. */
6132 if (GET_CODE (XEXP (x, 0)) == XOR
6133 && is_a <scalar_int_mode> (mode, &int_mode)
6134 && CONST_INT_P (XEXP (x, 1))
6135 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6136 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
6137 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
6138 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
6139 && HWI_COMPUTABLE_MODE_P (int_mode)
6140 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
6141 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
6142 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
6143 == (HOST_WIDE_INT_1U << (i + 1)) - 1))
6144 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
6145 && known_eq ((GET_MODE_PRECISION
6146 (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
6147 (unsigned int) i + 1))))
6148 return simplify_shift_const
6149 (NULL_RTX, ASHIFTRT, int_mode,
6150 simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6151 XEXP (XEXP (XEXP (x, 0), 0), 0),
6152 GET_MODE_PRECISION (int_mode) - (i + 1)),
6153 GET_MODE_PRECISION (int_mode) - (i + 1));
6154
6155 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6156 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6157 the bitsize of the mode - 1. This allows simplification of
6158 "a = (b & 8) == 0;" */
6159 if (XEXP (x, 1) == constm1_rtx
6160 && !REG_P (XEXP (x, 0))
6161 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
6162 && REG_P (SUBREG_REG (XEXP (x, 0))))
6163 && is_a <scalar_int_mode> (mode, &int_mode)
6164 && nonzero_bits (XEXP (x, 0), int_mode) == 1)
6165 return simplify_shift_const
6166 (NULL_RTX, ASHIFTRT, int_mode,
6167 simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6168 gen_rtx_XOR (int_mode, XEXP (x, 0),
6169 const1_rtx),
6170 GET_MODE_PRECISION (int_mode) - 1),
6171 GET_MODE_PRECISION (int_mode) - 1);
6172
6173 /* If we are adding two things that have no bits in common, convert
6174 the addition into an IOR. This will often be further simplified,
6175 for example in cases like ((a & 1) + (a & 2)), which can
6176 become a & 3. */
6177
6178 if (HWI_COMPUTABLE_MODE_P (mode)
6179 && (nonzero_bits (XEXP (x, 0), mode)
6180 & nonzero_bits (XEXP (x, 1), mode)) == 0)
6181 {
6182 /* Try to simplify the expression further. */
6183 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
6184 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
6185
6186 /* If we could, great. If not, do not go ahead with the IOR
6187 replacement, since PLUS appears in many special purpose
6188 address arithmetic instructions. */
6189 if (GET_CODE (temp) != CLOBBER
6190 && (GET_CODE (temp) != IOR
6191 || ((XEXP (temp, 0) != XEXP (x, 0)
6192 || XEXP (temp, 1) != XEXP (x, 1))
6193 && (XEXP (temp, 0) != XEXP (x, 1)
6194 || XEXP (temp, 1) != XEXP (x, 0)))))
6195 return temp;
6196 }
6197
6198 /* Canonicalize x + x into x << 1. */
6199 if (GET_MODE_CLASS (mode) == MODE_INT
6200 && rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
6201 && !side_effects_p (XEXP (x, 0)))
6202 return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx);
6203
6204 break;
6205
6206 case MINUS:
6207 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6208 (and <foo> (const_int pow2-1)) */
6209 if (is_a <scalar_int_mode> (mode, &int_mode)
6210 && GET_CODE (XEXP (x, 1)) == AND
6211 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
6212 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1)))
6213 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6214 return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0),
6215 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
6216 break;
6217
6218 case MULT:
6219 /* If we have (mult (plus A B) C), apply the distributive law and then
6220 the inverse distributive law to see if things simplify. This
6221 occurs mostly in addresses, often when unrolling loops. */
6222
6223 if (GET_CODE (XEXP (x, 0)) == PLUS)
6224 {
6225 rtx result = distribute_and_simplify_rtx (x, 0);
6226 if (result)
6227 return result;
6228 }
6229
6230 /* Try simplify a*(b/c) as (a*b)/c. */
6231 if (FLOAT_MODE_P (mode) && flag_associative_math
6232 && GET_CODE (XEXP (x, 0)) == DIV)
6233 {
6234 rtx tem = simplify_binary_operation (MULT, mode,
6235 XEXP (XEXP (x, 0), 0),
6236 XEXP (x, 1));
6237 if (tem)
6238 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
6239 }
6240 break;
6241
6242 case UDIV:
6243 /* If this is a divide by a power of two, treat it as a shift if
6244 its first operand is a shift. */
6245 if (is_a <scalar_int_mode> (mode, &int_mode)
6246 && CONST_INT_P (XEXP (x, 1))
6247 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
6248 && (GET_CODE (XEXP (x, 0)) == ASHIFT
6249 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
6250 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
6251 || GET_CODE (XEXP (x, 0)) == ROTATE
6252 || GET_CODE (XEXP (x, 0)) == ROTATERT))
6253 return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode,
6254 XEXP (x, 0), i);
6255 break;
6256
6257 case EQ: case NE:
6258 case GT: case GTU: case GE: case GEU:
6259 case LT: case LTU: case LE: case LEU:
6260 case UNEQ: case LTGT:
6261 case UNGT: case UNGE:
6262 case UNLT: case UNLE:
6263 case UNORDERED: case ORDERED:
6264 /* If the first operand is a condition code, we can't do anything
6265 with it. */
6266 if (GET_CODE (XEXP (x, 0)) == COMPARE
6267 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
6268 && ! CC0_P (XEXP (x, 0))))
6269 {
6270 rtx op0 = XEXP (x, 0);
6271 rtx op1 = XEXP (x, 1);
6272 enum rtx_code new_code;
6273
6274 if (GET_CODE (op0) == COMPARE)
6275 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
6276
6277 /* Simplify our comparison, if possible. */
6278 new_code = simplify_comparison (code, &op0, &op1);
6279
6280 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6281 if only the low-order bit is possibly nonzero in X (such as when
6282 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6283 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6284 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6285 (plus X 1).
6286
6287 Remove any ZERO_EXTRACT we made when thinking this was a
6288 comparison. It may now be simpler to use, e.g., an AND. If a
6289 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6290 the call to make_compound_operation in the SET case.
6291
6292 Don't apply these optimizations if the caller would
6293 prefer a comparison rather than a value.
6294 E.g., for the condition in an IF_THEN_ELSE most targets need
6295 an explicit comparison. */
6296
6297 if (in_cond)
6298 ;
6299
6300 else if (STORE_FLAG_VALUE == 1
6301 && new_code == NE
6302 && is_int_mode (mode, &int_mode)
6303 && op1 == const0_rtx
6304 && int_mode == GET_MODE (op0)
6305 && nonzero_bits (op0, int_mode) == 1)
6306 return gen_lowpart (int_mode,
6307 expand_compound_operation (op0));
6308
6309 else if (STORE_FLAG_VALUE == 1
6310 && new_code == NE
6311 && is_int_mode (mode, &int_mode)
6312 && op1 == const0_rtx
6313 && int_mode == GET_MODE (op0)
6314 && (num_sign_bit_copies (op0, int_mode)
6315 == GET_MODE_PRECISION (int_mode)))
6316 {
6317 op0 = expand_compound_operation (op0);
6318 return simplify_gen_unary (NEG, int_mode,
6319 gen_lowpart (int_mode, op0),
6320 int_mode);
6321 }
6322
6323 else if (STORE_FLAG_VALUE == 1
6324 && new_code == EQ
6325 && is_int_mode (mode, &int_mode)
6326 && op1 == const0_rtx
6327 && int_mode == GET_MODE (op0)
6328 && nonzero_bits (op0, int_mode) == 1)
6329 {
6330 op0 = expand_compound_operation (op0);
6331 return simplify_gen_binary (XOR, int_mode,
6332 gen_lowpart (int_mode, op0),
6333 const1_rtx);
6334 }
6335
6336 else if (STORE_FLAG_VALUE == 1
6337 && new_code == EQ
6338 && is_int_mode (mode, &int_mode)
6339 && op1 == const0_rtx
6340 && int_mode == GET_MODE (op0)
6341 && (num_sign_bit_copies (op0, int_mode)
6342 == GET_MODE_PRECISION (int_mode)))
6343 {
6344 op0 = expand_compound_operation (op0);
6345 return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1);
6346 }
6347
6348 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6349 those above. */
6350 if (in_cond)
6351 ;
6352
6353 else if (STORE_FLAG_VALUE == -1
6354 && new_code == NE
6355 && is_int_mode (mode, &int_mode)
6356 && op1 == const0_rtx
6357 && int_mode == GET_MODE (op0)
6358 && (num_sign_bit_copies (op0, int_mode)
6359 == GET_MODE_PRECISION (int_mode)))
6360 return gen_lowpart (int_mode, expand_compound_operation (op0));
6361
6362 else if (STORE_FLAG_VALUE == -1
6363 && new_code == NE
6364 && is_int_mode (mode, &int_mode)
6365 && op1 == const0_rtx
6366 && int_mode == GET_MODE (op0)
6367 && nonzero_bits (op0, int_mode) == 1)
6368 {
6369 op0 = expand_compound_operation (op0);
6370 return simplify_gen_unary (NEG, int_mode,
6371 gen_lowpart (int_mode, op0),
6372 int_mode);
6373 }
6374
6375 else if (STORE_FLAG_VALUE == -1
6376 && new_code == EQ
6377 && is_int_mode (mode, &int_mode)
6378 && op1 == const0_rtx
6379 && int_mode == GET_MODE (op0)
6380 && (num_sign_bit_copies (op0, int_mode)
6381 == GET_MODE_PRECISION (int_mode)))
6382 {
6383 op0 = expand_compound_operation (op0);
6384 return simplify_gen_unary (NOT, int_mode,
6385 gen_lowpart (int_mode, op0),
6386 int_mode);
6387 }
6388
6389 /* If X is 0/1, (eq X 0) is X-1. */
6390 else if (STORE_FLAG_VALUE == -1
6391 && new_code == EQ
6392 && is_int_mode (mode, &int_mode)
6393 && op1 == const0_rtx
6394 && int_mode == GET_MODE (op0)
6395 && nonzero_bits (op0, int_mode) == 1)
6396 {
6397 op0 = expand_compound_operation (op0);
6398 return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1);
6399 }
6400
6401 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6402 one bit that might be nonzero, we can convert (ne x 0) to
6403 (ashift x c) where C puts the bit in the sign bit. Remove any
6404 AND with STORE_FLAG_VALUE when we are done, since we are only
6405 going to test the sign bit. */
6406 if (new_code == NE
6407 && is_int_mode (mode, &int_mode)
6408 && HWI_COMPUTABLE_MODE_P (int_mode)
6409 && val_signbit_p (int_mode, STORE_FLAG_VALUE)
6410 && op1 == const0_rtx
6411 && int_mode == GET_MODE (op0)
6412 && (i = exact_log2 (nonzero_bits (op0, int_mode))) >= 0)
6413 {
6414 x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6415 expand_compound_operation (op0),
6416 GET_MODE_PRECISION (int_mode) - 1 - i);
6417 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6418 return XEXP (x, 0);
6419 else
6420 return x;
6421 }
6422
6423 /* If the code changed, return a whole new comparison.
6424 We also need to avoid using SUBST in cases where
6425 simplify_comparison has widened a comparison with a CONST_INT,
6426 since in that case the wider CONST_INT may fail the sanity
6427 checks in do_SUBST. */
6428 if (new_code != code
6429 || (CONST_INT_P (op1)
6430 && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6431 && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6432 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6433
6434 /* Otherwise, keep this operation, but maybe change its operands.
6435 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6436 SUBST (XEXP (x, 0), op0);
6437 SUBST (XEXP (x, 1), op1);
6438 }
6439 break;
6440
6441 case IF_THEN_ELSE:
6442 return simplify_if_then_else (x);
6443
6444 case ZERO_EXTRACT:
6445 case SIGN_EXTRACT:
6446 case ZERO_EXTEND:
6447 case SIGN_EXTEND:
6448 /* If we are processing SET_DEST, we are done. */
6449 if (in_dest)
6450 return x;
6451
6452 return expand_compound_operation (x);
6453
6454 case SET:
6455 return simplify_set (x);
6456
6457 case AND:
6458 case IOR:
6459 return simplify_logical (x);
6460
6461 case ASHIFT:
6462 case LSHIFTRT:
6463 case ASHIFTRT:
6464 case ROTATE:
6465 case ROTATERT:
6466 /* If this is a shift by a constant amount, simplify it. */
6467 if (CONST_INT_P (XEXP (x, 1)))
6468 return simplify_shift_const (x, code, mode, XEXP (x, 0),
6469 INTVAL (XEXP (x, 1)));
6470
6471 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6472 SUBST (XEXP (x, 1),
6473 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6474 (HOST_WIDE_INT_1U
6475 << exact_log2 (GET_MODE_UNIT_BITSIZE
6476 (GET_MODE (x))))
6477 - 1,
6478 0));
6479 break;
6480
6481 default:
6482 break;
6483 }
6484
6485 return x;
6486 }
6487
6488 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6489
6490 static rtx
simplify_if_then_else(rtx x)6491 simplify_if_then_else (rtx x)
6492 {
6493 machine_mode mode = GET_MODE (x);
6494 rtx cond = XEXP (x, 0);
6495 rtx true_rtx = XEXP (x, 1);
6496 rtx false_rtx = XEXP (x, 2);
6497 enum rtx_code true_code = GET_CODE (cond);
6498 int comparison_p = COMPARISON_P (cond);
6499 rtx temp;
6500 int i;
6501 enum rtx_code false_code;
6502 rtx reversed;
6503 scalar_int_mode int_mode, inner_mode;
6504
6505 /* Simplify storing of the truth value. */
6506 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6507 return simplify_gen_relational (true_code, mode, VOIDmode,
6508 XEXP (cond, 0), XEXP (cond, 1));
6509
6510 /* Also when the truth value has to be reversed. */
6511 if (comparison_p
6512 && true_rtx == const0_rtx && false_rtx == const_true_rtx
6513 && (reversed = reversed_comparison (cond, mode)))
6514 return reversed;
6515
6516 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6517 in it is being compared against certain values. Get the true and false
6518 comparisons and see if that says anything about the value of each arm. */
6519
6520 if (comparison_p
6521 && ((false_code = reversed_comparison_code (cond, NULL))
6522 != UNKNOWN)
6523 && REG_P (XEXP (cond, 0)))
6524 {
6525 HOST_WIDE_INT nzb;
6526 rtx from = XEXP (cond, 0);
6527 rtx true_val = XEXP (cond, 1);
6528 rtx false_val = true_val;
6529 int swapped = 0;
6530
6531 /* If FALSE_CODE is EQ, swap the codes and arms. */
6532
6533 if (false_code == EQ)
6534 {
6535 swapped = 1, true_code = EQ, false_code = NE;
6536 std::swap (true_rtx, false_rtx);
6537 }
6538
6539 scalar_int_mode from_mode;
6540 if (is_a <scalar_int_mode> (GET_MODE (from), &from_mode))
6541 {
6542 /* If we are comparing against zero and the expression being
6543 tested has only a single bit that might be nonzero, that is
6544 its value when it is not equal to zero. Similarly if it is
6545 known to be -1 or 0. */
6546 if (true_code == EQ
6547 && true_val == const0_rtx
6548 && pow2p_hwi (nzb = nonzero_bits (from, from_mode)))
6549 {
6550 false_code = EQ;
6551 false_val = gen_int_mode (nzb, from_mode);
6552 }
6553 else if (true_code == EQ
6554 && true_val == const0_rtx
6555 && (num_sign_bit_copies (from, from_mode)
6556 == GET_MODE_PRECISION (from_mode)))
6557 {
6558 false_code = EQ;
6559 false_val = constm1_rtx;
6560 }
6561 }
6562
6563 /* Now simplify an arm if we know the value of the register in the
6564 branch and it is used in the arm. Be careful due to the potential
6565 of locally-shared RTL. */
6566
6567 if (reg_mentioned_p (from, true_rtx))
6568 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6569 from, true_val),
6570 pc_rtx, pc_rtx, 0, 0, 0);
6571 if (reg_mentioned_p (from, false_rtx))
6572 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6573 from, false_val),
6574 pc_rtx, pc_rtx, 0, 0, 0);
6575
6576 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6577 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6578
6579 true_rtx = XEXP (x, 1);
6580 false_rtx = XEXP (x, 2);
6581 true_code = GET_CODE (cond);
6582 }
6583
6584 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6585 reversed, do so to avoid needing two sets of patterns for
6586 subtract-and-branch insns. Similarly if we have a constant in the true
6587 arm, the false arm is the same as the first operand of the comparison, or
6588 the false arm is more complicated than the true arm. */
6589
6590 if (comparison_p
6591 && reversed_comparison_code (cond, NULL) != UNKNOWN
6592 && (true_rtx == pc_rtx
6593 || (CONSTANT_P (true_rtx)
6594 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6595 || true_rtx == const0_rtx
6596 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6597 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6598 && !OBJECT_P (false_rtx))
6599 || reg_mentioned_p (true_rtx, false_rtx)
6600 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6601 {
6602 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6603 SUBST (XEXP (x, 1), false_rtx);
6604 SUBST (XEXP (x, 2), true_rtx);
6605
6606 std::swap (true_rtx, false_rtx);
6607 cond = XEXP (x, 0);
6608
6609 /* It is possible that the conditional has been simplified out. */
6610 true_code = GET_CODE (cond);
6611 comparison_p = COMPARISON_P (cond);
6612 }
6613
6614 /* If the two arms are identical, we don't need the comparison. */
6615
6616 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6617 return true_rtx;
6618
6619 /* Convert a == b ? b : a to "a". */
6620 if (true_code == EQ && ! side_effects_p (cond)
6621 && !HONOR_NANS (mode)
6622 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6623 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6624 return false_rtx;
6625 else if (true_code == NE && ! side_effects_p (cond)
6626 && !HONOR_NANS (mode)
6627 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6628 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6629 return true_rtx;
6630
6631 /* Look for cases where we have (abs x) or (neg (abs X)). */
6632
6633 if (GET_MODE_CLASS (mode) == MODE_INT
6634 && comparison_p
6635 && XEXP (cond, 1) == const0_rtx
6636 && GET_CODE (false_rtx) == NEG
6637 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6638 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6639 && ! side_effects_p (true_rtx))
6640 switch (true_code)
6641 {
6642 case GT:
6643 case GE:
6644 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6645 case LT:
6646 case LE:
6647 return
6648 simplify_gen_unary (NEG, mode,
6649 simplify_gen_unary (ABS, mode, true_rtx, mode),
6650 mode);
6651 default:
6652 break;
6653 }
6654
6655 /* Look for MIN or MAX. */
6656
6657 if ((! FLOAT_MODE_P (mode)
6658 || (flag_unsafe_math_optimizations
6659 && !HONOR_NANS (mode)
6660 && !HONOR_SIGNED_ZEROS (mode)))
6661 && comparison_p
6662 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6663 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6664 && ! side_effects_p (cond))
6665 switch (true_code)
6666 {
6667 case GE:
6668 case GT:
6669 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6670 case LE:
6671 case LT:
6672 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6673 case GEU:
6674 case GTU:
6675 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6676 case LEU:
6677 case LTU:
6678 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6679 default:
6680 break;
6681 }
6682
6683 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6684 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6685 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6686 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6687 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6688 neither 1 or -1, but it isn't worth checking for. */
6689
6690 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6691 && comparison_p
6692 && is_int_mode (mode, &int_mode)
6693 && ! side_effects_p (x))
6694 {
6695 rtx t = make_compound_operation (true_rtx, SET);
6696 rtx f = make_compound_operation (false_rtx, SET);
6697 rtx cond_op0 = XEXP (cond, 0);
6698 rtx cond_op1 = XEXP (cond, 1);
6699 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6700 scalar_int_mode m = int_mode;
6701 rtx z = 0, c1 = NULL_RTX;
6702
6703 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6704 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6705 || GET_CODE (t) == ASHIFT
6706 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6707 && rtx_equal_p (XEXP (t, 0), f))
6708 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6709
6710 /* If an identity-zero op is commutative, check whether there
6711 would be a match if we swapped the operands. */
6712 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6713 || GET_CODE (t) == XOR)
6714 && rtx_equal_p (XEXP (t, 1), f))
6715 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6716 else if (GET_CODE (t) == SIGN_EXTEND
6717 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6718 && (GET_CODE (XEXP (t, 0)) == PLUS
6719 || GET_CODE (XEXP (t, 0)) == MINUS
6720 || GET_CODE (XEXP (t, 0)) == IOR
6721 || GET_CODE (XEXP (t, 0)) == XOR
6722 || GET_CODE (XEXP (t, 0)) == ASHIFT
6723 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6724 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6725 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6726 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6727 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6728 && (num_sign_bit_copies (f, GET_MODE (f))
6729 > (unsigned int)
6730 (GET_MODE_PRECISION (int_mode)
6731 - GET_MODE_PRECISION (inner_mode))))
6732 {
6733 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6734 extend_op = SIGN_EXTEND;
6735 m = inner_mode;
6736 }
6737 else if (GET_CODE (t) == SIGN_EXTEND
6738 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6739 && (GET_CODE (XEXP (t, 0)) == PLUS
6740 || GET_CODE (XEXP (t, 0)) == IOR
6741 || GET_CODE (XEXP (t, 0)) == XOR)
6742 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6743 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6744 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6745 && (num_sign_bit_copies (f, GET_MODE (f))
6746 > (unsigned int)
6747 (GET_MODE_PRECISION (int_mode)
6748 - GET_MODE_PRECISION (inner_mode))))
6749 {
6750 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6751 extend_op = SIGN_EXTEND;
6752 m = inner_mode;
6753 }
6754 else if (GET_CODE (t) == ZERO_EXTEND
6755 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6756 && (GET_CODE (XEXP (t, 0)) == PLUS
6757 || GET_CODE (XEXP (t, 0)) == MINUS
6758 || GET_CODE (XEXP (t, 0)) == IOR
6759 || GET_CODE (XEXP (t, 0)) == XOR
6760 || GET_CODE (XEXP (t, 0)) == ASHIFT
6761 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6762 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6763 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6764 && HWI_COMPUTABLE_MODE_P (int_mode)
6765 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6766 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6767 && ((nonzero_bits (f, GET_MODE (f))
6768 & ~GET_MODE_MASK (inner_mode))
6769 == 0))
6770 {
6771 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6772 extend_op = ZERO_EXTEND;
6773 m = inner_mode;
6774 }
6775 else if (GET_CODE (t) == ZERO_EXTEND
6776 && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6777 && (GET_CODE (XEXP (t, 0)) == PLUS
6778 || GET_CODE (XEXP (t, 0)) == IOR
6779 || GET_CODE (XEXP (t, 0)) == XOR)
6780 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6781 && HWI_COMPUTABLE_MODE_P (int_mode)
6782 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6783 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6784 && ((nonzero_bits (f, GET_MODE (f))
6785 & ~GET_MODE_MASK (inner_mode))
6786 == 0))
6787 {
6788 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6789 extend_op = ZERO_EXTEND;
6790 m = inner_mode;
6791 }
6792
6793 if (z)
6794 {
6795 machine_mode cm = m;
6796 if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT)
6797 && GET_MODE (c1) != VOIDmode)
6798 cm = GET_MODE (c1);
6799 temp = subst (simplify_gen_relational (true_code, cm, VOIDmode,
6800 cond_op0, cond_op1),
6801 pc_rtx, pc_rtx, 0, 0, 0);
6802 temp = simplify_gen_binary (MULT, cm, temp,
6803 simplify_gen_binary (MULT, cm, c1,
6804 const_true_rtx));
6805 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6806 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6807
6808 if (extend_op != UNKNOWN)
6809 temp = simplify_gen_unary (extend_op, int_mode, temp, m);
6810
6811 return temp;
6812 }
6813 }
6814
6815 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6816 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6817 negation of a single bit, we can convert this operation to a shift. We
6818 can actually do this more generally, but it doesn't seem worth it. */
6819
6820 if (true_code == NE
6821 && is_a <scalar_int_mode> (mode, &int_mode)
6822 && XEXP (cond, 1) == const0_rtx
6823 && false_rtx == const0_rtx
6824 && CONST_INT_P (true_rtx)
6825 && ((nonzero_bits (XEXP (cond, 0), int_mode) == 1
6826 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6827 || ((num_sign_bit_copies (XEXP (cond, 0), int_mode)
6828 == GET_MODE_PRECISION (int_mode))
6829 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6830 return
6831 simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6832 gen_lowpart (int_mode, XEXP (cond, 0)), i);
6833
6834 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6835 non-zero bit in A is C1. */
6836 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6837 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6838 && is_a <scalar_int_mode> (mode, &int_mode)
6839 && is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), &inner_mode)
6840 && (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))
6841 == nonzero_bits (XEXP (cond, 0), inner_mode)
6842 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0)
6843 {
6844 rtx val = XEXP (cond, 0);
6845 if (inner_mode == int_mode)
6846 return val;
6847 else if (GET_MODE_PRECISION (inner_mode) < GET_MODE_PRECISION (int_mode))
6848 return simplify_gen_unary (ZERO_EXTEND, int_mode, val, inner_mode);
6849 }
6850
6851 return x;
6852 }
6853
6854 /* Simplify X, a SET expression. Return the new expression. */
6855
6856 static rtx
simplify_set(rtx x)6857 simplify_set (rtx x)
6858 {
6859 rtx src = SET_SRC (x);
6860 rtx dest = SET_DEST (x);
6861 machine_mode mode
6862 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6863 rtx_insn *other_insn;
6864 rtx *cc_use;
6865 scalar_int_mode int_mode;
6866
6867 /* (set (pc) (return)) gets written as (return). */
6868 if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6869 return src;
6870
6871 /* Now that we know for sure which bits of SRC we are using, see if we can
6872 simplify the expression for the object knowing that we only need the
6873 low-order bits. */
6874
6875 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6876 {
6877 src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, 0);
6878 SUBST (SET_SRC (x), src);
6879 }
6880
6881 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6882 the comparison result and try to simplify it unless we already have used
6883 undobuf.other_insn. */
6884 if ((GET_MODE_CLASS (mode) == MODE_CC
6885 || GET_CODE (src) == COMPARE
6886 || CC0_P (dest))
6887 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6888 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6889 && COMPARISON_P (*cc_use)
6890 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6891 {
6892 enum rtx_code old_code = GET_CODE (*cc_use);
6893 enum rtx_code new_code;
6894 rtx op0, op1, tmp;
6895 int other_changed = 0;
6896 rtx inner_compare = NULL_RTX;
6897 machine_mode compare_mode = GET_MODE (dest);
6898
6899 if (GET_CODE (src) == COMPARE)
6900 {
6901 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6902 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6903 {
6904 inner_compare = op0;
6905 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6906 }
6907 }
6908 else
6909 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6910
6911 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6912 op0, op1);
6913 if (!tmp)
6914 new_code = old_code;
6915 else if (!CONSTANT_P (tmp))
6916 {
6917 new_code = GET_CODE (tmp);
6918 op0 = XEXP (tmp, 0);
6919 op1 = XEXP (tmp, 1);
6920 }
6921 else
6922 {
6923 rtx pat = PATTERN (other_insn);
6924 undobuf.other_insn = other_insn;
6925 SUBST (*cc_use, tmp);
6926
6927 /* Attempt to simplify CC user. */
6928 if (GET_CODE (pat) == SET)
6929 {
6930 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6931 if (new_rtx != NULL_RTX)
6932 SUBST (SET_SRC (pat), new_rtx);
6933 }
6934
6935 /* Convert X into a no-op move. */
6936 SUBST (SET_DEST (x), pc_rtx);
6937 SUBST (SET_SRC (x), pc_rtx);
6938 return x;
6939 }
6940
6941 /* Simplify our comparison, if possible. */
6942 new_code = simplify_comparison (new_code, &op0, &op1);
6943
6944 #ifdef SELECT_CC_MODE
6945 /* If this machine has CC modes other than CCmode, check to see if we
6946 need to use a different CC mode here. */
6947 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6948 compare_mode = GET_MODE (op0);
6949 else if (inner_compare
6950 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6951 && new_code == old_code
6952 && op0 == XEXP (inner_compare, 0)
6953 && op1 == XEXP (inner_compare, 1))
6954 compare_mode = GET_MODE (inner_compare);
6955 else
6956 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6957
6958 /* If the mode changed, we have to change SET_DEST, the mode in the
6959 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6960 a hard register, just build new versions with the proper mode. If it
6961 is a pseudo, we lose unless it is only time we set the pseudo, in
6962 which case we can safely change its mode. */
6963 if (!HAVE_cc0 && compare_mode != GET_MODE (dest))
6964 {
6965 if (can_change_dest_mode (dest, 0, compare_mode))
6966 {
6967 unsigned int regno = REGNO (dest);
6968 rtx new_dest;
6969
6970 if (regno < FIRST_PSEUDO_REGISTER)
6971 new_dest = gen_rtx_REG (compare_mode, regno);
6972 else
6973 {
6974 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6975 new_dest = regno_reg_rtx[regno];
6976 }
6977
6978 SUBST (SET_DEST (x), new_dest);
6979 SUBST (XEXP (*cc_use, 0), new_dest);
6980 other_changed = 1;
6981
6982 dest = new_dest;
6983 }
6984 }
6985 #endif /* SELECT_CC_MODE */
6986
6987 /* If the code changed, we have to build a new comparison in
6988 undobuf.other_insn. */
6989 if (new_code != old_code)
6990 {
6991 int other_changed_previously = other_changed;
6992 unsigned HOST_WIDE_INT mask;
6993 rtx old_cc_use = *cc_use;
6994
6995 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6996 dest, const0_rtx));
6997 other_changed = 1;
6998
6999 /* If the only change we made was to change an EQ into an NE or
7000 vice versa, OP0 has only one bit that might be nonzero, and OP1
7001 is zero, check if changing the user of the condition code will
7002 produce a valid insn. If it won't, we can keep the original code
7003 in that insn by surrounding our operation with an XOR. */
7004
7005 if (((old_code == NE && new_code == EQ)
7006 || (old_code == EQ && new_code == NE))
7007 && ! other_changed_previously && op1 == const0_rtx
7008 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
7009 && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0))))
7010 {
7011 rtx pat = PATTERN (other_insn), note = 0;
7012
7013 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
7014 && ! check_asm_operands (pat)))
7015 {
7016 *cc_use = old_cc_use;
7017 other_changed = 0;
7018
7019 op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
7020 gen_int_mode (mask,
7021 GET_MODE (op0)));
7022 }
7023 }
7024 }
7025
7026 if (other_changed)
7027 undobuf.other_insn = other_insn;
7028
7029 /* Don't generate a compare of a CC with 0, just use that CC. */
7030 if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
7031 {
7032 SUBST (SET_SRC (x), op0);
7033 src = SET_SRC (x);
7034 }
7035 /* Otherwise, if we didn't previously have the same COMPARE we
7036 want, create it from scratch. */
7037 else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
7038 || XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
7039 {
7040 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
7041 src = SET_SRC (x);
7042 }
7043 }
7044 else
7045 {
7046 /* Get SET_SRC in a form where we have placed back any
7047 compound expressions. Then do the checks below. */
7048 src = make_compound_operation (src, SET);
7049 SUBST (SET_SRC (x), src);
7050 }
7051
7052 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7053 and X being a REG or (subreg (reg)), we may be able to convert this to
7054 (set (subreg:m2 x) (op)).
7055
7056 We can always do this if M1 is narrower than M2 because that means that
7057 we only care about the low bits of the result.
7058
7059 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7060 perform a narrower operation than requested since the high-order bits will
7061 be undefined. On machine where it is defined, this transformation is safe
7062 as long as M1 and M2 have the same number of words. */
7063
7064 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
7065 && !OBJECT_P (SUBREG_REG (src))
7066 && (known_equal_after_align_up
7067 (GET_MODE_SIZE (GET_MODE (src)),
7068 GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))),
7069 UNITS_PER_WORD))
7070 && (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (src))
7071 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
7072 && !REG_CAN_CHANGE_MODE_P (REGNO (dest),
7073 GET_MODE (SUBREG_REG (src)),
7074 GET_MODE (src)))
7075 && (REG_P (dest)
7076 || (GET_CODE (dest) == SUBREG
7077 && REG_P (SUBREG_REG (dest)))))
7078 {
7079 SUBST (SET_DEST (x),
7080 gen_lowpart (GET_MODE (SUBREG_REG (src)),
7081 dest));
7082 SUBST (SET_SRC (x), SUBREG_REG (src));
7083
7084 src = SET_SRC (x), dest = SET_DEST (x);
7085 }
7086
7087 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
7088 in SRC. */
7089 if (dest == cc0_rtx
7090 && partial_subreg_p (src)
7091 && subreg_lowpart_p (src))
7092 {
7093 rtx inner = SUBREG_REG (src);
7094 machine_mode inner_mode = GET_MODE (inner);
7095
7096 /* Here we make sure that we don't have a sign bit on. */
7097 if (val_signbit_known_clear_p (GET_MODE (src),
7098 nonzero_bits (inner, inner_mode)))
7099 {
7100 SUBST (SET_SRC (x), inner);
7101 src = SET_SRC (x);
7102 }
7103 }
7104
7105 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7106 would require a paradoxical subreg. Replace the subreg with a
7107 zero_extend to avoid the reload that would otherwise be required.
7108 Don't do this unless we have a scalar integer mode, otherwise the
7109 transformation is incorrect. */
7110
7111 enum rtx_code extend_op;
7112 if (paradoxical_subreg_p (src)
7113 && MEM_P (SUBREG_REG (src))
7114 && SCALAR_INT_MODE_P (GET_MODE (src))
7115 && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
7116 {
7117 SUBST (SET_SRC (x),
7118 gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src)));
7119
7120 src = SET_SRC (x);
7121 }
7122
7123 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7124 are comparing an item known to be 0 or -1 against 0, use a logical
7125 operation instead. Check for one of the arms being an IOR of the other
7126 arm with some value. We compute three terms to be IOR'ed together. In
7127 practice, at most two will be nonzero. Then we do the IOR's. */
7128
7129 if (GET_CODE (dest) != PC
7130 && GET_CODE (src) == IF_THEN_ELSE
7131 && is_int_mode (GET_MODE (src), &int_mode)
7132 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
7133 && XEXP (XEXP (src, 0), 1) == const0_rtx
7134 && int_mode == GET_MODE (XEXP (XEXP (src, 0), 0))
7135 && (!HAVE_conditional_move
7136 || ! can_conditionally_move_p (int_mode))
7137 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode)
7138 == GET_MODE_PRECISION (int_mode))
7139 && ! side_effects_p (src))
7140 {
7141 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
7142 ? XEXP (src, 1) : XEXP (src, 2));
7143 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
7144 ? XEXP (src, 2) : XEXP (src, 1));
7145 rtx term1 = const0_rtx, term2, term3;
7146
7147 if (GET_CODE (true_rtx) == IOR
7148 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
7149 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
7150 else if (GET_CODE (true_rtx) == IOR
7151 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
7152 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
7153 else if (GET_CODE (false_rtx) == IOR
7154 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
7155 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
7156 else if (GET_CODE (false_rtx) == IOR
7157 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
7158 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
7159
7160 term2 = simplify_gen_binary (AND, int_mode,
7161 XEXP (XEXP (src, 0), 0), true_rtx);
7162 term3 = simplify_gen_binary (AND, int_mode,
7163 simplify_gen_unary (NOT, int_mode,
7164 XEXP (XEXP (src, 0), 0),
7165 int_mode),
7166 false_rtx);
7167
7168 SUBST (SET_SRC (x),
7169 simplify_gen_binary (IOR, int_mode,
7170 simplify_gen_binary (IOR, int_mode,
7171 term1, term2),
7172 term3));
7173
7174 src = SET_SRC (x);
7175 }
7176
7177 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7178 whole thing fail. */
7179 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
7180 return src;
7181 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
7182 return dest;
7183 else
7184 /* Convert this into a field assignment operation, if possible. */
7185 return make_field_assignment (x);
7186 }
7187
7188 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7189 result. */
7190
7191 static rtx
simplify_logical(rtx x)7192 simplify_logical (rtx x)
7193 {
7194 rtx op0 = XEXP (x, 0);
7195 rtx op1 = XEXP (x, 1);
7196 scalar_int_mode mode;
7197
7198 switch (GET_CODE (x))
7199 {
7200 case AND:
7201 /* We can call simplify_and_const_int only if we don't lose
7202 any (sign) bits when converting INTVAL (op1) to
7203 "unsigned HOST_WIDE_INT". */
7204 if (is_a <scalar_int_mode> (GET_MODE (x), &mode)
7205 && CONST_INT_P (op1)
7206 && (HWI_COMPUTABLE_MODE_P (mode)
7207 || INTVAL (op1) > 0))
7208 {
7209 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
7210 if (GET_CODE (x) != AND)
7211 return x;
7212
7213 op0 = XEXP (x, 0);
7214 op1 = XEXP (x, 1);
7215 }
7216
7217 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7218 apply the distributive law and then the inverse distributive
7219 law to see if things simplify. */
7220 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
7221 {
7222 rtx result = distribute_and_simplify_rtx (x, 0);
7223 if (result)
7224 return result;
7225 }
7226 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
7227 {
7228 rtx result = distribute_and_simplify_rtx (x, 1);
7229 if (result)
7230 return result;
7231 }
7232 break;
7233
7234 case IOR:
7235 /* If we have (ior (and A B) C), apply the distributive law and then
7236 the inverse distributive law to see if things simplify. */
7237
7238 if (GET_CODE (op0) == AND)
7239 {
7240 rtx result = distribute_and_simplify_rtx (x, 0);
7241 if (result)
7242 return result;
7243 }
7244
7245 if (GET_CODE (op1) == AND)
7246 {
7247 rtx result = distribute_and_simplify_rtx (x, 1);
7248 if (result)
7249 return result;
7250 }
7251 break;
7252
7253 default:
7254 gcc_unreachable ();
7255 }
7256
7257 return x;
7258 }
7259
7260 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7261 operations" because they can be replaced with two more basic operations.
7262 ZERO_EXTEND is also considered "compound" because it can be replaced with
7263 an AND operation, which is simpler, though only one operation.
7264
7265 The function expand_compound_operation is called with an rtx expression
7266 and will convert it to the appropriate shifts and AND operations,
7267 simplifying at each stage.
7268
7269 The function make_compound_operation is called to convert an expression
7270 consisting of shifts and ANDs into the equivalent compound expression.
7271 It is the inverse of this function, loosely speaking. */
7272
7273 static rtx
expand_compound_operation(rtx x)7274 expand_compound_operation (rtx x)
7275 {
7276 unsigned HOST_WIDE_INT pos = 0, len;
7277 int unsignedp = 0;
7278 unsigned int modewidth;
7279 rtx tem;
7280 scalar_int_mode inner_mode;
7281
7282 switch (GET_CODE (x))
7283 {
7284 case ZERO_EXTEND:
7285 unsignedp = 1;
7286 /* FALLTHRU */
7287 case SIGN_EXTEND:
7288 /* We can't necessarily use a const_int for a multiword mode;
7289 it depends on implicitly extending the value.
7290 Since we don't know the right way to extend it,
7291 we can't tell whether the implicit way is right.
7292
7293 Even for a mode that is no wider than a const_int,
7294 we can't win, because we need to sign extend one of its bits through
7295 the rest of it, and we don't know which bit. */
7296 if (CONST_INT_P (XEXP (x, 0)))
7297 return x;
7298
7299 /* Reject modes that aren't scalar integers because turning vector
7300 or complex modes into shifts causes problems. */
7301 if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7302 return x;
7303
7304 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7305 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7306 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7307 reloaded. If not for that, MEM's would very rarely be safe.
7308
7309 Reject modes bigger than a word, because we might not be able
7310 to reference a two-register group starting with an arbitrary register
7311 (and currently gen_lowpart might crash for a SUBREG). */
7312
7313 if (GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7314 return x;
7315
7316 len = GET_MODE_PRECISION (inner_mode);
7317 /* If the inner object has VOIDmode (the only way this can happen
7318 is if it is an ASM_OPERANDS), we can't do anything since we don't
7319 know how much masking to do. */
7320 if (len == 0)
7321 return x;
7322
7323 break;
7324
7325 case ZERO_EXTRACT:
7326 unsignedp = 1;
7327
7328 /* fall through */
7329
7330 case SIGN_EXTRACT:
7331 /* If the operand is a CLOBBER, just return it. */
7332 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7333 return XEXP (x, 0);
7334
7335 if (!CONST_INT_P (XEXP (x, 1))
7336 || !CONST_INT_P (XEXP (x, 2)))
7337 return x;
7338
7339 /* Reject modes that aren't scalar integers because turning vector
7340 or complex modes into shifts causes problems. */
7341 if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7342 return x;
7343
7344 len = INTVAL (XEXP (x, 1));
7345 pos = INTVAL (XEXP (x, 2));
7346
7347 /* This should stay within the object being extracted, fail otherwise. */
7348 if (len + pos > GET_MODE_PRECISION (inner_mode))
7349 return x;
7350
7351 if (BITS_BIG_ENDIAN)
7352 pos = GET_MODE_PRECISION (inner_mode) - len - pos;
7353
7354 break;
7355
7356 default:
7357 return x;
7358 }
7359
7360 /* We've rejected non-scalar operations by now. */
7361 scalar_int_mode mode = as_a <scalar_int_mode> (GET_MODE (x));
7362
7363 /* Convert sign extension to zero extension, if we know that the high
7364 bit is not set, as this is easier to optimize. It will be converted
7365 back to cheaper alternative in make_extraction. */
7366 if (GET_CODE (x) == SIGN_EXTEND
7367 && HWI_COMPUTABLE_MODE_P (mode)
7368 && ((nonzero_bits (XEXP (x, 0), inner_mode)
7369 & ~(((unsigned HOST_WIDE_INT) GET_MODE_MASK (inner_mode)) >> 1))
7370 == 0))
7371 {
7372 rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0));
7373 rtx temp2 = expand_compound_operation (temp);
7374
7375 /* Make sure this is a profitable operation. */
7376 if (set_src_cost (x, mode, optimize_this_for_speed_p)
7377 > set_src_cost (temp2, mode, optimize_this_for_speed_p))
7378 return temp2;
7379 else if (set_src_cost (x, mode, optimize_this_for_speed_p)
7380 > set_src_cost (temp, mode, optimize_this_for_speed_p))
7381 return temp;
7382 else
7383 return x;
7384 }
7385
7386 /* We can optimize some special cases of ZERO_EXTEND. */
7387 if (GET_CODE (x) == ZERO_EXTEND)
7388 {
7389 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7390 know that the last value didn't have any inappropriate bits
7391 set. */
7392 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7393 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7394 && HWI_COMPUTABLE_MODE_P (mode)
7395 && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
7396 & ~GET_MODE_MASK (inner_mode)) == 0)
7397 return XEXP (XEXP (x, 0), 0);
7398
7399 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7400 if (GET_CODE (XEXP (x, 0)) == SUBREG
7401 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7402 && subreg_lowpart_p (XEXP (x, 0))
7403 && HWI_COMPUTABLE_MODE_P (mode)
7404 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), mode)
7405 & ~GET_MODE_MASK (inner_mode)) == 0)
7406 return SUBREG_REG (XEXP (x, 0));
7407
7408 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7409 is a comparison and STORE_FLAG_VALUE permits. This is like
7410 the first case, but it works even when MODE is larger
7411 than HOST_WIDE_INT. */
7412 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7413 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7414 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
7415 && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7416 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7417 return XEXP (XEXP (x, 0), 0);
7418
7419 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7420 if (GET_CODE (XEXP (x, 0)) == SUBREG
7421 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7422 && subreg_lowpart_p (XEXP (x, 0))
7423 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
7424 && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7425 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7426 return SUBREG_REG (XEXP (x, 0));
7427
7428 }
7429
7430 /* If we reach here, we want to return a pair of shifts. The inner
7431 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7432 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7433 logical depending on the value of UNSIGNEDP.
7434
7435 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7436 converted into an AND of a shift.
7437
7438 We must check for the case where the left shift would have a negative
7439 count. This can happen in a case like (x >> 31) & 255 on machines
7440 that can't shift by a constant. On those machines, we would first
7441 combine the shift with the AND to produce a variable-position
7442 extraction. Then the constant of 31 would be substituted in
7443 to produce such a position. */
7444
7445 modewidth = GET_MODE_PRECISION (mode);
7446 if (modewidth >= pos + len)
7447 {
7448 tem = gen_lowpart (mode, XEXP (x, 0));
7449 if (!tem || GET_CODE (tem) == CLOBBER)
7450 return x;
7451 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7452 tem, modewidth - pos - len);
7453 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
7454 mode, tem, modewidth - len);
7455 }
7456 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
7457 {
7458 tem = simplify_shift_const (NULL_RTX, LSHIFTRT, inner_mode,
7459 XEXP (x, 0), pos);
7460 tem = gen_lowpart (mode, tem);
7461 if (!tem || GET_CODE (tem) == CLOBBER)
7462 return x;
7463 tem = simplify_and_const_int (NULL_RTX, mode, tem,
7464 (HOST_WIDE_INT_1U << len) - 1);
7465 }
7466 else
7467 /* Any other cases we can't handle. */
7468 return x;
7469
7470 /* If we couldn't do this for some reason, return the original
7471 expression. */
7472 if (GET_CODE (tem) == CLOBBER)
7473 return x;
7474
7475 return tem;
7476 }
7477
7478 /* X is a SET which contains an assignment of one object into
7479 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7480 or certain SUBREGS). If possible, convert it into a series of
7481 logical operations.
7482
7483 We half-heartedly support variable positions, but do not at all
7484 support variable lengths. */
7485
7486 static const_rtx
expand_field_assignment(const_rtx x)7487 expand_field_assignment (const_rtx x)
7488 {
7489 rtx inner;
7490 rtx pos; /* Always counts from low bit. */
7491 int len, inner_len;
7492 rtx mask, cleared, masked;
7493 scalar_int_mode compute_mode;
7494
7495 /* Loop until we find something we can't simplify. */
7496 while (1)
7497 {
7498 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7499 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7500 {
7501 rtx x0 = XEXP (SET_DEST (x), 0);
7502 if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
7503 break;
7504 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7505 pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)),
7506 MAX_MODE_INT);
7507 }
7508 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7509 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7510 {
7511 inner = XEXP (SET_DEST (x), 0);
7512 if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (&inner_len))
7513 break;
7514
7515 len = INTVAL (XEXP (SET_DEST (x), 1));
7516 pos = XEXP (SET_DEST (x), 2);
7517
7518 /* A constant position should stay within the width of INNER. */
7519 if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len)
7520 break;
7521
7522 if (BITS_BIG_ENDIAN)
7523 {
7524 if (CONST_INT_P (pos))
7525 pos = GEN_INT (inner_len - len - INTVAL (pos));
7526 else if (GET_CODE (pos) == MINUS
7527 && CONST_INT_P (XEXP (pos, 1))
7528 && INTVAL (XEXP (pos, 1)) == inner_len - len)
7529 /* If position is ADJUST - X, new position is X. */
7530 pos = XEXP (pos, 0);
7531 else
7532 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7533 gen_int_mode (inner_len - len,
7534 GET_MODE (pos)),
7535 pos);
7536 }
7537 }
7538
7539 /* If the destination is a subreg that overwrites the whole of the inner
7540 register, we can move the subreg to the source. */
7541 else if (GET_CODE (SET_DEST (x)) == SUBREG
7542 /* We need SUBREGs to compute nonzero_bits properly. */
7543 && nonzero_sign_valid
7544 && !read_modify_subreg_p (SET_DEST (x)))
7545 {
7546 x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)),
7547 gen_lowpart
7548 (GET_MODE (SUBREG_REG (SET_DEST (x))),
7549 SET_SRC (x)));
7550 continue;
7551 }
7552 else
7553 break;
7554
7555 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7556 inner = SUBREG_REG (inner);
7557
7558 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7559 if (!is_a <scalar_int_mode> (GET_MODE (inner), &compute_mode))
7560 {
7561 /* Don't do anything for vector or complex integral types. */
7562 if (! FLOAT_MODE_P (GET_MODE (inner)))
7563 break;
7564
7565 /* Try to find an integral mode to pun with. */
7566 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner)), 0)
7567 .exists (&compute_mode))
7568 break;
7569
7570 inner = gen_lowpart (compute_mode, inner);
7571 }
7572
7573 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7574 if (len >= HOST_BITS_PER_WIDE_INT)
7575 break;
7576
7577 /* Don't try to compute in too wide unsupported modes. */
7578 if (!targetm.scalar_mode_supported_p (compute_mode))
7579 break;
7580
7581 /* Now compute the equivalent expression. Make a copy of INNER
7582 for the SET_DEST in case it is a MEM into which we will substitute;
7583 we don't want shared RTL in that case. */
7584 mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1,
7585 compute_mode);
7586 cleared = simplify_gen_binary (AND, compute_mode,
7587 simplify_gen_unary (NOT, compute_mode,
7588 simplify_gen_binary (ASHIFT,
7589 compute_mode,
7590 mask, pos),
7591 compute_mode),
7592 inner);
7593 masked = simplify_gen_binary (ASHIFT, compute_mode,
7594 simplify_gen_binary (
7595 AND, compute_mode,
7596 gen_lowpart (compute_mode, SET_SRC (x)),
7597 mask),
7598 pos);
7599
7600 x = gen_rtx_SET (copy_rtx (inner),
7601 simplify_gen_binary (IOR, compute_mode,
7602 cleared, masked));
7603 }
7604
7605 return x;
7606 }
7607
7608 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7609 it is an RTX that represents the (variable) starting position; otherwise,
7610 POS is the (constant) starting bit position. Both are counted from the LSB.
7611
7612 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7613
7614 IN_DEST is nonzero if this is a reference in the destination of a SET.
7615 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7616 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7617 be used.
7618
7619 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7620 ZERO_EXTRACT should be built even for bits starting at bit 0.
7621
7622 MODE is the desired mode of the result (if IN_DEST == 0).
7623
7624 The result is an RTX for the extraction or NULL_RTX if the target
7625 can't handle it. */
7626
7627 static rtx
make_extraction(machine_mode mode,rtx inner,HOST_WIDE_INT pos,rtx pos_rtx,unsigned HOST_WIDE_INT len,int unsignedp,int in_dest,int in_compare)7628 make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7629 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7630 int in_dest, int in_compare)
7631 {
7632 /* This mode describes the size of the storage area
7633 to fetch the overall value from. Within that, we
7634 ignore the POS lowest bits, etc. */
7635 machine_mode is_mode = GET_MODE (inner);
7636 machine_mode inner_mode;
7637 scalar_int_mode wanted_inner_mode;
7638 scalar_int_mode wanted_inner_reg_mode = word_mode;
7639 scalar_int_mode pos_mode = word_mode;
7640 machine_mode extraction_mode = word_mode;
7641 rtx new_rtx = 0;
7642 rtx orig_pos_rtx = pos_rtx;
7643 HOST_WIDE_INT orig_pos;
7644
7645 if (pos_rtx && CONST_INT_P (pos_rtx))
7646 pos = INTVAL (pos_rtx), pos_rtx = 0;
7647
7648 if (GET_CODE (inner) == SUBREG
7649 && subreg_lowpart_p (inner)
7650 && (paradoxical_subreg_p (inner)
7651 /* If trying or potentionally trying to extract
7652 bits outside of is_mode, don't look through
7653 non-paradoxical SUBREGs. See PR82192. */
7654 || (pos_rtx == NULL_RTX
7655 && known_le (pos + len, GET_MODE_PRECISION (is_mode)))))
7656 {
7657 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7658 consider just the QI as the memory to extract from.
7659 The subreg adds or removes high bits; its mode is
7660 irrelevant to the meaning of this extraction,
7661 since POS and LEN count from the lsb. */
7662 if (MEM_P (SUBREG_REG (inner)))
7663 is_mode = GET_MODE (SUBREG_REG (inner));
7664 inner = SUBREG_REG (inner);
7665 }
7666 else if (GET_CODE (inner) == ASHIFT
7667 && CONST_INT_P (XEXP (inner, 1))
7668 && pos_rtx == 0 && pos == 0
7669 && len > UINTVAL (XEXP (inner, 1)))
7670 {
7671 /* We're extracting the least significant bits of an rtx
7672 (ashift X (const_int C)), where LEN > C. Extract the
7673 least significant (LEN - C) bits of X, giving an rtx
7674 whose mode is MODE, then shift it left C times. */
7675 new_rtx = make_extraction (mode, XEXP (inner, 0),
7676 0, 0, len - INTVAL (XEXP (inner, 1)),
7677 unsignedp, in_dest, in_compare);
7678 if (new_rtx != 0)
7679 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7680 }
7681 else if (GET_CODE (inner) == TRUNCATE
7682 /* If trying or potentionally trying to extract
7683 bits outside of is_mode, don't look through
7684 TRUNCATE. See PR82192. */
7685 && pos_rtx == NULL_RTX
7686 && known_le (pos + len, GET_MODE_PRECISION (is_mode)))
7687 inner = XEXP (inner, 0);
7688
7689 inner_mode = GET_MODE (inner);
7690
7691 /* See if this can be done without an extraction. We never can if the
7692 width of the field is not the same as that of some integer mode. For
7693 registers, we can only avoid the extraction if the position is at the
7694 low-order bit and this is either not in the destination or we have the
7695 appropriate STRICT_LOW_PART operation available.
7696
7697 For MEM, we can avoid an extract if the field starts on an appropriate
7698 boundary and we can change the mode of the memory reference. */
7699
7700 scalar_int_mode tmode;
7701 if (int_mode_for_size (len, 1).exists (&tmode)
7702 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7703 && !MEM_P (inner)
7704 && (pos == 0 || REG_P (inner))
7705 && (inner_mode == tmode
7706 || !REG_P (inner)
7707 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7708 || reg_truncated_to_mode (tmode, inner))
7709 && (! in_dest
7710 || (REG_P (inner)
7711 && have_insn_for (STRICT_LOW_PART, tmode))))
7712 || (MEM_P (inner) && pos_rtx == 0
7713 && (pos
7714 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7715 : BITS_PER_UNIT)) == 0
7716 /* We can't do this if we are widening INNER_MODE (it
7717 may not be aligned, for one thing). */
7718 && !paradoxical_subreg_p (tmode, inner_mode)
7719 && known_le (pos + len, GET_MODE_PRECISION (is_mode))
7720 && (inner_mode == tmode
7721 || (! mode_dependent_address_p (XEXP (inner, 0),
7722 MEM_ADDR_SPACE (inner))
7723 && ! MEM_VOLATILE_P (inner))))))
7724 {
7725 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7726 field. If the original and current mode are the same, we need not
7727 adjust the offset. Otherwise, we do if bytes big endian.
7728
7729 If INNER is not a MEM, get a piece consisting of just the field
7730 of interest (in this case POS % BITS_PER_WORD must be 0). */
7731
7732 if (MEM_P (inner))
7733 {
7734 poly_int64 offset;
7735
7736 /* POS counts from lsb, but make OFFSET count in memory order. */
7737 if (BYTES_BIG_ENDIAN)
7738 offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode)
7739 - len - pos);
7740 else
7741 offset = pos / BITS_PER_UNIT;
7742
7743 new_rtx = adjust_address_nv (inner, tmode, offset);
7744 }
7745 else if (REG_P (inner))
7746 {
7747 if (tmode != inner_mode)
7748 {
7749 /* We can't call gen_lowpart in a DEST since we
7750 always want a SUBREG (see below) and it would sometimes
7751 return a new hard register. */
7752 if (pos || in_dest)
7753 {
7754 poly_uint64 offset
7755 = subreg_offset_from_lsb (tmode, inner_mode, pos);
7756
7757 /* Avoid creating invalid subregs, for example when
7758 simplifying (x>>32)&255. */
7759 if (!validate_subreg (tmode, inner_mode, inner, offset))
7760 return NULL_RTX;
7761
7762 new_rtx = gen_rtx_SUBREG (tmode, inner, offset);
7763 }
7764 else
7765 new_rtx = gen_lowpart (tmode, inner);
7766 }
7767 else
7768 new_rtx = inner;
7769 }
7770 else
7771 new_rtx = force_to_mode (inner, tmode,
7772 len >= HOST_BITS_PER_WIDE_INT
7773 ? HOST_WIDE_INT_M1U
7774 : (HOST_WIDE_INT_1U << len) - 1, 0);
7775
7776 /* If this extraction is going into the destination of a SET,
7777 make a STRICT_LOW_PART unless we made a MEM. */
7778
7779 if (in_dest)
7780 return (MEM_P (new_rtx) ? new_rtx
7781 : (GET_CODE (new_rtx) != SUBREG
7782 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7783 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7784
7785 if (mode == tmode)
7786 return new_rtx;
7787
7788 if (CONST_SCALAR_INT_P (new_rtx))
7789 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7790 mode, new_rtx, tmode);
7791
7792 /* If we know that no extraneous bits are set, and that the high
7793 bit is not set, convert the extraction to the cheaper of
7794 sign and zero extension, that are equivalent in these cases. */
7795 if (flag_expensive_optimizations
7796 && (HWI_COMPUTABLE_MODE_P (tmode)
7797 && ((nonzero_bits (new_rtx, tmode)
7798 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7799 == 0)))
7800 {
7801 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7802 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7803
7804 /* Prefer ZERO_EXTENSION, since it gives more information to
7805 backends. */
7806 if (set_src_cost (temp, mode, optimize_this_for_speed_p)
7807 <= set_src_cost (temp1, mode, optimize_this_for_speed_p))
7808 return temp;
7809 return temp1;
7810 }
7811
7812 /* Otherwise, sign- or zero-extend unless we already are in the
7813 proper mode. */
7814
7815 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7816 mode, new_rtx));
7817 }
7818
7819 /* Unless this is a COMPARE or we have a funny memory reference,
7820 don't do anything with zero-extending field extracts starting at
7821 the low-order bit since they are simple AND operations. */
7822 if (pos_rtx == 0 && pos == 0 && ! in_dest
7823 && ! in_compare && unsignedp)
7824 return 0;
7825
7826 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7827 if the position is not a constant and the length is not 1. In all
7828 other cases, we would only be going outside our object in cases when
7829 an original shift would have been undefined. */
7830 if (MEM_P (inner)
7831 && ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode)))
7832 || (pos_rtx != 0 && len != 1)))
7833 return 0;
7834
7835 enum extraction_pattern pattern = (in_dest ? EP_insv
7836 : unsignedp ? EP_extzv : EP_extv);
7837
7838 /* If INNER is not from memory, we want it to have the mode of a register
7839 extraction pattern's structure operand, or word_mode if there is no
7840 such pattern. The same applies to extraction_mode and pos_mode
7841 and their respective operands.
7842
7843 For memory, assume that the desired extraction_mode and pos_mode
7844 are the same as for a register operation, since at present we don't
7845 have named patterns for aligned memory structures. */
7846 class extraction_insn insn;
7847 unsigned int inner_size;
7848 if (GET_MODE_BITSIZE (inner_mode).is_constant (&inner_size)
7849 && get_best_reg_extraction_insn (&insn, pattern, inner_size, mode))
7850 {
7851 wanted_inner_reg_mode = insn.struct_mode.require ();
7852 pos_mode = insn.pos_mode;
7853 extraction_mode = insn.field_mode;
7854 }
7855
7856 /* Never narrow an object, since that might not be safe. */
7857
7858 if (mode != VOIDmode
7859 && partial_subreg_p (extraction_mode, mode))
7860 extraction_mode = mode;
7861
7862 /* Punt if len is too large for extraction_mode. */
7863 if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode)))
7864 return NULL_RTX;
7865
7866 if (!MEM_P (inner))
7867 wanted_inner_mode = wanted_inner_reg_mode;
7868 else
7869 {
7870 /* Be careful not to go beyond the extracted object and maintain the
7871 natural alignment of the memory. */
7872 wanted_inner_mode = smallest_int_mode_for_size (len);
7873 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7874 > GET_MODE_BITSIZE (wanted_inner_mode))
7875 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode).require ();
7876 }
7877
7878 orig_pos = pos;
7879
7880 if (BITS_BIG_ENDIAN)
7881 {
7882 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7883 BITS_BIG_ENDIAN style. If position is constant, compute new
7884 position. Otherwise, build subtraction.
7885 Note that POS is relative to the mode of the original argument.
7886 If it's a MEM we need to recompute POS relative to that.
7887 However, if we're extracting from (or inserting into) a register,
7888 we want to recompute POS relative to wanted_inner_mode. */
7889 int width;
7890 if (!MEM_P (inner))
7891 width = GET_MODE_BITSIZE (wanted_inner_mode);
7892 else if (!GET_MODE_BITSIZE (is_mode).is_constant (&width))
7893 return NULL_RTX;
7894
7895 if (pos_rtx == 0)
7896 pos = width - len - pos;
7897 else
7898 pos_rtx
7899 = gen_rtx_MINUS (GET_MODE (pos_rtx),
7900 gen_int_mode (width - len, GET_MODE (pos_rtx)),
7901 pos_rtx);
7902 /* POS may be less than 0 now, but we check for that below.
7903 Note that it can only be less than 0 if !MEM_P (inner). */
7904 }
7905
7906 /* If INNER has a wider mode, and this is a constant extraction, try to
7907 make it smaller and adjust the byte to point to the byte containing
7908 the value. */
7909 if (wanted_inner_mode != VOIDmode
7910 && inner_mode != wanted_inner_mode
7911 && ! pos_rtx
7912 && partial_subreg_p (wanted_inner_mode, is_mode)
7913 && MEM_P (inner)
7914 && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7915 && ! MEM_VOLATILE_P (inner))
7916 {
7917 poly_int64 offset = 0;
7918
7919 /* The computations below will be correct if the machine is big
7920 endian in both bits and bytes or little endian in bits and bytes.
7921 If it is mixed, we must adjust. */
7922
7923 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7924 adjust OFFSET to compensate. */
7925 if (BYTES_BIG_ENDIAN
7926 && paradoxical_subreg_p (is_mode, inner_mode))
7927 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7928
7929 /* We can now move to the desired byte. */
7930 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7931 * GET_MODE_SIZE (wanted_inner_mode);
7932 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7933
7934 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7935 && is_mode != wanted_inner_mode)
7936 offset = (GET_MODE_SIZE (is_mode)
7937 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7938
7939 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7940 }
7941
7942 /* If INNER is not memory, get it into the proper mode. If we are changing
7943 its mode, POS must be a constant and smaller than the size of the new
7944 mode. */
7945 else if (!MEM_P (inner))
7946 {
7947 /* On the LHS, don't create paradoxical subregs implicitely truncating
7948 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7949 if (in_dest
7950 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7951 wanted_inner_mode))
7952 return NULL_RTX;
7953
7954 if (GET_MODE (inner) != wanted_inner_mode
7955 && (pos_rtx != 0
7956 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7957 return NULL_RTX;
7958
7959 if (orig_pos < 0)
7960 return NULL_RTX;
7961
7962 inner = force_to_mode (inner, wanted_inner_mode,
7963 pos_rtx
7964 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7965 ? HOST_WIDE_INT_M1U
7966 : (((HOST_WIDE_INT_1U << len) - 1)
7967 << orig_pos),
7968 0);
7969 }
7970
7971 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7972 have to zero extend. Otherwise, we can just use a SUBREG.
7973
7974 We dealt with constant rtxes earlier, so pos_rtx cannot
7975 have VOIDmode at this point. */
7976 if (pos_rtx != 0
7977 && (GET_MODE_SIZE (pos_mode)
7978 > GET_MODE_SIZE (as_a <scalar_int_mode> (GET_MODE (pos_rtx)))))
7979 {
7980 rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7981 GET_MODE (pos_rtx));
7982
7983 /* If we know that no extraneous bits are set, and that the high
7984 bit is not set, convert extraction to cheaper one - either
7985 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7986 cases. */
7987 if (flag_expensive_optimizations
7988 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7989 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7990 & ~(((unsigned HOST_WIDE_INT)
7991 GET_MODE_MASK (GET_MODE (pos_rtx)))
7992 >> 1))
7993 == 0)))
7994 {
7995 rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7996 GET_MODE (pos_rtx));
7997
7998 /* Prefer ZERO_EXTENSION, since it gives more information to
7999 backends. */
8000 if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p)
8001 < set_src_cost (temp, pos_mode, optimize_this_for_speed_p))
8002 temp = temp1;
8003 }
8004 pos_rtx = temp;
8005 }
8006
8007 /* Make POS_RTX unless we already have it and it is correct. If we don't
8008 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
8009 be a CONST_INT. */
8010 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
8011 pos_rtx = orig_pos_rtx;
8012
8013 else if (pos_rtx == 0)
8014 pos_rtx = GEN_INT (pos);
8015
8016 /* Make the required operation. See if we can use existing rtx. */
8017 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
8018 extraction_mode, inner, GEN_INT (len), pos_rtx);
8019 if (! in_dest)
8020 new_rtx = gen_lowpart (mode, new_rtx);
8021
8022 return new_rtx;
8023 }
8024
8025 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
8026 can be commuted with any other operations in X. Return X without
8027 that shift if so. */
8028
8029 static rtx
extract_left_shift(scalar_int_mode mode,rtx x,int count)8030 extract_left_shift (scalar_int_mode mode, rtx x, int count)
8031 {
8032 enum rtx_code code = GET_CODE (x);
8033 rtx tem;
8034
8035 switch (code)
8036 {
8037 case ASHIFT:
8038 /* This is the shift itself. If it is wide enough, we will return
8039 either the value being shifted if the shift count is equal to
8040 COUNT or a shift for the difference. */
8041 if (CONST_INT_P (XEXP (x, 1))
8042 && INTVAL (XEXP (x, 1)) >= count)
8043 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
8044 INTVAL (XEXP (x, 1)) - count);
8045 break;
8046
8047 case NEG: case NOT:
8048 if ((tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8049 return simplify_gen_unary (code, mode, tem, mode);
8050
8051 break;
8052
8053 case PLUS: case IOR: case XOR: case AND:
8054 /* If we can safely shift this constant and we find the inner shift,
8055 make a new operation. */
8056 if (CONST_INT_P (XEXP (x, 1))
8057 && (UINTVAL (XEXP (x, 1))
8058 & (((HOST_WIDE_INT_1U << count)) - 1)) == 0
8059 && (tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8060 {
8061 HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
8062 return simplify_gen_binary (code, mode, tem,
8063 gen_int_mode (val, mode));
8064 }
8065 break;
8066
8067 default:
8068 break;
8069 }
8070
8071 return 0;
8072 }
8073
8074 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8075 level of the expression and MODE is its mode. IN_CODE is as for
8076 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8077 that should be used when recursing on operands of *X_PTR.
8078
8079 There are two possible actions:
8080
8081 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8082 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8083
8084 - Return a new rtx, which the caller returns directly. */
8085
8086 static rtx
make_compound_operation_int(scalar_int_mode mode,rtx * x_ptr,enum rtx_code in_code,enum rtx_code * next_code_ptr)8087 make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
8088 enum rtx_code in_code,
8089 enum rtx_code *next_code_ptr)
8090 {
8091 rtx x = *x_ptr;
8092 enum rtx_code next_code = *next_code_ptr;
8093 enum rtx_code code = GET_CODE (x);
8094 int mode_width = GET_MODE_PRECISION (mode);
8095 rtx rhs, lhs;
8096 rtx new_rtx = 0;
8097 int i;
8098 rtx tem;
8099 scalar_int_mode inner_mode;
8100 bool equality_comparison = false;
8101
8102 if (in_code == EQ)
8103 {
8104 equality_comparison = true;
8105 in_code = COMPARE;
8106 }
8107
8108 /* Process depending on the code of this operation. If NEW is set
8109 nonzero, it will be returned. */
8110
8111 switch (code)
8112 {
8113 case ASHIFT:
8114 /* Convert shifts by constants into multiplications if inside
8115 an address. */
8116 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
8117 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8118 && INTVAL (XEXP (x, 1)) >= 0)
8119 {
8120 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
8121 HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count;
8122
8123 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8124 if (GET_CODE (new_rtx) == NEG)
8125 {
8126 new_rtx = XEXP (new_rtx, 0);
8127 multval = -multval;
8128 }
8129 multval = trunc_int_for_mode (multval, mode);
8130 new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
8131 }
8132 break;
8133
8134 case PLUS:
8135 lhs = XEXP (x, 0);
8136 rhs = XEXP (x, 1);
8137 lhs = make_compound_operation (lhs, next_code);
8138 rhs = make_compound_operation (rhs, next_code);
8139 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG)
8140 {
8141 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
8142 XEXP (lhs, 1));
8143 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
8144 }
8145 else if (GET_CODE (lhs) == MULT
8146 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
8147 {
8148 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
8149 simplify_gen_unary (NEG, mode,
8150 XEXP (lhs, 1),
8151 mode));
8152 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
8153 }
8154 else
8155 {
8156 SUBST (XEXP (x, 0), lhs);
8157 SUBST (XEXP (x, 1), rhs);
8158 }
8159 maybe_swap_commutative_operands (x);
8160 return x;
8161
8162 case MINUS:
8163 lhs = XEXP (x, 0);
8164 rhs = XEXP (x, 1);
8165 lhs = make_compound_operation (lhs, next_code);
8166 rhs = make_compound_operation (rhs, next_code);
8167 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG)
8168 {
8169 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
8170 XEXP (rhs, 1));
8171 return simplify_gen_binary (PLUS, mode, tem, lhs);
8172 }
8173 else if (GET_CODE (rhs) == MULT
8174 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
8175 {
8176 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
8177 simplify_gen_unary (NEG, mode,
8178 XEXP (rhs, 1),
8179 mode));
8180 return simplify_gen_binary (PLUS, mode, tem, lhs);
8181 }
8182 else
8183 {
8184 SUBST (XEXP (x, 0), lhs);
8185 SUBST (XEXP (x, 1), rhs);
8186 return x;
8187 }
8188
8189 case AND:
8190 /* If the second operand is not a constant, we can't do anything
8191 with it. */
8192 if (!CONST_INT_P (XEXP (x, 1)))
8193 break;
8194
8195 /* If the constant is a power of two minus one and the first operand
8196 is a logical right shift, make an extraction. */
8197 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8198 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8199 {
8200 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8201 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1),
8202 i, 1, 0, in_code == COMPARE);
8203 }
8204
8205 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8206 else if (GET_CODE (XEXP (x, 0)) == SUBREG
8207 && subreg_lowpart_p (XEXP (x, 0))
8208 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
8209 &inner_mode)
8210 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
8211 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8212 {
8213 rtx inner_x0 = SUBREG_REG (XEXP (x, 0));
8214 new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code);
8215 new_rtx = make_extraction (inner_mode, new_rtx, 0,
8216 XEXP (inner_x0, 1),
8217 i, 1, 0, in_code == COMPARE);
8218
8219 /* If we narrowed the mode when dropping the subreg, then we lose. */
8220 if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode))
8221 new_rtx = NULL;
8222
8223 /* If that didn't give anything, see if the AND simplifies on
8224 its own. */
8225 if (!new_rtx && i >= 0)
8226 {
8227 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8228 new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i, 1,
8229 0, in_code == COMPARE);
8230 }
8231 }
8232 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8233 else if ((GET_CODE (XEXP (x, 0)) == XOR
8234 || GET_CODE (XEXP (x, 0)) == IOR)
8235 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
8236 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
8237 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8238 {
8239 /* Apply the distributive law, and then try to make extractions. */
8240 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
8241 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
8242 XEXP (x, 1)),
8243 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
8244 XEXP (x, 1)));
8245 new_rtx = make_compound_operation (new_rtx, in_code);
8246 }
8247
8248 /* If we are have (and (rotate X C) M) and C is larger than the number
8249 of bits in M, this is an extraction. */
8250
8251 else if (GET_CODE (XEXP (x, 0)) == ROTATE
8252 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8253 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
8254 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
8255 {
8256 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8257 new_rtx = make_extraction (mode, new_rtx,
8258 (GET_MODE_PRECISION (mode)
8259 - INTVAL (XEXP (XEXP (x, 0), 1))),
8260 NULL_RTX, i, 1, 0, in_code == COMPARE);
8261 }
8262
8263 /* On machines without logical shifts, if the operand of the AND is
8264 a logical shift and our mask turns off all the propagated sign
8265 bits, we can replace the logical shift with an arithmetic shift. */
8266 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8267 && !have_insn_for (LSHIFTRT, mode)
8268 && have_insn_for (ASHIFTRT, mode)
8269 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8270 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8271 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8272 && mode_width <= HOST_BITS_PER_WIDE_INT)
8273 {
8274 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8275
8276 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
8277 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
8278 SUBST (XEXP (x, 0),
8279 gen_rtx_ASHIFTRT (mode,
8280 make_compound_operation (XEXP (XEXP (x,
8281 0),
8282 0),
8283 next_code),
8284 XEXP (XEXP (x, 0), 1)));
8285 }
8286
8287 /* If the constant is one less than a power of two, this might be
8288 representable by an extraction even if no shift is present.
8289 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8290 we are in a COMPARE. */
8291 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8292 new_rtx = make_extraction (mode,
8293 make_compound_operation (XEXP (x, 0),
8294 next_code),
8295 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
8296
8297 /* If we are in a comparison and this is an AND with a power of two,
8298 convert this into the appropriate bit extract. */
8299 else if (in_code == COMPARE
8300 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
8301 && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1))
8302 new_rtx = make_extraction (mode,
8303 make_compound_operation (XEXP (x, 0),
8304 next_code),
8305 i, NULL_RTX, 1, 1, 0, 1);
8306
8307 /* If the one operand is a paradoxical subreg of a register or memory and
8308 the constant (limited to the smaller mode) has only zero bits where
8309 the sub expression has known zero bits, this can be expressed as
8310 a zero_extend. */
8311 else if (GET_CODE (XEXP (x, 0)) == SUBREG)
8312 {
8313 rtx sub;
8314
8315 sub = XEXP (XEXP (x, 0), 0);
8316 machine_mode sub_mode = GET_MODE (sub);
8317 int sub_width;
8318 if ((REG_P (sub) || MEM_P (sub))
8319 && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width)
8320 && sub_width < mode_width)
8321 {
8322 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
8323 unsigned HOST_WIDE_INT mask;
8324
8325 /* original AND constant with all the known zero bits set */
8326 mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode));
8327 if ((mask & mode_mask) == mode_mask)
8328 {
8329 new_rtx = make_compound_operation (sub, next_code);
8330 new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width,
8331 1, 0, in_code == COMPARE);
8332 }
8333 }
8334 }
8335
8336 break;
8337
8338 case LSHIFTRT:
8339 /* If the sign bit is known to be zero, replace this with an
8340 arithmetic shift. */
8341 if (have_insn_for (ASHIFTRT, mode)
8342 && ! have_insn_for (LSHIFTRT, mode)
8343 && mode_width <= HOST_BITS_PER_WIDE_INT
8344 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
8345 {
8346 new_rtx = gen_rtx_ASHIFTRT (mode,
8347 make_compound_operation (XEXP (x, 0),
8348 next_code),
8349 XEXP (x, 1));
8350 break;
8351 }
8352
8353 /* fall through */
8354
8355 case ASHIFTRT:
8356 lhs = XEXP (x, 0);
8357 rhs = XEXP (x, 1);
8358
8359 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8360 this is a SIGN_EXTRACT. */
8361 if (CONST_INT_P (rhs)
8362 && GET_CODE (lhs) == ASHIFT
8363 && CONST_INT_P (XEXP (lhs, 1))
8364 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
8365 && INTVAL (XEXP (lhs, 1)) >= 0
8366 && INTVAL (rhs) < mode_width)
8367 {
8368 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
8369 new_rtx = make_extraction (mode, new_rtx,
8370 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
8371 NULL_RTX, mode_width - INTVAL (rhs),
8372 code == LSHIFTRT, 0, in_code == COMPARE);
8373 break;
8374 }
8375
8376 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8377 If so, try to merge the shifts into a SIGN_EXTEND. We could
8378 also do this for some cases of SIGN_EXTRACT, but it doesn't
8379 seem worth the effort; the case checked for occurs on Alpha. */
8380
8381 if (!OBJECT_P (lhs)
8382 && ! (GET_CODE (lhs) == SUBREG
8383 && (OBJECT_P (SUBREG_REG (lhs))))
8384 && CONST_INT_P (rhs)
8385 && INTVAL (rhs) >= 0
8386 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
8387 && INTVAL (rhs) < mode_width
8388 && (new_rtx = extract_left_shift (mode, lhs, INTVAL (rhs))) != 0)
8389 new_rtx = make_extraction (mode, make_compound_operation (new_rtx,
8390 next_code),
8391 0, NULL_RTX, mode_width - INTVAL (rhs),
8392 code == LSHIFTRT, 0, in_code == COMPARE);
8393
8394 break;
8395
8396 case SUBREG:
8397 /* Call ourselves recursively on the inner expression. If we are
8398 narrowing the object and it has a different RTL code from
8399 what it originally did, do this SUBREG as a force_to_mode. */
8400 {
8401 rtx inner = SUBREG_REG (x), simplified;
8402 enum rtx_code subreg_code = in_code;
8403
8404 /* If the SUBREG is masking of a logical right shift,
8405 make an extraction. */
8406 if (GET_CODE (inner) == LSHIFTRT
8407 && is_a <scalar_int_mode> (GET_MODE (inner), &inner_mode)
8408 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (inner_mode)
8409 && CONST_INT_P (XEXP (inner, 1))
8410 && UINTVAL (XEXP (inner, 1)) < GET_MODE_PRECISION (inner_mode)
8411 && subreg_lowpart_p (x))
8412 {
8413 new_rtx = make_compound_operation (XEXP (inner, 0), next_code);
8414 int width = GET_MODE_PRECISION (inner_mode)
8415 - INTVAL (XEXP (inner, 1));
8416 if (width > mode_width)
8417 width = mode_width;
8418 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (inner, 1),
8419 width, 1, 0, in_code == COMPARE);
8420 break;
8421 }
8422
8423 /* If in_code is COMPARE, it isn't always safe to pass it through
8424 to the recursive make_compound_operation call. */
8425 if (subreg_code == COMPARE
8426 && (!subreg_lowpart_p (x)
8427 || GET_CODE (inner) == SUBREG
8428 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8429 is (const_int 0), rather than
8430 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8431 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8432 for non-equality comparisons against 0 is not equivalent
8433 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8434 || (GET_CODE (inner) == AND
8435 && CONST_INT_P (XEXP (inner, 1))
8436 && partial_subreg_p (x)
8437 && exact_log2 (UINTVAL (XEXP (inner, 1)))
8438 >= GET_MODE_BITSIZE (mode) - 1)))
8439 subreg_code = SET;
8440
8441 tem = make_compound_operation (inner, subreg_code);
8442
8443 simplified
8444 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
8445 if (simplified)
8446 tem = simplified;
8447
8448 if (GET_CODE (tem) != GET_CODE (inner)
8449 && partial_subreg_p (x)
8450 && subreg_lowpart_p (x))
8451 {
8452 rtx newer
8453 = force_to_mode (tem, mode, HOST_WIDE_INT_M1U, 0);
8454
8455 /* If we have something other than a SUBREG, we might have
8456 done an expansion, so rerun ourselves. */
8457 if (GET_CODE (newer) != SUBREG)
8458 newer = make_compound_operation (newer, in_code);
8459
8460 /* force_to_mode can expand compounds. If it just re-expanded
8461 the compound, use gen_lowpart to convert to the desired
8462 mode. */
8463 if (rtx_equal_p (newer, x)
8464 /* Likewise if it re-expanded the compound only partially.
8465 This happens for SUBREG of ZERO_EXTRACT if they extract
8466 the same number of bits. */
8467 || (GET_CODE (newer) == SUBREG
8468 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
8469 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
8470 && GET_CODE (inner) == AND
8471 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
8472 return gen_lowpart (GET_MODE (x), tem);
8473
8474 return newer;
8475 }
8476
8477 if (simplified)
8478 return tem;
8479 }
8480 break;
8481
8482 default:
8483 break;
8484 }
8485
8486 if (new_rtx)
8487 *x_ptr = gen_lowpart (mode, new_rtx);
8488 *next_code_ptr = next_code;
8489 return NULL_RTX;
8490 }
8491
8492 /* Look at the expression rooted at X. Look for expressions
8493 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8494 Form these expressions.
8495
8496 Return the new rtx, usually just X.
8497
8498 Also, for machines like the VAX that don't have logical shift insns,
8499 try to convert logical to arithmetic shift operations in cases where
8500 they are equivalent. This undoes the canonicalizations to logical
8501 shifts done elsewhere.
8502
8503 We try, as much as possible, to re-use rtl expressions to save memory.
8504
8505 IN_CODE says what kind of expression we are processing. Normally, it is
8506 SET. In a memory address it is MEM. When processing the arguments of
8507 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8508 precisely it is an equality comparison against zero. */
8509
8510 rtx
make_compound_operation(rtx x,enum rtx_code in_code)8511 make_compound_operation (rtx x, enum rtx_code in_code)
8512 {
8513 enum rtx_code code = GET_CODE (x);
8514 const char *fmt;
8515 int i, j;
8516 enum rtx_code next_code;
8517 rtx new_rtx, tem;
8518
8519 /* Select the code to be used in recursive calls. Once we are inside an
8520 address, we stay there. If we have a comparison, set to COMPARE,
8521 but once inside, go back to our default of SET. */
8522
8523 next_code = (code == MEM ? MEM
8524 : ((code == COMPARE || COMPARISON_P (x))
8525 && XEXP (x, 1) == const0_rtx) ? COMPARE
8526 : in_code == COMPARE || in_code == EQ ? SET : in_code);
8527
8528 scalar_int_mode mode;
8529 if (is_a <scalar_int_mode> (GET_MODE (x), &mode))
8530 {
8531 rtx new_rtx = make_compound_operation_int (mode, &x, in_code,
8532 &next_code);
8533 if (new_rtx)
8534 return new_rtx;
8535 code = GET_CODE (x);
8536 }
8537
8538 /* Now recursively process each operand of this operation. We need to
8539 handle ZERO_EXTEND specially so that we don't lose track of the
8540 inner mode. */
8541 if (code == ZERO_EXTEND)
8542 {
8543 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8544 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
8545 new_rtx, GET_MODE (XEXP (x, 0)));
8546 if (tem)
8547 return tem;
8548 SUBST (XEXP (x, 0), new_rtx);
8549 return x;
8550 }
8551
8552 fmt = GET_RTX_FORMAT (code);
8553 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8554 if (fmt[i] == 'e')
8555 {
8556 new_rtx = make_compound_operation (XEXP (x, i), next_code);
8557 SUBST (XEXP (x, i), new_rtx);
8558 }
8559 else if (fmt[i] == 'E')
8560 for (j = 0; j < XVECLEN (x, i); j++)
8561 {
8562 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
8563 SUBST (XVECEXP (x, i, j), new_rtx);
8564 }
8565
8566 maybe_swap_commutative_operands (x);
8567 return x;
8568 }
8569
8570 /* Given M see if it is a value that would select a field of bits
8571 within an item, but not the entire word. Return -1 if not.
8572 Otherwise, return the starting position of the field, where 0 is the
8573 low-order bit.
8574
8575 *PLEN is set to the length of the field. */
8576
8577 static int
get_pos_from_mask(unsigned HOST_WIDE_INT m,unsigned HOST_WIDE_INT * plen)8578 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
8579 {
8580 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8581 int pos = m ? ctz_hwi (m) : -1;
8582 int len = 0;
8583
8584 if (pos >= 0)
8585 /* Now shift off the low-order zero bits and see if we have a
8586 power of two minus 1. */
8587 len = exact_log2 ((m >> pos) + 1);
8588
8589 if (len <= 0)
8590 pos = -1;
8591
8592 *plen = len;
8593 return pos;
8594 }
8595
8596 /* If X refers to a register that equals REG in value, replace these
8597 references with REG. */
8598 static rtx
canon_reg_for_combine(rtx x,rtx reg)8599 canon_reg_for_combine (rtx x, rtx reg)
8600 {
8601 rtx op0, op1, op2;
8602 const char *fmt;
8603 int i;
8604 bool copied;
8605
8606 enum rtx_code code = GET_CODE (x);
8607 switch (GET_RTX_CLASS (code))
8608 {
8609 case RTX_UNARY:
8610 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8611 if (op0 != XEXP (x, 0))
8612 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8613 GET_MODE (reg));
8614 break;
8615
8616 case RTX_BIN_ARITH:
8617 case RTX_COMM_ARITH:
8618 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8619 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8620 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8621 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8622 break;
8623
8624 case RTX_COMPARE:
8625 case RTX_COMM_COMPARE:
8626 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8627 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8628 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8629 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8630 GET_MODE (op0), op0, op1);
8631 break;
8632
8633 case RTX_TERNARY:
8634 case RTX_BITFIELD_OPS:
8635 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8636 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8637 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8638 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8639 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8640 GET_MODE (op0), op0, op1, op2);
8641 /* FALLTHRU */
8642
8643 case RTX_OBJ:
8644 if (REG_P (x))
8645 {
8646 if (rtx_equal_p (get_last_value (reg), x)
8647 || rtx_equal_p (reg, get_last_value (x)))
8648 return reg;
8649 else
8650 break;
8651 }
8652
8653 /* fall through */
8654
8655 default:
8656 fmt = GET_RTX_FORMAT (code);
8657 copied = false;
8658 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8659 if (fmt[i] == 'e')
8660 {
8661 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8662 if (op != XEXP (x, i))
8663 {
8664 if (!copied)
8665 {
8666 copied = true;
8667 x = copy_rtx (x);
8668 }
8669 XEXP (x, i) = op;
8670 }
8671 }
8672 else if (fmt[i] == 'E')
8673 {
8674 int j;
8675 for (j = 0; j < XVECLEN (x, i); j++)
8676 {
8677 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8678 if (op != XVECEXP (x, i, j))
8679 {
8680 if (!copied)
8681 {
8682 copied = true;
8683 x = copy_rtx (x);
8684 }
8685 XVECEXP (x, i, j) = op;
8686 }
8687 }
8688 }
8689
8690 break;
8691 }
8692
8693 return x;
8694 }
8695
8696 /* Return X converted to MODE. If the value is already truncated to
8697 MODE we can just return a subreg even though in the general case we
8698 would need an explicit truncation. */
8699
8700 static rtx
gen_lowpart_or_truncate(machine_mode mode,rtx x)8701 gen_lowpart_or_truncate (machine_mode mode, rtx x)
8702 {
8703 if (!CONST_INT_P (x)
8704 && partial_subreg_p (mode, GET_MODE (x))
8705 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8706 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8707 {
8708 /* Bit-cast X into an integer mode. */
8709 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8710 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)).require (), x);
8711 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode).require (),
8712 x, GET_MODE (x));
8713 }
8714
8715 return gen_lowpart (mode, x);
8716 }
8717
8718 /* See if X can be simplified knowing that we will only refer to it in
8719 MODE and will only refer to those bits that are nonzero in MASK.
8720 If other bits are being computed or if masking operations are done
8721 that select a superset of the bits in MASK, they can sometimes be
8722 ignored.
8723
8724 Return a possibly simplified expression, but always convert X to
8725 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8726
8727 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8728 are all off in X. This is used when X will be complemented, by either
8729 NOT, NEG, or XOR. */
8730
8731 static rtx
force_to_mode(rtx x,machine_mode mode,unsigned HOST_WIDE_INT mask,int just_select)8732 force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8733 int just_select)
8734 {
8735 enum rtx_code code = GET_CODE (x);
8736 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8737 machine_mode op_mode;
8738 unsigned HOST_WIDE_INT nonzero;
8739
8740 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8741 code below will do the wrong thing since the mode of such an
8742 expression is VOIDmode.
8743
8744 Also do nothing if X is a CLOBBER; this can happen if X was
8745 the return value from a call to gen_lowpart. */
8746 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8747 return x;
8748
8749 /* We want to perform the operation in its present mode unless we know
8750 that the operation is valid in MODE, in which case we do the operation
8751 in MODE. */
8752 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8753 && have_insn_for (code, mode))
8754 ? mode : GET_MODE (x));
8755
8756 /* It is not valid to do a right-shift in a narrower mode
8757 than the one it came in with. */
8758 if ((code == LSHIFTRT || code == ASHIFTRT)
8759 && partial_subreg_p (mode, GET_MODE (x)))
8760 op_mode = GET_MODE (x);
8761
8762 /* Truncate MASK to fit OP_MODE. */
8763 if (op_mode)
8764 mask &= GET_MODE_MASK (op_mode);
8765
8766 /* Determine what bits of X are guaranteed to be (non)zero. */
8767 nonzero = nonzero_bits (x, mode);
8768
8769 /* If none of the bits in X are needed, return a zero. */
8770 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8771 x = const0_rtx;
8772
8773 /* If X is a CONST_INT, return a new one. Do this here since the
8774 test below will fail. */
8775 if (CONST_INT_P (x))
8776 {
8777 if (SCALAR_INT_MODE_P (mode))
8778 return gen_int_mode (INTVAL (x) & mask, mode);
8779 else
8780 {
8781 x = GEN_INT (INTVAL (x) & mask);
8782 return gen_lowpart_common (mode, x);
8783 }
8784 }
8785
8786 /* If X is narrower than MODE and we want all the bits in X's mode, just
8787 get X in the proper mode. */
8788 if (paradoxical_subreg_p (mode, GET_MODE (x))
8789 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8790 return gen_lowpart (mode, x);
8791
8792 /* We can ignore the effect of a SUBREG if it narrows the mode or
8793 if the constant masks to zero all the bits the mode doesn't have. */
8794 if (GET_CODE (x) == SUBREG
8795 && subreg_lowpart_p (x)
8796 && (partial_subreg_p (x)
8797 || (mask
8798 & GET_MODE_MASK (GET_MODE (x))
8799 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0))
8800 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8801
8802 scalar_int_mode int_mode, xmode;
8803 if (is_a <scalar_int_mode> (mode, &int_mode)
8804 && is_a <scalar_int_mode> (GET_MODE (x), &xmode))
8805 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8806 integer too. */
8807 return force_int_to_mode (x, int_mode, xmode,
8808 as_a <scalar_int_mode> (op_mode),
8809 mask, just_select);
8810
8811 return gen_lowpart_or_truncate (mode, x);
8812 }
8813
8814 /* Subroutine of force_to_mode that handles cases in which both X and
8815 the result are scalar integers. MODE is the mode of the result,
8816 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8817 is preferred for simplified versions of X. The other arguments
8818 are as for force_to_mode. */
8819
8820 static rtx
force_int_to_mode(rtx x,scalar_int_mode mode,scalar_int_mode xmode,scalar_int_mode op_mode,unsigned HOST_WIDE_INT mask,int just_select)8821 force_int_to_mode (rtx x, scalar_int_mode mode, scalar_int_mode xmode,
8822 scalar_int_mode op_mode, unsigned HOST_WIDE_INT mask,
8823 int just_select)
8824 {
8825 enum rtx_code code = GET_CODE (x);
8826 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8827 unsigned HOST_WIDE_INT fuller_mask;
8828 rtx op0, op1, temp;
8829 poly_int64 const_op0;
8830
8831 /* When we have an arithmetic operation, or a shift whose count we
8832 do not know, we need to assume that all bits up to the highest-order
8833 bit in MASK will be needed. This is how we form such a mask. */
8834 if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
8835 fuller_mask = HOST_WIDE_INT_M1U;
8836 else
8837 fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (mask) + 1))
8838 - 1);
8839
8840 switch (code)
8841 {
8842 case CLOBBER:
8843 /* If X is a (clobber (const_int)), return it since we know we are
8844 generating something that won't match. */
8845 return x;
8846
8847 case SIGN_EXTEND:
8848 case ZERO_EXTEND:
8849 case ZERO_EXTRACT:
8850 case SIGN_EXTRACT:
8851 x = expand_compound_operation (x);
8852 if (GET_CODE (x) != code)
8853 return force_to_mode (x, mode, mask, next_select);
8854 break;
8855
8856 case TRUNCATE:
8857 /* Similarly for a truncate. */
8858 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8859
8860 case AND:
8861 /* If this is an AND with a constant, convert it into an AND
8862 whose constant is the AND of that constant with MASK. If it
8863 remains an AND of MASK, delete it since it is redundant. */
8864
8865 if (CONST_INT_P (XEXP (x, 1)))
8866 {
8867 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8868 mask & INTVAL (XEXP (x, 1)));
8869 xmode = op_mode;
8870
8871 /* If X is still an AND, see if it is an AND with a mask that
8872 is just some low-order bits. If so, and it is MASK, we don't
8873 need it. */
8874
8875 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8876 && (INTVAL (XEXP (x, 1)) & GET_MODE_MASK (xmode)) == mask)
8877 x = XEXP (x, 0);
8878
8879 /* If it remains an AND, try making another AND with the bits
8880 in the mode mask that aren't in MASK turned on. If the
8881 constant in the AND is wide enough, this might make a
8882 cheaper constant. */
8883
8884 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8885 && GET_MODE_MASK (xmode) != mask
8886 && HWI_COMPUTABLE_MODE_P (xmode))
8887 {
8888 unsigned HOST_WIDE_INT cval
8889 = UINTVAL (XEXP (x, 1)) | (GET_MODE_MASK (xmode) & ~mask);
8890 rtx y;
8891
8892 y = simplify_gen_binary (AND, xmode, XEXP (x, 0),
8893 gen_int_mode (cval, xmode));
8894 if (set_src_cost (y, xmode, optimize_this_for_speed_p)
8895 < set_src_cost (x, xmode, optimize_this_for_speed_p))
8896 x = y;
8897 }
8898
8899 break;
8900 }
8901
8902 goto binop;
8903
8904 case PLUS:
8905 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8906 low-order bits (as in an alignment operation) and FOO is already
8907 aligned to that boundary, mask C1 to that boundary as well.
8908 This may eliminate that PLUS and, later, the AND. */
8909
8910 {
8911 unsigned int width = GET_MODE_PRECISION (mode);
8912 unsigned HOST_WIDE_INT smask = mask;
8913
8914 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8915 number, sign extend it. */
8916
8917 if (width < HOST_BITS_PER_WIDE_INT
8918 && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8919 smask |= HOST_WIDE_INT_M1U << width;
8920
8921 if (CONST_INT_P (XEXP (x, 1))
8922 && pow2p_hwi (- smask)
8923 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8924 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8925 return force_to_mode (plus_constant (xmode, XEXP (x, 0),
8926 (INTVAL (XEXP (x, 1)) & smask)),
8927 mode, smask, next_select);
8928 }
8929
8930 /* fall through */
8931
8932 case MULT:
8933 /* Substituting into the operands of a widening MULT is not likely to
8934 create RTL matching a machine insn. */
8935 if (code == MULT
8936 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8937 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
8938 && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
8939 || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
8940 && REG_P (XEXP (XEXP (x, 0), 0))
8941 && REG_P (XEXP (XEXP (x, 1), 0)))
8942 return gen_lowpart_or_truncate (mode, x);
8943
8944 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8945 most significant bit in MASK since carries from those bits will
8946 affect the bits we are interested in. */
8947 mask = fuller_mask;
8948 goto binop;
8949
8950 case MINUS:
8951 /* If X is (minus C Y) where C's least set bit is larger than any bit
8952 in the mask, then we may replace with (neg Y). */
8953 if (poly_int_rtx_p (XEXP (x, 0), &const_op0)
8954 && known_alignment (poly_uint64 (const_op0)) > mask)
8955 {
8956 x = simplify_gen_unary (NEG, xmode, XEXP (x, 1), xmode);
8957 return force_to_mode (x, mode, mask, next_select);
8958 }
8959
8960 /* Similarly, if C contains every bit in the fuller_mask, then we may
8961 replace with (not Y). */
8962 if (CONST_INT_P (XEXP (x, 0))
8963 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8964 {
8965 x = simplify_gen_unary (NOT, xmode, XEXP (x, 1), xmode);
8966 return force_to_mode (x, mode, mask, next_select);
8967 }
8968
8969 mask = fuller_mask;
8970 goto binop;
8971
8972 case IOR:
8973 case XOR:
8974 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8975 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8976 operation which may be a bitfield extraction. Ensure that the
8977 constant we form is not wider than the mode of X. */
8978
8979 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8980 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8981 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8982 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8983 && CONST_INT_P (XEXP (x, 1))
8984 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8985 + floor_log2 (INTVAL (XEXP (x, 1))))
8986 < GET_MODE_PRECISION (xmode))
8987 && (UINTVAL (XEXP (x, 1))
8988 & ~nonzero_bits (XEXP (x, 0), xmode)) == 0)
8989 {
8990 temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8991 << INTVAL (XEXP (XEXP (x, 0), 1)),
8992 xmode);
8993 temp = simplify_gen_binary (GET_CODE (x), xmode,
8994 XEXP (XEXP (x, 0), 0), temp);
8995 x = simplify_gen_binary (LSHIFTRT, xmode, temp,
8996 XEXP (XEXP (x, 0), 1));
8997 return force_to_mode (x, mode, mask, next_select);
8998 }
8999
9000 binop:
9001 /* For most binary operations, just propagate into the operation and
9002 change the mode if we have an operation of that mode. */
9003
9004 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
9005 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
9006
9007 /* If we ended up truncating both operands, truncate the result of the
9008 operation instead. */
9009 if (GET_CODE (op0) == TRUNCATE
9010 && GET_CODE (op1) == TRUNCATE)
9011 {
9012 op0 = XEXP (op0, 0);
9013 op1 = XEXP (op1, 0);
9014 }
9015
9016 op0 = gen_lowpart_or_truncate (op_mode, op0);
9017 op1 = gen_lowpart_or_truncate (op_mode, op1);
9018
9019 if (op_mode != xmode || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
9020 {
9021 x = simplify_gen_binary (code, op_mode, op0, op1);
9022 xmode = op_mode;
9023 }
9024 break;
9025
9026 case ASHIFT:
9027 /* For left shifts, do the same, but just for the first operand.
9028 However, we cannot do anything with shifts where we cannot
9029 guarantee that the counts are smaller than the size of the mode
9030 because such a count will have a different meaning in a
9031 wider mode. */
9032
9033 if (! (CONST_INT_P (XEXP (x, 1))
9034 && INTVAL (XEXP (x, 1)) >= 0
9035 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
9036 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
9037 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
9038 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
9039 break;
9040
9041 /* If the shift count is a constant and we can do arithmetic in
9042 the mode of the shift, refine which bits we need. Otherwise, use the
9043 conservative form of the mask. */
9044 if (CONST_INT_P (XEXP (x, 1))
9045 && INTVAL (XEXP (x, 1)) >= 0
9046 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
9047 && HWI_COMPUTABLE_MODE_P (op_mode))
9048 mask >>= INTVAL (XEXP (x, 1));
9049 else
9050 mask = fuller_mask;
9051
9052 op0 = gen_lowpart_or_truncate (op_mode,
9053 force_to_mode (XEXP (x, 0), mode,
9054 mask, next_select));
9055
9056 if (op_mode != xmode || op0 != XEXP (x, 0))
9057 {
9058 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
9059 xmode = op_mode;
9060 }
9061 break;
9062
9063 case LSHIFTRT:
9064 /* Here we can only do something if the shift count is a constant,
9065 this shift constant is valid for the host, and we can do arithmetic
9066 in OP_MODE. */
9067
9068 if (CONST_INT_P (XEXP (x, 1))
9069 && INTVAL (XEXP (x, 1)) >= 0
9070 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
9071 && HWI_COMPUTABLE_MODE_P (op_mode))
9072 {
9073 rtx inner = XEXP (x, 0);
9074 unsigned HOST_WIDE_INT inner_mask;
9075
9076 /* Select the mask of the bits we need for the shift operand. */
9077 inner_mask = mask << INTVAL (XEXP (x, 1));
9078
9079 /* We can only change the mode of the shift if we can do arithmetic
9080 in the mode of the shift and INNER_MASK is no wider than the
9081 width of X's mode. */
9082 if ((inner_mask & ~GET_MODE_MASK (xmode)) != 0)
9083 op_mode = xmode;
9084
9085 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
9086
9087 if (xmode != op_mode || inner != XEXP (x, 0))
9088 {
9089 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
9090 xmode = op_mode;
9091 }
9092 }
9093
9094 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9095 shift and AND produces only copies of the sign bit (C2 is one less
9096 than a power of two), we can do this with just a shift. */
9097
9098 if (GET_CODE (x) == LSHIFTRT
9099 && CONST_INT_P (XEXP (x, 1))
9100 /* The shift puts one of the sign bit copies in the least significant
9101 bit. */
9102 && ((INTVAL (XEXP (x, 1))
9103 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
9104 >= GET_MODE_PRECISION (xmode))
9105 && pow2p_hwi (mask + 1)
9106 /* Number of bits left after the shift must be more than the mask
9107 needs. */
9108 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
9109 <= GET_MODE_PRECISION (xmode))
9110 /* Must be more sign bit copies than the mask needs. */
9111 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
9112 >= exact_log2 (mask + 1)))
9113 {
9114 int nbits = GET_MODE_PRECISION (xmode) - exact_log2 (mask + 1);
9115 x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0),
9116 gen_int_shift_amount (xmode, nbits));
9117 }
9118 goto shiftrt;
9119
9120 case ASHIFTRT:
9121 /* If we are just looking for the sign bit, we don't need this shift at
9122 all, even if it has a variable count. */
9123 if (val_signbit_p (xmode, mask))
9124 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9125
9126 /* If this is a shift by a constant, get a mask that contains those bits
9127 that are not copies of the sign bit. We then have two cases: If
9128 MASK only includes those bits, this can be a logical shift, which may
9129 allow simplifications. If MASK is a single-bit field not within
9130 those bits, we are requesting a copy of the sign bit and hence can
9131 shift the sign bit to the appropriate location. */
9132
9133 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
9134 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
9135 {
9136 unsigned HOST_WIDE_INT nonzero;
9137 int i;
9138
9139 /* If the considered data is wider than HOST_WIDE_INT, we can't
9140 represent a mask for all its bits in a single scalar.
9141 But we only care about the lower bits, so calculate these. */
9142
9143 if (GET_MODE_PRECISION (xmode) > HOST_BITS_PER_WIDE_INT)
9144 {
9145 nonzero = HOST_WIDE_INT_M1U;
9146
9147 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9148 is the number of bits a full-width mask would have set.
9149 We need only shift if these are fewer than nonzero can
9150 hold. If not, we must keep all bits set in nonzero. */
9151
9152 if (GET_MODE_PRECISION (xmode) - INTVAL (XEXP (x, 1))
9153 < HOST_BITS_PER_WIDE_INT)
9154 nonzero >>= INTVAL (XEXP (x, 1))
9155 + HOST_BITS_PER_WIDE_INT
9156 - GET_MODE_PRECISION (xmode);
9157 }
9158 else
9159 {
9160 nonzero = GET_MODE_MASK (xmode);
9161 nonzero >>= INTVAL (XEXP (x, 1));
9162 }
9163
9164 if ((mask & ~nonzero) == 0)
9165 {
9166 x = simplify_shift_const (NULL_RTX, LSHIFTRT, xmode,
9167 XEXP (x, 0), INTVAL (XEXP (x, 1)));
9168 if (GET_CODE (x) != ASHIFTRT)
9169 return force_to_mode (x, mode, mask, next_select);
9170 }
9171
9172 else if ((i = exact_log2 (mask)) >= 0)
9173 {
9174 x = simplify_shift_const
9175 (NULL_RTX, LSHIFTRT, xmode, XEXP (x, 0),
9176 GET_MODE_PRECISION (xmode) - 1 - i);
9177
9178 if (GET_CODE (x) != ASHIFTRT)
9179 return force_to_mode (x, mode, mask, next_select);
9180 }
9181 }
9182
9183 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9184 even if the shift count isn't a constant. */
9185 if (mask == 1)
9186 x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0), XEXP (x, 1));
9187
9188 shiftrt:
9189
9190 /* If this is a zero- or sign-extension operation that just affects bits
9191 we don't care about, remove it. Be sure the call above returned
9192 something that is still a shift. */
9193
9194 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
9195 && CONST_INT_P (XEXP (x, 1))
9196 && INTVAL (XEXP (x, 1)) >= 0
9197 && (INTVAL (XEXP (x, 1))
9198 <= GET_MODE_PRECISION (xmode) - (floor_log2 (mask) + 1))
9199 && GET_CODE (XEXP (x, 0)) == ASHIFT
9200 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
9201 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
9202 next_select);
9203
9204 break;
9205
9206 case ROTATE:
9207 case ROTATERT:
9208 /* If the shift count is constant and we can do computations
9209 in the mode of X, compute where the bits we care about are.
9210 Otherwise, we can't do anything. Don't change the mode of
9211 the shift or propagate MODE into the shift, though. */
9212 if (CONST_INT_P (XEXP (x, 1))
9213 && INTVAL (XEXP (x, 1)) >= 0)
9214 {
9215 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
9216 xmode, gen_int_mode (mask, xmode),
9217 XEXP (x, 1));
9218 if (temp && CONST_INT_P (temp))
9219 x = simplify_gen_binary (code, xmode,
9220 force_to_mode (XEXP (x, 0), xmode,
9221 INTVAL (temp), next_select),
9222 XEXP (x, 1));
9223 }
9224 break;
9225
9226 case NEG:
9227 /* If we just want the low-order bit, the NEG isn't needed since it
9228 won't change the low-order bit. */
9229 if (mask == 1)
9230 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
9231
9232 /* We need any bits less significant than the most significant bit in
9233 MASK since carries from those bits will affect the bits we are
9234 interested in. */
9235 mask = fuller_mask;
9236 goto unop;
9237
9238 case NOT:
9239 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9240 same as the XOR case above. Ensure that the constant we form is not
9241 wider than the mode of X. */
9242
9243 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
9244 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9245 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
9246 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
9247 < GET_MODE_PRECISION (xmode))
9248 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9249 {
9250 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), xmode);
9251 temp = simplify_gen_binary (XOR, xmode, XEXP (XEXP (x, 0), 0), temp);
9252 x = simplify_gen_binary (LSHIFTRT, xmode,
9253 temp, XEXP (XEXP (x, 0), 1));
9254
9255 return force_to_mode (x, mode, mask, next_select);
9256 }
9257
9258 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9259 use the full mask inside the NOT. */
9260 mask = fuller_mask;
9261
9262 unop:
9263 op0 = gen_lowpart_or_truncate (op_mode,
9264 force_to_mode (XEXP (x, 0), mode, mask,
9265 next_select));
9266 if (op_mode != xmode || op0 != XEXP (x, 0))
9267 {
9268 x = simplify_gen_unary (code, op_mode, op0, op_mode);
9269 xmode = op_mode;
9270 }
9271 break;
9272
9273 case NE:
9274 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9275 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9276 which is equal to STORE_FLAG_VALUE. */
9277 if ((mask & ~STORE_FLAG_VALUE) == 0
9278 && XEXP (x, 1) == const0_rtx
9279 && GET_MODE (XEXP (x, 0)) == mode
9280 && pow2p_hwi (nonzero_bits (XEXP (x, 0), mode))
9281 && (nonzero_bits (XEXP (x, 0), mode)
9282 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
9283 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9284
9285 break;
9286
9287 case IF_THEN_ELSE:
9288 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9289 written in a narrower mode. We play it safe and do not do so. */
9290
9291 op0 = gen_lowpart_or_truncate (xmode,
9292 force_to_mode (XEXP (x, 1), mode,
9293 mask, next_select));
9294 op1 = gen_lowpart_or_truncate (xmode,
9295 force_to_mode (XEXP (x, 2), mode,
9296 mask, next_select));
9297 if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
9298 x = simplify_gen_ternary (IF_THEN_ELSE, xmode,
9299 GET_MODE (XEXP (x, 0)), XEXP (x, 0),
9300 op0, op1);
9301 break;
9302
9303 default:
9304 break;
9305 }
9306
9307 /* Ensure we return a value of the proper mode. */
9308 return gen_lowpart_or_truncate (mode, x);
9309 }
9310
9311 /* Return nonzero if X is an expression that has one of two values depending on
9312 whether some other value is zero or nonzero. In that case, we return the
9313 value that is being tested, *PTRUE is set to the value if the rtx being
9314 returned has a nonzero value, and *PFALSE is set to the other alternative.
9315
9316 If we return zero, we set *PTRUE and *PFALSE to X. */
9317
9318 static rtx
if_then_else_cond(rtx x,rtx * ptrue,rtx * pfalse)9319 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
9320 {
9321 machine_mode mode = GET_MODE (x);
9322 enum rtx_code code = GET_CODE (x);
9323 rtx cond0, cond1, true0, true1, false0, false1;
9324 unsigned HOST_WIDE_INT nz;
9325 scalar_int_mode int_mode;
9326
9327 /* If we are comparing a value against zero, we are done. */
9328 if ((code == NE || code == EQ)
9329 && XEXP (x, 1) == const0_rtx)
9330 {
9331 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
9332 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
9333 return XEXP (x, 0);
9334 }
9335
9336 /* If this is a unary operation whose operand has one of two values, apply
9337 our opcode to compute those values. */
9338 else if (UNARY_P (x)
9339 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
9340 {
9341 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
9342 *pfalse = simplify_gen_unary (code, mode, false0,
9343 GET_MODE (XEXP (x, 0)));
9344 return cond0;
9345 }
9346
9347 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9348 make can't possibly match and would suppress other optimizations. */
9349 else if (code == COMPARE)
9350 ;
9351
9352 /* If this is a binary operation, see if either side has only one of two
9353 values. If either one does or if both do and they are conditional on
9354 the same value, compute the new true and false values. */
9355 else if (BINARY_P (x))
9356 {
9357 rtx op0 = XEXP (x, 0);
9358 rtx op1 = XEXP (x, 1);
9359 cond0 = if_then_else_cond (op0, &true0, &false0);
9360 cond1 = if_then_else_cond (op1, &true1, &false1);
9361
9362 if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))
9363 && (REG_P (op0) || REG_P (op1)))
9364 {
9365 /* Try to enable a simplification by undoing work done by
9366 if_then_else_cond if it converted a REG into something more
9367 complex. */
9368 if (REG_P (op0))
9369 {
9370 cond0 = 0;
9371 true0 = false0 = op0;
9372 }
9373 else
9374 {
9375 cond1 = 0;
9376 true1 = false1 = op1;
9377 }
9378 }
9379
9380 if ((cond0 != 0 || cond1 != 0)
9381 && ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)))
9382 {
9383 /* If if_then_else_cond returned zero, then true/false are the
9384 same rtl. We must copy one of them to prevent invalid rtl
9385 sharing. */
9386 if (cond0 == 0)
9387 true0 = copy_rtx (true0);
9388 else if (cond1 == 0)
9389 true1 = copy_rtx (true1);
9390
9391 if (COMPARISON_P (x))
9392 {
9393 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
9394 true0, true1);
9395 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
9396 false0, false1);
9397 }
9398 else
9399 {
9400 *ptrue = simplify_gen_binary (code, mode, true0, true1);
9401 *pfalse = simplify_gen_binary (code, mode, false0, false1);
9402 }
9403
9404 return cond0 ? cond0 : cond1;
9405 }
9406
9407 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9408 operands is zero when the other is nonzero, and vice-versa,
9409 and STORE_FLAG_VALUE is 1 or -1. */
9410
9411 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9412 && (code == PLUS || code == IOR || code == XOR || code == MINUS
9413 || code == UMAX)
9414 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9415 {
9416 rtx op0 = XEXP (XEXP (x, 0), 1);
9417 rtx op1 = XEXP (XEXP (x, 1), 1);
9418
9419 cond0 = XEXP (XEXP (x, 0), 0);
9420 cond1 = XEXP (XEXP (x, 1), 0);
9421
9422 if (COMPARISON_P (cond0)
9423 && COMPARISON_P (cond1)
9424 && SCALAR_INT_MODE_P (mode)
9425 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9426 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9427 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9428 || ((swap_condition (GET_CODE (cond0))
9429 == reversed_comparison_code (cond1, NULL))
9430 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9431 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9432 && ! side_effects_p (x))
9433 {
9434 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
9435 *pfalse = simplify_gen_binary (MULT, mode,
9436 (code == MINUS
9437 ? simplify_gen_unary (NEG, mode,
9438 op1, mode)
9439 : op1),
9440 const_true_rtx);
9441 return cond0;
9442 }
9443 }
9444
9445 /* Similarly for MULT, AND and UMIN, except that for these the result
9446 is always zero. */
9447 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9448 && (code == MULT || code == AND || code == UMIN)
9449 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9450 {
9451 cond0 = XEXP (XEXP (x, 0), 0);
9452 cond1 = XEXP (XEXP (x, 1), 0);
9453
9454 if (COMPARISON_P (cond0)
9455 && COMPARISON_P (cond1)
9456 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9457 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9458 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9459 || ((swap_condition (GET_CODE (cond0))
9460 == reversed_comparison_code (cond1, NULL))
9461 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9462 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9463 && ! side_effects_p (x))
9464 {
9465 *ptrue = *pfalse = const0_rtx;
9466 return cond0;
9467 }
9468 }
9469 }
9470
9471 else if (code == IF_THEN_ELSE)
9472 {
9473 /* If we have IF_THEN_ELSE already, extract the condition and
9474 canonicalize it if it is NE or EQ. */
9475 cond0 = XEXP (x, 0);
9476 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
9477 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
9478 return XEXP (cond0, 0);
9479 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
9480 {
9481 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
9482 return XEXP (cond0, 0);
9483 }
9484 else
9485 return cond0;
9486 }
9487
9488 /* If X is a SUBREG, we can narrow both the true and false values
9489 if the inner expression, if there is a condition. */
9490 else if (code == SUBREG
9491 && (cond0 = if_then_else_cond (SUBREG_REG (x), &true0,
9492 &false0)) != 0)
9493 {
9494 true0 = simplify_gen_subreg (mode, true0,
9495 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9496 false0 = simplify_gen_subreg (mode, false0,
9497 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9498 if (true0 && false0)
9499 {
9500 *ptrue = true0;
9501 *pfalse = false0;
9502 return cond0;
9503 }
9504 }
9505
9506 /* If X is a constant, this isn't special and will cause confusions
9507 if we treat it as such. Likewise if it is equivalent to a constant. */
9508 else if (CONSTANT_P (x)
9509 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
9510 ;
9511
9512 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9513 will be least confusing to the rest of the compiler. */
9514 else if (mode == BImode)
9515 {
9516 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
9517 return x;
9518 }
9519
9520 /* If X is known to be either 0 or -1, those are the true and
9521 false values when testing X. */
9522 else if (x == constm1_rtx || x == const0_rtx
9523 || (is_a <scalar_int_mode> (mode, &int_mode)
9524 && (num_sign_bit_copies (x, int_mode)
9525 == GET_MODE_PRECISION (int_mode))))
9526 {
9527 *ptrue = constm1_rtx, *pfalse = const0_rtx;
9528 return x;
9529 }
9530
9531 /* Likewise for 0 or a single bit. */
9532 else if (HWI_COMPUTABLE_MODE_P (mode)
9533 && pow2p_hwi (nz = nonzero_bits (x, mode)))
9534 {
9535 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
9536 return x;
9537 }
9538
9539 /* Otherwise fail; show no condition with true and false values the same. */
9540 *ptrue = *pfalse = x;
9541 return 0;
9542 }
9543
9544 /* Return the value of expression X given the fact that condition COND
9545 is known to be true when applied to REG as its first operand and VAL
9546 as its second. X is known to not be shared and so can be modified in
9547 place.
9548
9549 We only handle the simplest cases, and specifically those cases that
9550 arise with IF_THEN_ELSE expressions. */
9551
9552 static rtx
known_cond(rtx x,enum rtx_code cond,rtx reg,rtx val)9553 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
9554 {
9555 enum rtx_code code = GET_CODE (x);
9556 const char *fmt;
9557 int i, j;
9558
9559 if (side_effects_p (x))
9560 return x;
9561
9562 /* If either operand of the condition is a floating point value,
9563 then we have to avoid collapsing an EQ comparison. */
9564 if (cond == EQ
9565 && rtx_equal_p (x, reg)
9566 && ! FLOAT_MODE_P (GET_MODE (x))
9567 && ! FLOAT_MODE_P (GET_MODE (val)))
9568 return val;
9569
9570 if (cond == UNEQ && rtx_equal_p (x, reg))
9571 return val;
9572
9573 /* If X is (abs REG) and we know something about REG's relationship
9574 with zero, we may be able to simplify this. */
9575
9576 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
9577 switch (cond)
9578 {
9579 case GE: case GT: case EQ:
9580 return XEXP (x, 0);
9581 case LT: case LE:
9582 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
9583 XEXP (x, 0),
9584 GET_MODE (XEXP (x, 0)));
9585 default:
9586 break;
9587 }
9588
9589 /* The only other cases we handle are MIN, MAX, and comparisons if the
9590 operands are the same as REG and VAL. */
9591
9592 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
9593 {
9594 if (rtx_equal_p (XEXP (x, 0), val))
9595 {
9596 std::swap (val, reg);
9597 cond = swap_condition (cond);
9598 }
9599
9600 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
9601 {
9602 if (COMPARISON_P (x))
9603 {
9604 if (comparison_dominates_p (cond, code))
9605 return VECTOR_MODE_P (GET_MODE (x)) ? x : const_true_rtx;
9606
9607 code = reversed_comparison_code (x, NULL);
9608 if (code != UNKNOWN
9609 && comparison_dominates_p (cond, code))
9610 return CONST0_RTX (GET_MODE (x));
9611 else
9612 return x;
9613 }
9614 else if (code == SMAX || code == SMIN
9615 || code == UMIN || code == UMAX)
9616 {
9617 int unsignedp = (code == UMIN || code == UMAX);
9618
9619 /* Do not reverse the condition when it is NE or EQ.
9620 This is because we cannot conclude anything about
9621 the value of 'SMAX (x, y)' when x is not equal to y,
9622 but we can when x equals y. */
9623 if ((code == SMAX || code == UMAX)
9624 && ! (cond == EQ || cond == NE))
9625 cond = reverse_condition (cond);
9626
9627 switch (cond)
9628 {
9629 case GE: case GT:
9630 return unsignedp ? x : XEXP (x, 1);
9631 case LE: case LT:
9632 return unsignedp ? x : XEXP (x, 0);
9633 case GEU: case GTU:
9634 return unsignedp ? XEXP (x, 1) : x;
9635 case LEU: case LTU:
9636 return unsignedp ? XEXP (x, 0) : x;
9637 default:
9638 break;
9639 }
9640 }
9641 }
9642 }
9643 else if (code == SUBREG)
9644 {
9645 machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
9646 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
9647
9648 if (SUBREG_REG (x) != r)
9649 {
9650 /* We must simplify subreg here, before we lose track of the
9651 original inner_mode. */
9652 new_rtx = simplify_subreg (GET_MODE (x), r,
9653 inner_mode, SUBREG_BYTE (x));
9654 if (new_rtx)
9655 return new_rtx;
9656 else
9657 SUBST (SUBREG_REG (x), r);
9658 }
9659
9660 return x;
9661 }
9662 /* We don't have to handle SIGN_EXTEND here, because even in the
9663 case of replacing something with a modeless CONST_INT, a
9664 CONST_INT is already (supposed to be) a valid sign extension for
9665 its narrower mode, which implies it's already properly
9666 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9667 story is different. */
9668 else if (code == ZERO_EXTEND)
9669 {
9670 machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9671 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9672
9673 if (XEXP (x, 0) != r)
9674 {
9675 /* We must simplify the zero_extend here, before we lose
9676 track of the original inner_mode. */
9677 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9678 r, inner_mode);
9679 if (new_rtx)
9680 return new_rtx;
9681 else
9682 SUBST (XEXP (x, 0), r);
9683 }
9684
9685 return x;
9686 }
9687
9688 fmt = GET_RTX_FORMAT (code);
9689 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9690 {
9691 if (fmt[i] == 'e')
9692 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9693 else if (fmt[i] == 'E')
9694 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9695 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9696 cond, reg, val));
9697 }
9698
9699 return x;
9700 }
9701
9702 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9703 assignment as a field assignment. */
9704
9705 static int
rtx_equal_for_field_assignment_p(rtx x,rtx y,bool widen_x)9706 rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
9707 {
9708 if (widen_x && GET_MODE (x) != GET_MODE (y))
9709 {
9710 if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (y)))
9711 return 0;
9712 if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
9713 return 0;
9714 x = adjust_address_nv (x, GET_MODE (y),
9715 byte_lowpart_offset (GET_MODE (y),
9716 GET_MODE (x)));
9717 }
9718
9719 if (x == y || rtx_equal_p (x, y))
9720 return 1;
9721
9722 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9723 return 0;
9724
9725 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9726 Note that all SUBREGs of MEM are paradoxical; otherwise they
9727 would have been rewritten. */
9728 if (MEM_P (x) && GET_CODE (y) == SUBREG
9729 && MEM_P (SUBREG_REG (y))
9730 && rtx_equal_p (SUBREG_REG (y),
9731 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9732 return 1;
9733
9734 if (MEM_P (y) && GET_CODE (x) == SUBREG
9735 && MEM_P (SUBREG_REG (x))
9736 && rtx_equal_p (SUBREG_REG (x),
9737 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9738 return 1;
9739
9740 /* We used to see if get_last_value of X and Y were the same but that's
9741 not correct. In one direction, we'll cause the assignment to have
9742 the wrong destination and in the case, we'll import a register into this
9743 insn that might have already have been dead. So fail if none of the
9744 above cases are true. */
9745 return 0;
9746 }
9747
9748 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9749 Return that assignment if so.
9750
9751 We only handle the most common cases. */
9752
9753 static rtx
make_field_assignment(rtx x)9754 make_field_assignment (rtx x)
9755 {
9756 rtx dest = SET_DEST (x);
9757 rtx src = SET_SRC (x);
9758 rtx assign;
9759 rtx rhs, lhs;
9760 HOST_WIDE_INT c1;
9761 HOST_WIDE_INT pos;
9762 unsigned HOST_WIDE_INT len;
9763 rtx other;
9764
9765 /* All the rules in this function are specific to scalar integers. */
9766 scalar_int_mode mode;
9767 if (!is_a <scalar_int_mode> (GET_MODE (dest), &mode))
9768 return x;
9769
9770 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9771 a clear of a one-bit field. We will have changed it to
9772 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9773 for a SUBREG. */
9774
9775 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9776 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9777 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9778 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9779 {
9780 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9781 1, 1, 1, 0);
9782 if (assign != 0)
9783 return gen_rtx_SET (assign, const0_rtx);
9784 return x;
9785 }
9786
9787 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9788 && subreg_lowpart_p (XEXP (src, 0))
9789 && partial_subreg_p (XEXP (src, 0))
9790 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9791 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9792 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9793 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9794 {
9795 assign = make_extraction (VOIDmode, dest, 0,
9796 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9797 1, 1, 1, 0);
9798 if (assign != 0)
9799 return gen_rtx_SET (assign, const0_rtx);
9800 return x;
9801 }
9802
9803 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9804 one-bit field. */
9805 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9806 && XEXP (XEXP (src, 0), 0) == const1_rtx
9807 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9808 {
9809 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9810 1, 1, 1, 0);
9811 if (assign != 0)
9812 return gen_rtx_SET (assign, const1_rtx);
9813 return x;
9814 }
9815
9816 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9817 SRC is an AND with all bits of that field set, then we can discard
9818 the AND. */
9819 if (GET_CODE (dest) == ZERO_EXTRACT
9820 && CONST_INT_P (XEXP (dest, 1))
9821 && GET_CODE (src) == AND
9822 && CONST_INT_P (XEXP (src, 1)))
9823 {
9824 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9825 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9826 unsigned HOST_WIDE_INT ze_mask;
9827
9828 if (width >= HOST_BITS_PER_WIDE_INT)
9829 ze_mask = -1;
9830 else
9831 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9832
9833 /* Complete overlap. We can remove the source AND. */
9834 if ((and_mask & ze_mask) == ze_mask)
9835 return gen_rtx_SET (dest, XEXP (src, 0));
9836
9837 /* Partial overlap. We can reduce the source AND. */
9838 if ((and_mask & ze_mask) != and_mask)
9839 {
9840 src = gen_rtx_AND (mode, XEXP (src, 0),
9841 gen_int_mode (and_mask & ze_mask, mode));
9842 return gen_rtx_SET (dest, src);
9843 }
9844 }
9845
9846 /* The other case we handle is assignments into a constant-position
9847 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9848 a mask that has all one bits except for a group of zero bits and
9849 OTHER is known to have zeros where C1 has ones, this is such an
9850 assignment. Compute the position and length from C1. Shift OTHER
9851 to the appropriate position, force it to the required mode, and
9852 make the extraction. Check for the AND in both operands. */
9853
9854 /* One or more SUBREGs might obscure the constant-position field
9855 assignment. The first one we are likely to encounter is an outer
9856 narrowing SUBREG, which we can just strip for the purposes of
9857 identifying the constant-field assignment. */
9858 scalar_int_mode src_mode = mode;
9859 if (GET_CODE (src) == SUBREG
9860 && subreg_lowpart_p (src)
9861 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
9862 src = SUBREG_REG (src);
9863
9864 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9865 return x;
9866
9867 rhs = expand_compound_operation (XEXP (src, 0));
9868 lhs = expand_compound_operation (XEXP (src, 1));
9869
9870 if (GET_CODE (rhs) == AND
9871 && CONST_INT_P (XEXP (rhs, 1))
9872 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9873 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9874 /* The second SUBREG that might get in the way is a paradoxical
9875 SUBREG around the first operand of the AND. We want to
9876 pretend the operand is as wide as the destination here. We
9877 do this by adjusting the MEM to wider mode for the sole
9878 purpose of the call to rtx_equal_for_field_assignment_p. Also
9879 note this trick only works for MEMs. */
9880 else if (GET_CODE (rhs) == AND
9881 && paradoxical_subreg_p (XEXP (rhs, 0))
9882 && MEM_P (SUBREG_REG (XEXP (rhs, 0)))
9883 && CONST_INT_P (XEXP (rhs, 1))
9884 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)),
9885 dest, true))
9886 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9887 else if (GET_CODE (lhs) == AND
9888 && CONST_INT_P (XEXP (lhs, 1))
9889 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9890 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9891 /* The second SUBREG that might get in the way is a paradoxical
9892 SUBREG around the first operand of the AND. We want to
9893 pretend the operand is as wide as the destination here. We
9894 do this by adjusting the MEM to wider mode for the sole
9895 purpose of the call to rtx_equal_for_field_assignment_p. Also
9896 note this trick only works for MEMs. */
9897 else if (GET_CODE (lhs) == AND
9898 && paradoxical_subreg_p (XEXP (lhs, 0))
9899 && MEM_P (SUBREG_REG (XEXP (lhs, 0)))
9900 && CONST_INT_P (XEXP (lhs, 1))
9901 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)),
9902 dest, true))
9903 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9904 else
9905 return x;
9906
9907 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (mode), &len);
9908 if (pos < 0
9909 || pos + len > GET_MODE_PRECISION (mode)
9910 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
9911 || (c1 & nonzero_bits (other, mode)) != 0)
9912 return x;
9913
9914 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9915 if (assign == 0)
9916 return x;
9917
9918 /* The mode to use for the source is the mode of the assignment, or of
9919 what is inside a possible STRICT_LOW_PART. */
9920 machine_mode new_mode = (GET_CODE (assign) == STRICT_LOW_PART
9921 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9922
9923 /* Shift OTHER right POS places and make it the source, restricting it
9924 to the proper length and mode. */
9925
9926 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9927 src_mode, other, pos),
9928 dest);
9929 src = force_to_mode (src, new_mode,
9930 len >= HOST_BITS_PER_WIDE_INT
9931 ? HOST_WIDE_INT_M1U
9932 : (HOST_WIDE_INT_1U << len) - 1,
9933 0);
9934
9935 /* If SRC is masked by an AND that does not make a difference in
9936 the value being stored, strip it. */
9937 if (GET_CODE (assign) == ZERO_EXTRACT
9938 && CONST_INT_P (XEXP (assign, 1))
9939 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9940 && GET_CODE (src) == AND
9941 && CONST_INT_P (XEXP (src, 1))
9942 && UINTVAL (XEXP (src, 1))
9943 == (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1)
9944 src = XEXP (src, 0);
9945
9946 return gen_rtx_SET (assign, src);
9947 }
9948
9949 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9950 if so. */
9951
9952 static rtx
apply_distributive_law(rtx x)9953 apply_distributive_law (rtx x)
9954 {
9955 enum rtx_code code = GET_CODE (x);
9956 enum rtx_code inner_code;
9957 rtx lhs, rhs, other;
9958 rtx tem;
9959
9960 /* Distributivity is not true for floating point as it can change the
9961 value. So we don't do it unless -funsafe-math-optimizations. */
9962 if (FLOAT_MODE_P (GET_MODE (x))
9963 && ! flag_unsafe_math_optimizations)
9964 return x;
9965
9966 /* The outer operation can only be one of the following: */
9967 if (code != IOR && code != AND && code != XOR
9968 && code != PLUS && code != MINUS)
9969 return x;
9970
9971 lhs = XEXP (x, 0);
9972 rhs = XEXP (x, 1);
9973
9974 /* If either operand is a primitive we can't do anything, so get out
9975 fast. */
9976 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9977 return x;
9978
9979 lhs = expand_compound_operation (lhs);
9980 rhs = expand_compound_operation (rhs);
9981 inner_code = GET_CODE (lhs);
9982 if (inner_code != GET_CODE (rhs))
9983 return x;
9984
9985 /* See if the inner and outer operations distribute. */
9986 switch (inner_code)
9987 {
9988 case LSHIFTRT:
9989 case ASHIFTRT:
9990 case AND:
9991 case IOR:
9992 /* These all distribute except over PLUS. */
9993 if (code == PLUS || code == MINUS)
9994 return x;
9995 break;
9996
9997 case MULT:
9998 if (code != PLUS && code != MINUS)
9999 return x;
10000 break;
10001
10002 case ASHIFT:
10003 /* This is also a multiply, so it distributes over everything. */
10004 break;
10005
10006 /* This used to handle SUBREG, but this turned out to be counter-
10007 productive, since (subreg (op ...)) usually is not handled by
10008 insn patterns, and this "optimization" therefore transformed
10009 recognizable patterns into unrecognizable ones. Therefore the
10010 SUBREG case was removed from here.
10011
10012 It is possible that distributing SUBREG over arithmetic operations
10013 leads to an intermediate result than can then be optimized further,
10014 e.g. by moving the outer SUBREG to the other side of a SET as done
10015 in simplify_set. This seems to have been the original intent of
10016 handling SUBREGs here.
10017
10018 However, with current GCC this does not appear to actually happen,
10019 at least on major platforms. If some case is found where removing
10020 the SUBREG case here prevents follow-on optimizations, distributing
10021 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
10022
10023 default:
10024 return x;
10025 }
10026
10027 /* Set LHS and RHS to the inner operands (A and B in the example
10028 above) and set OTHER to the common operand (C in the example).
10029 There is only one way to do this unless the inner operation is
10030 commutative. */
10031 if (COMMUTATIVE_ARITH_P (lhs)
10032 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
10033 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
10034 else if (COMMUTATIVE_ARITH_P (lhs)
10035 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
10036 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
10037 else if (COMMUTATIVE_ARITH_P (lhs)
10038 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
10039 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
10040 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
10041 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
10042 else
10043 return x;
10044
10045 /* Form the new inner operation, seeing if it simplifies first. */
10046 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
10047
10048 /* There is one exception to the general way of distributing:
10049 (a | c) ^ (b | c) -> (a ^ b) & ~c */
10050 if (code == XOR && inner_code == IOR)
10051 {
10052 inner_code = AND;
10053 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
10054 }
10055
10056 /* We may be able to continuing distributing the result, so call
10057 ourselves recursively on the inner operation before forming the
10058 outer operation, which we return. */
10059 return simplify_gen_binary (inner_code, GET_MODE (x),
10060 apply_distributive_law (tem), other);
10061 }
10062
10063 /* See if X is of the form (* (+ A B) C), and if so convert to
10064 (+ (* A C) (* B C)) and try to simplify.
10065
10066 Most of the time, this results in no change. However, if some of
10067 the operands are the same or inverses of each other, simplifications
10068 will result.
10069
10070 For example, (and (ior A B) (not B)) can occur as the result of
10071 expanding a bit field assignment. When we apply the distributive
10072 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10073 which then simplifies to (and (A (not B))).
10074
10075 Note that no checks happen on the validity of applying the inverse
10076 distributive law. This is pointless since we can do it in the
10077 few places where this routine is called.
10078
10079 N is the index of the term that is decomposed (the arithmetic operation,
10080 i.e. (+ A B) in the first example above). !N is the index of the term that
10081 is distributed, i.e. of C in the first example above. */
10082 static rtx
distribute_and_simplify_rtx(rtx x,int n)10083 distribute_and_simplify_rtx (rtx x, int n)
10084 {
10085 machine_mode mode;
10086 enum rtx_code outer_code, inner_code;
10087 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
10088
10089 /* Distributivity is not true for floating point as it can change the
10090 value. So we don't do it unless -funsafe-math-optimizations. */
10091 if (FLOAT_MODE_P (GET_MODE (x))
10092 && ! flag_unsafe_math_optimizations)
10093 return NULL_RTX;
10094
10095 decomposed = XEXP (x, n);
10096 if (!ARITHMETIC_P (decomposed))
10097 return NULL_RTX;
10098
10099 mode = GET_MODE (x);
10100 outer_code = GET_CODE (x);
10101 distributed = XEXP (x, !n);
10102
10103 inner_code = GET_CODE (decomposed);
10104 inner_op0 = XEXP (decomposed, 0);
10105 inner_op1 = XEXP (decomposed, 1);
10106
10107 /* Special case (and (xor B C) (not A)), which is equivalent to
10108 (xor (ior A B) (ior A C)) */
10109 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
10110 {
10111 distributed = XEXP (distributed, 0);
10112 outer_code = IOR;
10113 }
10114
10115 if (n == 0)
10116 {
10117 /* Distribute the second term. */
10118 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
10119 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
10120 }
10121 else
10122 {
10123 /* Distribute the first term. */
10124 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
10125 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
10126 }
10127
10128 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
10129 new_op0, new_op1));
10130 if (GET_CODE (tmp) != outer_code
10131 && (set_src_cost (tmp, mode, optimize_this_for_speed_p)
10132 < set_src_cost (x, mode, optimize_this_for_speed_p)))
10133 return tmp;
10134
10135 return NULL_RTX;
10136 }
10137
10138 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10139 in MODE. Return an equivalent form, if different from (and VAROP
10140 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10141
10142 static rtx
simplify_and_const_int_1(scalar_int_mode mode,rtx varop,unsigned HOST_WIDE_INT constop)10143 simplify_and_const_int_1 (scalar_int_mode mode, rtx varop,
10144 unsigned HOST_WIDE_INT constop)
10145 {
10146 unsigned HOST_WIDE_INT nonzero;
10147 unsigned HOST_WIDE_INT orig_constop;
10148 rtx orig_varop;
10149 int i;
10150
10151 orig_varop = varop;
10152 orig_constop = constop;
10153 if (GET_CODE (varop) == CLOBBER)
10154 return NULL_RTX;
10155
10156 /* Simplify VAROP knowing that we will be only looking at some of the
10157 bits in it.
10158
10159 Note by passing in CONSTOP, we guarantee that the bits not set in
10160 CONSTOP are not significant and will never be examined. We must
10161 ensure that is the case by explicitly masking out those bits
10162 before returning. */
10163 varop = force_to_mode (varop, mode, constop, 0);
10164
10165 /* If VAROP is a CLOBBER, we will fail so return it. */
10166 if (GET_CODE (varop) == CLOBBER)
10167 return varop;
10168
10169 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10170 to VAROP and return the new constant. */
10171 if (CONST_INT_P (varop))
10172 return gen_int_mode (INTVAL (varop) & constop, mode);
10173
10174 /* See what bits may be nonzero in VAROP. Unlike the general case of
10175 a call to nonzero_bits, here we don't care about bits outside
10176 MODE. */
10177
10178 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
10179
10180 /* Turn off all bits in the constant that are known to already be zero.
10181 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10182 which is tested below. */
10183
10184 constop &= nonzero;
10185
10186 /* If we don't have any bits left, return zero. */
10187 if (constop == 0 && !side_effects_p (varop))
10188 return const0_rtx;
10189
10190 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10191 a power of two, we can replace this with an ASHIFT. */
10192 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
10193 && (i = exact_log2 (constop)) >= 0)
10194 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
10195
10196 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10197 or XOR, then try to apply the distributive law. This may eliminate
10198 operations if either branch can be simplified because of the AND.
10199 It may also make some cases more complex, but those cases probably
10200 won't match a pattern either with or without this. */
10201
10202 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
10203 {
10204 scalar_int_mode varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10205 return
10206 gen_lowpart
10207 (mode,
10208 apply_distributive_law
10209 (simplify_gen_binary (GET_CODE (varop), varop_mode,
10210 simplify_and_const_int (NULL_RTX, varop_mode,
10211 XEXP (varop, 0),
10212 constop),
10213 simplify_and_const_int (NULL_RTX, varop_mode,
10214 XEXP (varop, 1),
10215 constop))));
10216 }
10217
10218 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10219 the AND and see if one of the operands simplifies to zero. If so, we
10220 may eliminate it. */
10221
10222 if (GET_CODE (varop) == PLUS
10223 && pow2p_hwi (constop + 1))
10224 {
10225 rtx o0, o1;
10226
10227 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
10228 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
10229 if (o0 == const0_rtx)
10230 return o1;
10231 if (o1 == const0_rtx)
10232 return o0;
10233 }
10234
10235 /* Make a SUBREG if necessary. If we can't make it, fail. */
10236 varop = gen_lowpart (mode, varop);
10237 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10238 return NULL_RTX;
10239
10240 /* If we are only masking insignificant bits, return VAROP. */
10241 if (constop == nonzero)
10242 return varop;
10243
10244 if (varop == orig_varop && constop == orig_constop)
10245 return NULL_RTX;
10246
10247 /* Otherwise, return an AND. */
10248 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
10249 }
10250
10251
10252 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10253 in MODE.
10254
10255 Return an equivalent form, if different from X. Otherwise, return X. If
10256 X is zero, we are to always construct the equivalent form. */
10257
10258 static rtx
simplify_and_const_int(rtx x,scalar_int_mode mode,rtx varop,unsigned HOST_WIDE_INT constop)10259 simplify_and_const_int (rtx x, scalar_int_mode mode, rtx varop,
10260 unsigned HOST_WIDE_INT constop)
10261 {
10262 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
10263 if (tem)
10264 return tem;
10265
10266 if (!x)
10267 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
10268 gen_int_mode (constop, mode));
10269 if (GET_MODE (x) != mode)
10270 x = gen_lowpart (mode, x);
10271 return x;
10272 }
10273
10274 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10275 We don't care about bits outside of those defined in MODE.
10276 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10277
10278 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10279 a shift, AND, or zero_extract, we can do better. */
10280
10281 static rtx
reg_nonzero_bits_for_combine(const_rtx x,scalar_int_mode xmode,scalar_int_mode mode,unsigned HOST_WIDE_INT * nonzero)10282 reg_nonzero_bits_for_combine (const_rtx x, scalar_int_mode xmode,
10283 scalar_int_mode mode,
10284 unsigned HOST_WIDE_INT *nonzero)
10285 {
10286 rtx tem;
10287 reg_stat_type *rsp;
10288
10289 /* If X is a register whose nonzero bits value is current, use it.
10290 Otherwise, if X is a register whose value we can find, use that
10291 value. Otherwise, use the previously-computed global nonzero bits
10292 for this register. */
10293
10294 rsp = ®_stat[REGNO (x)];
10295 if (rsp->last_set_value != 0
10296 && (rsp->last_set_mode == mode
10297 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10298 && GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
10299 && GET_MODE_CLASS (mode) == MODE_INT))
10300 && ((rsp->last_set_label >= label_tick_ebb_start
10301 && rsp->last_set_label < label_tick)
10302 || (rsp->last_set_label == label_tick
10303 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10304 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10305 && REGNO (x) < reg_n_sets_max
10306 && REG_N_SETS (REGNO (x)) == 1
10307 && !REGNO_REG_SET_P
10308 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10309 REGNO (x)))))
10310 {
10311 /* Note that, even if the precision of last_set_mode is lower than that
10312 of mode, record_value_for_reg invoked nonzero_bits on the register
10313 with nonzero_bits_mode (because last_set_mode is necessarily integral
10314 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10315 are all valid, hence in mode too since nonzero_bits_mode is defined
10316 to the largest HWI_COMPUTABLE_MODE_P mode. */
10317 *nonzero &= rsp->last_set_nonzero_bits;
10318 return NULL;
10319 }
10320
10321 tem = get_last_value (x);
10322 if (tem)
10323 {
10324 if (SHORT_IMMEDIATES_SIGN_EXTEND)
10325 tem = sign_extend_short_imm (tem, xmode, GET_MODE_PRECISION (mode));
10326
10327 return tem;
10328 }
10329
10330 if (nonzero_sign_valid && rsp->nonzero_bits)
10331 {
10332 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
10333
10334 if (GET_MODE_PRECISION (xmode) < GET_MODE_PRECISION (mode))
10335 /* We don't know anything about the upper bits. */
10336 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (xmode);
10337
10338 *nonzero &= mask;
10339 }
10340
10341 return NULL;
10342 }
10343
10344 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10345 end of X that are known to be equal to the sign bit. X will be used
10346 in mode MODE; the returned value will always be between 1 and the
10347 number of bits in MODE. */
10348
10349 static rtx
reg_num_sign_bit_copies_for_combine(const_rtx x,scalar_int_mode xmode,scalar_int_mode mode,unsigned int * result)10350 reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
10351 scalar_int_mode mode,
10352 unsigned int *result)
10353 {
10354 rtx tem;
10355 reg_stat_type *rsp;
10356
10357 rsp = ®_stat[REGNO (x)];
10358 if (rsp->last_set_value != 0
10359 && rsp->last_set_mode == mode
10360 && ((rsp->last_set_label >= label_tick_ebb_start
10361 && rsp->last_set_label < label_tick)
10362 || (rsp->last_set_label == label_tick
10363 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10364 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10365 && REGNO (x) < reg_n_sets_max
10366 && REG_N_SETS (REGNO (x)) == 1
10367 && !REGNO_REG_SET_P
10368 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10369 REGNO (x)))))
10370 {
10371 *result = rsp->last_set_sign_bit_copies;
10372 return NULL;
10373 }
10374
10375 tem = get_last_value (x);
10376 if (tem != 0)
10377 return tem;
10378
10379 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
10380 && GET_MODE_PRECISION (xmode) == GET_MODE_PRECISION (mode))
10381 *result = rsp->sign_bit_copies;
10382
10383 return NULL;
10384 }
10385
10386 /* Return the number of "extended" bits there are in X, when interpreted
10387 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10388 unsigned quantities, this is the number of high-order zero bits.
10389 For signed quantities, this is the number of copies of the sign bit
10390 minus 1. In both case, this function returns the number of "spare"
10391 bits. For example, if two quantities for which this function returns
10392 at least 1 are added, the addition is known not to overflow.
10393
10394 This function will always return 0 unless called during combine, which
10395 implies that it must be called from a define_split. */
10396
10397 unsigned int
extended_count(const_rtx x,machine_mode mode,int unsignedp)10398 extended_count (const_rtx x, machine_mode mode, int unsignedp)
10399 {
10400 if (nonzero_sign_valid == 0)
10401 return 0;
10402
10403 scalar_int_mode int_mode;
10404 return (unsignedp
10405 ? (is_a <scalar_int_mode> (mode, &int_mode)
10406 && HWI_COMPUTABLE_MODE_P (int_mode)
10407 ? (unsigned int) (GET_MODE_PRECISION (int_mode) - 1
10408 - floor_log2 (nonzero_bits (x, int_mode)))
10409 : 0)
10410 : num_sign_bit_copies (x, mode) - 1);
10411 }
10412
10413 /* This function is called from `simplify_shift_const' to merge two
10414 outer operations. Specifically, we have already found that we need
10415 to perform operation *POP0 with constant *PCONST0 at the outermost
10416 position. We would now like to also perform OP1 with constant CONST1
10417 (with *POP0 being done last).
10418
10419 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10420 the resulting operation. *PCOMP_P is set to 1 if we would need to
10421 complement the innermost operand, otherwise it is unchanged.
10422
10423 MODE is the mode in which the operation will be done. No bits outside
10424 the width of this mode matter. It is assumed that the width of this mode
10425 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10426
10427 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10428 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10429 result is simply *PCONST0.
10430
10431 If the resulting operation cannot be expressed as one operation, we
10432 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10433
10434 static int
merge_outer_ops(enum rtx_code * pop0,HOST_WIDE_INT * pconst0,enum rtx_code op1,HOST_WIDE_INT const1,machine_mode mode,int * pcomp_p)10435 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10436 {
10437 enum rtx_code op0 = *pop0;
10438 HOST_WIDE_INT const0 = *pconst0;
10439
10440 const0 &= GET_MODE_MASK (mode);
10441 const1 &= GET_MODE_MASK (mode);
10442
10443 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10444 if (op0 == AND)
10445 const1 &= const0;
10446
10447 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10448 if OP0 is SET. */
10449
10450 if (op1 == UNKNOWN || op0 == SET)
10451 return 1;
10452
10453 else if (op0 == UNKNOWN)
10454 op0 = op1, const0 = const1;
10455
10456 else if (op0 == op1)
10457 {
10458 switch (op0)
10459 {
10460 case AND:
10461 const0 &= const1;
10462 break;
10463 case IOR:
10464 const0 |= const1;
10465 break;
10466 case XOR:
10467 const0 ^= const1;
10468 break;
10469 case PLUS:
10470 const0 += const1;
10471 break;
10472 case NEG:
10473 op0 = UNKNOWN;
10474 break;
10475 default:
10476 break;
10477 }
10478 }
10479
10480 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10481 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
10482 return 0;
10483
10484 /* If the two constants aren't the same, we can't do anything. The
10485 remaining six cases can all be done. */
10486 else if (const0 != const1)
10487 return 0;
10488
10489 else
10490 switch (op0)
10491 {
10492 case IOR:
10493 if (op1 == AND)
10494 /* (a & b) | b == b */
10495 op0 = SET;
10496 else /* op1 == XOR */
10497 /* (a ^ b) | b == a | b */
10498 {;}
10499 break;
10500
10501 case XOR:
10502 if (op1 == AND)
10503 /* (a & b) ^ b == (~a) & b */
10504 op0 = AND, *pcomp_p = 1;
10505 else /* op1 == IOR */
10506 /* (a | b) ^ b == a & ~b */
10507 op0 = AND, const0 = ~const0;
10508 break;
10509
10510 case AND:
10511 if (op1 == IOR)
10512 /* (a | b) & b == b */
10513 op0 = SET;
10514 else /* op1 == XOR */
10515 /* (a ^ b) & b) == (~a) & b */
10516 *pcomp_p = 1;
10517 break;
10518 default:
10519 break;
10520 }
10521
10522 /* Check for NO-OP cases. */
10523 const0 &= GET_MODE_MASK (mode);
10524 if (const0 == 0
10525 && (op0 == IOR || op0 == XOR || op0 == PLUS))
10526 op0 = UNKNOWN;
10527 else if (const0 == 0 && op0 == AND)
10528 op0 = SET;
10529 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
10530 && op0 == AND)
10531 op0 = UNKNOWN;
10532
10533 *pop0 = op0;
10534
10535 /* ??? Slightly redundant with the above mask, but not entirely.
10536 Moving this above means we'd have to sign-extend the mode mask
10537 for the final test. */
10538 if (op0 != UNKNOWN && op0 != NEG)
10539 *pconst0 = trunc_int_for_mode (const0, mode);
10540
10541 return 1;
10542 }
10543
10544 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10545 the shift in. The original shift operation CODE is performed on OP in
10546 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10547 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10548 result of the shift is subject to operation OUTER_CODE with operand
10549 OUTER_CONST. */
10550
10551 static scalar_int_mode
try_widen_shift_mode(enum rtx_code code,rtx op,int count,scalar_int_mode orig_mode,scalar_int_mode mode,enum rtx_code outer_code,HOST_WIDE_INT outer_const)10552 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
10553 scalar_int_mode orig_mode, scalar_int_mode mode,
10554 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
10555 {
10556 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
10557
10558 /* In general we can't perform in wider mode for right shift and rotate. */
10559 switch (code)
10560 {
10561 case ASHIFTRT:
10562 /* We can still widen if the bits brought in from the left are identical
10563 to the sign bit of ORIG_MODE. */
10564 if (num_sign_bit_copies (op, mode)
10565 > (unsigned) (GET_MODE_PRECISION (mode)
10566 - GET_MODE_PRECISION (orig_mode)))
10567 return mode;
10568 return orig_mode;
10569
10570 case LSHIFTRT:
10571 /* Similarly here but with zero bits. */
10572 if (HWI_COMPUTABLE_MODE_P (mode)
10573 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
10574 return mode;
10575
10576 /* We can also widen if the bits brought in will be masked off. This
10577 operation is performed in ORIG_MODE. */
10578 if (outer_code == AND)
10579 {
10580 int care_bits = low_bitmask_len (orig_mode, outer_const);
10581
10582 if (care_bits >= 0
10583 && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
10584 return mode;
10585 }
10586 /* fall through */
10587
10588 case ROTATE:
10589 return orig_mode;
10590
10591 case ROTATERT:
10592 gcc_unreachable ();
10593
10594 default:
10595 return mode;
10596 }
10597 }
10598
10599 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10600 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10601 if we cannot simplify it. Otherwise, return a simplified value.
10602
10603 The shift is normally computed in the widest mode we find in VAROP, as
10604 long as it isn't a different number of words than RESULT_MODE. Exceptions
10605 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10606
10607 static rtx
simplify_shift_const_1(enum rtx_code code,machine_mode result_mode,rtx varop,int orig_count)10608 simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
10609 rtx varop, int orig_count)
10610 {
10611 enum rtx_code orig_code = code;
10612 rtx orig_varop = varop;
10613 int count, log2;
10614 machine_mode mode = result_mode;
10615 machine_mode shift_mode;
10616 scalar_int_mode tmode, inner_mode, int_mode, int_varop_mode, int_result_mode;
10617 /* We form (outer_op (code varop count) (outer_const)). */
10618 enum rtx_code outer_op = UNKNOWN;
10619 HOST_WIDE_INT outer_const = 0;
10620 int complement_p = 0;
10621 rtx new_rtx, x;
10622
10623 /* Make sure and truncate the "natural" shift on the way in. We don't
10624 want to do this inside the loop as it makes it more difficult to
10625 combine shifts. */
10626 if (SHIFT_COUNT_TRUNCATED)
10627 orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1;
10628
10629 /* If we were given an invalid count, don't do anything except exactly
10630 what was requested. */
10631
10632 if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode))
10633 return NULL_RTX;
10634
10635 count = orig_count;
10636
10637 /* Unless one of the branches of the `if' in this loop does a `continue',
10638 we will `break' the loop after the `if'. */
10639
10640 while (count != 0)
10641 {
10642 /* If we have an operand of (clobber (const_int 0)), fail. */
10643 if (GET_CODE (varop) == CLOBBER)
10644 return NULL_RTX;
10645
10646 /* Convert ROTATERT to ROTATE. */
10647 if (code == ROTATERT)
10648 {
10649 unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode);
10650 code = ROTATE;
10651 count = bitsize - count;
10652 }
10653
10654 shift_mode = result_mode;
10655 if (shift_mode != mode)
10656 {
10657 /* We only change the modes of scalar shifts. */
10658 int_mode = as_a <scalar_int_mode> (mode);
10659 int_result_mode = as_a <scalar_int_mode> (result_mode);
10660 shift_mode = try_widen_shift_mode (code, varop, count,
10661 int_result_mode, int_mode,
10662 outer_op, outer_const);
10663 }
10664
10665 scalar_int_mode shift_unit_mode
10666 = as_a <scalar_int_mode> (GET_MODE_INNER (shift_mode));
10667
10668 /* Handle cases where the count is greater than the size of the mode
10669 minus 1. For ASHIFT, use the size minus one as the count (this can
10670 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10671 take the count modulo the size. For other shifts, the result is
10672 zero.
10673
10674 Since these shifts are being produced by the compiler by combining
10675 multiple operations, each of which are defined, we know what the
10676 result is supposed to be. */
10677
10678 if (count > (GET_MODE_PRECISION (shift_unit_mode) - 1))
10679 {
10680 if (code == ASHIFTRT)
10681 count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10682 else if (code == ROTATE || code == ROTATERT)
10683 count %= GET_MODE_PRECISION (shift_unit_mode);
10684 else
10685 {
10686 /* We can't simply return zero because there may be an
10687 outer op. */
10688 varop = const0_rtx;
10689 count = 0;
10690 break;
10691 }
10692 }
10693
10694 /* If we discovered we had to complement VAROP, leave. Making a NOT
10695 here would cause an infinite loop. */
10696 if (complement_p)
10697 break;
10698
10699 if (shift_mode == shift_unit_mode)
10700 {
10701 /* An arithmetic right shift of a quantity known to be -1 or 0
10702 is a no-op. */
10703 if (code == ASHIFTRT
10704 && (num_sign_bit_copies (varop, shift_unit_mode)
10705 == GET_MODE_PRECISION (shift_unit_mode)))
10706 {
10707 count = 0;
10708 break;
10709 }
10710
10711 /* If we are doing an arithmetic right shift and discarding all but
10712 the sign bit copies, this is equivalent to doing a shift by the
10713 bitsize minus one. Convert it into that shift because it will
10714 often allow other simplifications. */
10715
10716 if (code == ASHIFTRT
10717 && (count + num_sign_bit_copies (varop, shift_unit_mode)
10718 >= GET_MODE_PRECISION (shift_unit_mode)))
10719 count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10720
10721 /* We simplify the tests below and elsewhere by converting
10722 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10723 `make_compound_operation' will convert it to an ASHIFTRT for
10724 those machines (such as VAX) that don't have an LSHIFTRT. */
10725 if (code == ASHIFTRT
10726 && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10727 && val_signbit_known_clear_p (shift_unit_mode,
10728 nonzero_bits (varop,
10729 shift_unit_mode)))
10730 code = LSHIFTRT;
10731
10732 if (((code == LSHIFTRT
10733 && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10734 && !(nonzero_bits (varop, shift_unit_mode) >> count))
10735 || (code == ASHIFT
10736 && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10737 && !((nonzero_bits (varop, shift_unit_mode) << count)
10738 & GET_MODE_MASK (shift_unit_mode))))
10739 && !side_effects_p (varop))
10740 varop = const0_rtx;
10741 }
10742
10743 switch (GET_CODE (varop))
10744 {
10745 case SIGN_EXTEND:
10746 case ZERO_EXTEND:
10747 case SIGN_EXTRACT:
10748 case ZERO_EXTRACT:
10749 new_rtx = expand_compound_operation (varop);
10750 if (new_rtx != varop)
10751 {
10752 varop = new_rtx;
10753 continue;
10754 }
10755 break;
10756
10757 case MEM:
10758 /* The following rules apply only to scalars. */
10759 if (shift_mode != shift_unit_mode)
10760 break;
10761 int_mode = as_a <scalar_int_mode> (mode);
10762
10763 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10764 minus the width of a smaller mode, we can do this with a
10765 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10766 if ((code == ASHIFTRT || code == LSHIFTRT)
10767 && ! mode_dependent_address_p (XEXP (varop, 0),
10768 MEM_ADDR_SPACE (varop))
10769 && ! MEM_VOLATILE_P (varop)
10770 && (int_mode_for_size (GET_MODE_BITSIZE (int_mode) - count, 1)
10771 .exists (&tmode)))
10772 {
10773 new_rtx = adjust_address_nv (varop, tmode,
10774 BYTES_BIG_ENDIAN ? 0
10775 : count / BITS_PER_UNIT);
10776
10777 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10778 : ZERO_EXTEND, int_mode, new_rtx);
10779 count = 0;
10780 continue;
10781 }
10782 break;
10783
10784 case SUBREG:
10785 /* The following rules apply only to scalars. */
10786 if (shift_mode != shift_unit_mode)
10787 break;
10788 int_mode = as_a <scalar_int_mode> (mode);
10789 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10790
10791 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10792 the same number of words as what we've seen so far. Then store
10793 the widest mode in MODE. */
10794 if (subreg_lowpart_p (varop)
10795 && is_int_mode (GET_MODE (SUBREG_REG (varop)), &inner_mode)
10796 && GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_varop_mode)
10797 && (CEIL (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD)
10798 == CEIL (GET_MODE_SIZE (int_mode), UNITS_PER_WORD))
10799 && GET_MODE_CLASS (int_varop_mode) == MODE_INT)
10800 {
10801 varop = SUBREG_REG (varop);
10802 if (GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_mode))
10803 mode = inner_mode;
10804 continue;
10805 }
10806 break;
10807
10808 case MULT:
10809 /* Some machines use MULT instead of ASHIFT because MULT
10810 is cheaper. But it is still better on those machines to
10811 merge two shifts into one. */
10812 if (CONST_INT_P (XEXP (varop, 1))
10813 && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10814 {
10815 rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10816 varop = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10817 XEXP (varop, 0), log2_rtx);
10818 continue;
10819 }
10820 break;
10821
10822 case UDIV:
10823 /* Similar, for when divides are cheaper. */
10824 if (CONST_INT_P (XEXP (varop, 1))
10825 && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10826 {
10827 rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10828 varop = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10829 XEXP (varop, 0), log2_rtx);
10830 continue;
10831 }
10832 break;
10833
10834 case ASHIFTRT:
10835 /* If we are extracting just the sign bit of an arithmetic
10836 right shift, that shift is not needed. However, the sign
10837 bit of a wider mode may be different from what would be
10838 interpreted as the sign bit in a narrower mode, so, if
10839 the result is narrower, don't discard the shift. */
10840 if (code == LSHIFTRT
10841 && count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1)
10842 && (GET_MODE_UNIT_BITSIZE (result_mode)
10843 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop))))
10844 {
10845 varop = XEXP (varop, 0);
10846 continue;
10847 }
10848
10849 /* fall through */
10850
10851 case LSHIFTRT:
10852 case ASHIFT:
10853 case ROTATE:
10854 /* The following rules apply only to scalars. */
10855 if (shift_mode != shift_unit_mode)
10856 break;
10857 int_mode = as_a <scalar_int_mode> (mode);
10858 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10859 int_result_mode = as_a <scalar_int_mode> (result_mode);
10860
10861 /* Here we have two nested shifts. The result is usually the
10862 AND of a new shift with a mask. We compute the result below. */
10863 if (CONST_INT_P (XEXP (varop, 1))
10864 && INTVAL (XEXP (varop, 1)) >= 0
10865 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (int_varop_mode)
10866 && HWI_COMPUTABLE_MODE_P (int_result_mode)
10867 && HWI_COMPUTABLE_MODE_P (int_mode))
10868 {
10869 enum rtx_code first_code = GET_CODE (varop);
10870 unsigned int first_count = INTVAL (XEXP (varop, 1));
10871 unsigned HOST_WIDE_INT mask;
10872 rtx mask_rtx;
10873
10874 /* We have one common special case. We can't do any merging if
10875 the inner code is an ASHIFTRT of a smaller mode. However, if
10876 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10877 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10878 we can convert it to
10879 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10880 This simplifies certain SIGN_EXTEND operations. */
10881 if (code == ASHIFT && first_code == ASHIFTRT
10882 && count == (GET_MODE_PRECISION (int_result_mode)
10883 - GET_MODE_PRECISION (int_varop_mode)))
10884 {
10885 /* C3 has the low-order C1 bits zero. */
10886
10887 mask = GET_MODE_MASK (int_mode)
10888 & ~((HOST_WIDE_INT_1U << first_count) - 1);
10889
10890 varop = simplify_and_const_int (NULL_RTX, int_result_mode,
10891 XEXP (varop, 0), mask);
10892 varop = simplify_shift_const (NULL_RTX, ASHIFT,
10893 int_result_mode, varop, count);
10894 count = first_count;
10895 code = ASHIFTRT;
10896 continue;
10897 }
10898
10899 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10900 than C1 high-order bits equal to the sign bit, we can convert
10901 this to either an ASHIFT or an ASHIFTRT depending on the
10902 two counts.
10903
10904 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10905
10906 if (code == ASHIFTRT && first_code == ASHIFT
10907 && int_varop_mode == shift_unit_mode
10908 && (num_sign_bit_copies (XEXP (varop, 0), shift_unit_mode)
10909 > first_count))
10910 {
10911 varop = XEXP (varop, 0);
10912 count -= first_count;
10913 if (count < 0)
10914 {
10915 count = -count;
10916 code = ASHIFT;
10917 }
10918
10919 continue;
10920 }
10921
10922 /* There are some cases we can't do. If CODE is ASHIFTRT,
10923 we can only do this if FIRST_CODE is also ASHIFTRT.
10924
10925 We can't do the case when CODE is ROTATE and FIRST_CODE is
10926 ASHIFTRT.
10927
10928 If the mode of this shift is not the mode of the outer shift,
10929 we can't do this if either shift is a right shift or ROTATE.
10930
10931 Finally, we can't do any of these if the mode is too wide
10932 unless the codes are the same.
10933
10934 Handle the case where the shift codes are the same
10935 first. */
10936
10937 if (code == first_code)
10938 {
10939 if (int_varop_mode != int_result_mode
10940 && (code == ASHIFTRT || code == LSHIFTRT
10941 || code == ROTATE))
10942 break;
10943
10944 count += first_count;
10945 varop = XEXP (varop, 0);
10946 continue;
10947 }
10948
10949 if (code == ASHIFTRT
10950 || (code == ROTATE && first_code == ASHIFTRT)
10951 || GET_MODE_PRECISION (int_mode) > HOST_BITS_PER_WIDE_INT
10952 || (int_varop_mode != int_result_mode
10953 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10954 || first_code == ROTATE
10955 || code == ROTATE)))
10956 break;
10957
10958 /* To compute the mask to apply after the shift, shift the
10959 nonzero bits of the inner shift the same way the
10960 outer shift will. */
10961
10962 mask_rtx = gen_int_mode (nonzero_bits (varop, int_varop_mode),
10963 int_result_mode);
10964 rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10965 mask_rtx
10966 = simplify_const_binary_operation (code, int_result_mode,
10967 mask_rtx, count_rtx);
10968
10969 /* Give up if we can't compute an outer operation to use. */
10970 if (mask_rtx == 0
10971 || !CONST_INT_P (mask_rtx)
10972 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10973 INTVAL (mask_rtx),
10974 int_result_mode, &complement_p))
10975 break;
10976
10977 /* If the shifts are in the same direction, we add the
10978 counts. Otherwise, we subtract them. */
10979 if ((code == ASHIFTRT || code == LSHIFTRT)
10980 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10981 count += first_count;
10982 else
10983 count -= first_count;
10984
10985 /* If COUNT is positive, the new shift is usually CODE,
10986 except for the two exceptions below, in which case it is
10987 FIRST_CODE. If the count is negative, FIRST_CODE should
10988 always be used */
10989 if (count > 0
10990 && ((first_code == ROTATE && code == ASHIFT)
10991 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10992 code = first_code;
10993 else if (count < 0)
10994 code = first_code, count = -count;
10995
10996 varop = XEXP (varop, 0);
10997 continue;
10998 }
10999
11000 /* If we have (A << B << C) for any shift, we can convert this to
11001 (A << C << B). This wins if A is a constant. Only try this if
11002 B is not a constant. */
11003
11004 else if (GET_CODE (varop) == code
11005 && CONST_INT_P (XEXP (varop, 0))
11006 && !CONST_INT_P (XEXP (varop, 1)))
11007 {
11008 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
11009 sure the result will be masked. See PR70222. */
11010 if (code == LSHIFTRT
11011 && int_mode != int_result_mode
11012 && !merge_outer_ops (&outer_op, &outer_const, AND,
11013 GET_MODE_MASK (int_result_mode)
11014 >> orig_count, int_result_mode,
11015 &complement_p))
11016 break;
11017 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
11018 up outer sign extension (often left and right shift) is
11019 hardly more efficient than the original. See PR70429.
11020 Similarly punt for rotates with different modes.
11021 See PR97386. */
11022 if ((code == ASHIFTRT || code == ROTATE)
11023 && int_mode != int_result_mode)
11024 break;
11025
11026 rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
11027 rtx new_rtx = simplify_const_binary_operation (code, int_mode,
11028 XEXP (varop, 0),
11029 count_rtx);
11030 varop = gen_rtx_fmt_ee (code, int_mode, new_rtx, XEXP (varop, 1));
11031 count = 0;
11032 continue;
11033 }
11034 break;
11035
11036 case NOT:
11037 /* The following rules apply only to scalars. */
11038 if (shift_mode != shift_unit_mode)
11039 break;
11040
11041 /* Make this fit the case below. */
11042 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
11043 continue;
11044
11045 case IOR:
11046 case AND:
11047 case XOR:
11048 /* The following rules apply only to scalars. */
11049 if (shift_mode != shift_unit_mode)
11050 break;
11051 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11052 int_result_mode = as_a <scalar_int_mode> (result_mode);
11053
11054 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11055 with C the size of VAROP - 1 and the shift is logical if
11056 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11057 we have an (le X 0) operation. If we have an arithmetic shift
11058 and STORE_FLAG_VALUE is 1 or we have a logical shift with
11059 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11060
11061 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
11062 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
11063 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11064 && (code == LSHIFTRT || code == ASHIFTRT)
11065 && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11066 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11067 {
11068 count = 0;
11069 varop = gen_rtx_LE (int_varop_mode, XEXP (varop, 1),
11070 const0_rtx);
11071
11072 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11073 varop = gen_rtx_NEG (int_varop_mode, varop);
11074
11075 continue;
11076 }
11077
11078 /* If we have (shift (logical)), move the logical to the outside
11079 to allow it to possibly combine with another logical and the
11080 shift to combine with another shift. This also canonicalizes to
11081 what a ZERO_EXTRACT looks like. Also, some machines have
11082 (and (shift)) insns. */
11083
11084 if (CONST_INT_P (XEXP (varop, 1))
11085 /* We can't do this if we have (ashiftrt (xor)) and the
11086 constant has its sign bit set in shift_unit_mode with
11087 shift_unit_mode wider than result_mode. */
11088 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11089 && int_result_mode != shift_unit_mode
11090 && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11091 shift_unit_mode) < 0)
11092 && (new_rtx = simplify_const_binary_operation
11093 (code, int_result_mode,
11094 gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11095 gen_int_shift_amount (int_result_mode, count))) != 0
11096 && CONST_INT_P (new_rtx)
11097 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
11098 INTVAL (new_rtx), int_result_mode,
11099 &complement_p))
11100 {
11101 varop = XEXP (varop, 0);
11102 continue;
11103 }
11104
11105 /* If we can't do that, try to simplify the shift in each arm of the
11106 logical expression, make a new logical expression, and apply
11107 the inverse distributive law. This also can't be done for
11108 (ashiftrt (xor)) where we've widened the shift and the constant
11109 changes the sign bit. */
11110 if (CONST_INT_P (XEXP (varop, 1))
11111 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11112 && int_result_mode != shift_unit_mode
11113 && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11114 shift_unit_mode) < 0))
11115 {
11116 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11117 XEXP (varop, 0), count);
11118 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11119 XEXP (varop, 1), count);
11120
11121 varop = simplify_gen_binary (GET_CODE (varop), shift_unit_mode,
11122 lhs, rhs);
11123 varop = apply_distributive_law (varop);
11124
11125 count = 0;
11126 continue;
11127 }
11128 break;
11129
11130 case EQ:
11131 /* The following rules apply only to scalars. */
11132 if (shift_mode != shift_unit_mode)
11133 break;
11134 int_result_mode = as_a <scalar_int_mode> (result_mode);
11135
11136 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11137 says that the sign bit can be tested, FOO has mode MODE, C is
11138 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11139 that may be nonzero. */
11140 if (code == LSHIFTRT
11141 && XEXP (varop, 1) == const0_rtx
11142 && GET_MODE (XEXP (varop, 0)) == int_result_mode
11143 && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11144 && HWI_COMPUTABLE_MODE_P (int_result_mode)
11145 && STORE_FLAG_VALUE == -1
11146 && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11147 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11148 int_result_mode, &complement_p))
11149 {
11150 varop = XEXP (varop, 0);
11151 count = 0;
11152 continue;
11153 }
11154 break;
11155
11156 case NEG:
11157 /* The following rules apply only to scalars. */
11158 if (shift_mode != shift_unit_mode)
11159 break;
11160 int_result_mode = as_a <scalar_int_mode> (result_mode);
11161
11162 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11163 than the number of bits in the mode is equivalent to A. */
11164 if (code == LSHIFTRT
11165 && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11166 && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1)
11167 {
11168 varop = XEXP (varop, 0);
11169 count = 0;
11170 continue;
11171 }
11172
11173 /* NEG commutes with ASHIFT since it is multiplication. Move the
11174 NEG outside to allow shifts to combine. */
11175 if (code == ASHIFT
11176 && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
11177 int_result_mode, &complement_p))
11178 {
11179 varop = XEXP (varop, 0);
11180 continue;
11181 }
11182 break;
11183
11184 case PLUS:
11185 /* The following rules apply only to scalars. */
11186 if (shift_mode != shift_unit_mode)
11187 break;
11188 int_result_mode = as_a <scalar_int_mode> (result_mode);
11189
11190 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11191 is one less than the number of bits in the mode is
11192 equivalent to (xor A 1). */
11193 if (code == LSHIFTRT
11194 && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11195 && XEXP (varop, 1) == constm1_rtx
11196 && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11197 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11198 int_result_mode, &complement_p))
11199 {
11200 count = 0;
11201 varop = XEXP (varop, 0);
11202 continue;
11203 }
11204
11205 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11206 that might be nonzero in BAR are those being shifted out and those
11207 bits are known zero in FOO, we can replace the PLUS with FOO.
11208 Similarly in the other operand order. This code occurs when
11209 we are computing the size of a variable-size array. */
11210
11211 if ((code == ASHIFTRT || code == LSHIFTRT)
11212 && count < HOST_BITS_PER_WIDE_INT
11213 && nonzero_bits (XEXP (varop, 1), int_result_mode) >> count == 0
11214 && (nonzero_bits (XEXP (varop, 1), int_result_mode)
11215 & nonzero_bits (XEXP (varop, 0), int_result_mode)) == 0)
11216 {
11217 varop = XEXP (varop, 0);
11218 continue;
11219 }
11220 else if ((code == ASHIFTRT || code == LSHIFTRT)
11221 && count < HOST_BITS_PER_WIDE_INT
11222 && HWI_COMPUTABLE_MODE_P (int_result_mode)
11223 && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11224 >> count) == 0
11225 && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11226 & nonzero_bits (XEXP (varop, 1), int_result_mode)) == 0)
11227 {
11228 varop = XEXP (varop, 1);
11229 continue;
11230 }
11231
11232 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11233 if (code == ASHIFT
11234 && CONST_INT_P (XEXP (varop, 1))
11235 && (new_rtx = simplify_const_binary_operation
11236 (ASHIFT, int_result_mode,
11237 gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11238 gen_int_shift_amount (int_result_mode, count))) != 0
11239 && CONST_INT_P (new_rtx)
11240 && merge_outer_ops (&outer_op, &outer_const, PLUS,
11241 INTVAL (new_rtx), int_result_mode,
11242 &complement_p))
11243 {
11244 varop = XEXP (varop, 0);
11245 continue;
11246 }
11247
11248 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11249 signbit', and attempt to change the PLUS to an XOR and move it to
11250 the outer operation as is done above in the AND/IOR/XOR case
11251 leg for shift(logical). See details in logical handling above
11252 for reasoning in doing so. */
11253 if (code == LSHIFTRT
11254 && CONST_INT_P (XEXP (varop, 1))
11255 && mode_signbit_p (int_result_mode, XEXP (varop, 1))
11256 && (new_rtx = simplify_const_binary_operation
11257 (code, int_result_mode,
11258 gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11259 gen_int_shift_amount (int_result_mode, count))) != 0
11260 && CONST_INT_P (new_rtx)
11261 && merge_outer_ops (&outer_op, &outer_const, XOR,
11262 INTVAL (new_rtx), int_result_mode,
11263 &complement_p))
11264 {
11265 varop = XEXP (varop, 0);
11266 continue;
11267 }
11268
11269 break;
11270
11271 case MINUS:
11272 /* The following rules apply only to scalars. */
11273 if (shift_mode != shift_unit_mode)
11274 break;
11275 int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11276
11277 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11278 with C the size of VAROP - 1 and the shift is logical if
11279 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11280 we have a (gt X 0) operation. If the shift is arithmetic with
11281 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11282 we have a (neg (gt X 0)) operation. */
11283
11284 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11285 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
11286 && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11287 && (code == LSHIFTRT || code == ASHIFTRT)
11288 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11289 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
11290 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11291 {
11292 count = 0;
11293 varop = gen_rtx_GT (int_varop_mode, XEXP (varop, 1),
11294 const0_rtx);
11295
11296 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11297 varop = gen_rtx_NEG (int_varop_mode, varop);
11298
11299 continue;
11300 }
11301 break;
11302
11303 case TRUNCATE:
11304 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11305 if the truncate does not affect the value. */
11306 if (code == LSHIFTRT
11307 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
11308 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11309 && (INTVAL (XEXP (XEXP (varop, 0), 1))
11310 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0)))
11311 - GET_MODE_UNIT_PRECISION (GET_MODE (varop)))))
11312 {
11313 rtx varop_inner = XEXP (varop, 0);
11314 int new_count = count + INTVAL (XEXP (varop_inner, 1));
11315 rtx new_count_rtx = gen_int_shift_amount (GET_MODE (varop_inner),
11316 new_count);
11317 varop_inner = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
11318 XEXP (varop_inner, 0),
11319 new_count_rtx);
11320 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
11321 count = 0;
11322 continue;
11323 }
11324 break;
11325
11326 default:
11327 break;
11328 }
11329
11330 break;
11331 }
11332
11333 shift_mode = result_mode;
11334 if (shift_mode != mode)
11335 {
11336 /* We only change the modes of scalar shifts. */
11337 int_mode = as_a <scalar_int_mode> (mode);
11338 int_result_mode = as_a <scalar_int_mode> (result_mode);
11339 shift_mode = try_widen_shift_mode (code, varop, count, int_result_mode,
11340 int_mode, outer_op, outer_const);
11341 }
11342
11343 /* We have now finished analyzing the shift. The result should be
11344 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11345 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11346 to the result of the shift. OUTER_CONST is the relevant constant,
11347 but we must turn off all bits turned off in the shift. */
11348
11349 if (outer_op == UNKNOWN
11350 && orig_code == code && orig_count == count
11351 && varop == orig_varop
11352 && shift_mode == GET_MODE (varop))
11353 return NULL_RTX;
11354
11355 /* Make a SUBREG if necessary. If we can't make it, fail. */
11356 varop = gen_lowpart (shift_mode, varop);
11357 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
11358 return NULL_RTX;
11359
11360 /* If we have an outer operation and we just made a shift, it is
11361 possible that we could have simplified the shift were it not
11362 for the outer operation. So try to do the simplification
11363 recursively. */
11364
11365 if (outer_op != UNKNOWN)
11366 x = simplify_shift_const_1 (code, shift_mode, varop, count);
11367 else
11368 x = NULL_RTX;
11369
11370 if (x == NULL_RTX)
11371 x = simplify_gen_binary (code, shift_mode, varop,
11372 gen_int_shift_amount (shift_mode, count));
11373
11374 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11375 turn off all the bits that the shift would have turned off. */
11376 if (orig_code == LSHIFTRT && result_mode != shift_mode)
11377 /* We only change the modes of scalar shifts. */
11378 x = simplify_and_const_int (NULL_RTX, as_a <scalar_int_mode> (shift_mode),
11379 x, GET_MODE_MASK (result_mode) >> orig_count);
11380
11381 /* Do the remainder of the processing in RESULT_MODE. */
11382 x = gen_lowpart_or_truncate (result_mode, x);
11383
11384 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11385 operation. */
11386 if (complement_p)
11387 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
11388
11389 if (outer_op != UNKNOWN)
11390 {
11391 int_result_mode = as_a <scalar_int_mode> (result_mode);
11392
11393 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
11394 && GET_MODE_PRECISION (int_result_mode) < HOST_BITS_PER_WIDE_INT)
11395 outer_const = trunc_int_for_mode (outer_const, int_result_mode);
11396
11397 if (outer_op == AND)
11398 x = simplify_and_const_int (NULL_RTX, int_result_mode, x, outer_const);
11399 else if (outer_op == SET)
11400 {
11401 /* This means that we have determined that the result is
11402 equivalent to a constant. This should be rare. */
11403 if (!side_effects_p (x))
11404 x = GEN_INT (outer_const);
11405 }
11406 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
11407 x = simplify_gen_unary (outer_op, int_result_mode, x, int_result_mode);
11408 else
11409 x = simplify_gen_binary (outer_op, int_result_mode, x,
11410 GEN_INT (outer_const));
11411 }
11412
11413 return x;
11414 }
11415
11416 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11417 The result of the shift is RESULT_MODE. If we cannot simplify it,
11418 return X or, if it is NULL, synthesize the expression with
11419 simplify_gen_binary. Otherwise, return a simplified value.
11420
11421 The shift is normally computed in the widest mode we find in VAROP, as
11422 long as it isn't a different number of words than RESULT_MODE. Exceptions
11423 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11424
11425 static rtx
simplify_shift_const(rtx x,enum rtx_code code,machine_mode result_mode,rtx varop,int count)11426 simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
11427 rtx varop, int count)
11428 {
11429 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
11430 if (tem)
11431 return tem;
11432
11433 if (!x)
11434 x = simplify_gen_binary (code, GET_MODE (varop), varop,
11435 gen_int_shift_amount (GET_MODE (varop), count));
11436 if (GET_MODE (x) != result_mode)
11437 x = gen_lowpart (result_mode, x);
11438 return x;
11439 }
11440
11441
11442 /* A subroutine of recog_for_combine. See there for arguments and
11443 return value. */
11444
11445 static int
recog_for_combine_1(rtx * pnewpat,rtx_insn * insn,rtx * pnotes)11446 recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
11447 {
11448 rtx pat = *pnewpat;
11449 rtx pat_without_clobbers;
11450 int insn_code_number;
11451 int num_clobbers_to_add = 0;
11452 int i;
11453 rtx notes = NULL_RTX;
11454 rtx old_notes, old_pat;
11455 int old_icode;
11456
11457 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11458 we use to indicate that something didn't match. If we find such a
11459 thing, force rejection. */
11460 if (GET_CODE (pat) == PARALLEL)
11461 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
11462 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
11463 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
11464 return -1;
11465
11466 old_pat = PATTERN (insn);
11467 old_notes = REG_NOTES (insn);
11468 PATTERN (insn) = pat;
11469 REG_NOTES (insn) = NULL_RTX;
11470
11471 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11472 if (dump_file && (dump_flags & TDF_DETAILS))
11473 {
11474 if (insn_code_number < 0)
11475 fputs ("Failed to match this instruction:\n", dump_file);
11476 else
11477 fputs ("Successfully matched this instruction:\n", dump_file);
11478 print_rtl_single (dump_file, pat);
11479 }
11480
11481 /* If it isn't, there is the possibility that we previously had an insn
11482 that clobbered some register as a side effect, but the combined
11483 insn doesn't need to do that. So try once more without the clobbers
11484 unless this represents an ASM insn. */
11485
11486 if (insn_code_number < 0 && ! check_asm_operands (pat)
11487 && GET_CODE (pat) == PARALLEL)
11488 {
11489 int pos;
11490
11491 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
11492 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
11493 {
11494 if (i != pos)
11495 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
11496 pos++;
11497 }
11498
11499 SUBST_INT (XVECLEN (pat, 0), pos);
11500
11501 if (pos == 1)
11502 pat = XVECEXP (pat, 0, 0);
11503
11504 PATTERN (insn) = pat;
11505 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11506 if (dump_file && (dump_flags & TDF_DETAILS))
11507 {
11508 if (insn_code_number < 0)
11509 fputs ("Failed to match this instruction:\n", dump_file);
11510 else
11511 fputs ("Successfully matched this instruction:\n", dump_file);
11512 print_rtl_single (dump_file, pat);
11513 }
11514 }
11515
11516 pat_without_clobbers = pat;
11517
11518 PATTERN (insn) = old_pat;
11519 REG_NOTES (insn) = old_notes;
11520
11521 /* Recognize all noop sets, these will be killed by followup pass. */
11522 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
11523 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
11524
11525 /* If we had any clobbers to add, make a new pattern than contains
11526 them. Then check to make sure that all of them are dead. */
11527 if (num_clobbers_to_add)
11528 {
11529 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
11530 rtvec_alloc (GET_CODE (pat) == PARALLEL
11531 ? (XVECLEN (pat, 0)
11532 + num_clobbers_to_add)
11533 : num_clobbers_to_add + 1));
11534
11535 if (GET_CODE (pat) == PARALLEL)
11536 for (i = 0; i < XVECLEN (pat, 0); i++)
11537 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
11538 else
11539 XVECEXP (newpat, 0, 0) = pat;
11540
11541 add_clobbers (newpat, insn_code_number);
11542
11543 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
11544 i < XVECLEN (newpat, 0); i++)
11545 {
11546 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
11547 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
11548 return -1;
11549 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
11550 {
11551 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
11552 notes = alloc_reg_note (REG_UNUSED,
11553 XEXP (XVECEXP (newpat, 0, i), 0), notes);
11554 }
11555 }
11556 pat = newpat;
11557 }
11558
11559 if (insn_code_number >= 0
11560 && insn_code_number != NOOP_MOVE_INSN_CODE)
11561 {
11562 old_pat = PATTERN (insn);
11563 old_notes = REG_NOTES (insn);
11564 old_icode = INSN_CODE (insn);
11565 PATTERN (insn) = pat;
11566 REG_NOTES (insn) = notes;
11567 INSN_CODE (insn) = insn_code_number;
11568
11569 /* Allow targets to reject combined insn. */
11570 if (!targetm.legitimate_combined_insn (insn))
11571 {
11572 if (dump_file && (dump_flags & TDF_DETAILS))
11573 fputs ("Instruction not appropriate for target.",
11574 dump_file);
11575
11576 /* Callers expect recog_for_combine to strip
11577 clobbers from the pattern on failure. */
11578 pat = pat_without_clobbers;
11579 notes = NULL_RTX;
11580
11581 insn_code_number = -1;
11582 }
11583
11584 PATTERN (insn) = old_pat;
11585 REG_NOTES (insn) = old_notes;
11586 INSN_CODE (insn) = old_icode;
11587 }
11588
11589 *pnewpat = pat;
11590 *pnotes = notes;
11591
11592 return insn_code_number;
11593 }
11594
11595 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11596 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11597 Return whether anything was so changed. */
11598
11599 static bool
change_zero_ext(rtx pat)11600 change_zero_ext (rtx pat)
11601 {
11602 bool changed = false;
11603 rtx *src = &SET_SRC (pat);
11604
11605 subrtx_ptr_iterator::array_type array;
11606 FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11607 {
11608 rtx x = **iter;
11609 scalar_int_mode mode, inner_mode;
11610 if (!is_a <scalar_int_mode> (GET_MODE (x), &mode))
11611 continue;
11612 int size;
11613
11614 if (GET_CODE (x) == ZERO_EXTRACT
11615 && CONST_INT_P (XEXP (x, 1))
11616 && CONST_INT_P (XEXP (x, 2))
11617 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode)
11618 && GET_MODE_PRECISION (inner_mode) <= GET_MODE_PRECISION (mode))
11619 {
11620 size = INTVAL (XEXP (x, 1));
11621
11622 int start = INTVAL (XEXP (x, 2));
11623 if (BITS_BIG_ENDIAN)
11624 start = GET_MODE_PRECISION (inner_mode) - size - start;
11625
11626 if (start != 0)
11627 x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0),
11628 gen_int_shift_amount (inner_mode, start));
11629 else
11630 x = XEXP (x, 0);
11631
11632 if (mode != inner_mode)
11633 {
11634 if (REG_P (x) && HARD_REGISTER_P (x)
11635 && !can_change_dest_mode (x, 0, mode))
11636 continue;
11637
11638 x = gen_lowpart_SUBREG (mode, x);
11639 }
11640 }
11641 else if (GET_CODE (x) == ZERO_EXTEND
11642 && GET_CODE (XEXP (x, 0)) == SUBREG
11643 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
11644 && !paradoxical_subreg_p (XEXP (x, 0))
11645 && subreg_lowpart_p (XEXP (x, 0)))
11646 {
11647 inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11648 size = GET_MODE_PRECISION (inner_mode);
11649 x = SUBREG_REG (XEXP (x, 0));
11650 if (GET_MODE (x) != mode)
11651 {
11652 if (REG_P (x) && HARD_REGISTER_P (x)
11653 && !can_change_dest_mode (x, 0, mode))
11654 continue;
11655
11656 x = gen_lowpart_SUBREG (mode, x);
11657 }
11658 }
11659 else if (GET_CODE (x) == ZERO_EXTEND
11660 && REG_P (XEXP (x, 0))
11661 && HARD_REGISTER_P (XEXP (x, 0))
11662 && can_change_dest_mode (XEXP (x, 0), 0, mode))
11663 {
11664 inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11665 size = GET_MODE_PRECISION (inner_mode);
11666 x = gen_rtx_REG (mode, REGNO (XEXP (x, 0)));
11667 }
11668 else
11669 continue;
11670
11671 if (!(GET_CODE (x) == LSHIFTRT
11672 && CONST_INT_P (XEXP (x, 1))
11673 && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode)))
11674 {
11675 wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode));
11676 x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
11677 }
11678
11679 SUBST (**iter, x);
11680 changed = true;
11681 }
11682
11683 if (changed)
11684 FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11685 maybe_swap_commutative_operands (**iter);
11686
11687 rtx *dst = &SET_DEST (pat);
11688 scalar_int_mode mode;
11689 if (GET_CODE (*dst) == ZERO_EXTRACT
11690 && REG_P (XEXP (*dst, 0))
11691 && is_a <scalar_int_mode> (GET_MODE (XEXP (*dst, 0)), &mode)
11692 && CONST_INT_P (XEXP (*dst, 1))
11693 && CONST_INT_P (XEXP (*dst, 2)))
11694 {
11695 rtx reg = XEXP (*dst, 0);
11696 int width = INTVAL (XEXP (*dst, 1));
11697 int offset = INTVAL (XEXP (*dst, 2));
11698 int reg_width = GET_MODE_PRECISION (mode);
11699 if (BITS_BIG_ENDIAN)
11700 offset = reg_width - width - offset;
11701
11702 rtx x, y, z, w;
11703 wide_int mask = wi::shifted_mask (offset, width, true, reg_width);
11704 wide_int mask2 = wi::shifted_mask (offset, width, false, reg_width);
11705 x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode));
11706 if (offset)
11707 y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset));
11708 else
11709 y = SET_SRC (pat);
11710 z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode));
11711 w = gen_rtx_IOR (mode, x, z);
11712 SUBST (SET_DEST (pat), reg);
11713 SUBST (SET_SRC (pat), w);
11714
11715 changed = true;
11716 }
11717
11718 return changed;
11719 }
11720
11721 /* Like recog, but we receive the address of a pointer to a new pattern.
11722 We try to match the rtx that the pointer points to.
11723 If that fails, we may try to modify or replace the pattern,
11724 storing the replacement into the same pointer object.
11725
11726 Modifications include deletion or addition of CLOBBERs. If the
11727 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11728 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11729 (and undo if that fails).
11730
11731 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11732 the CLOBBERs are placed.
11733
11734 The value is the final insn code from the pattern ultimately matched,
11735 or -1. */
11736
11737 static int
recog_for_combine(rtx * pnewpat,rtx_insn * insn,rtx * pnotes)11738 recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
11739 {
11740 rtx pat = *pnewpat;
11741 int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11742 if (insn_code_number >= 0 || check_asm_operands (pat))
11743 return insn_code_number;
11744
11745 void *marker = get_undo_marker ();
11746 bool changed = false;
11747
11748 if (GET_CODE (pat) == SET)
11749 changed = change_zero_ext (pat);
11750 else if (GET_CODE (pat) == PARALLEL)
11751 {
11752 int i;
11753 for (i = 0; i < XVECLEN (pat, 0); i++)
11754 {
11755 rtx set = XVECEXP (pat, 0, i);
11756 if (GET_CODE (set) == SET)
11757 changed |= change_zero_ext (set);
11758 }
11759 }
11760
11761 if (changed)
11762 {
11763 insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11764
11765 if (insn_code_number < 0)
11766 undo_to_marker (marker);
11767 }
11768
11769 return insn_code_number;
11770 }
11771
11772 /* Like gen_lowpart_general but for use by combine. In combine it
11773 is not possible to create any new pseudoregs. However, it is
11774 safe to create invalid memory addresses, because combine will
11775 try to recognize them and all they will do is make the combine
11776 attempt fail.
11777
11778 If for some reason this cannot do its job, an rtx
11779 (clobber (const_int 0)) is returned.
11780 An insn containing that will not be recognized. */
11781
11782 static rtx
gen_lowpart_for_combine(machine_mode omode,rtx x)11783 gen_lowpart_for_combine (machine_mode omode, rtx x)
11784 {
11785 machine_mode imode = GET_MODE (x);
11786 rtx result;
11787
11788 if (omode == imode)
11789 return x;
11790
11791 /* We can only support MODE being wider than a word if X is a
11792 constant integer or has a mode the same size. */
11793 if (maybe_gt (GET_MODE_SIZE (omode), UNITS_PER_WORD)
11794 && ! (CONST_SCALAR_INT_P (x)
11795 || known_eq (GET_MODE_SIZE (imode), GET_MODE_SIZE (omode))))
11796 goto fail;
11797
11798 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11799 won't know what to do. So we will strip off the SUBREG here and
11800 process normally. */
11801 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
11802 {
11803 x = SUBREG_REG (x);
11804
11805 /* For use in case we fall down into the address adjustments
11806 further below, we need to adjust the known mode and size of
11807 x; imode and isize, since we just adjusted x. */
11808 imode = GET_MODE (x);
11809
11810 if (imode == omode)
11811 return x;
11812 }
11813
11814 result = gen_lowpart_common (omode, x);
11815
11816 if (result)
11817 return result;
11818
11819 if (MEM_P (x))
11820 {
11821 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11822 address. */
11823 if (MEM_VOLATILE_P (x)
11824 || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
11825 goto fail;
11826
11827 /* If we want to refer to something bigger than the original memref,
11828 generate a paradoxical subreg instead. That will force a reload
11829 of the original memref X. */
11830 if (paradoxical_subreg_p (omode, imode))
11831 return gen_rtx_SUBREG (omode, x, 0);
11832
11833 poly_int64 offset = byte_lowpart_offset (omode, imode);
11834 return adjust_address_nv (x, omode, offset);
11835 }
11836
11837 /* If X is a comparison operator, rewrite it in a new mode. This
11838 probably won't match, but may allow further simplifications. */
11839 else if (COMPARISON_P (x)
11840 && SCALAR_INT_MODE_P (imode)
11841 && SCALAR_INT_MODE_P (omode))
11842 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
11843
11844 /* If we couldn't simplify X any other way, just enclose it in a
11845 SUBREG. Normally, this SUBREG won't match, but some patterns may
11846 include an explicit SUBREG or we may simplify it further in combine. */
11847 else
11848 {
11849 rtx res;
11850
11851 if (imode == VOIDmode)
11852 {
11853 imode = int_mode_for_mode (omode).require ();
11854 x = gen_lowpart_common (imode, x);
11855 if (x == NULL)
11856 goto fail;
11857 }
11858 res = lowpart_subreg (omode, x, imode);
11859 if (res)
11860 return res;
11861 }
11862
11863 fail:
11864 return gen_rtx_CLOBBER (omode, const0_rtx);
11865 }
11866
11867 /* Try to simplify a comparison between OP0 and a constant OP1,
11868 where CODE is the comparison code that will be tested, into a
11869 (CODE OP0 const0_rtx) form.
11870
11871 The result is a possibly different comparison code to use.
11872 *POP1 may be updated. */
11873
11874 static enum rtx_code
simplify_compare_const(enum rtx_code code,machine_mode mode,rtx op0,rtx * pop1)11875 simplify_compare_const (enum rtx_code code, machine_mode mode,
11876 rtx op0, rtx *pop1)
11877 {
11878 scalar_int_mode int_mode;
11879 HOST_WIDE_INT const_op = INTVAL (*pop1);
11880
11881 /* Get the constant we are comparing against and turn off all bits
11882 not on in our mode. */
11883 if (mode != VOIDmode)
11884 const_op = trunc_int_for_mode (const_op, mode);
11885
11886 /* If we are comparing against a constant power of two and the value
11887 being compared can only have that single bit nonzero (e.g., it was
11888 `and'ed with that bit), we can replace this with a comparison
11889 with zero. */
11890 if (const_op
11891 && (code == EQ || code == NE || code == GE || code == GEU
11892 || code == LT || code == LTU)
11893 && is_a <scalar_int_mode> (mode, &int_mode)
11894 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11895 && pow2p_hwi (const_op & GET_MODE_MASK (int_mode))
11896 && (nonzero_bits (op0, int_mode)
11897 == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (int_mode))))
11898 {
11899 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11900 const_op = 0;
11901 }
11902
11903 /* Similarly, if we are comparing a value known to be either -1 or
11904 0 with -1, change it to the opposite comparison against zero. */
11905 if (const_op == -1
11906 && (code == EQ || code == NE || code == GT || code == LE
11907 || code == GEU || code == LTU)
11908 && is_a <scalar_int_mode> (mode, &int_mode)
11909 && num_sign_bit_copies (op0, int_mode) == GET_MODE_PRECISION (int_mode))
11910 {
11911 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11912 const_op = 0;
11913 }
11914
11915 /* Do some canonicalizations based on the comparison code. We prefer
11916 comparisons against zero and then prefer equality comparisons.
11917 If we can reduce the size of a constant, we will do that too. */
11918 switch (code)
11919 {
11920 case LT:
11921 /* < C is equivalent to <= (C - 1) */
11922 if (const_op > 0)
11923 {
11924 const_op -= 1;
11925 code = LE;
11926 /* ... fall through to LE case below. */
11927 gcc_fallthrough ();
11928 }
11929 else
11930 break;
11931
11932 case LE:
11933 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11934 if (const_op < 0)
11935 {
11936 const_op += 1;
11937 code = LT;
11938 }
11939
11940 /* If we are doing a <= 0 comparison on a value known to have
11941 a zero sign bit, we can replace this with == 0. */
11942 else if (const_op == 0
11943 && is_a <scalar_int_mode> (mode, &int_mode)
11944 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11945 && (nonzero_bits (op0, int_mode)
11946 & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11947 == 0)
11948 code = EQ;
11949 break;
11950
11951 case GE:
11952 /* >= C is equivalent to > (C - 1). */
11953 if (const_op > 0)
11954 {
11955 const_op -= 1;
11956 code = GT;
11957 /* ... fall through to GT below. */
11958 gcc_fallthrough ();
11959 }
11960 else
11961 break;
11962
11963 case GT:
11964 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11965 if (const_op < 0)
11966 {
11967 const_op += 1;
11968 code = GE;
11969 }
11970
11971 /* If we are doing a > 0 comparison on a value known to have
11972 a zero sign bit, we can replace this with != 0. */
11973 else if (const_op == 0
11974 && is_a <scalar_int_mode> (mode, &int_mode)
11975 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11976 && (nonzero_bits (op0, int_mode)
11977 & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11978 == 0)
11979 code = NE;
11980 break;
11981
11982 case LTU:
11983 /* < C is equivalent to <= (C - 1). */
11984 if (const_op > 0)
11985 {
11986 const_op -= 1;
11987 code = LEU;
11988 /* ... fall through ... */
11989 gcc_fallthrough ();
11990 }
11991 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11992 else if (is_a <scalar_int_mode> (mode, &int_mode)
11993 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11994 && ((unsigned HOST_WIDE_INT) const_op
11995 == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11996 {
11997 const_op = 0;
11998 code = GE;
11999 break;
12000 }
12001 else
12002 break;
12003
12004 case LEU:
12005 /* unsigned <= 0 is equivalent to == 0 */
12006 if (const_op == 0)
12007 code = EQ;
12008 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
12009 else if (is_a <scalar_int_mode> (mode, &int_mode)
12010 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12011 && ((unsigned HOST_WIDE_INT) const_op
12012 == ((HOST_WIDE_INT_1U
12013 << (GET_MODE_PRECISION (int_mode) - 1)) - 1)))
12014 {
12015 const_op = 0;
12016 code = GE;
12017 }
12018 break;
12019
12020 case GEU:
12021 /* >= C is equivalent to > (C - 1). */
12022 if (const_op > 1)
12023 {
12024 const_op -= 1;
12025 code = GTU;
12026 /* ... fall through ... */
12027 gcc_fallthrough ();
12028 }
12029
12030 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
12031 else if (is_a <scalar_int_mode> (mode, &int_mode)
12032 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12033 && ((unsigned HOST_WIDE_INT) const_op
12034 == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12035 {
12036 const_op = 0;
12037 code = LT;
12038 break;
12039 }
12040 else
12041 break;
12042
12043 case GTU:
12044 /* unsigned > 0 is equivalent to != 0 */
12045 if (const_op == 0)
12046 code = NE;
12047 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12048 else if (is_a <scalar_int_mode> (mode, &int_mode)
12049 && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12050 && ((unsigned HOST_WIDE_INT) const_op
12051 == (HOST_WIDE_INT_1U
12052 << (GET_MODE_PRECISION (int_mode) - 1)) - 1))
12053 {
12054 const_op = 0;
12055 code = LT;
12056 }
12057 break;
12058
12059 default:
12060 break;
12061 }
12062
12063 *pop1 = GEN_INT (const_op);
12064 return code;
12065 }
12066
12067 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12068 comparison code that will be tested.
12069
12070 The result is a possibly different comparison code to use. *POP0 and
12071 *POP1 may be updated.
12072
12073 It is possible that we might detect that a comparison is either always
12074 true or always false. However, we do not perform general constant
12075 folding in combine, so this knowledge isn't useful. Such tautologies
12076 should have been detected earlier. Hence we ignore all such cases. */
12077
12078 static enum rtx_code
simplify_comparison(enum rtx_code code,rtx * pop0,rtx * pop1)12079 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
12080 {
12081 rtx op0 = *pop0;
12082 rtx op1 = *pop1;
12083 rtx tem, tem1;
12084 int i;
12085 scalar_int_mode mode, inner_mode, tmode;
12086 opt_scalar_int_mode tmode_iter;
12087
12088 /* Try a few ways of applying the same transformation to both operands. */
12089 while (1)
12090 {
12091 /* The test below this one won't handle SIGN_EXTENDs on these machines,
12092 so check specially. */
12093 if (!WORD_REGISTER_OPERATIONS
12094 && code != GTU && code != GEU && code != LTU && code != LEU
12095 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
12096 && GET_CODE (XEXP (op0, 0)) == ASHIFT
12097 && GET_CODE (XEXP (op1, 0)) == ASHIFT
12098 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
12099 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
12100 && is_a <scalar_int_mode> (GET_MODE (op0), &mode)
12101 && (is_a <scalar_int_mode>
12102 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
12103 && inner_mode == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))
12104 && CONST_INT_P (XEXP (op0, 1))
12105 && XEXP (op0, 1) == XEXP (op1, 1)
12106 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12107 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
12108 && (INTVAL (XEXP (op0, 1))
12109 == (GET_MODE_PRECISION (mode)
12110 - GET_MODE_PRECISION (inner_mode))))
12111 {
12112 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
12113 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
12114 }
12115
12116 /* If both operands are the same constant shift, see if we can ignore the
12117 shift. We can if the shift is a rotate or if the bits shifted out of
12118 this shift are known to be zero for both inputs and if the type of
12119 comparison is compatible with the shift. */
12120 if (GET_CODE (op0) == GET_CODE (op1)
12121 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
12122 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
12123 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
12124 && (code != GT && code != LT && code != GE && code != LE))
12125 || (GET_CODE (op0) == ASHIFTRT
12126 && (code != GTU && code != LTU
12127 && code != GEU && code != LEU)))
12128 && CONST_INT_P (XEXP (op0, 1))
12129 && INTVAL (XEXP (op0, 1)) >= 0
12130 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12131 && XEXP (op0, 1) == XEXP (op1, 1))
12132 {
12133 machine_mode mode = GET_MODE (op0);
12134 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12135 int shift_count = INTVAL (XEXP (op0, 1));
12136
12137 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
12138 mask &= (mask >> shift_count) << shift_count;
12139 else if (GET_CODE (op0) == ASHIFT)
12140 mask = (mask & (mask << shift_count)) >> shift_count;
12141
12142 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
12143 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
12144 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
12145 else
12146 break;
12147 }
12148
12149 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12150 SUBREGs are of the same mode, and, in both cases, the AND would
12151 be redundant if the comparison was done in the narrower mode,
12152 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12153 and the operand's possibly nonzero bits are 0xffffff01; in that case
12154 if we only care about QImode, we don't need the AND). This case
12155 occurs if the output mode of an scc insn is not SImode and
12156 STORE_FLAG_VALUE == 1 (e.g., the 386).
12157
12158 Similarly, check for a case where the AND's are ZERO_EXTEND
12159 operations from some narrower mode even though a SUBREG is not
12160 present. */
12161
12162 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
12163 && CONST_INT_P (XEXP (op0, 1))
12164 && CONST_INT_P (XEXP (op1, 1)))
12165 {
12166 rtx inner_op0 = XEXP (op0, 0);
12167 rtx inner_op1 = XEXP (op1, 0);
12168 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
12169 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
12170 int changed = 0;
12171
12172 if (paradoxical_subreg_p (inner_op0)
12173 && GET_CODE (inner_op1) == SUBREG
12174 && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
12175 && (GET_MODE (SUBREG_REG (inner_op0))
12176 == GET_MODE (SUBREG_REG (inner_op1)))
12177 && ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
12178 GET_MODE (SUBREG_REG (inner_op0)))) == 0
12179 && ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
12180 GET_MODE (SUBREG_REG (inner_op1)))) == 0)
12181 {
12182 op0 = SUBREG_REG (inner_op0);
12183 op1 = SUBREG_REG (inner_op1);
12184
12185 /* The resulting comparison is always unsigned since we masked
12186 off the original sign bit. */
12187 code = unsigned_condition (code);
12188
12189 changed = 1;
12190 }
12191
12192 else if (c0 == c1)
12193 FOR_EACH_MODE_UNTIL (tmode,
12194 as_a <scalar_int_mode> (GET_MODE (op0)))
12195 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
12196 {
12197 op0 = gen_lowpart_or_truncate (tmode, inner_op0);
12198 op1 = gen_lowpart_or_truncate (tmode, inner_op1);
12199 code = unsigned_condition (code);
12200 changed = 1;
12201 break;
12202 }
12203
12204 if (! changed)
12205 break;
12206 }
12207
12208 /* If both operands are NOT, we can strip off the outer operation
12209 and adjust the comparison code for swapped operands; similarly for
12210 NEG, except that this must be an equality comparison. */
12211 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
12212 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
12213 && (code == EQ || code == NE)))
12214 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
12215
12216 else
12217 break;
12218 }
12219
12220 /* If the first operand is a constant, swap the operands and adjust the
12221 comparison code appropriately, but don't do this if the second operand
12222 is already a constant integer. */
12223 if (swap_commutative_operands_p (op0, op1))
12224 {
12225 std::swap (op0, op1);
12226 code = swap_condition (code);
12227 }
12228
12229 /* We now enter a loop during which we will try to simplify the comparison.
12230 For the most part, we only are concerned with comparisons with zero,
12231 but some things may really be comparisons with zero but not start
12232 out looking that way. */
12233
12234 while (CONST_INT_P (op1))
12235 {
12236 machine_mode raw_mode = GET_MODE (op0);
12237 scalar_int_mode int_mode;
12238 int equality_comparison_p;
12239 int sign_bit_comparison_p;
12240 int unsigned_comparison_p;
12241 HOST_WIDE_INT const_op;
12242
12243 /* We only want to handle integral modes. This catches VOIDmode,
12244 CCmode, and the floating-point modes. An exception is that we
12245 can handle VOIDmode if OP0 is a COMPARE or a comparison
12246 operation. */
12247
12248 if (GET_MODE_CLASS (raw_mode) != MODE_INT
12249 && ! (raw_mode == VOIDmode
12250 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
12251 break;
12252
12253 /* Try to simplify the compare to constant, possibly changing the
12254 comparison op, and/or changing op1 to zero. */
12255 code = simplify_compare_const (code, raw_mode, op0, &op1);
12256 const_op = INTVAL (op1);
12257
12258 /* Compute some predicates to simplify code below. */
12259
12260 equality_comparison_p = (code == EQ || code == NE);
12261 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
12262 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
12263 || code == GEU);
12264
12265 /* If this is a sign bit comparison and we can do arithmetic in
12266 MODE, say that we will only be needing the sign bit of OP0. */
12267 if (sign_bit_comparison_p
12268 && is_a <scalar_int_mode> (raw_mode, &int_mode)
12269 && HWI_COMPUTABLE_MODE_P (int_mode))
12270 op0 = force_to_mode (op0, int_mode,
12271 HOST_WIDE_INT_1U
12272 << (GET_MODE_PRECISION (int_mode) - 1),
12273 0);
12274
12275 if (COMPARISON_P (op0))
12276 {
12277 /* We can't do anything if OP0 is a condition code value, rather
12278 than an actual data value. */
12279 if (const_op != 0
12280 || CC0_P (XEXP (op0, 0))
12281 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
12282 break;
12283
12284 /* Get the two operands being compared. */
12285 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
12286 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
12287 else
12288 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
12289
12290 /* Check for the cases where we simply want the result of the
12291 earlier test or the opposite of that result. */
12292 if (code == NE || code == EQ
12293 || (val_signbit_known_set_p (raw_mode, STORE_FLAG_VALUE)
12294 && (code == LT || code == GE)))
12295 {
12296 enum rtx_code new_code;
12297 if (code == LT || code == NE)
12298 new_code = GET_CODE (op0);
12299 else
12300 new_code = reversed_comparison_code (op0, NULL);
12301
12302 if (new_code != UNKNOWN)
12303 {
12304 code = new_code;
12305 op0 = tem;
12306 op1 = tem1;
12307 continue;
12308 }
12309 }
12310 break;
12311 }
12312
12313 if (raw_mode == VOIDmode)
12314 break;
12315 scalar_int_mode mode = as_a <scalar_int_mode> (raw_mode);
12316
12317 /* Now try cases based on the opcode of OP0. If none of the cases
12318 does a "continue", we exit this loop immediately after the
12319 switch. */
12320
12321 unsigned int mode_width = GET_MODE_PRECISION (mode);
12322 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12323 switch (GET_CODE (op0))
12324 {
12325 case ZERO_EXTRACT:
12326 /* If we are extracting a single bit from a variable position in
12327 a constant that has only a single bit set and are comparing it
12328 with zero, we can convert this into an equality comparison
12329 between the position and the location of the single bit. */
12330 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12331 have already reduced the shift count modulo the word size. */
12332 if (!SHIFT_COUNT_TRUNCATED
12333 && CONST_INT_P (XEXP (op0, 0))
12334 && XEXP (op0, 1) == const1_rtx
12335 && equality_comparison_p && const_op == 0
12336 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
12337 {
12338 if (BITS_BIG_ENDIAN)
12339 i = BITS_PER_WORD - 1 - i;
12340
12341 op0 = XEXP (op0, 2);
12342 op1 = GEN_INT (i);
12343 const_op = i;
12344
12345 /* Result is nonzero iff shift count is equal to I. */
12346 code = reverse_condition (code);
12347 continue;
12348 }
12349
12350 /* fall through */
12351
12352 case SIGN_EXTRACT:
12353 tem = expand_compound_operation (op0);
12354 if (tem != op0)
12355 {
12356 op0 = tem;
12357 continue;
12358 }
12359 break;
12360
12361 case NOT:
12362 /* If testing for equality, we can take the NOT of the constant. */
12363 if (equality_comparison_p
12364 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
12365 {
12366 op0 = XEXP (op0, 0);
12367 op1 = tem;
12368 continue;
12369 }
12370
12371 /* If just looking at the sign bit, reverse the sense of the
12372 comparison. */
12373 if (sign_bit_comparison_p)
12374 {
12375 op0 = XEXP (op0, 0);
12376 code = (code == GE ? LT : GE);
12377 continue;
12378 }
12379 break;
12380
12381 case NEG:
12382 /* If testing for equality, we can take the NEG of the constant. */
12383 if (equality_comparison_p
12384 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
12385 {
12386 op0 = XEXP (op0, 0);
12387 op1 = tem;
12388 continue;
12389 }
12390
12391 /* The remaining cases only apply to comparisons with zero. */
12392 if (const_op != 0)
12393 break;
12394
12395 /* When X is ABS or is known positive,
12396 (neg X) is < 0 if and only if X != 0. */
12397
12398 if (sign_bit_comparison_p
12399 && (GET_CODE (XEXP (op0, 0)) == ABS
12400 || (mode_width <= HOST_BITS_PER_WIDE_INT
12401 && (nonzero_bits (XEXP (op0, 0), mode)
12402 & (HOST_WIDE_INT_1U << (mode_width - 1)))
12403 == 0)))
12404 {
12405 op0 = XEXP (op0, 0);
12406 code = (code == LT ? NE : EQ);
12407 continue;
12408 }
12409
12410 /* If we have NEG of something whose two high-order bits are the
12411 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12412 if (num_sign_bit_copies (op0, mode) >= 2)
12413 {
12414 op0 = XEXP (op0, 0);
12415 code = swap_condition (code);
12416 continue;
12417 }
12418 break;
12419
12420 case ROTATE:
12421 /* If we are testing equality and our count is a constant, we
12422 can perform the inverse operation on our RHS. */
12423 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
12424 && (tem = simplify_binary_operation (ROTATERT, mode,
12425 op1, XEXP (op0, 1))) != 0)
12426 {
12427 op0 = XEXP (op0, 0);
12428 op1 = tem;
12429 continue;
12430 }
12431
12432 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12433 a particular bit. Convert it to an AND of a constant of that
12434 bit. This will be converted into a ZERO_EXTRACT. */
12435 if (const_op == 0 && sign_bit_comparison_p
12436 && CONST_INT_P (XEXP (op0, 1))
12437 && mode_width <= HOST_BITS_PER_WIDE_INT
12438 && UINTVAL (XEXP (op0, 1)) < mode_width)
12439 {
12440 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12441 (HOST_WIDE_INT_1U
12442 << (mode_width - 1
12443 - INTVAL (XEXP (op0, 1)))));
12444 code = (code == LT ? NE : EQ);
12445 continue;
12446 }
12447
12448 /* Fall through. */
12449
12450 case ABS:
12451 /* ABS is ignorable inside an equality comparison with zero. */
12452 if (const_op == 0 && equality_comparison_p)
12453 {
12454 op0 = XEXP (op0, 0);
12455 continue;
12456 }
12457 break;
12458
12459 case SIGN_EXTEND:
12460 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12461 (compare FOO CONST) if CONST fits in FOO's mode and we
12462 are either testing inequality or have an unsigned
12463 comparison with ZERO_EXTEND or a signed comparison with
12464 SIGN_EXTEND. But don't do it if we don't have a compare
12465 insn of the given mode, since we'd have to revert it
12466 later on, and then we wouldn't know whether to sign- or
12467 zero-extend. */
12468 if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12469 && ! unsigned_comparison_p
12470 && HWI_COMPUTABLE_MODE_P (mode)
12471 && trunc_int_for_mode (const_op, mode) == const_op
12472 && have_insn_for (COMPARE, mode))
12473 {
12474 op0 = XEXP (op0, 0);
12475 continue;
12476 }
12477 break;
12478
12479 case SUBREG:
12480 /* Check for the case where we are comparing A - C1 with C2, that is
12481
12482 (subreg:MODE (plus (A) (-C1))) op (C2)
12483
12484 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12485 comparison in the wider mode. One of the following two conditions
12486 must be true in order for this to be valid:
12487
12488 1. The mode extension results in the same bit pattern being added
12489 on both sides and the comparison is equality or unsigned. As
12490 C2 has been truncated to fit in MODE, the pattern can only be
12491 all 0s or all 1s.
12492
12493 2. The mode extension results in the sign bit being copied on
12494 each side.
12495
12496 The difficulty here is that we have predicates for A but not for
12497 (A - C1) so we need to check that C1 is within proper bounds so
12498 as to perturbate A as little as possible. */
12499
12500 if (mode_width <= HOST_BITS_PER_WIDE_INT
12501 && subreg_lowpart_p (op0)
12502 && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12503 &inner_mode)
12504 && GET_MODE_PRECISION (inner_mode) > mode_width
12505 && GET_CODE (SUBREG_REG (op0)) == PLUS
12506 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
12507 {
12508 rtx a = XEXP (SUBREG_REG (op0), 0);
12509 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
12510
12511 if ((c1 > 0
12512 && (unsigned HOST_WIDE_INT) c1
12513 < HOST_WIDE_INT_1U << (mode_width - 1)
12514 && (equality_comparison_p || unsigned_comparison_p)
12515 /* (A - C1) zero-extends if it is positive and sign-extends
12516 if it is negative, C2 both zero- and sign-extends. */
12517 && (((nonzero_bits (a, inner_mode)
12518 & ~GET_MODE_MASK (mode)) == 0
12519 && const_op >= 0)
12520 /* (A - C1) sign-extends if it is positive and 1-extends
12521 if it is negative, C2 both sign- and 1-extends. */
12522 || (num_sign_bit_copies (a, inner_mode)
12523 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12524 - mode_width)
12525 && const_op < 0)))
12526 || ((unsigned HOST_WIDE_INT) c1
12527 < HOST_WIDE_INT_1U << (mode_width - 2)
12528 /* (A - C1) always sign-extends, like C2. */
12529 && num_sign_bit_copies (a, inner_mode)
12530 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12531 - (mode_width - 1))))
12532 {
12533 op0 = SUBREG_REG (op0);
12534 continue;
12535 }
12536 }
12537
12538 /* If the inner mode is narrower and we are extracting the low part,
12539 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12540 if (paradoxical_subreg_p (op0))
12541 ;
12542 else if (subreg_lowpart_p (op0)
12543 && GET_MODE_CLASS (mode) == MODE_INT
12544 && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
12545 && (code == NE || code == EQ)
12546 && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
12547 && !paradoxical_subreg_p (op0)
12548 && (nonzero_bits (SUBREG_REG (op0), inner_mode)
12549 & ~GET_MODE_MASK (mode)) == 0)
12550 {
12551 /* Remove outer subregs that don't do anything. */
12552 tem = gen_lowpart (inner_mode, op1);
12553
12554 if ((nonzero_bits (tem, inner_mode)
12555 & ~GET_MODE_MASK (mode)) == 0)
12556 {
12557 op0 = SUBREG_REG (op0);
12558 op1 = tem;
12559 continue;
12560 }
12561 break;
12562 }
12563 else
12564 break;
12565
12566 /* FALLTHROUGH */
12567
12568 case ZERO_EXTEND:
12569 if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12570 && (unsigned_comparison_p || equality_comparison_p)
12571 && HWI_COMPUTABLE_MODE_P (mode)
12572 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
12573 && const_op >= 0
12574 && have_insn_for (COMPARE, mode))
12575 {
12576 op0 = XEXP (op0, 0);
12577 continue;
12578 }
12579 break;
12580
12581 case PLUS:
12582 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12583 this for equality comparisons due to pathological cases involving
12584 overflows. */
12585 if (equality_comparison_p
12586 && (tem = simplify_binary_operation (MINUS, mode,
12587 op1, XEXP (op0, 1))) != 0)
12588 {
12589 op0 = XEXP (op0, 0);
12590 op1 = tem;
12591 continue;
12592 }
12593
12594 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12595 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
12596 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
12597 {
12598 op0 = XEXP (XEXP (op0, 0), 0);
12599 code = (code == LT ? EQ : NE);
12600 continue;
12601 }
12602 break;
12603
12604 case MINUS:
12605 /* We used to optimize signed comparisons against zero, but that
12606 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12607 arrive here as equality comparisons, or (GEU, LTU) are
12608 optimized away. No need to special-case them. */
12609
12610 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12611 (eq B (minus A C)), whichever simplifies. We can only do
12612 this for equality comparisons due to pathological cases involving
12613 overflows. */
12614 if (equality_comparison_p
12615 && (tem = simplify_binary_operation (PLUS, mode,
12616 XEXP (op0, 1), op1)) != 0)
12617 {
12618 op0 = XEXP (op0, 0);
12619 op1 = tem;
12620 continue;
12621 }
12622
12623 if (equality_comparison_p
12624 && (tem = simplify_binary_operation (MINUS, mode,
12625 XEXP (op0, 0), op1)) != 0)
12626 {
12627 op0 = XEXP (op0, 1);
12628 op1 = tem;
12629 continue;
12630 }
12631
12632 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12633 of bits in X minus 1, is one iff X > 0. */
12634 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
12635 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12636 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
12637 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12638 {
12639 op0 = XEXP (op0, 1);
12640 code = (code == GE ? LE : GT);
12641 continue;
12642 }
12643 break;
12644
12645 case XOR:
12646 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12647 if C is zero or B is a constant. */
12648 if (equality_comparison_p
12649 && (tem = simplify_binary_operation (XOR, mode,
12650 XEXP (op0, 1), op1)) != 0)
12651 {
12652 op0 = XEXP (op0, 0);
12653 op1 = tem;
12654 continue;
12655 }
12656 break;
12657
12658
12659 case IOR:
12660 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12661 iff X <= 0. */
12662 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
12663 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
12664 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12665 {
12666 op0 = XEXP (op0, 1);
12667 code = (code == GE ? GT : LE);
12668 continue;
12669 }
12670 break;
12671
12672 case AND:
12673 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12674 will be converted to a ZERO_EXTRACT later. */
12675 if (const_op == 0 && equality_comparison_p
12676 && GET_CODE (XEXP (op0, 0)) == ASHIFT
12677 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
12678 {
12679 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
12680 XEXP (XEXP (op0, 0), 1));
12681 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12682 continue;
12683 }
12684
12685 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12686 zero and X is a comparison and C1 and C2 describe only bits set
12687 in STORE_FLAG_VALUE, we can compare with X. */
12688 if (const_op == 0 && equality_comparison_p
12689 && mode_width <= HOST_BITS_PER_WIDE_INT
12690 && CONST_INT_P (XEXP (op0, 1))
12691 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
12692 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12693 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
12694 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
12695 {
12696 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12697 << INTVAL (XEXP (XEXP (op0, 0), 1)));
12698 if ((~STORE_FLAG_VALUE & mask) == 0
12699 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
12700 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
12701 && COMPARISON_P (tem))))
12702 {
12703 op0 = XEXP (XEXP (op0, 0), 0);
12704 continue;
12705 }
12706 }
12707
12708 /* If we are doing an equality comparison of an AND of a bit equal
12709 to the sign bit, replace this with a LT or GE comparison of
12710 the underlying value. */
12711 if (equality_comparison_p
12712 && const_op == 0
12713 && CONST_INT_P (XEXP (op0, 1))
12714 && mode_width <= HOST_BITS_PER_WIDE_INT
12715 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12716 == HOST_WIDE_INT_1U << (mode_width - 1)))
12717 {
12718 op0 = XEXP (op0, 0);
12719 code = (code == EQ ? GE : LT);
12720 continue;
12721 }
12722
12723 /* If this AND operation is really a ZERO_EXTEND from a narrower
12724 mode, the constant fits within that mode, and this is either an
12725 equality or unsigned comparison, try to do this comparison in
12726 the narrower mode.
12727
12728 Note that in:
12729
12730 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12731 -> (ne:DI (reg:SI 4) (const_int 0))
12732
12733 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12734 known to hold a value of the required mode the
12735 transformation is invalid. */
12736 if ((equality_comparison_p || unsigned_comparison_p)
12737 && CONST_INT_P (XEXP (op0, 1))
12738 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
12739 & GET_MODE_MASK (mode))
12740 + 1)) >= 0
12741 && const_op >> i == 0
12742 && int_mode_for_size (i, 1).exists (&tmode))
12743 {
12744 op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0));
12745 continue;
12746 }
12747
12748 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12749 fits in both M1 and M2 and the SUBREG is either paradoxical
12750 or represents the low part, permute the SUBREG and the AND
12751 and try again. */
12752 if (GET_CODE (XEXP (op0, 0)) == SUBREG
12753 && CONST_INT_P (XEXP (op0, 1)))
12754 {
12755 unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
12756 /* Require an integral mode, to avoid creating something like
12757 (AND:SF ...). */
12758 if ((is_a <scalar_int_mode>
12759 (GET_MODE (SUBREG_REG (XEXP (op0, 0))), &tmode))
12760 /* It is unsafe to commute the AND into the SUBREG if the
12761 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12762 not defined. As originally written the upper bits
12763 have a defined value due to the AND operation.
12764 However, if we commute the AND inside the SUBREG then
12765 they no longer have defined values and the meaning of
12766 the code has been changed.
12767 Also C1 should not change value in the smaller mode,
12768 see PR67028 (a positive C1 can become negative in the
12769 smaller mode, so that the AND does no longer mask the
12770 upper bits). */
12771 && ((WORD_REGISTER_OPERATIONS
12772 && mode_width > GET_MODE_PRECISION (tmode)
12773 && mode_width <= BITS_PER_WORD
12774 && trunc_int_for_mode (c1, tmode) == (HOST_WIDE_INT) c1)
12775 || (mode_width <= GET_MODE_PRECISION (tmode)
12776 && subreg_lowpart_p (XEXP (op0, 0))))
12777 && mode_width <= HOST_BITS_PER_WIDE_INT
12778 && HWI_COMPUTABLE_MODE_P (tmode)
12779 && (c1 & ~mask) == 0
12780 && (c1 & ~GET_MODE_MASK (tmode)) == 0
12781 && c1 != mask
12782 && c1 != GET_MODE_MASK (tmode))
12783 {
12784 op0 = simplify_gen_binary (AND, tmode,
12785 SUBREG_REG (XEXP (op0, 0)),
12786 gen_int_mode (c1, tmode));
12787 op0 = gen_lowpart (mode, op0);
12788 continue;
12789 }
12790 }
12791
12792 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12793 if (const_op == 0 && equality_comparison_p
12794 && XEXP (op0, 1) == const1_rtx
12795 && GET_CODE (XEXP (op0, 0)) == NOT)
12796 {
12797 op0 = simplify_and_const_int (NULL_RTX, mode,
12798 XEXP (XEXP (op0, 0), 0), 1);
12799 code = (code == NE ? EQ : NE);
12800 continue;
12801 }
12802
12803 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12804 (eq (and (lshiftrt X) 1) 0).
12805 Also handle the case where (not X) is expressed using xor. */
12806 if (const_op == 0 && equality_comparison_p
12807 && XEXP (op0, 1) == const1_rtx
12808 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
12809 {
12810 rtx shift_op = XEXP (XEXP (op0, 0), 0);
12811 rtx shift_count = XEXP (XEXP (op0, 0), 1);
12812
12813 if (GET_CODE (shift_op) == NOT
12814 || (GET_CODE (shift_op) == XOR
12815 && CONST_INT_P (XEXP (shift_op, 1))
12816 && CONST_INT_P (shift_count)
12817 && HWI_COMPUTABLE_MODE_P (mode)
12818 && (UINTVAL (XEXP (shift_op, 1))
12819 == HOST_WIDE_INT_1U
12820 << INTVAL (shift_count))))
12821 {
12822 op0
12823 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
12824 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12825 code = (code == NE ? EQ : NE);
12826 continue;
12827 }
12828 }
12829 break;
12830
12831 case ASHIFT:
12832 /* If we have (compare (ashift FOO N) (const_int C)) and
12833 the high order N bits of FOO (N+1 if an inequality comparison)
12834 are known to be zero, we can do this by comparing FOO with C
12835 shifted right N bits so long as the low-order N bits of C are
12836 zero. */
12837 if (CONST_INT_P (XEXP (op0, 1))
12838 && INTVAL (XEXP (op0, 1)) >= 0
12839 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
12840 < HOST_BITS_PER_WIDE_INT)
12841 && (((unsigned HOST_WIDE_INT) const_op
12842 & ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1)))
12843 - 1)) == 0)
12844 && mode_width <= HOST_BITS_PER_WIDE_INT
12845 && (nonzero_bits (XEXP (op0, 0), mode)
12846 & ~(mask >> (INTVAL (XEXP (op0, 1))
12847 + ! equality_comparison_p))) == 0)
12848 {
12849 /* We must perform a logical shift, not an arithmetic one,
12850 as we want the top N bits of C to be zero. */
12851 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
12852
12853 temp >>= INTVAL (XEXP (op0, 1));
12854 op1 = gen_int_mode (temp, mode);
12855 op0 = XEXP (op0, 0);
12856 continue;
12857 }
12858
12859 /* If we are doing a sign bit comparison, it means we are testing
12860 a particular bit. Convert it to the appropriate AND. */
12861 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
12862 && mode_width <= HOST_BITS_PER_WIDE_INT)
12863 {
12864 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12865 (HOST_WIDE_INT_1U
12866 << (mode_width - 1
12867 - INTVAL (XEXP (op0, 1)))));
12868 code = (code == LT ? NE : EQ);
12869 continue;
12870 }
12871
12872 /* If this an equality comparison with zero and we are shifting
12873 the low bit to the sign bit, we can convert this to an AND of the
12874 low-order bit. */
12875 if (const_op == 0 && equality_comparison_p
12876 && CONST_INT_P (XEXP (op0, 1))
12877 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12878 {
12879 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
12880 continue;
12881 }
12882 break;
12883
12884 case ASHIFTRT:
12885 /* If this is an equality comparison with zero, we can do this
12886 as a logical shift, which might be much simpler. */
12887 if (equality_comparison_p && const_op == 0
12888 && CONST_INT_P (XEXP (op0, 1)))
12889 {
12890 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
12891 XEXP (op0, 0),
12892 INTVAL (XEXP (op0, 1)));
12893 continue;
12894 }
12895
12896 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12897 do the comparison in a narrower mode. */
12898 if (! unsigned_comparison_p
12899 && CONST_INT_P (XEXP (op0, 1))
12900 && GET_CODE (XEXP (op0, 0)) == ASHIFT
12901 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12902 && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
12903 .exists (&tmode))
12904 && (((unsigned HOST_WIDE_INT) const_op
12905 + (GET_MODE_MASK (tmode) >> 1) + 1)
12906 <= GET_MODE_MASK (tmode)))
12907 {
12908 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
12909 continue;
12910 }
12911
12912 /* Likewise if OP0 is a PLUS of a sign extension with a
12913 constant, which is usually represented with the PLUS
12914 between the shifts. */
12915 if (! unsigned_comparison_p
12916 && CONST_INT_P (XEXP (op0, 1))
12917 && GET_CODE (XEXP (op0, 0)) == PLUS
12918 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12919 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
12920 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
12921 && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
12922 .exists (&tmode))
12923 && (((unsigned HOST_WIDE_INT) const_op
12924 + (GET_MODE_MASK (tmode) >> 1) + 1)
12925 <= GET_MODE_MASK (tmode)))
12926 {
12927 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
12928 rtx add_const = XEXP (XEXP (op0, 0), 1);
12929 rtx new_const = simplify_gen_binary (ASHIFTRT, mode,
12930 add_const, XEXP (op0, 1));
12931
12932 op0 = simplify_gen_binary (PLUS, tmode,
12933 gen_lowpart (tmode, inner),
12934 new_const);
12935 continue;
12936 }
12937
12938 /* FALLTHROUGH */
12939 case LSHIFTRT:
12940 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12941 the low order N bits of FOO are known to be zero, we can do this
12942 by comparing FOO with C shifted left N bits so long as no
12943 overflow occurs. Even if the low order N bits of FOO aren't known
12944 to be zero, if the comparison is >= or < we can use the same
12945 optimization and for > or <= by setting all the low
12946 order N bits in the comparison constant. */
12947 if (CONST_INT_P (XEXP (op0, 1))
12948 && INTVAL (XEXP (op0, 1)) > 0
12949 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12950 && mode_width <= HOST_BITS_PER_WIDE_INT
12951 && (((unsigned HOST_WIDE_INT) const_op
12952 + (GET_CODE (op0) != LSHIFTRT
12953 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
12954 + 1)
12955 : 0))
12956 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
12957 {
12958 unsigned HOST_WIDE_INT low_bits
12959 = (nonzero_bits (XEXP (op0, 0), mode)
12960 & ((HOST_WIDE_INT_1U
12961 << INTVAL (XEXP (op0, 1))) - 1));
12962 if (low_bits == 0 || !equality_comparison_p)
12963 {
12964 /* If the shift was logical, then we must make the condition
12965 unsigned. */
12966 if (GET_CODE (op0) == LSHIFTRT)
12967 code = unsigned_condition (code);
12968
12969 const_op = (unsigned HOST_WIDE_INT) const_op
12970 << INTVAL (XEXP (op0, 1));
12971 if (low_bits != 0
12972 && (code == GT || code == GTU
12973 || code == LE || code == LEU))
12974 const_op
12975 |= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1);
12976 op1 = GEN_INT (const_op);
12977 op0 = XEXP (op0, 0);
12978 continue;
12979 }
12980 }
12981
12982 /* If we are using this shift to extract just the sign bit, we
12983 can replace this with an LT or GE comparison. */
12984 if (const_op == 0
12985 && (equality_comparison_p || sign_bit_comparison_p)
12986 && CONST_INT_P (XEXP (op0, 1))
12987 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12988 {
12989 op0 = XEXP (op0, 0);
12990 code = (code == NE || code == GT ? LT : GE);
12991 continue;
12992 }
12993 break;
12994
12995 default:
12996 break;
12997 }
12998
12999 break;
13000 }
13001
13002 /* Now make any compound operations involved in this comparison. Then,
13003 check for an outmost SUBREG on OP0 that is not doing anything or is
13004 paradoxical. The latter transformation must only be performed when
13005 it is known that the "extra" bits will be the same in op0 and op1 or
13006 that they don't matter. There are three cases to consider:
13007
13008 1. SUBREG_REG (op0) is a register. In this case the bits are don't
13009 care bits and we can assume they have any convenient value. So
13010 making the transformation is safe.
13011
13012 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13013 In this case the upper bits of op0 are undefined. We should not make
13014 the simplification in that case as we do not know the contents of
13015 those bits.
13016
13017 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13018 In that case we know those bits are zeros or ones. We must also be
13019 sure that they are the same as the upper bits of op1.
13020
13021 We can never remove a SUBREG for a non-equality comparison because
13022 the sign bit is in a different place in the underlying object. */
13023
13024 rtx_code op0_mco_code = SET;
13025 if (op1 == const0_rtx)
13026 op0_mco_code = code == NE || code == EQ ? EQ : COMPARE;
13027
13028 op0 = make_compound_operation (op0, op0_mco_code);
13029 op1 = make_compound_operation (op1, SET);
13030
13031 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
13032 && is_int_mode (GET_MODE (op0), &mode)
13033 && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
13034 && (code == NE || code == EQ))
13035 {
13036 if (paradoxical_subreg_p (op0))
13037 {
13038 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13039 implemented. */
13040 if (REG_P (SUBREG_REG (op0)))
13041 {
13042 op0 = SUBREG_REG (op0);
13043 op1 = gen_lowpart (inner_mode, op1);
13044 }
13045 }
13046 else if (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
13047 && (nonzero_bits (SUBREG_REG (op0), inner_mode)
13048 & ~GET_MODE_MASK (mode)) == 0)
13049 {
13050 tem = gen_lowpart (inner_mode, op1);
13051
13052 if ((nonzero_bits (tem, inner_mode) & ~GET_MODE_MASK (mode)) == 0)
13053 op0 = SUBREG_REG (op0), op1 = tem;
13054 }
13055 }
13056
13057 /* We now do the opposite procedure: Some machines don't have compare
13058 insns in all modes. If OP0's mode is an integer mode smaller than a
13059 word and we can't do a compare in that mode, see if there is a larger
13060 mode for which we can do the compare. There are a number of cases in
13061 which we can use the wider mode. */
13062
13063 if (is_int_mode (GET_MODE (op0), &mode)
13064 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
13065 && ! have_insn_for (COMPARE, mode))
13066 FOR_EACH_WIDER_MODE (tmode_iter, mode)
13067 {
13068 tmode = tmode_iter.require ();
13069 if (!HWI_COMPUTABLE_MODE_P (tmode))
13070 break;
13071 if (have_insn_for (COMPARE, tmode))
13072 {
13073 int zero_extended;
13074
13075 /* If this is a test for negative, we can make an explicit
13076 test of the sign bit. Test this first so we can use
13077 a paradoxical subreg to extend OP0. */
13078
13079 if (op1 == const0_rtx && (code == LT || code == GE)
13080 && HWI_COMPUTABLE_MODE_P (mode))
13081 {
13082 unsigned HOST_WIDE_INT sign
13083 = HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1);
13084 op0 = simplify_gen_binary (AND, tmode,
13085 gen_lowpart (tmode, op0),
13086 gen_int_mode (sign, tmode));
13087 code = (code == LT) ? NE : EQ;
13088 break;
13089 }
13090
13091 /* If the only nonzero bits in OP0 and OP1 are those in the
13092 narrower mode and this is an equality or unsigned comparison,
13093 we can use the wider mode. Similarly for sign-extended
13094 values, in which case it is true for all comparisons. */
13095 zero_extended = ((code == EQ || code == NE
13096 || code == GEU || code == GTU
13097 || code == LEU || code == LTU)
13098 && (nonzero_bits (op0, tmode)
13099 & ~GET_MODE_MASK (mode)) == 0
13100 && ((CONST_INT_P (op1)
13101 || (nonzero_bits (op1, tmode)
13102 & ~GET_MODE_MASK (mode)) == 0)));
13103
13104 if (zero_extended
13105 || ((num_sign_bit_copies (op0, tmode)
13106 > (unsigned int) (GET_MODE_PRECISION (tmode)
13107 - GET_MODE_PRECISION (mode)))
13108 && (num_sign_bit_copies (op1, tmode)
13109 > (unsigned int) (GET_MODE_PRECISION (tmode)
13110 - GET_MODE_PRECISION (mode)))))
13111 {
13112 /* If OP0 is an AND and we don't have an AND in MODE either,
13113 make a new AND in the proper mode. */
13114 if (GET_CODE (op0) == AND
13115 && !have_insn_for (AND, mode))
13116 op0 = simplify_gen_binary (AND, tmode,
13117 gen_lowpart (tmode,
13118 XEXP (op0, 0)),
13119 gen_lowpart (tmode,
13120 XEXP (op0, 1)));
13121 else
13122 {
13123 if (zero_extended)
13124 {
13125 op0 = simplify_gen_unary (ZERO_EXTEND, tmode,
13126 op0, mode);
13127 op1 = simplify_gen_unary (ZERO_EXTEND, tmode,
13128 op1, mode);
13129 }
13130 else
13131 {
13132 op0 = simplify_gen_unary (SIGN_EXTEND, tmode,
13133 op0, mode);
13134 op1 = simplify_gen_unary (SIGN_EXTEND, tmode,
13135 op1, mode);
13136 }
13137 break;
13138 }
13139 }
13140 }
13141 }
13142
13143 /* We may have changed the comparison operands. Re-canonicalize. */
13144 if (swap_commutative_operands_p (op0, op1))
13145 {
13146 std::swap (op0, op1);
13147 code = swap_condition (code);
13148 }
13149
13150 /* If this machine only supports a subset of valid comparisons, see if we
13151 can convert an unsupported one into a supported one. */
13152 target_canonicalize_comparison (&code, &op0, &op1, 0);
13153
13154 *pop0 = op0;
13155 *pop1 = op1;
13156
13157 return code;
13158 }
13159
13160 /* Utility function for record_value_for_reg. Count number of
13161 rtxs in X. */
13162 static int
count_rtxs(rtx x)13163 count_rtxs (rtx x)
13164 {
13165 enum rtx_code code = GET_CODE (x);
13166 const char *fmt;
13167 int i, j, ret = 1;
13168
13169 if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
13170 || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
13171 {
13172 rtx x0 = XEXP (x, 0);
13173 rtx x1 = XEXP (x, 1);
13174
13175 if (x0 == x1)
13176 return 1 + 2 * count_rtxs (x0);
13177
13178 if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
13179 || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
13180 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13181 return 2 + 2 * count_rtxs (x0)
13182 + count_rtxs (x == XEXP (x1, 0)
13183 ? XEXP (x1, 1) : XEXP (x1, 0));
13184
13185 if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
13186 || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
13187 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13188 return 2 + 2 * count_rtxs (x1)
13189 + count_rtxs (x == XEXP (x0, 0)
13190 ? XEXP (x0, 1) : XEXP (x0, 0));
13191 }
13192
13193 fmt = GET_RTX_FORMAT (code);
13194 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13195 if (fmt[i] == 'e')
13196 ret += count_rtxs (XEXP (x, i));
13197 else if (fmt[i] == 'E')
13198 for (j = 0; j < XVECLEN (x, i); j++)
13199 ret += count_rtxs (XVECEXP (x, i, j));
13200
13201 return ret;
13202 }
13203
13204 /* Utility function for following routine. Called when X is part of a value
13205 being stored into last_set_value. Sets last_set_table_tick
13206 for each register mentioned. Similar to mention_regs in cse.c */
13207
13208 static void
update_table_tick(rtx x)13209 update_table_tick (rtx x)
13210 {
13211 enum rtx_code code = GET_CODE (x);
13212 const char *fmt = GET_RTX_FORMAT (code);
13213 int i, j;
13214
13215 if (code == REG)
13216 {
13217 unsigned int regno = REGNO (x);
13218 unsigned int endregno = END_REGNO (x);
13219 unsigned int r;
13220
13221 for (r = regno; r < endregno; r++)
13222 {
13223 reg_stat_type *rsp = ®_stat[r];
13224 rsp->last_set_table_tick = label_tick;
13225 }
13226
13227 return;
13228 }
13229
13230 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13231 if (fmt[i] == 'e')
13232 {
13233 /* Check for identical subexpressions. If x contains
13234 identical subexpression we only have to traverse one of
13235 them. */
13236 if (i == 0 && ARITHMETIC_P (x))
13237 {
13238 /* Note that at this point x1 has already been
13239 processed. */
13240 rtx x0 = XEXP (x, 0);
13241 rtx x1 = XEXP (x, 1);
13242
13243 /* If x0 and x1 are identical then there is no need to
13244 process x0. */
13245 if (x0 == x1)
13246 break;
13247
13248 /* If x0 is identical to a subexpression of x1 then while
13249 processing x1, x0 has already been processed. Thus we
13250 are done with x. */
13251 if (ARITHMETIC_P (x1)
13252 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13253 break;
13254
13255 /* If x1 is identical to a subexpression of x0 then we
13256 still have to process the rest of x0. */
13257 if (ARITHMETIC_P (x0)
13258 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13259 {
13260 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
13261 break;
13262 }
13263 }
13264
13265 update_table_tick (XEXP (x, i));
13266 }
13267 else if (fmt[i] == 'E')
13268 for (j = 0; j < XVECLEN (x, i); j++)
13269 update_table_tick (XVECEXP (x, i, j));
13270 }
13271
13272 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13273 are saying that the register is clobbered and we no longer know its
13274 value. If INSN is zero, don't update reg_stat[].last_set; this is
13275 only permitted with VALUE also zero and is used to invalidate the
13276 register. */
13277
13278 static void
record_value_for_reg(rtx reg,rtx_insn * insn,rtx value)13279 record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
13280 {
13281 unsigned int regno = REGNO (reg);
13282 unsigned int endregno = END_REGNO (reg);
13283 unsigned int i;
13284 reg_stat_type *rsp;
13285
13286 /* If VALUE contains REG and we have a previous value for REG, substitute
13287 the previous value. */
13288 if (value && insn && reg_overlap_mentioned_p (reg, value))
13289 {
13290 rtx tem;
13291
13292 /* Set things up so get_last_value is allowed to see anything set up to
13293 our insn. */
13294 subst_low_luid = DF_INSN_LUID (insn);
13295 tem = get_last_value (reg);
13296
13297 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13298 it isn't going to be useful and will take a lot of time to process,
13299 so just use the CLOBBER. */
13300
13301 if (tem)
13302 {
13303 if (ARITHMETIC_P (tem)
13304 && GET_CODE (XEXP (tem, 0)) == CLOBBER
13305 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
13306 tem = XEXP (tem, 0);
13307 else if (count_occurrences (value, reg, 1) >= 2)
13308 {
13309 /* If there are two or more occurrences of REG in VALUE,
13310 prevent the value from growing too much. */
13311 if (count_rtxs (tem) > param_max_last_value_rtl)
13312 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
13313 }
13314
13315 value = replace_rtx (copy_rtx (value), reg, tem);
13316 }
13317 }
13318
13319 /* For each register modified, show we don't know its value, that
13320 we don't know about its bitwise content, that its value has been
13321 updated, and that we don't know the location of the death of the
13322 register. */
13323 for (i = regno; i < endregno; i++)
13324 {
13325 rsp = ®_stat[i];
13326
13327 if (insn)
13328 rsp->last_set = insn;
13329
13330 rsp->last_set_value = 0;
13331 rsp->last_set_mode = VOIDmode;
13332 rsp->last_set_nonzero_bits = 0;
13333 rsp->last_set_sign_bit_copies = 0;
13334 rsp->last_death = 0;
13335 rsp->truncated_to_mode = VOIDmode;
13336 }
13337
13338 /* Mark registers that are being referenced in this value. */
13339 if (value)
13340 update_table_tick (value);
13341
13342 /* Now update the status of each register being set.
13343 If someone is using this register in this block, set this register
13344 to invalid since we will get confused between the two lives in this
13345 basic block. This makes using this register always invalid. In cse, we
13346 scan the table to invalidate all entries using this register, but this
13347 is too much work for us. */
13348
13349 for (i = regno; i < endregno; i++)
13350 {
13351 rsp = ®_stat[i];
13352 rsp->last_set_label = label_tick;
13353 if (!insn
13354 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
13355 rsp->last_set_invalid = 1;
13356 else
13357 rsp->last_set_invalid = 0;
13358 }
13359
13360 /* The value being assigned might refer to X (like in "x++;"). In that
13361 case, we must replace it with (clobber (const_int 0)) to prevent
13362 infinite loops. */
13363 rsp = ®_stat[regno];
13364 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
13365 {
13366 value = copy_rtx (value);
13367 if (!get_last_value_validate (&value, insn, label_tick, 1))
13368 value = 0;
13369 }
13370
13371 /* For the main register being modified, update the value, the mode, the
13372 nonzero bits, and the number of sign bit copies. */
13373
13374 rsp->last_set_value = value;
13375
13376 if (value)
13377 {
13378 machine_mode mode = GET_MODE (reg);
13379 subst_low_luid = DF_INSN_LUID (insn);
13380 rsp->last_set_mode = mode;
13381 if (GET_MODE_CLASS (mode) == MODE_INT
13382 && HWI_COMPUTABLE_MODE_P (mode))
13383 mode = nonzero_bits_mode;
13384 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
13385 rsp->last_set_sign_bit_copies
13386 = num_sign_bit_copies (value, GET_MODE (reg));
13387 }
13388 }
13389
13390 /* Called via note_stores from record_dead_and_set_regs to handle one
13391 SET or CLOBBER in an insn. DATA is the instruction in which the
13392 set is occurring. */
13393
13394 static void
record_dead_and_set_regs_1(rtx dest,const_rtx setter,void * data)13395 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
13396 {
13397 rtx_insn *record_dead_insn = (rtx_insn *) data;
13398
13399 if (GET_CODE (dest) == SUBREG)
13400 dest = SUBREG_REG (dest);
13401
13402 if (!record_dead_insn)
13403 {
13404 if (REG_P (dest))
13405 record_value_for_reg (dest, NULL, NULL_RTX);
13406 return;
13407 }
13408
13409 if (REG_P (dest))
13410 {
13411 /* If we are setting the whole register, we know its value. Otherwise
13412 show that we don't know the value. We can handle a SUBREG if it's
13413 the low part, but we must be careful with paradoxical SUBREGs on
13414 RISC architectures because we cannot strip e.g. an extension around
13415 a load and record the naked load since the RTL middle-end considers
13416 that the upper bits are defined according to LOAD_EXTEND_OP. */
13417 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
13418 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13419 else if (GET_CODE (setter) == SET
13420 && GET_CODE (SET_DEST (setter)) == SUBREG
13421 && SUBREG_REG (SET_DEST (setter)) == dest
13422 && known_le (GET_MODE_PRECISION (GET_MODE (dest)),
13423 BITS_PER_WORD)
13424 && subreg_lowpart_p (SET_DEST (setter)))
13425 record_value_for_reg (dest, record_dead_insn,
13426 WORD_REGISTER_OPERATIONS
13427 && word_register_operation_p (SET_SRC (setter))
13428 && paradoxical_subreg_p (SET_DEST (setter))
13429 ? SET_SRC (setter)
13430 : gen_lowpart (GET_MODE (dest),
13431 SET_SRC (setter)));
13432 else
13433 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
13434 }
13435 else if (MEM_P (dest)
13436 /* Ignore pushes, they clobber nothing. */
13437 && ! push_operand (dest, GET_MODE (dest)))
13438 mem_last_set = DF_INSN_LUID (record_dead_insn);
13439 }
13440
13441 /* Update the records of when each REG was most recently set or killed
13442 for the things done by INSN. This is the last thing done in processing
13443 INSN in the combiner loop.
13444
13445 We update reg_stat[], in particular fields last_set, last_set_value,
13446 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13447 last_death, and also the similar information mem_last_set (which insn
13448 most recently modified memory) and last_call_luid (which insn was the
13449 most recent subroutine call). */
13450
13451 static void
record_dead_and_set_regs(rtx_insn * insn)13452 record_dead_and_set_regs (rtx_insn *insn)
13453 {
13454 rtx link;
13455 unsigned int i;
13456
13457 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
13458 {
13459 if (REG_NOTE_KIND (link) == REG_DEAD
13460 && REG_P (XEXP (link, 0)))
13461 {
13462 unsigned int regno = REGNO (XEXP (link, 0));
13463 unsigned int endregno = END_REGNO (XEXP (link, 0));
13464
13465 for (i = regno; i < endregno; i++)
13466 {
13467 reg_stat_type *rsp;
13468
13469 rsp = ®_stat[i];
13470 rsp->last_death = insn;
13471 }
13472 }
13473 else if (REG_NOTE_KIND (link) == REG_INC)
13474 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
13475 }
13476
13477 if (CALL_P (insn))
13478 {
13479 HARD_REG_SET callee_clobbers
13480 = insn_callee_abi (insn).full_and_partial_reg_clobbers ();
13481 hard_reg_set_iterator hrsi;
13482 EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, i, hrsi)
13483 {
13484 reg_stat_type *rsp;
13485
13486 /* ??? We could try to preserve some information from the last
13487 set of register I if the call doesn't actually clobber
13488 (reg:last_set_mode I), which might be true for ABIs with
13489 partial clobbers. However, it would be difficult to
13490 update last_set_nonzero_bits and last_sign_bit_copies
13491 to account for the part of I that actually was clobbered.
13492 It wouldn't help much anyway, since we rarely see this
13493 situation before RA. */
13494 rsp = ®_stat[i];
13495 rsp->last_set_invalid = 1;
13496 rsp->last_set = insn;
13497 rsp->last_set_value = 0;
13498 rsp->last_set_mode = VOIDmode;
13499 rsp->last_set_nonzero_bits = 0;
13500 rsp->last_set_sign_bit_copies = 0;
13501 rsp->last_death = 0;
13502 rsp->truncated_to_mode = VOIDmode;
13503 }
13504
13505 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
13506
13507 /* We can't combine into a call pattern. Remember, though, that
13508 the return value register is set at this LUID. We could
13509 still replace a register with the return value from the
13510 wrong subroutine call! */
13511 note_stores (insn, record_dead_and_set_regs_1, NULL_RTX);
13512 }
13513 else
13514 note_stores (insn, record_dead_and_set_regs_1, insn);
13515 }
13516
13517 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13518 register present in the SUBREG, so for each such SUBREG go back and
13519 adjust nonzero and sign bit information of the registers that are
13520 known to have some zero/sign bits set.
13521
13522 This is needed because when combine blows the SUBREGs away, the
13523 information on zero/sign bits is lost and further combines can be
13524 missed because of that. */
13525
13526 static void
record_promoted_value(rtx_insn * insn,rtx subreg)13527 record_promoted_value (rtx_insn *insn, rtx subreg)
13528 {
13529 struct insn_link *links;
13530 rtx set;
13531 unsigned int regno = REGNO (SUBREG_REG (subreg));
13532 machine_mode mode = GET_MODE (subreg);
13533
13534 if (!HWI_COMPUTABLE_MODE_P (mode))
13535 return;
13536
13537 for (links = LOG_LINKS (insn); links;)
13538 {
13539 reg_stat_type *rsp;
13540
13541 insn = links->insn;
13542 set = single_set (insn);
13543
13544 if (! set || !REG_P (SET_DEST (set))
13545 || REGNO (SET_DEST (set)) != regno
13546 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
13547 {
13548 links = links->next;
13549 continue;
13550 }
13551
13552 rsp = ®_stat[regno];
13553 if (rsp->last_set == insn)
13554 {
13555 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
13556 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
13557 }
13558
13559 if (REG_P (SET_SRC (set)))
13560 {
13561 regno = REGNO (SET_SRC (set));
13562 links = LOG_LINKS (insn);
13563 }
13564 else
13565 break;
13566 }
13567 }
13568
13569 /* Check if X, a register, is known to contain a value already
13570 truncated to MODE. In this case we can use a subreg to refer to
13571 the truncated value even though in the generic case we would need
13572 an explicit truncation. */
13573
13574 static bool
reg_truncated_to_mode(machine_mode mode,const_rtx x)13575 reg_truncated_to_mode (machine_mode mode, const_rtx x)
13576 {
13577 reg_stat_type *rsp = ®_stat[REGNO (x)];
13578 machine_mode truncated = rsp->truncated_to_mode;
13579
13580 if (truncated == 0
13581 || rsp->truncation_label < label_tick_ebb_start)
13582 return false;
13583 if (!partial_subreg_p (mode, truncated))
13584 return true;
13585 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
13586 return true;
13587 return false;
13588 }
13589
13590 /* If X is a hard reg or a subreg record the mode that the register is
13591 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13592 able to turn a truncate into a subreg using this information. Return true
13593 if traversing X is complete. */
13594
13595 static bool
record_truncated_value(rtx x)13596 record_truncated_value (rtx x)
13597 {
13598 machine_mode truncated_mode;
13599 reg_stat_type *rsp;
13600
13601 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
13602 {
13603 machine_mode original_mode = GET_MODE (SUBREG_REG (x));
13604 truncated_mode = GET_MODE (x);
13605
13606 if (!partial_subreg_p (truncated_mode, original_mode))
13607 return true;
13608
13609 truncated_mode = GET_MODE (x);
13610 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
13611 return true;
13612
13613 x = SUBREG_REG (x);
13614 }
13615 /* ??? For hard-regs we now record everything. We might be able to
13616 optimize this using last_set_mode. */
13617 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
13618 truncated_mode = GET_MODE (x);
13619 else
13620 return false;
13621
13622 rsp = ®_stat[REGNO (x)];
13623 if (rsp->truncated_to_mode == 0
13624 || rsp->truncation_label < label_tick_ebb_start
13625 || partial_subreg_p (truncated_mode, rsp->truncated_to_mode))
13626 {
13627 rsp->truncated_to_mode = truncated_mode;
13628 rsp->truncation_label = label_tick;
13629 }
13630
13631 return true;
13632 }
13633
13634 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13635 the modes they are used in. This can help truning TRUNCATEs into
13636 SUBREGs. */
13637
13638 static void
record_truncated_values(rtx * loc,void * data ATTRIBUTE_UNUSED)13639 record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
13640 {
13641 subrtx_var_iterator::array_type array;
13642 FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
13643 if (record_truncated_value (*iter))
13644 iter.skip_subrtxes ();
13645 }
13646
13647 /* Scan X for promoted SUBREGs. For each one found,
13648 note what it implies to the registers used in it. */
13649
13650 static void
check_promoted_subreg(rtx_insn * insn,rtx x)13651 check_promoted_subreg (rtx_insn *insn, rtx x)
13652 {
13653 if (GET_CODE (x) == SUBREG
13654 && SUBREG_PROMOTED_VAR_P (x)
13655 && REG_P (SUBREG_REG (x)))
13656 record_promoted_value (insn, x);
13657 else
13658 {
13659 const char *format = GET_RTX_FORMAT (GET_CODE (x));
13660 int i, j;
13661
13662 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
13663 switch (format[i])
13664 {
13665 case 'e':
13666 check_promoted_subreg (insn, XEXP (x, i));
13667 break;
13668 case 'V':
13669 case 'E':
13670 if (XVEC (x, i) != 0)
13671 for (j = 0; j < XVECLEN (x, i); j++)
13672 check_promoted_subreg (insn, XVECEXP (x, i, j));
13673 break;
13674 }
13675 }
13676 }
13677
13678 /* Verify that all the registers and memory references mentioned in *LOC are
13679 still valid. *LOC was part of a value set in INSN when label_tick was
13680 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13681 the invalid references with (clobber (const_int 0)) and return 1. This
13682 replacement is useful because we often can get useful information about
13683 the form of a value (e.g., if it was produced by a shift that always
13684 produces -1 or 0) even though we don't know exactly what registers it
13685 was produced from. */
13686
13687 static int
get_last_value_validate(rtx * loc,rtx_insn * insn,int tick,int replace)13688 get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, int replace)
13689 {
13690 rtx x = *loc;
13691 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
13692 int len = GET_RTX_LENGTH (GET_CODE (x));
13693 int i, j;
13694
13695 if (REG_P (x))
13696 {
13697 unsigned int regno = REGNO (x);
13698 unsigned int endregno = END_REGNO (x);
13699 unsigned int j;
13700
13701 for (j = regno; j < endregno; j++)
13702 {
13703 reg_stat_type *rsp = ®_stat[j];
13704 if (rsp->last_set_invalid
13705 /* If this is a pseudo-register that was only set once and not
13706 live at the beginning of the function, it is always valid. */
13707 || (! (regno >= FIRST_PSEUDO_REGISTER
13708 && regno < reg_n_sets_max
13709 && REG_N_SETS (regno) == 1
13710 && (!REGNO_REG_SET_P
13711 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
13712 regno)))
13713 && rsp->last_set_label > tick))
13714 {
13715 if (replace)
13716 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13717 return replace;
13718 }
13719 }
13720
13721 return 1;
13722 }
13723 /* If this is a memory reference, make sure that there were no stores after
13724 it that might have clobbered the value. We don't have alias info, so we
13725 assume any store invalidates it. Moreover, we only have local UIDs, so
13726 we also assume that there were stores in the intervening basic blocks. */
13727 else if (MEM_P (x) && !MEM_READONLY_P (x)
13728 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
13729 {
13730 if (replace)
13731 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13732 return replace;
13733 }
13734
13735 for (i = 0; i < len; i++)
13736 {
13737 if (fmt[i] == 'e')
13738 {
13739 /* Check for identical subexpressions. If x contains
13740 identical subexpression we only have to traverse one of
13741 them. */
13742 if (i == 1 && ARITHMETIC_P (x))
13743 {
13744 /* Note that at this point x0 has already been checked
13745 and found valid. */
13746 rtx x0 = XEXP (x, 0);
13747 rtx x1 = XEXP (x, 1);
13748
13749 /* If x0 and x1 are identical then x is also valid. */
13750 if (x0 == x1)
13751 return 1;
13752
13753 /* If x1 is identical to a subexpression of x0 then
13754 while checking x0, x1 has already been checked. Thus
13755 it is valid and so as x. */
13756 if (ARITHMETIC_P (x0)
13757 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13758 return 1;
13759
13760 /* If x0 is identical to a subexpression of x1 then x is
13761 valid iff the rest of x1 is valid. */
13762 if (ARITHMETIC_P (x1)
13763 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13764 return
13765 get_last_value_validate (&XEXP (x1,
13766 x0 == XEXP (x1, 0) ? 1 : 0),
13767 insn, tick, replace);
13768 }
13769
13770 if (get_last_value_validate (&XEXP (x, i), insn, tick,
13771 replace) == 0)
13772 return 0;
13773 }
13774 else if (fmt[i] == 'E')
13775 for (j = 0; j < XVECLEN (x, i); j++)
13776 if (get_last_value_validate (&XVECEXP (x, i, j),
13777 insn, tick, replace) == 0)
13778 return 0;
13779 }
13780
13781 /* If we haven't found a reason for it to be invalid, it is valid. */
13782 return 1;
13783 }
13784
13785 /* Get the last value assigned to X, if known. Some registers
13786 in the value may be replaced with (clobber (const_int 0)) if their value
13787 is known longer known reliably. */
13788
13789 static rtx
get_last_value(const_rtx x)13790 get_last_value (const_rtx x)
13791 {
13792 unsigned int regno;
13793 rtx value;
13794 reg_stat_type *rsp;
13795
13796 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13797 then convert it to the desired mode. If this is a paradoxical SUBREG,
13798 we cannot predict what values the "extra" bits might have. */
13799 if (GET_CODE (x) == SUBREG
13800 && subreg_lowpart_p (x)
13801 && !paradoxical_subreg_p (x)
13802 && (value = get_last_value (SUBREG_REG (x))) != 0)
13803 return gen_lowpart (GET_MODE (x), value);
13804
13805 if (!REG_P (x))
13806 return 0;
13807
13808 regno = REGNO (x);
13809 rsp = ®_stat[regno];
13810 value = rsp->last_set_value;
13811
13812 /* If we don't have a value, or if it isn't for this basic block and
13813 it's either a hard register, set more than once, or it's a live
13814 at the beginning of the function, return 0.
13815
13816 Because if it's not live at the beginning of the function then the reg
13817 is always set before being used (is never used without being set).
13818 And, if it's set only once, and it's always set before use, then all
13819 uses must have the same last value, even if it's not from this basic
13820 block. */
13821
13822 if (value == 0
13823 || (rsp->last_set_label < label_tick_ebb_start
13824 && (regno < FIRST_PSEUDO_REGISTER
13825 || regno >= reg_n_sets_max
13826 || REG_N_SETS (regno) != 1
13827 || REGNO_REG_SET_P
13828 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
13829 return 0;
13830
13831 /* If the value was set in a later insn than the ones we are processing,
13832 we can't use it even if the register was only set once. */
13833 if (rsp->last_set_label == label_tick
13834 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
13835 return 0;
13836
13837 /* If fewer bits were set than what we are asked for now, we cannot use
13838 the value. */
13839 if (maybe_lt (GET_MODE_PRECISION (rsp->last_set_mode),
13840 GET_MODE_PRECISION (GET_MODE (x))))
13841 return 0;
13842
13843 /* If the value has all its registers valid, return it. */
13844 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
13845 return value;
13846
13847 /* Otherwise, make a copy and replace any invalid register with
13848 (clobber (const_int 0)). If that fails for some reason, return 0. */
13849
13850 value = copy_rtx (value);
13851 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
13852 return value;
13853
13854 return 0;
13855 }
13856
13857 /* Define three variables used for communication between the following
13858 routines. */
13859
13860 static unsigned int reg_dead_regno, reg_dead_endregno;
13861 static int reg_dead_flag;
13862 rtx reg_dead_reg;
13863
13864 /* Function called via note_stores from reg_dead_at_p.
13865
13866 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13867 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13868
13869 static void
reg_dead_at_p_1(rtx dest,const_rtx x,void * data ATTRIBUTE_UNUSED)13870 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
13871 {
13872 unsigned int regno, endregno;
13873
13874 if (!REG_P (dest))
13875 return;
13876
13877 regno = REGNO (dest);
13878 endregno = END_REGNO (dest);
13879 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
13880 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
13881 }
13882
13883 /* Return nonzero if REG is known to be dead at INSN.
13884
13885 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13886 referencing REG, it is dead. If we hit a SET referencing REG, it is
13887 live. Otherwise, see if it is live or dead at the start of the basic
13888 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13889 must be assumed to be always live. */
13890
13891 static int
reg_dead_at_p(rtx reg,rtx_insn * insn)13892 reg_dead_at_p (rtx reg, rtx_insn *insn)
13893 {
13894 basic_block block;
13895 unsigned int i;
13896
13897 /* Set variables for reg_dead_at_p_1. */
13898 reg_dead_regno = REGNO (reg);
13899 reg_dead_endregno = END_REGNO (reg);
13900 reg_dead_reg = reg;
13901
13902 reg_dead_flag = 0;
13903
13904 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13905 we allow the machine description to decide whether use-and-clobber
13906 patterns are OK. */
13907 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
13908 {
13909 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
13910 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
13911 return 0;
13912 }
13913
13914 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13915 beginning of basic block. */
13916 block = BLOCK_FOR_INSN (insn);
13917 for (;;)
13918 {
13919 if (INSN_P (insn))
13920 {
13921 if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
13922 return 1;
13923
13924 note_stores (insn, reg_dead_at_p_1, NULL);
13925 if (reg_dead_flag)
13926 return reg_dead_flag == 1 ? 1 : 0;
13927
13928 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
13929 return 1;
13930 }
13931
13932 if (insn == BB_HEAD (block))
13933 break;
13934
13935 insn = PREV_INSN (insn);
13936 }
13937
13938 /* Look at live-in sets for the basic block that we were in. */
13939 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
13940 if (REGNO_REG_SET_P (df_get_live_in (block), i))
13941 return 0;
13942
13943 return 1;
13944 }
13945
13946 /* Note hard registers in X that are used. */
13947
13948 static void
mark_used_regs_combine(rtx x)13949 mark_used_regs_combine (rtx x)
13950 {
13951 RTX_CODE code = GET_CODE (x);
13952 unsigned int regno;
13953 int i;
13954
13955 switch (code)
13956 {
13957 case LABEL_REF:
13958 case SYMBOL_REF:
13959 case CONST:
13960 CASE_CONST_ANY:
13961 case PC:
13962 case ADDR_VEC:
13963 case ADDR_DIFF_VEC:
13964 case ASM_INPUT:
13965 /* CC0 must die in the insn after it is set, so we don't need to take
13966 special note of it here. */
13967 case CC0:
13968 return;
13969
13970 case CLOBBER:
13971 /* If we are clobbering a MEM, mark any hard registers inside the
13972 address as used. */
13973 if (MEM_P (XEXP (x, 0)))
13974 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
13975 return;
13976
13977 case REG:
13978 regno = REGNO (x);
13979 /* A hard reg in a wide mode may really be multiple registers.
13980 If so, mark all of them just like the first. */
13981 if (regno < FIRST_PSEUDO_REGISTER)
13982 {
13983 /* None of this applies to the stack, frame or arg pointers. */
13984 if (regno == STACK_POINTER_REGNUM
13985 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13986 && regno == HARD_FRAME_POINTER_REGNUM)
13987 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13988 && regno == ARG_POINTER_REGNUM && fixed_regs[regno])
13989 || regno == FRAME_POINTER_REGNUM)
13990 return;
13991
13992 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
13993 }
13994 return;
13995
13996 case SET:
13997 {
13998 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13999 the address. */
14000 rtx testreg = SET_DEST (x);
14001
14002 while (GET_CODE (testreg) == SUBREG
14003 || GET_CODE (testreg) == ZERO_EXTRACT
14004 || GET_CODE (testreg) == STRICT_LOW_PART)
14005 testreg = XEXP (testreg, 0);
14006
14007 if (MEM_P (testreg))
14008 mark_used_regs_combine (XEXP (testreg, 0));
14009
14010 mark_used_regs_combine (SET_SRC (x));
14011 }
14012 return;
14013
14014 default:
14015 break;
14016 }
14017
14018 /* Recursively scan the operands of this expression. */
14019
14020 {
14021 const char *fmt = GET_RTX_FORMAT (code);
14022
14023 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
14024 {
14025 if (fmt[i] == 'e')
14026 mark_used_regs_combine (XEXP (x, i));
14027 else if (fmt[i] == 'E')
14028 {
14029 int j;
14030
14031 for (j = 0; j < XVECLEN (x, i); j++)
14032 mark_used_regs_combine (XVECEXP (x, i, j));
14033 }
14034 }
14035 }
14036 }
14037
14038 /* Remove register number REGNO from the dead registers list of INSN.
14039
14040 Return the note used to record the death, if there was one. */
14041
14042 rtx
remove_death(unsigned int regno,rtx_insn * insn)14043 remove_death (unsigned int regno, rtx_insn *insn)
14044 {
14045 rtx note = find_regno_note (insn, REG_DEAD, regno);
14046
14047 if (note)
14048 remove_note (insn, note);
14049
14050 return note;
14051 }
14052
14053 /* For each register (hardware or pseudo) used within expression X, if its
14054 death is in an instruction with luid between FROM_LUID (inclusive) and
14055 TO_INSN (exclusive), put a REG_DEAD note for that register in the
14056 list headed by PNOTES.
14057
14058 That said, don't move registers killed by maybe_kill_insn.
14059
14060 This is done when X is being merged by combination into TO_INSN. These
14061 notes will then be distributed as needed. */
14062
14063 static void
move_deaths(rtx x,rtx maybe_kill_insn,int from_luid,rtx_insn * to_insn,rtx * pnotes)14064 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
14065 rtx *pnotes)
14066 {
14067 const char *fmt;
14068 int len, i;
14069 enum rtx_code code = GET_CODE (x);
14070
14071 if (code == REG)
14072 {
14073 unsigned int regno = REGNO (x);
14074 rtx_insn *where_dead = reg_stat[regno].last_death;
14075
14076 /* If we do not know where the register died, it may still die between
14077 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14078 if (!where_dead || DF_INSN_LUID (where_dead) >= DF_INSN_LUID (to_insn))
14079 {
14080 rtx_insn *insn = prev_real_nondebug_insn (to_insn);
14081 while (insn
14082 && BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (to_insn)
14083 && DF_INSN_LUID (insn) >= from_luid)
14084 {
14085 if (dead_or_set_regno_p (insn, regno))
14086 {
14087 if (find_regno_note (insn, REG_DEAD, regno))
14088 where_dead = insn;
14089 break;
14090 }
14091
14092 insn = prev_real_nondebug_insn (insn);
14093 }
14094 }
14095
14096 /* Don't move the register if it gets killed in between from and to. */
14097 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
14098 && ! reg_referenced_p (x, maybe_kill_insn))
14099 return;
14100
14101 if (where_dead
14102 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
14103 && DF_INSN_LUID (where_dead) >= from_luid
14104 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
14105 {
14106 rtx note = remove_death (regno, where_dead);
14107
14108 /* It is possible for the call above to return 0. This can occur
14109 when last_death points to I2 or I1 that we combined with.
14110 In that case make a new note.
14111
14112 We must also check for the case where X is a hard register
14113 and NOTE is a death note for a range of hard registers
14114 including X. In that case, we must put REG_DEAD notes for
14115 the remaining registers in place of NOTE. */
14116
14117 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
14118 && partial_subreg_p (GET_MODE (x), GET_MODE (XEXP (note, 0))))
14119 {
14120 unsigned int deadregno = REGNO (XEXP (note, 0));
14121 unsigned int deadend = END_REGNO (XEXP (note, 0));
14122 unsigned int ourend = END_REGNO (x);
14123 unsigned int i;
14124
14125 for (i = deadregno; i < deadend; i++)
14126 if (i < regno || i >= ourend)
14127 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
14128 }
14129
14130 /* If we didn't find any note, or if we found a REG_DEAD note that
14131 covers only part of the given reg, and we have a multi-reg hard
14132 register, then to be safe we must check for REG_DEAD notes
14133 for each register other than the first. They could have
14134 their own REG_DEAD notes lying around. */
14135 else if ((note == 0
14136 || (note != 0
14137 && partial_subreg_p (GET_MODE (XEXP (note, 0)),
14138 GET_MODE (x))))
14139 && regno < FIRST_PSEUDO_REGISTER
14140 && REG_NREGS (x) > 1)
14141 {
14142 unsigned int ourend = END_REGNO (x);
14143 unsigned int i, offset;
14144 rtx oldnotes = 0;
14145
14146 if (note)
14147 offset = hard_regno_nregs (regno, GET_MODE (XEXP (note, 0)));
14148 else
14149 offset = 1;
14150
14151 for (i = regno + offset; i < ourend; i++)
14152 move_deaths (regno_reg_rtx[i],
14153 maybe_kill_insn, from_luid, to_insn, &oldnotes);
14154 }
14155
14156 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
14157 {
14158 XEXP (note, 1) = *pnotes;
14159 *pnotes = note;
14160 }
14161 else
14162 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
14163 }
14164
14165 return;
14166 }
14167
14168 else if (GET_CODE (x) == SET)
14169 {
14170 rtx dest = SET_DEST (x);
14171
14172 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
14173
14174 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14175 that accesses one word of a multi-word item, some
14176 piece of everything register in the expression is used by
14177 this insn, so remove any old death. */
14178 /* ??? So why do we test for equality of the sizes? */
14179
14180 if (GET_CODE (dest) == ZERO_EXTRACT
14181 || GET_CODE (dest) == STRICT_LOW_PART
14182 || (GET_CODE (dest) == SUBREG
14183 && !read_modify_subreg_p (dest)))
14184 {
14185 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
14186 return;
14187 }
14188
14189 /* If this is some other SUBREG, we know it replaces the entire
14190 value, so use that as the destination. */
14191 if (GET_CODE (dest) == SUBREG)
14192 dest = SUBREG_REG (dest);
14193
14194 /* If this is a MEM, adjust deaths of anything used in the address.
14195 For a REG (the only other possibility), the entire value is
14196 being replaced so the old value is not used in this insn. */
14197
14198 if (MEM_P (dest))
14199 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
14200 to_insn, pnotes);
14201 return;
14202 }
14203
14204 else if (GET_CODE (x) == CLOBBER)
14205 return;
14206
14207 len = GET_RTX_LENGTH (code);
14208 fmt = GET_RTX_FORMAT (code);
14209
14210 for (i = 0; i < len; i++)
14211 {
14212 if (fmt[i] == 'E')
14213 {
14214 int j;
14215 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
14216 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
14217 to_insn, pnotes);
14218 }
14219 else if (fmt[i] == 'e')
14220 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
14221 }
14222 }
14223
14224 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14225 pattern of an insn. X must be a REG. */
14226
14227 static int
reg_bitfield_target_p(rtx x,rtx body)14228 reg_bitfield_target_p (rtx x, rtx body)
14229 {
14230 int i;
14231
14232 if (GET_CODE (body) == SET)
14233 {
14234 rtx dest = SET_DEST (body);
14235 rtx target;
14236 unsigned int regno, tregno, endregno, endtregno;
14237
14238 if (GET_CODE (dest) == ZERO_EXTRACT)
14239 target = XEXP (dest, 0);
14240 else if (GET_CODE (dest) == STRICT_LOW_PART)
14241 target = SUBREG_REG (XEXP (dest, 0));
14242 else
14243 return 0;
14244
14245 if (GET_CODE (target) == SUBREG)
14246 target = SUBREG_REG (target);
14247
14248 if (!REG_P (target))
14249 return 0;
14250
14251 tregno = REGNO (target), regno = REGNO (x);
14252 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
14253 return target == x;
14254
14255 endtregno = end_hard_regno (GET_MODE (target), tregno);
14256 endregno = end_hard_regno (GET_MODE (x), regno);
14257
14258 return endregno > tregno && regno < endtregno;
14259 }
14260
14261 else if (GET_CODE (body) == PARALLEL)
14262 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
14263 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
14264 return 1;
14265
14266 return 0;
14267 }
14268
14269 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14270 as appropriate. I3 and I2 are the insns resulting from the combination
14271 insns including FROM (I2 may be zero).
14272
14273 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14274 not need REG_DEAD notes because they are being substituted for. This
14275 saves searching in the most common cases.
14276
14277 Each note in the list is either ignored or placed on some insns, depending
14278 on the type of note. */
14279
14280 static void
distribute_notes(rtx notes,rtx_insn * from_insn,rtx_insn * i3,rtx_insn * i2,rtx elim_i2,rtx elim_i1,rtx elim_i0)14281 distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
14282 rtx elim_i2, rtx elim_i1, rtx elim_i0)
14283 {
14284 rtx note, next_note;
14285 rtx tem_note;
14286 rtx_insn *tem_insn;
14287
14288 for (note = notes; note; note = next_note)
14289 {
14290 rtx_insn *place = 0, *place2 = 0;
14291
14292 next_note = XEXP (note, 1);
14293 switch (REG_NOTE_KIND (note))
14294 {
14295 case REG_BR_PROB:
14296 case REG_BR_PRED:
14297 /* Doesn't matter much where we put this, as long as it's somewhere.
14298 It is preferable to keep these notes on branches, which is most
14299 likely to be i3. */
14300 place = i3;
14301 break;
14302
14303 case REG_NON_LOCAL_GOTO:
14304 if (JUMP_P (i3))
14305 place = i3;
14306 else
14307 {
14308 gcc_assert (i2 && JUMP_P (i2));
14309 place = i2;
14310 }
14311 break;
14312
14313 case REG_EH_REGION:
14314 /* These notes must remain with the call or trapping instruction. */
14315 if (CALL_P (i3))
14316 place = i3;
14317 else if (i2 && CALL_P (i2))
14318 place = i2;
14319 else
14320 {
14321 gcc_assert (cfun->can_throw_non_call_exceptions);
14322 if (may_trap_p (i3))
14323 place = i3;
14324 else if (i2 && may_trap_p (i2))
14325 place = i2;
14326 /* ??? Otherwise assume we've combined things such that we
14327 can now prove that the instructions can't trap. Drop the
14328 note in this case. */
14329 }
14330 break;
14331
14332 case REG_ARGS_SIZE:
14333 /* ??? How to distribute between i3-i1. Assume i3 contains the
14334 entire adjustment. Assert i3 contains at least some adjust. */
14335 if (!noop_move_p (i3))
14336 {
14337 poly_int64 old_size, args_size = get_args_size (note);
14338 /* fixup_args_size_notes looks at REG_NORETURN note,
14339 so ensure the note is placed there first. */
14340 if (CALL_P (i3))
14341 {
14342 rtx *np;
14343 for (np = &next_note; *np; np = &XEXP (*np, 1))
14344 if (REG_NOTE_KIND (*np) == REG_NORETURN)
14345 {
14346 rtx n = *np;
14347 *np = XEXP (n, 1);
14348 XEXP (n, 1) = REG_NOTES (i3);
14349 REG_NOTES (i3) = n;
14350 break;
14351 }
14352 }
14353 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
14354 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14355 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14356 gcc_assert (maybe_ne (old_size, args_size)
14357 || (CALL_P (i3)
14358 && !ACCUMULATE_OUTGOING_ARGS
14359 && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
14360 }
14361 break;
14362
14363 case REG_NORETURN:
14364 case REG_SETJMP:
14365 case REG_TM:
14366 case REG_CALL_DECL:
14367 case REG_CALL_NOCF_CHECK:
14368 /* These notes must remain with the call. It should not be
14369 possible for both I2 and I3 to be a call. */
14370 if (CALL_P (i3))
14371 place = i3;
14372 else
14373 {
14374 gcc_assert (i2 && CALL_P (i2));
14375 place = i2;
14376 }
14377 break;
14378
14379 case REG_UNUSED:
14380 /* Any clobbers for i3 may still exist, and so we must process
14381 REG_UNUSED notes from that insn.
14382
14383 Any clobbers from i2 or i1 can only exist if they were added by
14384 recog_for_combine. In that case, recog_for_combine created the
14385 necessary REG_UNUSED notes. Trying to keep any original
14386 REG_UNUSED notes from these insns can cause incorrect output
14387 if it is for the same register as the original i3 dest.
14388 In that case, we will notice that the register is set in i3,
14389 and then add a REG_UNUSED note for the destination of i3, which
14390 is wrong. However, it is possible to have REG_UNUSED notes from
14391 i2 or i1 for register which were both used and clobbered, so
14392 we keep notes from i2 or i1 if they will turn into REG_DEAD
14393 notes. */
14394
14395 /* If this register is set or clobbered between FROM_INSN and I3,
14396 we should not create a note for it. */
14397 if (reg_set_between_p (XEXP (note, 0), from_insn, i3))
14398 break;
14399
14400 /* If this register is set or clobbered in I3, put the note there
14401 unless there is one already. */
14402 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
14403 {
14404 if (from_insn != i3)
14405 break;
14406
14407 if (! (REG_P (XEXP (note, 0))
14408 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
14409 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
14410 place = i3;
14411 }
14412 /* Otherwise, if this register is used by I3, then this register
14413 now dies here, so we must put a REG_DEAD note here unless there
14414 is one already. */
14415 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
14416 && ! (REG_P (XEXP (note, 0))
14417 ? find_regno_note (i3, REG_DEAD,
14418 REGNO (XEXP (note, 0)))
14419 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
14420 {
14421 PUT_REG_NOTE_KIND (note, REG_DEAD);
14422 place = i3;
14423 }
14424
14425 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14426 but we can't tell which at this point. We must reset any
14427 expectations we had about the value that was previously
14428 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14429 and, if appropriate, restore its previous value, but we
14430 don't have enough information for that at this point. */
14431 else
14432 {
14433 record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14434
14435 /* Otherwise, if this register is now referenced in i2
14436 then the register used to be modified in one of the
14437 original insns. If it was i3 (say, in an unused
14438 parallel), it's now completely gone, so the note can
14439 be discarded. But if it was modified in i2, i1 or i0
14440 and we still reference it in i2, then we're
14441 referencing the previous value, and since the
14442 register was modified and REG_UNUSED, we know that
14443 the previous value is now dead. So, if we only
14444 reference the register in i2, we change the note to
14445 REG_DEAD, to reflect the previous value. However, if
14446 we're also setting or clobbering the register as
14447 scratch, we know (because the register was not
14448 referenced in i3) that it's unused, just as it was
14449 unused before, and we place the note in i2. */
14450 if (from_insn != i3 && i2 && INSN_P (i2)
14451 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14452 {
14453 if (!reg_set_p (XEXP (note, 0), PATTERN (i2)))
14454 PUT_REG_NOTE_KIND (note, REG_DEAD);
14455 if (! (REG_P (XEXP (note, 0))
14456 ? find_regno_note (i2, REG_NOTE_KIND (note),
14457 REGNO (XEXP (note, 0)))
14458 : find_reg_note (i2, REG_NOTE_KIND (note),
14459 XEXP (note, 0))))
14460 place = i2;
14461 }
14462 }
14463
14464 break;
14465
14466 case REG_EQUAL:
14467 case REG_EQUIV:
14468 case REG_NOALIAS:
14469 /* These notes say something about results of an insn. We can
14470 only support them if they used to be on I3 in which case they
14471 remain on I3. Otherwise they are ignored.
14472
14473 If the note refers to an expression that is not a constant, we
14474 must also ignore the note since we cannot tell whether the
14475 equivalence is still true. It might be possible to do
14476 slightly better than this (we only have a problem if I2DEST
14477 or I1DEST is present in the expression), but it doesn't
14478 seem worth the trouble. */
14479
14480 if (from_insn == i3
14481 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
14482 place = i3;
14483 break;
14484
14485 case REG_INC:
14486 /* These notes say something about how a register is used. They must
14487 be present on any use of the register in I2 or I3. */
14488 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
14489 place = i3;
14490
14491 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
14492 {
14493 if (place)
14494 place2 = i2;
14495 else
14496 place = i2;
14497 }
14498 break;
14499
14500 case REG_LABEL_TARGET:
14501 case REG_LABEL_OPERAND:
14502 /* This can show up in several ways -- either directly in the
14503 pattern, or hidden off in the constant pool with (or without?)
14504 a REG_EQUAL note. */
14505 /* ??? Ignore the without-reg_equal-note problem for now. */
14506 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
14507 || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
14508 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14509 && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
14510 place = i3;
14511
14512 if (i2
14513 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
14514 || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
14515 && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14516 && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
14517 {
14518 if (place)
14519 place2 = i2;
14520 else
14521 place = i2;
14522 }
14523
14524 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14525 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14526 there. */
14527 if (place && JUMP_P (place)
14528 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14529 && (JUMP_LABEL (place) == NULL
14530 || JUMP_LABEL (place) == XEXP (note, 0)))
14531 {
14532 rtx label = JUMP_LABEL (place);
14533
14534 if (!label)
14535 JUMP_LABEL (place) = XEXP (note, 0);
14536 else if (LABEL_P (label))
14537 LABEL_NUSES (label)--;
14538 }
14539
14540 if (place2 && JUMP_P (place2)
14541 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14542 && (JUMP_LABEL (place2) == NULL
14543 || JUMP_LABEL (place2) == XEXP (note, 0)))
14544 {
14545 rtx label = JUMP_LABEL (place2);
14546
14547 if (!label)
14548 JUMP_LABEL (place2) = XEXP (note, 0);
14549 else if (LABEL_P (label))
14550 LABEL_NUSES (label)--;
14551 place2 = 0;
14552 }
14553 break;
14554
14555 case REG_NONNEG:
14556 /* This note says something about the value of a register prior
14557 to the execution of an insn. It is too much trouble to see
14558 if the note is still correct in all situations. It is better
14559 to simply delete it. */
14560 break;
14561
14562 case REG_DEAD:
14563 /* If we replaced the right hand side of FROM_INSN with a
14564 REG_EQUAL note, the original use of the dying register
14565 will not have been combined into I3 and I2. In such cases,
14566 FROM_INSN is guaranteed to be the first of the combined
14567 instructions, so we simply need to search back before
14568 FROM_INSN for the previous use or set of this register,
14569 then alter the notes there appropriately.
14570
14571 If the register is used as an input in I3, it dies there.
14572 Similarly for I2, if it is nonzero and adjacent to I3.
14573
14574 If the register is not used as an input in either I3 or I2
14575 and it is not one of the registers we were supposed to eliminate,
14576 there are two possibilities. We might have a non-adjacent I2
14577 or we might have somehow eliminated an additional register
14578 from a computation. For example, we might have had A & B where
14579 we discover that B will always be zero. In this case we will
14580 eliminate the reference to A.
14581
14582 In both cases, we must search to see if we can find a previous
14583 use of A and put the death note there. */
14584
14585 if (from_insn
14586 && from_insn == i2mod
14587 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
14588 tem_insn = from_insn;
14589 else
14590 {
14591 if (from_insn
14592 && CALL_P (from_insn)
14593 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
14594 place = from_insn;
14595 else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
14596 {
14597 /* If the new I2 sets the same register that is marked
14598 dead in the note, we do not in general know where to
14599 put the note. One important case we _can_ handle is
14600 when the note comes from I3. */
14601 if (from_insn == i3)
14602 place = i3;
14603 else
14604 break;
14605 }
14606 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14607 place = i3;
14608 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
14609 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14610 place = i2;
14611 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
14612 && !(i2mod
14613 && reg_overlap_mentioned_p (XEXP (note, 0),
14614 i2mod_old_rhs)))
14615 || rtx_equal_p (XEXP (note, 0), elim_i1)
14616 || rtx_equal_p (XEXP (note, 0), elim_i0))
14617 break;
14618 tem_insn = i3;
14619 }
14620
14621 if (place == 0)
14622 {
14623 basic_block bb = this_basic_block;
14624
14625 for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
14626 {
14627 if (!NONDEBUG_INSN_P (tem_insn))
14628 {
14629 if (tem_insn == BB_HEAD (bb))
14630 break;
14631 continue;
14632 }
14633
14634 /* If the register is being set at TEM_INSN, see if that is all
14635 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14636 into a REG_UNUSED note instead. Don't delete sets to
14637 global register vars. */
14638 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
14639 || !global_regs[REGNO (XEXP (note, 0))])
14640 && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
14641 {
14642 rtx set = single_set (tem_insn);
14643 rtx inner_dest = 0;
14644 rtx_insn *cc0_setter = NULL;
14645
14646 if (set != 0)
14647 for (inner_dest = SET_DEST (set);
14648 (GET_CODE (inner_dest) == STRICT_LOW_PART
14649 || GET_CODE (inner_dest) == SUBREG
14650 || GET_CODE (inner_dest) == ZERO_EXTRACT);
14651 inner_dest = XEXP (inner_dest, 0))
14652 ;
14653
14654 /* Verify that it was the set, and not a clobber that
14655 modified the register.
14656
14657 CC0 targets must be careful to maintain setter/user
14658 pairs. If we cannot delete the setter due to side
14659 effects, mark the user with an UNUSED note instead
14660 of deleting it. */
14661
14662 if (set != 0 && ! side_effects_p (SET_SRC (set))
14663 && rtx_equal_p (XEXP (note, 0), inner_dest)
14664 && (!HAVE_cc0
14665 || (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
14666 || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL
14667 && sets_cc0_p (PATTERN (cc0_setter)) > 0))))
14668 {
14669 /* Move the notes and links of TEM_INSN elsewhere.
14670 This might delete other dead insns recursively.
14671 First set the pattern to something that won't use
14672 any register. */
14673 rtx old_notes = REG_NOTES (tem_insn);
14674
14675 PATTERN (tem_insn) = pc_rtx;
14676 REG_NOTES (tem_insn) = NULL;
14677
14678 distribute_notes (old_notes, tem_insn, tem_insn, NULL,
14679 NULL_RTX, NULL_RTX, NULL_RTX);
14680 distribute_links (LOG_LINKS (tem_insn));
14681
14682 unsigned int regno = REGNO (XEXP (note, 0));
14683 reg_stat_type *rsp = ®_stat[regno];
14684 if (rsp->last_set == tem_insn)
14685 record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14686
14687 SET_INSN_DELETED (tem_insn);
14688 if (tem_insn == i2)
14689 i2 = NULL;
14690
14691 /* Delete the setter too. */
14692 if (cc0_setter)
14693 {
14694 PATTERN (cc0_setter) = pc_rtx;
14695 old_notes = REG_NOTES (cc0_setter);
14696 REG_NOTES (cc0_setter) = NULL;
14697
14698 distribute_notes (old_notes, cc0_setter,
14699 cc0_setter, NULL,
14700 NULL_RTX, NULL_RTX, NULL_RTX);
14701 distribute_links (LOG_LINKS (cc0_setter));
14702
14703 SET_INSN_DELETED (cc0_setter);
14704 if (cc0_setter == i2)
14705 i2 = NULL;
14706 }
14707 }
14708 else
14709 {
14710 PUT_REG_NOTE_KIND (note, REG_UNUSED);
14711
14712 /* If there isn't already a REG_UNUSED note, put one
14713 here. Do not place a REG_DEAD note, even if
14714 the register is also used here; that would not
14715 match the algorithm used in lifetime analysis
14716 and can cause the consistency check in the
14717 scheduler to fail. */
14718 if (! find_regno_note (tem_insn, REG_UNUSED,
14719 REGNO (XEXP (note, 0))))
14720 place = tem_insn;
14721 break;
14722 }
14723 }
14724 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
14725 || (CALL_P (tem_insn)
14726 && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
14727 {
14728 place = tem_insn;
14729
14730 /* If we are doing a 3->2 combination, and we have a
14731 register which formerly died in i3 and was not used
14732 by i2, which now no longer dies in i3 and is used in
14733 i2 but does not die in i2, and place is between i2
14734 and i3, then we may need to move a link from place to
14735 i2. */
14736 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
14737 && from_insn
14738 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
14739 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14740 {
14741 struct insn_link *links = LOG_LINKS (place);
14742 LOG_LINKS (place) = NULL;
14743 distribute_links (links);
14744 }
14745 break;
14746 }
14747
14748 if (tem_insn == BB_HEAD (bb))
14749 break;
14750 }
14751
14752 }
14753
14754 /* If the register is set or already dead at PLACE, we needn't do
14755 anything with this note if it is still a REG_DEAD note.
14756 We check here if it is set at all, not if is it totally replaced,
14757 which is what `dead_or_set_p' checks, so also check for it being
14758 set partially. */
14759
14760 if (place && REG_NOTE_KIND (note) == REG_DEAD)
14761 {
14762 unsigned int regno = REGNO (XEXP (note, 0));
14763 reg_stat_type *rsp = ®_stat[regno];
14764
14765 if (dead_or_set_p (place, XEXP (note, 0))
14766 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
14767 {
14768 /* Unless the register previously died in PLACE, clear
14769 last_death. [I no longer understand why this is
14770 being done.] */
14771 if (rsp->last_death != place)
14772 rsp->last_death = 0;
14773 place = 0;
14774 }
14775 else
14776 rsp->last_death = place;
14777
14778 /* If this is a death note for a hard reg that is occupying
14779 multiple registers, ensure that we are still using all
14780 parts of the object. If we find a piece of the object
14781 that is unused, we must arrange for an appropriate REG_DEAD
14782 note to be added for it. However, we can't just emit a USE
14783 and tag the note to it, since the register might actually
14784 be dead; so we recourse, and the recursive call then finds
14785 the previous insn that used this register. */
14786
14787 if (place && REG_NREGS (XEXP (note, 0)) > 1)
14788 {
14789 unsigned int endregno = END_REGNO (XEXP (note, 0));
14790 bool all_used = true;
14791 unsigned int i;
14792
14793 for (i = regno; i < endregno; i++)
14794 if ((! refers_to_regno_p (i, PATTERN (place))
14795 && ! find_regno_fusage (place, USE, i))
14796 || dead_or_set_regno_p (place, i))
14797 {
14798 all_used = false;
14799 break;
14800 }
14801
14802 if (! all_used)
14803 {
14804 /* Put only REG_DEAD notes for pieces that are
14805 not already dead or set. */
14806
14807 for (i = regno; i < endregno;
14808 i += hard_regno_nregs (i, reg_raw_mode[i]))
14809 {
14810 rtx piece = regno_reg_rtx[i];
14811 basic_block bb = this_basic_block;
14812
14813 if (! dead_or_set_p (place, piece)
14814 && ! reg_bitfield_target_p (piece,
14815 PATTERN (place)))
14816 {
14817 rtx new_note = alloc_reg_note (REG_DEAD, piece,
14818 NULL_RTX);
14819
14820 distribute_notes (new_note, place, place,
14821 NULL, NULL_RTX, NULL_RTX,
14822 NULL_RTX);
14823 }
14824 else if (! refers_to_regno_p (i, PATTERN (place))
14825 && ! find_regno_fusage (place, USE, i))
14826 for (tem_insn = PREV_INSN (place); ;
14827 tem_insn = PREV_INSN (tem_insn))
14828 {
14829 if (!NONDEBUG_INSN_P (tem_insn))
14830 {
14831 if (tem_insn == BB_HEAD (bb))
14832 break;
14833 continue;
14834 }
14835 if (dead_or_set_p (tem_insn, piece)
14836 || reg_bitfield_target_p (piece,
14837 PATTERN (tem_insn)))
14838 {
14839 add_reg_note (tem_insn, REG_UNUSED, piece);
14840 break;
14841 }
14842 }
14843 }
14844
14845 place = 0;
14846 }
14847 }
14848 }
14849 break;
14850
14851 default:
14852 /* Any other notes should not be present at this point in the
14853 compilation. */
14854 gcc_unreachable ();
14855 }
14856
14857 if (place)
14858 {
14859 XEXP (note, 1) = REG_NOTES (place);
14860 REG_NOTES (place) = note;
14861
14862 /* Set added_notes_insn to the earliest insn we added a note to. */
14863 if (added_notes_insn == 0
14864 || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place))
14865 added_notes_insn = place;
14866 }
14867
14868 if (place2)
14869 {
14870 add_shallow_copy_of_reg_note (place2, note);
14871
14872 /* Set added_notes_insn to the earliest insn we added a note to. */
14873 if (added_notes_insn == 0
14874 || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place2))
14875 added_notes_insn = place2;
14876 }
14877 }
14878 }
14879
14880 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14881 I3, I2, and I1 to new locations. This is also called to add a link
14882 pointing at I3 when I3's destination is changed. */
14883
14884 static void
distribute_links(struct insn_link * links)14885 distribute_links (struct insn_link *links)
14886 {
14887 struct insn_link *link, *next_link;
14888
14889 for (link = links; link; link = next_link)
14890 {
14891 rtx_insn *place = 0;
14892 rtx_insn *insn;
14893 rtx set, reg;
14894
14895 next_link = link->next;
14896
14897 /* If the insn that this link points to is a NOTE, ignore it. */
14898 if (NOTE_P (link->insn))
14899 continue;
14900
14901 set = 0;
14902 rtx pat = PATTERN (link->insn);
14903 if (GET_CODE (pat) == SET)
14904 set = pat;
14905 else if (GET_CODE (pat) == PARALLEL)
14906 {
14907 int i;
14908 for (i = 0; i < XVECLEN (pat, 0); i++)
14909 {
14910 set = XVECEXP (pat, 0, i);
14911 if (GET_CODE (set) != SET)
14912 continue;
14913
14914 reg = SET_DEST (set);
14915 while (GET_CODE (reg) == ZERO_EXTRACT
14916 || GET_CODE (reg) == STRICT_LOW_PART
14917 || GET_CODE (reg) == SUBREG)
14918 reg = XEXP (reg, 0);
14919
14920 if (!REG_P (reg))
14921 continue;
14922
14923 if (REGNO (reg) == link->regno)
14924 break;
14925 }
14926 if (i == XVECLEN (pat, 0))
14927 continue;
14928 }
14929 else
14930 continue;
14931
14932 reg = SET_DEST (set);
14933
14934 while (GET_CODE (reg) == ZERO_EXTRACT
14935 || GET_CODE (reg) == STRICT_LOW_PART
14936 || GET_CODE (reg) == SUBREG)
14937 reg = XEXP (reg, 0);
14938
14939 if (reg == pc_rtx)
14940 continue;
14941
14942 /* A LOG_LINK is defined as being placed on the first insn that uses
14943 a register and points to the insn that sets the register. Start
14944 searching at the next insn after the target of the link and stop
14945 when we reach a set of the register or the end of the basic block.
14946
14947 Note that this correctly handles the link that used to point from
14948 I3 to I2. Also note that not much searching is typically done here
14949 since most links don't point very far away. */
14950
14951 for (insn = NEXT_INSN (link->insn);
14952 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
14953 || BB_HEAD (this_basic_block->next_bb) != insn));
14954 insn = NEXT_INSN (insn))
14955 if (DEBUG_INSN_P (insn))
14956 continue;
14957 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
14958 {
14959 if (reg_referenced_p (reg, PATTERN (insn)))
14960 place = insn;
14961 break;
14962 }
14963 else if (CALL_P (insn)
14964 && find_reg_fusage (insn, USE, reg))
14965 {
14966 place = insn;
14967 break;
14968 }
14969 else if (INSN_P (insn) && reg_set_p (reg, insn))
14970 break;
14971
14972 /* If we found a place to put the link, place it there unless there
14973 is already a link to the same insn as LINK at that point. */
14974
14975 if (place)
14976 {
14977 struct insn_link *link2;
14978
14979 FOR_EACH_LOG_LINK (link2, place)
14980 if (link2->insn == link->insn && link2->regno == link->regno)
14981 break;
14982
14983 if (link2 == NULL)
14984 {
14985 link->next = LOG_LINKS (place);
14986 LOG_LINKS (place) = link;
14987
14988 /* Set added_links_insn to the earliest insn we added a
14989 link to. */
14990 if (added_links_insn == 0
14991 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
14992 added_links_insn = place;
14993 }
14994 }
14995 }
14996 }
14997
14998 /* Check for any register or memory mentioned in EQUIV that is not
14999 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
15000 of EXPR where some registers may have been replaced by constants. */
15001
15002 static bool
unmentioned_reg_p(rtx equiv,rtx expr)15003 unmentioned_reg_p (rtx equiv, rtx expr)
15004 {
15005 subrtx_iterator::array_type array;
15006 FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
15007 {
15008 const_rtx x = *iter;
15009 if ((REG_P (x) || MEM_P (x))
15010 && !reg_mentioned_p (x, expr))
15011 return true;
15012 }
15013 return false;
15014 }
15015
15016 DEBUG_FUNCTION void
dump_combine_stats(FILE * file)15017 dump_combine_stats (FILE *file)
15018 {
15019 fprintf
15020 (file,
15021 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
15022 combine_attempts, combine_merges, combine_extras, combine_successes);
15023 }
15024
15025 void
dump_combine_total_stats(FILE * file)15026 dump_combine_total_stats (FILE *file)
15027 {
15028 fprintf
15029 (file,
15030 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
15031 total_attempts, total_merges, total_extras, total_successes);
15032 }
15033
15034 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15035 the reg-to-reg copy can usefully combine with later instructions, but we
15036 do not want to combine the hard reg into later instructions, for that
15037 restricts register allocation. */
15038 static void
make_more_copies(void)15039 make_more_copies (void)
15040 {
15041 basic_block bb;
15042
15043 FOR_EACH_BB_FN (bb, cfun)
15044 {
15045 rtx_insn *insn;
15046
15047 FOR_BB_INSNS (bb, insn)
15048 {
15049 if (!NONDEBUG_INSN_P (insn))
15050 continue;
15051
15052 rtx set = single_set (insn);
15053 if (!set)
15054 continue;
15055
15056 rtx dest = SET_DEST (set);
15057 if (!(REG_P (dest) && !HARD_REGISTER_P (dest)))
15058 continue;
15059
15060 rtx src = SET_SRC (set);
15061 if (!(REG_P (src) && HARD_REGISTER_P (src)))
15062 continue;
15063 if (TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)))
15064 continue;
15065
15066 rtx new_reg = gen_reg_rtx (GET_MODE (dest));
15067 rtx_insn *new_insn = gen_move_insn (new_reg, src);
15068 SET_SRC (set) = new_reg;
15069 emit_insn_before (new_insn, insn);
15070 df_insn_rescan (insn);
15071 }
15072 }
15073 }
15074
15075 /* Try combining insns through substitution. */
15076 static unsigned int
rest_of_handle_combine(void)15077 rest_of_handle_combine (void)
15078 {
15079 make_more_copies ();
15080
15081 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
15082 df_note_add_problem ();
15083 df_analyze ();
15084
15085 regstat_init_n_sets_and_refs ();
15086 reg_n_sets_max = max_reg_num ();
15087
15088 int rebuild_jump_labels_after_combine
15089 = combine_instructions (get_insns (), max_reg_num ());
15090
15091 /* Combining insns may have turned an indirect jump into a
15092 direct jump. Rebuild the JUMP_LABEL fields of jumping
15093 instructions. */
15094 if (rebuild_jump_labels_after_combine)
15095 {
15096 if (dom_info_available_p (CDI_DOMINATORS))
15097 free_dominance_info (CDI_DOMINATORS);
15098 timevar_push (TV_JUMP);
15099 rebuild_jump_labels (get_insns ());
15100 cleanup_cfg (0);
15101 timevar_pop (TV_JUMP);
15102 }
15103
15104 regstat_free_n_sets_and_refs ();
15105 return 0;
15106 }
15107
15108 namespace {
15109
15110 const pass_data pass_data_combine =
15111 {
15112 RTL_PASS, /* type */
15113 "combine", /* name */
15114 OPTGROUP_NONE, /* optinfo_flags */
15115 TV_COMBINE, /* tv_id */
15116 PROP_cfglayout, /* properties_required */
15117 0, /* properties_provided */
15118 0, /* properties_destroyed */
15119 0, /* todo_flags_start */
15120 TODO_df_finish, /* todo_flags_finish */
15121 };
15122
15123 class pass_combine : public rtl_opt_pass
15124 {
15125 public:
pass_combine(gcc::context * ctxt)15126 pass_combine (gcc::context *ctxt)
15127 : rtl_opt_pass (pass_data_combine, ctxt)
15128 {}
15129
15130 /* opt_pass methods: */
gate(function *)15131 virtual bool gate (function *) { return (optimize > 0); }
execute(function *)15132 virtual unsigned int execute (function *)
15133 {
15134 return rest_of_handle_combine ();
15135 }
15136
15137 }; // class pass_combine
15138
15139 } // anon namespace
15140
15141 rtl_opt_pass *
make_pass_combine(gcc::context * ctxt)15142 make_pass_combine (gcc::context *ctxt)
15143 {
15144 return new pass_combine (ctxt);
15145 }
15146