1 /* Definition of RISC-V target for GNU compiler. 2 Copyright (C) 2011-2020 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman (andrew@sifive.com). 4 Based on MIPS target for GNU compiler. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #ifndef GCC_RISCV_H 23 #define GCC_RISCV_H 24 25 #include "config/riscv/riscv-opts.h" 26 27 /* Target CPU builtins. */ 28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile) 29 30 /* Target CPU versions for D. */ 31 #define TARGET_D_CPU_VERSIONS riscv_d_target_versions 32 33 /* Default target_flags if no switches are specified */ 34 35 #ifndef TARGET_DEFAULT 36 #define TARGET_DEFAULT 0 37 #endif 38 39 #ifndef RISCV_TUNE_STRING_DEFAULT 40 #define RISCV_TUNE_STRING_DEFAULT "rocket" 41 #endif 42 43 /* Support for a compile-time default CPU, et cetera. The rules are: 44 --with-arch is ignored if -march is specified. 45 --with-abi is ignored if -mabi is specified. 46 --with-tune is ignored if -mtune is specified. */ 47 #define OPTION_DEFAULT_SPECS \ 48 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 49 {"arch", "%{!march=*:-march=%(VALUE)}" }, \ 50 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 51 52 #ifdef IN_LIBGCC2 53 #undef TARGET_64BIT 54 /* Make this compile time constant for libgcc2 */ 55 #define TARGET_64BIT (__riscv_xlen == 64) 56 #endif /* IN_LIBGCC2 */ 57 58 #undef ASM_SPEC 59 #define ASM_SPEC "\ 60 %(subtarget_asm_debugging_spec) \ 61 %{" FPIE_OR_FPIC_SPEC ":-fpic} \ 62 %{march=*} \ 63 %{mabi=*} \ 64 %(subtarget_asm_spec)" 65 66 #define TARGET_DEFAULT_CMODEL CM_MEDLOW 67 68 #define LOCAL_LABEL_PREFIX "." 69 #define USER_LABEL_PREFIX "" 70 71 /* Offsets recorded in opcodes are a multiple of this alignment factor. 72 The default for this in 64-bit mode is 8, which causes problems with 73 SFmode register saves. */ 74 #define DWARF_CIE_DATA_ALIGNMENT -4 75 76 /* The mapping from gcc register number to DWARF 2 CFA column number. */ 77 #define DWARF_FRAME_REGNUM(REGNO) \ 78 (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM) 79 80 /* The DWARF 2 CFA column which tracks the return address. */ 81 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM 82 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM) 83 84 /* Describe how we implement __builtin_eh_return. */ 85 #define EH_RETURN_DATA_REGNO(N) \ 86 ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 87 88 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4) 89 90 /* Target machine storage layout */ 91 92 #define BITS_BIG_ENDIAN 0 93 #define BYTES_BIG_ENDIAN 0 94 #define WORDS_BIG_ENDIAN 0 95 96 #define MAX_BITS_PER_WORD 64 97 98 /* Width of a word, in units (bytes). */ 99 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 100 #ifndef IN_LIBGCC2 101 #define MIN_UNITS_PER_WORD 4 102 #endif 103 104 /* The `Q' extension is not yet supported. */ 105 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) 106 107 /* The largest type that can be passed in floating-point registers. */ 108 #define UNITS_PER_FP_ARG \ 109 ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \ 110 || riscv_abi == ABI_LP64) \ 111 ? 0 \ 112 : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8)) 113 114 /* Set the sizes of the core types. */ 115 #define SHORT_TYPE_SIZE 16 116 #define INT_TYPE_SIZE 32 117 #define LONG_LONG_TYPE_SIZE 64 118 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32) 119 #define LONG_TYPE_SIZE POINTER_SIZE 120 121 #define FLOAT_TYPE_SIZE 32 122 #define DOUBLE_TYPE_SIZE 64 123 #define LONG_DOUBLE_TYPE_SIZE 128 124 125 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 126 #define PARM_BOUNDARY BITS_PER_WORD 127 128 /* Allocation boundary (in *bits*) for the code of a function. */ 129 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32) 130 131 /* The smallest supported stack boundary the calling convention supports. */ 132 #define STACK_BOUNDARY \ 133 (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD) 134 135 /* The ABI stack alignment. */ 136 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128) 137 138 /* There is no point aligning anything to a rounder boundary than this. */ 139 #define BIGGEST_ALIGNMENT 128 140 141 /* The user-level ISA permits unaligned accesses, but they are not required 142 of the privileged architecture. */ 143 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 144 145 /* Define this if you wish to imitate the way many other C compilers 146 handle alignment of bitfields and the structures that contain 147 them. 148 149 The behavior is that the type written for a bit-field (`int', 150 `short', or other integer type) imposes an alignment for the 151 entire structure, as if the structure really did contain an 152 ordinary field of that type. In addition, the bit-field is placed 153 within the structure so that it would fit within such a field, 154 not crossing a boundary for it. 155 156 Thus, on most machines, a bit-field whose type is written as `int' 157 would not cross a four-byte boundary, and would force four-byte 158 alignment for the whole structure. (The alignment used may not 159 be four bytes; it is controlled by the other alignment 160 parameters.) 161 162 If the macro is defined, its definition should be a C expression; 163 a nonzero value for the expression enables this behavior. */ 164 165 #define PCC_BITFIELD_TYPE_MATTERS 1 166 167 /* An integer expression for the size in bits of the largest integer machine 168 mode that should actually be used. We allow pairs of registers. */ 169 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 170 171 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition. */ 172 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN) \ 173 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 174 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 175 || TREE_CODE (TYPE) == UNION_TYPE \ 176 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 177 178 /* If defined, a C expression to compute the alignment for a static 179 variable. TYPE is the data type, and ALIGN is the alignment that 180 the object would ordinarily have. The value of this macro is used 181 instead of that alignment to align the object. 182 183 If this macro is not defined, then ALIGN is used. 184 185 One use of this macro is to increase alignment of medium-size 186 data to make it all fit in fewer cache lines. Another is to 187 cause character arrays to be word-aligned so that `strcpy' calls 188 that copy constants to character arrays can be done inline. */ 189 190 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 191 RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen, \ 192 TYPE, ALIGN) 193 194 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause 195 character arrays to be word-aligned so that `strcpy' calls that copy 196 constants to character arrays can be done inline, and 'strcmp' can be 197 optimised to use word loads. */ 198 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 199 RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN) 200 201 /* Define if operations between registers always perform the operation 202 on the full register even if a narrower mode is specified. */ 203 #define WORD_REGISTER_OPERATIONS 1 204 205 /* When in 64-bit mode, move insns will sign extend SImode and CCmode 206 moves. All other references are zero extended. */ 207 #define LOAD_EXTEND_OP(MODE) \ 208 (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) 209 210 /* Define this macro if it is advisable to hold scalars in registers 211 in a wider mode than that declared by the program. In such cases, 212 the value is constrained to be within the bounds of the declared 213 type, but kept valid in the wider mode. The signedness of the 214 extension may differ from that of the type. */ 215 216 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 217 if (GET_MODE_CLASS (MODE) == MODE_INT \ 218 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 219 { \ 220 if ((MODE) == SImode) \ 221 (UNSIGNEDP) = 0; \ 222 (MODE) = word_mode; \ 223 } 224 225 /* Pmode is always the same as ptr_mode, but not always the same as word_mode. 226 Extensions of pointers to word_mode must be signed. */ 227 #define POINTERS_EXTEND_UNSIGNED false 228 229 /* Define if loading short immediate values into registers sign extends. */ 230 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 231 232 /* Standard register usage. */ 233 234 /* Number of hardware registers. We have: 235 236 - 32 integer registers 237 - 32 floating point registers 238 - 2 fake registers: 239 - ARG_POINTER_REGNUM 240 - FRAME_POINTER_REGNUM */ 241 242 #define FIRST_PSEUDO_REGISTER 66 243 244 /* x0, sp, gp, and tp are fixed. */ 245 246 #define FIXED_REGISTERS \ 247 { /* General registers. */ \ 248 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 250 /* Floating-point registers. */ \ 251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 253 /* Others. */ \ 254 1, 1 \ 255 } 256 257 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls. 258 The call RTLs themselves clobber ra. */ 259 260 #define CALL_USED_REGISTERS \ 261 { /* General registers. */ \ 262 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ 263 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 264 /* Floating-point registers. */ \ 265 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ 266 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 267 /* Others. */ \ 268 1, 1 \ 269 } 270 271 /* Select a register mode required for caller save of hard regno REGNO. 272 Contrary to what is documented, the default is not the smallest suitable 273 mode but the largest suitable mode for the given (REGNO, NREGS) pair and 274 it quickly creates paradoxical subregs that can be problematic. */ 275 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 276 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE)) 277 278 /* Internal macros to classify an ISA register's type. */ 279 280 #define GP_REG_FIRST 0 281 #define GP_REG_LAST (TARGET_RVE ? 15 : 31) 282 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 283 284 #define FP_REG_FIRST 32 285 #define FP_REG_LAST 63 286 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 287 288 /* The DWARF 2 CFA column which tracks the return address from a 289 signal handler context. This means that to maintain backwards 290 compatibility, no hard register can be assigned this column if it 291 would need to be handled by the DWARF unwinder. */ 292 #define DWARF_ALT_FRAME_RETURN_COLUMN 64 293 294 #define GP_REG_P(REGNO) \ 295 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 296 #define FP_REG_P(REGNO) \ 297 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 298 299 /* True when REGNO is in SIBCALL_REGS set. */ 300 #define SIBCALL_REG_P(REGNO) \ 301 TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO) 302 303 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 304 305 /* Use s0 as the frame pointer if it is so requested. */ 306 #define HARD_FRAME_POINTER_REGNUM 8 307 #define STACK_POINTER_REGNUM 2 308 #define THREAD_POINTER_REGNUM 4 309 310 /* These two registers don't really exist: they get eliminated to either 311 the stack or hard frame pointer. */ 312 #define ARG_POINTER_REGNUM 64 313 #define FRAME_POINTER_REGNUM 65 314 315 /* Register in which static-chain is passed to a function. */ 316 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2) 317 318 /* Registers used as temporaries in prologue/epilogue code. 319 320 The prologue registers mustn't conflict with any 321 incoming arguments, the static chain pointer, or the frame pointer. 322 The epilogue temporary mustn't conflict with the return registers, 323 the frame pointer, the EH stack adjustment, or the EH data registers. */ 324 325 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST) 326 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM) 327 328 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1) 329 #define RISCV_CALL_ADDRESS_TEMP(MODE) \ 330 gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM) 331 332 #define MCOUNT_NAME "_mcount" 333 334 #define NO_PROFILE_COUNTERS 1 335 336 /* Emit rtl for profiling. Output assembler code to FILE 337 to call "_mcount" for profiling a function entry. */ 338 #define PROFILE_HOOK(LABEL) \ 339 { \ 340 rtx fun, ra; \ 341 ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \ 342 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 343 emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \ 344 } 345 346 /* All the work done in PROFILE_HOOK, but still required. */ 347 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 348 349 /* Define this macro if it is as good or better to call a constant 350 function address than to call an address kept in a register. */ 351 #define NO_FUNCTION_CSE 1 352 353 /* Define the classes of registers for register constraints in the 354 machine description. Also define ranges of constants. 355 356 One of the classes must always be named ALL_REGS and include all hard regs. 357 If there is more than one class, another class must be named NO_REGS 358 and contain no registers. 359 360 The name GENERAL_REGS must be the name of a class (or an alias for 361 another name such as ALL_REGS). This is the class of registers 362 that is allowed by "g" or "r" in a register constraint. 363 Also, registers outside this class are allocated only when 364 instructions express preferences for them. 365 366 The classes must be numbered in nondecreasing order; that is, 367 a larger-numbered class must never be contained completely 368 in a smaller-numbered class. 369 370 For any two classes, it is very desirable that there be another 371 class that represents their union. */ 372 373 enum reg_class 374 { 375 NO_REGS, /* no registers in set */ 376 SIBCALL_REGS, /* registers used by indirect sibcalls */ 377 JALR_REGS, /* registers used by indirect calls */ 378 GR_REGS, /* integer registers */ 379 FP_REGS, /* floating-point registers */ 380 FRAME_REGS, /* arg pointer and frame pointer */ 381 ALL_REGS, /* all registers */ 382 LIM_REG_CLASSES /* max value + 1 */ 383 }; 384 385 #define N_REG_CLASSES (int) LIM_REG_CLASSES 386 387 #define GENERAL_REGS GR_REGS 388 389 /* An initializer containing the names of the register classes as C 390 string constants. These names are used in writing some of the 391 debugging dumps. */ 392 393 #define REG_CLASS_NAMES \ 394 { \ 395 "NO_REGS", \ 396 "SIBCALL_REGS", \ 397 "JALR_REGS", \ 398 "GR_REGS", \ 399 "FP_REGS", \ 400 "FRAME_REGS", \ 401 "ALL_REGS" \ 402 } 403 404 /* An initializer containing the contents of the register classes, 405 as integers which are bit masks. The Nth integer specifies the 406 contents of class N. The way the integer MASK is interpreted is 407 that register R is in the class if `MASK & (1 << R)' is 1. 408 409 When the machine has more than 32 registers, an integer does not 410 suffice. Then the integers are replaced by sub-initializers, 411 braced groupings containing several integers. Each 412 sub-initializer must be suitable as an initializer for the type 413 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 414 415 #define REG_CLASS_CONTENTS \ 416 { \ 417 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 418 { 0xf003fcc0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ 419 { 0xffffffc0, 0x00000000, 0x00000000 }, /* JALR_REGS */ \ 420 { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \ 421 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 422 { 0x00000000, 0x00000000, 0x00000003 }, /* FRAME_REGS */ \ 423 { 0xffffffff, 0xffffffff, 0x00000003 } /* ALL_REGS */ \ 424 } 425 426 /* A C expression whose value is a register class containing hard 427 register REGNO. In general there is more that one such class; 428 choose a class which is "minimal", meaning that no smaller class 429 also contains the register. */ 430 431 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ] 432 433 /* A macro whose definition is the name of the class to which a 434 valid base register must belong. A base register is one used in 435 an address which is the register value plus a displacement. */ 436 437 #define BASE_REG_CLASS GR_REGS 438 439 /* A macro whose definition is the name of the class to which a 440 valid index register must belong. An index register is one used 441 in an address where its value is either multiplied by a scale 442 factor or added to another register (as well as added to a 443 displacement). */ 444 445 #define INDEX_REG_CLASS NO_REGS 446 447 /* We generally want to put call-clobbered registers ahead of 448 call-saved ones. (IRA expects this.) */ 449 450 #define REG_ALLOC_ORDER \ 451 { \ 452 /* Call-clobbered GPRs. */ \ 453 15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1, \ 454 /* Call-saved GPRs. */ \ 455 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ 456 /* GPRs that can never be exposed to the register allocator. */ \ 457 0, 2, 3, 4, \ 458 /* Call-clobbered FPRs. */ \ 459 47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49, \ 460 60, 61, 62, 63, \ 461 /* Call-saved FPRs. */ \ 462 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ 463 /* None of the remaining classes have defined call-saved \ 464 registers. */ \ 465 64, 65 \ 466 } 467 468 /* True if VALUE is a signed 12-bit number. */ 469 470 #define SMALL_OPERAND(VALUE) \ 471 ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH) 472 473 /* True if VALUE can be loaded into a register using LUI. */ 474 475 #define LUI_OPERAND(VALUE) \ 476 (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \ 477 || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0) 478 479 /* Stack layout; function entry, exit and calling. */ 480 481 #define STACK_GROWS_DOWNWARD 1 482 483 #define FRAME_GROWS_DOWNWARD 1 484 485 #define RETURN_ADDR_RTX riscv_return_addr 486 487 #define ELIMINABLE_REGS \ 488 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 489 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 490 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 491 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 492 493 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 494 (OFFSET) = riscv_initial_elimination_offset (FROM, TO) 495 496 /* Allocate stack space for arguments at the beginning of each function. */ 497 #define ACCUMULATE_OUTGOING_ARGS 1 498 499 /* The argument pointer always points to the first argument. */ 500 #define FIRST_PARM_OFFSET(FNDECL) 0 501 502 #define REG_PARM_STACK_SPACE(FNDECL) 0 503 504 /* Define this if it is the responsibility of the caller to 505 allocate the area reserved for arguments passed in registers. 506 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 507 of this macro is to determine whether the space is included in 508 `crtl->outgoing_args_size'. */ 509 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 510 511 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary 512 513 /* Symbolic macros for the registers used to return integer and floating 514 point values. */ 515 516 #define GP_RETURN GP_ARG_FIRST 517 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST) 518 519 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8) 520 521 /* Symbolic macros for the first/last argument registers. */ 522 523 #define GP_ARG_FIRST (GP_REG_FIRST + 10) 524 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 525 #define GP_TEMP_FIRST (GP_REG_FIRST + 5) 526 #define FP_ARG_FIRST (FP_REG_FIRST + 10) 527 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 528 529 #define CALLEE_SAVED_REG_NUMBER(REGNO) \ 530 ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \ 531 (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1) 532 533 #define LIBCALL_VALUE(MODE) \ 534 riscv_function_value (NULL_TREE, NULL_TREE, MODE) 535 536 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 537 riscv_function_value (VALTYPE, FUNC, VOIDmode) 538 539 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) 540 541 /* 1 if N is a possible register number for function argument passing. 542 We have no FP argument registers when soft-float. */ 543 544 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */ 545 #define FUNCTION_ARG_REGNO_P(N) \ 546 (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \ 547 || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST))) 548 549 typedef struct { 550 /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */ 551 unsigned int num_gprs; 552 553 /* Number of floating-point registers used so far, likewise. */ 554 unsigned int num_fprs; 555 } CUMULATIVE_ARGS; 556 557 /* Initialize a variable CUM of type CUMULATIVE_ARGS 558 for a call to a function whose data type is FNTYPE. 559 For a library call, FNTYPE is 0. */ 560 561 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 562 memset (&(CUM), 0, sizeof (CUM)) 563 564 #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO) 565 566 /* Align based on stack boundary, which might have been set by the user. */ 567 #define RISCV_STACK_ALIGN(LOC) \ 568 (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8)) 569 570 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 571 the stack pointer does not matter. The value is tested only in 572 functions that have frame pointers. 573 No definition is equivalent to always zero. */ 574 575 #define EXIT_IGNORE_STACK 1 576 577 578 /* Trampolines are a block of code followed by two pointers. */ 579 580 #define TRAMPOLINE_CODE_SIZE 16 581 #define TRAMPOLINE_SIZE \ 582 ((Pmode == SImode) \ 583 ? TRAMPOLINE_CODE_SIZE \ 584 : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2)) 585 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE 586 587 /* Addressing modes, and classification of registers for them. */ 588 589 #define REGNO_OK_FOR_INDEX_P(REGNO) 0 590 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 591 riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1) 592 593 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 594 and check its validity for a certain class. 595 We have two alternate definitions for each of them. 596 The usual definition accepts all pseudo regs; the other rejects them all. 597 The symbol REG_OK_STRICT causes the latter definition to be used. 598 599 Most source files want to accept pseudo regs in the hope that 600 they will get allocated to the class that the insn wants them to be in. 601 Some source files that are used after register allocation 602 need to be strict. */ 603 604 #ifndef REG_OK_STRICT 605 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 606 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) 607 #else 608 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 609 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) 610 #endif 611 612 #define REG_OK_FOR_INDEX_P(X) 0 613 614 /* Maximum number of registers that can appear in a valid memory address. */ 615 616 #define MAX_REGS_PER_ADDRESS 1 617 618 #define CONSTANT_ADDRESS_P(X) \ 619 (CONSTANT_P (X) && memory_address_p (SImode, X)) 620 621 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means 622 'the start of the function that this code is output in'. */ 623 624 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 625 do { \ 626 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 627 asm_fprintf ((FILE), "%U%s", \ 628 XSTR (XEXP (DECL_RTL (current_function_decl), \ 629 0), 0)); \ 630 else \ 631 asm_fprintf ((FILE), "%U%s", (NAME)); \ 632 } while (0) 633 634 #define JUMP_TABLES_IN_TEXT_SECTION 0 635 #define CASE_VECTOR_MODE SImode 636 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW) 637 638 /* The load-address macro is used for PC-relative addressing of symbols 639 that bind locally. Don't use it for symbols that should be addressed 640 via the GOT. Also, avoid it for CM_MEDLOW, where LUI addressing 641 currently results in more opportunities for linker relaxation. */ 642 #define USE_LOAD_ADDRESS_MACRO(sym) \ 643 (!TARGET_EXPLICIT_RELOCS && \ 644 ((flag_pic \ 645 && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym)) \ 646 || ((GET_CODE (sym) == CONST) \ 647 && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0)) \ 648 && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))) \ 649 || riscv_cmodel == CM_MEDANY)) 650 651 /* Define this as 1 if `char' should by default be signed; else as 0. */ 652 #define DEFAULT_SIGNED_CHAR 0 653 654 #define MOVE_MAX UNITS_PER_WORD 655 #define MAX_MOVE_MAX 8 656 657 /* The SPARC port says: 658 Nonzero if access to memory by bytes is slow and undesirable. 659 For RISC chips, it means that access to memory by bytes is no 660 better than access by words when possible, so grab a whole word 661 and maybe make use of that. */ 662 #define SLOW_BYTE_ACCESS 1 663 664 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns 665 in the md file instead. */ 666 #define SHIFT_COUNT_TRUNCATED 0 667 668 /* Specify the machine mode that pointers have. 669 After generation of rtl, the compiler makes no further distinction 670 between pointers and any other objects of this machine mode. */ 671 672 #define Pmode word_mode 673 674 /* Give call MEMs SImode since it is the "most permissive" mode 675 for both 32-bit and 64-bit targets. */ 676 677 #define FUNCTION_MODE SImode 678 679 /* A C expression for the cost of a branch instruction. A value of 2 680 seems to minimize code size. */ 681 682 #define BRANCH_COST(speed_p, predictable_p) \ 683 ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost) 684 685 /* True if the target optimizes short forward branches around integer 686 arithmetic instructions into predicated operations, e.g., for 687 conditional-move operations. The macro assumes that all branch 688 instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ) 689 support this feature. The macro further assumes that any integer 690 arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I], 691 SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed 692 counterparts, including C.MV and C.LI) can be in the branch shadow. */ 693 694 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7) 695 696 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 697 698 /* Control the assembler format that we output. */ 699 700 /* Output to assembler file text saying following lines 701 may contain character constants, extra white space, comments, etc. */ 702 703 #ifndef ASM_APP_ON 704 #define ASM_APP_ON " #APP\n" 705 #endif 706 707 /* Output to assembler file text saying following lines 708 no longer contain unusual constructs. */ 709 710 #ifndef ASM_APP_OFF 711 #define ASM_APP_OFF " #NO_APP\n" 712 #endif 713 714 #define REGISTER_NAMES \ 715 { "zero","ra", "sp", "gp", "tp", "t0", "t1", "t2", \ 716 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \ 717 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \ 718 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \ 719 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \ 720 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \ 721 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \ 722 "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \ 723 "arg", "frame", } 724 725 #define ADDITIONAL_REGISTER_NAMES \ 726 { \ 727 { "x0", 0 + GP_REG_FIRST }, \ 728 { "x1", 1 + GP_REG_FIRST }, \ 729 { "x2", 2 + GP_REG_FIRST }, \ 730 { "x3", 3 + GP_REG_FIRST }, \ 731 { "x4", 4 + GP_REG_FIRST }, \ 732 { "x5", 5 + GP_REG_FIRST }, \ 733 { "x6", 6 + GP_REG_FIRST }, \ 734 { "x7", 7 + GP_REG_FIRST }, \ 735 { "x8", 8 + GP_REG_FIRST }, \ 736 { "x9", 9 + GP_REG_FIRST }, \ 737 { "x10", 10 + GP_REG_FIRST }, \ 738 { "x11", 11 + GP_REG_FIRST }, \ 739 { "x12", 12 + GP_REG_FIRST }, \ 740 { "x13", 13 + GP_REG_FIRST }, \ 741 { "x14", 14 + GP_REG_FIRST }, \ 742 { "x15", 15 + GP_REG_FIRST }, \ 743 { "x16", 16 + GP_REG_FIRST }, \ 744 { "x17", 17 + GP_REG_FIRST }, \ 745 { "x18", 18 + GP_REG_FIRST }, \ 746 { "x19", 19 + GP_REG_FIRST }, \ 747 { "x20", 20 + GP_REG_FIRST }, \ 748 { "x21", 21 + GP_REG_FIRST }, \ 749 { "x22", 22 + GP_REG_FIRST }, \ 750 { "x23", 23 + GP_REG_FIRST }, \ 751 { "x24", 24 + GP_REG_FIRST }, \ 752 { "x25", 25 + GP_REG_FIRST }, \ 753 { "x26", 26 + GP_REG_FIRST }, \ 754 { "x27", 27 + GP_REG_FIRST }, \ 755 { "x28", 28 + GP_REG_FIRST }, \ 756 { "x29", 29 + GP_REG_FIRST }, \ 757 { "x30", 30 + GP_REG_FIRST }, \ 758 { "x31", 31 + GP_REG_FIRST }, \ 759 { "f0", 0 + FP_REG_FIRST }, \ 760 { "f1", 1 + FP_REG_FIRST }, \ 761 { "f2", 2 + FP_REG_FIRST }, \ 762 { "f3", 3 + FP_REG_FIRST }, \ 763 { "f4", 4 + FP_REG_FIRST }, \ 764 { "f5", 5 + FP_REG_FIRST }, \ 765 { "f6", 6 + FP_REG_FIRST }, \ 766 { "f7", 7 + FP_REG_FIRST }, \ 767 { "f8", 8 + FP_REG_FIRST }, \ 768 { "f9", 9 + FP_REG_FIRST }, \ 769 { "f10", 10 + FP_REG_FIRST }, \ 770 { "f11", 11 + FP_REG_FIRST }, \ 771 { "f12", 12 + FP_REG_FIRST }, \ 772 { "f13", 13 + FP_REG_FIRST }, \ 773 { "f14", 14 + FP_REG_FIRST }, \ 774 { "f15", 15 + FP_REG_FIRST }, \ 775 { "f16", 16 + FP_REG_FIRST }, \ 776 { "f17", 17 + FP_REG_FIRST }, \ 777 { "f18", 18 + FP_REG_FIRST }, \ 778 { "f19", 19 + FP_REG_FIRST }, \ 779 { "f20", 20 + FP_REG_FIRST }, \ 780 { "f21", 21 + FP_REG_FIRST }, \ 781 { "f22", 22 + FP_REG_FIRST }, \ 782 { "f23", 23 + FP_REG_FIRST }, \ 783 { "f24", 24 + FP_REG_FIRST }, \ 784 { "f25", 25 + FP_REG_FIRST }, \ 785 { "f26", 26 + FP_REG_FIRST }, \ 786 { "f27", 27 + FP_REG_FIRST }, \ 787 { "f28", 28 + FP_REG_FIRST }, \ 788 { "f29", 29 + FP_REG_FIRST }, \ 789 { "f30", 30 + FP_REG_FIRST }, \ 790 { "f31", 31 + FP_REG_FIRST }, \ 791 } 792 793 /* Globalizing directive for a label. */ 794 #define GLOBAL_ASM_OP "\t.globl\t" 795 796 /* This is how to store into the string LABEL 797 the symbol_ref name of an internal numbered label where 798 PREFIX is the class of label and NUM is the number within the class. 799 This is suitable for output with `assemble_name'. */ 800 801 #undef ASM_GENERATE_INTERNAL_LABEL 802 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 803 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 804 805 /* This is how to output an element of a case-vector that is absolute. */ 806 807 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 808 fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE) 809 810 /* This is how to output an element of a PIC case-vector. */ 811 812 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 813 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ 814 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL) 815 816 /* This is how to output an assembler line 817 that says to advance the location counter 818 to a multiple of 2**LOG bytes. */ 819 820 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 821 fprintf (STREAM, "\t.align\t%d\n", (LOG)) 822 823 /* Define the strings to put out for each section in the object file. */ 824 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 825 #define DATA_SECTION_ASM_OP "\t.data" /* large data */ 826 #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" 827 #define BSS_SECTION_ASM_OP "\t.bss" 828 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits" 829 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits" 830 831 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 832 do \ 833 { \ 834 fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ 835 reg_names[STACK_POINTER_REGNUM], \ 836 reg_names[STACK_POINTER_REGNUM], \ 837 TARGET_64BIT ? "sd" : "sw", \ 838 reg_names[REGNO], \ 839 reg_names[STACK_POINTER_REGNUM]); \ 840 } \ 841 while (0) 842 843 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 844 do \ 845 { \ 846 fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \ 847 TARGET_64BIT ? "ld" : "lw", \ 848 reg_names[REGNO], \ 849 reg_names[STACK_POINTER_REGNUM], \ 850 reg_names[STACK_POINTER_REGNUM], \ 851 reg_names[STACK_POINTER_REGNUM]); \ 852 } \ 853 while (0) 854 855 #define ASM_COMMENT_START "#" 856 857 #undef SIZE_TYPE 858 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 859 860 #undef PTRDIFF_TYPE 861 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 862 863 /* The maximum number of bytes copied by one iteration of a cpymemsi loop. */ 864 865 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4) 866 867 /* The maximum number of bytes that can be copied by a straight-line 868 cpymemsi implementation. */ 869 870 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3) 871 872 /* If a memory-to-memory move would take MOVE_RATIO or more simple 873 move-instruction pairs, we will do a cpymem or libcall instead. 874 Do not use move_by_pieces at all when strict alignment is not 875 in effect but the target has slow unaligned accesses; in this 876 case, cpymem or libcall is more efficient. */ 877 878 #define MOVE_RATIO(speed) \ 879 (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 : \ 880 (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD : \ 881 CLEAR_RATIO (speed) / 2) 882 883 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 884 of the length of a memset call, but use the default otherwise. */ 885 886 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6) 887 888 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when 889 optimizing for size adjust the ratio to account for the overhead of 890 loading the constant and replicating it across the word. */ 891 892 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2)) 893 894 #ifndef USED_FOR_TARGET 895 extern const enum reg_class riscv_regno_to_class[]; 896 extern bool riscv_slow_unaligned_access_p; 897 extern unsigned riscv_stack_boundary; 898 #endif 899 900 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 901 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) 902 903 #define XLEN_SPEC \ 904 "%{march=rv32*:32}" \ 905 "%{march=rv64*:64}" \ 906 907 #define ABI_SPEC \ 908 "%{mabi=ilp32:ilp32}" \ 909 "%{mabi=ilp32e:ilp32e}" \ 910 "%{mabi=ilp32f:ilp32f}" \ 911 "%{mabi=ilp32d:ilp32d}" \ 912 "%{mabi=lp64:lp64}" \ 913 "%{mabi=lp64f:lp64f}" \ 914 "%{mabi=lp64d:lp64d}" \ 915 916 /* ISA constants needed for code generation. */ 917 #define OPCODE_LW 0x2003 918 #define OPCODE_LD 0x3003 919 #define OPCODE_AUIPC 0x17 920 #define OPCODE_JALR 0x67 921 #define OPCODE_LUI 0x37 922 #define OPCODE_ADDI 0x13 923 #define SHIFT_RD 7 924 #define SHIFT_RS1 15 925 #define SHIFT_IMM 20 926 #define IMM_BITS 12 927 #define C_SxSP_BITS 6 928 929 #define IMM_REACH (1LL << IMM_BITS) 930 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1)) 931 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) 932 933 #define SWSP_REACH (4LL << C_SxSP_BITS) 934 #define SDSP_REACH (8LL << C_SxSP_BITS) 935 936 /* Called from RISCV_REORG, this is defined in riscv-sr.c. */ 937 938 extern void riscv_remove_unneeded_save_restore_calls (void); 939 940 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO) 941 942 #endif /* ! GCC_RISCV_H */ 943