1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992-2020 Free Software Foundation, Inc. 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 Under Section 7 of GPL version 3, you are granted additional 18 permissions described in the GCC Runtime Library Exception, version 19 3.1, as published by the Free Software Foundation. 20 21 You should have received a copy of the GNU General Public License and 22 a copy of the GCC Runtime Library Exception along with this program; 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 <http://www.gnu.org/licenses/>. */ 25 26 /* Note that some other tm.h files include this one and then override 27 many of the definitions. */ 28 29 #ifndef RS6000_OPTS_H 30 #include "config/rs6000/rs6000-opts.h" 31 #endif 32 33 /* 128-bit floating point precision values. */ 34 #ifndef RS6000_MODES_H 35 #include "config/rs6000/rs6000-modes.h" 36 #endif 37 38 /* Definitions for the object file format. These are set at 39 compile-time. */ 40 41 #define OBJECT_XCOFF 1 42 #define OBJECT_ELF 2 43 #define OBJECT_MACHO 4 44 45 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 46 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 48 49 #ifndef TARGET_AIX 50 #define TARGET_AIX 0 51 #endif 52 53 #ifndef TARGET_AIX_OS 54 #define TARGET_AIX_OS 0 55 #endif 56 57 /* Turn off TOC support if pc-relative addressing is used. */ 58 #define TARGET_TOC (TARGET_HAS_TOC && !TARGET_PCREL) 59 60 /* On 32-bit systems without a TOC or pc-relative addressing, we need to use 61 ADDIS/ADDI to load up the address of a symbol. */ 62 #define TARGET_NO_TOC_OR_PCREL (!TARGET_HAS_TOC && !TARGET_PCREL) 63 64 /* Control whether function entry points use a "dot" symbol when 65 ABI_AIX. */ 66 #define DOT_SYMBOLS 1 67 68 /* Default string to use for cpu if not specified. */ 69 #ifndef TARGET_CPU_DEFAULT 70 #define TARGET_CPU_DEFAULT ((char *)0) 71 #endif 72 73 /* If configured for PPC405, support PPC405CR Erratum77. */ 74 #ifdef CONFIG_PPC405CR 75 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 76 #else 77 #define PPC405_ERRATUM77 0 78 #endif 79 80 #ifndef SUBTARGET_DRIVER_SELF_SPECS 81 # define SUBTARGET_DRIVER_SELF_SPECS "" 82 #endif 83 84 /* Only for use in the testsuite: -mdejagnu-cpu= simply overrides -mcpu=. 85 With older versions of Dejagnu the command line arguments you set in 86 RUNTESTFLAGS override those set in the testcases; with this option, 87 the testcase will always win. Ditto for -mdejagnu-tune=. */ 88 #define DRIVER_SELF_SPECS \ 89 "%{mdejagnu-cpu=*: %<mcpu=* -mcpu=%*}", \ 90 "%{mdejagnu-tune=*: %<mtune=* -mtune=%*}", \ 91 "%{mdejagnu-*: %<mdejagnu-*}", \ 92 SUBTARGET_DRIVER_SELF_SPECS 93 94 #if CHECKING_P 95 #define ASM_OPT_ANY "" 96 #else 97 #define ASM_OPT_ANY " -many" 98 #endif 99 100 /* Common ASM definitions used by ASM_SPEC among the various targets for 101 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to 102 provide the default assembler options if the user uses -mcpu=native, so if 103 you make changes here, make them also there. PR63177: Do not pass -mpower8 104 to the assembler if -mpower9-vector was also used. */ 105 #define ASM_CPU_SPEC \ 106 "%{mcpu=native: %(asm_cpu_native); \ 107 mcpu=power10: -mpower10; \ 108 mcpu=power9: -mpower9; \ 109 mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ 110 mcpu=power7: -mpower7; \ 111 mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ 112 mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ 113 mcpu=power5+: -mpower5; \ 114 mcpu=power5: -mpower5; \ 115 mcpu=power4: -mpower4; \ 116 mcpu=power3: -mppc64; \ 117 mcpu=powerpc: -mppc; \ 118 mcpu=powerpc64: -mppc64; \ 119 mcpu=a2: -ma2; \ 120 mcpu=cell: -mcell; \ 121 mcpu=rs64: -mppc64; \ 122 mcpu=401: -mppc; \ 123 mcpu=403: -m403; \ 124 mcpu=405: -m405; \ 125 mcpu=405fp: -m405; \ 126 mcpu=440: -m440; \ 127 mcpu=440fp: -m440; \ 128 mcpu=464: -m440; \ 129 mcpu=464fp: -m440; \ 130 mcpu=476: -m476; \ 131 mcpu=476fp: -m476; \ 132 mcpu=505: -mppc; \ 133 mcpu=601: -m601; \ 134 mcpu=602: -mppc; \ 135 mcpu=603: -mppc; \ 136 mcpu=603e: -mppc; \ 137 mcpu=ec603e: -mppc; \ 138 mcpu=604: -mppc; \ 139 mcpu=604e: -mppc; \ 140 mcpu=620: -mppc64; \ 141 mcpu=630: -mppc64; \ 142 mcpu=740: -mppc; \ 143 mcpu=750: -mppc; \ 144 mcpu=G3: -mppc; \ 145 mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 146 mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 147 mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 148 mcpu=801: -mppc; \ 149 mcpu=821: -mppc; \ 150 mcpu=823: -mppc; \ 151 mcpu=860: -mppc; \ 152 mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ 153 mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ 154 mcpu=8540: -me500; \ 155 mcpu=8548: -me500; \ 156 mcpu=e300c2: -me300; \ 157 mcpu=e300c3: -me300; \ 158 mcpu=e500mc: -me500mc; \ 159 mcpu=e500mc64: -me500mc64; \ 160 mcpu=e5500: -me5500; \ 161 mcpu=e6500: -me6500; \ 162 mcpu=titan: -mtitan; \ 163 !mcpu*: %{mpower9-vector: -mpower9; \ 164 mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ 165 mvsx: -mpower7; \ 166 mpowerpc64: -mppc64;: %(asm_default)}; \ 167 :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \ 168 %{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \ 169 ASM_OPT_ANY 170 171 #define CPP_DEFAULT_SPEC "" 172 173 #define ASM_DEFAULT_SPEC "" 174 #define ASM_DEFAULT_EXTRA "" 175 176 /* This macro defines names of additional specifications to put in the specs 177 that can be used in various specifications like CC1_SPEC. Its definition 178 is an initializer with a subgrouping for each command option. 179 180 Each subgrouping contains a string constant, that defines the 181 specification name, and a string constant that used by the GCC driver 182 program. 183 184 Do not define this macro if it does not need to do anything. */ 185 186 #define SUBTARGET_EXTRA_SPECS 187 188 #define EXTRA_SPECS \ 189 { "cpp_default", CPP_DEFAULT_SPEC }, \ 190 { "asm_cpu", ASM_CPU_SPEC }, \ 191 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 192 { "asm_default", ASM_DEFAULT_SPEC ASM_DEFAULT_EXTRA }, \ 193 { "cc1_cpu", CC1_CPU_SPEC }, \ 194 SUBTARGET_EXTRA_SPECS 195 196 /* -mcpu=native handling only makes sense with compiler running on 197 an PowerPC chip. If changing this condition, also change 198 the condition in driver-rs6000.c. */ 199 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) 200 /* In driver-rs6000.c. */ 201 extern const char *host_detect_local_cpu (int argc, const char **argv); 202 #define EXTRA_SPEC_FUNCTIONS \ 203 { "local_cpu_detect", host_detect_local_cpu }, 204 #define HAVE_LOCAL_CPU_DETECT 205 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" 206 207 #else 208 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" 209 #endif 210 211 #ifndef CC1_CPU_SPEC 212 #ifdef HAVE_LOCAL_CPU_DETECT 213 #define CC1_CPU_SPEC \ 214 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ 215 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 216 #else 217 #define CC1_CPU_SPEC "" 218 #endif 219 #endif 220 221 /* Architecture type. */ 222 223 /* Define TARGET_MFCRF if the target assembler does not support the 224 optional field operand for mfcr. */ 225 226 #ifndef HAVE_AS_MFCRF 227 #undef TARGET_MFCRF 228 #define TARGET_MFCRF 0 229 #endif 230 231 #ifndef TARGET_SECURE_PLT 232 #define TARGET_SECURE_PLT 0 233 #endif 234 235 #ifndef TARGET_CMODEL 236 #define TARGET_CMODEL CMODEL_SMALL 237 #endif 238 239 #define TARGET_32BIT (! TARGET_64BIT) 240 241 #ifndef HAVE_AS_TLS 242 #define HAVE_AS_TLS 0 243 #endif 244 245 #ifndef HAVE_AS_PLTSEQ 246 #define HAVE_AS_PLTSEQ 0 247 #endif 248 249 #ifndef TARGET_PLTSEQ 250 #define TARGET_PLTSEQ 0 251 #endif 252 253 #ifndef TARGET_LINK_STACK 254 #define TARGET_LINK_STACK 0 255 #endif 256 257 #ifndef SET_TARGET_LINK_STACK 258 #define SET_TARGET_LINK_STACK(X) do { } while (0) 259 #endif 260 261 #ifndef TARGET_FLOAT128_ENABLE_TYPE 262 #define TARGET_FLOAT128_ENABLE_TYPE 0 263 #endif 264 265 /* Return 1 for a symbol ref for a thread-local storage symbol. */ 266 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ 267 (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0) 268 269 #ifdef IN_LIBGCC2 270 /* For libgcc2 we make sure this is a compile time constant */ 271 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 272 #undef TARGET_POWERPC64 273 #define TARGET_POWERPC64 1 274 #else 275 #undef TARGET_POWERPC64 276 #define TARGET_POWERPC64 0 277 #endif 278 #else 279 /* The option machinery will define this. */ 280 #endif 281 282 #define TARGET_DEFAULT (MASK_MULTIPLE) 283 284 /* Define generic processor types based upon current deployment. */ 285 #define PROCESSOR_COMMON PROCESSOR_PPC601 286 #define PROCESSOR_POWERPC PROCESSOR_PPC604 287 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 288 289 /* Define the default processor. This is overridden by other tm.h files. */ 290 #define PROCESSOR_DEFAULT PROCESSOR_PPC603 291 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 292 293 /* Specify the dialect of assembler to use. Only new mnemonics are supported 294 starting with GCC 4.8, i.e. just one dialect, but for backwards 295 compatibility with older inline asm ASSEMBLER_DIALECT needs to be 296 defined. */ 297 #define ASSEMBLER_DIALECT 1 298 299 /* Debug support */ 300 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ 301 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ 302 #define MASK_DEBUG_REG 0x04 /* debug register handling */ 303 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ 304 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ 305 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ 306 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ 307 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ 308 | MASK_DEBUG_ARG \ 309 | MASK_DEBUG_REG \ 310 | MASK_DEBUG_ADDR \ 311 | MASK_DEBUG_COST \ 312 | MASK_DEBUG_TARGET \ 313 | MASK_DEBUG_BUILTIN) 314 315 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) 316 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) 317 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) 318 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) 319 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) 320 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) 321 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) 322 323 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM 324 long double format that uses a pair of doubles, or IEEE 128-bit floating 325 point. KFmode was added as a way to represent IEEE 128-bit floating point, 326 even if the default for long double is the IBM long double format. 327 Similarly IFmode is the IBM long double format even if the default is IEEE 328 128-bit. Don't allow IFmode if -msoft-float. */ 329 #define FLOAT128_IEEE_P(MODE) \ 330 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 331 && ((MODE) == TFmode || (MODE) == TCmode)) \ 332 || ((MODE) == KFmode) || ((MODE) == KCmode)) 333 334 #define FLOAT128_IBM_P(MODE) \ 335 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 336 && ((MODE) == TFmode || (MODE) == TCmode)) \ 337 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) 338 339 /* Helper macros to say whether a 128-bit floating point type can go in a 340 single vector register, or whether it needs paired scalar values. */ 341 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) 342 343 #define FLOAT128_2REG_P(MODE) \ 344 (FLOAT128_IBM_P (MODE) \ 345 || ((MODE) == TDmode) \ 346 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) 347 348 /* Return true for floating point that does not use a vector register. */ 349 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ 350 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) 351 352 /* Describe the vector unit used for arithmetic operations. */ 353 extern enum rs6000_vector rs6000_vector_unit[]; 354 355 #define VECTOR_UNIT_NONE_P(MODE) \ 356 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) 357 358 #define VECTOR_UNIT_VSX_P(MODE) \ 359 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) 360 361 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ 362 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) 363 364 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ 365 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) 366 367 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ 368 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 369 (int)VECTOR_VSX, \ 370 (int)VECTOR_P8_VECTOR)) 371 372 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either 373 altivec (VMX) or VSX vector instructions. P8 vector support is upwards 374 compatible, so allow it as well, rather than changing all of the uses of the 375 macro. */ 376 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ 377 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 378 (int)VECTOR_ALTIVEC, \ 379 (int)VECTOR_P8_VECTOR)) 380 381 /* Describe whether to use VSX loads or Altivec loads. For now, just use the 382 same unit as the vector unit we are using, but we may want to migrate to 383 using VSX style loads even for types handled by altivec. */ 384 extern enum rs6000_vector rs6000_vector_mem[]; 385 386 #define VECTOR_MEM_NONE_P(MODE) \ 387 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) 388 389 #define VECTOR_MEM_VSX_P(MODE) \ 390 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 391 392 #define VECTOR_MEM_P8_VECTOR_P(MODE) \ 393 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 394 395 #define VECTOR_MEM_ALTIVEC_P(MODE) \ 396 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) 397 398 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ 399 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 400 (int)VECTOR_VSX, \ 401 (int)VECTOR_P8_VECTOR)) 402 403 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ 404 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 405 (int)VECTOR_ALTIVEC, \ 406 (int)VECTOR_P8_VECTOR)) 407 408 /* Return the alignment of a given vector type, which is set based on the 409 vector unit use. VSX for instance can load 32 or 64 bit aligned words 410 without problems, while Altivec requires 128-bit aligned vectors. */ 411 extern int rs6000_vector_align[]; 412 413 #define VECTOR_ALIGN(MODE) \ 414 ((rs6000_vector_align[(MODE)] != 0) \ 415 ? rs6000_vector_align[(MODE)] \ 416 : (int)GET_MODE_BITSIZE ((MODE))) 417 418 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 419 with scalar instructions. */ 420 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) 421 422 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 423 with the ISA 3.0 MFVSRLD instructions. */ 424 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) 425 426 /* Alignment options for fields in structures for sub-targets following 427 AIX-like ABI. 428 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 429 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 430 431 Override the macro definitions when compiling libobjc to avoid undefined 432 reference to rs6000_alignment_flags due to library's use of GCC alignment 433 macros which use the macros below. */ 434 435 #ifndef IN_TARGET_LIBS 436 #define MASK_ALIGN_POWER 0x00000000 437 #define MASK_ALIGN_NATURAL 0x00000001 438 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 439 #else 440 #define TARGET_ALIGN_NATURAL 0 441 #endif 442 443 /* We use values 126..128 to pick the appropriate long double type (IFmode, 444 KFmode, TFmode). */ 445 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) 446 #define TARGET_IEEEQUAD rs6000_ieeequad 447 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 448 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 449 450 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. 451 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ 452 #define TARGET_FCFID (TARGET_POWERPC64 \ 453 || TARGET_PPC_GPOPT /* 970/power4 */ \ 454 || TARGET_POPCNTB /* ISA 2.02 */ \ 455 || TARGET_CMPB /* ISA 2.05 */ \ 456 || TARGET_POPCNTD) /* ISA 2.06 */ 457 458 #define TARGET_FCTIDZ TARGET_FCFID 459 #define TARGET_STFIWX TARGET_PPC_GFXOPT 460 #define TARGET_LFIWAX TARGET_CMPB 461 #define TARGET_LFIWZX TARGET_POPCNTD 462 #define TARGET_FCFIDS TARGET_POPCNTD 463 #define TARGET_FCFIDU TARGET_POPCNTD 464 #define TARGET_FCFIDUS TARGET_POPCNTD 465 #define TARGET_FCTIDUZ TARGET_POPCNTD 466 #define TARGET_FCTIWUZ TARGET_POPCNTD 467 #define TARGET_CTZ TARGET_MODULO 468 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) 469 #define TARGET_MADDLD TARGET_MODULO 470 471 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 472 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 473 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) 474 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 475 && TARGET_POWERPC64) 476 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 477 && TARGET_POWERPC64) 478 479 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ 480 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT 481 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) 482 483 /* This wants to be set for p8 and newer. On p7, overlapping unaligned 484 loads are slow. */ 485 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX 486 487 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present 488 in power7, so conditionalize them on p8 features. TImode syncs need quad 489 memory support. */ 490 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ 491 || TARGET_QUAD_MEMORY_ATOMIC \ 492 || TARGET_DIRECT_MOVE) 493 494 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC 495 496 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need 497 to allocate the SDmode stack slot to get the value into the proper location 498 in the register. */ 499 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) 500 501 /* ISA 3.0 has new min/max functions that don't need fast math that are being 502 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct 503 answers if the arguments are not in the normal range. */ 504 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ 505 && (TARGET_P9_MINMAX || !flag_trapping_math)) 506 507 /* In switching from using target_flags to using rs6000_isa_flags, the options 508 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map 509 OPTION_MASK_<xxx> back into MASK_<xxx>. */ 510 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC 511 #define MASK_CMPB OPTION_MASK_CMPB 512 #define MASK_CRYPTO OPTION_MASK_CRYPTO 513 #define MASK_DFP OPTION_MASK_DFP 514 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE 515 #define MASK_DLMZB OPTION_MASK_DLMZB 516 #define MASK_EABI OPTION_MASK_EABI 517 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD 518 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW 519 #define MASK_FPRND OPTION_MASK_FPRND 520 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION 521 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT 522 #define MASK_HTM OPTION_MASK_HTM 523 #define MASK_ISEL OPTION_MASK_ISEL 524 #define MASK_MFCRF OPTION_MASK_MFCRF 525 #define MASK_MMA OPTION_MASK_MMA 526 #define MASK_MULHW OPTION_MASK_MULHW 527 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE 528 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE 529 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR 530 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR 531 #define MASK_P9_MISC OPTION_MASK_P9_MISC 532 #define MASK_POPCNTB OPTION_MASK_POPCNTB 533 #define MASK_POPCNTD OPTION_MASK_POPCNTD 534 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT 535 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT 536 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION 537 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT 538 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN 539 #define MASK_UPDATE OPTION_MASK_UPDATE 540 #define MASK_VSX OPTION_MASK_VSX 541 #define MASK_POWER10 OPTION_MASK_POWER10 542 543 #ifndef IN_LIBGCC2 544 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 545 #endif 546 547 #ifdef TARGET_64BIT 548 #define MASK_64BIT OPTION_MASK_64BIT 549 #endif 550 551 #ifdef TARGET_LITTLE_ENDIAN 552 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN 553 #endif 554 555 #ifdef TARGET_REGNAMES 556 #define MASK_REGNAMES OPTION_MASK_REGNAMES 557 #endif 558 559 #ifdef TARGET_PROTOTYPE 560 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE 561 #endif 562 563 #ifdef TARGET_MODULO 564 #define RS6000_BTM_MODULO OPTION_MASK_MODULO 565 #endif 566 567 568 /* For power systems, we want to enable Altivec and VSX builtins even if the 569 user did not use -maltivec or -mvsx to allow the builtins to be used inside 570 of #pragma GCC target or the target attribute to change the code level for a 571 given system. */ 572 573 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ 574 || TARGET_PPC_GPOPT /* 970/power4 */ \ 575 || TARGET_POPCNTB /* ISA 2.02 */ \ 576 || TARGET_CMPB /* ISA 2.05 */ \ 577 || TARGET_POPCNTD /* ISA 2.06 */ \ 578 || TARGET_ALTIVEC \ 579 || TARGET_VSX \ 580 || TARGET_HARD_FLOAT) 581 582 /* E500 cores only support plain "sync", not lwsync. */ 583 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ 584 || rs6000_cpu == PROCESSOR_PPC8548) 585 586 587 /* Which machine supports the various reciprocal estimate instructions. */ 588 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) 589 590 #define TARGET_FRE (TARGET_HARD_FLOAT \ 591 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) 592 593 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ 594 && TARGET_PPC_GFXOPT) 595 596 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ 597 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) 598 599 /* Macro to say whether we can do optimizations where we need to do parts of 600 the calculation in 64-bit GPRs and then is transfered to the vector 601 registers. */ 602 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ 603 && TARGET_P8_VECTOR \ 604 && TARGET_POWERPC64) 605 606 /* Whether the various reciprocal divide/square root estimate instructions 607 exist, and whether we should automatically generate code for the instruction 608 by default. */ 609 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ 610 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ 611 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ 612 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ 613 614 extern unsigned char rs6000_recip_bits[]; 615 616 #define RS6000_RECIP_HAVE_RE_P(MODE) \ 617 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) 618 619 #define RS6000_RECIP_AUTO_RE_P(MODE) \ 620 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) 621 622 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ 623 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) 624 625 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ 626 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) 627 628 /* The default CPU for TARGET_OPTION_OVERRIDE. */ 629 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT 630 631 /* Target pragma. */ 632 #define REGISTER_TARGET_PRAGMAS() do { \ 633 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 634 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ 635 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 636 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ 637 } while (0) 638 639 /* Target #defines. */ 640 #define TARGET_CPU_CPP_BUILTINS() \ 641 rs6000_cpu_cpp_builtins (pfile) 642 643 /* Target CPU versions for D. */ 644 #define TARGET_D_CPU_VERSIONS rs6000_d_target_versions 645 646 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 647 we're compiling for. Some configurations may need to override it. */ 648 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 649 do \ 650 { \ 651 if (BYTES_BIG_ENDIAN) \ 652 { \ 653 builtin_define ("__BIG_ENDIAN__"); \ 654 builtin_define ("_BIG_ENDIAN"); \ 655 builtin_assert ("machine=bigendian"); \ 656 } \ 657 else \ 658 { \ 659 builtin_define ("__LITTLE_ENDIAN__"); \ 660 builtin_define ("_LITTLE_ENDIAN"); \ 661 builtin_assert ("machine=littleendian"); \ 662 } \ 663 } \ 664 while (0) 665 666 /* Target machine storage layout. */ 667 668 /* Define this macro if it is advisable to hold scalars in registers 669 in a wider mode than that declared by the program. In such cases, 670 the value is constrained to be within the bounds of the declared 671 type, but kept valid in the wider mode. The signedness of the 672 extension may differ from that of the type. */ 673 674 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 675 if (GET_MODE_CLASS (MODE) == MODE_INT \ 676 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ 677 (MODE) = TARGET_32BIT ? SImode : DImode; 678 679 /* Define this if most significant bit is lowest numbered 680 in instructions that operate on numbered bit-fields. */ 681 /* That is true on RS/6000. */ 682 #define BITS_BIG_ENDIAN 1 683 684 /* Define this if most significant byte of a word is the lowest numbered. */ 685 /* That is true on RS/6000. */ 686 #define BYTES_BIG_ENDIAN 1 687 688 /* Define this if most significant word of a multiword number is lowest 689 numbered. 690 691 For RS/6000 we can decide arbitrarily since there are no machine 692 instructions for them. Might as well be consistent with bits and bytes. */ 693 #define WORDS_BIG_ENDIAN 1 694 695 /* This says that for the IBM long double the larger magnitude double 696 comes first. It's really a two element double array, and arrays 697 don't index differently between little- and big-endian. */ 698 #define LONG_DOUBLE_LARGE_FIRST 1 699 700 #define MAX_BITS_PER_WORD 64 701 702 /* Width of a word, in units (bytes). */ 703 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 704 #ifdef IN_LIBGCC2 705 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 706 #else 707 #define MIN_UNITS_PER_WORD 4 708 #endif 709 #define UNITS_PER_FP_WORD 8 710 #define UNITS_PER_ALTIVEC_WORD 16 711 #define UNITS_PER_VSX_WORD 16 712 713 /* Type used for ptrdiff_t, as a string used in a declaration. */ 714 #define PTRDIFF_TYPE "int" 715 716 /* Type used for size_t, as a string used in a declaration. */ 717 #define SIZE_TYPE "long unsigned int" 718 719 /* Type used for wchar_t, as a string used in a declaration. */ 720 #define WCHAR_TYPE "short unsigned int" 721 722 /* Width of wchar_t in bits. */ 723 #define WCHAR_TYPE_SIZE 16 724 725 /* A C expression for the size in bits of the type `short' on the 726 target machine. If you don't define this, the default is half a 727 word. (If this would be less than one storage unit, it is 728 rounded up to one unit.) */ 729 #define SHORT_TYPE_SIZE 16 730 731 /* A C expression for the size in bits of the type `int' on the 732 target machine. If you don't define this, the default is one 733 word. */ 734 #define INT_TYPE_SIZE 32 735 736 /* A C expression for the size in bits of the type `long' on the 737 target machine. If you don't define this, the default is one 738 word. */ 739 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 740 741 /* A C expression for the size in bits of the type `long long' on the 742 target machine. If you don't define this, the default is two 743 words. */ 744 #define LONG_LONG_TYPE_SIZE 64 745 746 /* A C expression for the size in bits of the type `float' on the 747 target machine. If you don't define this, the default is one 748 word. */ 749 #define FLOAT_TYPE_SIZE 32 750 751 /* A C expression for the size in bits of the type `double' on the 752 target machine. If you don't define this, the default is two 753 words. */ 754 #define DOUBLE_TYPE_SIZE 64 755 756 /* A C expression for the size in bits of the type `long double' on the target 757 machine. If you don't define this, the default is two words. */ 758 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 759 760 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 761 #define WIDEST_HARDWARE_FP_SIZE 64 762 763 /* Width in bits of a pointer. 764 See also the macro `Pmode' defined below. */ 765 extern unsigned rs6000_pointer_size; 766 #define POINTER_SIZE rs6000_pointer_size 767 768 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 769 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 770 771 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 772 #define STACK_BOUNDARY \ 773 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ 774 ? 64 : 128) 775 776 /* Allocation boundary (in *bits*) for the code of a function. */ 777 #define FUNCTION_BOUNDARY 32 778 779 /* No data type is required to be aligned rounder than this. Warning, if 780 BIGGEST_ALIGNMENT is changed, then this may be an ABI break. An example 781 of where this can break an ABI is in GLIBC's struct _Unwind_Exception. */ 782 #define BIGGEST_ALIGNMENT 128 783 784 /* Alignment of field after `int : 0' in a structure. */ 785 #define EMPTY_FIELD_BOUNDARY 32 786 787 /* Every structure's size must be a multiple of this. */ 788 #define STRUCTURE_SIZE_BOUNDARY 8 789 790 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 791 #define PCC_BITFIELD_TYPE_MATTERS 1 792 793 enum data_align { align_abi, align_opt, align_both }; 794 795 /* A C expression to compute the alignment for a variables in the 796 local store. TYPE is the data type, and ALIGN is the alignment 797 that the object would ordinarily have. */ 798 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 799 rs6000_data_alignment (TYPE, ALIGN, align_both) 800 801 /* Make arrays of chars word-aligned for the same reasons. */ 802 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 803 rs6000_data_alignment (TYPE, ALIGN, align_opt) 804 805 /* Align vectors to 128 bits. */ 806 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 807 rs6000_data_alignment (TYPE, ALIGN, align_abi) 808 809 /* Nonzero if move instructions will actually fail to work 810 when given unaligned data. */ 811 #define STRICT_ALIGNMENT 0 812 813 /* Standard register usage. */ 814 815 /* Number of actual hardware registers. 816 The hardware registers are assigned numbers for the compiler 817 from 0 to just below FIRST_PSEUDO_REGISTER. 818 All registers that the compiler knows about must be given numbers, 819 even those that are not normally considered general registers. 820 821 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 822 a count register, a link register, and 8 condition register fields, 823 which we view here as separate registers. AltiVec adds 32 vector 824 registers and a VRsave register. 825 826 In addition, the difference between the frame and argument pointers is 827 a function of the number of registers saved, so we need to have a 828 register for AP that will later be eliminated in favor of SP or FP. 829 This is a normal register, but it is fixed. 830 831 We also create a pseudo register for float/int conversions, that will 832 really represent the memory location used. It is represented here as 833 a register, in order to work around problems in allocating stack storage 834 in inline functions. 835 836 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 837 pointer, which is eventually eliminated in favor of SP or FP. */ 838 839 #define FIRST_PSEUDO_REGISTER 111 840 841 /* Use standard DWARF numbering for DWARF debugging information. */ 842 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) 843 844 /* Use gcc hard register numbering for eh_frame. */ 845 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) 846 847 /* Map register numbers held in the call frame info that gcc has 848 collected using DWARF_FRAME_REGNUM to those that should be output in 849 .debug_frame and .eh_frame. */ 850 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 851 rs6000_dbx_register_number ((REGNO), (FOR_EH) ? 2 : 1) 852 853 /* 1 for registers that have pervasive standard uses 854 and are not available for the register allocator. 855 856 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 857 as a local register; for all other OS's r2 is the TOC pointer. 858 859 On System V implementations, r13 is fixed and not available for use. */ 860 861 #define FIXED_REGISTERS \ 862 {/* GPRs */ \ 863 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 864 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 865 /* FPRs */ \ 866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 868 /* VRs */ \ 869 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 870 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 871 /* lr ctr ca ap */ \ 872 0, 0, 1, 1, \ 873 /* cr0..cr7 */ \ 874 0, 0, 0, 0, 0, 0, 0, 0, \ 875 /* vrsave vscr sfp */ \ 876 1, 1, 1 \ 877 } 878 879 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that 880 the entire set of `FIXED_REGISTERS' be included. 881 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 882 This macro is optional. If not specified, it defaults to the value 883 of `CALL_USED_REGISTERS'. */ 884 885 #define CALL_REALLY_USED_REGISTERS \ 886 {/* GPRs */ \ 887 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 888 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 889 /* FPRs */ \ 890 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 891 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 892 /* VRs */ \ 893 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 894 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 895 /* lr ctr ca ap */ \ 896 1, 1, 1, 1, \ 897 /* cr0..cr7 */ \ 898 1, 1, 0, 0, 0, 1, 1, 1, \ 899 /* vrsave vscr sfp */ \ 900 0, 0, 0 \ 901 } 902 903 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 904 905 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 906 #define FIRST_SAVED_FP_REGNO (14+32) 907 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) 908 909 /* List the order in which to allocate registers. Each register must be 910 listed once, even those in FIXED_REGISTERS. 911 912 We allocate in the following order: 913 fp0 (not saved or used for anything) 914 fp13 - fp2 (not saved; incoming fp arg registers) 915 fp1 (not saved; return value) 916 fp31 - fp14 (saved; order given to save least number) 917 cr7, cr5 (not saved or special) 918 cr6 (not saved, but used for vector operations) 919 cr1 (not saved, but used for FP operations) 920 cr0 (not saved, but used for arithmetic operations) 921 cr4, cr3, cr2 (saved) 922 r9 (not saved; best for TImode) 923 r10, r8-r4 (not saved; highest first for less conflict with params) 924 r3 (not saved; return value register) 925 r11 (not saved; later alloc to help shrink-wrap) 926 r0 (not saved; cannot be base reg) 927 r31 - r13 (saved; order given to save least number) 928 r12 (not saved; if used for DImode or DFmode would use r13) 929 ctr (not saved; when we have the choice ctr is better) 930 lr (saved) 931 r1, r2, ap, ca (fixed) 932 v0 - v1 (not saved or used for anything) 933 v13 - v3 (not saved; incoming vector arg registers) 934 v2 (not saved; incoming vector arg reg; return value) 935 v19 - v14 (not saved or used for anything) 936 v31 - v20 (saved; order given to save least number) 937 vrsave, vscr (fixed) 938 sfp (fixed) 939 */ 940 941 #if FIXED_R2 == 1 942 #define MAYBE_R2_AVAILABLE 943 #define MAYBE_R2_FIXED 2, 944 #else 945 #define MAYBE_R2_AVAILABLE 2, 946 #define MAYBE_R2_FIXED 947 #endif 948 949 #if FIXED_R13 == 1 950 #define EARLY_R12 12, 951 #define LATE_R12 952 #else 953 #define EARLY_R12 954 #define LATE_R12 12, 955 #endif 956 957 #define REG_ALLOC_ORDER \ 958 {32, \ 959 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ 960 /* not use fr14 which is a saved register. */ \ 961 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ 962 33, \ 963 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 964 50, 49, 48, 47, 46, \ 965 100, 107, 105, 106, 101, 104, 103, 102, \ 966 MAYBE_R2_AVAILABLE \ 967 9, 10, 8, 7, 6, 5, 4, \ 968 3, EARLY_R12 11, 0, \ 969 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 970 18, 17, 16, 15, 14, 13, LATE_R12 \ 971 97, 96, \ 972 1, MAYBE_R2_FIXED 99, 98, \ 973 /* AltiVec registers. */ \ 974 64, 65, \ 975 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \ 976 66, \ 977 83, 82, 81, 80, 79, 78, \ 978 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \ 979 108, 109, \ 980 110 \ 981 } 982 983 /* True if register is floating-point. */ 984 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 985 986 /* True if register is a condition register. */ 987 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) 988 989 /* True if register is a condition register, but not cr0. */ 990 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) 991 992 /* True if register is an integer register. */ 993 #define INT_REGNO_P(N) \ 994 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 995 996 /* True if register is the CA register. */ 997 #define CA_REGNO_P(N) ((N) == CA_REGNO) 998 999 /* True if register is an AltiVec register. */ 1000 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 1001 1002 /* True if register is a VSX register. */ 1003 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) 1004 1005 /* Alternate name for any vector register supporting floating point, no matter 1006 which instruction set(s) are available. */ 1007 #define VFLOAT_REGNO_P(N) \ 1008 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) 1009 1010 /* Alternate name for any vector register supporting integer, no matter which 1011 instruction set(s) are available. */ 1012 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) 1013 1014 /* Alternate name for any vector register supporting logical operations, no 1015 matter which instruction set(s) are available. Allow GPRs as well as the 1016 vector registers. */ 1017 #define VLOGICAL_REGNO_P(N) \ 1018 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ 1019 || (TARGET_VSX && FP_REGNO_P (N))) \ 1020 1021 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate 1022 enough space to account for vectors in FP regs. However, TFmode/TDmode 1023 should not use VSX instructions to do a caller save. */ 1024 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1025 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ 1026 ? (MODE) \ 1027 : TARGET_VSX \ 1028 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ 1029 && FP_REGNO_P (REGNO) \ 1030 ? V2DFmode \ 1031 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ 1032 ? DFmode \ 1033 : (MODE) == TDmode && FP_REGNO_P (REGNO) \ 1034 ? DImode \ 1035 : choose_hard_reg_mode ((REGNO), (NREGS), NULL)) 1036 1037 #define VSX_VECTOR_MODE(MODE) \ 1038 ((MODE) == V4SFmode \ 1039 || (MODE) == V2DFmode) \ 1040 1041 /* Modes that are not vectors, but require vector alignment. Treat these like 1042 vectors in terms of loads and stores. */ 1043 #define VECTOR_ALIGNMENT_P(MODE) \ 1044 (FLOAT128_VECTOR_P (MODE) || (MODE) == POImode || (MODE) == PXImode) 1045 1046 #define ALTIVEC_VECTOR_MODE(MODE) \ 1047 ((MODE) == V16QImode \ 1048 || (MODE) == V8HImode \ 1049 || (MODE) == V4SFmode \ 1050 || (MODE) == V4SImode \ 1051 || VECTOR_ALIGNMENT_P (MODE)) 1052 1053 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1054 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1055 || (MODE) == V2DImode || (MODE) == V1TImode) 1056 1057 /* Post-reload, we can't use any new AltiVec registers, as we already 1058 emitted the vrsave mask. */ 1059 1060 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1061 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) 1062 1063 /* Specify the cost of a branch insn; roughly the number of extra insns that 1064 should be added to avoid a branch. 1065 1066 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1067 unscheduled conditional branch. */ 1068 1069 #define BRANCH_COST(speed_p, predictable_p) 3 1070 1071 /* Override BRANCH_COST heuristic which empirically produces worse 1072 performance for removing short circuiting from the logical ops. */ 1073 1074 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1075 1076 /* Specify the registers used for certain standard purposes. 1077 The values of these macros are register numbers. */ 1078 1079 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1080 /* #define PC_REGNUM */ 1081 1082 /* Register to use for pushing function arguments. */ 1083 #define STACK_POINTER_REGNUM 1 1084 1085 /* Base register for access to local variables of the function. */ 1086 #define HARD_FRAME_POINTER_REGNUM 31 1087 1088 /* Base register for access to local variables of the function. */ 1089 #define FRAME_POINTER_REGNUM 110 1090 1091 /* Base register for access to arguments of the function. */ 1092 #define ARG_POINTER_REGNUM 99 1093 1094 /* Place to put static chain when calling a function that requires it. */ 1095 #define STATIC_CHAIN_REGNUM 11 1096 1097 /* Base register for access to thread local storage variables. */ 1098 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) 1099 1100 1101 /* Define the classes of registers for register constraints in the 1102 machine description. Also define ranges of constants. 1103 1104 One of the classes must always be named ALL_REGS and include all hard regs. 1105 If there is more than one class, another class must be named NO_REGS 1106 and contain no registers. 1107 1108 The name GENERAL_REGS must be the name of a class (or an alias for 1109 another name such as ALL_REGS). This is the class of registers 1110 that is allowed by "g" or "r" in a register constraint. 1111 Also, registers outside this class are allocated only when 1112 instructions express preferences for them. 1113 1114 The classes must be numbered in nondecreasing order; that is, 1115 a larger-numbered class must never be contained completely 1116 in a smaller-numbered class. 1117 1118 For any two classes, it is very desirable that there be another 1119 class that represents their union. */ 1120 1121 /* The RS/6000 has three types of registers, fixed-point, floating-point, and 1122 condition registers, plus three special registers, CTR, and the link 1123 register. AltiVec adds a vector register class. VSX registers overlap the 1124 FPR registers and the Altivec registers. 1125 1126 However, r0 is special in that it cannot be used as a base register. 1127 So make a class for registers valid as base registers. 1128 1129 Also, cr0 is the only condition code register that can be used in 1130 arithmetic insns, so make a separate class for it. */ 1131 1132 enum reg_class 1133 { 1134 NO_REGS, 1135 BASE_REGS, 1136 GENERAL_REGS, 1137 FLOAT_REGS, 1138 ALTIVEC_REGS, 1139 VSX_REGS, 1140 VRSAVE_REGS, 1141 VSCR_REGS, 1142 GEN_OR_FLOAT_REGS, 1143 GEN_OR_VSX_REGS, 1144 LINK_REGS, 1145 CTR_REGS, 1146 LINK_OR_CTR_REGS, 1147 SPECIAL_REGS, 1148 SPEC_OR_GEN_REGS, 1149 CR0_REGS, 1150 CR_REGS, 1151 NON_FLOAT_REGS, 1152 CA_REGS, 1153 ALL_REGS, 1154 LIM_REG_CLASSES 1155 }; 1156 1157 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1158 1159 /* Give names of register classes as strings for dump file. */ 1160 1161 #define REG_CLASS_NAMES \ 1162 { \ 1163 "NO_REGS", \ 1164 "BASE_REGS", \ 1165 "GENERAL_REGS", \ 1166 "FLOAT_REGS", \ 1167 "ALTIVEC_REGS", \ 1168 "VSX_REGS", \ 1169 "VRSAVE_REGS", \ 1170 "VSCR_REGS", \ 1171 "GEN_OR_FLOAT_REGS", \ 1172 "GEN_OR_VSX_REGS", \ 1173 "LINK_REGS", \ 1174 "CTR_REGS", \ 1175 "LINK_OR_CTR_REGS", \ 1176 "SPECIAL_REGS", \ 1177 "SPEC_OR_GEN_REGS", \ 1178 "CR0_REGS", \ 1179 "CR_REGS", \ 1180 "NON_FLOAT_REGS", \ 1181 "CA_REGS", \ 1182 "ALL_REGS" \ 1183 } 1184 1185 /* Define which registers fit in which classes. 1186 This is an initializer for a vector of HARD_REG_SET 1187 of length N_REG_CLASSES. */ 1188 1189 #define REG_CLASS_CONTENTS \ 1190 { \ 1191 /* NO_REGS. */ \ 1192 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1193 /* BASE_REGS. */ \ 1194 { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \ 1195 /* GENERAL_REGS. */ \ 1196 { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \ 1197 /* FLOAT_REGS. */ \ 1198 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ 1199 /* ALTIVEC_REGS. */ \ 1200 { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \ 1201 /* VSX_REGS. */ \ 1202 { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ 1203 /* VRSAVE_REGS. */ \ 1204 { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \ 1205 /* VSCR_REGS. */ \ 1206 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ 1207 /* GEN_OR_FLOAT_REGS. */ \ 1208 { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \ 1209 /* GEN_OR_VSX_REGS. */ \ 1210 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \ 1211 /* LINK_REGS. */ \ 1212 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \ 1213 /* CTR_REGS. */ \ 1214 { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \ 1215 /* LINK_OR_CTR_REGS. */ \ 1216 { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \ 1217 /* SPECIAL_REGS. */ \ 1218 { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \ 1219 /* SPEC_OR_GEN_REGS. */ \ 1220 { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \ 1221 /* CR0_REGS. */ \ 1222 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \ 1223 /* CR_REGS. */ \ 1224 { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \ 1225 /* NON_FLOAT_REGS. */ \ 1226 { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \ 1227 /* CA_REGS. */ \ 1228 { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \ 1229 /* ALL_REGS. */ \ 1230 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \ 1231 } 1232 1233 /* The same information, inverted: 1234 Return the class number of the smallest class containing 1235 reg number REGNO. This could be a conditional expression 1236 or could index an array. */ 1237 1238 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; 1239 1240 #define REGNO_REG_CLASS(REGNO) \ 1241 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ 1242 rs6000_regno_regclass[(REGNO)]) 1243 1244 /* Register classes for various constraints that are based on the target 1245 switches. */ 1246 enum r6000_reg_class_enum { 1247 RS6000_CONSTRAINT_d, /* fpr registers for double values */ 1248 RS6000_CONSTRAINT_f, /* fpr registers for single values */ 1249 RS6000_CONSTRAINT_v, /* Altivec registers */ 1250 RS6000_CONSTRAINT_wa, /* Any VSX register */ 1251 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ 1252 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ 1253 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ 1254 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ 1255 RS6000_CONSTRAINT_MAX 1256 }; 1257 1258 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; 1259 1260 /* The class value for index registers, and the one for base regs. */ 1261 #define INDEX_REG_CLASS GENERAL_REGS 1262 #define BASE_REG_CLASS BASE_REGS 1263 1264 /* Return whether a given register class can hold VSX objects. */ 1265 #define VSX_REG_CLASS_P(CLASS) \ 1266 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) 1267 1268 /* Return whether a given register class targets general purpose registers. */ 1269 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) 1270 1271 /* Given an rtx X being reloaded into a reg required to be 1272 in class CLASS, return the class of reg to actually use. 1273 In general this is just CLASS; but on some machines 1274 in some cases it is preferable to use a more restrictive class. 1275 1276 On the RS/6000, we have to return NO_REGS when we want to reload a 1277 floating-point CONST_DOUBLE to force it to be copied to memory. 1278 1279 We also don't want to reload integer values into floating-point 1280 registers if we can at all help it. In fact, this can 1281 cause reload to die, if it tries to generate a reload of CTR 1282 into a FP register and discovers it doesn't have the memory location 1283 required. 1284 1285 ??? Would it be a good idea to have reload do the converse, that is 1286 try to reload floating modes into FP registers if possible? 1287 */ 1288 1289 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1290 rs6000_preferred_reload_class_ptr (X, CLASS) 1291 1292 /* Return the register class of a scratch register needed to copy IN into 1293 or out of a register in CLASS in MODE. If it can be done directly, 1294 NO_REGS is returned. */ 1295 1296 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1297 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) 1298 1299 /* Return the maximum number of consecutive registers 1300 needed to represent mode MODE in a register of class CLASS. 1301 1302 On RS/6000, this is the size of MODE in words, except in the FP regs, where 1303 a single reg is enough for two words, unless we have VSX, where the FP 1304 registers can hold 128 bits. */ 1305 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] 1306 1307 /* Stack layout; function entry, exit and calling. */ 1308 1309 /* Define this if pushing a word on the stack 1310 makes the stack pointer a smaller address. */ 1311 #define STACK_GROWS_DOWNWARD 1 1312 1313 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1314 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1315 1316 /* Define this to nonzero if the nominal address of the stack frame 1317 is at the high-address end of the local variables; 1318 that is, each additional local variable allocated 1319 goes at a more negative offset in the frame. 1320 1321 On the RS/6000, we grow upwards, from the area after the outgoing 1322 arguments. */ 1323 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ 1324 || (flag_sanitize & SANITIZE_ADDRESS) != 0) 1325 1326 /* Size of the fixed area on the stack */ 1327 #define RS6000_SAVE_AREA \ 1328 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ 1329 << (TARGET_64BIT ? 1 : 0)) 1330 1331 /* Stack offset for toc save slot. */ 1332 #define RS6000_TOC_SAVE_SLOT \ 1333 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) 1334 1335 /* Align an address */ 1336 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) 1337 1338 /* Offset within stack frame to start allocating local variables at. 1339 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1340 first local allocated. Otherwise, it is the offset to the BEGINNING 1341 of the first local allocated. 1342 1343 On the RS/6000, the frame pointer is the same as the stack pointer, 1344 except for dynamic allocations. So we start after the fixed area and 1345 outgoing parameter area. 1346 1347 If the function uses dynamic stack space (CALLS_ALLOCA is set), that 1348 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the 1349 sizes of the fixed area and the parameter area must be a multiple of 1350 STACK_BOUNDARY. */ 1351 1352 #define RS6000_STARTING_FRAME_OFFSET \ 1353 (cfun->calls_alloca \ 1354 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ 1355 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ 1356 : (RS6000_ALIGN (crtl->outgoing_args_size, \ 1357 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1358 + RS6000_SAVE_AREA)) 1359 1360 /* Offset from the stack pointer register to an item dynamically 1361 allocated on the stack, e.g., by `alloca'. 1362 1363 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1364 length of the outgoing arguments. The default is correct for most 1365 machines. See `function.c' for details. 1366 1367 This value must be a multiple of STACK_BOUNDARY (hard coded in 1368 `emit-rtl.c'). */ 1369 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1370 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ 1371 + STACK_POINTER_OFFSET, \ 1372 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) 1373 1374 /* If we generate an insn to push BYTES bytes, 1375 this says how many the stack pointer really advances by. 1376 On RS/6000, don't define this because there are no push insns. */ 1377 /* #define PUSH_ROUNDING(BYTES) */ 1378 1379 /* Offset of first parameter from the argument pointer register value. 1380 On the RS/6000, we define the argument pointer to the start of the fixed 1381 area. */ 1382 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1383 1384 /* Offset from the argument pointer register value to the top of 1385 stack. This is different from FIRST_PARM_OFFSET because of the 1386 register save area. */ 1387 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1388 1389 /* Define this if stack space is still allocated for a parameter passed 1390 in a register. The value is the number of bytes allocated to this 1391 area. */ 1392 #define REG_PARM_STACK_SPACE(FNDECL) \ 1393 rs6000_reg_parm_stack_space ((FNDECL), false) 1394 1395 /* Define this macro if space guaranteed when compiling a function body 1396 is different to space required when making a call, a situation that 1397 can arise with K&R style function definitions. */ 1398 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ 1399 rs6000_reg_parm_stack_space ((FNDECL), true) 1400 1401 /* Define this if the above stack space is to be considered part of the 1402 space allocated by the caller. */ 1403 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 1404 1405 /* This is the difference between the logical top of stack and the actual sp. 1406 1407 For the RS/6000, sp points past the fixed area. */ 1408 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1409 1410 /* Define this if the maximum size of all the outgoing args is to be 1411 accumulated and pushed during the prologue. The amount can be 1412 found in the variable crtl->outgoing_args_size. */ 1413 #define ACCUMULATE_OUTGOING_ARGS 1 1414 1415 /* Define how to find the value returned by a library function 1416 assuming the value has mode MODE. */ 1417 1418 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1419 1420 /* DRAFT_V4_STRUCT_RET defaults off. */ 1421 #define DRAFT_V4_STRUCT_RET 0 1422 1423 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1424 #define DEFAULT_PCC_STRUCT_RETURN 0 1425 1426 /* Mode of stack savearea. 1427 FUNCTION is VOIDmode because calling convention maintains SP. 1428 BLOCK needs Pmode for SP. 1429 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1430 #define STACK_SAVEAREA_MODE(LEVEL) \ 1431 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1432 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) 1433 1434 /* Minimum and maximum general purpose registers used to hold arguments. */ 1435 #define GP_ARG_MIN_REG 3 1436 #define GP_ARG_MAX_REG 10 1437 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1438 1439 /* Minimum and maximum floating point registers used to hold arguments. */ 1440 #define FP_ARG_MIN_REG 33 1441 #define FP_ARG_AIX_MAX_REG 45 1442 #define FP_ARG_V4_MAX_REG 40 1443 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ 1444 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) 1445 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1446 1447 /* Minimum and maximum AltiVec registers used to hold arguments. */ 1448 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1449 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1450 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1451 1452 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ 1453 #define AGGR_ARG_NUM_REG 8 1454 1455 /* Return registers */ 1456 #define GP_ARG_RETURN GP_ARG_MIN_REG 1457 #define FP_ARG_RETURN FP_ARG_MIN_REG 1458 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1459 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ 1460 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1461 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ 1462 ? (ALTIVEC_ARG_RETURN \ 1463 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ 1464 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1465 1466 /* Flags for the call/call_value rtl operations set up by function_arg */ 1467 #define CALL_NORMAL 0x00000000 /* no special processing */ 1468 /* Bits in 0x00000001 are unused. */ 1469 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1470 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1471 #define CALL_LONG 0x00000008 /* always call indirect */ 1472 #define CALL_LIBCALL 0x00000010 /* libcall */ 1473 1474 /* Identify PLT sequence for rs6000_pltseq_template. */ 1475 enum rs6000_pltseq_enum { 1476 RS6000_PLTSEQ_TOCSAVE, 1477 RS6000_PLTSEQ_PLT16_HA, 1478 RS6000_PLTSEQ_PLT16_LO, 1479 RS6000_PLTSEQ_MTCTR, 1480 RS6000_PLTSEQ_PLT_PCREL34 1481 }; 1482 1483 #define IS_V4_FP_ARGS(OP) \ 1484 ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0) 1485 1486 /* We don't have prologue and epilogue functions to save/restore 1487 everything for most ABIs. */ 1488 #define WORLD_SAVE_P(INFO) 0 1489 1490 /* 1 if N is a possible register number for a function value 1491 as seen by the caller. 1492 1493 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1494 #define FUNCTION_VALUE_REGNO_P(N) \ 1495 ((N) == GP_ARG_RETURN \ 1496 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ 1497 && TARGET_HARD_FLOAT) \ 1498 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ 1499 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1500 1501 /* 1 if N is a possible register number for function argument passing. 1502 On RS/6000, these are r3-r10 and fp1-fp13. 1503 On AltiVec, v2 - v13 are used for passing vectors. */ 1504 #define FUNCTION_ARG_REGNO_P(N) \ 1505 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ 1506 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ 1507 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1508 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ 1509 && TARGET_HARD_FLOAT)) 1510 1511 /* Define a data type for recording info about an argument list 1512 during the scan of that argument list. This data type should 1513 hold all necessary information about the function itself 1514 and about the args processed so far, enough to enable macros 1515 such as FUNCTION_ARG to determine where the next arg should go. 1516 1517 On the RS/6000, this is a structure. The first element is the number of 1518 total argument words, the second is used to store the next 1519 floating-point register number, and the third says how many more args we 1520 have prototype types for. 1521 1522 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1523 the next available GP register, `fregno' is the next available FP 1524 register, and `words' is the number of words used on the stack. 1525 1526 The varargs/stdarg support requires that this structure's size 1527 be a multiple of sizeof(int). */ 1528 1529 typedef struct rs6000_args 1530 { 1531 int words; /* # words used for passing GP registers */ 1532 int fregno; /* next available FP register */ 1533 int vregno; /* next available AltiVec register */ 1534 int nargs_prototype; /* # args left in the current prototype */ 1535 int prototype; /* Whether a prototype was defined */ 1536 int stdarg; /* Whether function is a stdarg function. */ 1537 int call_cookie; /* Do special things for this call */ 1538 int sysv_gregno; /* next available GP register */ 1539 int intoffset; /* running offset in struct (darwin64) */ 1540 int use_stack; /* any part of struct on stack (darwin64) */ 1541 int floats_in_gpr; /* count of SFmode floats taking up 1542 GPR space (darwin64) */ 1543 int named; /* false for varargs params */ 1544 int escapes; /* if function visible outside tu */ 1545 int libcall; /* If this is a compiler generated call. */ 1546 } CUMULATIVE_ARGS; 1547 1548 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1549 for a call to a function whose data type is FNTYPE. 1550 For a library call, FNTYPE is 0. */ 1551 1552 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1553 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ 1554 N_NAMED_ARGS, FNDECL, VOIDmode) 1555 1556 /* Similar, but when scanning the definition of a procedure. We always 1557 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1558 1559 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1560 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ 1561 1000, current_function_decl, VOIDmode) 1562 1563 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1564 1565 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1566 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ 1567 0, NULL_TREE, MODE) 1568 1569 #define PAD_VARARGS_DOWN \ 1570 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) 1571 1572 /* Output assembler code to FILE to increment profiler label # LABELNO 1573 for profiling a function entry. */ 1574 1575 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1576 output_function_profiler ((FILE), (LABELNO)); 1577 1578 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1579 the stack pointer does not matter. No definition is equivalent to 1580 always zero. 1581 1582 On the RS/6000, this is nonzero because we can restore the stack from 1583 its backpointer, which we maintain. */ 1584 #define EXIT_IGNORE_STACK 1 1585 1586 /* Define this macro as a C expression that is nonzero for registers 1587 that are used by the epilogue or the return' pattern. The stack 1588 and frame pointer registers are already be assumed to be used as 1589 needed. */ 1590 1591 #define EPILOGUE_USES(REGNO) \ 1592 ((reload_completed && (REGNO) == LR_REGNO) \ 1593 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1594 || (crtl->calls_eh_return \ 1595 && TARGET_AIX \ 1596 && (REGNO) == 2)) 1597 1598 1599 /* Length in units of the trampoline for entering a nested function. */ 1600 1601 #define TRAMPOLINE_SIZE rs6000_trampoline_size () 1602 1603 /* Definitions for __builtin_return_address and __builtin_frame_address. 1604 __builtin_return_address (0) should give link register (LR_REGNO), enable 1605 this. */ 1606 /* This should be uncommented, so that the link register is used, but 1607 currently this would result in unmatched insns and spilling fixed 1608 registers so we'll leave it for another day. When these problems are 1609 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1610 (mrs) */ 1611 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1612 1613 /* Number of bytes into the frame return addresses can be found. See 1614 rs6000_stack_info in rs6000.c for more information on how the different 1615 abi's store the return address. */ 1616 #define RETURN_ADDRESS_OFFSET \ 1617 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) 1618 1619 /* The current return address is in the link register. The return address 1620 of anything farther back is accessed normally at an offset of 8 from the 1621 frame pointer. */ 1622 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1623 (rs6000_return_addr (COUNT, FRAME)) 1624 1625 1626 /* Definitions for register eliminations. 1627 1628 We have two registers that can be eliminated on the RS/6000. First, the 1629 frame pointer register can often be eliminated in favor of the stack 1630 pointer register. Secondly, the argument pointer register can always be 1631 eliminated; it is replaced with either the stack or frame pointer. 1632 1633 In addition, we use the elimination mechanism to see if r30 is needed 1634 Initially we assume that it isn't. If it is, we spill it. This is done 1635 by making it an eliminable register. We replace it with itself so that 1636 if it isn't needed, then existing uses won't be modified. */ 1637 1638 /* This is an array of structures. Each structure initializes one pair 1639 of eliminable registers. The "from" register number is given first, 1640 followed by "to". Eliminations of the same "from" register are listed 1641 in order of preference. */ 1642 #define ELIMINABLE_REGS \ 1643 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1644 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1645 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1646 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1647 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1648 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1649 1650 /* Define the offset between two registers, one to be eliminated, and the other 1651 its replacement, at the start of a routine. */ 1652 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1653 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1654 1655 /* Addressing modes, and classification of registers for them. */ 1656 1657 #define HAVE_PRE_DECREMENT 1 1658 #define HAVE_PRE_INCREMENT 1 1659 #define HAVE_PRE_MODIFY_DISP 1 1660 #define HAVE_PRE_MODIFY_REG 1 1661 1662 /* Macros to check register numbers against specific register classes. */ 1663 1664 /* These assume that REGNO is a hard or pseudo reg number. 1665 They give nonzero only if REGNO is a hard reg of the suitable class 1666 or a pseudo reg currently allocated to a suitable hard reg. 1667 Since they use reg_renumber, they are safe only once reg_renumber 1668 has been allocated, which happens in reginfo.c during register 1669 allocation. */ 1670 1671 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1672 (HARD_REGISTER_NUM_P (REGNO) \ 1673 ? (REGNO) <= 31 \ 1674 || (REGNO) == ARG_POINTER_REGNUM \ 1675 || (REGNO) == FRAME_POINTER_REGNUM \ 1676 : (reg_renumber[REGNO] >= 0 \ 1677 && (reg_renumber[REGNO] <= 31 \ 1678 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ 1679 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1680 1681 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1682 (HARD_REGISTER_NUM_P (REGNO) \ 1683 ? ((REGNO) > 0 && (REGNO) <= 31) \ 1684 || (REGNO) == ARG_POINTER_REGNUM \ 1685 || (REGNO) == FRAME_POINTER_REGNUM \ 1686 : (reg_renumber[REGNO] > 0 \ 1687 && (reg_renumber[REGNO] <= 31 \ 1688 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ 1689 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1690 1691 /* Nonzero if X is a hard reg that can be used as an index 1692 or if it is a pseudo reg in the non-strict case. */ 1693 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1694 ((!(STRICT) && !HARD_REGISTER_P (X)) \ 1695 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1696 1697 /* Nonzero if X is a hard reg that can be used as a base reg 1698 or if it is a pseudo reg in the non-strict case. */ 1699 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1700 ((!(STRICT) && !HARD_REGISTER_P (X)) \ 1701 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1702 1703 1704 /* Maximum number of registers that can appear in a valid memory address. */ 1705 1706 #define MAX_REGS_PER_ADDRESS 2 1707 1708 /* Recognize any constant value that is a valid address. */ 1709 1710 #define CONSTANT_ADDRESS_P(X) \ 1711 (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \ 1712 || CONST_INT_P (X) || GET_CODE (X) == CONST \ 1713 || GET_CODE (X) == HIGH) 1714 1715 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1716 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1717 && EASY_VECTOR_15((n) >> 1) \ 1718 && ((n) & 1) == 0) 1719 1720 #define EASY_VECTOR_MSB(n,mode) \ 1721 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ 1722 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) 1723 1724 1725 #define FIND_BASE_TERM rs6000_find_base_term 1726 1727 /* The register number of the register used to address a table of 1728 static data addresses in memory. In some cases this register is 1729 defined by a processor's "application binary interface" (ABI). 1730 When this macro is defined, RTL is generated for this register 1731 once, as with the stack pointer and frame pointer registers. If 1732 this macro is not defined, it is up to the machine-dependent files 1733 to allocate such a register (if necessary). */ 1734 1735 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1736 #define PIC_OFFSET_TABLE_REGNUM \ 1737 (TARGET_TOC ? TOC_REGISTER \ 1738 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ 1739 : INVALID_REGNUM) 1740 1741 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1742 1743 /* Define this macro if the register defined by 1744 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1745 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1746 1747 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1748 1749 /* A C expression that is nonzero if X is a legitimate immediate 1750 operand on the target machine when generating position independent 1751 code. You can assume that X satisfies `CONSTANT_P', so you need 1752 not check this. You can also assume FLAG_PIC is true, so you need 1753 not check it either. You need not define this macro if all 1754 constants (including `SYMBOL_REF') can be immediate operands when 1755 generating position independent code. */ 1756 1757 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ 1758 1759 /* Specify the machine mode that this machine uses 1760 for the index in the tablejump instruction. */ 1761 #define CASE_VECTOR_MODE SImode 1762 1763 /* Define as C expression which evaluates to nonzero if the tablejump 1764 instruction expects the table to contain offsets from the address of the 1765 table. 1766 Do not define this if the table should contain absolute addresses. */ 1767 #define CASE_VECTOR_PC_RELATIVE 1 1768 1769 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1770 #define DEFAULT_SIGNED_CHAR 0 1771 1772 /* An integer expression for the size in bits of the largest integer machine 1773 mode that should actually be used. */ 1774 1775 /* Allow pairs of registers to be used, which is the intent of the default. */ 1776 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 1777 1778 /* Max number of bytes we can move from memory to memory 1779 in one reasonably fast instruction. */ 1780 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 1781 #define MAX_MOVE_MAX 8 1782 1783 /* Nonzero if access to memory by bytes is no faster than for words. 1784 Also nonzero if doing byte operations (specifically shifts) in registers 1785 is undesirable. */ 1786 #define SLOW_BYTE_ACCESS 1 1787 1788 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1789 will either zero-extend or sign-extend. The value of this macro should 1790 be the code that says which one of the two operations is implicitly 1791 done, UNKNOWN if none. */ 1792 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1793 1794 /* Define if loading short immediate values into registers sign extends. */ 1795 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 1796 1797 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 1798 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1799 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) 1800 1801 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of 1802 zero. The hardware instructions added in Power9 and the sequences using 1803 popcount return 32 or 64. */ 1804 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1805 (TARGET_CTZ || TARGET_POPCNTD \ 1806 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ 1807 : ((VALUE) = -1, 2)) 1808 1809 /* Specify the machine mode that pointers have. 1810 After generation of rtl, the compiler makes no further distinction 1811 between pointers and any other objects of this machine mode. */ 1812 extern scalar_int_mode rs6000_pmode; 1813 #define Pmode rs6000_pmode 1814 1815 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 1816 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 1817 1818 /* Mode of a function address in a call instruction (for indexing purposes). 1819 Doesn't matter on RS/6000. */ 1820 #define FUNCTION_MODE SImode 1821 1822 /* Define this if addresses of constant functions 1823 shouldn't be put through pseudo regs where they can be cse'd. 1824 Desirable on machines where ordinary constants are expensive 1825 but a CALL with constant address is cheap. */ 1826 #define NO_FUNCTION_CSE 1 1827 1828 /* Define this to be nonzero if shift instructions ignore all but the low-order 1829 few bits. 1830 1831 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 1832 have been dropped from the PowerPC architecture. */ 1833 #define SHIFT_COUNT_TRUNCATED 0 1834 1835 /* Adjust the length of an INSN. LENGTH is the currently-computed length and 1836 should be adjusted to reflect any required changes. This macro is used when 1837 there is some systematic length adjustment required that would be difficult 1838 to express in the length attribute. 1839 1840 In the PowerPC, we use this to adjust the length of an instruction if one or 1841 more prefixed instructions are generated, using the attribute 1842 num_prefixed_insns. A prefixed instruction is 8 bytes instead of 4, but the 1843 hardware requires that a prefied instruciton does not cross a 64-byte 1844 boundary. This means the compiler has to assume the length of the first 1845 prefixed instruction is 12 bytes instead of 8 bytes. Since the length is 1846 already set for the non-prefixed instruction, we just need to udpate for the 1847 difference. */ 1848 1849 #define ADJUST_INSN_LENGTH(INSN,LENGTH) \ 1850 (LENGTH) = rs6000_adjust_insn_length ((INSN), (LENGTH)) 1851 1852 /* Given a comparison code (EQ, NE, etc.) and the first operand of a 1853 COMPARE, return the mode to be used for the comparison. For 1854 floating-point, CCFPmode should be used. CCUNSmode should be used 1855 for unsigned comparisons. CCEQmode should be used when we are 1856 doing an inequality comparison on the result of a 1857 comparison. CCmode should be used in all other cases. */ 1858 1859 #define SELECT_CC_MODE(OP,X,Y) \ 1860 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 1861 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 1862 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 1863 ? CCEQmode : CCmode)) 1864 1865 /* Can the condition code MODE be safely reversed? This is safe in 1866 all cases on this port, because at present it doesn't use the 1867 trapping FP comparisons (fcmpo). */ 1868 #define REVERSIBLE_CC_MODE(MODE) 1 1869 1870 /* Given a condition code and a mode, return the inverse condition. */ 1871 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 1872 1873 1874 /* Target cpu costs. */ 1875 1876 struct processor_costs { 1877 const int mulsi; /* cost of SImode multiplication. */ 1878 const int mulsi_const; /* cost of SImode multiplication by constant. */ 1879 const int mulsi_const9; /* cost of SImode mult by short constant. */ 1880 const int muldi; /* cost of DImode multiplication. */ 1881 const int divsi; /* cost of SImode division. */ 1882 const int divdi; /* cost of DImode division. */ 1883 const int fp; /* cost of simple SFmode and DFmode insns. */ 1884 const int dmul; /* cost of DFmode multiplication (and fmadd). */ 1885 const int sdiv; /* cost of SFmode division (fdivs). */ 1886 const int ddiv; /* cost of DFmode division (fdiv). */ 1887 const int cache_line_size; /* cache line size in bytes. */ 1888 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 1889 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 1890 const int simultaneous_prefetches; /* number of parallel prefetch 1891 operations. */ 1892 const int sfdf_convert; /* cost of SF->DF conversion. */ 1893 }; 1894 1895 extern const struct processor_costs *rs6000_cost; 1896 1897 /* Control the assembler format that we output. */ 1898 1899 /* A C string constant describing how to begin a comment in the target 1900 assembler language. The compiler assumes that the comment will end at 1901 the end of the line. */ 1902 #define ASM_COMMENT_START " #" 1903 1904 /* Flag to say the TOC is initialized */ 1905 extern int toc_initialized; 1906 1907 /* Macro to output a special constant pool entry. Go to WIN if we output 1908 it. Otherwise, it is written the usual way. 1909 1910 On the RS/6000, toc entries are handled this way. */ 1911 1912 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 1913 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 1914 { \ 1915 output_toc (FILE, X, LABELNO, MODE); \ 1916 goto WIN; \ 1917 } \ 1918 } 1919 1920 #ifdef HAVE_GAS_WEAK 1921 #define RS6000_WEAK 1 1922 #else 1923 #define RS6000_WEAK 0 1924 #endif 1925 1926 #if RS6000_WEAK 1927 /* Used in lieu of ASM_WEAKEN_LABEL. */ 1928 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 1929 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) 1930 #endif 1931 1932 #if HAVE_GAS_WEAKREF 1933 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 1934 do \ 1935 { \ 1936 fputs ("\t.weakref\t", (FILE)); \ 1937 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1938 fputs (", ", (FILE)); \ 1939 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1940 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 1941 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1942 { \ 1943 fputs ("\n\t.weakref\t.", (FILE)); \ 1944 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1945 fputs (", .", (FILE)); \ 1946 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1947 } \ 1948 fputc ('\n', (FILE)); \ 1949 } while (0) 1950 #endif 1951 1952 /* This implements the `alias' attribute. */ 1953 #undef ASM_OUTPUT_DEF_FROM_DECLS 1954 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 1955 do \ 1956 { \ 1957 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 1958 const char *name = IDENTIFIER_POINTER (TARGET); \ 1959 if (TREE_CODE (DECL) == FUNCTION_DECL \ 1960 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1961 { \ 1962 if (TREE_PUBLIC (DECL)) \ 1963 { \ 1964 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 1965 { \ 1966 fputs ("\t.globl\t.", FILE); \ 1967 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1968 putc ('\n', FILE); \ 1969 } \ 1970 } \ 1971 else if (TARGET_XCOFF) \ 1972 { \ 1973 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 1974 { \ 1975 fputs ("\t.lglobl\t.", FILE); \ 1976 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1977 putc ('\n', FILE); \ 1978 fputs ("\t.lglobl\t", FILE); \ 1979 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1980 putc ('\n', FILE); \ 1981 } \ 1982 } \ 1983 fputs ("\t.set\t.", FILE); \ 1984 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1985 fputs (",.", FILE); \ 1986 RS6000_OUTPUT_BASENAME (FILE, name); \ 1987 fputc ('\n', FILE); \ 1988 } \ 1989 ASM_OUTPUT_DEF (FILE, alias, name); \ 1990 } \ 1991 while (0) 1992 1993 #define TARGET_ASM_FILE_START rs6000_file_start 1994 1995 /* Output to assembler file text saying following lines 1996 may contain character constants, extra white space, comments, etc. */ 1997 1998 #define ASM_APP_ON "" 1999 2000 /* Output to assembler file text saying following lines 2001 no longer contain unusual constructs. */ 2002 2003 #define ASM_APP_OFF "" 2004 2005 /* How to refer to registers in assembler output. 2006 This sequence is indexed by compiler's hard-register-number (see above). */ 2007 2008 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2009 2010 #define REGISTER_NAMES \ 2011 { \ 2012 &rs6000_reg_names[ 0][0], /* r0 */ \ 2013 &rs6000_reg_names[ 1][0], /* r1 */ \ 2014 &rs6000_reg_names[ 2][0], /* r2 */ \ 2015 &rs6000_reg_names[ 3][0], /* r3 */ \ 2016 &rs6000_reg_names[ 4][0], /* r4 */ \ 2017 &rs6000_reg_names[ 5][0], /* r5 */ \ 2018 &rs6000_reg_names[ 6][0], /* r6 */ \ 2019 &rs6000_reg_names[ 7][0], /* r7 */ \ 2020 &rs6000_reg_names[ 8][0], /* r8 */ \ 2021 &rs6000_reg_names[ 9][0], /* r9 */ \ 2022 &rs6000_reg_names[10][0], /* r10 */ \ 2023 &rs6000_reg_names[11][0], /* r11 */ \ 2024 &rs6000_reg_names[12][0], /* r12 */ \ 2025 &rs6000_reg_names[13][0], /* r13 */ \ 2026 &rs6000_reg_names[14][0], /* r14 */ \ 2027 &rs6000_reg_names[15][0], /* r15 */ \ 2028 &rs6000_reg_names[16][0], /* r16 */ \ 2029 &rs6000_reg_names[17][0], /* r17 */ \ 2030 &rs6000_reg_names[18][0], /* r18 */ \ 2031 &rs6000_reg_names[19][0], /* r19 */ \ 2032 &rs6000_reg_names[20][0], /* r20 */ \ 2033 &rs6000_reg_names[21][0], /* r21 */ \ 2034 &rs6000_reg_names[22][0], /* r22 */ \ 2035 &rs6000_reg_names[23][0], /* r23 */ \ 2036 &rs6000_reg_names[24][0], /* r24 */ \ 2037 &rs6000_reg_names[25][0], /* r25 */ \ 2038 &rs6000_reg_names[26][0], /* r26 */ \ 2039 &rs6000_reg_names[27][0], /* r27 */ \ 2040 &rs6000_reg_names[28][0], /* r28 */ \ 2041 &rs6000_reg_names[29][0], /* r29 */ \ 2042 &rs6000_reg_names[30][0], /* r30 */ \ 2043 &rs6000_reg_names[31][0], /* r31 */ \ 2044 \ 2045 &rs6000_reg_names[32][0], /* fr0 */ \ 2046 &rs6000_reg_names[33][0], /* fr1 */ \ 2047 &rs6000_reg_names[34][0], /* fr2 */ \ 2048 &rs6000_reg_names[35][0], /* fr3 */ \ 2049 &rs6000_reg_names[36][0], /* fr4 */ \ 2050 &rs6000_reg_names[37][0], /* fr5 */ \ 2051 &rs6000_reg_names[38][0], /* fr6 */ \ 2052 &rs6000_reg_names[39][0], /* fr7 */ \ 2053 &rs6000_reg_names[40][0], /* fr8 */ \ 2054 &rs6000_reg_names[41][0], /* fr9 */ \ 2055 &rs6000_reg_names[42][0], /* fr10 */ \ 2056 &rs6000_reg_names[43][0], /* fr11 */ \ 2057 &rs6000_reg_names[44][0], /* fr12 */ \ 2058 &rs6000_reg_names[45][0], /* fr13 */ \ 2059 &rs6000_reg_names[46][0], /* fr14 */ \ 2060 &rs6000_reg_names[47][0], /* fr15 */ \ 2061 &rs6000_reg_names[48][0], /* fr16 */ \ 2062 &rs6000_reg_names[49][0], /* fr17 */ \ 2063 &rs6000_reg_names[50][0], /* fr18 */ \ 2064 &rs6000_reg_names[51][0], /* fr19 */ \ 2065 &rs6000_reg_names[52][0], /* fr20 */ \ 2066 &rs6000_reg_names[53][0], /* fr21 */ \ 2067 &rs6000_reg_names[54][0], /* fr22 */ \ 2068 &rs6000_reg_names[55][0], /* fr23 */ \ 2069 &rs6000_reg_names[56][0], /* fr24 */ \ 2070 &rs6000_reg_names[57][0], /* fr25 */ \ 2071 &rs6000_reg_names[58][0], /* fr26 */ \ 2072 &rs6000_reg_names[59][0], /* fr27 */ \ 2073 &rs6000_reg_names[60][0], /* fr28 */ \ 2074 &rs6000_reg_names[61][0], /* fr29 */ \ 2075 &rs6000_reg_names[62][0], /* fr30 */ \ 2076 &rs6000_reg_names[63][0], /* fr31 */ \ 2077 \ 2078 &rs6000_reg_names[64][0], /* vr0 */ \ 2079 &rs6000_reg_names[65][0], /* vr1 */ \ 2080 &rs6000_reg_names[66][0], /* vr2 */ \ 2081 &rs6000_reg_names[67][0], /* vr3 */ \ 2082 &rs6000_reg_names[68][0], /* vr4 */ \ 2083 &rs6000_reg_names[69][0], /* vr5 */ \ 2084 &rs6000_reg_names[70][0], /* vr6 */ \ 2085 &rs6000_reg_names[71][0], /* vr7 */ \ 2086 &rs6000_reg_names[72][0], /* vr8 */ \ 2087 &rs6000_reg_names[73][0], /* vr9 */ \ 2088 &rs6000_reg_names[74][0], /* vr10 */ \ 2089 &rs6000_reg_names[75][0], /* vr11 */ \ 2090 &rs6000_reg_names[76][0], /* vr12 */ \ 2091 &rs6000_reg_names[77][0], /* vr13 */ \ 2092 &rs6000_reg_names[78][0], /* vr14 */ \ 2093 &rs6000_reg_names[79][0], /* vr15 */ \ 2094 &rs6000_reg_names[80][0], /* vr16 */ \ 2095 &rs6000_reg_names[81][0], /* vr17 */ \ 2096 &rs6000_reg_names[82][0], /* vr18 */ \ 2097 &rs6000_reg_names[83][0], /* vr19 */ \ 2098 &rs6000_reg_names[84][0], /* vr20 */ \ 2099 &rs6000_reg_names[85][0], /* vr21 */ \ 2100 &rs6000_reg_names[86][0], /* vr22 */ \ 2101 &rs6000_reg_names[87][0], /* vr23 */ \ 2102 &rs6000_reg_names[88][0], /* vr24 */ \ 2103 &rs6000_reg_names[89][0], /* vr25 */ \ 2104 &rs6000_reg_names[90][0], /* vr26 */ \ 2105 &rs6000_reg_names[91][0], /* vr27 */ \ 2106 &rs6000_reg_names[92][0], /* vr28 */ \ 2107 &rs6000_reg_names[93][0], /* vr29 */ \ 2108 &rs6000_reg_names[94][0], /* vr30 */ \ 2109 &rs6000_reg_names[95][0], /* vr31 */ \ 2110 \ 2111 &rs6000_reg_names[96][0], /* lr */ \ 2112 &rs6000_reg_names[97][0], /* ctr */ \ 2113 &rs6000_reg_names[98][0], /* ca */ \ 2114 &rs6000_reg_names[99][0], /* ap */ \ 2115 \ 2116 &rs6000_reg_names[100][0], /* cr0 */ \ 2117 &rs6000_reg_names[101][0], /* cr1 */ \ 2118 &rs6000_reg_names[102][0], /* cr2 */ \ 2119 &rs6000_reg_names[103][0], /* cr3 */ \ 2120 &rs6000_reg_names[104][0], /* cr4 */ \ 2121 &rs6000_reg_names[105][0], /* cr5 */ \ 2122 &rs6000_reg_names[106][0], /* cr6 */ \ 2123 &rs6000_reg_names[107][0], /* cr7 */ \ 2124 \ 2125 &rs6000_reg_names[108][0], /* vrsave */ \ 2126 &rs6000_reg_names[109][0], /* vscr */ \ 2127 \ 2128 &rs6000_reg_names[110][0] /* sfp */ \ 2129 } 2130 2131 /* Table of additional register names to use in user input. */ 2132 2133 #define ADDITIONAL_REGISTER_NAMES \ 2134 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2135 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2136 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2137 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2138 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2139 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2140 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2141 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2142 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2143 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2144 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2145 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2146 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2147 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2148 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2149 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2150 {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \ 2151 {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \ 2152 {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \ 2153 {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \ 2154 {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \ 2155 {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \ 2156 {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \ 2157 {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \ 2158 {"vrsave", 108}, {"vscr", 109}, \ 2159 /* no additional names for: lr, ctr, ap */ \ 2160 {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \ 2161 {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \ 2162 {"cc", 100},{"sp", 1}, {"toc", 2}, \ 2163 /* CA is only part of XER, but we do not model the other parts (yet). */ \ 2164 {"xer", 98}, \ 2165 /* VSX registers overlaid on top of FR, Altivec registers */ \ 2166 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ 2167 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ 2168 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ 2169 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ 2170 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ 2171 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ 2172 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ 2173 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ 2174 {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \ 2175 {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \ 2176 {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \ 2177 {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \ 2178 {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \ 2179 {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \ 2180 {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \ 2181 {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \ 2182 } 2183 2184 /* This is how to output an element of a case-vector that is relative. */ 2185 2186 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2187 do { char buf[100]; \ 2188 fputs ("\t.long ", FILE); \ 2189 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2190 assemble_name (FILE, buf); \ 2191 putc ('-', FILE); \ 2192 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2193 assemble_name (FILE, buf); \ 2194 putc ('\n', FILE); \ 2195 } while (0) 2196 2197 /* This is how to output an assembler line 2198 that says to advance the location counter 2199 to a multiple of 2**LOG bytes. */ 2200 2201 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2202 if ((LOG) != 0) \ 2203 fprintf (FILE, "\t.align %d\n", (LOG)) 2204 2205 /* How to align the given loop. */ 2206 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) 2207 2208 /* Alignment guaranteed by __builtin_malloc. */ 2209 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. 2210 However, specifying the stronger guarantee currently leads to 2211 a regression in SPEC CPU2006 437.leslie3d. The stronger 2212 guarantee should be implemented here once that's fixed. */ 2213 #define MALLOC_ABI_ALIGNMENT (64) 2214 2215 /* Pick up the return address upon entry to a procedure. Used for 2216 dwarf2 unwind information. This also enables the table driven 2217 mechanism. */ 2218 2219 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) 2220 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) 2221 2222 /* Describe how we implement __builtin_eh_return. */ 2223 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2224 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2225 2226 /* Print operand X (an rtx) in assembler syntax to file FILE. 2227 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2228 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2229 2230 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2231 2232 /* Define which CODE values are valid. */ 2233 2234 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') 2235 2236 /* Print a memory address as an operand to reference that memory location. */ 2237 2238 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2239 2240 /* For switching between functions with different target attributes. */ 2241 #define SWITCHABLE_TARGET 1 2242 2243 /* uncomment for disabling the corresponding default options */ 2244 /* #define MACHINE_no_sched_interblock */ 2245 /* #define MACHINE_no_sched_speculative */ 2246 /* #define MACHINE_no_sched_speculative_load */ 2247 2248 /* General flags. */ 2249 extern int frame_pointer_needed; 2250 2251 /* Classification of the builtin functions as to which switches enable the 2252 builtin, and what attributes it should have. We used to use the target 2253 flags macros, but we've run out of bits, so we now map the options into new 2254 settings used here. */ 2255 2256 /* Builtin operand count. */ 2257 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ 2258 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ 2259 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ 2260 #define RS6000_BTC_QUATERNARY 0x00000004 /* normal quaternary 2261 function. */ 2262 #define RS6000_BTC_QUINARY 0x00000005 /* normal quinary function. */ 2263 #define RS6000_BTC_SENARY 0x00000006 /* normal senary function. */ 2264 #define RS6000_BTC_OPND_MASK 0x00000007 /* Mask to isolate operands. */ 2265 2266 /* Builtin attributes. */ 2267 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ 2268 #define RS6000_BTC_PREDICATE 0x00000008 /* predicate function. */ 2269 #define RS6000_BTC_ABS 0x00000010 /* Altivec/VSX ABS 2270 function. */ 2271 #define RS6000_BTC_DST 0x00000020 /* Altivec DST function. */ 2272 2273 #define RS6000_BTC_TYPE_MASK 0x0000003f /* Mask to isolate types */ 2274 2275 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ 2276 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor 2277 modifies global state. */ 2278 #define RS6000_BTC_PURE 0x00000200 /* reads global 2279 state/mem and does 2280 not modify global state. */ 2281 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ 2282 #define RS6000_BTC_QUAD 0x00000800 /* Uses a register quad. */ 2283 #define RS6000_BTC_PAIR 0x00001000 /* Uses a register pair. */ 2284 #define RS6000_BTC_QUADPAIR 0x00001800 /* Uses a quad and a pair. */ 2285 #define RS6000_BTC_ATTR_MASK 0x00001f00 /* Mask of the attributes. */ 2286 2287 /* Miscellaneous information. */ 2288 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ 2289 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ 2290 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ 2291 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ 2292 #define RS6000_BTC_GIMPLE 0x10000000 /* function should be expanded 2293 into gimple. */ 2294 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ 2295 2296 /* Convenience macros to document the instruction type. */ 2297 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ 2298 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ 2299 2300 /* Builtin targets. For now, we reuse the masks for those options that are in 2301 target flags, and pick a random bit for ldbl128, which isn't in 2302 target_flags. */ 2303 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ 2304 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ 2305 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ 2306 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ 2307 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ 2308 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ 2309 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ 2310 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ 2311 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ 2312 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ 2313 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ 2314 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ 2315 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ 2316 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ 2317 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ 2318 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ 2319 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ 2320 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ 2321 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ 2322 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ 2323 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ 2324 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ 2325 #define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */ 2326 #define RS6000_BTM_P10 MASK_POWER10 2327 2328 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ 2329 | RS6000_BTM_VSX \ 2330 | RS6000_BTM_P8_VECTOR \ 2331 | RS6000_BTM_P9_VECTOR \ 2332 | RS6000_BTM_P9_MISC \ 2333 | RS6000_BTM_MODULO \ 2334 | RS6000_BTM_CRYPTO \ 2335 | RS6000_BTM_FRE \ 2336 | RS6000_BTM_FRES \ 2337 | RS6000_BTM_FRSQRTE \ 2338 | RS6000_BTM_FRSQRTES \ 2339 | RS6000_BTM_HTM \ 2340 | RS6000_BTM_POPCNTD \ 2341 | RS6000_BTM_CELL \ 2342 | RS6000_BTM_DFP \ 2343 | RS6000_BTM_HARD_FLOAT \ 2344 | RS6000_BTM_LDBL128 \ 2345 | RS6000_BTM_POWERPC64 \ 2346 | RS6000_BTM_FLOAT128 \ 2347 | RS6000_BTM_FLOAT128_HW \ 2348 | RS6000_BTM_MMA \ 2349 | RS6000_BTM_P10) 2350 2351 /* Define builtin enum index. */ 2352 2353 #undef RS6000_BUILTIN_0 2354 #undef RS6000_BUILTIN_1 2355 #undef RS6000_BUILTIN_2 2356 #undef RS6000_BUILTIN_3 2357 #undef RS6000_BUILTIN_A 2358 #undef RS6000_BUILTIN_D 2359 #undef RS6000_BUILTIN_H 2360 #undef RS6000_BUILTIN_M 2361 #undef RS6000_BUILTIN_P 2362 #undef RS6000_BUILTIN_X 2363 2364 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2365 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2366 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2367 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2368 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2369 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2370 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2371 #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2372 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2373 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2374 2375 enum rs6000_builtins 2376 { 2377 #include "rs6000-builtin.def" 2378 2379 RS6000_BUILTIN_COUNT 2380 }; 2381 2382 #undef RS6000_BUILTIN_0 2383 #undef RS6000_BUILTIN_1 2384 #undef RS6000_BUILTIN_2 2385 #undef RS6000_BUILTIN_3 2386 #undef RS6000_BUILTIN_A 2387 #undef RS6000_BUILTIN_D 2388 #undef RS6000_BUILTIN_H 2389 #undef RS6000_BUILTIN_M 2390 #undef RS6000_BUILTIN_P 2391 #undef RS6000_BUILTIN_X 2392 2393 /* Mappings for overloaded builtins. */ 2394 struct altivec_builtin_types 2395 { 2396 enum rs6000_builtins code; 2397 enum rs6000_builtins overloaded_code; 2398 signed char ret_type; 2399 signed char op1; 2400 signed char op2; 2401 signed char op3; 2402 }; 2403 extern const struct altivec_builtin_types altivec_overloaded_builtins[]; 2404 2405 enum rs6000_builtin_type_index 2406 { 2407 RS6000_BTI_NOT_OPAQUE, 2408 RS6000_BTI_opaque_V4SI, 2409 RS6000_BTI_V16QI, /* __vector signed char */ 2410 RS6000_BTI_V1TI, 2411 RS6000_BTI_V2DI, 2412 RS6000_BTI_V2DF, 2413 RS6000_BTI_V4HI, 2414 RS6000_BTI_V4SI, 2415 RS6000_BTI_V4SF, 2416 RS6000_BTI_V8HI, 2417 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ 2418 RS6000_BTI_unsigned_V1TI, 2419 RS6000_BTI_unsigned_V8HI, 2420 RS6000_BTI_unsigned_V4SI, 2421 RS6000_BTI_unsigned_V2DI, 2422 RS6000_BTI_bool_char, /* __bool char */ 2423 RS6000_BTI_bool_short, /* __bool short */ 2424 RS6000_BTI_bool_int, /* __bool int */ 2425 RS6000_BTI_bool_long_long, /* __bool long long */ 2426 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 2427 channels of 1, 5, 5, and 5 bits 2428 respectively as packed with the 2429 vpkpx insn. __pixel is only 2430 meaningful as a vector type. 2431 There is no corresponding scalar 2432 __pixel data type.) */ 2433 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2434 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2435 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2436 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2437 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2438 RS6000_BTI_long, /* long_integer_type_node */ 2439 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2440 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2441 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2442 RS6000_BTI_INTQI, /* (signed) intQI_type_node */ 2443 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2444 RS6000_BTI_INTHI, /* intHI_type_node */ 2445 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2446 RS6000_BTI_INTSI, /* intSI_type_node (signed) */ 2447 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2448 RS6000_BTI_INTDI, /* intDI_type_node */ 2449 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2450 RS6000_BTI_INTTI, /* intTI_type_node */ 2451 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ 2452 RS6000_BTI_float, /* float_type_node */ 2453 RS6000_BTI_double, /* double_type_node */ 2454 RS6000_BTI_long_double, /* long_double_type_node */ 2455 RS6000_BTI_dfloat64, /* dfloat64_type_node */ 2456 RS6000_BTI_dfloat128, /* dfloat128_type_node */ 2457 RS6000_BTI_void, /* void_type_node */ 2458 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ 2459 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ 2460 RS6000_BTI_const_str, /* pointer to const char * */ 2461 RS6000_BTI_vector_pair, /* unsigned 256-bit types (vector pair). */ 2462 RS6000_BTI_vector_quad, /* unsigned 512-bit types (vector quad). */ 2463 RS6000_BTI_MAX 2464 }; 2465 2466 2467 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2468 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2469 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) 2470 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2471 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2472 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2473 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2474 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2475 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2476 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2477 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) 2478 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2479 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2480 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2481 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2482 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2483 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2484 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) 2485 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2486 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2487 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2488 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2489 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2490 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2491 2492 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) 2493 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) 2494 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2495 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2496 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2497 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2498 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2499 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2500 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2501 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2502 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) 2503 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) 2504 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) 2505 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) 2506 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2507 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) 2508 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) 2509 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) 2510 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) 2511 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2512 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) 2513 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) 2514 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) 2515 #define vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_vector_pair]) 2516 #define vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_vector_quad]) 2517 2518 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2519 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 2520 2521 #ifndef USED_FOR_TARGET 2522 extern GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2]; 2523 extern GTY(()) tree altivec_builtin_mask_for_load; 2524 extern GTY(()) section *toc_section; 2525 2526 /* A C structure for machine-specific, per-function data. 2527 This is added to the cfun structure. */ 2528 typedef struct GTY(()) machine_function 2529 { 2530 /* Flags if __builtin_return_address (n) with n >= 1 was used. */ 2531 int ra_needs_full_frame; 2532 /* Flags if __builtin_return_address (0) was used. */ 2533 int ra_need_lr; 2534 /* Cache lr_save_p after expansion of builtin_eh_return. */ 2535 int lr_save_state; 2536 /* Whether we need to save the TOC to the reserved stack location in the 2537 function prologue. */ 2538 bool save_toc_in_prologue; 2539 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4 2540 varargs save area. */ 2541 HOST_WIDE_INT varargs_save_offset; 2542 /* Alternative internal arg pointer for -fsplit-stack. */ 2543 rtx split_stack_arg_pointer; 2544 bool split_stack_argp_used; 2545 /* Flag if r2 setup is needed with ELFv2 ABI. */ 2546 bool r2_setup_needed; 2547 /* The number of components we use for separate shrink-wrapping. */ 2548 int n_components; 2549 /* The components already handled by separate shrink-wrapping, which should 2550 not be considered by the prologue and epilogue. */ 2551 bool gpr_is_wrapped_separately[32]; 2552 bool fpr_is_wrapped_separately[32]; 2553 bool lr_is_wrapped_separately; 2554 bool toc_is_wrapped_separately; 2555 } machine_function; 2556 #endif 2557 2558 2559 #define TARGET_SUPPORTS_WIDE_INT 1 2560 2561 #if (GCC_VERSION >= 3000) 2562 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 2563 #endif 2564 2565 /* Whether a given VALUE is a valid 16 or 34-bit signed integer. */ 2566 #define SIGNED_INTEGER_NBIT_P(VALUE, N) \ 2567 IN_RANGE ((VALUE), \ 2568 -(HOST_WIDE_INT_1 << ((N)-1)), \ 2569 (HOST_WIDE_INT_1 << ((N)-1)) - 1) 2570 2571 #define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16) 2572 #define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34) 2573 2574 /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra 2575 argument that gives a length to validate a range of addresses, to allow for 2576 splitting insns into several insns, each of which has an offsettable 2577 address. */ 2578 #define SIGNED_16BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ 2579 IN_RANGE ((VALUE), \ 2580 -(HOST_WIDE_INT_1 << 15), \ 2581 (HOST_WIDE_INT_1 << 15) - 1 - (EXTRA)) 2582 2583 #define SIGNED_34BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ 2584 IN_RANGE ((VALUE), \ 2585 -(HOST_WIDE_INT_1 << 33), \ 2586 (HOST_WIDE_INT_1 << 33) - 1 - (EXTRA)) 2587 2588 /* Define this if some processing needs to be done before outputting the 2589 assembler code. On the PowerPC, we remember if the current insn is a normal 2590 prefixed insn where we need to emit a 'p' before the insn. */ 2591 #define FINAL_PRESCAN_INSN(INSN, OPERANDS, NOPERANDS) \ 2592 do \ 2593 { \ 2594 if (TARGET_PREFIXED) \ 2595 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS); \ 2596 } \ 2597 while (0) 2598 2599 /* Do anything special before emitting an opcode. We use it to emit a 'p' for 2600 prefixed insns that is set in FINAL_PRESCAN_INSN. */ 2601 #define ASM_OUTPUT_OPCODE(STREAM, OPCODE) \ 2602 do \ 2603 { \ 2604 if (TARGET_PREFIXED) \ 2605 rs6000_asm_output_opcode (STREAM); \ 2606 } \ 2607 while (0) 2608