1 /* { dg-do compile { target { powerpc*-*-* } } } */
2 /* { dg-require-effective-target lp64 } */
3 /* { dg-require-effective-target powerpc_p9vector_ok } */
4 /* { dg-options "-O2 -mdejagnu-cpu=power9" } */
5
6 #include <altivec.h>
7
8 vector unsigned int
rlmi_test_1(vector unsigned int x,vector unsigned int y,vector unsigned int z)9 rlmi_test_1 (vector unsigned int x, vector unsigned int y,
10 vector unsigned int z)
11 {
12 return vec_rlmi (x, y, z);
13 }
14
15 vector unsigned long long
rlmi_test_2(vector unsigned long long x,vector unsigned long long y,vector unsigned long long z)16 rlmi_test_2 (vector unsigned long long x, vector unsigned long long y,
17 vector unsigned long long z)
18 {
19 return vec_rlmi (x, y, z);
20 }
21
22 vector unsigned int
vrlnm_test_1(vector unsigned int x,vector unsigned int y)23 vrlnm_test_1 (vector unsigned int x, vector unsigned int y)
24 {
25 return vec_vrlnm (x, y);
26 }
27
28 vector unsigned long long
vrlnm_test_2(vector unsigned long long x,vector unsigned long long y)29 vrlnm_test_2 (vector unsigned long long x, vector unsigned long long y)
30 {
31 return vec_vrlnm (x, y);
32 }
33
34 vector unsigned int
rlnm_test_1(vector unsigned int x,vector unsigned int y,vector unsigned int z)35 rlnm_test_1 (vector unsigned int x, vector unsigned int y,
36 vector unsigned int z)
37 {
38 return vec_rlnm (x, y, z);
39 }
40
41 vector unsigned long long
rlnm_test_2(vector unsigned long long x,vector unsigned long long y,vector unsigned long long z)42 rlnm_test_2 (vector unsigned long long x, vector unsigned long long y,
43 vector unsigned long long z)
44 {
45 return vec_rlnm (x, y, z);
46 }
47
48 /* Expected code generation for rlmi_test_1 is vrlwmi.
49 Expected code generation for rlmi_test_2 is vrldmi.
50 Expected code generation for vrlnm_test_1 is vrlwnm.
51 Expected code generation for vrlnm_test_2 is vrldnm.
52 Expected code generation for the others is more complex, because
53 the second and third arguments are combined by a shift and OR,
54 and because there is no splat-immediate doubleword.
55 - For rlnm_test_1: vspltisw, vslw, xxlor, vrlwnm.
56 - For rlnm_test_2: xxspltib, vextsb2d, vsld, xxlor, vrldnm.
57 There is a choice of splat instructions in both cases, so we
58 just check for "splt". */
59
60 /* { dg-final { scan-assembler-times "vrlwmi" 1 } } */
61 /* { dg-final { scan-assembler-times "vrldmi" 1 } } */
62 /* { dg-final { scan-assembler-times "splt" 2 } } */
63 /* { dg-final { scan-assembler-times "vextsb2d" 1 } } */
64 /* { dg-final { scan-assembler-times "vslw" 1 } } */
65 /* { dg-final { scan-assembler-times "vsld" 1 } } */
66 /* { dg-final { scan-assembler-times "xxlor" 2 } } */
67 /* { dg-final { scan-assembler-times "vrlwnm" 2 } } */
68 /* { dg-final { scan-assembler-times "vrldnm" 2 } } */
69