1 /* Definition of RISC-V target for GNU compiler. 2 Copyright (C) 2011-2021 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman (andrew@sifive.com). 4 Based on MIPS target for GNU compiler. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #ifndef GCC_RISCV_H 23 #define GCC_RISCV_H 24 25 #include "config/riscv/riscv-opts.h" 26 27 /* Target CPU builtins. */ 28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile) 29 30 /* Target hooks for D language. */ 31 #define TARGET_D_CPU_VERSIONS riscv_d_target_versions 32 #define TARGET_D_REGISTER_CPU_TARGET_INFO riscv_d_register_target_info 33 34 #ifdef TARGET_BIG_ENDIAN_DEFAULT 35 #define DEFAULT_ENDIAN_SPEC "b" 36 #else 37 #define DEFAULT_ENDIAN_SPEC "l" 38 #endif 39 40 /* Default target_flags if no switches are specified */ 41 42 #ifndef TARGET_DEFAULT 43 #define TARGET_DEFAULT 0 44 #endif 45 46 #ifndef RISCV_TUNE_STRING_DEFAULT 47 #define RISCV_TUNE_STRING_DEFAULT "rocket" 48 #endif 49 50 extern const char *riscv_expand_arch (int argc, const char **argv); 51 extern const char *riscv_expand_arch_from_cpu (int argc, const char **argv); 52 extern const char *riscv_default_mtune (int argc, const char **argv); 53 54 # define EXTRA_SPEC_FUNCTIONS \ 55 { "riscv_expand_arch", riscv_expand_arch }, \ 56 { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, \ 57 { "riscv_default_mtune", riscv_default_mtune }, 58 59 /* Support for a compile-time default CPU, et cetera. The rules are: 60 --with-arch is ignored if -march or -mcpu is specified. 61 --with-abi is ignored if -mabi is specified. 62 --with-tune is ignored if -mtune or -mcpu is specified. 63 64 But using default -march/-mtune value if -mcpu don't have valid option. */ 65 #define OPTION_DEFAULT_SPECS \ 66 {"tune", "%{!mtune=*:" \ 67 " %{!mcpu=*:-mtune=%(VALUE)}" \ 68 " %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" }, \ 69 {"arch", "%{!march=*:" \ 70 " %{!mcpu=*:-march=%(VALUE)}" \ 71 " %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \ 72 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ 73 74 #ifdef IN_LIBGCC2 75 #undef TARGET_64BIT 76 /* Make this compile time constant for libgcc2 */ 77 #define TARGET_64BIT (__riscv_xlen == 64) 78 #endif /* IN_LIBGCC2 */ 79 80 #ifdef HAVE_AS_MISA_SPEC 81 #define ASM_MISA_SPEC "%{misa-spec=*}" 82 #else 83 #define ASM_MISA_SPEC "" 84 #endif 85 86 /* Reference: 87 https://gcc.gnu.org/onlinedocs/cpp/Stringizing.html#Stringizing */ 88 #define STRINGIZING(s) __STRINGIZING(s) 89 #define __STRINGIZING(s) #s 90 91 #define MULTILIB_DEFAULTS \ 92 {"march=" STRINGIZING (TARGET_RISCV_DEFAULT_ARCH), \ 93 "mabi=" STRINGIZING (TARGET_RISCV_DEFAULT_ABI) } 94 95 #undef ASM_SPEC 96 #define ASM_SPEC "\ 97 %(subtarget_asm_debugging_spec) \ 98 %{" FPIE_OR_FPIC_SPEC ":-fpic} \ 99 %{march=*} \ 100 %{mabi=*} \ 101 %{mbig-endian} \ 102 %{mlittle-endian} \ 103 %(subtarget_asm_spec)" \ 104 ASM_MISA_SPEC 105 106 #undef DRIVER_SELF_SPECS 107 #define DRIVER_SELF_SPECS \ 108 "%{march=*:%:riscv_expand_arch(%*)} " \ 109 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} " 110 111 #define TARGET_DEFAULT_CMODEL CM_MEDLOW 112 113 #define LOCAL_LABEL_PREFIX "." 114 #define USER_LABEL_PREFIX "" 115 116 /* Offsets recorded in opcodes are a multiple of this alignment factor. 117 The default for this in 64-bit mode is 8, which causes problems with 118 SFmode register saves. */ 119 #define DWARF_CIE_DATA_ALIGNMENT -4 120 121 /* The mapping from gcc register number to DWARF 2 CFA column number. */ 122 #define DWARF_FRAME_REGNUM(REGNO) \ 123 (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM) 124 125 /* The DWARF 2 CFA column which tracks the return address. */ 126 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM 127 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM) 128 129 /* Describe how we implement __builtin_eh_return. */ 130 #define EH_RETURN_DATA_REGNO(N) \ 131 ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM) 132 133 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4) 134 135 /* Target machine storage layout */ 136 137 #define BITS_BIG_ENDIAN 0 138 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 139 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 140 141 #define MAX_BITS_PER_WORD 64 142 143 /* Width of a word, in units (bytes). */ 144 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 145 #ifndef IN_LIBGCC2 146 #define MIN_UNITS_PER_WORD 4 147 #endif 148 149 /* The `Q' extension is not yet supported. */ 150 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) 151 152 /* The largest type that can be passed in floating-point registers. */ 153 #define UNITS_PER_FP_ARG \ 154 ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \ 155 || riscv_abi == ABI_LP64) \ 156 ? 0 \ 157 : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8)) 158 159 /* Set the sizes of the core types. */ 160 #define SHORT_TYPE_SIZE 16 161 #define INT_TYPE_SIZE 32 162 #define LONG_LONG_TYPE_SIZE 64 163 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32) 164 #define LONG_TYPE_SIZE POINTER_SIZE 165 166 #define FLOAT_TYPE_SIZE 32 167 #define DOUBLE_TYPE_SIZE 64 168 #define LONG_DOUBLE_TYPE_SIZE 128 169 170 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 171 #define PARM_BOUNDARY BITS_PER_WORD 172 173 /* Allocation boundary (in *bits*) for the code of a function. */ 174 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32) 175 176 /* The smallest supported stack boundary the calling convention supports. */ 177 #define STACK_BOUNDARY \ 178 (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD) 179 180 /* The ABI stack alignment. */ 181 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128) 182 183 /* There is no point aligning anything to a rounder boundary than this. */ 184 #define BIGGEST_ALIGNMENT 128 185 186 /* The user-level ISA permits unaligned accesses, but they are not required 187 of the privileged architecture. */ 188 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 189 190 /* Define this if you wish to imitate the way many other C compilers 191 handle alignment of bitfields and the structures that contain 192 them. 193 194 The behavior is that the type written for a bit-field (`int', 195 `short', or other integer type) imposes an alignment for the 196 entire structure, as if the structure really did contain an 197 ordinary field of that type. In addition, the bit-field is placed 198 within the structure so that it would fit within such a field, 199 not crossing a boundary for it. 200 201 Thus, on most machines, a bit-field whose type is written as `int' 202 would not cross a four-byte boundary, and would force four-byte 203 alignment for the whole structure. (The alignment used may not 204 be four bytes; it is controlled by the other alignment 205 parameters.) 206 207 If the macro is defined, its definition should be a C expression; 208 a nonzero value for the expression enables this behavior. */ 209 210 #define PCC_BITFIELD_TYPE_MATTERS 1 211 212 /* An integer expression for the size in bits of the largest integer machine 213 mode that should actually be used. We allow pairs of registers. */ 214 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 215 216 /* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition. */ 217 #define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN) \ 218 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 219 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 220 || TREE_CODE (TYPE) == UNION_TYPE \ 221 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 222 223 /* If defined, a C expression to compute the alignment for a static 224 variable. TYPE is the data type, and ALIGN is the alignment that 225 the object would ordinarily have. The value of this macro is used 226 instead of that alignment to align the object. 227 228 If this macro is not defined, then ALIGN is used. 229 230 One use of this macro is to increase alignment of medium-size 231 data to make it all fit in fewer cache lines. Another is to 232 cause character arrays to be word-aligned so that `strcpy' calls 233 that copy constants to character arrays can be done inline. */ 234 235 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 236 RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen, \ 237 TYPE, ALIGN) 238 239 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause 240 character arrays to be word-aligned so that `strcpy' calls that copy 241 constants to character arrays can be done inline, and 'strcmp' can be 242 optimised to use word loads. */ 243 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 244 RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN) 245 246 /* Define if operations between registers always perform the operation 247 on the full register even if a narrower mode is specified. */ 248 #define WORD_REGISTER_OPERATIONS 1 249 250 /* When in 64-bit mode, move insns will sign extend SImode and CCmode 251 moves. All other references are zero extended. */ 252 #define LOAD_EXTEND_OP(MODE) \ 253 (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) 254 255 /* Define this macro if it is advisable to hold scalars in registers 256 in a wider mode than that declared by the program. In such cases, 257 the value is constrained to be within the bounds of the declared 258 type, but kept valid in the wider mode. The signedness of the 259 extension may differ from that of the type. */ 260 261 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 262 if (GET_MODE_CLASS (MODE) == MODE_INT \ 263 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 264 { \ 265 if ((MODE) == SImode) \ 266 (UNSIGNEDP) = 0; \ 267 (MODE) = word_mode; \ 268 } 269 270 /* Pmode is always the same as ptr_mode, but not always the same as word_mode. 271 Extensions of pointers to word_mode must be signed. */ 272 #define POINTERS_EXTEND_UNSIGNED false 273 274 /* Define if loading short immediate values into registers sign extends. */ 275 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 276 277 /* Standard register usage. */ 278 279 /* Number of hardware registers. We have: 280 281 - 32 integer registers 282 - 32 floating point registers 283 - 2 fake registers: 284 - ARG_POINTER_REGNUM 285 - FRAME_POINTER_REGNUM */ 286 287 #define FIRST_PSEUDO_REGISTER 66 288 289 /* x0, sp, gp, and tp are fixed. */ 290 291 #define FIXED_REGISTERS \ 292 { /* General registers. */ \ 293 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 294 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 295 /* Floating-point registers. */ \ 296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 298 /* Others. */ \ 299 1, 1 \ 300 } 301 302 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls. 303 The call RTLs themselves clobber ra. */ 304 305 #define CALL_USED_REGISTERS \ 306 { /* General registers. */ \ 307 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ 308 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 309 /* Floating-point registers. */ \ 310 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ 311 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \ 312 /* Others. */ \ 313 1, 1 \ 314 } 315 316 /* Select a register mode required for caller save of hard regno REGNO. 317 Contrary to what is documented, the default is not the smallest suitable 318 mode but the largest suitable mode for the given (REGNO, NREGS) pair and 319 it quickly creates paradoxical subregs that can be problematic. */ 320 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 321 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE)) 322 323 /* Internal macros to classify an ISA register's type. */ 324 325 #define GP_REG_FIRST 0 326 #define GP_REG_LAST (TARGET_RVE ? 15 : 31) 327 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 328 329 #define FP_REG_FIRST 32 330 #define FP_REG_LAST 63 331 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 332 333 /* The DWARF 2 CFA column which tracks the return address from a 334 signal handler context. This means that to maintain backwards 335 compatibility, no hard register can be assigned this column if it 336 would need to be handled by the DWARF unwinder. */ 337 #define DWARF_ALT_FRAME_RETURN_COLUMN 64 338 339 #define GP_REG_P(REGNO) \ 340 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) 341 #define FP_REG_P(REGNO) \ 342 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) 343 344 /* True when REGNO is in SIBCALL_REGS set. */ 345 #define SIBCALL_REG_P(REGNO) \ 346 TEST_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], REGNO) 347 348 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) 349 350 /* Use s0 as the frame pointer if it is so requested. */ 351 #define HARD_FRAME_POINTER_REGNUM 8 352 #define STACK_POINTER_REGNUM 2 353 #define THREAD_POINTER_REGNUM 4 354 355 /* These two registers don't really exist: they get eliminated to either 356 the stack or hard frame pointer. */ 357 #define ARG_POINTER_REGNUM 64 358 #define FRAME_POINTER_REGNUM 65 359 360 /* Register in which static-chain is passed to a function. */ 361 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2) 362 363 /* Registers used as temporaries in prologue/epilogue code. 364 365 The prologue registers mustn't conflict with any 366 incoming arguments, the static chain pointer, or the frame pointer. 367 The epilogue temporary mustn't conflict with the return registers, 368 the frame pointer, the EH stack adjustment, or the EH data registers. */ 369 370 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST) 371 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM) 372 373 #define RISCV_CALL_ADDRESS_TEMP_REGNUM (GP_TEMP_FIRST + 1) 374 #define RISCV_CALL_ADDRESS_TEMP(MODE) \ 375 gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM) 376 377 #define MCOUNT_NAME "_mcount" 378 379 #define NO_PROFILE_COUNTERS 1 380 381 /* Emit rtl for profiling. Output assembler code to FILE 382 to call "_mcount" for profiling a function entry. */ 383 #define PROFILE_HOOK(LABEL) \ 384 { \ 385 rtx fun, ra; \ 386 ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \ 387 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 388 emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \ 389 } 390 391 /* All the work done in PROFILE_HOOK, but still required. */ 392 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 393 394 /* Define this macro if it is as good or better to call a constant 395 function address than to call an address kept in a register. */ 396 #define NO_FUNCTION_CSE 1 397 398 /* Define the classes of registers for register constraints in the 399 machine description. Also define ranges of constants. 400 401 One of the classes must always be named ALL_REGS and include all hard regs. 402 If there is more than one class, another class must be named NO_REGS 403 and contain no registers. 404 405 The name GENERAL_REGS must be the name of a class (or an alias for 406 another name such as ALL_REGS). This is the class of registers 407 that is allowed by "g" or "r" in a register constraint. 408 Also, registers outside this class are allocated only when 409 instructions express preferences for them. 410 411 The classes must be numbered in nondecreasing order; that is, 412 a larger-numbered class must never be contained completely 413 in a smaller-numbered class. 414 415 For any two classes, it is very desirable that there be another 416 class that represents their union. */ 417 418 enum reg_class 419 { 420 NO_REGS, /* no registers in set */ 421 SIBCALL_REGS, /* registers used by indirect sibcalls */ 422 JALR_REGS, /* registers used by indirect calls */ 423 GR_REGS, /* integer registers */ 424 FP_REGS, /* floating-point registers */ 425 FRAME_REGS, /* arg pointer and frame pointer */ 426 ALL_REGS, /* all registers */ 427 LIM_REG_CLASSES /* max value + 1 */ 428 }; 429 430 #define N_REG_CLASSES (int) LIM_REG_CLASSES 431 432 #define GENERAL_REGS GR_REGS 433 434 /* An initializer containing the names of the register classes as C 435 string constants. These names are used in writing some of the 436 debugging dumps. */ 437 438 #define REG_CLASS_NAMES \ 439 { \ 440 "NO_REGS", \ 441 "SIBCALL_REGS", \ 442 "JALR_REGS", \ 443 "GR_REGS", \ 444 "FP_REGS", \ 445 "FRAME_REGS", \ 446 "ALL_REGS" \ 447 } 448 449 /* An initializer containing the contents of the register classes, 450 as integers which are bit masks. The Nth integer specifies the 451 contents of class N. The way the integer MASK is interpreted is 452 that register R is in the class if `MASK & (1 << R)' is 1. 453 454 When the machine has more than 32 registers, an integer does not 455 suffice. Then the integers are replaced by sub-initializers, 456 braced groupings containing several integers. Each 457 sub-initializer must be suitable as an initializer for the type 458 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ 459 460 #define REG_CLASS_CONTENTS \ 461 { \ 462 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 463 { 0xf003fcc0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ 464 { 0xffffffc0, 0x00000000, 0x00000000 }, /* JALR_REGS */ \ 465 { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \ 466 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 467 { 0x00000000, 0x00000000, 0x00000003 }, /* FRAME_REGS */ \ 468 { 0xffffffff, 0xffffffff, 0x00000003 } /* ALL_REGS */ \ 469 } 470 471 /* A C expression whose value is a register class containing hard 472 register REGNO. In general there is more that one such class; 473 choose a class which is "minimal", meaning that no smaller class 474 also contains the register. */ 475 476 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ] 477 478 /* A macro whose definition is the name of the class to which a 479 valid base register must belong. A base register is one used in 480 an address which is the register value plus a displacement. */ 481 482 #define BASE_REG_CLASS GR_REGS 483 484 /* A macro whose definition is the name of the class to which a 485 valid index register must belong. An index register is one used 486 in an address where its value is either multiplied by a scale 487 factor or added to another register (as well as added to a 488 displacement). */ 489 490 #define INDEX_REG_CLASS NO_REGS 491 492 /* We generally want to put call-clobbered registers ahead of 493 call-saved ones. (IRA expects this.) */ 494 495 #define REG_ALLOC_ORDER \ 496 { \ 497 /* Call-clobbered GPRs. */ \ 498 15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1, \ 499 /* Call-saved GPRs. */ \ 500 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ 501 /* GPRs that can never be exposed to the register allocator. */ \ 502 0, 2, 3, 4, \ 503 /* Call-clobbered FPRs. */ \ 504 47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49, \ 505 60, 61, 62, 63, \ 506 /* Call-saved FPRs. */ \ 507 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ 508 /* None of the remaining classes have defined call-saved \ 509 registers. */ \ 510 64, 65 \ 511 } 512 513 /* True if VALUE is a signed 12-bit number. */ 514 515 #define SMALL_OPERAND(VALUE) \ 516 ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH) 517 518 /* True if VALUE can be loaded into a register using LUI. */ 519 520 #define LUI_OPERAND(VALUE) \ 521 (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \ 522 || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0) 523 524 /* Stack layout; function entry, exit and calling. */ 525 526 #define STACK_GROWS_DOWNWARD 1 527 528 #define FRAME_GROWS_DOWNWARD 1 529 530 #define RETURN_ADDR_RTX riscv_return_addr 531 532 #define ELIMINABLE_REGS \ 533 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 534 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 535 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 536 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 537 538 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 539 (OFFSET) = riscv_initial_elimination_offset (FROM, TO) 540 541 /* Allocate stack space for arguments at the beginning of each function. */ 542 #define ACCUMULATE_OUTGOING_ARGS 1 543 544 /* The argument pointer always points to the first argument. */ 545 #define FIRST_PARM_OFFSET(FNDECL) 0 546 547 #define REG_PARM_STACK_SPACE(FNDECL) 0 548 549 /* Define this if it is the responsibility of the caller to 550 allocate the area reserved for arguments passed in registers. 551 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 552 of this macro is to determine whether the space is included in 553 `crtl->outgoing_args_size'. */ 554 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 555 556 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary 557 558 /* Symbolic macros for the registers used to return integer and floating 559 point values. */ 560 561 #define GP_RETURN GP_ARG_FIRST 562 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST) 563 564 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8) 565 566 /* Symbolic macros for the first/last argument registers. */ 567 568 #define GP_ARG_FIRST (GP_REG_FIRST + 10) 569 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 570 #define GP_TEMP_FIRST (GP_REG_FIRST + 5) 571 #define FP_ARG_FIRST (FP_REG_FIRST + 10) 572 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) 573 574 #define CALLEE_SAVED_REG_NUMBER(REGNO) \ 575 ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 : \ 576 (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1) 577 578 #define LIBCALL_VALUE(MODE) \ 579 riscv_function_value (NULL_TREE, NULL_TREE, MODE) 580 581 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 582 riscv_function_value (VALTYPE, FUNC, VOIDmode) 583 584 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) 585 586 /* 1 if N is a possible register number for function argument passing. 587 We have no FP argument registers when soft-float. */ 588 589 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */ 590 #define FUNCTION_ARG_REGNO_P(N) \ 591 (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \ 592 || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST))) 593 594 typedef struct { 595 /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */ 596 unsigned int num_gprs; 597 598 /* Number of floating-point registers used so far, likewise. */ 599 unsigned int num_fprs; 600 } CUMULATIVE_ARGS; 601 602 /* Initialize a variable CUM of type CUMULATIVE_ARGS 603 for a call to a function whose data type is FNTYPE. 604 For a library call, FNTYPE is 0. */ 605 606 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 607 memset (&(CUM), 0, sizeof (CUM)) 608 609 #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO) 610 611 /* Align based on stack boundary, which might have been set by the user. */ 612 #define RISCV_STACK_ALIGN(LOC) \ 613 (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8)) 614 615 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 616 the stack pointer does not matter. The value is tested only in 617 functions that have frame pointers. 618 No definition is equivalent to always zero. */ 619 620 #define EXIT_IGNORE_STACK 1 621 622 623 /* Trampolines are a block of code followed by two pointers. */ 624 625 #define TRAMPOLINE_CODE_SIZE 16 626 #define TRAMPOLINE_SIZE \ 627 ((Pmode == SImode) \ 628 ? TRAMPOLINE_CODE_SIZE \ 629 : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2)) 630 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE 631 632 /* Addressing modes, and classification of registers for them. */ 633 634 #define REGNO_OK_FOR_INDEX_P(REGNO) 0 635 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 636 riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1) 637 638 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 639 and check its validity for a certain class. 640 We have two alternate definitions for each of them. 641 The usual definition accepts all pseudo regs; the other rejects them all. 642 The symbol REG_OK_STRICT causes the latter definition to be used. 643 644 Most source files want to accept pseudo regs in the hope that 645 they will get allocated to the class that the insn wants them to be in. 646 Some source files that are used after register allocation 647 need to be strict. */ 648 649 #ifndef REG_OK_STRICT 650 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 651 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) 652 #else 653 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 654 riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) 655 #endif 656 657 #define REG_OK_FOR_INDEX_P(X) 0 658 659 /* Maximum number of registers that can appear in a valid memory address. */ 660 661 #define MAX_REGS_PER_ADDRESS 1 662 663 #define CONSTANT_ADDRESS_P(X) \ 664 (CONSTANT_P (X) && memory_address_p (SImode, X)) 665 666 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means 667 'the start of the function that this code is output in'. */ 668 669 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 670 do { \ 671 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ 672 asm_fprintf ((FILE), "%U%s", \ 673 XSTR (XEXP (DECL_RTL (current_function_decl), \ 674 0), 0)); \ 675 else \ 676 asm_fprintf ((FILE), "%U%s", (NAME)); \ 677 } while (0) 678 679 #define JUMP_TABLES_IN_TEXT_SECTION 0 680 #define CASE_VECTOR_MODE SImode 681 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW) 682 683 /* The load-address macro is used for PC-relative addressing of symbols 684 that bind locally. Don't use it for symbols that should be addressed 685 via the GOT. Also, avoid it for CM_MEDLOW, where LUI addressing 686 currently results in more opportunities for linker relaxation. */ 687 #define USE_LOAD_ADDRESS_MACRO(sym) \ 688 (!TARGET_EXPLICIT_RELOCS && \ 689 ((flag_pic \ 690 && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym)) \ 691 || ((GET_CODE (sym) == CONST) \ 692 && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0)) \ 693 && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0))))) \ 694 || riscv_cmodel == CM_MEDANY)) 695 696 /* Define this as 1 if `char' should by default be signed; else as 0. */ 697 #define DEFAULT_SIGNED_CHAR 0 698 699 #define MOVE_MAX UNITS_PER_WORD 700 #define MAX_MOVE_MAX 8 701 702 /* The SPARC port says: 703 Nonzero if access to memory by bytes is slow and undesirable. 704 For RISC chips, it means that access to memory by bytes is no 705 better than access by words when possible, so grab a whole word 706 and maybe make use of that. */ 707 #define SLOW_BYTE_ACCESS 1 708 709 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns 710 in the md file instead. */ 711 #define SHIFT_COUNT_TRUNCATED 0 712 713 /* Specify the machine mode that pointers have. 714 After generation of rtl, the compiler makes no further distinction 715 between pointers and any other objects of this machine mode. */ 716 717 #define Pmode word_mode 718 719 /* Give call MEMs SImode since it is the "most permissive" mode 720 for both 32-bit and 64-bit targets. */ 721 722 #define FUNCTION_MODE SImode 723 724 /* A C expression for the cost of a branch instruction. A value of 2 725 seems to minimize code size. */ 726 727 #define BRANCH_COST(speed_p, predictable_p) \ 728 ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost) 729 730 /* True if the target optimizes short forward branches around integer 731 arithmetic instructions into predicated operations, e.g., for 732 conditional-move operations. The macro assumes that all branch 733 instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ) 734 support this feature. The macro further assumes that any integer 735 arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I], 736 SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed 737 counterparts, including C.MV and C.LI) can be in the branch shadow. */ 738 739 #define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7) 740 741 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 742 743 /* Control the assembler format that we output. */ 744 745 /* Output to assembler file text saying following lines 746 may contain character constants, extra white space, comments, etc. */ 747 748 #ifndef ASM_APP_ON 749 #define ASM_APP_ON " #APP\n" 750 #endif 751 752 /* Output to assembler file text saying following lines 753 no longer contain unusual constructs. */ 754 755 #ifndef ASM_APP_OFF 756 #define ASM_APP_OFF " #NO_APP\n" 757 #endif 758 759 #define REGISTER_NAMES \ 760 { "zero","ra", "sp", "gp", "tp", "t0", "t1", "t2", \ 761 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", \ 762 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", \ 763 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", \ 764 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", \ 765 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", \ 766 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", \ 767 "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \ 768 "arg", "frame", } 769 770 #define ADDITIONAL_REGISTER_NAMES \ 771 { \ 772 { "x0", 0 + GP_REG_FIRST }, \ 773 { "x1", 1 + GP_REG_FIRST }, \ 774 { "x2", 2 + GP_REG_FIRST }, \ 775 { "x3", 3 + GP_REG_FIRST }, \ 776 { "x4", 4 + GP_REG_FIRST }, \ 777 { "x5", 5 + GP_REG_FIRST }, \ 778 { "x6", 6 + GP_REG_FIRST }, \ 779 { "x7", 7 + GP_REG_FIRST }, \ 780 { "x8", 8 + GP_REG_FIRST }, \ 781 { "x9", 9 + GP_REG_FIRST }, \ 782 { "x10", 10 + GP_REG_FIRST }, \ 783 { "x11", 11 + GP_REG_FIRST }, \ 784 { "x12", 12 + GP_REG_FIRST }, \ 785 { "x13", 13 + GP_REG_FIRST }, \ 786 { "x14", 14 + GP_REG_FIRST }, \ 787 { "x15", 15 + GP_REG_FIRST }, \ 788 { "x16", 16 + GP_REG_FIRST }, \ 789 { "x17", 17 + GP_REG_FIRST }, \ 790 { "x18", 18 + GP_REG_FIRST }, \ 791 { "x19", 19 + GP_REG_FIRST }, \ 792 { "x20", 20 + GP_REG_FIRST }, \ 793 { "x21", 21 + GP_REG_FIRST }, \ 794 { "x22", 22 + GP_REG_FIRST }, \ 795 { "x23", 23 + GP_REG_FIRST }, \ 796 { "x24", 24 + GP_REG_FIRST }, \ 797 { "x25", 25 + GP_REG_FIRST }, \ 798 { "x26", 26 + GP_REG_FIRST }, \ 799 { "x27", 27 + GP_REG_FIRST }, \ 800 { "x28", 28 + GP_REG_FIRST }, \ 801 { "x29", 29 + GP_REG_FIRST }, \ 802 { "x30", 30 + GP_REG_FIRST }, \ 803 { "x31", 31 + GP_REG_FIRST }, \ 804 { "f0", 0 + FP_REG_FIRST }, \ 805 { "f1", 1 + FP_REG_FIRST }, \ 806 { "f2", 2 + FP_REG_FIRST }, \ 807 { "f3", 3 + FP_REG_FIRST }, \ 808 { "f4", 4 + FP_REG_FIRST }, \ 809 { "f5", 5 + FP_REG_FIRST }, \ 810 { "f6", 6 + FP_REG_FIRST }, \ 811 { "f7", 7 + FP_REG_FIRST }, \ 812 { "f8", 8 + FP_REG_FIRST }, \ 813 { "f9", 9 + FP_REG_FIRST }, \ 814 { "f10", 10 + FP_REG_FIRST }, \ 815 { "f11", 11 + FP_REG_FIRST }, \ 816 { "f12", 12 + FP_REG_FIRST }, \ 817 { "f13", 13 + FP_REG_FIRST }, \ 818 { "f14", 14 + FP_REG_FIRST }, \ 819 { "f15", 15 + FP_REG_FIRST }, \ 820 { "f16", 16 + FP_REG_FIRST }, \ 821 { "f17", 17 + FP_REG_FIRST }, \ 822 { "f18", 18 + FP_REG_FIRST }, \ 823 { "f19", 19 + FP_REG_FIRST }, \ 824 { "f20", 20 + FP_REG_FIRST }, \ 825 { "f21", 21 + FP_REG_FIRST }, \ 826 { "f22", 22 + FP_REG_FIRST }, \ 827 { "f23", 23 + FP_REG_FIRST }, \ 828 { "f24", 24 + FP_REG_FIRST }, \ 829 { "f25", 25 + FP_REG_FIRST }, \ 830 { "f26", 26 + FP_REG_FIRST }, \ 831 { "f27", 27 + FP_REG_FIRST }, \ 832 { "f28", 28 + FP_REG_FIRST }, \ 833 { "f29", 29 + FP_REG_FIRST }, \ 834 { "f30", 30 + FP_REG_FIRST }, \ 835 { "f31", 31 + FP_REG_FIRST }, \ 836 } 837 838 /* Globalizing directive for a label. */ 839 #define GLOBAL_ASM_OP "\t.globl\t" 840 841 /* This is how to store into the string LABEL 842 the symbol_ref name of an internal numbered label where 843 PREFIX is the class of label and NUM is the number within the class. 844 This is suitable for output with `assemble_name'. */ 845 846 #undef ASM_GENERATE_INTERNAL_LABEL 847 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 848 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 849 850 /* This is how to output an element of a case-vector that is absolute. */ 851 852 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 853 fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE) 854 855 /* This is how to output an element of a PIC case-vector. */ 856 857 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 858 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ 859 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL) 860 861 /* This is how to output an assembler line 862 that says to advance the location counter 863 to a multiple of 2**LOG bytes. */ 864 865 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 866 fprintf (STREAM, "\t.align\t%d\n", (LOG)) 867 868 /* Define the strings to put out for each section in the object file. */ 869 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ 870 #define DATA_SECTION_ASM_OP "\t.data" /* large data */ 871 #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" 872 #define BSS_SECTION_ASM_OP "\t.bss" 873 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss,\"aw\",@nobits" 874 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata,\"aw\",@progbits" 875 876 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ 877 do \ 878 { \ 879 fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ 880 reg_names[STACK_POINTER_REGNUM], \ 881 reg_names[STACK_POINTER_REGNUM], \ 882 TARGET_64BIT ? "sd" : "sw", \ 883 reg_names[REGNO], \ 884 reg_names[STACK_POINTER_REGNUM]); \ 885 } \ 886 while (0) 887 888 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ 889 do \ 890 { \ 891 fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n", \ 892 TARGET_64BIT ? "ld" : "lw", \ 893 reg_names[REGNO], \ 894 reg_names[STACK_POINTER_REGNUM], \ 895 reg_names[STACK_POINTER_REGNUM], \ 896 reg_names[STACK_POINTER_REGNUM]); \ 897 } \ 898 while (0) 899 900 #define ASM_COMMENT_START "#" 901 902 #undef SIZE_TYPE 903 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") 904 905 #undef PTRDIFF_TYPE 906 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") 907 908 /* The maximum number of bytes copied by one iteration of a cpymemsi loop. */ 909 910 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4) 911 912 /* The maximum number of bytes that can be copied by a straight-line 913 cpymemsi implementation. */ 914 915 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3) 916 917 /* If a memory-to-memory move would take MOVE_RATIO or more simple 918 move-instruction pairs, we will do a cpymem or libcall instead. 919 Do not use move_by_pieces at all when strict alignment is not 920 in effect but the target has slow unaligned accesses; in this 921 case, cpymem or libcall is more efficient. */ 922 923 #define MOVE_RATIO(speed) \ 924 (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 : \ 925 (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD : \ 926 CLEAR_RATIO (speed) / 2) 927 928 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 929 of the length of a memset call, but use the default otherwise. */ 930 931 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6) 932 933 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when 934 optimizing for size adjust the ratio to account for the overhead of 935 loading the constant and replicating it across the word. */ 936 937 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2)) 938 939 #ifndef USED_FOR_TARGET 940 extern const enum reg_class riscv_regno_to_class[]; 941 extern bool riscv_slow_unaligned_access_p; 942 extern unsigned riscv_stack_boundary; 943 #endif 944 945 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 946 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) 947 948 #define XLEN_SPEC \ 949 "%{march=rv32*:32}" \ 950 "%{march=rv64*:64}" \ 951 952 #define ABI_SPEC \ 953 "%{mabi=ilp32:ilp32}" \ 954 "%{mabi=ilp32e:ilp32e}" \ 955 "%{mabi=ilp32f:ilp32f}" \ 956 "%{mabi=ilp32d:ilp32d}" \ 957 "%{mabi=lp64:lp64}" \ 958 "%{mabi=lp64f:lp64f}" \ 959 "%{mabi=lp64d:lp64d}" \ 960 961 /* ISA constants needed for code generation. */ 962 #define OPCODE_LW 0x2003 963 #define OPCODE_LD 0x3003 964 #define OPCODE_AUIPC 0x17 965 #define OPCODE_JALR 0x67 966 #define OPCODE_LUI 0x37 967 #define OPCODE_ADDI 0x13 968 #define SHIFT_RD 7 969 #define SHIFT_RS1 15 970 #define SHIFT_IMM 20 971 #define IMM_BITS 12 972 #define C_S_BITS 5 973 #define C_SxSP_BITS 6 974 975 #define IMM_REACH (1LL << IMM_BITS) 976 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1)) 977 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) 978 979 #define SWSP_REACH (4LL << C_SxSP_BITS) 980 #define SDSP_REACH (8LL << C_SxSP_BITS) 981 982 /* This is the maximum value that can be represented in a compressed load/store 983 offset (an unsigned 5-bit value scaled by 4). */ 984 #define CSW_MAX_OFFSET (((4LL << C_S_BITS) - 1) & ~3) 985 986 /* Called from RISCV_REORG, this is defined in riscv-sr.c. */ 987 988 extern void riscv_remove_unneeded_save_restore_calls (void); 989 990 #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO) 991 992 #endif /* ! GCC_RISCV_H */ 993