1 /* { dg-do compile } */
2 /* { dg-do run { target { s390_z14_hw } } } */
3 /* z14 only because we need msrkc, msc, msgrkc, msgc */
4 /* { dg-options "-O3 -march=z14 -mzarch --save-temps" } */
5
6 #include <stddef.h>
7 #include <limits.h>
8
9 int __attribute__((noinline,noclone))
smul(int a,int b,int * res)10 smul (int a, int b, int *res)
11 {
12 return __builtin_smul_overflow(a, b, res);
13 }
14
15 int __attribute__((noinline,noclone))
smull(long a,long b,long * res)16 smull (long a, long b, long *res)
17 {
18 return __builtin_smull_overflow(a, b, res);
19 }
20
21 int __attribute__((noinline,noclone))
smulll(long long a,long long b,long long * res)22 smulll (long long a, long long b, long long *res)
23 {
24 return __builtin_smulll_overflow(a, b, res);
25 }
26
27
28 int
main()29 main ()
30 {
31 int ret = 0;
32 int result;
33 long lresult;
34 long long llresult;
35
36 ret += !!smul (INT_MAX, 2, &result);
37 ret += !!smull (LONG_MAX, 2, &lresult);
38 ret += !!smulll (LLONG_MAX, 2, &llresult);
39
40 if (ret != 3)
41 __builtin_abort ();
42
43 return 0;
44 }
45
46 /* Check that no compare or bitop instructions are emitted. */
47 /* { dg-final { scan-assembler-not "\tcr" } } */
48 /* { dg-final { scan-assembler-not "\txr" } } */
49 /* { dg-final { scan-assembler-not "\tnr" } } */
50 /* { dg-final { scan-assembler-not "\tcgr" } } */
51 /* { dg-final { scan-assembler-not "\txgr" } } */
52 /* { dg-final { scan-assembler-not "\tngr" } } */
53 /* On 31 bit the long long variants use risbgn to merge the 32 bit
54 regs into a 64 bit reg. */
55 /* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */
56 /* Just one for the ret != 3 comparison. */
57 /* { dg-final { scan-assembler-times "ci" 1 } } */
58 /* { dg-final { scan-assembler-times "\tlochio\t" 3 { target { ! lp64 } } } } */
59 /* { dg-final { scan-assembler-times "\tlocghio\t" 3 { target lp64 } } } */
60