1 /* Definitions of target machine for GNU compiler, for the pdp-11 2 Copyright (C) 1994-2021 Free Software Foundation, Inc. 3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #define CONSTANT_POOL_BEFORE_FUNCTION 0 22 23 /* check whether load_fpu_reg or not */ 24 #define LOAD_FPU_REG_P(x) ((x) >= AC0_REGNUM && (x) <= AC3_REGNUM) 25 #define NO_LOAD_FPU_REG_P(x) ((x) == AC4_REGNUM || (x) == AC5_REGNUM) 26 #define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x)) 27 #define CPU_REG_P(x) ((x) <= PC_REGNUM) 28 29 /* Names to predefine in the preprocessor for this target machine. */ 30 31 #define TARGET_CPU_CPP_BUILTINS() \ 32 do \ 33 { \ 34 builtin_define_std ("pdp11"); \ 35 if (TARGET_INT16) \ 36 builtin_define_with_int_value ("__pdp11_int", 16); \ 37 else \ 38 builtin_define_with_int_value ("__pdp11_int", 32); \ 39 if (TARGET_40) \ 40 builtin_define_with_int_value ("__pdp11_model", 40); \ 41 else if (TARGET_45) \ 42 builtin_define_with_int_value ("__pdp11_model", 45); \ 43 else \ 44 builtin_define_with_int_value ("__pdp11_model", 10); \ 45 if (TARGET_FPU) \ 46 builtin_define ("__pdp11_fpu"); \ 47 if (TARGET_AC0) \ 48 builtin_define ("__pdp11_ac0"); \ 49 } \ 50 while (0) 51 52 53 /* Generate DBX debugging information. */ 54 55 #define DBX_DEBUGGING_INFO 56 57 #undef PREFERRED_DEBUGGING_TYPE 58 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG 59 60 #define TARGET_40_PLUS (TARGET_40 || TARGET_45) 61 #define TARGET_10 (! TARGET_40_PLUS) 62 63 #define TARGET_UNIX_ASM_DEFAULT 0 64 65 /* "Dialect" just distinguishes between standard DEC mnemonics, which 66 are also used by the GNU assembler, vs. Unix mnemonics and float 67 register names. So it is tied to the -munit-asm option, and treats 68 -mgnu-asm and -mdec-asm as equivalent (both are dialect zero). */ 69 #define ASSEMBLER_DIALECT (TARGET_UNIX_ASM ? 1 : 0) 70 71 72 73 /* TYPE SIZES */ 74 #define SHORT_TYPE_SIZE 16 75 #define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32) 76 #define LONG_TYPE_SIZE 32 77 #define LONG_LONG_TYPE_SIZE 64 78 79 /* In earlier versions, FLOAT_TYPE_SIZE was selectable as 32 or 64, 80 but that conflicts with Fortran language rules. Since there is no 81 obvious reason why we should have that feature -- other targets 82 generally don't have float and double the same size -- I've removed 83 it. Note that it continues to be true (for now) that arithmetic is 84 always done with 64-bit values, i.e., the FPU is always in "double" 85 mode. */ 86 #define FLOAT_TYPE_SIZE 32 87 #define DOUBLE_TYPE_SIZE 64 88 #define LONG_DOUBLE_TYPE_SIZE 64 89 90 /* machine types from ansi */ 91 #define SIZE_TYPE "short unsigned int" /* definition of size_t */ 92 #define WCHAR_TYPE "short int" /* or long int???? */ 93 #define WCHAR_TYPE_SIZE 16 94 95 #define PTRDIFF_TYPE "short int" 96 97 /* target machine storage layout */ 98 99 /* Define this if most significant bit is lowest numbered 100 in instructions that operate on numbered bit-fields. */ 101 #define BITS_BIG_ENDIAN 0 102 103 /* Define this if most significant byte of a word is the lowest numbered. */ 104 #define BYTES_BIG_ENDIAN 0 105 106 /* Define this if most significant word of a multiword number is first. */ 107 #define WORDS_BIG_ENDIAN 1 108 109 /* Define that floats are in VAX order, not high word first as for ints. */ 110 #define FLOAT_WORDS_BIG_ENDIAN 0 111 112 /* Width of a word, in units (bytes). 113 114 UNITS OR BYTES - seems like units */ 115 #define UNITS_PER_WORD 2 116 117 /* This machine doesn't use IEEE floats. */ 118 /* Because the pdp11 (at least Unix) convention for 32-bit ints is 119 big endian, opposite for what you need for float, the vax float 120 conversion routines aren't actually used directly. But the underlying 121 format is indeed the vax/pdp11 float format. */ 122 extern const struct real_format pdp11_f_format; 123 extern const struct real_format pdp11_d_format; 124 125 /* Maximum sized of reasonable data type -- DImode ...*/ 126 #define MAX_FIXED_MODE_SIZE 64 127 128 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 129 #define POINTER_BOUNDARY 16 130 131 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 132 #define PARM_BOUNDARY 16 133 134 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 135 #define STACK_BOUNDARY 16 136 137 /* Allocation boundary (in *bits*) for the code of a function. */ 138 #define FUNCTION_BOUNDARY 16 139 140 /* Alignment of field after `int : 0' in a structure. */ 141 #define EMPTY_FIELD_BOUNDARY 16 142 143 /* No data type wants to be aligned rounder than this. */ 144 #define BIGGEST_ALIGNMENT 16 145 146 /* Define this if move instructions will actually fail to work 147 when given unaligned data. */ 148 #define STRICT_ALIGNMENT 1 149 150 /* "HW_DIVIDE" actually means 64 by 32 bit divide. While some PDP11 151 models have hardware divide, it is for 32 by 16 bits only, so we 152 call this platform "no hardware divide". */ 153 #define TARGET_HAS_NO_HW_DIVIDE 1 154 155 /* Standard register usage. */ 156 157 /* Number of actual hardware registers. 158 The hardware registers are assigned numbers for the compiler 159 from 0 to just below FIRST_PSEUDO_REGISTER. 160 All registers that the compiler knows about must be given numbers, 161 even those that are not normally considered general registers. 162 163 we have 8 integer registers, plus 6 float 164 (don't use scratch float !) */ 165 166 /* 1 for registers that have pervasive standard uses 167 and are not available for the register allocator. 168 169 On the pdp, these are: 170 Reg 7 = pc; 171 reg 6 = sp; 172 reg 5 = fp; not necessarily! 173 */ 174 175 #define FIXED_REGISTERS \ 176 {0, 0, 0, 0, 0, 0, 1, 1, \ 177 0, 0, 0, 0, 0, 0, 1, 1, \ 178 1 } 179 180 181 182 /* 1 for registers not available across function calls. 183 These must include the FIXED_REGISTERS and also any 184 registers that can be used without being saved. 185 The latter must include the registers where values are returned 186 and the register where structure-value addresses are passed. 187 Aside from that, you can include as many other registers as you like. */ 188 189 /* don't know about fp */ 190 #define CALL_USED_REGISTERS \ 191 {1, 1, 0, 0, 0, 0, 1, 1, \ 192 0, 0, 0, 0, 0, 0, 1, 1, \ 193 1 } 194 195 196 /* Specify the registers used for certain standard purposes. 197 The values of these macros are register numbers. */ 198 199 /* Register in which static-chain is passed to a function. */ 200 /* ??? - i don't want to give up a reg for this! */ 201 #define STATIC_CHAIN_REGNUM 4 202 203 /* Define the classes of registers for register constraints in the 204 machine description. Also define ranges of constants. 205 206 One of the classes must always be named ALL_REGS and include all hard regs. 207 If there is more than one class, another class must be named NO_REGS 208 and contain no registers. 209 210 The name GENERAL_REGS must be the name of a class (or an alias for 211 another name such as ALL_REGS). This is the class of registers 212 that is allowed by "g" or "r" in a register constraint. 213 Also, registers outside this class are allocated only when 214 instructions express preferences for them. 215 216 The classes must be numbered in nondecreasing order; that is, 217 a larger-numbered class must never be contained completely 218 in a smaller-numbered class. 219 220 For any two classes, it is very desirable that there be another 221 class that represents their union. */ 222 223 /* The pdp has a couple of classes: 224 225 MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication 226 (even numbered do 32-bit multiply) 227 GENERAL_REGS is all cpu 228 LOAD_FPU_REGS is the first four cpu regs, they are easier to load 229 NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them 230 FPU_REGS is all fpu regs 231 CC_REGS is the condition codes (CPU and FPU) 232 */ 233 234 enum reg_class 235 { NO_REGS, 236 NOTR0_REG, 237 NOTR1_REG, 238 NOTR2_REG, 239 NOTR3_REG, 240 NOTR4_REG, 241 NOTR5_REG, 242 NOTSP_REG, 243 MUL_REGS, 244 GENERAL_REGS, 245 LOAD_FPU_REGS, 246 NO_LOAD_FPU_REGS, 247 FPU_REGS, 248 CC_REGS, 249 ALL_REGS, 250 LIM_REG_CLASSES }; 251 252 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 253 254 /* have to allow this till cmpsi/tstsi are fixed in a better way !! */ 255 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 256 257 /* Give names of register classes as strings for dump file. */ 258 259 #define REG_CLASS_NAMES \ 260 { "NO_REGS", \ 261 "NOTR0_REG", \ 262 "NOTR1_REG", \ 263 "NOTR2_REG", \ 264 "NOTR3_REG", \ 265 "NOTR4_REG", \ 266 "NOTR5_REG", \ 267 "SP_REG", \ 268 "MUL_REGS", \ 269 "GENERAL_REGS", \ 270 "LOAD_FPU_REGS", \ 271 "NO_LOAD_FPU_REGS", \ 272 "FPU_REGS", \ 273 "CC_REGS", \ 274 "ALL_REGS" } 275 276 /* Define which registers fit in which classes. 277 This is an initializer for a vector of HARD_REG_SET 278 of length N_REG_CLASSES. */ 279 280 #define REG_CLASS_CONTENTS \ 281 { {0x00000}, /* NO_REGS */ \ 282 {0x000fe}, /* NOTR0_REG */ \ 283 {0x000fd}, /* NOTR1_REG */ \ 284 {0x000fb}, /* NOTR2_REG */ \ 285 {0x000f7}, /* NOTR3_REG */ \ 286 {0x000ef}, /* NOTR4_REG */ \ 287 {0x000df}, /* NOTR5_REG */ \ 288 {0x000bf}, /* NOTSP_REG */ \ 289 {0x0002a}, /* MUL_REGS */ \ 290 {0x040ff}, /* GENERAL_REGS */ \ 291 {0x00f00}, /* LOAD_FPU_REGS */ \ 292 {0x03000}, /* NO_LOAD_FPU_REGS */ \ 293 {0x03f00}, /* FPU_REGS */ \ 294 {0x18000}, /* CC_REGS */ \ 295 {0x1ffff}} /* ALL_REGS */ 296 297 /* The same information, inverted: 298 Return the class number of the smallest class containing 299 reg number REGNO. This could be a conditional expression 300 or could index an array. */ 301 302 #define REGNO_REG_CLASS(REGNO) pdp11_regno_reg_class (REGNO) 303 304 /* The class value for index registers, and the one for base regs. */ 305 #define INDEX_REG_CLASS GENERAL_REGS 306 #define BASE_REG_CLASS GENERAL_REGS 307 308 /* Return TRUE if the class is a CPU register. */ 309 #define CPU_REG_CLASS(CLASS) \ 310 (CLASS >= NOTR0_REG && CLASS <= GENERAL_REGS) 311 312 /* Return the maximum number of consecutive registers 313 needed to represent mode MODE in a register of class CLASS. */ 314 #define CLASS_MAX_NREGS(CLASS, MODE) \ 315 (CPU_REG_CLASS (CLASS) ? \ 316 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \ 317 1 \ 318 ) 319 320 /* Stack layout; function entry, exit and calling. */ 321 322 /* Define this if pushing a word on the stack 323 makes the stack pointer a smaller address. */ 324 #define STACK_GROWS_DOWNWARD 1 325 326 /* Define this to nonzero if the nominal address of the stack frame 327 is at the high-address end of the local variables; 328 that is, each additional local variable allocated 329 goes at a more negative offset in the frame. 330 */ 331 #define FRAME_GROWS_DOWNWARD 1 332 333 #define PUSH_ROUNDING(BYTES) pdp11_push_rounding (BYTES) 334 335 /* current_first_parm_offset stores the # of registers pushed on the 336 stack */ 337 extern int current_first_parm_offset; 338 339 /* Offset of first parameter from the argument pointer register value. */ 340 #define FIRST_PARM_OFFSET(FNDECL) 0 341 342 /* Define how to find the value returned by a function. 343 VALTYPE is the data type of the value (as a tree). 344 If the precise function being called is known, FUNC is its FUNCTION_DECL; 345 otherwise, FUNC is 0. */ 346 #define BASE_RETURN_VALUE_REG(MODE) \ 347 (FLOAT_MODE_P (MODE) ? AC0_REGNUM : RETVAL_REGNUM) 348 349 /* 1 if N is a possible register number for function argument passing. 350 - not used on pdp */ 351 352 #define FUNCTION_ARG_REGNO_P(N) 0 353 354 /* Define a data type for recording info about an argument list 355 during the scan of that argument list. This data type should 356 hold all necessary information about the function itself 357 and about the args processed so far, enough to enable macros 358 such as FUNCTION_ARG to determine where the next arg should go. 359 360 */ 361 362 #define CUMULATIVE_ARGS int 363 364 /* Initialize a variable CUM of type CUMULATIVE_ARGS 365 for a call to a function whose data type is FNTYPE. 366 For a library call, FNTYPE is 0. 367 368 ...., the offset normally starts at 0, but starts at 1 word 369 when the function gets a structure-value-address as an 370 invisible first argument. */ 371 372 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 373 ((CUM) = 0) 374 375 /* Output assembler code to FILE to increment profiler label # LABELNO 376 for profiling a function entry. */ 377 378 #define FUNCTION_PROFILER(FILE, LABELNO) 379 380 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 381 the stack pointer does not matter. The value is tested only in 382 functions that have frame pointers. 383 No definition is equivalent to always zero. */ 384 385 #define EXIT_IGNORE_STACK 1 386 387 /* Definitions for register eliminations. 388 389 This is an array of structures. Each structure initializes one pair 390 of eliminable registers. The "from" register number is given first, 391 followed by "to". Eliminations of the same "from" register are listed 392 in order of preference. 393 394 There are two registers that can be eliminated on the pdp11. The 395 arg pointer can be replaced by the frame pointer; the frame pointer 396 can often be replaced by the stack pointer. */ 397 398 #define ELIMINABLE_REGS \ 399 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 400 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 401 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} 402 403 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 404 ((OFFSET) = pdp11_initial_elimination_offset ((FROM), (TO))) 405 406 407 /* Addressing modes, and classification of registers for them. */ 408 409 #define HAVE_POST_INCREMENT 1 410 411 #define HAVE_PRE_DECREMENT 1 412 413 /* Macros to check register numbers against specific register classes. */ 414 415 /* These assume that REGNO is a hard or pseudo reg number. 416 They give nonzero only if REGNO is a hard reg of the suitable class 417 or a pseudo reg currently allocated to a suitable hard reg. 418 Since they use reg_renumber, they are safe only once reg_renumber 419 has been allocated, which happens in reginfo.c during register 420 allocation. */ 421 422 #define REGNO_OK_FOR_BASE_P(REGNO) \ 423 ((REGNO) <= PC_REGNUM || (unsigned) reg_renumber[REGNO] <= PC_REGNUM || \ 424 (REGNO) == ARG_POINTER_REGNUM || (REGNO) == FRAME_POINTER_REGNUM) 425 426 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P (REGNO) 427 428 /* Now macros that check whether X is a register and also, 429 strictly, whether it is in a specified class. 430 */ 431 432 433 434 /* Maximum number of registers that can appear in a valid memory address. */ 435 436 #define MAX_REGS_PER_ADDRESS 1 437 438 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 439 and check its validity for a certain class. 440 We have two alternate definitions for each of them. 441 The usual definition accepts all pseudo regs; the other rejects 442 them unless they have been allocated suitable hard regs. 443 The symbol REG_OK_STRICT causes the latter definition to be used. 444 445 Most source files want to accept pseudo regs in the hope that 446 they will get allocated to the class that the insn wants them to be in. 447 Source files for reload pass need to be strict. 448 After reload, it makes no difference, since pseudo regs have 449 been eliminated by then. */ 450 451 #ifndef REG_OK_STRICT 452 453 /* Nonzero if X is a hard reg that can be used as an index 454 or if it is a pseudo reg. */ 455 #define REG_OK_FOR_INDEX_P(X) (1) 456 /* Nonzero if X is a hard reg that can be used as a base reg 457 or if it is a pseudo reg. */ 458 #define REG_OK_FOR_BASE_P(X) (1) 459 460 #else 461 462 /* Nonzero if X is a hard reg that can be used as an index. */ 463 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 464 /* Nonzero if X is a hard reg that can be used as a base reg. */ 465 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 466 467 #endif 468 469 /* Specify the machine mode that this machine uses 470 for the index in the tablejump instruction. */ 471 #define CASE_VECTOR_MODE HImode 472 473 /* Define this if a raw index is all that is needed for a 474 `tablejump' insn. */ 475 #define CASE_TAKES_INDEX_RAW 476 477 /* Define this as 1 if `char' should by default be signed; else as 0. */ 478 #define DEFAULT_SIGNED_CHAR 1 479 480 /* Max number of bytes we can move from memory to memory 481 in one reasonably fast instruction. 482 */ 483 #define MOVE_MAX 2 484 485 /* Max number of insns to use for inline move rather than library 486 call. */ 487 #define MOVE_RATIO(speed) 6 488 489 /* Nonzero if access to memory by byte is no faster than by word. */ 490 #define SLOW_BYTE_ACCESS 1 491 492 /* Do not break .stabs pseudos into continuations. */ 493 #define DBX_CONTIN_LENGTH 0 494 495 /* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE, 496 return the mode to be used for the comparison. */ 497 498 #define SELECT_CC_MODE(OP,X,Y) pdp11_cc_mode (OP, X, Y) 499 500 /* Enable compare elimination pass. */ 501 #undef TARGET_FLAGS_REGNUM 502 #define TARGET_FLAGS_REGNUM CC_REGNUM 503 504 /* Specify the CC registers. TODO: is this for "type 1" CC handling only? */ 505 #undef TARGET_FIXED_CONDITION_CODE_REGS 506 #define TARGET_FIXED_CONDITION_CODE_REGS pdp11_fixed_cc_regs 507 508 /* Specify the machine mode that pointers have. 509 After generation of rtl, the compiler makes no further distinction 510 between pointers and any other objects of this machine mode. */ 511 #define Pmode HImode 512 513 /* A function address in a call instruction 514 is a word address (for indexing purposes) 515 so give the MEM rtx a word's mode. */ 516 #define FUNCTION_MODE HImode 517 518 /* Define this if addresses of constant functions 519 shouldn't be put through pseudo regs where they can be cse'd. 520 Desirable on machines where ordinary constants are expensive 521 but a CALL with constant address is cheap. */ 522 /* #define NO_FUNCTION_CSE */ 523 524 525 /* Control the assembler format that we output. */ 526 527 /* Output to assembler file text saying following lines 528 may contain character constants, extra white space, comments, etc. */ 529 530 #define ASM_APP_ON "" 531 532 /* Output to assembler file text saying following lines 533 no longer contain unusual constructs. */ 534 535 #define ASM_APP_OFF "" 536 537 /* Output before read-only data. */ 538 539 #define TEXT_SECTION_ASM_OP \ 540 ((TARGET_DEC_ASM) ? "\t.psect\tcode,i,ro,con" : "\t.text") 541 542 /* Output before writable data. */ 543 544 #define DATA_SECTION_ASM_OP \ 545 ((TARGET_DEC_ASM) ? "\t.psect\tdata,d,rw,con" : "\t.data") 546 547 /* Output before read-only data. Same as read-write data for non-DEC 548 assemblers because they don't know about .rodata. */ 549 550 #define READONLY_DATA_SECTION_ASM_OP \ 551 ((TARGET_DEC_ASM) ? "\t.psect\trodata,d,ro,con" : "\t.data") 552 553 /* How to refer to registers in assembler output. 554 This sequence is indexed by compiler's hard-register-number (see above). */ 555 556 #define REGISTER_NAMES \ 557 {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \ 558 "ac0", "ac1", "ac2", "ac3", "ac4", "ac5", "ap", "cc", \ 559 "fcc" } 560 561 /* Globalizing directive for a label. */ 562 #define GLOBAL_ASM_OP "\t.globl\t" 563 564 /* The prefix to add to user-visible assembler symbols. For the DEC 565 assembler case, this is not used. */ 566 567 #define USER_LABEL_PREFIX "_" 568 569 /* Line separators. */ 570 571 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \ 572 ((C) == '\n' || (!TARGET_DEC_ASM && (C) == ';')) 573 574 /* This is how to store into the string LABEL 575 the symbol_ref name of an internal numbered label where 576 PREFIX is the class of label and NUM is the number within the class. 577 This is suitable for output with `assemble_name'. */ 578 579 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 580 pdp11_gen_int_label ((LABEL), (PREFIX), (NUM)) 581 582 /* Emit a string. */ 583 584 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ 585 output_ascii (FILE, P, SIZE) 586 587 /* Print a label reference, with _ prefix if not DEC. */ 588 589 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ 590 pdp11_output_labelref ((STREAM), (NAME)) 591 592 /* Equate a symbol to an expression. */ 593 594 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ 595 pdp11_output_def (STREAM, NAME, VALUE) 596 597 /* Mark a reference to an external symbol. Needed for DEC assembler. */ 598 599 #define ASM_OUTPUT_EXTERNAL(STREAM, DECL, NAME) \ 600 if (TARGET_DEC_ASM) \ 601 fprintf ((STREAM), "\t.globl\t%s\n", (NAME)) 602 603 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ 604 if (TARGET_DEC_ASM) \ 605 fprintf ((STREAM), ".title\t%s\n", (NAME)) 606 607 /* This is how to output an element of a case-vector that is absolute. */ 608 609 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 610 pdp11_output_addr_vec_elt (FILE, VALUE) 611 612 /* This is how to output an assembler line that says to advance the 613 location counter to a multiple of 2**LOG bytes. Only values 0 and 614 1 should appear, but due to PR87795 larger values (which are not 615 supported) can also appear. So we treat all alignment of LOG >= 1 616 as word (2 byte) alignment. 617 */ 618 619 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 620 if (LOG != 0) \ 621 fprintf (FILE, "\t.even\n") 622 623 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 624 do { \ 625 if (TARGET_DEC_ASM) \ 626 fprintf (FILE, "\t.blkb\t%o\n", (int) ((SIZE) & 0xffff)); \ 627 else \ 628 fprintf (FILE, "\t.=.+ %#o\n", (int) ((SIZE) & 0xffff)); \ 629 } while (0) 630 631 /* This says how to output an assembler line 632 to define a global common symbol. */ 633 634 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 635 pdp11_asm_output_var (FILE, NAME, SIZE, ALIGN, true) 636 637 /* This says how to output an assembler line 638 to define a local common symbol. */ 639 640 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ 641 pdp11_asm_output_var (FILE, NAME, SIZE, ALIGN, false) 642 643 /* Print a memory address as an operand to reference that memory location. */ 644 645 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 646 print_operand_address (FILE, ADDR) 647 648 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 649 fprintf (FILE, "\tmov\t%s,-(sp)\n", reg_names[REGNO]) 650 651 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 652 fprintf (FILE, "\tmov\t(sp)+,%s\n", reg_names[REGNO]) 653 654 #define TRAMPOLINE_SIZE 8 655 #define TRAMPOLINE_ALIGNMENT 16 656 657 #define BRANCH_COST(speed_p, predictable_p) 1 658 659 #define COMPARE_FLAG_MODE HImode 660 661 /* May be overridden by command option processing. */ 662 #define TARGET_HAVE_NAMED_SECTIONS false 663 664 /* pdp11-unknown-aout target has no support of C99 runtime */ 665 #undef TARGET_LIBC_HAS_FUNCTION 666 #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function 667