1;; Constraint definitions for RS6000 2;; Copyright (C) 2006-2021 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Available constraint letters: k q t u A B C D S T 21 22;; Register constraints 23 24; Actually defined in common.md: 25; (define_register_constraint "r" "GENERAL_REGS" 26; "A general purpose register (GPR), @code{r0}@dots{}@code{r31}.") 27 28(define_register_constraint "b" "BASE_REGS" 29 "A base register. Like @code{r}, but @code{r0} is not allowed, so 30 @code{r1}@dots{}@code{r31}.") 31 32(define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]" 33 "A floating point register (FPR), @code{f0}@dots{}@code{f31}.") 34 35(define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]" 36 "A floating point register. This is the same as @code{f} nowadays; 37 historically @code{f} was for single-precision and @code{d} was for 38 double-precision floating point.") 39 40(define_register_constraint "v" "ALTIVEC_REGS" 41 "An Altivec vector register (VR), @code{v0}@dots{}@code{v31}.") 42 43(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 44 "A VSX register (VSR), @code{vs0}@dots{}@code{vs63}. This is either an 45 FPR (@code{vs0}@dots{}@code{vs31} are @code{f0}@dots{}@code{f31}) or a VR 46 (@code{vs32}@dots{}@code{vs63} are @code{v0}@dots{}@code{v31}).") 47 48(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 49 "@internal A compatibility alias for @code{wa}.") 50(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 51 "@internal A compatibility alias for @code{wa}.") 52(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 53 "@internal A compatibility alias for @code{wa}.") 54(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 55 "@internal A compatibility alias for @code{wa}.") 56(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 57 "@internal A compatibility alias for @code{wa}.") 58 59(define_register_constraint "h" "SPECIAL_REGS" 60 "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).") 61 62(define_register_constraint "c" "CTR_REGS" 63 "The count register, @code{ctr}.") 64 65(define_register_constraint "l" "LINK_REGS" 66 "The link register, @code{lr}.") 67 68(define_register_constraint "x" "CR0_REGS" 69 "Condition register field 0, @code{cr0}.") 70 71(define_register_constraint "y" "CR_REGS" 72 "Any condition register field, @code{cr0}@dots{}@code{cr7}.") 73 74(define_register_constraint "z" "CA_REGS" 75 "@internal The carry bit, @code{XER[CA]}.") 76 77;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits. 78;; It is currently used for that purpose in LLVM. 79 80(define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]" 81 "@internal Like @code{wa}, if @option{-mpower9-vector} and @option{-m64} are 82 used; otherwise, @code{NO_REGS}.") 83 84;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use 85;; direct move directly, and movsf can't to move between the register sets. 86;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode 87(define_register_constraint "wn" "NO_REGS" 88 "@internal No register (@code{NO_REGS}).") 89 90(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]" 91 "@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise, 92 @code{NO_REGS}.") 93 94(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]" 95 "@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, 96 @code{NO_REGS}.") 97 98(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]" 99 "@internal Like @code{b}, if @option{-mpowerpc64} is used; otherwise, 100 @code{NO_REGS}.") 101 102;; wB needs ISA 2.07 VUPKHSW 103(define_constraint "wB" 104 "@internal Signed 5-bit constant integer that can be loaded into an 105 Altivec register." 106 (and (match_code "const_int") 107 (match_test "TARGET_P8_VECTOR") 108 (match_operand 0 "s5bit_cint_operand"))) 109 110(define_constraint "wD" 111 "@internal Int constant that is the element number of the 64-bit scalar 112 in a vector." 113 (and (match_code "const_int") 114 (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)"))) 115 116(define_constraint "wE" 117 "@internal Vector constant that can be loaded with the XXSPLTIB instruction." 118 (match_test "xxspltib_constant_nosplit (op, mode)")) 119 120;; Extended fusion store 121(define_memory_constraint "wF" 122 "@internal Memory operand suitable for power8 GPR load fusion." 123 (match_operand 0 "fusion_addis_mem_combo_load")) 124 125(define_constraint "wL" 126 "@internal Int constant that is the element number mfvsrld accesses in 127 a vector." 128 (and (match_code "const_int") 129 (match_test "TARGET_DIRECT_MOVE_128") 130 (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)"))) 131 132;; Generate the XXORC instruction to set a register to all 1's 133(define_constraint "wM" 134 "@internal Match vector constant with all 1's if the XXLORC instruction 135 is available." 136 (and (match_test "TARGET_P8_VECTOR") 137 (match_operand 0 "all_ones_constant"))) 138 139;; ISA 3.0 vector d-form addresses 140(define_memory_constraint "wO" 141 "@internal Memory operand suitable for the ISA 3.0 vector d-form instructions." 142 (match_operand 0 "vsx_quad_dform_memory_operand")) 143 144;; Lq/stq validates the address for load/store quad 145(define_memory_constraint "wQ" 146 "@internal Memory operand suitable for the load/store quad instructions." 147 (match_operand 0 "quad_memory_operand")) 148 149(define_constraint "wS" 150 "@internal Vector constant that can be loaded with XXSPLTIB & sign extension." 151 (match_test "xxspltib_constant_split (op, mode)")) 152 153;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form. 154;; Used by LXSD/STXSD/LXSSP/STXSSP. In contrast to "Y", the multiple-of-four 155;; offset is enforced for 32-bit too. 156(define_memory_constraint "wY" 157 "@internal A memory operand for a DS-form instruction." 158 (and (match_code "mem") 159 (not (match_test "update_address_mem (op, mode)")) 160 (match_test "mem_operand_ds_form (op, mode)"))) 161 162;; Altivec style load/store that ignores the bottom bits of the address 163(define_memory_constraint "wZ" 164 "@internal An indexed or indirect memory operand, ignoring the bottom 4 bits." 165 (match_operand 0 "altivec_indexed_or_indirect_operand")) 166 167;; Integer constraints 168 169(define_constraint "I" 170 "A signed 16-bit constant." 171 (and (match_code "const_int") 172 (match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000"))) 173 174(define_constraint "J" 175 "An unsigned 16-bit constant shifted left 16 bits (use @code{L} instead 176 for @code{SImode} constants)." 177 (and (match_code "const_int") 178 (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0"))) 179 180(define_constraint "K" 181 "An unsigned 16-bit constant." 182 (and (match_code "const_int") 183 (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0"))) 184 185(define_constraint "L" 186 "A signed 16-bit constant shifted left 16 bits." 187 (and (match_code "const_int") 188 (match_test "((ival & 0xffff) == 0 189 && (ival >> 31 == -1 || ival >> 31 == 0))"))) 190 191(define_constraint "M" 192 "@internal A constant greater than 31." 193 (and (match_code "const_int") 194 (match_test "ival > 31"))) 195 196(define_constraint "N" 197 "@internal An exact power of two." 198 (and (match_code "const_int") 199 (match_test "ival > 0 && exact_log2 (ival) >= 0"))) 200 201(define_constraint "O" 202 "@internal The integer constant zero." 203 (and (match_code "const_int") 204 (match_test "ival == 0"))) 205 206(define_constraint "P" 207 "@internal A constant whose negation is a signed 16-bit constant." 208 (and (match_code "const_int") 209 (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000"))) 210 211;; 34-bit signed integer constant 212(define_constraint "eI" 213 "A signed 34-bit integer constant if prefixed instructions are supported." 214 (match_operand 0 "cint34_operand")) 215 216;; Floating-point constraints. These two are defined so that insn 217;; length attributes can be calculated exactly. 218 219(define_constraint "G" 220 "@internal A floating point constant that can be loaded into a register 221 with one instruction per word." 222 (and (match_code "const_double") 223 (match_test "num_insns_constant (op, mode) 224 == (mode == SFmode || mode == SDmode ? 1 : 2)"))) 225 226(define_constraint "H" 227 "@internal A floating point constant that can be loaded into a register 228 using three instructions." 229 (and (match_code "const_double") 230 (match_test "num_insns_constant (op, mode) == 3"))) 231 232;; Memory constraints 233 234; Actually defined in common.md: 235; (define_memory_constraint "m" 236; "A memory operand." 237 238(define_memory_constraint "es" 239 "@internal 240 A ``stable'' memory operand; that is, one which does not include any 241 automodification of the base register. This used to be useful when 242 @code{m} allowed automodification of the base register, but as those 243 are now only allowed when @code{<} or @code{>} is used, @code{es} is 244 basically the same as @code{m} without @code{<} and @code{>}." 245 (and (match_code "mem") 246 (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC"))) 247 248(define_memory_constraint "Q" 249 "A memory operand addressed by just a base register." 250 (and (match_code "mem") 251 (match_test "REG_P (XEXP (op, 0))"))) 252 253(define_memory_constraint "Y" 254 "@internal A memory operand for a DQ-form instruction." 255 (and (match_code "mem") 256 (match_test "mem_operand_gpr (op, mode)"))) 257 258(define_memory_constraint "Z" 259 "A memory operand accessed with indexed or indirect addressing." 260 (match_operand 0 "indexed_or_indirect_operand")) 261 262;; Address constraints 263 264(define_constraint "R" 265 "@internal An AIX TOC entry." 266 (match_test "legitimate_constant_pool_address_p (op, QImode, false)")) 267 268(define_address_constraint "a" 269 "An indexed or indirect address." 270 (match_operand 0 "indexed_or_indirect_address")) 271 272;; General constraints 273 274(define_constraint "U" 275 "@internal A V.4 small data reference." 276 (and (match_test "DEFAULT_ABI == ABI_V4") 277 (match_test "small_data_operand (op, mode)"))) 278 279(define_constraint "W" 280 "@internal A vector constant that does not require memory." 281 (match_operand 0 "easy_vector_constant")) 282 283(define_constraint "j" 284 "@internal The zero vector constant." 285 (match_test "op == const0_rtx || op == CONST0_RTX (mode)")) 286