1 /* { dg-do compile } */
2 /* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
3 /* { dg-add-options arm_v8_3a_complex_neon } */
4 /* { dg-additional-options "-O2 -save-temps" } */
5
6 #include <arm_neon.h>
7
8 float32x2_t
test_vcadd_rot90_f32(float32x2_t __a,float32x2_t __b)9 test_vcadd_rot90_f32 (float32x2_t __a, float32x2_t __b)
10 {
11 return vcadd_rot90_f32 (__a, __b);
12 }
13
14 float32x4_t
test_vcaddq_rot90_f32(float32x4_t __a,float32x4_t __b)15 test_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b)
16 {
17 return vcaddq_rot90_f32 (__a, __b);
18 }
19
20 #ifdef __ARM_ARCH_ISA_A64
21 float64x2_t
test_vcaddq_rot90_f64(float64x2_t __a,float64x2_t __b)22 test_vcaddq_rot90_f64 (float64x2_t __a, float64x2_t __b)
23 {
24 return vcaddq_rot90_f64 (__a, __b);
25 }
26 #endif
27
28 float32x2_t
test_vcadd_rot270_f32(float32x2_t __a,float32x2_t __b)29 test_vcadd_rot270_f32 (float32x2_t __a, float32x2_t __b)
30 {
31 return vcadd_rot270_f32 (__a, __b);
32 }
33
34 float32x4_t
test_vcaddq_rot270_f32(float32x4_t __a,float32x4_t __b)35 test_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b)
36 {
37 return vcaddq_rot270_f32 (__a, __b);
38 }
39
40 #ifdef __ARM_ARCH_ISA_A64
41 float64x2_t
test_vcaddq_rot270_f64(float64x2_t __a,float64x2_t __b)42 test_vcaddq_rot270_f64 (float64x2_t __a, float64x2_t __b)
43 {
44 return vcaddq_rot270_f64 (__a, __b);
45 }
46 #endif
47
48 float32x2_t
test_vcmla_f32(float32x2_t __r,float32x2_t __a,float32x2_t __b)49 test_vcmla_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
50 {
51 return vcmla_f32 (__r, __a, __b);
52 }
53
54 float32x4_t
test_vcmlaq_f32(float32x4_t __r,float32x4_t __a,float32x4_t __b)55 test_vcmlaq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
56 {
57 return vcmlaq_f32 (__r, __a, __b);
58 }
59
60 #ifdef __ARM_ARCH_ISA_A64
61 float64x2_t
test_vcmlaq_f64(float64x2_t __r,float64x2_t __a,float64x2_t __b)62 test_vcmlaq_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
63 {
64 return vcmlaq_f64 (__r, __a, __b);
65 }
66 #endif
67
68 float32x2_t
test_vcmla_lane_f32(float32x2_t __r,float32x2_t __a,float32x2_t __b)69 test_vcmla_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
70 {
71 return vcmla_lane_f32 (__r, __a, __b, 0);
72 }
73
74 float32x2_t
test_vcmla_laneq_f32(float32x2_t __r,float32x2_t __a,float32x4_t __b)75 test_vcmla_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b)
76 {
77 return vcmla_laneq_f32 (__r, __a, __b, 1);
78 }
79
80 float32x4_t
test_vcmlaq_lane_f32(float32x4_t __r,float32x4_t __a,float32x2_t __b)81 test_vcmlaq_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b)
82 {
83 return vcmlaq_lane_f32 (__r, __a, __b, 0);
84 }
85
86 float32x4_t
test_vcmlaq_laneq_f32(float32x4_t __r,float32x4_t __a,float32x4_t __b)87 test_vcmlaq_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
88 {
89 return vcmlaq_laneq_f32 (__r, __a, __b, 1);
90 }
91
92 float32x2_t
test_vcmla_rot90_f32(float32x2_t __r,float32x2_t __a,float32x2_t __b)93 test_vcmla_rot90_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
94 {
95 return vcmla_rot90_f32 (__r, __a, __b);
96 }
97
98 float32x4_t
test_vcmlaq_rot90_f32(float32x4_t __r,float32x4_t __a,float32x4_t __b)99 test_vcmlaq_rot90_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
100 {
101 return vcmlaq_rot90_f32 (__r, __a, __b);
102 }
103
104 #ifdef __ARM_ARCH_ISA_A64
105 float64x2_t
test_vcmlaq_rot90_f64(float64x2_t __r,float64x2_t __a,float64x2_t __b)106 test_vcmlaq_rot90_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
107 {
108 return vcmlaq_rot90_f64 (__r, __a, __b);
109 }
110 #endif
111
112 float32x2_t
test_vcmla_rot90_lane_f32(float32x2_t __r,float32x2_t __a,float32x2_t __b)113 test_vcmla_rot90_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
114 {
115 return vcmla_rot90_lane_f32 (__r, __a, __b, 0);
116 }
117
118 float32x2_t
test_vcmla_rot90_laneq_f32(float32x2_t __r,float32x2_t __a,float32x4_t __b)119 test_vcmla_rot90_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b)
120 {
121 return vcmla_rot90_laneq_f32 (__r, __a, __b, 1);
122 }
123
124 float32x4_t
test_vcmlaq_rot90_lane_f32(float32x4_t __r,float32x4_t __a,float32x2_t __b)125 test_vcmlaq_rot90_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b)
126 {
127 return vcmlaq_rot90_lane_f32 (__r, __a, __b, 0);
128 }
129
130 float32x4_t
test_vcmlaq_rot90_laneq_f32(float32x4_t __r,float32x4_t __a,float32x4_t __b)131 test_vcmlaq_rot90_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
132 {
133 return vcmlaq_rot90_laneq_f32 (__r, __a, __b, 1);
134 }
135
136 float32x2_t
test_vcmla_rot180_f32(float32x2_t __r,float32x2_t __a,float32x2_t __b)137 test_vcmla_rot180_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
138 {
139 return vcmla_rot180_f32 (__r, __a, __b);
140 }
141
142 float32x4_t
test_vcmlaq_rot180_f32(float32x4_t __r,float32x4_t __a,float32x4_t __b)143 test_vcmlaq_rot180_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
144 {
145 return vcmlaq_rot180_f32 (__r, __a, __b);
146 }
147
148 #ifdef __ARM_ARCH_ISA_A64
149 float64x2_t
test_vcmlaq_rot180_f64(float64x2_t __r,float64x2_t __a,float64x2_t __b)150 test_vcmlaq_rot180_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
151 {
152 return vcmlaq_rot180_f64 (__r, __a, __b);
153 }
154 #endif
155
156 float32x2_t
test_vcmla_rot180_lane_f32(float32x2_t __r,float32x2_t __a,float32x2_t __b)157 test_vcmla_rot180_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
158 {
159 return vcmla_rot180_lane_f32 (__r, __a, __b, 0);
160 }
161
162 float32x2_t
test_vcmla_rot180_laneq_f32(float32x2_t __r,float32x2_t __a,float32x4_t __b)163 test_vcmla_rot180_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b)
164 {
165 return vcmla_rot180_laneq_f32 (__r, __a, __b, 1);
166 }
167
168 float32x4_t
test_vcmlaq_rot180_lane_f32(float32x4_t __r,float32x4_t __a,float32x2_t __b)169 test_vcmlaq_rot180_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b)
170 {
171 return vcmlaq_rot180_lane_f32 (__r, __a, __b, 0);
172 }
173
174 float32x4_t
test_vcmlaq_rot180_laneq_f32(float32x4_t __r,float32x4_t __a,float32x4_t __b)175 test_vcmlaq_rot180_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
176 {
177 return vcmlaq_rot180_laneq_f32 (__r, __a, __b, 1);
178 }
179
180 float32x2_t
test_vcmla_rot270_f32(float32x2_t __r,float32x2_t __a,float32x2_t __b)181 test_vcmla_rot270_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
182 {
183 return vcmla_rot270_f32 (__r, __a, __b);
184 }
185
186 float32x4_t
test_vcmlaq_rot270_f32(float32x4_t __r,float32x4_t __a,float32x4_t __b)187 test_vcmlaq_rot270_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
188 {
189 return vcmlaq_rot270_f32 (__r, __a, __b);
190 }
191
192 #ifdef __ARM_ARCH_ISA_A64
193 float64x2_t
test_vcmlaq_rot270_f64(float64x2_t __r,float64x2_t __a,float64x2_t __b)194 test_vcmlaq_rot270_f64 (float64x2_t __r, float64x2_t __a, float64x2_t __b)
195 {
196 return vcmlaq_rot270_f64 (__r, __a, __b);
197 }
198 #endif
199
200 float32x2_t
test_vcmla_rot270_lane_f32(float32x2_t __r,float32x2_t __a,float32x2_t __b)201 test_vcmla_rot270_lane_f32 (float32x2_t __r, float32x2_t __a, float32x2_t __b)
202 {
203 return vcmla_rot270_lane_f32 (__r, __a, __b, 0);
204 }
205
206 float32x2_t
test_vcmla_rot270_laneq_f32(float32x2_t __r,float32x2_t __a,float32x4_t __b)207 test_vcmla_rot270_laneq_f32 (float32x2_t __r, float32x2_t __a, float32x4_t __b)
208 {
209 return vcmla_rot270_laneq_f32 (__r, __a, __b, 1);
210 }
211
212 float32x4_t
test_vcmlaq_rot270_lane_f32(float32x4_t __r,float32x4_t __a,float32x2_t __b)213 test_vcmlaq_rot270_lane_f32 (float32x4_t __r, float32x4_t __a, float32x2_t __b)
214 {
215 return vcmlaq_rot270_lane_f32 (__r, __a, __b, 0);
216 }
217
218 float32x4_t
test_vcmlaq_rot270_laneq_f32(float32x4_t __r,float32x4_t __a,float32x4_t __b)219 test_vcmlaq_rot270_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b)
220 {
221 return vcmlaq_rot270_laneq_f32 (__r, __a, __b, 1);
222 }
223
224 /* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #270} 1 { target { aarch64*-*-* } } } } */
225 /* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #90} 1 { target { aarch64*-*-* } } } } */
226 /* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #270} 1 { target { aarch64*-*-* } } } } */
227 /* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #90} 1 { target { aarch64*-*-* } } } } */
228 /* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #270} 1 { target { aarch64*-*-* } } } } */
229 /* { dg-final { scan-assembler-times {fcadd\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #90} 1 { target { aarch64*-*-* } } } } */
230 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #0} 1 { target { aarch64*-*-* } } } } */
231 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #180} 1 { target { aarch64*-*-* } } } } */
232 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #270} 1 { target { aarch64*-*-* } } } } */
233 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.2d, #90} 1 { target { aarch64*-*-* } } } } */
234 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #0} 3 { target { aarch64*-*-* } } } } */
235 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #180} 3 { target { aarch64*-*-* } } } } */
236 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #270} 3 { target { aarch64*-*-* } } } } */
237 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.2s, v[0-9]+.2s, v[0-9]+.2s, #90} 3 { target { aarch64*-*-* } } } } */
238 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #0} 1 { target { aarch64*-*-* } } } } */
239 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #180} 1 { target { aarch64*-*-* } } } } */
240 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #270} 1 { target { aarch64*-*-* } } } } */
241 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4s, #90} 1 { target { aarch64*-*-* } } } } */
242 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[0\], #0} 1 { target { aarch64*-*-* } } } } */
243 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[0\], #180} 1 { target { aarch64*-*-* } } } } */
244 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[0\], #270} 1 { target { aarch64*-*-* } } } } */
245 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[0\], #90} 1 { target { aarch64*-*-* } } } } */
246 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[1\], #0} 1 { target { aarch64*-*-* } } } } */
247 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[1\], #180} 1 { target { aarch64*-*-* } } } } */
248 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[1\], #270} 1 { target { aarch64*-*-* } } } } */
249 /* { dg-final { scan-assembler-times {fcmla\tv[0-9]+.4s, v[0-9]+.4s, v[0-9]+.s\[1\], #90} 1 { target { aarch64*-*-* } } } } */
250 /* { dg-final { scan-assembler-times {dup\td[0-9]+, v[0-9]+.d\[1\]} 4 { target { aarch64*-*-* } } } } */
251
252 /* { dg-final { scan-assembler-times {vcadd.f32\td[0-9]+, d[0-9]+, d[0-9]+, #90} 2 { target { arm*-*-* } } } } */
253 /* { dg-final { scan-assembler-times {vcadd.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #90} 2 { target { arm*-*-* } } } } */
254 /* { dg-final { scan-assembler-times {vcmla.f32\td[0-9]+, d[0-9]+, d[0-9]+, #0} 1 { target { arm*-*-* } } } } */
255 /* { dg-final { scan-assembler-times {vcmla.f32\td[0-9]+, d[0-9]+, d[0-9]+, #180} 1 { target { arm*-*-* } } } } */
256 /* { dg-final { scan-assembler-times {vcmla.f32\td[0-9]+, d[0-9]+, d[0-9]+, #270} 1 { target { arm*-*-* } } } } */
257 /* { dg-final { scan-assembler-times {vcmla.f32\td[0-9]+, d[0-9]+, d[0-9]+, #90} 1 { target { arm*-*-* } } } } */
258 /* { dg-final { scan-assembler-times {vcmla.f32\td[0-9]+, d[0-9]+, d[0-9]+\[0\], #0} 2 { target { arm*-*-* } } } } */
259 /* { dg-final { scan-assembler-times {vcmla.f32\td[0-9]+, d[0-9]+, d[0-9]+\[0\], #180} 2 { target { arm*-*-* } } } } */
260 /* { dg-final { scan-assembler-times {vcmla.f32\td[0-9]+, d[0-9]+, d[0-9]+\[0\], #270} 2 { target { arm*-*-* } } } } */
261 /* { dg-final { scan-assembler-times {vcmla.f32\td[0-9]+, d[0-9]+, d[0-9]+\[0\], #90} 2 { target { arm*-*-* } } } } */
262 /* { dg-final { scan-assembler-times {vcmla.f32\tq[0-9]+, q[0-9]+, d[0-9]+\[0\], #0} 2 { target { arm*-*-* } } } } */
263 /* { dg-final { scan-assembler-times {vcmla.f32\tq[0-9]+, q[0-9]+, d[0-9]+\[0\], #180} 2 { target { arm*-*-* } } } } */
264 /* { dg-final { scan-assembler-times {vcmla.f32\tq[0-9]+, q[0-9]+, d[0-9]+\[0\], #270} 2 { target { arm*-*-* } } } } */
265 /* { dg-final { scan-assembler-times {vcmla.f32\tq[0-9]+, q[0-9]+, d[0-9]+\[0\], #90} 2 { target { arm*-*-* } } } } */
266 /* { dg-final { scan-assembler-times {vcmla.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #0} 1 { target { arm*-*-* } } } } */
267 /* { dg-final { scan-assembler-times {vcmla.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #180} 1 { target { arm*-*-* } } } } */
268 /* { dg-final { scan-assembler-times {vcmla.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #270} 1 { target { arm*-*-* } } } } */
269 /* { dg-final { scan-assembler-times {vcmla.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #90} 1 { target { arm*-*-* } } } } */
270