1 /* Verify that overloaded built-ins for vec_insert with
2 double inputs produce the right codegen. */
3
4 /* { dg-do compile } */
5 /* { dg-require-effective-target powerpc_vsx_ok } */
6 /* { dg-options "-mvsx -O2" } */
7
8 #include <altivec.h>
9
10 vector double
testd_var(double d,vector double vd,signed int si)11 testd_var (double d, vector double vd, signed int si)
12 {
13 return vec_insert (d, vd, si);
14 }
15
16 vector double
testd_cst(double d,vector double vd)17 testd_cst (double d, vector double vd)
18 {
19 return vec_insert (d, vd, 1);
20 }
21 /* The number of xxpermdi instructions varies between
22 P7,P8,P9, ensure at least one hit. */
23 /* { dg-final { scan-assembler {\mxxpermdi\M} } } */
24
25 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
26
27 /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { ! has_arch_pwr7 } } } } */
28 /* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { ! has_arch_pwr7 } } } } */
29 /* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { ! has_arch_pwr7 } } } } */
30
31 /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
32 /* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
33
34 /* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
35 /* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
36 /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
37 /* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
38
39