1 /* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987-2013 Free Software Foundation, Inc. 3 Contributed by Michael Tiemann (tiemann@cygnus.com). 4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5 at Cygnus Support. 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GCC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #include "config/vxworks-dummy.h" 24 25 /* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () 29 30 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ 31 /* #define SPARC_BI_ARCH */ 32 33 /* Macro used later in this file to determine default architecture. */ 34 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 35 36 /* TARGET_ARCH{32,64} are the main macros to decide which of the two 37 architectures to compile for. We allow targets to choose compile time or 38 runtime selection. */ 39 #ifdef IN_LIBGCC2 40 #if defined(__sparcv9) || defined(__arch64__) 41 #define TARGET_ARCH32 0 42 #else 43 #define TARGET_ARCH32 1 44 #endif /* sparc64 */ 45 #else 46 #ifdef SPARC_BI_ARCH 47 #define TARGET_ARCH32 (! TARGET_64BIT) 48 #else 49 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) 50 #endif /* SPARC_BI_ARCH */ 51 #endif /* IN_LIBGCC2 */ 52 #define TARGET_ARCH64 (! TARGET_ARCH32) 53 54 /* Code model selection in 64-bit environment. 55 56 The machine mode used for addresses is 32-bit wide: 57 58 TARGET_CM_32: 32-bit address space. 59 It is the code model used when generating 32-bit code. 60 61 The machine mode used for addresses is 64-bit wide: 62 63 TARGET_CM_MEDLOW: 32-bit address space. 64 The executable must be in the low 32 bits of memory. 65 This avoids generating %uhi and %ulo terms. Programs 66 can be statically or dynamically linked. 67 68 TARGET_CM_MEDMID: 44-bit address space. 69 The executable must be in the low 44 bits of memory, 70 and the %[hml]44 terms are used. The text and data 71 segments have a maximum size of 2GB (31-bit span). 72 The maximum offset from any instruction to the label 73 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 74 75 TARGET_CM_MEDANY: 64-bit address space. 76 The text and data segments have a maximum size of 2GB 77 (31-bit span) and may be located anywhere in memory. 78 The maximum offset from any instruction to the label 79 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 80 81 TARGET_CM_EMBMEDANY: 64-bit address space. 82 The text and data segments have a maximum size of 2GB 83 (31-bit span) and may be located anywhere in memory. 84 The global register %g4 contains the start address of 85 the data segment. Programs are statically linked and 86 PIC is not supported. 87 88 Different code models are not supported in 32-bit environment. */ 89 90 enum cmodel { 91 CM_32, 92 CM_MEDLOW, 93 CM_MEDMID, 94 CM_MEDANY, 95 CM_EMBMEDANY 96 }; 97 98 /* One of CM_FOO. */ 99 extern enum cmodel sparc_cmodel; 100 101 /* V9 code model selection. */ 102 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) 103 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) 104 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) 105 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) 106 107 #define SPARC_DEFAULT_CMODEL CM_32 108 109 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO) 110 which requires the following macro to be true if enabled. Prior to V9, 111 there are no instructions to even talk about memory synchronization. 112 Note that the UltraSPARC III processors don't implement RMO, unlike the 113 UltraSPARC II processors. Niagara, Niagara-2, and Niagara-3 do not 114 implement RMO either. 115 116 Default to false; for example, Solaris never enables RMO, only ever uses 117 total memory ordering (TMO). */ 118 #define SPARC_RELAXED_ORDERING false 119 120 /* Do not use the .note.GNU-stack convention by default. */ 121 #define NEED_INDICATE_EXEC_STACK 0 122 123 /* This is call-clobbered in the normal ABI, but is reserved in the 124 home grown (aka upward compatible) embedded ABI. */ 125 #define EMBMEDANY_BASE_REG "%g4" 126 127 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 128 and specified by the user via --with-cpu=foo. 129 This specifies the cpu implementation, not the architecture size. */ 130 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 131 capable cpu's. */ 132 #define TARGET_CPU_sparc 0 133 #define TARGET_CPU_v7 0 /* alias */ 134 #define TARGET_CPU_cypress 0 /* alias */ 135 #define TARGET_CPU_v8 1 /* generic v8 implementation */ 136 #define TARGET_CPU_supersparc 2 137 #define TARGET_CPU_hypersparc 3 138 #define TARGET_CPU_leon 4 139 #define TARGET_CPU_leon3 5 140 #define TARGET_CPU_leon3v7 6 141 #define TARGET_CPU_sparclite 7 142 #define TARGET_CPU_f930 7 /* alias */ 143 #define TARGET_CPU_f934 7 /* alias */ 144 #define TARGET_CPU_sparclite86x 8 145 #define TARGET_CPU_sparclet 9 146 #define TARGET_CPU_tsc701 9 /* alias */ 147 #define TARGET_CPU_v9 10 /* generic v9 implementation */ 148 #define TARGET_CPU_sparcv9 10 /* alias */ 149 #define TARGET_CPU_sparc64 10 /* alias */ 150 #define TARGET_CPU_ultrasparc 11 151 #define TARGET_CPU_ultrasparc3 12 152 #define TARGET_CPU_niagara 13 153 #define TARGET_CPU_niagara2 14 154 #define TARGET_CPU_niagara3 15 155 #define TARGET_CPU_niagara4 16 156 157 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 158 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 159 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ 160 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ 161 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ 162 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ 163 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 164 165 #define CPP_CPU32_DEFAULT_SPEC "" 166 #define ASM_CPU32_DEFAULT_SPEC "" 167 168 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 169 /* ??? What does Sun's CC pass? */ 170 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 171 /* ??? It's not clear how other assemblers will handle this, so by default 172 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 173 is handled in sol2.h. */ 174 #define ASM_CPU64_DEFAULT_SPEC "-Av9" 175 #endif 176 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 177 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 178 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" 179 #endif 180 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 181 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 182 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 183 #endif 184 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara 185 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 186 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 187 #endif 188 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 189 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 190 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 191 #endif 192 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 193 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 194 #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG 195 #endif 196 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 197 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 198 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG 199 #endif 200 201 #else 202 203 #define CPP_CPU64_DEFAULT_SPEC "" 204 #define ASM_CPU64_DEFAULT_SPEC "" 205 206 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 207 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 208 #define CPP_CPU32_DEFAULT_SPEC "" 209 #define ASM_CPU32_DEFAULT_SPEC "" 210 #endif 211 212 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 213 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 214 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 215 #endif 216 217 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 218 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 219 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 220 #endif 221 222 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 223 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 224 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 225 #endif 226 227 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 228 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 229 #define ASM_CPU32_DEFAULT_SPEC "" 230 #endif 231 232 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 233 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 234 #define ASM_CPU32_DEFAULT_SPEC "" 235 #endif 236 237 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \ 238 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 239 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" 240 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG 241 #endif 242 243 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 244 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__" 245 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG 246 #endif 247 248 #endif 249 250 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 251 #error Unrecognized value in TARGET_CPU_DEFAULT. 252 #endif 253 254 #ifdef SPARC_BI_ARCH 255 256 #define CPP_CPU_DEFAULT_SPEC \ 257 (DEFAULT_ARCH32_P ? "\ 258 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 259 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 260 " : "\ 261 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 262 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 263 ") 264 #define ASM_CPU_DEFAULT_SPEC \ 265 (DEFAULT_ARCH32_P ? "\ 266 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 267 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 268 " : "\ 269 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 270 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 271 ") 272 273 #else /* !SPARC_BI_ARCH */ 274 275 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 276 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 277 278 #endif /* !SPARC_BI_ARCH */ 279 280 /* Define macros to distinguish architectures. */ 281 282 /* Common CPP definitions used by CPP_SPEC amongst the various targets 283 for handling -mcpu=xxx switches. */ 284 #define CPP_CPU_SPEC "\ 285 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 286 %{mcpu=sparclite:-D__sparclite__} \ 287 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 288 %{mcpu=sparclite86x:-D__sparclite86x__} \ 289 %{mcpu=v8:-D__sparc_v8__} \ 290 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 291 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 292 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ 293 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ 294 %{mcpu=leon3v7:-D__leon__} \ 295 %{mcpu=v9:-D__sparc_v9__} \ 296 %{mcpu=ultrasparc:-D__sparc_v9__} \ 297 %{mcpu=ultrasparc3:-D__sparc_v9__} \ 298 %{mcpu=niagara:-D__sparc_v9__} \ 299 %{mcpu=niagara2:-D__sparc_v9__} \ 300 %{mcpu=niagara3:-D__sparc_v9__} \ 301 %{mcpu=niagara4:-D__sparc_v9__} \ 302 %{!mcpu*:%(cpp_cpu_default)} \ 303 " 304 #define CPP_ARCH32_SPEC "" 305 #define CPP_ARCH64_SPEC "-D__arch64__" 306 307 #define CPP_ARCH_DEFAULT_SPEC \ 308 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 309 310 #define CPP_ARCH_SPEC "\ 311 %{m32:%(cpp_arch32)} \ 312 %{m64:%(cpp_arch64)} \ 313 %{!m32:%{!m64:%(cpp_arch_default)}} \ 314 " 315 316 /* Macros to distinguish the endianness, window model and FP support. */ 317 #define CPP_OTHER_SPEC "\ 318 %{mflat:-D_FLAT} \ 319 %{msoft-float:-D_SOFT_FLOAT} \ 320 " 321 322 /* Macros to distinguish the particular subtarget. */ 323 #define CPP_SUBTARGET_SPEC "" 324 325 #define CPP_SPEC \ 326 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)" 327 328 /* This used to translate -dalign to -malign, but that is no good 329 because it can't turn off the usual meaning of making debugging dumps. */ 330 331 #define CC1_SPEC "" 332 333 /* Override in target specific files. */ 334 #define ASM_CPU_SPEC "\ 335 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 336 %{mcpu=sparclite:-Asparclite} \ 337 %{mcpu=sparclite86x:-Asparclite} \ 338 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 339 %{mcpu=v8:-Av8} \ 340 %{mcpu=supersparc:-Av8} \ 341 %{mcpu=hypersparc:-Av8} \ 342 %{mcpu=leon:" AS_LEON_FLAG "} \ 343 %{mcpu=leon3:" AS_LEON_FLAG "} \ 344 %{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ 345 %{mv8plus:-Av8plus} \ 346 %{mcpu=v9:-Av9} \ 347 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 348 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 349 %{mcpu=niagara:%{!mv8plus:-Av9b}} \ 350 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ 351 %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ 352 %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \ 353 %{!mcpu*:%(asm_cpu_default)} \ 354 " 355 356 /* Word size selection, among other things. 357 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 358 359 #define ASM_ARCH32_SPEC "-32" 360 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 361 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 362 #else 363 #define ASM_ARCH64_SPEC "-64" 364 #endif 365 #define ASM_ARCH_DEFAULT_SPEC \ 366 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 367 368 #define ASM_ARCH_SPEC "\ 369 %{m32:%(asm_arch32)} \ 370 %{m64:%(asm_arch64)} \ 371 %{!m32:%{!m64:%(asm_arch_default)}} \ 372 " 373 374 #ifdef HAVE_AS_RELAX_OPTION 375 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 376 #else 377 #define ASM_RELAX_SPEC "" 378 #endif 379 380 /* Special flags to the Sun-4 assembler when using pipe for input. */ 381 382 #define ASM_SPEC "\ 383 %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \ 384 %(asm_cpu) %(asm_relax)" 385 386 /* This macro defines names of additional specifications to put in the specs 387 that can be used in various specifications like CC1_SPEC. Its definition 388 is an initializer with a subgrouping for each command option. 389 390 Each subgrouping contains a string constant, that defines the 391 specification name, and a string constant that used by the GCC driver 392 program. 393 394 Do not define this macro if it does not need to do anything. */ 395 396 #define EXTRA_SPECS \ 397 { "cpp_cpu", CPP_CPU_SPEC }, \ 398 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 399 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 400 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 401 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 402 { "cpp_arch", CPP_ARCH_SPEC }, \ 403 { "cpp_other", CPP_OTHER_SPEC }, \ 404 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 405 { "asm_cpu", ASM_CPU_SPEC }, \ 406 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 407 { "asm_arch32", ASM_ARCH32_SPEC }, \ 408 { "asm_arch64", ASM_ARCH64_SPEC }, \ 409 { "asm_relax", ASM_RELAX_SPEC }, \ 410 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 411 { "asm_arch", ASM_ARCH_SPEC }, \ 412 SUBTARGET_EXTRA_SPECS 413 414 #define SUBTARGET_EXTRA_SPECS 415 416 /* Because libgcc can generate references back to libc (via .umul etc.) we have 417 to list libc again after the second libgcc. */ 418 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" 419 420 421 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 422 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 423 424 /* ??? This should be 32 bits for v9 but what can we do? */ 425 #define WCHAR_TYPE "short unsigned int" 426 #define WCHAR_TYPE_SIZE 16 427 428 /* Mask of all CPU selection flags. */ 429 #define MASK_ISA \ 430 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 431 432 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. 433 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y 434 to get high 32 bits. False in V8+ or V9 because multiply stores 435 a 64-bit result in a register. */ 436 437 #define TARGET_HARD_MUL32 \ 438 ((TARGET_V8 || TARGET_SPARCLITE \ 439 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ 440 && ! TARGET_V8PLUS && TARGET_ARCH32) 441 442 #define TARGET_HARD_MUL \ 443 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ 444 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) 445 446 /* MASK_APP_REGS must always be the default because that's what 447 FIXED_REGISTERS is set to and -ffixed- is processed before 448 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process 449 -mno-app-regs). */ 450 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 451 452 /* Recast the cpu class to be the cpu attribute. 453 Every file includes us, but not every file includes insn-attr.h. */ 454 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 455 456 /* Support for a compile-time default CPU, et cetera. The rules are: 457 --with-cpu is ignored if -mcpu is specified. 458 --with-tune is ignored if -mtune is specified. 459 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 460 are specified. */ 461 #define OPTION_DEFAULT_SPECS \ 462 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 463 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 464 {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } 465 466 /* target machine storage layout */ 467 468 /* Define this if most significant bit is lowest numbered 469 in instructions that operate on numbered bit-fields. */ 470 #define BITS_BIG_ENDIAN 1 471 472 /* Define this if most significant byte of a word is the lowest numbered. */ 473 #define BYTES_BIG_ENDIAN 1 474 475 /* Define this if most significant word of a multiword number is the lowest 476 numbered. */ 477 #define WORDS_BIG_ENDIAN 1 478 479 #define MAX_BITS_PER_WORD 64 480 481 /* Width of a word, in units (bytes). */ 482 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 483 #ifdef IN_LIBGCC2 484 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 485 #else 486 #define MIN_UNITS_PER_WORD 4 487 #endif 488 489 /* Now define the sizes of the C data types. */ 490 #define SHORT_TYPE_SIZE 16 491 #define INT_TYPE_SIZE 32 492 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 493 #define LONG_LONG_TYPE_SIZE 64 494 #define FLOAT_TYPE_SIZE 32 495 #define DOUBLE_TYPE_SIZE 64 496 497 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the 498 SPARC ABI says that it is 128-bit wide. */ 499 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ 500 501 /* The widest floating-point format really supported by the hardware. */ 502 #define WIDEST_HARDWARE_FP_SIZE 64 503 504 /* Width in bits of a pointer. This is the size of ptr_mode. */ 505 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 506 507 /* This is the machine mode used for addresses. */ 508 #define Pmode (TARGET_ARCH64 ? DImode : SImode) 509 510 /* If we have to extend pointers (only when TARGET_ARCH64 and not 511 TARGET_PTR64), we want to do it unsigned. This macro does nothing 512 if ptr_mode and Pmode are the same. */ 513 #define POINTERS_EXTEND_UNSIGNED 1 514 515 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 516 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 517 518 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 519 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 520 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ 521 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 522 /* Temporary hack until the FIXME above is fixed. */ 523 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 524 525 /* ALIGN FRAMES on double word boundaries */ 526 #define SPARC_STACK_ALIGN(LOC) \ 527 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 528 529 /* Allocation boundary (in *bits*) for the code of a function. */ 530 #define FUNCTION_BOUNDARY 32 531 532 /* Alignment of field after `int : 0' in a structure. */ 533 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 534 535 /* Every structure's size must be a multiple of this. */ 536 #define STRUCTURE_SIZE_BOUNDARY 8 537 538 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 539 #define PCC_BITFIELD_TYPE_MATTERS 1 540 541 /* No data type wants to be aligned rounder than this. */ 542 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 543 544 /* The best alignment to use in cases where we have a choice. */ 545 #define FASTEST_ALIGNMENT 64 546 547 /* Define this macro as an expression for the alignment of a structure 548 (given by STRUCT as a tree node) if the alignment computed in the 549 usual way is COMPUTED and the alignment explicitly specified was 550 SPECIFIED. 551 552 The default is to use SPECIFIED if it is larger; otherwise, use 553 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 554 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 555 (TARGET_FASTER_STRUCTS ? \ 556 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 557 || TREE_CODE (STRUCT) == UNION_TYPE \ 558 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 559 && TYPE_FIELDS (STRUCT) != 0 \ 560 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 561 : MAX ((COMPUTED), (SPECIFIED))) \ 562 : MAX ((COMPUTED), (SPECIFIED))) 563 564 /* An integer expression for the size in bits of the largest integer machine 565 mode that should actually be used. We allow pairs of registers. */ 566 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode) 567 568 /* We need 2 words, so we can save the stack pointer and the return register 569 of the function containing a non-local goto target. */ 570 #define STACK_SAVEAREA_MODE(LEVEL) \ 571 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode) 572 573 /* Make strings word-aligned so strcpy from constants will be faster. */ 574 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 575 ((TREE_CODE (EXP) == STRING_CST \ 576 && (ALIGN) < FASTEST_ALIGNMENT) \ 577 ? FASTEST_ALIGNMENT : (ALIGN)) 578 579 /* Make arrays of chars word-aligned for the same reasons. */ 580 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 581 (TREE_CODE (TYPE) == ARRAY_TYPE \ 582 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 583 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 584 585 /* Make local arrays of chars word-aligned for the same reasons. */ 586 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 587 588 /* Set this nonzero if move instructions will actually fail to work 589 when given unaligned data. */ 590 #define STRICT_ALIGNMENT 1 591 592 /* Things that must be doubleword aligned cannot go in the text section, 593 because the linker fails to align the text section enough! 594 Put them in the data section. This macro is only used in this file. */ 595 #define MAX_TEXT_ALIGN 32 596 597 /* Standard register usage. */ 598 599 /* Number of actual hardware registers. 600 The hardware registers are assigned numbers for the compiler 601 from 0 to just below FIRST_PSEUDO_REGISTER. 602 All registers that the compiler knows about must be given numbers, 603 even those that are not normally considered general registers. 604 605 SPARC has 32 integer registers and 32 floating point registers. 606 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not 607 accessible. We still account for them to simplify register computations 608 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 609 32+32+32+4 == 100. 610 Register 100 is used as the integer condition code register. 611 Register 101 is used as the soft frame pointer register. */ 612 613 #define FIRST_PSEUDO_REGISTER 103 614 615 #define SPARC_FIRST_INT_REG 0 616 #define SPARC_LAST_INT_REG 31 617 #define SPARC_FIRST_FP_REG 32 618 /* Additional V9 fp regs. */ 619 #define SPARC_FIRST_V9_FP_REG 64 620 #define SPARC_LAST_V9_FP_REG 95 621 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 622 #define SPARC_FIRST_V9_FCC_REG 96 623 #define SPARC_LAST_V9_FCC_REG 99 624 /* V8 fcc reg. */ 625 #define SPARC_FCC_REG 96 626 /* Integer CC reg. We don't distinguish %icc from %xcc. */ 627 #define SPARC_ICC_REG 100 628 #define SPARC_GSR_REG 102 629 630 /* Nonzero if REGNO is an fp reg. */ 631 #define SPARC_FP_REG_P(REGNO) \ 632 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 633 634 /* Nonzero if REGNO is an int reg. */ 635 #define SPARC_INT_REG_P(REGNO) \ 636 (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG) 637 638 /* Argument passing regs. */ 639 #define SPARC_OUTGOING_INT_ARG_FIRST 8 640 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) 641 #define SPARC_FP_ARG_FIRST 32 642 643 /* 1 for registers that have pervasive standard uses 644 and are not available for the register allocator. 645 646 On non-v9 systems: 647 g1 is free to use as temporary. 648 g2-g4 are reserved for applications. Gcc normally uses them as 649 temporaries, but this can be disabled via the -mno-app-regs option. 650 g5 through g7 are reserved for the operating system. 651 652 On v9 systems: 653 g1,g5 are free to use as temporaries, and are free to use between calls 654 if the call is to an external function via the PLT. 655 g4 is free to use as a temporary in the non-embedded case. 656 g4 is reserved in the embedded case. 657 g2-g3 are reserved for applications. Gcc normally uses them as 658 temporaries, but this can be disabled via the -mno-app-regs option. 659 g6-g7 are reserved for the operating system (or application in 660 embedded case). 661 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 662 currently be a fixed register until this pattern is rewritten. 663 Register 1 is also used when restoring call-preserved registers in large 664 stack frames. 665 666 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 667 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 668 */ 669 670 #define FIXED_REGISTERS \ 671 {1, 0, 2, 2, 2, 2, 1, 1, \ 672 0, 0, 0, 0, 0, 0, 1, 0, \ 673 0, 0, 0, 0, 0, 0, 0, 0, \ 674 0, 0, 0, 0, 0, 0, 0, 1, \ 675 \ 676 0, 0, 0, 0, 0, 0, 0, 0, \ 677 0, 0, 0, 0, 0, 0, 0, 0, \ 678 0, 0, 0, 0, 0, 0, 0, 0, \ 679 0, 0, 0, 0, 0, 0, 0, 0, \ 680 \ 681 0, 0, 0, 0, 0, 0, 0, 0, \ 682 0, 0, 0, 0, 0, 0, 0, 0, \ 683 0, 0, 0, 0, 0, 0, 0, 0, \ 684 0, 0, 0, 0, 0, 0, 0, 0, \ 685 \ 686 0, 0, 0, 0, 0, 1, 1} 687 688 /* 1 for registers not available across function calls. 689 These must include the FIXED_REGISTERS and also any 690 registers that can be used without being saved. 691 The latter must include the registers where values are returned 692 and the register where structure-value addresses are passed. 693 Aside from that, you can include as many other registers as you like. */ 694 695 #define CALL_USED_REGISTERS \ 696 {1, 1, 1, 1, 1, 1, 1, 1, \ 697 1, 1, 1, 1, 1, 1, 1, 1, \ 698 0, 0, 0, 0, 0, 0, 0, 0, \ 699 0, 0, 0, 0, 0, 0, 0, 1, \ 700 \ 701 1, 1, 1, 1, 1, 1, 1, 1, \ 702 1, 1, 1, 1, 1, 1, 1, 1, \ 703 1, 1, 1, 1, 1, 1, 1, 1, \ 704 1, 1, 1, 1, 1, 1, 1, 1, \ 705 \ 706 1, 1, 1, 1, 1, 1, 1, 1, \ 707 1, 1, 1, 1, 1, 1, 1, 1, \ 708 1, 1, 1, 1, 1, 1, 1, 1, \ 709 1, 1, 1, 1, 1, 1, 1, 1, \ 710 \ 711 1, 1, 1, 1, 1, 1, 1} 712 713 /* Return number of consecutive hard regs needed starting at reg REGNO 714 to hold something of mode MODE. 715 This is ordinarily the length in words of a value of mode MODE 716 but can be less for certain modes in special long registers. 717 718 On SPARC, ordinary registers hold 32 bits worth; 719 this means both integer and floating point registers. 720 On v9, integer regs hold 64 bits worth; floating point regs hold 721 32 bits worth (this includes the new fp regs as even the odd ones are 722 included in the hard register count). */ 723 724 #define HARD_REGNO_NREGS(REGNO, MODE) \ 725 ((REGNO) == SPARC_GSR_REG ? 1 : \ 726 (TARGET_ARCH64 \ 727 ? (SPARC_INT_REG_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM \ 728 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ 729 : (GET_MODE_SIZE (MODE) + 3) / 4) \ 730 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 731 732 /* Due to the ARCH64 discrepancy above we must override this next 733 macro too. */ 734 #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE) 735 736 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 737 See sparc.c for how we initialize this. */ 738 extern const int *hard_regno_mode_classes; 739 extern int sparc_mode_class[]; 740 741 /* ??? Because of the funny way we pass parameters we should allow certain 742 ??? types of float/complex values to be in integer registers during 743 ??? RTL generation. This only matters on arch32. */ 744 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 745 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 746 747 /* Value is 1 if it is OK to rename a hard register FROM to another hard 748 register TO. We cannot rename %g1 as it may be used before the save 749 register window instruction in the prologue. */ 750 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) 751 752 #define MODES_TIEABLE_P(MODE1, MODE2) sparc_modes_tieable_p (MODE1, MODE2) 753 754 /* Specify the registers used for certain standard purposes. 755 The values of these macros are register numbers. */ 756 757 /* Register to use for pushing function arguments. */ 758 #define STACK_POINTER_REGNUM 14 759 760 /* The stack bias (amount by which the hardware register is offset by). */ 761 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 762 763 /* Actual top-of-stack address is 92/176 greater than the contents of the 764 stack pointer register for !v9/v9. That is: 765 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 766 address, and 6*4 bytes for the 6 register parameters. 767 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 768 parameter regs. */ 769 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 770 771 /* Base register for access to local variables of the function. */ 772 #define HARD_FRAME_POINTER_REGNUM 30 773 774 /* The soft frame pointer does not have the stack bias applied. */ 775 #define FRAME_POINTER_REGNUM 101 776 777 /* Given the stack bias, the stack pointer isn't actually aligned. */ 778 #define INIT_EXPANDERS \ 779 do { \ 780 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \ 781 { \ 782 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ 783 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ 784 } \ 785 } while (0) 786 787 /* Base register for access to arguments of the function. */ 788 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 789 790 /* Register in which static-chain is passed to a function. This must 791 not be a register used by the prologue. */ 792 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 793 794 /* Register which holds the global offset table, if any. */ 795 796 #define GLOBAL_OFFSET_TABLE_REGNUM 23 797 798 /* Register which holds offset table for position-independent 799 data references. */ 800 801 #define PIC_OFFSET_TABLE_REGNUM \ 802 (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 803 804 /* Pick a default value we can notice from override_options: 805 !v9: Default is on. 806 v9: Default is off. 807 Originally it was -1, but later on the container of options changed to 808 unsigned byte, so we decided to pick 127 as default value, which does 809 reflect an undefined default value in case of 0/1. */ 810 811 #define DEFAULT_PCC_STRUCT_RETURN 127 812 813 /* Functions which return large structures get the address 814 to place the wanted value at offset 64 from the frame. 815 Must reserve 64 bytes for the in and local registers. 816 v9: Functions which return large structures get the address to place the 817 wanted value from an invisible first argument. */ 818 #define STRUCT_VALUE_OFFSET 64 819 820 /* Define the classes of registers for register constraints in the 821 machine description. Also define ranges of constants. 822 823 One of the classes must always be named ALL_REGS and include all hard regs. 824 If there is more than one class, another class must be named NO_REGS 825 and contain no registers. 826 827 The name GENERAL_REGS must be the name of a class (or an alias for 828 another name such as ALL_REGS). This is the class of registers 829 that is allowed by "g" or "r" in a register constraint. 830 Also, registers outside this class are allocated only when 831 instructions express preferences for them. 832 833 The classes must be numbered in nondecreasing order; that is, 834 a larger-numbered class must never be contained completely 835 in a smaller-numbered class. 836 837 For any two classes, it is very desirable that there be another 838 class that represents their union. */ 839 840 /* The SPARC has various kinds of registers: general, floating point, 841 and condition codes [well, it has others as well, but none that we 842 care directly about]. 843 844 For v9 we must distinguish between the upper and lower floating point 845 registers because the upper ones can't hold SFmode values. 846 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) 847 satisfying a group need for a class will also satisfy a single need for 848 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp 849 regs. 850 851 It is important that one class contains all the general and all the standard 852 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 853 because reg_class_record() will bias the selection in favor of fp regs, 854 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 855 because FP_REGS > GENERAL_REGS. 856 857 It is also important that one class contain all the general and all 858 the fp regs. Otherwise when spilling a DFmode reg, it may be from 859 EXTRA_FP_REGS but find_reloads() may use class 860 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die 861 because the compiler thinks it doesn't have a spill reg when in 862 fact it does. 863 864 v9 also has 4 floating point condition code registers. Since we don't 865 have a class that is the union of FPCC_REGS with either of the others, 866 it is important that it appear first. Otherwise the compiler will die 867 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 868 constraints. 869 870 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine 871 may try to use it to hold an SImode value. See register_operand. 872 ??? Should %fcc[0123] be handled similarly? 873 */ 874 875 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 876 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 877 ALL_REGS, LIM_REG_CLASSES }; 878 879 #define N_REG_CLASSES (int) LIM_REG_CLASSES 880 881 /* Give names of register classes as strings for dump file. */ 882 883 #define REG_CLASS_NAMES \ 884 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 885 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 886 "ALL_REGS" } 887 888 /* Define which registers fit in which classes. 889 This is an initializer for a vector of HARD_REG_SET 890 of length N_REG_CLASSES. */ 891 892 #define REG_CLASS_CONTENTS \ 893 {{0, 0, 0, 0}, /* NO_REGS */ \ 894 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 895 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 896 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 897 {0, -1, 0, 0}, /* FP_REGS */ \ 898 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 899 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 900 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 901 {-1, -1, -1, 0x7f}} /* ALL_REGS */ 902 903 /* The same information, inverted: 904 Return the class number of the smallest class containing 905 reg number REGNO. This could be a conditional expression 906 or could index an array. */ 907 908 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 909 910 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 911 912 /* Defines invalid mode changes. Borrowed from the PA port. 913 914 SImode loads to floating-point registers are not zero-extended. 915 The definition for LOAD_EXTEND_OP specifies that integer loads 916 narrower than BITS_PER_WORD will be zero-extended. As a result, 917 we inhibit changes from SImode unless they are to a mode that is 918 identical in size. 919 920 Likewise for SFmode, since word-mode paradoxical subregs are 921 problematic on big-endian architectures. */ 922 923 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 924 (TARGET_ARCH64 \ 925 && GET_MODE_SIZE (FROM) == 4 \ 926 && GET_MODE_SIZE (TO) != 4 \ 927 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) 928 929 /* This is the order in which to allocate registers normally. 930 931 We put %f0-%f7 last among the float registers, so as to make it more 932 likely that a pseudo-register which dies in the float return register 933 area will get allocated to the float return register, thus saving a move 934 instruction at the end of the function. 935 936 Similarly for integer return value registers. 937 938 We know in this case that we will not end up with a leaf function. 939 940 The register allocator is given the global and out registers first 941 because these registers are call clobbered and thus less useful to 942 global register allocation. 943 944 Next we list the local and in registers. They are not call clobbered 945 and thus very useful for global register allocation. We list the input 946 registers before the locals so that it is more likely the incoming 947 arguments received in those registers can just stay there and not be 948 reloaded. */ 949 950 #define REG_ALLOC_ORDER \ 951 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 952 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 953 15, /* %o7 */ \ 954 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 955 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 956 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 957 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 958 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 959 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 960 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 961 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 962 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 963 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 964 96, 97, 98, 99, /* %fcc0-3 */ \ 965 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */ 966 967 /* This is the order in which to allocate registers for 968 leaf functions. If all registers can fit in the global and 969 output registers, then we have the possibility of having a leaf 970 function. 971 972 The macro actually mentioned the input registers first, 973 because they get renumbered into the output registers once 974 we know really do have a leaf function. 975 976 To be more precise, this register allocation order is used 977 when %o7 is found to not be clobbered right before register 978 allocation. Normally, the reason %o7 would be clobbered is 979 due to a call which could not be transformed into a sibling 980 call. 981 982 As a consequence, it is possible to use the leaf register 983 allocation order and not end up with a leaf function. We will 984 not get suboptimal register allocation in that case because by 985 definition of being potentially leaf, there were no function 986 calls. Therefore, allocation order within the local register 987 window is not critical like it is when we do have function calls. */ 988 989 #define REG_LEAF_ALLOC_ORDER \ 990 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 991 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 992 15, /* %o7 */ \ 993 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 994 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 995 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 996 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 997 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 998 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 999 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1000 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1001 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1002 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1003 96, 97, 98, 99, /* %fcc0-3 */ \ 1004 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ 1005 1006 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () 1007 1008 extern char sparc_leaf_regs[]; 1009 #define LEAF_REGISTERS sparc_leaf_regs 1010 1011 extern char leaf_reg_remap[]; 1012 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 1013 1014 /* The class value for index registers, and the one for base regs. */ 1015 #define INDEX_REG_CLASS GENERAL_REGS 1016 #define BASE_REG_CLASS GENERAL_REGS 1017 1018 /* Local macro to handle the two v9 classes of FP regs. */ 1019 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1020 1021 /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */ 1022 #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20) 1023 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 1024 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 1025 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 1026 1027 /* 10- and 11-bit immediates are only used for a few specific insns. 1028 SMALL_INT is used throughout the port so we continue to use it. */ 1029 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 1030 1031 /* Predicate for constants that can be loaded with a sethi instruction. 1032 This is the general, 64-bit aware, bitwise version that ensures that 1033 only constants whose representation fits in the mask 1034 1035 0x00000000fffffc00 1036 1037 are accepted. It will reject, for example, negative SImode constants 1038 on 64-bit hosts, so correct handling is to mask the value beforehand 1039 according to the mode of the instruction. */ 1040 #define SPARC_SETHI_P(X) \ 1041 (((unsigned HOST_WIDE_INT) (X) \ 1042 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1043 1044 /* Version of the above predicate for SImode constants and below. */ 1045 #define SPARC_SETHI32_P(X) \ 1046 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1047 1048 /* On SPARC when not VIS3 it is not possible to directly move data 1049 between GENERAL_REGS and FP_REGS. */ 1050 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1051 ((FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) \ 1052 && (! TARGET_VIS3 \ 1053 || GET_MODE_SIZE (MODE) > 8 \ 1054 || GET_MODE_SIZE (MODE) < 4)) 1055 1056 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 1057 because the movsi and movsf patterns don't handle r/f moves. 1058 For v8 we copy the default definition. */ 1059 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1060 (TARGET_ARCH64 \ 1061 ? (GET_MODE_BITSIZE (MODE) < 32 \ 1062 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1063 : MODE) \ 1064 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ 1065 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ 1066 : MODE)) 1067 1068 /* Return the maximum number of consecutive registers 1069 needed to represent mode MODE in a register of class CLASS. */ 1070 /* On SPARC, this is the size of MODE in words. */ 1071 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1072 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1073 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1074 1075 /* Stack layout; function entry, exit and calling. */ 1076 1077 /* Define this if pushing a word on the stack 1078 makes the stack pointer a smaller address. */ 1079 #define STACK_GROWS_DOWNWARD 1080 1081 /* Define this to nonzero if the nominal address of the stack frame 1082 is at the high-address end of the local variables; 1083 that is, each additional local variable allocated 1084 goes at a more negative offset in the frame. */ 1085 #define FRAME_GROWS_DOWNWARD 1 1086 1087 /* Offset within stack frame to start allocating local variables at. 1088 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1089 first local allocated. Otherwise, it is the offset to the BEGINNING 1090 of the first local allocated. */ 1091 #define STARTING_FRAME_OFFSET 0 1092 1093 /* Offset of first parameter from the argument pointer register value. 1094 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1095 even if this function isn't going to use it. 1096 v9: This is 128 for the ins and locals. */ 1097 #define FIRST_PARM_OFFSET(FNDECL) \ 1098 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1099 1100 /* Offset from the argument pointer register value to the CFA. 1101 This is different from FIRST_PARM_OFFSET because the register window 1102 comes between the CFA and the arguments. */ 1103 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1104 1105 /* When a parameter is passed in a register, stack space is still 1106 allocated for it. 1107 !v9: All 6 possible integer registers have backing store allocated. 1108 v9: Only space for the arguments passed is allocated. */ 1109 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1110 meaning to the backend. Further, we need to be able to detect if a 1111 varargs/unprototyped function is called, as they may want to spill more 1112 registers than we've provided space. Ugly, ugly. So for now we retain 1113 all 6 slots even for v9. */ 1114 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1115 1116 /* Definitions for register elimination. */ 1117 1118 #define ELIMINABLE_REGS \ 1119 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1120 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1121 1122 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1123 do \ 1124 { \ 1125 (OFFSET) = sparc_initial_elimination_offset ((TO)); \ 1126 } \ 1127 while (0) 1128 1129 /* Keep the stack pointer constant throughout the function. 1130 This is both an optimization and a necessity: longjmp 1131 doesn't behave itself when the stack pointer moves within 1132 the function! */ 1133 #define ACCUMULATE_OUTGOING_ARGS 1 1134 1135 /* Define this macro if the target machine has "register windows". This 1136 C expression returns the register number as seen by the called function 1137 corresponding to register number OUT as seen by the calling function. 1138 Return OUT if register number OUT is not an outbound register. */ 1139 1140 #define INCOMING_REGNO(OUT) \ 1141 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1142 1143 /* Define this macro if the target machine has "register windows". This 1144 C expression returns the register number as seen by the calling function 1145 corresponding to register number IN as seen by the called function. 1146 Return IN if register number IN is not an inbound register. */ 1147 1148 #define OUTGOING_REGNO(IN) \ 1149 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1150 1151 /* Define this macro if the target machine has register windows. This 1152 C expression returns true if the register is call-saved but is in the 1153 register window. */ 1154 1155 #define LOCAL_REGNO(REGNO) \ 1156 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31) 1157 1158 /* Define the size of space to allocate for the return value of an 1159 untyped_call. */ 1160 1161 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) 1162 1163 /* 1 if N is a possible register number for function argument passing. 1164 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1165 1166 #define FUNCTION_ARG_REGNO_P(N) \ 1167 (TARGET_ARCH64 \ 1168 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ 1169 : ((N) >= 8 && (N) <= 13)) 1170 1171 /* Define a data type for recording info about an argument list 1172 during the scan of that argument list. This data type should 1173 hold all necessary information about the function itself 1174 and about the args processed so far, enough to enable macros 1175 such as FUNCTION_ARG to determine where the next arg should go. 1176 1177 On SPARC (!v9), this is a single integer, which is a number of words 1178 of arguments scanned so far (including the invisible argument, 1179 if any, which holds the structure-value-address). 1180 Thus 7 or more means all following args should go on the stack. 1181 1182 For v9, we also need to know whether a prototype is present. */ 1183 1184 struct sparc_args { 1185 int words; /* number of words passed so far */ 1186 int prototype_p; /* nonzero if a prototype is present */ 1187 int libcall_p; /* nonzero if a library call */ 1188 }; 1189 #define CUMULATIVE_ARGS struct sparc_args 1190 1191 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1192 for a call to a function whose data type is FNTYPE. 1193 For a library call, FNTYPE is 0. */ 1194 1195 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1196 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1197 1198 /* If defined, a C expression which determines whether, and in which direction, 1199 to pad out an argument with extra space. The value should be of type 1200 `enum direction': either `upward' to pad above the argument, 1201 `downward' to pad below, or `none' to inhibit padding. */ 1202 1203 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1204 function_arg_padding ((MODE), (TYPE)) 1205 1206 1207 /* Generate the special assembly code needed to tell the assembler whatever 1208 it might need to know about the return value of a function. 1209 1210 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1211 information to the assembler relating to peephole optimization (done in 1212 the assembler). */ 1213 1214 #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1215 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1216 1217 /* Output the special assembly code needed to tell the assembler some 1218 register is used as global register variable. 1219 1220 SPARC 64bit psABI declares registers %g2 and %g3 as application 1221 registers and %g6 and %g7 as OS registers. Any object using them 1222 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1223 and how they are used (scratch or some global variable). 1224 Linker will then refuse to link together objects which use those 1225 registers incompatibly. 1226 1227 Unless the registers are used for scratch, two different global 1228 registers cannot be declared to the same name, so in the unlikely 1229 case of a global register variable occupying more than one register 1230 we prefix the second and following registers with .gnu.part1. etc. */ 1231 1232 extern GTY(()) char sparc_hard_reg_printed[8]; 1233 1234 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 1235 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1236 do { \ 1237 if (TARGET_ARCH64) \ 1238 { \ 1239 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ 1240 int reg; \ 1241 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1242 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1243 { \ 1244 if (reg == (REGNO)) \ 1245 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1246 else \ 1247 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1248 reg, reg - (REGNO), (NAME)); \ 1249 sparc_hard_reg_printed[reg] = 1; \ 1250 } \ 1251 } \ 1252 } while (0) 1253 #endif 1254 1255 1256 /* Emit rtl for profiling. */ 1257 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1258 1259 /* All the work done in PROFILE_HOOK, but still required. */ 1260 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1261 1262 /* Set the name of the mcount function for the system. */ 1263 #define MCOUNT_FUNCTION "*mcount" 1264 1265 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1266 the stack pointer does not matter. The value is tested only in 1267 functions that have frame pointers. */ 1268 #define EXIT_IGNORE_STACK 1 1269 1270 /* Length in units of the trampoline for entering a nested function. */ 1271 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1272 1273 /* Alignment required for trampolines, in bits. */ 1274 #define TRAMPOLINE_ALIGNMENT 128 1275 1276 /* Generate RTL to flush the register windows so as to make arbitrary frames 1277 available. */ 1278 #define SETUP_FRAME_ADDRESSES() \ 1279 do { \ 1280 if (!TARGET_FLAT) \ 1281 emit_insn (gen_flush_register_windows ());\ 1282 } while (0) 1283 1284 /* Given an rtx for the address of a frame, 1285 return an rtx for the address of the word in the frame 1286 that holds the dynamic chain--the previous frame's address. */ 1287 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1288 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1289 1290 /* Given an rtx for the frame pointer, 1291 return an rtx for the address of the frame. */ 1292 #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS) 1293 1294 /* The return address isn't on the stack, it is in a register, so we can't 1295 access it from the current frame pointer. We can access it from the 1296 previous frame pointer though by reading a value from the register window 1297 save area. */ 1298 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1299 1300 /* This is the offset of the return address to the true next instruction to be 1301 executed for the current function. */ 1302 #define RETURN_ADDR_OFFSET \ 1303 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) 1304 1305 /* The current return address is in %i7. The return address of anything 1306 farther back is in the register window save area at [%fp+60]. */ 1307 /* ??? This ignores the fact that the actual return address is +8 for normal 1308 returns, and +12 for structure returns. */ 1309 #define RETURN_ADDR_REGNUM 31 1310 #define RETURN_ADDR_RTX(count, frame) \ 1311 ((count == -1) \ 1312 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \ 1313 : gen_rtx_MEM (Pmode, \ 1314 memory_address (Pmode, plus_constant (Pmode, frame, \ 1315 15 * UNITS_PER_WORD \ 1316 + SPARC_STACK_BIAS)))) 1317 1318 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 1319 +12, but always using +8 is close enough for frame unwind purposes. 1320 Actually, just using %o7 is close enough for unwinding, but %o7+8 1321 is something you can return to. */ 1322 #define INCOMING_RETURN_ADDR_REGNUM 15 1323 #define INCOMING_RETURN_ADDR_RTX \ 1324 plus_constant (word_mode, \ 1325 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8) 1326 #define DWARF_FRAME_RETURN_COLUMN \ 1327 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM) 1328 1329 /* The offset from the incoming value of %sp to the top of the stack frame 1330 for the current function. On sparc64, we have to account for the stack 1331 bias if present. */ 1332 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 1333 1334 /* Describe how we implement __builtin_eh_return. */ 1335 #define EH_RETURN_REGNUM 1 1336 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 1337 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) 1338 1339 /* Define registers used by the epilogue and return instruction. */ 1340 #define EPILOGUE_USES(REGNO) \ 1341 ((REGNO) == RETURN_ADDR_REGNUM \ 1342 || (TARGET_FLAT \ 1343 && epilogue_completed \ 1344 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \ 1345 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM)) 1346 1347 /* Select a format to encode pointers in exception handling data. CODE 1348 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1349 true if the symbol may be affected by dynamic relocations. 1350 1351 If assembler and linker properly support .uaword %r_disp32(foo), 1352 then use PC relative 32-bit relocations instead of absolute relocs 1353 for shared libraries. On sparc64, use pc relative 32-bit relocs even 1354 for binaries, to save memory. 1355 1356 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 1357 symbol %r_disp32() is against was not local, but .hidden. In that 1358 case, we have to use DW_EH_PE_absptr for pic personality. */ 1359 #ifdef HAVE_AS_SPARC_UA_PCREL 1360 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 1361 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1362 (flag_pic \ 1363 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 1364 : ((TARGET_ARCH64 && ! GLOBAL) \ 1365 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1366 : DW_EH_PE_absptr)) 1367 #else 1368 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1369 (flag_pic \ 1370 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 1371 : ((TARGET_ARCH64 && ! GLOBAL) \ 1372 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1373 : DW_EH_PE_absptr)) 1374 #endif 1375 1376 /* Emit a PC-relative relocation. */ 1377 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1378 do { \ 1379 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1380 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 1381 assemble_name (FILE, LABEL); \ 1382 fputc (')', FILE); \ 1383 } while (0) 1384 #endif 1385 1386 /* Addressing modes, and classification of registers for them. */ 1387 1388 /* Macros to check register numbers against specific register classes. */ 1389 1390 /* These assume that REGNO is a hard or pseudo reg number. 1391 They give nonzero only if REGNO is a hard reg of the suitable class 1392 or a pseudo reg currently allocated to a suitable hard reg. 1393 Since they use reg_renumber, they are safe only once reg_renumber 1394 has been allocated, which happens in reginfo.c during register 1395 allocation. */ 1396 1397 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1398 (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \ 1399 || (REGNO) == FRAME_POINTER_REGNUM \ 1400 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 1401 1402 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 1403 1404 #define REGNO_OK_FOR_FP_P(REGNO) \ 1405 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 1406 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 1407 1408 #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1409 (TARGET_V9 \ 1410 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 1411 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 1412 1413 /* Maximum number of registers that can appear in a valid memory address. */ 1414 1415 #define MAX_REGS_PER_ADDRESS 2 1416 1417 /* Recognize any constant value that is a valid address. 1418 When PIC, we do not accept an address that would require a scratch reg 1419 to load into a register. */ 1420 1421 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1422 1423 /* Define this, so that when PIC, reload won't try to reload invalid 1424 addresses which require two reload registers. */ 1425 1426 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1427 1428 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 1429 1430 #ifdef HAVE_AS_OFFSETABLE_LO10 1431 #define USE_AS_OFFSETABLE_LO10 1 1432 #else 1433 #define USE_AS_OFFSETABLE_LO10 0 1434 #endif 1435 1436 /* Try a machine-dependent way of reloading an illegitimate address 1437 operand. If we find one, push the reload and jump to WIN. This 1438 macro is used in only one place: `find_reloads_address' in reload.c. */ 1439 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1440 do { \ 1441 int win; \ 1442 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1443 (int)(TYPE), (IND_LEVELS), &win); \ 1444 if (win) \ 1445 goto WIN; \ 1446 } while (0) 1447 1448 /* Specify the machine mode that this machine uses 1449 for the index in the tablejump instruction. */ 1450 /* If we ever implement any of the full models (such as CM_FULLANY), 1451 this has to be DImode in that case */ 1452 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1453 #define CASE_VECTOR_MODE \ 1454 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 1455 #else 1456 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 1457 we have to sign extend which slows things down. */ 1458 #define CASE_VECTOR_MODE \ 1459 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 1460 #endif 1461 1462 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1463 #define DEFAULT_SIGNED_CHAR 1 1464 1465 /* Max number of bytes we can move from memory to memory 1466 in one reasonably fast instruction. */ 1467 #define MOVE_MAX 8 1468 1469 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1470 move-instruction pairs, we will do a movmem or libcall instead. */ 1471 1472 #define MOVE_RATIO(speed) ((speed) ? 8 : 3) 1473 1474 /* Define if operations between registers always perform the operation 1475 on the full register even if a narrower mode is specified. */ 1476 #define WORD_REGISTER_OPERATIONS 1477 1478 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1479 will either zero-extend or sign-extend. The value of this macro should 1480 be the code that says which one of the two operations is implicitly 1481 done, UNKNOWN if none. */ 1482 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1483 1484 /* Nonzero if access to memory by bytes is slow and undesirable. 1485 For RISC chips, it means that access to memory by bytes is no 1486 better than access by words when possible, so grab a whole word 1487 and maybe make use of that. */ 1488 #define SLOW_BYTE_ACCESS 1 1489 1490 /* Define this to be nonzero if shift instructions ignore all but the low-order 1491 few bits. */ 1492 #define SHIFT_COUNT_TRUNCATED 1 1493 1494 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1495 is done just by pretending it is already truncated. */ 1496 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1497 1498 /* For SImode, we make sure the top 32-bits of the register are clear and 1499 then we subtract 32 from the lzd instruction result. */ 1500 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1501 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 1502 1503 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1504 return the mode to be used for the comparison. For floating-point, 1505 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 1506 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 1507 processing is needed. */ 1508 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 1509 1510 /* Return nonzero if MODE implies a floating point inequality can be 1511 reversed. For SPARC this is always true because we have a full 1512 compliment of ordered and unordered comparisons, but until generic 1513 code knows how to reverse it correctly we keep the old definition. */ 1514 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 1515 1516 /* A function address in a call instruction for indexing purposes. */ 1517 #define FUNCTION_MODE Pmode 1518 1519 /* Define this if addresses of constant functions 1520 shouldn't be put through pseudo regs where they can be cse'd. 1521 Desirable on machines where ordinary constants are expensive 1522 but a CALL with constant address is cheap. */ 1523 #define NO_FUNCTION_CSE 1524 1525 /* The _Q_* comparison libcalls return booleans. */ 1526 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 1527 1528 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such 1529 that the inputs are fully consumed before the output memory is clobbered. */ 1530 1531 #define TARGET_BUGGY_QP_LIB 0 1532 1533 /* Assume by default that we do not have the Solaris-specific conversion 1534 routines nor 64-bit integer multiply and divide routines. */ 1535 1536 #define SUN_CONVERSION_LIBFUNCS 0 1537 #define DITF_CONVERSION_LIBFUNCS 0 1538 #define SUN_INTEGER_MULTIPLY_64 0 1539 1540 /* Provide the cost of a branch. For pre-v9 processors we use 1541 a value of 3 to take into account the potential annulling of 1542 the delay slot (which ends up being a bubble in the pipeline slot) 1543 plus a cycle to take into consideration the instruction cache 1544 effects. 1545 1546 On v9 and later, which have branch prediction facilities, we set 1547 it to the depth of the pipeline as that is the cost of a 1548 mispredicted branch. 1549 1550 On Niagara, normal branches insert 3 bubbles into the pipe 1551 and annulled branches insert 4 bubbles. 1552 1553 On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas 1554 a taken branch costs 6 cycles. */ 1555 1556 #define BRANCH_COST(speed_p, predictable_p) \ 1557 ((sparc_cpu == PROCESSOR_V9 \ 1558 || sparc_cpu == PROCESSOR_ULTRASPARC) \ 1559 ? 7 \ 1560 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 1561 ? 9 \ 1562 : (sparc_cpu == PROCESSOR_NIAGARA \ 1563 ? 4 \ 1564 : ((sparc_cpu == PROCESSOR_NIAGARA2 \ 1565 || sparc_cpu == PROCESSOR_NIAGARA3) \ 1566 ? 5 \ 1567 : 3)))) 1568 1569 /* Control the assembler format that we output. */ 1570 1571 /* A C string constant describing how to begin a comment in the target 1572 assembler language. The compiler assumes that the comment will end at 1573 the end of the line. */ 1574 1575 #define ASM_COMMENT_START "!" 1576 1577 /* Output to assembler file text saying following lines 1578 may contain character constants, extra white space, comments, etc. */ 1579 1580 #define ASM_APP_ON "" 1581 1582 /* Output to assembler file text saying following lines 1583 no longer contain unusual constructs. */ 1584 1585 #define ASM_APP_OFF "" 1586 1587 /* How to refer to registers in assembler output. 1588 This sequence is indexed by compiler's hard-register-number (see above). */ 1589 1590 #define REGISTER_NAMES \ 1591 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 1592 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 1593 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 1594 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 1595 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 1596 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 1597 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 1598 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 1599 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 1600 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 1601 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 1602 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 1603 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" } 1604 1605 /* Define additional names for use in asm clobbers and asm declarations. */ 1606 1607 #define ADDITIONAL_REGISTER_NAMES \ 1608 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 1609 1610 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 1611 can run past this up to a continuation point. Once we used 1500, but 1612 a single entry in C++ can run more than 500 bytes, due to the length of 1613 mangled symbol names. dbxout.c should really be fixed to do 1614 continuations when they are actually needed instead of trying to 1615 guess... */ 1616 #define DBX_CONTIN_LENGTH 1000 1617 1618 /* This is how to output a command to make the user-level label named NAME 1619 defined for reference from other files. */ 1620 1621 /* Globalizing directive for a label. */ 1622 #define GLOBAL_ASM_OP "\t.global " 1623 1624 /* The prefix to add to user-visible assembler symbols. */ 1625 1626 #define USER_LABEL_PREFIX "_" 1627 1628 /* This is how to store into the string LABEL 1629 the symbol_ref name of an internal numbered label where 1630 PREFIX is the class of label and NUM is the number within the class. 1631 This is suitable for output with `assemble_name'. */ 1632 1633 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1634 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 1635 1636 /* This is how we hook in and defer the case-vector until the end of 1637 the function. */ 1638 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 1639 sparc_defer_case_vector ((LAB),(VEC), 0) 1640 1641 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 1642 sparc_defer_case_vector ((LAB),(VEC), 1) 1643 1644 /* This is how to output an element of a case-vector that is absolute. */ 1645 1646 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1647 do { \ 1648 char label[30]; \ 1649 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1650 if (CASE_VECTOR_MODE == SImode) \ 1651 fprintf (FILE, "\t.word\t"); \ 1652 else \ 1653 fprintf (FILE, "\t.xword\t"); \ 1654 assemble_name (FILE, label); \ 1655 fputc ('\n', FILE); \ 1656 } while (0) 1657 1658 /* This is how to output an element of a case-vector that is relative. 1659 (SPARC uses such vectors only when generating PIC.) */ 1660 1661 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1662 do { \ 1663 char label[30]; \ 1664 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 1665 if (CASE_VECTOR_MODE == SImode) \ 1666 fprintf (FILE, "\t.word\t"); \ 1667 else \ 1668 fprintf (FILE, "\t.xword\t"); \ 1669 assemble_name (FILE, label); \ 1670 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 1671 fputc ('-', FILE); \ 1672 assemble_name (FILE, label); \ 1673 fputc ('\n', FILE); \ 1674 } while (0) 1675 1676 /* This is what to output before and after case-vector (both 1677 relative and absolute). If .subsection -1 works, we put case-vectors 1678 at the beginning of the current section. */ 1679 1680 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1681 1682 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 1683 fprintf(FILE, "\t.subsection\t-1\n") 1684 1685 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 1686 fprintf(FILE, "\t.previous\n") 1687 1688 #endif 1689 1690 /* This is how to output an assembler line 1691 that says to advance the location counter 1692 to a multiple of 2**LOG bytes. */ 1693 1694 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1695 if ((LOG) != 0) \ 1696 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 1697 1698 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1699 fprintf (FILE, "\t.skip " HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 1700 1701 /* This says how to output an assembler line 1702 to define a global common symbol. */ 1703 1704 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1705 ( fputs ("\t.common ", (FILE)), \ 1706 assemble_name ((FILE), (NAME)), \ 1707 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 1708 1709 /* This says how to output an assembler line to define a local common 1710 symbol. */ 1711 1712 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 1713 ( fputs ("\t.reserve ", (FILE)), \ 1714 assemble_name ((FILE), (NAME)), \ 1715 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 1716 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 1717 1718 /* A C statement (sans semicolon) to output to the stdio stream 1719 FILE the assembler definition of uninitialized global DECL named 1720 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 1721 Try to use asm_output_aligned_bss to implement this macro. */ 1722 1723 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1724 do { \ 1725 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 1726 } while (0) 1727 1728 /* Output #ident as a .ident. */ 1729 1730 #undef TARGET_ASM_OUTPUT_IDENT 1731 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive 1732 1733 /* Prettify the assembly. */ 1734 1735 extern int sparc_indent_opcode; 1736 1737 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ 1738 do { \ 1739 if (sparc_indent_opcode) \ 1740 { \ 1741 putc (' ', FILE); \ 1742 sparc_indent_opcode = 0; \ 1743 } \ 1744 } while (0) 1745 1746 /* TLS support defaulting to original Sun flavor. GNU extensions 1747 must be activated in separate configuration files. */ 1748 #ifdef HAVE_AS_TLS 1749 #define TARGET_TLS 1 1750 #else 1751 #define TARGET_TLS 0 1752 #endif 1753 1754 #define TARGET_SUN_TLS TARGET_TLS 1755 #define TARGET_GNU_TLS 0 1756 1757 #ifdef HAVE_AS_FMAF_HPC_VIS3 1758 #define AS_NIAGARA3_FLAG "d" 1759 #else 1760 #define AS_NIAGARA3_FLAG "b" 1761 #endif 1762 1763 #ifdef HAVE_AS_SPARC4 1764 #define AS_NIAGARA4_FLAG "-xarch=sparc4" 1765 #else 1766 #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG 1767 #endif 1768 1769 #ifdef HAVE_AS_LEON 1770 #define AS_LEON_FLAG "-Aleon" 1771 #define AS_LEONV7_FLAG "-Aleon" 1772 #else 1773 #define AS_LEON_FLAG "-Av8" 1774 #define AS_LEONV7_FLAG "-Av7" 1775 #endif 1776 1777 /* We use gcc _mcount for profiling. */ 1778 #define NO_PROFILE_COUNTERS 0 1779 1780 /* Debug support */ 1781 #define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */ 1782 #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS 1783 1784 #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS) 1785 1786 /* By default, use the weakest memory model for the cpu. */ 1787 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL 1788 #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT 1789 #endif 1790