1;; ARM VFP11 pipeline description
2;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
3;; Written by CodeSourcery.
4;;
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21(define_automaton "vfp11")
22
23;; There are 3 pipelines in the VFP11 unit.
24;;
25;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
26;;   fourth stage for simple operations.
27;;
28;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
29;;   These insns also uses first execute stage of FMAC pipeline.
30;;
31;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
32;;   second memory stage for loads.
33
34;; We do not model Write-After-Read hazards.
35;; We do not do write scheduling with the arm core, so it is only necessary
36;; to model the first stage of each pipeline
37;; ??? Need to model LS pipeline properly for load/store multiple?
38;; We do not model fmstat properly.  This could be done by modeling pipelines
39;; properly and defining an absence set between a dummy fmstat unit and all
40;; other vfp units.
41
42(define_cpu_unit "fmac" "vfp11")
43
44(define_cpu_unit "ds" "vfp11")
45
46(define_cpu_unit "vfp_ls" "vfp11")
47
48(define_cpu_unit "fmstat" "vfp11")
49
50(exclusion_set "fmac,ds" "fmstat")
51
52(define_insn_reservation "vfp_ffarith" 4
53 (and (eq_attr "generic_vfp" "yes")
54      (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
55 "fmac")
56
57(define_insn_reservation "vfp_farith" 8
58 (and (eq_attr "generic_vfp" "yes")
59      (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,f_cvtf2i,f_cvti2f,\
60                       fmuls,fmacs,ffmas"))
61 "fmac")
62
63(define_insn_reservation "vfp_fmul" 9
64 (and (eq_attr "generic_vfp" "yes")
65      (eq_attr "type" "fmuld,fmacd,ffmad"))
66 "fmac*2")
67
68(define_insn_reservation "vfp_fdivs" 19
69 (and (eq_attr "generic_vfp" "yes")
70      (eq_attr "type" "fdivs, fsqrts"))
71 "ds*15")
72
73(define_insn_reservation "vfp_fdivd" 33
74 (and (eq_attr "generic_vfp" "yes")
75      (eq_attr "type" "fdivd, fsqrtd"))
76 "fmac+ds*29")
77
78;; Moves to/from arm regs also use the load/store pipeline.
79(define_insn_reservation "vfp_fload" 4
80 (and (eq_attr "generic_vfp" "yes")
81      (eq_attr "type" "f_loads,f_loadd,f_mcr,f_mcrr"))
82 "vfp_ls")
83
84(define_insn_reservation "vfp_fstore" 4
85 (and (eq_attr "generic_vfp" "yes")
86      (eq_attr "type" "f_stores,f_stored,f_mrc,f_mrrc"))
87 "vfp_ls")
88
89(define_insn_reservation "vfp_to_cpsr" 4
90 (and (eq_attr "generic_vfp" "yes")
91      (eq_attr "type" "f_flag"))
92 "fmstat,vfp_ls*3")
93
94