1 /*
2 * Copyright (C) 2007-2018 Free Software Foundation, Inc.
3 *
4 * This file is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 3, or (at your option) any
7 * later version.
8 *
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * Under Section 7 of GPL version 3, you are granted additional
15 * permissions described in the GCC Runtime Library Exception, version
16 * 3.1, as published by the Free Software Foundation.
17 *
18 * You should have received a copy of the GNU General Public License and
19 * a copy of the GCC Runtime Library Exception along with this program;
20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
21 * <http://www.gnu.org/licenses/>.
22 */
23
24 /* %ecx */
25 #define bit_SSE3 (1 << 0)
26 #define bit_PCLMUL (1 << 1)
27 #define bit_LZCNT (1 << 5)
28 #define bit_SSSE3 (1 << 9)
29 #define bit_FMA (1 << 12)
30 #define bit_CMPXCHG16B (1 << 13)
31 #define bit_SSE4_1 (1 << 19)
32 #define bit_SSE4_2 (1 << 20)
33 #define bit_MOVBE (1 << 22)
34 #define bit_POPCNT (1 << 23)
35 #define bit_AES (1 << 25)
36 #define bit_XSAVE (1 << 26)
37 #define bit_OSXSAVE (1 << 27)
38 #define bit_AVX (1 << 28)
39 #define bit_F16C (1 << 29)
40 #define bit_RDRND (1 << 30)
41
42 /* %edx */
43 #define bit_CMPXCHG8B (1 << 8)
44 #define bit_CMOV (1 << 15)
45 #define bit_MMX (1 << 23)
46 #define bit_FXSAVE (1 << 24)
47 #define bit_SSE (1 << 25)
48 #define bit_SSE2 (1 << 26)
49
50 /* Extended Features (%eax == 0x80000001) */
51 /* %ecx */
52 #define bit_LAHF_LM (1 << 0)
53 #define bit_ABM (1 << 5)
54 #define bit_SSE4a (1 << 6)
55 #define bit_PRFCHW (1 << 8)
56 #define bit_XOP (1 << 11)
57 #define bit_LWP (1 << 15)
58 #define bit_FMA4 (1 << 16)
59 #define bit_TBM (1 << 21)
60 #define bit_MWAITX (1 << 29)
61
62 /* %edx */
63 #define bit_MMXEXT (1 << 22)
64 #define bit_LM (1 << 29)
65 #define bit_3DNOWP (1 << 30)
66 #define bit_3DNOW (1u << 31)
67
68 /* %ebx */
69 #define bit_CLZERO (1 << 0)
70 #define bit_WBNOINVD (1 << 9)
71
72 /* Extended Features (%eax == 7) */
73 /* %ebx */
74 #define bit_FSGSBASE (1 << 0)
75 #define bit_SGX (1 << 2)
76 #define bit_BMI (1 << 3)
77 #define bit_HLE (1 << 4)
78 #define bit_AVX2 (1 << 5)
79 #define bit_BMI2 (1 << 8)
80 #define bit_RTM (1 << 11)
81 #define bit_MPX (1 << 14)
82 #define bit_AVX512F (1 << 16)
83 #define bit_AVX512DQ (1 << 17)
84 #define bit_RDSEED (1 << 18)
85 #define bit_ADX (1 << 19)
86 #define bit_AVX512IFMA (1 << 21)
87 #define bit_CLFLUSHOPT (1 << 23)
88 #define bit_CLWB (1 << 24)
89 #define bit_AVX512PF (1 << 26)
90 #define bit_AVX512ER (1 << 27)
91 #define bit_AVX512CD (1 << 28)
92 #define bit_SHA (1 << 29)
93 #define bit_AVX512BW (1 << 30)
94 #define bit_AVX512VL (1u << 31)
95
96 /* %ecx */
97 #define bit_PREFETCHWT1 (1 << 0)
98 #define bit_AVX512VBMI (1 << 1)
99 #define bit_PKU (1 << 3)
100 #define bit_OSPKE (1 << 4)
101 #define bit_AVX512VBMI2 (1 << 6)
102 #define bit_SHSTK (1 << 7)
103 #define bit_GFNI (1 << 8)
104 #define bit_VAES (1 << 9)
105 #define bit_AVX512VNNI (1 << 11)
106 #define bit_VPCLMULQDQ (1 << 10)
107 #define bit_AVX512BITALG (1 << 12)
108 #define bit_AVX512VPOPCNTDQ (1 << 14)
109 #define bit_RDPID (1 << 22)
110 #define bit_MOVDIRI (1 << 27)
111 #define bit_MOVDIR64B (1 << 28)
112
113 /* %edx */
114 #define bit_AVX5124VNNIW (1 << 2)
115 #define bit_AVX5124FMAPS (1 << 3)
116 #define bit_IBT (1 << 20)
117 #define bit_PCONFIG (1 << 18)
118 /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
119 #define bit_BNDREGS (1 << 3)
120 #define bit_BNDCSR (1 << 4)
121
122 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
123 #define bit_XSAVEOPT (1 << 0)
124 #define bit_XSAVEC (1 << 1)
125 #define bit_XSAVES (1 << 3)
126
127 /* Signatures for different CPU implementations as returned in uses
128 of cpuid with level 0. */
129 #define signature_AMD_ebx 0x68747541
130 #define signature_AMD_ecx 0x444d4163
131 #define signature_AMD_edx 0x69746e65
132
133 #define signature_CENTAUR_ebx 0x746e6543
134 #define signature_CENTAUR_ecx 0x736c7561
135 #define signature_CENTAUR_edx 0x48727561
136
137 #define signature_CYRIX_ebx 0x69727943
138 #define signature_CYRIX_ecx 0x64616574
139 #define signature_CYRIX_edx 0x736e4978
140
141 #define signature_INTEL_ebx 0x756e6547
142 #define signature_INTEL_ecx 0x6c65746e
143 #define signature_INTEL_edx 0x49656e69
144
145 #define signature_TM1_ebx 0x6e617254
146 #define signature_TM1_ecx 0x55504361
147 #define signature_TM1_edx 0x74656d73
148
149 #define signature_TM2_ebx 0x756e6547
150 #define signature_TM2_ecx 0x3638784d
151 #define signature_TM2_edx 0x54656e69
152
153 #define signature_NSC_ebx 0x646f6547
154 #define signature_NSC_ecx 0x43534e20
155 #define signature_NSC_edx 0x79622065
156
157 #define signature_NEXGEN_ebx 0x4778654e
158 #define signature_NEXGEN_ecx 0x6e657669
159 #define signature_NEXGEN_edx 0x72446e65
160
161 #define signature_RISE_ebx 0x65736952
162 #define signature_RISE_ecx 0x65736952
163 #define signature_RISE_edx 0x65736952
164
165 #define signature_SIS_ebx 0x20536953
166 #define signature_SIS_ecx 0x20536953
167 #define signature_SIS_edx 0x20536953
168
169 #define signature_UMC_ebx 0x20434d55
170 #define signature_UMC_ecx 0x20434d55
171 #define signature_UMC_edx 0x20434d55
172
173 #define signature_VIA_ebx 0x20414956
174 #define signature_VIA_ecx 0x20414956
175 #define signature_VIA_edx 0x20414956
176
177 #define signature_VORTEX_ebx 0x74726f56
178 #define signature_VORTEX_ecx 0x436f5320
179 #define signature_VORTEX_edx 0x36387865
180
181 #ifndef __x86_64__
182 /* At least one cpu (Winchip 2) does not set %ebx and %ecx
183 for cpuid leaf 1. Forcibly zero the two registers before
184 calling cpuid as a precaution. */
185 #define __cpuid(level, a, b, c, d) \
186 do { \
187 if (__builtin_constant_p (level) && (level) != 1) \
188 __asm__ __volatile__ ("cpuid\n\t" \
189 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
190 : "0" (level)); \
191 else \
192 __asm__ __volatile__ ("cpuid\n\t" \
193 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
194 : "0" (level), "1" (0), "2" (0)); \
195 } while (0)
196 #else
197 #define __cpuid(level, a, b, c, d) \
198 __asm__ __volatile__ ("cpuid\n\t" \
199 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
200 : "0" (level))
201 #endif
202
203 #define __cpuid_count(level, count, a, b, c, d) \
204 __asm__ __volatile__ ("cpuid\n\t" \
205 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
206 : "0" (level), "2" (count))
207
208
209 /* Return highest supported input value for cpuid instruction. ext can
210 be either 0x0 or 0x80000000 to return highest supported value for
211 basic or extended cpuid information. Function returns 0 if cpuid
212 is not supported or whatever cpuid returns in eax register. If sig
213 pointer is non-null, then first four bytes of the signature
214 (as found in ebx register) are returned in location pointed by sig. */
215
216 static __inline unsigned int
__get_cpuid_max(unsigned int __ext,unsigned int * __sig)217 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
218 {
219 unsigned int __eax, __ebx, __ecx, __edx;
220
221 #ifndef __x86_64__
222 /* See if we can use cpuid. On AMD64 we always can. */
223 #if __GNUC__ >= 3
224 __asm__ ("pushf{l|d}\n\t"
225 "pushf{l|d}\n\t"
226 "pop{l}\t%0\n\t"
227 "mov{l}\t{%0, %1|%1, %0}\n\t"
228 "xor{l}\t{%2, %0|%0, %2}\n\t"
229 "push{l}\t%0\n\t"
230 "popf{l|d}\n\t"
231 "pushf{l|d}\n\t"
232 "pop{l}\t%0\n\t"
233 "popf{l|d}\n\t"
234 : "=&r" (__eax), "=&r" (__ebx)
235 : "i" (0x00200000));
236 #else
237 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
238 nor alternatives in i386 code. */
239 __asm__ ("pushfl\n\t"
240 "pushfl\n\t"
241 "popl\t%0\n\t"
242 "movl\t%0, %1\n\t"
243 "xorl\t%2, %0\n\t"
244 "pushl\t%0\n\t"
245 "popfl\n\t"
246 "pushfl\n\t"
247 "popl\t%0\n\t"
248 "popfl\n\t"
249 : "=&r" (__eax), "=&r" (__ebx)
250 : "i" (0x00200000));
251 #endif
252
253 if (!((__eax ^ __ebx) & 0x00200000))
254 return 0;
255 #endif
256
257 /* Host supports cpuid. Return highest supported cpuid input value. */
258 __cpuid (__ext, __eax, __ebx, __ecx, __edx);
259
260 if (__sig)
261 *__sig = __ebx;
262
263 return __eax;
264 }
265
266 /* Return cpuid data for requested cpuid leaf, as found in returned
267 eax, ebx, ecx and edx registers. The function checks if cpuid is
268 supported and returns 1 for valid cpuid information or 0 for
269 unsupported cpuid leaf. All pointers are required to be non-null. */
270
271 static __inline int
__get_cpuid(unsigned int __leaf,unsigned int * __eax,unsigned int * __ebx,unsigned int * __ecx,unsigned int * __edx)272 __get_cpuid (unsigned int __leaf,
273 unsigned int *__eax, unsigned int *__ebx,
274 unsigned int *__ecx, unsigned int *__edx)
275 {
276 unsigned int __ext = __leaf & 0x80000000;
277 unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
278
279 if (__maxlevel == 0 || __maxlevel < __leaf)
280 return 0;
281
282 __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
283 return 1;
284 }
285
286 /* Same as above, but sub-leaf can be specified. */
287
288 static __inline int
__get_cpuid_count(unsigned int __leaf,unsigned int __subleaf,unsigned int * __eax,unsigned int * __ebx,unsigned int * __ecx,unsigned int * __edx)289 __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
290 unsigned int *__eax, unsigned int *__ebx,
291 unsigned int *__ecx, unsigned int *__edx)
292 {
293 unsigned int __ext = __leaf & 0x80000000;
294 unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
295
296 if (__maxlevel == 0 || __maxlevel < __leaf)
297 return 0;
298
299 __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
300 return 1;
301 }
302