1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #define IN_TARGET_CODE 1
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "backend.h"
27 #include "target.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "stringpool.h"
31 #include "attribs.h"
32 #include "cfghooks.h"
33 #include "df.h"
34 #include "memmodel.h"
35 #include "tm_p.h"
36 #include "optabs.h"
37 #include "regs.h"
38 #include "emit-rtl.h"
39 #include "recog.h"
40 #include "cgraph.h"
41 #include "diagnostic-core.h"
42 #include "conditions.h"
43 #include "insn-attr.h"
44 #include "alias.h"
45 #include "varasm.h"
46 #include "stor-layout.h"
47 #include "calls.h"
48 #include "explow.h"
49 #include "expr.h"
50 #include "reload.h"
51 #include "output.h"
52 #include "tm-constrs.h"
53 #include "builtins.h"
54
55 /* This file should be included last. */
56 #include "target-def.h"
57
58 /* Usable when we have an amount to add or subtract, and want the
59 optimal size of the insn. */
60 #define ADDITIVE_SIZE_MODIFIER(size) \
61 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
62
63 #define LOSE_AND_RETURN(msgid, x) \
64 do \
65 { \
66 cris_operand_lossage (msgid, x); \
67 return; \
68 } while (0)
69
70 enum cris_retinsn_type
71 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP };
72
73 /* Per-function machine data. */
74 struct GTY(()) machine_function
75 {
76 int needs_return_address_on_stack;
77
78 /* This is the number of registers we save in the prologue due to
79 stdarg. */
80 int stdarg_regs;
81
82 enum cris_retinsn_type return_type;
83 };
84
85 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
86 pattern. */
87 static char cris_output_insn_is_bound = 0;
88
89 /* In code for output macros, this is how we know whether e.g. constant
90 goes in code or in a static initializer. */
91 static int in_code = 0;
92
93 /* Fix for reg_overlap_mentioned_p. */
94 static int cris_reg_overlap_mentioned_p (rtx, rtx);
95
96 static machine_mode cris_promote_function_mode (const_tree, machine_mode,
97 int *, const_tree, int);
98
99 static unsigned int cris_atomic_align_for_mode (machine_mode);
100
101 static void cris_print_base (rtx, FILE *);
102
103 static void cris_print_index (rtx, FILE *);
104
105 static void cris_output_addr_const (FILE *, rtx);
106
107 static struct machine_function * cris_init_machine_status (void);
108
109 static rtx cris_struct_value_rtx (tree, int);
110
111 static void cris_setup_incoming_varargs (cumulative_args_t, machine_mode,
112 tree type, int *, int);
113
114 static int cris_initial_frame_pointer_offset (void);
115
116 static void cris_operand_lossage (const char *, rtx);
117
118 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
119
120 static void cris_print_operand (FILE *, rtx, int);
121
122 static void cris_print_operand_address (FILE *, machine_mode, rtx);
123
124 static bool cris_print_operand_punct_valid_p (unsigned char code);
125
126 static bool cris_output_addr_const_extra (FILE *, rtx);
127
128 static void cris_conditional_register_usage (void);
129
130 static void cris_asm_output_mi_thunk
131 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
132
133 static void cris_file_start (void);
134 static void cris_init_libfuncs (void);
135
136 static reg_class_t cris_preferred_reload_class (rtx, reg_class_t);
137
138 static int cris_register_move_cost (machine_mode, reg_class_t, reg_class_t);
139 static int cris_memory_move_cost (machine_mode, reg_class_t, bool);
140 static bool cris_rtx_costs (rtx, machine_mode, int, int, int *, bool);
141 static int cris_address_cost (rtx, machine_mode, addr_space_t, bool);
142 static bool cris_pass_by_reference (cumulative_args_t, machine_mode,
143 const_tree, bool);
144 static int cris_arg_partial_bytes (cumulative_args_t, machine_mode,
145 tree, bool);
146 static rtx cris_function_arg (cumulative_args_t, machine_mode,
147 const_tree, bool);
148 static rtx cris_function_incoming_arg (cumulative_args_t,
149 machine_mode, const_tree, bool);
150 static void cris_function_arg_advance (cumulative_args_t, machine_mode,
151 const_tree, bool);
152 static rtx_insn *cris_md_asm_adjust (vec<rtx> &, vec<rtx> &,
153 vec<const char *> &,
154 vec<rtx> &, HARD_REG_SET &);
155 static bool cris_cannot_force_const_mem (machine_mode, rtx);
156
157 static void cris_option_override (void);
158
159 static bool cris_frame_pointer_required (void);
160
161 static void cris_asm_trampoline_template (FILE *);
162 static void cris_trampoline_init (rtx, tree, rtx);
163
164 static rtx cris_function_value(const_tree, const_tree, bool);
165 static rtx cris_libcall_value (machine_mode, const_rtx);
166 static bool cris_function_value_regno_p (const unsigned int);
167 static void cris_file_end (void);
168 static unsigned int cris_hard_regno_nregs (unsigned int, machine_mode);
169 static bool cris_hard_regno_mode_ok (unsigned int, machine_mode);
170 static HOST_WIDE_INT cris_static_rtx_alignment (machine_mode);
171 static HOST_WIDE_INT cris_constant_alignment (const_tree, HOST_WIDE_INT);
172
173 /* This is the parsed result of the "-max-stack-stackframe=" option. If
174 it (still) is zero, then there was no such option given. */
175 int cris_max_stackframe = 0;
176
177 /* This is the parsed result of the "-march=" option, if given. */
178 int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
179
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
184 #undef TARGET_ASM_ALIGNED_DI_OP
185 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
186
187 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
188 available in ELF. These "normal" pseudos do not have any alignment
189 constraints or side-effects. */
190 #undef TARGET_ASM_UNALIGNED_HI_OP
191 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
192
193 #undef TARGET_ASM_UNALIGNED_SI_OP
194 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
195
196 #undef TARGET_ASM_UNALIGNED_DI_OP
197 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
198
199 #undef TARGET_PRINT_OPERAND
200 #define TARGET_PRINT_OPERAND cris_print_operand
201 #undef TARGET_PRINT_OPERAND_ADDRESS
202 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
203 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
204 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
205 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
206 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
207
208 #undef TARGET_CONDITIONAL_REGISTER_USAGE
209 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
210
211 #undef TARGET_ASM_OUTPUT_MI_THUNK
212 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
213 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
214 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
215
216 #undef TARGET_ASM_FILE_START
217 #define TARGET_ASM_FILE_START cris_file_start
218 #undef TARGET_ASM_FILE_END
219 #define TARGET_ASM_FILE_END cris_file_end
220
221 #undef TARGET_INIT_LIBFUNCS
222 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
223
224 #undef TARGET_LRA_P
225 #define TARGET_LRA_P hook_bool_void_false
226
227 #undef TARGET_LEGITIMATE_ADDRESS_P
228 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
229
230 #undef TARGET_LEGITIMATE_CONSTANT_P
231 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p
232
233 #undef TARGET_PREFERRED_RELOAD_CLASS
234 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
235
236 #undef TARGET_REGISTER_MOVE_COST
237 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
238 #undef TARGET_MEMORY_MOVE_COST
239 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
240 #undef TARGET_RTX_COSTS
241 #define TARGET_RTX_COSTS cris_rtx_costs
242 #undef TARGET_ADDRESS_COST
243 #define TARGET_ADDRESS_COST cris_address_cost
244
245 #undef TARGET_PROMOTE_FUNCTION_MODE
246 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
247
248 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
249 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
250
251 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
252 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
253
254 #undef TARGET_STRUCT_VALUE_RTX
255 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
256 #undef TARGET_SETUP_INCOMING_VARARGS
257 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
258 #undef TARGET_PASS_BY_REFERENCE
259 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
260 #undef TARGET_ARG_PARTIAL_BYTES
261 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
262 #undef TARGET_FUNCTION_ARG
263 #define TARGET_FUNCTION_ARG cris_function_arg
264 #undef TARGET_FUNCTION_INCOMING_ARG
265 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
266 #undef TARGET_FUNCTION_ARG_ADVANCE
267 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
268 #undef TARGET_MD_ASM_ADJUST
269 #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust
270
271 #undef TARGET_CANNOT_FORCE_CONST_MEM
272 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem
273
274 #undef TARGET_FRAME_POINTER_REQUIRED
275 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
276
277 #undef TARGET_OPTION_OVERRIDE
278 #define TARGET_OPTION_OVERRIDE cris_option_override
279
280 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
281 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
282 #undef TARGET_TRAMPOLINE_INIT
283 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
284
285 #undef TARGET_FUNCTION_VALUE
286 #define TARGET_FUNCTION_VALUE cris_function_value
287 #undef TARGET_LIBCALL_VALUE
288 #define TARGET_LIBCALL_VALUE cris_libcall_value
289 #undef TARGET_FUNCTION_VALUE_REGNO_P
290 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
291
292 #undef TARGET_HARD_REGNO_NREGS
293 #define TARGET_HARD_REGNO_NREGS cris_hard_regno_nregs
294 #undef TARGET_HARD_REGNO_MODE_OK
295 #define TARGET_HARD_REGNO_MODE_OK cris_hard_regno_mode_ok
296
297 #undef TARGET_STATIC_RTX_ALIGNMENT
298 #define TARGET_STATIC_RTX_ALIGNMENT cris_static_rtx_alignment
299 #undef TARGET_CONSTANT_ALIGNMENT
300 #define TARGET_CONSTANT_ALIGNMENT cris_constant_alignment
301
302 struct gcc_target targetm = TARGET_INITIALIZER;
303
304 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
305
306 bool
cris_movem_load_rest_p(rtx op,int offs)307 cris_movem_load_rest_p (rtx op, int offs)
308 {
309 unsigned int reg_count = XVECLEN (op, 0) - offs;
310 rtx src_addr;
311 int i;
312 rtx elt;
313 int setno;
314 int regno_dir = 1;
315 unsigned int regno = 0;
316
317 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
318 other than (MEM reg). */
319 if (reg_count <= 1
320 || GET_CODE (XVECEXP (op, 0, offs)) != SET
321 || !REG_P (SET_DEST (XVECEXP (op, 0, offs)))
322 || !MEM_P (SET_SRC (XVECEXP (op, 0, offs))))
323 return false;
324
325 /* Check a possible post-inc indicator. */
326 if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS)
327 {
328 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0);
329 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1);
330
331 reg_count--;
332
333 if (reg_count == 1
334 || !REG_P (reg)
335 || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1)))
336 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1)))
337 || !CONST_INT_P (inc)
338 || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4)
339 return false;
340 i = offs + 2;
341 }
342 else
343 i = offs + 1;
344
345 if (!TARGET_V32)
346 {
347 regno_dir = -1;
348 regno = reg_count - 1;
349 }
350
351 elt = XVECEXP (op, 0, offs);
352 src_addr = XEXP (SET_SRC (elt), 0);
353
354 if (GET_CODE (elt) != SET
355 || !REG_P (SET_DEST (elt))
356 || GET_MODE (SET_DEST (elt)) != SImode
357 || REGNO (SET_DEST (elt)) != regno
358 || !MEM_P (SET_SRC (elt))
359 || GET_MODE (SET_SRC (elt)) != SImode
360 || !memory_address_p (SImode, src_addr))
361 return false;
362
363 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
364 {
365 rtx elt = XVECEXP (op, 0, i);
366 regno += regno_dir;
367
368 if (GET_CODE (elt) != SET
369 || !REG_P (SET_DEST (elt))
370 || GET_MODE (SET_DEST (elt)) != SImode
371 || REGNO (SET_DEST (elt)) != regno
372 || !MEM_P (SET_SRC (elt))
373 || GET_MODE (SET_SRC (elt)) != SImode
374 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
375 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
376 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
377 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4)
378 return false;
379 }
380
381 return true;
382 }
383
384 /* Worker function for predicate for the parallel contents in a movem
385 to-memory. */
386
387 bool
cris_store_multiple_op_p(rtx op)388 cris_store_multiple_op_p (rtx op)
389 {
390 int reg_count = XVECLEN (op, 0);
391 rtx dest;
392 rtx dest_addr;
393 rtx dest_base;
394 int i;
395 rtx elt;
396 int setno;
397 int regno_dir = 1;
398 int regno = 0;
399 int offset = 0;
400
401 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
402 other than (MEM reg) and (MEM (PLUS reg const)). */
403 if (reg_count <= 1)
404 return false;
405
406 elt = XVECEXP (op, 0, 0);
407
408 if (GET_CODE (elt) != SET)
409 return false;
410
411 dest = SET_DEST (elt);
412
413 if (!REG_P (SET_SRC (elt)) || !MEM_P (dest))
414 return false;
415
416 dest_addr = XEXP (dest, 0);
417
418 /* Check a possible post-inc indicator. */
419 if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS)
420 {
421 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0);
422 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1);
423
424 reg_count--;
425
426 if (reg_count == 1
427 || !REG_P (reg)
428 || !REG_P (SET_DEST (XVECEXP (op, 0, 1)))
429 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1)))
430 || !CONST_INT_P (inc)
431 /* Support increment by number of registers, and by the offset
432 of the destination, if it has the form (MEM (PLUS reg
433 offset)). */
434 || !((REG_P (dest_addr)
435 && REGNO (dest_addr) == REGNO (reg)
436 && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4)
437 || (GET_CODE (dest_addr) == PLUS
438 && REG_P (XEXP (dest_addr, 0))
439 && REGNO (XEXP (dest_addr, 0)) == REGNO (reg)
440 && CONST_INT_P (XEXP (dest_addr, 1))
441 && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc))))
442 return false;
443
444 i = 2;
445 }
446 else
447 i = 1;
448
449 if (!TARGET_V32)
450 {
451 regno_dir = -1;
452 regno = reg_count - 1;
453 }
454
455 if (GET_CODE (elt) != SET
456 || !REG_P (SET_SRC (elt))
457 || GET_MODE (SET_SRC (elt)) != SImode
458 || REGNO (SET_SRC (elt)) != (unsigned int) regno
459 || !MEM_P (SET_DEST (elt))
460 || GET_MODE (SET_DEST (elt)) != SImode)
461 return false;
462
463 if (REG_P (dest_addr))
464 {
465 dest_base = dest_addr;
466 offset = 0;
467 }
468 else if (GET_CODE (dest_addr) == PLUS
469 && REG_P (XEXP (dest_addr, 0))
470 && CONST_INT_P (XEXP (dest_addr, 1)))
471 {
472 dest_base = XEXP (dest_addr, 0);
473 offset = INTVAL (XEXP (dest_addr, 1));
474 }
475 else
476 return false;
477
478 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
479 {
480 rtx elt = XVECEXP (op, 0, i);
481 regno += regno_dir;
482
483 if (GET_CODE (elt) != SET
484 || !REG_P (SET_SRC (elt))
485 || GET_MODE (SET_SRC (elt)) != SImode
486 || REGNO (SET_SRC (elt)) != (unsigned int) regno
487 || !MEM_P (SET_DEST (elt))
488 || GET_MODE (SET_DEST (elt)) != SImode
489 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
490 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base)
491 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
492 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset)
493 return false;
494 }
495
496 return true;
497 }
498
499 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
500
501 static void
cris_conditional_register_usage(void)502 cris_conditional_register_usage (void)
503 {
504 /* FIXME: This isn't nice. We should be able to use that register for
505 something else if the PIC table isn't needed. */
506 if (flag_pic)
507 fixed_regs[PIC_OFFSET_TABLE_REGNUM]
508 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
509
510 /* Allow use of ACR (PC in pre-V32) and tweak order. */
511 if (TARGET_V32)
512 {
513 static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32;
514 unsigned int i;
515
516 fixed_regs[CRIS_ACR_REGNUM] = 0;
517
518 for (i = 0;
519 i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]);
520 i++)
521 reg_alloc_order[i] = reg_alloc_order_v32[i];
522 }
523
524 if (TARGET_HAS_MUL_INSNS)
525 fixed_regs[CRIS_MOF_REGNUM] = 0;
526
527 /* On early versions, we must use the 16-bit condition-code register,
528 which has another name. */
529 if (cris_cpu_version < 8)
530 reg_names[CRIS_CC0_REGNUM] = "ccr";
531 }
532
533 /* Return crtl->uses_pic_offset_table. For use in cris.md,
534 since some generated files do not include function.h. */
535
536 int
cris_cfun_uses_pic_table(void)537 cris_cfun_uses_pic_table (void)
538 {
539 return crtl->uses_pic_offset_table;
540 }
541
542 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM.
543 We can't put PIC addresses in the constant pool, not even the ones that
544 can be reached as pc-relative as we can't tell when or how to do that. */
545
546 static bool
cris_cannot_force_const_mem(machine_mode mode ATTRIBUTE_UNUSED,rtx x)547 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
548 {
549 enum cris_symbol_type t = cris_symbol_type_of (x);
550
551 return
552 t == cris_unspec
553 || t == cris_got_symbol
554 || t == cris_rel_symbol;
555 }
556
557 /* Given an rtx, return the text string corresponding to the CODE of X.
558 Intended for use in the assembly language output section of a
559 define_insn. */
560
561 const char *
cris_op_str(rtx x)562 cris_op_str (rtx x)
563 {
564 cris_output_insn_is_bound = 0;
565 switch (GET_CODE (x))
566 {
567 case PLUS:
568 return "add";
569
570 case MINUS:
571 return "sub";
572
573 case MULT:
574 /* This function is for retrieving a part of an instruction name for
575 an operator, for immediate output. If that ever happens for
576 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
577 we notice. */
578 internal_error ("MULT case in cris_op_str");
579 break;
580
581 case DIV:
582 return "div";
583
584 case AND:
585 return "and";
586
587 case IOR:
588 return "or";
589
590 case XOR:
591 return "xor";
592
593 case NOT:
594 return "not";
595
596 case ASHIFT:
597 return "lsl";
598
599 case LSHIFTRT:
600 return "lsr";
601
602 case ASHIFTRT:
603 return "asr";
604
605 case UMIN:
606 /* Used to control the sign/zero-extend character for the 'E' modifier.
607 BOUND has none. */
608 cris_output_insn_is_bound = 1;
609 return "bound";
610
611 default:
612 return "Unknown operator";
613 }
614 }
615
616 /* Emit an error message when we're in an asm, and a fatal error for
617 "normal" insns. Formatted output isn't easily implemented, since we
618 use output_operand_lossage to output the actual message and handle the
619 categorization of the error. */
620
621 static void
cris_operand_lossage(const char * msgid,rtx op)622 cris_operand_lossage (const char *msgid, rtx op)
623 {
624 debug_rtx (op);
625 output_operand_lossage ("%s", msgid);
626 }
627
628 /* Print an index part of an address to file. */
629
630 static void
cris_print_index(rtx index,FILE * file)631 cris_print_index (rtx index, FILE *file)
632 {
633 /* Make the index "additive" unless we'll output a negative number, in
634 which case the sign character is free (as in free beer). */
635 if (!CONST_INT_P (index) || INTVAL (index) >= 0)
636 putc ('+', file);
637
638 if (REG_P (index))
639 fprintf (file, "$%s.b", reg_names[REGNO (index)]);
640 else if (CRIS_CONSTANT_P (index))
641 cris_output_addr_const (file, index);
642 else if (GET_CODE (index) == MULT)
643 {
644 fprintf (file, "$%s.",
645 reg_names[REGNO (XEXP (index, 0))]);
646
647 putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file);
648 }
649 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0)))
650 {
651 rtx inner = XEXP (index, 0);
652 rtx inner_inner = XEXP (inner, 0);
653
654 if (GET_CODE (inner_inner) == POST_INC)
655 {
656 fprintf (file, "[$%s+].",
657 reg_names[REGNO (XEXP (inner_inner, 0))]);
658 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
659 }
660 else
661 {
662 fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]);
663
664 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
665 }
666 }
667 else if (MEM_P (index))
668 {
669 rtx inner = XEXP (index, 0);
670 if (GET_CODE (inner) == POST_INC)
671 fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]);
672 else
673 fprintf (file, "[$%s].d", reg_names[REGNO (inner)]);
674 }
675 else
676 cris_operand_lossage ("unexpected index-type in cris_print_index",
677 index);
678 }
679
680 /* Print a base rtx of an address to file. */
681
682 static void
cris_print_base(rtx base,FILE * file)683 cris_print_base (rtx base, FILE *file)
684 {
685 if (REG_P (base))
686 fprintf (file, "$%s", reg_names[REGNO (base)]);
687 else if (GET_CODE (base) == POST_INC)
688 {
689 gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM);
690 fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]);
691 }
692 else
693 cris_operand_lossage ("unexpected base-type in cris_print_base",
694 base);
695 }
696
697 /* Usable as a guard in expressions. */
698
699 int
cris_fatal(char * arg)700 cris_fatal (char *arg)
701 {
702 internal_error (arg);
703
704 /* We'll never get here; this is just to appease compilers. */
705 return 0;
706 }
707
708 /* Return nonzero if REGNO is an ordinary register that *needs* to be
709 saved together with other registers, possibly by a MOVEM instruction,
710 or is saved for target-independent reasons. There may be
711 target-dependent reasons to save the register anyway; this is just a
712 wrapper for a complicated conditional. */
713
714 static int
cris_reg_saved_in_regsave_area(unsigned int regno,bool got_really_used)715 cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used)
716 {
717 return
718 (((df_regs_ever_live_p (regno)
719 && !call_used_regs[regno])
720 || (regno == PIC_OFFSET_TABLE_REGNUM
721 && (got_really_used
722 /* It is saved anyway, if there would be a gap. */
723 || (flag_pic
724 && df_regs_ever_live_p (regno + 1)
725 && !call_used_regs[regno + 1]))))
726 && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed)
727 && regno != CRIS_SRP_REGNUM)
728 || (crtl->calls_eh_return
729 && (regno == EH_RETURN_DATA_REGNO (0)
730 || regno == EH_RETURN_DATA_REGNO (1)
731 || regno == EH_RETURN_DATA_REGNO (2)
732 || regno == EH_RETURN_DATA_REGNO (3)));
733 }
734
735 /* The PRINT_OPERAND worker. */
736
737 static void
cris_print_operand(FILE * file,rtx x,int code)738 cris_print_operand (FILE *file, rtx x, int code)
739 {
740 rtx operand = x;
741
742 /* Size-strings corresponding to MULT expressions. */
743 static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
744
745 /* New code entries should just be added to the switch below. If
746 handling is finished, just return. If handling was just a
747 modification of the operand, the modified operand should be put in
748 "operand", and then do a break to let default handling
749 (zero-modifier) output the operand. */
750
751 switch (code)
752 {
753 case 'b':
754 /* Print the unsigned supplied integer as if it were signed
755 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
756 if (!satisfies_constraint_O (x))
757 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x);
758 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
759 INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535));
760 return;
761
762 case 'x':
763 /* Print assembler code for operator. */
764 fprintf (file, "%s", cris_op_str (operand));
765 return;
766
767 case 'o':
768 {
769 /* A movem modifier working on a parallel; output the register
770 name. */
771 int regno;
772
773 if (GET_CODE (x) != PARALLEL)
774 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x);
775
776 /* The second item can be (set reg (plus reg const)) to denote a
777 postincrement. */
778 regno
779 = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS
780 ? XVECLEN (x, 0) - 2
781 : XVECLEN (x, 0) - 1);
782
783 fprintf (file, "$%s", reg_names [regno]);
784 }
785 return;
786
787 case 'O':
788 {
789 /* A similar movem modifier; output the memory operand. */
790 rtx addr;
791
792 if (GET_CODE (x) != PARALLEL)
793 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x);
794
795 /* The lowest mem operand is in the first item, but perhaps it
796 needs to be output as postincremented. */
797 addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0)))
798 ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0)
799 : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0);
800
801 /* The second item can be a (set reg (plus reg const)) to denote
802 a modification. */
803 if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS)
804 {
805 /* It's a post-increment, if the address is a naked (reg). */
806 if (REG_P (addr))
807 addr = gen_rtx_POST_INC (SImode, addr);
808 else
809 {
810 /* Otherwise, it's a side-effect; RN=RN+M. */
811 fprintf (file, "[$%s=$%s%s%d]",
812 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))],
813 reg_names [REGNO (XEXP (addr, 0))],
814 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+",
815 (int) INTVAL (XEXP (addr, 1)));
816 return;
817 }
818 }
819 output_address (VOIDmode, addr);
820 }
821 return;
822
823 case 'p':
824 /* Adjust a power of two to its log2. */
825 if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 )
826 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x);
827 fprintf (file, "%d", exact_log2 (INTVAL (x)));
828 return;
829
830 case 's':
831 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
832 respectively. This modifier also terminates the inhibiting
833 effects of the 'x' modifier. */
834 cris_output_insn_is_bound = 0;
835 if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
836 {
837 if (INTVAL (x) >= 0)
838 {
839 if (INTVAL (x) <= 255)
840 putc ('b', file);
841 else if (INTVAL (x) <= 65535)
842 putc ('w', file);
843 else
844 putc ('d', file);
845 }
846 else
847 putc ('d', file);
848 return;
849 }
850
851 /* For a non-integer, print the size of the operand. */
852 putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode)
853 ? 'd' : GET_MODE (x) == HImode ? 'w'
854 : GET_MODE (x) == QImode ? 'b'
855 /* If none of the above, emit an erroneous size letter. */
856 : 'X',
857 file);
858 return;
859
860 case 'z':
861 /* Const_int: print b for -127 <= x <= 255,
862 w for -32768 <= x <= 65535, else die. */
863 if (!CONST_INT_P (x)
864 || INTVAL (x) < -32768 || INTVAL (x) > 65535)
865 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x);
866 putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file);
867 return;
868
869 case 'Z':
870 /* If this is a GOT-symbol, print the size-letter corresponding to
871 -fpic/-fPIC. For everything else, print "d". */
872 putc ((flag_pic == 1
873 && GET_CODE (x) == CONST
874 && GET_CODE (XEXP (x, 0)) == UNSPEC
875 && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD)
876 ? 'w' : 'd', file);
877 return;
878
879 case '#':
880 /* Output a 'nop' if there's nothing for the delay slot.
881 This method stolen from the sparc files. */
882 if (dbr_sequence_length () == 0)
883 fputs ("\n\tnop", file);
884 return;
885
886 case '!':
887 /* Output directive for alignment padded with "nop" insns.
888 Optimizing for size, it's plain 4-byte alignment, otherwise we
889 align the section to a cache-line (32 bytes) and skip at max 2
890 bytes, i.e. we skip if it's the last insn on a cache-line. The
891 latter is faster by a small amount (for two test-programs 99.6%
892 and 99.9%) and larger by a small amount (ditto 100.1% and
893 100.2%). This is supposed to be the simplest yet performance-
894 wise least intrusive way to make sure the immediately following
895 (supposed) muls/mulu insn isn't located at the end of a
896 cache-line. */
897 if (TARGET_MUL_BUG)
898 fputs (optimize_size
899 ? ".p2alignw 2,0x050f\n\t"
900 : ".p2alignw 5,0x050f,2\n\t", file);
901 return;
902
903 case ':':
904 /* The PIC register. */
905 if (! flag_pic)
906 internal_error ("invalid use of %<:%> modifier");
907 fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]);
908 return;
909
910 case 'H':
911 /* Print high (most significant) part of something. */
912 switch (GET_CODE (operand))
913 {
914 case CONST_INT:
915 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
916 value is kept here, and so may be other than 0 or -1. */
917 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
918 INTVAL (operand_subword (operand, 1, 0, DImode)));
919 return;
920
921 case CONST_DOUBLE:
922 /* High part of a long long constant. */
923 if (GET_MODE (operand) == VOIDmode)
924 {
925 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
926 return;
927 }
928 else
929 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
930
931 case REG:
932 /* Print reg + 1. Check that there's not an attempt to print
933 high-parts of registers like stack-pointer or higher, except
934 for SRP (where the "high part" is MOF). */
935 if (REGNO (operand) > STACK_POINTER_REGNUM - 2
936 && (REGNO (operand) != CRIS_SRP_REGNUM
937 || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM
938 || fixed_regs[CRIS_MOF_REGNUM] != 0))
939 LOSE_AND_RETURN ("bad register", operand);
940 fprintf (file, "$%s", reg_names[REGNO (operand) + 1]);
941 return;
942
943 case MEM:
944 /* Adjust memory address to high part. */
945 {
946 rtx adj_mem = operand;
947 int size
948 = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT;
949
950 /* Adjust so we can use two SImode in DImode.
951 Calling adj_offsettable_operand will make sure it is an
952 offsettable address. Don't do this for a postincrement
953 though; it should remain as it was. */
954 if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC)
955 adj_mem
956 = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2);
957
958 output_address (VOIDmode, XEXP (adj_mem, 0));
959 return;
960 }
961
962 default:
963 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
964 }
965
966 case 'L':
967 /* Strip the MEM expression. */
968 operand = XEXP (operand, 0);
969 break;
970
971 case 'e':
972 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
973 iterators and attributes in cris.md to avoid the need for %x
974 and %E (and %e) and state passed between those modifiers. */
975 cris_output_insn_is_bound = 0;
976 /* FALL THROUGH. */
977 case 'E':
978 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
979 cris_output_insn_is_bound is nonzero. */
980 if (GET_CODE (operand) != SIGN_EXTEND
981 && GET_CODE (operand) != ZERO_EXTEND
982 && !CONST_INT_P (operand))
983 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x);
984
985 if (cris_output_insn_is_bound)
986 {
987 cris_output_insn_is_bound = 0;
988 return;
989 }
990
991 putc (GET_CODE (operand) == SIGN_EXTEND
992 || (CONST_INT_P (operand) && INTVAL (operand) < 0)
993 ? 's' : 'u', file);
994 return;
995
996 case 'm':
997 /* Print the size letter of the inner element. We can do it by
998 calling ourselves with the 's' modifier. */
999 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
1000 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x);
1001 cris_print_operand (file, XEXP (operand, 0), 's');
1002 return;
1003
1004 case 'M':
1005 /* Print the least significant part of operand. */
1006 if (GET_CODE (operand) == CONST_DOUBLE)
1007 {
1008 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
1009 return;
1010 }
1011 else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand))
1012 {
1013 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1014 INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1));
1015 return;
1016 }
1017 /* Otherwise the least significant part equals the normal part,
1018 so handle it normally. */
1019 break;
1020
1021 case 'A':
1022 /* When emitting an add for the high part of a DImode constant, we
1023 want to use addq for 0 and adds.w for -1. */
1024 if (!CONST_INT_P (operand))
1025 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x);
1026 fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq");
1027 return;
1028
1029 case 'P':
1030 /* For const_int operands, print the additive mnemonic and the
1031 modified operand (byte-sized operands don't save anything):
1032 N=MIN_INT..-65536: add.d N
1033 -65535..-64: subu.w -N
1034 -63..-1: subq -N
1035 0..63: addq N
1036 64..65535: addu.w N
1037 65536..MAX_INT: add.d N.
1038 (Emitted mnemonics are capitalized to simplify testing.)
1039 For anything else (N.B: only register is valid), print "add.d". */
1040 if (REG_P (operand))
1041 {
1042 fprintf (file, "Add.d ");
1043
1044 /* Deal with printing the operand by dropping through to the
1045 normal path. */
1046 break;
1047 }
1048 else
1049 {
1050 int val;
1051 gcc_assert (CONST_INT_P (operand));
1052
1053 val = INTVAL (operand);
1054 if (!IN_RANGE (val, -65535, 65535))
1055 fprintf (file, "Add.d %d", val);
1056 else if (val <= -64)
1057 fprintf (file, "Subu.w %d", -val);
1058 else if (val <= -1)
1059 fprintf (file, "Subq %d", -val);
1060 else if (val <= 63)
1061 fprintf (file, "Addq %d", val);
1062 else if (val <= 65535)
1063 fprintf (file, "Addu.w %d", val);
1064 return;
1065 }
1066 break;
1067
1068 case 'q':
1069 /* If the operand is an integer -31..31, print "q" else ".d". */
1070 if (CONST_INT_P (operand) && IN_RANGE (INTVAL (operand), -31, 31))
1071 fprintf (file, "q");
1072 else
1073 fprintf (file, ".d");
1074 return;
1075
1076 case 'd':
1077 /* If this is a GOT symbol, force it to be emitted as :GOT and
1078 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1079 Avoid making this too much of a special case. */
1080 if (flag_pic == 1 && CRIS_CONSTANT_P (operand))
1081 {
1082 int flag_pic_save = flag_pic;
1083
1084 flag_pic = 2;
1085 cris_output_addr_const (file, operand);
1086 flag_pic = flag_pic_save;
1087 return;
1088 }
1089 break;
1090
1091 case 'D':
1092 /* When emitting an sub for the high part of a DImode constant, we
1093 want to use subq for 0 and subs.w for -1. */
1094 if (!CONST_INT_P (operand))
1095 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x);
1096 fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq");
1097 return;
1098
1099 case 'S':
1100 /* Print the operand as the index-part of an address.
1101 Easiest way out is to use cris_print_index. */
1102 cris_print_index (operand, file);
1103 return;
1104
1105 case 'T':
1106 /* Print the size letter for an operand to a MULT, which must be a
1107 const_int with a suitable value. */
1108 if (!CONST_INT_P (operand) || INTVAL (operand) > 4)
1109 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x);
1110 fprintf (file, "%s", mults[INTVAL (operand)]);
1111 return;
1112
1113 case 'u':
1114 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1115 if (flag_pic == 1
1116 && GET_CODE (operand) == CONST
1117 && GET_CODE (XEXP (operand, 0)) == UNSPEC
1118 && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD)
1119 fprintf (file, "u.w");
1120 else
1121 fprintf (file, ".d");
1122 return;
1123
1124 case 0:
1125 /* No code, print as usual. */
1126 break;
1127
1128 default:
1129 LOSE_AND_RETURN ("invalid operand modifier letter", x);
1130 }
1131
1132 /* Print an operand as without a modifier letter. */
1133 switch (GET_CODE (operand))
1134 {
1135 case REG:
1136 if (REGNO (operand) > 15
1137 && REGNO (operand) != CRIS_MOF_REGNUM
1138 && REGNO (operand) != CRIS_SRP_REGNUM
1139 && REGNO (operand) != CRIS_CC0_REGNUM)
1140 internal_error ("internal error: bad register: %d", REGNO (operand));
1141 fprintf (file, "$%s", reg_names[REGNO (operand)]);
1142 return;
1143
1144 case MEM:
1145 output_address (GET_MODE (operand), XEXP (operand, 0));
1146 return;
1147
1148 case CONST_DOUBLE:
1149 if (GET_MODE (operand) == VOIDmode)
1150 /* A long long constant. */
1151 output_addr_const (file, operand);
1152 else
1153 {
1154 /* Only single precision is allowed as plain operands the
1155 moment. */
1156 long l;
1157
1158 /* FIXME: Perhaps check overflow of the "single". */
1159 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operand), l);
1160
1161 fprintf (file, "0x%lx", l);
1162 }
1163 return;
1164
1165 case UNSPEC:
1166 /* Fall through. */
1167 case CONST:
1168 cris_output_addr_const (file, operand);
1169 return;
1170
1171 case MULT:
1172 case ASHIFT:
1173 {
1174 /* For a (MULT (reg X) const_int) we output "rX.S". */
1175 int i = CONST_INT_P (XEXP (operand, 1))
1176 ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0));
1177 rtx reg = CONST_INT_P (XEXP (operand, 1))
1178 ? XEXP (operand, 0) : XEXP (operand, 1);
1179
1180 if (!REG_P (reg)
1181 || (!CONST_INT_P (XEXP (operand, 0))
1182 && !CONST_INT_P (XEXP (operand, 1))))
1183 LOSE_AND_RETURN ("unexpected multiplicative operand", x);
1184
1185 cris_print_base (reg, file);
1186 fprintf (file, ".%c",
1187 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b'
1188 : i == 4 ? 'd'
1189 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w'
1190 : 'd');
1191 return;
1192 }
1193
1194 default:
1195 /* No need to handle all strange variants, let output_addr_const
1196 do it for us. */
1197 if (CRIS_CONSTANT_P (operand))
1198 {
1199 cris_output_addr_const (file, operand);
1200 return;
1201 }
1202
1203 LOSE_AND_RETURN ("unexpected operand", x);
1204 }
1205 }
1206
1207 static bool
cris_print_operand_punct_valid_p(unsigned char code)1208 cris_print_operand_punct_valid_p (unsigned char code)
1209 {
1210 return (code == '#' || code == '!' || code == ':');
1211 }
1212
1213 /* The PRINT_OPERAND_ADDRESS worker. */
1214
1215 static void
cris_print_operand_address(FILE * file,machine_mode,rtx x)1216 cris_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x)
1217 {
1218 /* All these were inside MEM:s so output indirection characters. */
1219 putc ('[', file);
1220
1221 if (CONSTANT_ADDRESS_P (x))
1222 cris_output_addr_const (file, x);
1223 else if (cris_base_or_autoincr_p (x, true))
1224 cris_print_base (x, file);
1225 else if (GET_CODE (x) == PLUS)
1226 {
1227 rtx x1, x2;
1228
1229 x1 = XEXP (x, 0);
1230 x2 = XEXP (x, 1);
1231 if (cris_base_p (x1, true))
1232 {
1233 cris_print_base (x1, file);
1234 cris_print_index (x2, file);
1235 }
1236 else if (cris_base_p (x2, true))
1237 {
1238 cris_print_base (x2, file);
1239 cris_print_index (x1, file);
1240 }
1241 else
1242 LOSE_AND_RETURN ("unrecognized address", x);
1243 }
1244 else if (MEM_P (x))
1245 {
1246 /* A DIP. Output more indirection characters. */
1247 putc ('[', file);
1248 cris_print_base (XEXP (x, 0), file);
1249 putc (']', file);
1250 }
1251 else
1252 LOSE_AND_RETURN ("unrecognized address", x);
1253
1254 putc (']', file);
1255 }
1256
1257 /* The RETURN_ADDR_RTX worker.
1258 We mark that the return address is used, either by EH or
1259 __builtin_return_address, for use by the function prologue and
1260 epilogue. FIXME: This isn't optimal; we just use the mark in the
1261 prologue and epilogue to say that the return address is to be stored
1262 in the stack frame. We could return SRP for leaf-functions and use the
1263 initial-value machinery. */
1264
1265 rtx
cris_return_addr_rtx(int count,rtx frameaddr ATTRIBUTE_UNUSED)1266 cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED)
1267 {
1268 cfun->machine->needs_return_address_on_stack = 1;
1269
1270 /* The return-address is stored just above the saved frame-pointer (if
1271 present). Apparently we can't eliminate from the frame-pointer in
1272 that direction, so use the incoming args (maybe pretended) pointer. */
1273 return count == 0
1274 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, virtual_incoming_args_rtx, -4))
1275 : NULL_RTX;
1276 }
1277
1278 /* Accessor used in cris.md:return because cfun->machine isn't available
1279 there. */
1280
1281 bool
cris_return_address_on_stack(void)1282 cris_return_address_on_stack (void)
1283 {
1284 return df_regs_ever_live_p (CRIS_SRP_REGNUM)
1285 || cfun->machine->needs_return_address_on_stack;
1286 }
1287
1288 /* Accessor used in cris.md:return because cfun->machine isn't available
1289 there. */
1290
1291 bool
cris_return_address_on_stack_for_return(void)1292 cris_return_address_on_stack_for_return (void)
1293 {
1294 return cfun->machine->return_type == CRIS_RETINSN_RET ? false
1295 : cris_return_address_on_stack ();
1296 }
1297
1298 /* This handles FP -> SP elimination offset. */
1299
1300 static int
cris_initial_frame_pointer_offset(void)1301 cris_initial_frame_pointer_offset (void)
1302 {
1303 int regno;
1304
1305 /* Initial offset is 0 if we don't have a frame pointer. */
1306 int offs = 0;
1307 bool got_really_used = false;
1308
1309 if (crtl->uses_pic_offset_table)
1310 {
1311 push_topmost_sequence ();
1312 got_really_used
1313 = reg_used_between_p (pic_offset_table_rtx, get_insns (),
1314 NULL);
1315 pop_topmost_sequence ();
1316 }
1317
1318 /* And 4 for each register pushed. */
1319 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1320 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1321 offs += 4;
1322
1323 /* And then, last, we add the locals allocated. */
1324 offs += get_frame_size ();
1325
1326 /* And more; the accumulated args size. */
1327 offs += crtl->outgoing_args_size;
1328
1329 /* Then round it off, in case we use aligned stack. */
1330 if (TARGET_STACK_ALIGN)
1331 offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1;
1332
1333 return offs;
1334 }
1335
1336 /* The INITIAL_ELIMINATION_OFFSET worker.
1337 Calculate the difference between imaginary registers such as frame
1338 pointer and the stack pointer. Used to eliminate the frame pointer
1339 and imaginary arg pointer. */
1340
1341 int
cris_initial_elimination_offset(int fromreg,int toreg)1342 cris_initial_elimination_offset (int fromreg, int toreg)
1343 {
1344 int fp_sp_offset
1345 = cris_initial_frame_pointer_offset ();
1346
1347 /* We should be able to use regs_ever_live and related prologue
1348 information here, or alpha should not as well. */
1349 bool return_address_on_stack = cris_return_address_on_stack ();
1350
1351 /* Here we act as if the frame-pointer were needed. */
1352 int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
1353
1354 if (fromreg == ARG_POINTER_REGNUM
1355 && toreg == FRAME_POINTER_REGNUM)
1356 return ap_fp_offset;
1357
1358 /* Between the frame pointer and the stack are only "normal" stack
1359 variables and saved registers. */
1360 if (fromreg == FRAME_POINTER_REGNUM
1361 && toreg == STACK_POINTER_REGNUM)
1362 return fp_sp_offset;
1363
1364 /* We need to balance out the frame pointer here. */
1365 if (fromreg == ARG_POINTER_REGNUM
1366 && toreg == STACK_POINTER_REGNUM)
1367 return ap_fp_offset + fp_sp_offset - 4;
1368
1369 gcc_unreachable ();
1370 }
1371
1372 /* Nonzero if X is a hard reg that can be used as an index. */
1373 static inline bool
reg_ok_for_base_p(const_rtx x,bool strict)1374 reg_ok_for_base_p (const_rtx x, bool strict)
1375 {
1376 return ((! strict && ! HARD_REGISTER_P (x))
1377 || REGNO_OK_FOR_BASE_P (REGNO (x)));
1378 }
1379
1380 /* Nonzero if X is a hard reg that can be used as an index. */
1381 static inline bool
reg_ok_for_index_p(const_rtx x,bool strict)1382 reg_ok_for_index_p (const_rtx x, bool strict)
1383 {
1384 return reg_ok_for_base_p (x, strict);
1385 }
1386
1387 /* No symbol can be used as an index (or more correct, as a base) together
1388 with a register with PIC; the PIC register must be there. */
1389
1390 bool
cris_constant_index_p(const_rtx x)1391 cris_constant_index_p (const_rtx x)
1392 {
1393 return (CRIS_CONSTANT_P (x) && (!flag_pic || cris_valid_pic_const (x, true)));
1394 }
1395
1396 /* True if X is a valid base register. */
1397
1398 bool
cris_base_p(const_rtx x,bool strict)1399 cris_base_p (const_rtx x, bool strict)
1400 {
1401 return (REG_P (x) && reg_ok_for_base_p (x, strict));
1402 }
1403
1404 /* True if X is a valid index register. */
1405
1406 static inline bool
cris_index_p(const_rtx x,bool strict)1407 cris_index_p (const_rtx x, bool strict)
1408 {
1409 return (REG_P (x) && reg_ok_for_index_p (x, strict));
1410 }
1411
1412 /* True if X is a valid base register with or without autoincrement. */
1413
1414 bool
cris_base_or_autoincr_p(const_rtx x,bool strict)1415 cris_base_or_autoincr_p (const_rtx x, bool strict)
1416 {
1417 return (cris_base_p (x, strict)
1418 || (GET_CODE (x) == POST_INC
1419 && cris_base_p (XEXP (x, 0), strict)
1420 && REGNO (XEXP (x, 0)) != CRIS_ACR_REGNUM));
1421 }
1422
1423 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1424
1425 bool
cris_bdap_index_p(const_rtx x,bool strict)1426 cris_bdap_index_p (const_rtx x, bool strict)
1427 {
1428 return ((MEM_P (x)
1429 && GET_MODE (x) == SImode
1430 && cris_base_or_autoincr_p (XEXP (x, 0), strict))
1431 || (GET_CODE (x) == SIGN_EXTEND
1432 && MEM_P (XEXP (x, 0))
1433 && (GET_MODE (XEXP (x, 0)) == HImode
1434 || GET_MODE (XEXP (x, 0)) == QImode)
1435 && cris_base_or_autoincr_p (XEXP (XEXP (x, 0), 0), strict)));
1436 }
1437
1438 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1439
1440 bool
cris_biap_index_p(const_rtx x,bool strict)1441 cris_biap_index_p (const_rtx x, bool strict)
1442 {
1443 return (cris_index_p (x, strict)
1444 || (GET_CODE (x) == MULT
1445 && cris_index_p (XEXP (x, 0), strict)
1446 && cris_scale_int_operand (XEXP (x, 1), VOIDmode)));
1447 }
1448
1449 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1450
1451 A PIC operand looks like a normal symbol here. At output we dress it
1452 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1453 symbol) so we exclude all addressing modes where we can't replace a
1454 plain "symbol" with that. A global PIC symbol does not fit anywhere
1455 here (but is thankfully a general_operand in itself). A local PIC
1456 symbol is valid for the plain "symbol + offset" case. */
1457
1458 bool
cris_legitimate_address_p(machine_mode mode,rtx x,bool strict)1459 cris_legitimate_address_p (machine_mode mode, rtx x, bool strict)
1460 {
1461 const_rtx x1, x2;
1462
1463 if (cris_base_or_autoincr_p (x, strict))
1464 return true;
1465 else if (TARGET_V32)
1466 /* Nothing else is valid then. */
1467 return false;
1468 else if (cris_constant_index_p (x))
1469 return true;
1470 /* Indexed? */
1471 else if (GET_CODE (x) == PLUS)
1472 {
1473 x1 = XEXP (x, 0);
1474 x2 = XEXP (x, 1);
1475 /* BDAP o, Rd. */
1476 if ((cris_base_p (x1, strict) && cris_constant_index_p (x2))
1477 || (cris_base_p (x2, strict) && cris_constant_index_p (x1))
1478 /* BDAP Rs[+], Rd. */
1479 || (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1480 && ((cris_base_p (x1, strict)
1481 && cris_bdap_index_p (x2, strict))
1482 || (cris_base_p (x2, strict)
1483 && cris_bdap_index_p (x1, strict))
1484 /* BIAP.m Rs, Rd */
1485 || (cris_base_p (x1, strict)
1486 && cris_biap_index_p (x2, strict))
1487 || (cris_base_p (x2, strict)
1488 && cris_biap_index_p (x1, strict)))))
1489 return true;
1490 }
1491 else if (MEM_P (x))
1492 {
1493 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1494 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1495 && cris_base_or_autoincr_p (XEXP (x, 0), strict))
1496 return true;
1497 }
1498
1499 return false;
1500 }
1501
1502 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle
1503 PIC constants that aren't legitimized. FIXME: there used to be a
1504 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle
1505 PIC constants, but no more (4.7 era); testcase: glibc init-first.c.
1506 While that may be seen as a bug, that guarantee seems a wart by design,
1507 so don't bother; fix the documentation instead. */
1508
1509 bool
cris_legitimate_constant_p(machine_mode mode ATTRIBUTE_UNUSED,rtx x)1510 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1511 {
1512 enum cris_symbol_type t;
1513
1514 if (flag_pic)
1515 return LEGITIMATE_PIC_OPERAND_P (x);
1516
1517 t = cris_symbol_type_of (x);
1518
1519 return
1520 t == cris_no_symbol
1521 || t == cris_offsettable_symbol
1522 || t == cris_unspec;
1523 }
1524
1525 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1526
1527 bool
cris_reload_address_legitimized(rtx x,machine_mode mode ATTRIBUTE_UNUSED,int opnum ATTRIBUTE_UNUSED,int itype,int ind_levels ATTRIBUTE_UNUSED)1528 cris_reload_address_legitimized (rtx x,
1529 machine_mode mode ATTRIBUTE_UNUSED,
1530 int opnum ATTRIBUTE_UNUSED,
1531 int itype,
1532 int ind_levels ATTRIBUTE_UNUSED)
1533 {
1534 enum reload_type type = (enum reload_type) itype;
1535 rtx op0, op1;
1536 rtx *op1p;
1537
1538 if (GET_CODE (x) != PLUS)
1539 return false;
1540
1541 if (TARGET_V32)
1542 return false;
1543
1544 op0 = XEXP (x, 0);
1545 op1 = XEXP (x, 1);
1546 op1p = &XEXP (x, 1);
1547
1548 if (!REG_P (op1))
1549 return false;
1550
1551 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0)))
1552 {
1553 rtx op00 = XEXP (op0, 0);
1554 rtx op000 = XEXP (op00, 0);
1555 rtx *op000p = &XEXP (op00, 0);
1556
1557 if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode)
1558 && (REG_P (op000)
1559 || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0)))))
1560 {
1561 bool something_reloaded = false;
1562
1563 if (GET_CODE (op000) == POST_INC
1564 && REG_P (XEXP (op000, 0))
1565 && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER)
1566 /* No, this gets too complicated and is too rare to care
1567 about trying to improve on the general code Here.
1568 As the return-value is an all-or-nothing indicator, we
1569 punt on the other register too. */
1570 return false;
1571
1572 if ((REG_P (op000)
1573 && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER))
1574 {
1575 /* The address of the inner mem is a pseudo or wrong
1576 reg: reload that. */
1577 push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS,
1578 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
1579 something_reloaded = true;
1580 }
1581
1582 if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER)
1583 {
1584 /* Base register is a pseudo or wrong reg: reload it. */
1585 push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS,
1586 GET_MODE (x), VOIDmode, 0, 0,
1587 opnum, type);
1588 something_reloaded = true;
1589 }
1590
1591 gcc_assert (something_reloaded);
1592
1593 return true;
1594 }
1595 }
1596
1597 return false;
1598 }
1599
1600
1601 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1602
1603 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1604 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1605 out a constant into the constant pool, we will trap this case and
1606 return something a bit more sane. FIXME: Check if this is a bug.
1607 Beware that we must not "override" classes that can be specified as
1608 constraint letters, or else asm operands using them will fail when
1609 they need to be reloaded. FIXME: Investigate whether that constitutes
1610 a bug. */
1611
1612 static reg_class_t
cris_preferred_reload_class(rtx x ATTRIBUTE_UNUSED,reg_class_t rclass)1613 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass)
1614 {
1615 if (rclass != ACR_REGS
1616 && rclass != MOF_REGS
1617 && rclass != MOF_SRP_REGS
1618 && rclass != SRP_REGS
1619 && rclass != CC0_REGS
1620 && rclass != SPECIAL_REGS)
1621 return GENNONACR_REGS;
1622
1623 return rclass;
1624 }
1625
1626 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1627
1628 static int
cris_register_move_cost(machine_mode mode ATTRIBUTE_UNUSED,reg_class_t from,reg_class_t to)1629 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
1630 reg_class_t from, reg_class_t to)
1631 {
1632 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1633 their move cost within that class is higher. How about 7? That's 3
1634 for a move to a GENERAL_REGS register, 3 for the move from the
1635 GENERAL_REGS register, and 1 for the increased register pressure.
1636 Also, it's higher than the memory move cost, as it should.
1637 We also do this for ALL_REGS, since we don't want that class to be
1638 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1639 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1640 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1641 used when a GENERAL_REGS should be used, even if there are call-saved
1642 GENERAL_REGS left to allocate. This is because the fall-back when
1643 the most preferred register class isn't available, isn't the next
1644 (or next good) wider register class, but the *most widest* register
1645 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1646
1647 if ((reg_classes_intersect_p (from, SPECIAL_REGS)
1648 && reg_classes_intersect_p (to, SPECIAL_REGS))
1649 || from == ALL_REGS || to == ALL_REGS)
1650 return 7;
1651
1652 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1653 generally prefer GENERAL_REGS. */
1654 if (reg_classes_intersect_p (from, SPECIAL_REGS)
1655 || reg_classes_intersect_p (to, SPECIAL_REGS))
1656 return 3;
1657
1658 return 2;
1659 }
1660
1661 /* Worker function for TARGET_MEMORY_MOVE_COST.
1662
1663 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1664 suffice. */
1665
1666 static int
cris_memory_move_cost(machine_mode mode,reg_class_t rclass ATTRIBUTE_UNUSED,bool in ATTRIBUTE_UNUSED)1667 cris_memory_move_cost (machine_mode mode,
1668 reg_class_t rclass ATTRIBUTE_UNUSED,
1669 bool in ATTRIBUTE_UNUSED)
1670 {
1671 if (mode == QImode
1672 || mode == HImode)
1673 return 4;
1674 else
1675 return 6;
1676 }
1677
1678 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1679 FIXME: this code is historical; its functionality should be
1680 refactored to look at insn attributes and moved to
1681 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1682
1683 static void
cris_normal_notice_update_cc(rtx exp,rtx insn)1684 cris_normal_notice_update_cc (rtx exp, rtx insn)
1685 {
1686 /* "Normal" means, for:
1687 (set (cc0) (...)):
1688 CC is (...).
1689
1690 (set (reg) (...)):
1691 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1692 register or (v32 and (...) is -32..-1), then CC does not change.
1693 CC_NO_OVERFLOW unless (...) is reg or mem.
1694
1695 (set (mem) (...)):
1696 CC does not change.
1697
1698 (set (pc) (...)):
1699 CC does not change.
1700
1701 (parallel
1702 (set (reg1) (mem (bdap/biap)))
1703 (set (reg2) (bdap/biap))):
1704 CC is (reg1) and (mem (reg2))
1705
1706 (parallel
1707 (set (mem (bdap/biap)) (reg1)) [or 0]
1708 (set (reg2) (bdap/biap))):
1709 CC does not change.
1710
1711 (where reg and mem includes strict_low_parts variants thereof)
1712
1713 For all others, assume CC is clobbered.
1714 Note that we do not have to care about setting CC_NO_OVERFLOW,
1715 since the overflow flag is set to 0 (i.e. right) for
1716 instructions where it does not have any sane sense, but where
1717 other flags have meanings. (This includes shifts; the carry is
1718 not set by them).
1719
1720 Note that there are other parallel constructs we could match,
1721 but we don't do that yet. */
1722
1723 if (GET_CODE (exp) == SET)
1724 {
1725 /* FIXME: Check when this happens. It looks like we should
1726 actually do a CC_STATUS_INIT here to be safe. */
1727 if (SET_DEST (exp) == pc_rtx)
1728 return;
1729
1730 /* Record CC0 changes, so we do not have to output multiple
1731 test insns. */
1732 if (SET_DEST (exp) == cc0_rtx)
1733 {
1734 CC_STATUS_INIT;
1735
1736 if (GET_CODE (SET_SRC (exp)) == COMPARE
1737 && XEXP (SET_SRC (exp), 1) == const0_rtx)
1738 cc_status.value1 = XEXP (SET_SRC (exp), 0);
1739 else
1740 cc_status.value1 = SET_SRC (exp);
1741
1742 /* Handle flags for the special btstq on one bit. */
1743 if (GET_CODE (cc_status.value1) == ZERO_EXTRACT
1744 && XEXP (cc_status.value1, 1) == const1_rtx)
1745 {
1746 if (CONST_INT_P (XEXP (cc_status.value1, 0)))
1747 /* Using cmpq. */
1748 cc_status.flags = CC_INVERTED;
1749 else
1750 /* A one-bit btstq. */
1751 cc_status.flags = CC_Z_IN_NOT_N;
1752 }
1753
1754 else if (GET_CODE (SET_SRC (exp)) == COMPARE)
1755 {
1756 if (!REG_P (XEXP (SET_SRC (exp), 0))
1757 && XEXP (SET_SRC (exp), 1) != const0_rtx)
1758 /* For some reason gcc will not canonicalize compare
1759 operations, reversing the sign by itself if
1760 operands are in wrong order. */
1761 /* (But NOT inverted; eq is still eq.) */
1762 cc_status.flags = CC_REVERSED;
1763
1764 /* This seems to be overlooked by gcc. FIXME: Check again.
1765 FIXME: Is it really safe? */
1766 cc_status.value2
1767 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)),
1768 XEXP (SET_SRC (exp), 0),
1769 XEXP (SET_SRC (exp), 1));
1770 }
1771 return;
1772 }
1773 else if (REG_P (SET_DEST (exp))
1774 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1775 && REG_P (XEXP (SET_DEST (exp), 0))))
1776 {
1777 /* A register is set; normally CC is set to show that no
1778 test insn is needed. Catch the exceptions. */
1779
1780 /* If not to cc0, then no "set"s in non-natural mode give
1781 ok cc0... */
1782 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
1783 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
1784 {
1785 /* ... except add:s and sub:s in DImode. */
1786 if (GET_MODE (SET_DEST (exp)) == DImode
1787 && (GET_CODE (SET_SRC (exp)) == PLUS
1788 || GET_CODE (SET_SRC (exp)) == MINUS))
1789 {
1790 CC_STATUS_INIT;
1791 cc_status.value1 = SET_DEST (exp);
1792 cc_status.value2 = SET_SRC (exp);
1793
1794 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1795 cc_status.value2))
1796 cc_status.value2 = 0;
1797
1798 /* Add and sub may set V, which gets us
1799 unoptimizable results in "gt" and "le" condition
1800 codes. */
1801 cc_status.flags |= CC_NO_OVERFLOW;
1802
1803 return;
1804 }
1805 }
1806 else if (SET_SRC (exp) == const0_rtx
1807 || (REG_P (SET_SRC (exp))
1808 && (REGNO (SET_SRC (exp))
1809 > CRIS_LAST_GENERAL_REGISTER))
1810 || (TARGET_V32
1811 && REG_P (SET_DEST (exp))
1812 && satisfies_constraint_I (SET_SRC (exp))))
1813 {
1814 /* There's no CC0 change for this case. Just check
1815 for overlap. */
1816 if (cc_status.value1
1817 && modified_in_p (cc_status.value1, insn))
1818 cc_status.value1 = 0;
1819
1820 if (cc_status.value2
1821 && modified_in_p (cc_status.value2, insn))
1822 cc_status.value2 = 0;
1823
1824 return;
1825 }
1826 else
1827 {
1828 CC_STATUS_INIT;
1829 cc_status.value1 = SET_DEST (exp);
1830 cc_status.value2 = SET_SRC (exp);
1831
1832 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1833 cc_status.value2))
1834 cc_status.value2 = 0;
1835
1836 /* Some operations may set V, which gets us
1837 unoptimizable results in "gt" and "le" condition
1838 codes. */
1839 if (GET_CODE (SET_SRC (exp)) == PLUS
1840 || GET_CODE (SET_SRC (exp)) == MINUS
1841 || GET_CODE (SET_SRC (exp)) == NEG)
1842 cc_status.flags |= CC_NO_OVERFLOW;
1843
1844 /* For V32, nothing with a register destination sets
1845 C and V usefully. */
1846 if (TARGET_V32)
1847 cc_status.flags |= CC_NO_OVERFLOW;
1848
1849 return;
1850 }
1851 }
1852 else if (MEM_P (SET_DEST (exp))
1853 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1854 && MEM_P (XEXP (SET_DEST (exp), 0))))
1855 {
1856 /* When SET to MEM, then CC is not changed (except for
1857 overlap). */
1858 if (cc_status.value1
1859 && modified_in_p (cc_status.value1, insn))
1860 cc_status.value1 = 0;
1861
1862 if (cc_status.value2
1863 && modified_in_p (cc_status.value2, insn))
1864 cc_status.value2 = 0;
1865
1866 return;
1867 }
1868 }
1869 else if (GET_CODE (exp) == PARALLEL)
1870 {
1871 if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
1872 && GET_CODE (XVECEXP (exp, 0, 1)) == SET
1873 && REG_P (XEXP (XVECEXP (exp, 0, 1), 0)))
1874 {
1875 if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0))
1876 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1)))
1877 {
1878 CC_STATUS_INIT;
1879
1880 /* For "move.S [rx=ry+o],rz", say CC reflects
1881 value1=rz and value2=[rx] */
1882 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1883 cc_status.value2
1884 = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1),
1885 XEXP (XVECEXP (exp, 0, 1), 0));
1886
1887 /* Huh? A side-effect cannot change the destination
1888 register. */
1889 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1890 cc_status.value2))
1891 internal_error ("internal error: sideeffect-insn affecting main effect");
1892
1893 /* For V32, moves to registers don't set C and V. */
1894 if (TARGET_V32)
1895 cc_status.flags |= CC_NO_OVERFLOW;
1896 return;
1897 }
1898 else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1))
1899 || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx)
1900 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0)))
1901 {
1902 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1903 say flags are not changed, except for overlap. */
1904 if (cc_status.value1
1905 && modified_in_p (cc_status.value1, insn))
1906 cc_status.value1 = 0;
1907
1908 if (cc_status.value2
1909 && modified_in_p (cc_status.value2, insn))
1910 cc_status.value2 = 0;
1911
1912 return;
1913 }
1914 }
1915 }
1916
1917 /* If we got here, the case wasn't covered by the code above. */
1918 CC_STATUS_INIT;
1919 }
1920
1921 /* This function looks into the pattern to see how this insn affects
1922 condition codes.
1923
1924 Used when to eliminate test insns before a condition-code user,
1925 such as a "scc" insn or a conditional branch. This includes
1926 checking if the entities that cc was updated by, are changed by the
1927 operation.
1928
1929 Currently a jumble of the old peek-inside-the-insn and the newer
1930 check-cc-attribute methods. */
1931
1932 void
cris_notice_update_cc(rtx exp,rtx_insn * insn)1933 cris_notice_update_cc (rtx exp, rtx_insn *insn)
1934 {
1935 enum attr_cc attrval = get_attr_cc (insn);
1936
1937 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1938 to still set CC_REVERSED as below, since that's required by some
1939 compare insn alternatives. (FIXME: GCC should do this virtual
1940 operand swap by itself.) A test-case that may otherwise fail is
1941 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1942 if (TARGET_CCINIT)
1943 {
1944 CC_STATUS_INIT;
1945
1946 if (attrval == CC_REV)
1947 cc_status.flags = CC_REVERSED;
1948 return;
1949 }
1950
1951 /* Slowly, we're converting to using attributes to control the setting
1952 of condition-code status. */
1953 switch (attrval)
1954 {
1955 case CC_NONE:
1956 /* Even if it is "none", a setting may clobber a previous
1957 cc-value, so check. */
1958 if (GET_CODE (exp) == SET)
1959 {
1960 if (cc_status.value1
1961 && modified_in_p (cc_status.value1, insn))
1962 cc_status.value1 = 0;
1963
1964 if (cc_status.value2
1965 && modified_in_p (cc_status.value2, insn))
1966 cc_status.value2 = 0;
1967 }
1968 return;
1969
1970 case CC_CLOBBER:
1971 CC_STATUS_INIT;
1972 return;
1973
1974 case CC_REV:
1975 case CC_NOOV32:
1976 case CC_NORMAL:
1977 cris_normal_notice_update_cc (exp, insn);
1978
1979 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1980 can change bge => bpl and blt => bmi by passing on to the cc0
1981 user that V should not be considered; bgt and ble are taken
1982 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1983 if (attrval == CC_NOOV32 && TARGET_V32)
1984 cc_status.flags |= CC_NO_OVERFLOW;
1985 return;
1986
1987 default:
1988 internal_error ("unknown cc_attr value");
1989 }
1990
1991 CC_STATUS_INIT;
1992 }
1993
1994 /* Return != 0 if the return sequence for the current function is short,
1995 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1996 registers must be saved, so return 0 then. */
1997
1998 bool
cris_simple_epilogue(void)1999 cris_simple_epilogue (void)
2000 {
2001 unsigned int regno;
2002 unsigned int reglimit = STACK_POINTER_REGNUM;
2003 bool got_really_used = false;
2004
2005 if (! reload_completed
2006 || frame_pointer_needed
2007 || get_frame_size () != 0
2008 || crtl->args.pretend_args_size
2009 || crtl->args.size
2010 || crtl->outgoing_args_size
2011 || crtl->calls_eh_return
2012
2013 /* If we're not supposed to emit prologue and epilogue, we must
2014 not emit return-type instructions. */
2015 || !TARGET_PROLOGUE_EPILOGUE)
2016 return false;
2017
2018 /* Can't return from stacked return address with v32. */
2019 if (TARGET_V32 && cris_return_address_on_stack ())
2020 return false;
2021
2022 if (crtl->uses_pic_offset_table)
2023 {
2024 push_topmost_sequence ();
2025 got_really_used
2026 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL);
2027 pop_topmost_sequence ();
2028 }
2029
2030 /* No simple epilogue if there are saved registers. */
2031 for (regno = 0; regno < reglimit; regno++)
2032 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2033 return false;
2034
2035 return true;
2036 }
2037
2038 /* Emit checking that MEM is aligned for an access in MODE, failing
2039 that, executing a "break 8" (or call to abort, if "break 8" is
2040 disabled). */
2041
2042 void
cris_emit_trap_for_misalignment(rtx mem)2043 cris_emit_trap_for_misalignment (rtx mem)
2044 {
2045 rtx addr, reg, ok_label, andop;
2046 rtx_insn *jmp;
2047 int natural_alignment;
2048 gcc_assert (MEM_P (mem));
2049
2050 natural_alignment = GET_MODE_SIZE (GET_MODE (mem));
2051 addr = XEXP (mem, 0);
2052 reg = force_reg (Pmode, addr);
2053 ok_label = gen_label_rtx ();
2054
2055 /* This will yield a btstq without a separate register used, usually -
2056 with the exception for PRE hoisting the "and" but not the branch
2057 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2058 andop = gen_rtx_AND (Pmode, reg, GEN_INT (natural_alignment - 1));
2059 emit_cmp_and_jump_insns (force_reg (SImode, andop), const0_rtx, EQ,
2060 NULL_RTX, Pmode, 1, ok_label);
2061 jmp = get_last_insn ();
2062 gcc_assert (JUMP_P (jmp));
2063
2064 predict_insn_def (jmp, PRED_NORETURN, TAKEN);
2065 expand_builtin_trap ();
2066 emit_label (ok_label);
2067 }
2068
2069 /* Expand a return insn (just one insn) marked as using SRP or stack
2070 slot depending on parameter ON_STACK. */
2071
2072 void
cris_expand_return(bool on_stack)2073 cris_expand_return (bool on_stack)
2074 {
2075 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2076 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2077 GCC expect just (return) to do the right thing when optimizing, so
2078 we do that until they're fixed. Currently, all return insns in a
2079 function must be the same (not really a limiting factor) so we need
2080 to check that it doesn't change half-way through. */
2081 emit_jump_insn (ret_rtx);
2082
2083 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
2084 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
2085
2086 cfun->machine->return_type
2087 = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET;
2088 }
2089
2090 /* Compute a (partial) cost for rtx X. Return true if the complete
2091 cost has been computed, and false if subexpressions should be
2092 scanned. In either case, *TOTAL contains the cost result. */
2093
2094 static bool
cris_rtx_costs(rtx x,machine_mode mode,int outer_code,int opno,int * total,bool speed)2095 cris_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno,
2096 int *total, bool speed)
2097 {
2098 int code = GET_CODE (x);
2099
2100 switch (code)
2101 {
2102 case CONST_INT:
2103 {
2104 HOST_WIDE_INT val = INTVAL (x);
2105 if (val == 0)
2106 *total = 0;
2107 else if (val < 32 && val >= -32)
2108 *total = 1;
2109 /* Eight or 16 bits are a word and cycle more expensive. */
2110 else if (val <= 32767 && val >= -32768)
2111 *total = 2;
2112 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2113 another word. FIXME: This isn't linear to 16 bits. */
2114 else
2115 *total = 4;
2116 return true;
2117 }
2118
2119 case LABEL_REF:
2120 *total = 6;
2121 return true;
2122
2123 case CONST:
2124 case SYMBOL_REF:
2125 *total = 6;
2126 return true;
2127
2128 case CONST_DOUBLE:
2129 if (x != CONST0_RTX (mode == VOIDmode ? DImode : mode))
2130 *total = 12;
2131 else
2132 /* Make 0.0 cheap, else test-insns will not be used. */
2133 *total = 0;
2134 return true;
2135
2136 case MULT:
2137 /* If we have one arm of an ADDI, make sure it gets the cost of
2138 one insn, i.e. zero cost for this operand, and just the cost
2139 of the PLUS, as the insn is created by combine from a PLUS
2140 and an ASHIFT, and the MULT cost below would make the
2141 combined value be larger than the separate insns. The insn
2142 validity is checked elsewhere by combine.
2143
2144 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2145 function should be rewritten. */
2146 if (outer_code == PLUS && cris_biap_index_p (x, false))
2147 {
2148 *total = 0;
2149 return true;
2150 }
2151
2152 /* Identify values that are no powers of two. Powers of 2 are
2153 taken care of already and those values should not be changed. */
2154 if (!CONST_INT_P (XEXP (x, 1))
2155 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
2156 {
2157 /* If we have a multiply insn, then the cost is between
2158 1 and 2 "fast" instructions. */
2159 if (TARGET_HAS_MUL_INSNS)
2160 {
2161 *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2162 return true;
2163 }
2164
2165 /* Estimate as 4 + 4 * #ofbits. */
2166 *total = COSTS_N_INSNS (132);
2167 return true;
2168 }
2169 return false;
2170
2171 case UDIV:
2172 case MOD:
2173 case UMOD:
2174 case DIV:
2175 if (!CONST_INT_P (XEXP (x, 1))
2176 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
2177 {
2178 /* Estimate this as 4 + 8 * #of bits. */
2179 *total = COSTS_N_INSNS (260);
2180 return true;
2181 }
2182 return false;
2183
2184 case AND:
2185 if (CONST_INT_P (XEXP (x, 1))
2186 /* Two constants may actually happen before optimization. */
2187 && !CONST_INT_P (XEXP (x, 0))
2188 && !satisfies_constraint_I (XEXP (x, 1)))
2189 {
2190 *total
2191 = (rtx_cost (XEXP (x, 0), mode, (enum rtx_code) outer_code,
2192 opno, speed) + 2
2193 + 2 * GET_MODE_NUNITS (mode));
2194 return true;
2195 }
2196 return false;
2197
2198 case ZERO_EXTRACT:
2199 if (outer_code != COMPARE)
2200 return false;
2201 /* fall through */
2202
2203 case ZERO_EXTEND: case SIGN_EXTEND:
2204 *total = rtx_cost (XEXP (x, 0), VOIDmode, (enum rtx_code) outer_code,
2205 opno, speed);
2206 return true;
2207
2208 default:
2209 return false;
2210 }
2211 }
2212
2213 /* The ADDRESS_COST worker. */
2214
2215 static int
cris_address_cost(rtx x,machine_mode mode ATTRIBUTE_UNUSED,addr_space_t as ATTRIBUTE_UNUSED,bool speed ATTRIBUTE_UNUSED)2216 cris_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED,
2217 addr_space_t as ATTRIBUTE_UNUSED,
2218 bool speed ATTRIBUTE_UNUSED)
2219 {
2220 /* The metric to use for the cost-macros is unclear.
2221 The metric used here is (the number of cycles needed) / 2,
2222 where we consider equal a cycle for a word of code and a cycle to
2223 read memory. FIXME: Adding "+ 1" to all values would avoid
2224 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2225 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2226 Unfortunately(?) such a hack would expose other pessimizations,
2227 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2228 loop there, without apparent reason. */
2229
2230 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2231 if (cris_base_or_autoincr_p (x, false))
2232 return 0;
2233
2234 /* An indirect mem must be a DIP. This means two bytes extra for code,
2235 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2236 if (MEM_P (x))
2237 return (2 + 4) / 2;
2238
2239 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2240 an extra DIP prefix and 4 bytes of constant in most cases. */
2241 if (CONSTANT_P (x))
2242 return (2 + 4) / 2;
2243
2244 /* Handle BIAP and BDAP prefixes. */
2245 if (GET_CODE (x) == PLUS)
2246 {
2247 rtx tem1 = XEXP (x, 0);
2248 rtx tem2 = XEXP (x, 1);
2249
2250 /* Local extended canonicalization rule: the first operand must
2251 be REG, unless it's an operation (MULT). */
2252 if (!REG_P (tem1) && GET_CODE (tem1) != MULT)
2253 tem1 = tem2, tem2 = XEXP (x, 0);
2254
2255 /* We'll "assume" we have canonical RTX now. */
2256 gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT);
2257
2258 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2259 recognize the typical MULT which is always in tem1 because of
2260 insn canonicalization. */
2261 if ((GET_CODE (tem1) == MULT && cris_biap_index_p (tem1, false))
2262 || REG_P (tem2))
2263 return 2 / 2;
2264
2265 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2266 PLUS is always found in tem2. */
2267 if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128)
2268 return 2 / 2;
2269
2270 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2271 bytes. */
2272 if (satisfies_constraint_L (tem2))
2273 return (2 + 2) / 2;
2274
2275 /* A BDAP with some other constant is 2 bytes extra. */
2276 if (CRIS_CONSTANT_P (tem2))
2277 return (2 + 2 + 2) / 2;
2278
2279 /* BDAP with something indirect should have a higher cost than
2280 BIAP with register. FIXME: Should it cost like a MEM or more? */
2281 return (2 + 2 + 2) / 2;
2282 }
2283
2284 /* What else? Return a high cost. It matters only for valid
2285 addressing modes. */
2286 return 10;
2287 }
2288
2289 /* Check various objections to the side-effect. Used in the test-part
2290 of an anonymous insn describing an insn with a possible side-effect.
2291 Returns nonzero if the implied side-effect is ok.
2292
2293 code : PLUS or MULT
2294 ops : An array of rtx:es. lreg, rreg, rval,
2295 The variables multop and other_op are indexes into this,
2296 or -1 if they are not applicable.
2297 lreg : The register that gets assigned in the side-effect.
2298 rreg : One register in the side-effect expression
2299 rval : The other register, or an int.
2300 multop : An integer to multiply rval with.
2301 other_op : One of the entities of the main effect,
2302 whose mode we must consider. */
2303
2304 int
cris_side_effect_mode_ok(enum rtx_code code,rtx * ops,int lreg,int rreg,int rval,int multop,int other_op)2305 cris_side_effect_mode_ok (enum rtx_code code, rtx *ops,
2306 int lreg, int rreg, int rval,
2307 int multop, int other_op)
2308 {
2309 /* Find what value to multiply with, for rx =ry + rz * n. */
2310 int mult = multop < 0 ? 1 : INTVAL (ops[multop]);
2311
2312 rtx reg_rtx = ops[rreg];
2313 rtx val_rtx = ops[rval];
2314
2315 /* The operands may be swapped. Canonicalize them in reg_rtx and
2316 val_rtx, where reg_rtx always is a reg (for this constraint to
2317 match). */
2318 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed))
2319 reg_rtx = val_rtx, val_rtx = ops[rreg];
2320
2321 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2322 we have no business. */
2323 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed))
2324 return 0;
2325
2326 /* Don't do this when -mno-split. */
2327 if (!TARGET_SIDE_EFFECT_PREFIXES)
2328 return 0;
2329
2330 /* The mult expression may be hidden in lreg. FIXME: Add more
2331 commentary about that. */
2332 if (GET_CODE (val_rtx) == MULT)
2333 {
2334 mult = INTVAL (XEXP (val_rtx, 1));
2335 val_rtx = XEXP (val_rtx, 0);
2336 code = MULT;
2337 }
2338
2339 /* First check the "other operand". */
2340 if (other_op >= 0)
2341 {
2342 if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD)
2343 return 0;
2344
2345 /* Check if the lvalue register is the same as the "other
2346 operand". If so, the result is undefined and we shouldn't do
2347 this. FIXME: Check again. */
2348 if ((cris_base_p (ops[lreg], reload_in_progress || reload_completed)
2349 && cris_base_p (ops[other_op],
2350 reload_in_progress || reload_completed)
2351 && REGNO (ops[lreg]) == REGNO (ops[other_op]))
2352 || rtx_equal_p (ops[other_op], ops[lreg]))
2353 return 0;
2354 }
2355
2356 /* Do not accept frame_pointer_rtx as any operand. */
2357 if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx
2358 || ops[rval] == frame_pointer_rtx
2359 || (other_op >= 0 && ops[other_op] == frame_pointer_rtx))
2360 return 0;
2361
2362 if (code == PLUS
2363 && ! cris_base_p (val_rtx, reload_in_progress || reload_completed))
2364 {
2365
2366 /* Do not allow rx = rx + n if a normal add or sub with same size
2367 would do. */
2368 if (rtx_equal_p (ops[lreg], reg_rtx)
2369 && CONST_INT_P (val_rtx)
2370 && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63))
2371 return 0;
2372
2373 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2374 if (CRIS_CONSTANT_P (val_rtx))
2375 return 1;
2376
2377 if (MEM_P (val_rtx)
2378 && cris_base_or_autoincr_p (XEXP (val_rtx, 0),
2379 reload_in_progress || reload_completed))
2380 return 1;
2381
2382 if (GET_CODE (val_rtx) == SIGN_EXTEND
2383 && MEM_P (XEXP (val_rtx, 0))
2384 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx, 0), 0),
2385 reload_in_progress || reload_completed))
2386 return 1;
2387
2388 /* If we got here, it's not a valid addressing mode. */
2389 return 0;
2390 }
2391 else if (code == MULT
2392 || (code == PLUS
2393 && cris_base_p (val_rtx,
2394 reload_in_progress || reload_completed)))
2395 {
2396 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2397 if (rtx_equal_p (ops[lreg], reg_rtx)
2398 || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx)))
2399 return 0;
2400
2401 /* Do not allow bad multiply-values. */
2402 if (mult != 1 && mult != 2 && mult != 4)
2403 return 0;
2404
2405 /* Only allow r + ... */
2406 if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed))
2407 return 0;
2408
2409 /* If we got here, all seems ok.
2410 (All checks need to be done above). */
2411 return 1;
2412 }
2413
2414 /* If we get here, the caller got its initial tests wrong. */
2415 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2416 }
2417
2418 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2419 insn for other reasons. */
2420
2421 bool
cris_cc0_user_requires_cmp(rtx_insn * insn)2422 cris_cc0_user_requires_cmp (rtx_insn *insn)
2423 {
2424 rtx_insn *cc0_user = NULL;
2425 rtx body;
2426 rtx set;
2427
2428 gcc_assert (insn != NULL);
2429
2430 if (!TARGET_V32)
2431 return false;
2432
2433 cc0_user = next_cc0_user (insn);
2434 if (cc0_user == NULL)
2435 return false;
2436
2437 body = PATTERN (cc0_user);
2438 set = single_set (cc0_user);
2439
2440 /* Users can be sCC and bCC. */
2441 if (JUMP_P (cc0_user)
2442 && GET_CODE (body) == SET
2443 && SET_DEST (body) == pc_rtx
2444 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
2445 && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx)
2446 {
2447 return
2448 GET_CODE (XEXP (SET_SRC (body), 0)) == GT
2449 || GET_CODE (XEXP (SET_SRC (body), 0)) == LE;
2450 }
2451 else if (set)
2452 {
2453 return
2454 GET_CODE (SET_SRC (body)) == GT
2455 || GET_CODE (SET_SRC (body)) == LE;
2456 }
2457
2458 gcc_unreachable ();
2459 }
2460
2461 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2462 does not handle the case where the IN operand is strict_low_part; it
2463 does handle it for X. Test-case in Axis-20010516. This function takes
2464 care of that for THIS port. FIXME: strict_low_part is going away
2465 anyway. */
2466
2467 static int
cris_reg_overlap_mentioned_p(rtx x,rtx in)2468 cris_reg_overlap_mentioned_p (rtx x, rtx in)
2469 {
2470 /* The function reg_overlap_mentioned now handles when X is
2471 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2472 if (GET_CODE (in) == STRICT_LOW_PART)
2473 in = XEXP (in, 0);
2474
2475 return reg_overlap_mentioned_p (x, in);
2476 }
2477
2478 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2479 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2480 elsewhere. */
2481
2482 bool
cris_valid_pic_const(const_rtx x,bool any_operand)2483 cris_valid_pic_const (const_rtx x, bool any_operand)
2484 {
2485 gcc_assert (flag_pic);
2486
2487 switch (GET_CODE (x))
2488 {
2489 case CONST_INT:
2490 case CONST_DOUBLE:
2491 return true;
2492 default:
2493 ;
2494 }
2495
2496 if (GET_CODE (x) != CONST)
2497 return false;
2498
2499 x = XEXP (x, 0);
2500
2501 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2502 if (GET_CODE (x) == PLUS
2503 && GET_CODE (XEXP (x, 0)) == UNSPEC
2504 && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL
2505 || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL)
2506 && CONST_INT_P (XEXP (x, 1)))
2507 x = XEXP (x, 0);
2508
2509 if (GET_CODE (x) == UNSPEC)
2510 switch (XINT (x, 1))
2511 {
2512 /* A PCREL operand is only valid for call and movsi. */
2513 case CRIS_UNSPEC_PLT_PCREL:
2514 case CRIS_UNSPEC_PCREL:
2515 return !any_operand;
2516
2517 case CRIS_UNSPEC_PLT_GOTREL:
2518 case CRIS_UNSPEC_PLTGOTREAD:
2519 case CRIS_UNSPEC_GOTREAD:
2520 case CRIS_UNSPEC_GOTREL:
2521 return true;
2522 default:
2523 gcc_unreachable ();
2524 }
2525
2526 return cris_symbol_type_of (x) == cris_no_symbol;
2527 }
2528
2529 /* Helper function to find the right symbol-type to generate,
2530 given the original (non-PIC) representation. */
2531
2532 enum cris_symbol_type
cris_symbol_type_of(const_rtx x)2533 cris_symbol_type_of (const_rtx x)
2534 {
2535 switch (GET_CODE (x))
2536 {
2537 case SYMBOL_REF:
2538 return flag_pic
2539 ? (SYMBOL_REF_LOCAL_P (x)
2540 ? cris_rel_symbol : cris_got_symbol)
2541 : cris_offsettable_symbol;
2542
2543 case LABEL_REF:
2544 return flag_pic ? cris_rel_symbol : cris_offsettable_symbol;
2545
2546 case CONST:
2547 return cris_symbol_type_of (XEXP (x, 0));
2548
2549 case PLUS:
2550 case MINUS:
2551 {
2552 enum cris_symbol_type t1 = cris_symbol_type_of (XEXP (x, 0));
2553 enum cris_symbol_type t2 = cris_symbol_type_of (XEXP (x, 1));
2554
2555 gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol);
2556
2557 if (t1 == cris_got_symbol || t2 == cris_got_symbol)
2558 return cris_got_symbol_needing_fixup;
2559
2560 return t1 != cris_no_symbol ? t1 : t2;
2561 }
2562
2563 case CONST_INT:
2564 case CONST_DOUBLE:
2565 return cris_no_symbol;
2566
2567 case UNSPEC:
2568 return cris_unspec;
2569
2570 default:
2571 fatal_insn ("unrecognized supposed constant", x);
2572 }
2573
2574 gcc_unreachable ();
2575 }
2576
2577 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2578
2579 int
cris_legitimate_pic_operand(rtx x)2580 cris_legitimate_pic_operand (rtx x)
2581 {
2582 /* Symbols are not valid PIC operands as-is; just constants. */
2583 return cris_valid_pic_const (x, true);
2584 }
2585
2586 /* Queue an .ident string in the queue of top-level asm statements.
2587 If the front-end is done, we must be being called from toplev.c.
2588 In that case, do nothing. */
2589 void
cris_asm_output_ident(const char * string)2590 cris_asm_output_ident (const char *string)
2591 {
2592 if (symtab->state != PARSING)
2593 return;
2594
2595 default_asm_output_ident_directive (string);
2596 }
2597
2598 /* The ASM_OUTPUT_CASE_END worker. */
2599
2600 void
cris_asm_output_case_end(FILE * stream,int num,rtx_insn * table)2601 cris_asm_output_case_end (FILE *stream, int num, rtx_insn *table)
2602 {
2603 /* Step back, over the label for the table, to the actual casejump and
2604 assert that we find only what's expected. */
2605 rtx_insn *whole_jump_insn = prev_nonnote_nondebug_insn (table);
2606 gcc_assert (whole_jump_insn != NULL_RTX && LABEL_P (whole_jump_insn));
2607 whole_jump_insn = prev_nonnote_nondebug_insn (whole_jump_insn);
2608 gcc_assert (whole_jump_insn != NULL_RTX
2609 && (JUMP_P (whole_jump_insn)
2610 || (TARGET_V32 && INSN_P (whole_jump_insn)
2611 && GET_CODE (PATTERN (whole_jump_insn)) == SEQUENCE)));
2612 /* Get the pattern of the casejump, so we can extract the default label. */
2613 rtx whole_jump_pat = PATTERN (whole_jump_insn);
2614
2615 if (TARGET_V32)
2616 {
2617 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2618 filled. We also output the offset word a little differently. */
2619 rtx parallel_jump
2620 = (GET_CODE (whole_jump_pat) == SEQUENCE
2621 ? PATTERN (XVECEXP (whole_jump_pat, 0, 0)) : whole_jump_pat);
2622
2623 asm_fprintf (stream,
2624 "\t.word %LL%d-.%s\n",
2625 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2626 (parallel_jump, 0, 0),
2627 1), 2), 0)),
2628 (TARGET_PDEBUG ? "; default" : ""));
2629 return;
2630 }
2631
2632 asm_fprintf (stream,
2633 "\t.word %LL%d-%LL%d%s\n",
2634 CODE_LABEL_NUMBER (XEXP
2635 (XEXP
2636 (XEXP (XVECEXP (whole_jump_pat, 0, 0), 1),
2637 2), 0)),
2638 num,
2639 (TARGET_PDEBUG ? "; default" : ""));
2640 }
2641
2642 /* The TARGET_OPTION_OVERRIDE worker.
2643 As is the norm, this also parses -mfoo=bar type parameters. */
2644
2645 static void
cris_option_override(void)2646 cris_option_override (void)
2647 {
2648 if (cris_max_stackframe_str)
2649 {
2650 cris_max_stackframe = atoi (cris_max_stackframe_str);
2651
2652 /* Do some sanity checking. */
2653 if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000)
2654 internal_error ("%<-max-stackframe=%d%> is not usable, "
2655 "not between 0 and %d",
2656 cris_max_stackframe, 0x20000000);
2657 }
2658
2659 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2660 if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO)
2661 cris_cpu_version = CRIS_CPU_SVINTO;
2662 else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4)
2663 cris_cpu_version = CRIS_CPU_ETRAX4;
2664
2665 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2666 if (cris_cpu_str)
2667 {
2668 cris_cpu_version
2669 = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1);
2670
2671 if (strcmp ("etrax4", cris_cpu_str) == 0)
2672 cris_cpu_version = 3;
2673
2674 if (strcmp ("svinto", cris_cpu_str) == 0
2675 || strcmp ("etrax100", cris_cpu_str) == 0)
2676 cris_cpu_version = 8;
2677
2678 if (strcmp ("ng", cris_cpu_str) == 0
2679 || strcmp ("etrax100lx", cris_cpu_str) == 0)
2680 cris_cpu_version = 10;
2681
2682 if (cris_cpu_version < 0 || cris_cpu_version > 32)
2683 error ("unknown CRIS version specification in %<-march=%> or "
2684 "%<-mcpu=%> : %s", cris_cpu_str);
2685
2686 /* Set the target flags. */
2687 if (cris_cpu_version >= CRIS_CPU_ETRAX4)
2688 target_flags |= MASK_ETRAX4_ADD;
2689
2690 /* If this is Svinto or higher, align for 32 bit accesses. */
2691 if (cris_cpu_version >= CRIS_CPU_SVINTO)
2692 target_flags
2693 |= (MASK_SVINTO | MASK_ALIGN_BY_32
2694 | MASK_STACK_ALIGN | MASK_CONST_ALIGN
2695 | MASK_DATA_ALIGN);
2696
2697 /* Note that we do not add new flags when it can be completely
2698 described with a macro that uses -mcpu=X. So
2699 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2700 }
2701
2702 if (cris_tune_str)
2703 {
2704 int cris_tune
2705 = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1);
2706
2707 if (strcmp ("etrax4", cris_tune_str) == 0)
2708 cris_tune = 3;
2709
2710 if (strcmp ("svinto", cris_tune_str) == 0
2711 || strcmp ("etrax100", cris_tune_str) == 0)
2712 cris_tune = 8;
2713
2714 if (strcmp ("ng", cris_tune_str) == 0
2715 || strcmp ("etrax100lx", cris_tune_str) == 0)
2716 cris_tune = 10;
2717
2718 if (cris_tune < 0 || cris_tune > 32)
2719 error ("unknown CRIS cpu version specification in %<-mtune=%> : %s",
2720 cris_tune_str);
2721
2722 if (cris_tune >= CRIS_CPU_SVINTO)
2723 /* We have currently nothing more to tune than alignment for
2724 memory accesses. */
2725 target_flags
2726 |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN
2727 | MASK_DATA_ALIGN | MASK_ALIGN_BY_32);
2728 }
2729
2730 if (cris_cpu_version >= CRIS_CPU_V32)
2731 target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG);
2732
2733 if (flag_pic)
2734 {
2735 /* Use error rather than warning, so invalid use is easily
2736 detectable. Still change to the values we expect, to avoid
2737 further errors. */
2738 if (! TARGET_LINUX)
2739 {
2740 error ("%<-fPIC%> and %<-fpic%> are not supported "
2741 "in this configuration");
2742 flag_pic = 0;
2743 }
2744
2745 /* Turn off function CSE. We need to have the addresses reach the
2746 call expanders to get PLT-marked, as they could otherwise be
2747 compared against zero directly or indirectly. After visiting the
2748 call expanders they will then be cse:ed, as the call expanders
2749 force_reg the addresses, effectively forcing flag_no_function_cse
2750 to 0. */
2751 flag_no_function_cse = 1;
2752 }
2753
2754 /* Set the per-function-data initializer. */
2755 init_machine_status = cris_init_machine_status;
2756 }
2757
2758 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2759
2760 static void
cris_asm_output_mi_thunk(FILE * stream,tree thunkdecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,tree funcdecl)2761 cris_asm_output_mi_thunk (FILE *stream,
2762 tree thunkdecl ATTRIBUTE_UNUSED,
2763 HOST_WIDE_INT delta,
2764 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2765 tree funcdecl)
2766 {
2767 /* Make sure unwind info is emitted for the thunk if needed. */
2768 final_start_function (emit_barrier (), stream, 1);
2769
2770 if (delta > 0)
2771 fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2772 ADDITIVE_SIZE_MODIFIER (delta), delta,
2773 reg_names[CRIS_FIRST_ARG_REG]);
2774 else if (delta < 0)
2775 fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2776 ADDITIVE_SIZE_MODIFIER (-delta), -delta,
2777 reg_names[CRIS_FIRST_ARG_REG]);
2778
2779 if (flag_pic)
2780 {
2781 const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0);
2782
2783 name = (* targetm.strip_name_encoding) (name);
2784
2785 if (TARGET_V32)
2786 {
2787 fprintf (stream, "\tba ");
2788 assemble_name (stream, name);
2789 fprintf (stream, "%s\n\tnop\n", CRIS_PLT_PCOFFSET_SUFFIX);
2790 }
2791 else
2792 {
2793 fprintf (stream, "\tadd.d ");
2794 assemble_name (stream, name);
2795 fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX);
2796 }
2797 }
2798 else
2799 {
2800 fprintf (stream, "\tjump ");
2801 assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0));
2802 fprintf (stream, "\n");
2803
2804 if (TARGET_V32)
2805 fprintf (stream, "\tnop\n");
2806 }
2807
2808 final_end_function ();
2809 }
2810
2811 /* Boilerplate emitted at start of file.
2812
2813 NO_APP *only at file start* means faster assembly. It also means
2814 comments are not allowed. In some cases comments will be output
2815 for debugging purposes. Make sure they are allowed then. */
2816 static void
cris_file_start(void)2817 cris_file_start (void)
2818 {
2819 /* These expressions can vary at run time, so we cannot put
2820 them into TARGET_INITIALIZER. */
2821 targetm.asm_file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name);
2822
2823 default_file_start ();
2824 }
2825
2826 /* Output that goes at the end of the file, similarly. */
2827
2828 static void
cris_file_end(void)2829 cris_file_end (void)
2830 {
2831 /* For CRIS, the default is to assume *no* executable stack, so output
2832 an executable-stack-note only when needed. */
2833 if (TARGET_LINUX && trampolines_created)
2834 file_end_indicate_exec_stack ();
2835 }
2836
2837 /* Rename the function calls for integer multiply and divide. */
2838 static void
cris_init_libfuncs(void)2839 cris_init_libfuncs (void)
2840 {
2841 set_optab_libfunc (smul_optab, SImode, "__Mul");
2842 set_optab_libfunc (sdiv_optab, SImode, "__Div");
2843 set_optab_libfunc (udiv_optab, SImode, "__Udiv");
2844 set_optab_libfunc (smod_optab, SImode, "__Mod");
2845 set_optab_libfunc (umod_optab, SImode, "__Umod");
2846
2847 /* Atomic data being unaligned is unfortunately a reality.
2848 Deal with it. */
2849 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS)
2850 {
2851 set_optab_libfunc (sync_compare_and_swap_optab, SImode,
2852 "__cris_atcmpxchgr32");
2853 set_optab_libfunc (sync_compare_and_swap_optab, HImode,
2854 "__cris_atcmpxchgr16");
2855 }
2856 }
2857
2858 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2859 mark functions. */
2860
2861 void
cris_init_expanders(void)2862 cris_init_expanders (void)
2863 {
2864 /* Nothing here at the moment. */
2865 }
2866
2867 /* Zero initialization is OK for all current fields. */
2868
2869 static struct machine_function *
cris_init_machine_status(void)2870 cris_init_machine_status (void)
2871 {
2872 return ggc_cleared_alloc<machine_function> ();
2873 }
2874
2875 /* Split a 2 word move (DI or presumably DF) into component parts.
2876 Originally a copy of gen_split_move_double in m32r.c. */
2877
2878 rtx
cris_split_movdx(rtx * operands)2879 cris_split_movdx (rtx *operands)
2880 {
2881 machine_mode mode = GET_MODE (operands[0]);
2882 rtx dest = operands[0];
2883 rtx src = operands[1];
2884 rtx val;
2885
2886 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2887 longer happen; after reload there are no SUBREGs any more, and we're
2888 only called after reload. */
2889 CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
2890
2891 start_sequence ();
2892 if (REG_P (dest))
2893 {
2894 int dregno = REGNO (dest);
2895
2896 /* Reg-to-reg copy. */
2897 if (REG_P (src))
2898 {
2899 int sregno = REGNO (src);
2900
2901 int reverse = (dregno == sregno + 1);
2902
2903 /* We normally copy the low-numbered register first. However, if
2904 the first register operand 0 is the same as the second register of
2905 operand 1, we must copy in the opposite order. */
2906 emit_insn (gen_rtx_SET (operand_subword (dest, reverse, TRUE, mode),
2907 operand_subword (src, reverse, TRUE, mode)));
2908
2909 emit_insn (gen_rtx_SET (operand_subword (dest, !reverse, TRUE, mode),
2910 operand_subword (src, !reverse, TRUE, mode)));
2911 }
2912 /* Constant-to-reg copy. */
2913 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
2914 {
2915 rtx words[2];
2916 split_double (src, &words[0], &words[1]);
2917 emit_insn (gen_rtx_SET (operand_subword (dest, 0, TRUE, mode),
2918 words[0]));
2919
2920 emit_insn (gen_rtx_SET (operand_subword (dest, 1, TRUE, mode),
2921 words[1]));
2922 }
2923 /* Mem-to-reg copy. */
2924 else if (MEM_P (src))
2925 {
2926 /* If the high-address word is used in the address, we must load it
2927 last. Otherwise, load it first. */
2928 rtx addr = XEXP (src, 0);
2929 int reverse = (refers_to_regno_p (dregno, addr) != 0);
2930
2931 /* The original code implies that we can't do
2932 move.x [rN+],rM move.x [rN],rM+1
2933 when rN is dead, because of REG_NOTES damage. That is
2934 consistent with what I've seen, so don't try it.
2935
2936 We have two different cases here; if the addr is POST_INC,
2937 just pass it through, otherwise add constants. */
2938
2939 if (GET_CODE (addr) == POST_INC)
2940 {
2941 rtx mem;
2942 rtx insn;
2943
2944 /* Whenever we emit insns with post-incremented
2945 addresses ourselves, we must add a post-inc note
2946 manually. */
2947 mem = change_address (src, SImode, addr);
2948 insn
2949 = gen_rtx_SET (operand_subword (dest, 0, TRUE, mode), mem);
2950 insn = emit_insn (insn);
2951 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2952 REG_NOTES (insn)
2953 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2954 REG_NOTES (insn));
2955
2956 mem = copy_rtx (mem);
2957 insn
2958 = gen_rtx_SET (operand_subword (dest, 1, TRUE, mode), mem);
2959 insn = emit_insn (insn);
2960 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2961 REG_NOTES (insn)
2962 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2963 REG_NOTES (insn));
2964 }
2965 else
2966 {
2967 /* Make sure we don't get any other addresses with
2968 embedded postincrements. They should be stopped in
2969 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2970 safety. */
2971 if (side_effects_p (addr))
2972 fatal_insn ("unexpected side-effects in address", addr);
2973
2974 emit_insn (gen_rtx_SET
2975 (operand_subword (dest, reverse, TRUE, mode),
2976 change_address
2977 (src, SImode,
2978 plus_constant (Pmode, addr,
2979 reverse * UNITS_PER_WORD))));
2980 emit_insn (gen_rtx_SET
2981 (operand_subword (dest, ! reverse, TRUE, mode),
2982 change_address
2983 (src, SImode,
2984 plus_constant (Pmode, addr,
2985 (! reverse) *
2986 UNITS_PER_WORD))));
2987 }
2988 }
2989 else
2990 internal_error ("unknown src");
2991 }
2992 /* Reg-to-mem copy or clear mem. */
2993 else if (MEM_P (dest)
2994 && (REG_P (src)
2995 || src == const0_rtx
2996 || src == CONST0_RTX (DFmode)))
2997 {
2998 rtx addr = XEXP (dest, 0);
2999
3000 if (GET_CODE (addr) == POST_INC)
3001 {
3002 rtx mem;
3003 rtx insn;
3004
3005 /* Whenever we emit insns with post-incremented addresses
3006 ourselves, we must add a post-inc note manually. */
3007 mem = change_address (dest, SImode, addr);
3008 insn
3009 = gen_rtx_SET (mem, operand_subword (src, 0, TRUE, mode));
3010 insn = emit_insn (insn);
3011 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
3012 REG_NOTES (insn)
3013 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
3014 REG_NOTES (insn));
3015
3016 mem = copy_rtx (mem);
3017 insn = gen_rtx_SET (mem, operand_subword (src, 1, TRUE, mode));
3018 insn = emit_insn (insn);
3019 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
3020 REG_NOTES (insn)
3021 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
3022 REG_NOTES (insn));
3023 }
3024 else
3025 {
3026 /* Make sure we don't get any other addresses with embedded
3027 postincrements. They should be stopped in
3028 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
3029 if (side_effects_p (addr))
3030 fatal_insn ("unexpected side-effects in address", addr);
3031
3032 emit_insn (gen_rtx_SET
3033 (change_address (dest, SImode, addr),
3034 operand_subword (src, 0, TRUE, mode)));
3035
3036 emit_insn (gen_rtx_SET
3037 (change_address (dest, SImode,
3038 plus_constant (Pmode, addr,
3039 UNITS_PER_WORD)),
3040 operand_subword (src, 1, TRUE, mode)));
3041 }
3042 }
3043
3044 else
3045 internal_error ("unknown dest");
3046
3047 val = get_insns ();
3048 end_sequence ();
3049 return val;
3050 }
3051
3052 /* The expander for the prologue pattern name. */
3053
3054 void
cris_expand_prologue(void)3055 cris_expand_prologue (void)
3056 {
3057 int regno;
3058 int size = get_frame_size ();
3059 /* Shorten the used name for readability. */
3060 int cfoa_size = crtl->outgoing_args_size;
3061 int last_movem_reg = -1;
3062 int framesize = 0;
3063 rtx mem, insn;
3064 int return_address_on_stack = cris_return_address_on_stack ();
3065 int got_really_used = false;
3066 int n_movem_regs = 0;
3067 int pretend = crtl->args.pretend_args_size;
3068
3069 /* Don't do anything if no prologues or epilogues are wanted. */
3070 if (!TARGET_PROLOGUE_EPILOGUE)
3071 return;
3072
3073 CRIS_ASSERT (size >= 0);
3074
3075 if (crtl->uses_pic_offset_table)
3076 {
3077 /* A reference may have been optimized out (like the abort () in
3078 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3079 it's still used. */
3080 push_topmost_sequence ();
3081 got_really_used
3082 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL);
3083 pop_topmost_sequence ();
3084 }
3085
3086 /* Align the size to what's best for the CPU model. */
3087 if (TARGET_STACK_ALIGN)
3088 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
3089
3090 if (pretend)
3091 {
3092 /* See also cris_setup_incoming_varargs where
3093 cfun->machine->stdarg_regs is set. There are other setters of
3094 crtl->args.pretend_args_size than stdarg handling, like
3095 for an argument passed with parts in R13 and stack. We must
3096 not store R13 into the pretend-area for that case, as GCC does
3097 that itself. "Our" store would be marked as redundant and GCC
3098 will attempt to remove it, which will then be flagged as an
3099 internal error; trying to remove a frame-related insn. */
3100 int stdarg_regs = cfun->machine->stdarg_regs;
3101
3102 framesize += pretend;
3103
3104 for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1;
3105 stdarg_regs > 0;
3106 regno--, pretend -= 4, stdarg_regs--)
3107 {
3108 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3109 plus_constant (Pmode,
3110 stack_pointer_rtx,
3111 -4)));
3112 /* FIXME: When dwarf2 frame output and unless asynchronous
3113 exceptions, make dwarf2 bundle together all stack
3114 adjustments like it does for registers between stack
3115 adjustments. */
3116 RTX_FRAME_RELATED_P (insn) = 1;
3117
3118 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3119 set_mem_alias_set (mem, get_varargs_alias_set ());
3120 insn = emit_move_insn (mem, gen_raw_REG (SImode, regno));
3121
3122 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3123 the value isn't restored, so we don't want to tell dwarf2
3124 that it's been stored to stack, else EH handling info would
3125 get confused. */
3126 }
3127
3128 /* For other setters of crtl->args.pretend_args_size, we
3129 just adjust the stack by leaving the remaining size in
3130 "pretend", handled below. */
3131 }
3132
3133 /* Save SRP if not a leaf function. */
3134 if (return_address_on_stack)
3135 {
3136 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3137 plus_constant (Pmode, stack_pointer_rtx,
3138 -4 - pretend)));
3139 pretend = 0;
3140 RTX_FRAME_RELATED_P (insn) = 1;
3141
3142 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3143 set_mem_alias_set (mem, get_frame_alias_set ());
3144 insn = emit_move_insn (mem, gen_raw_REG (SImode, CRIS_SRP_REGNUM));
3145 RTX_FRAME_RELATED_P (insn) = 1;
3146 framesize += 4;
3147 }
3148
3149 /* Set up the frame pointer, if needed. */
3150 if (frame_pointer_needed)
3151 {
3152 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3153 plus_constant (Pmode, stack_pointer_rtx,
3154 -4 - pretend)));
3155 pretend = 0;
3156 RTX_FRAME_RELATED_P (insn) = 1;
3157
3158 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3159 set_mem_alias_set (mem, get_frame_alias_set ());
3160 insn = emit_move_insn (mem, frame_pointer_rtx);
3161 RTX_FRAME_RELATED_P (insn) = 1;
3162
3163 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3164 RTX_FRAME_RELATED_P (insn) = 1;
3165
3166 framesize += 4;
3167 }
3168
3169 /* Between frame-pointer and saved registers lie the area for local
3170 variables. If we get here with "pretended" size remaining, count
3171 it into the general stack size. */
3172 size += pretend;
3173
3174 /* Get a contiguous sequence of registers, starting with R0, that need
3175 to be saved. */
3176 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
3177 {
3178 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3179 {
3180 n_movem_regs++;
3181
3182 /* Check if movem may be used for registers so far. */
3183 if (regno == last_movem_reg + 1)
3184 /* Yes, update next expected register. */
3185 last_movem_reg = regno;
3186 else
3187 {
3188 /* We cannot use movem for all registers. We have to flush
3189 any movem:ed registers we got so far. */
3190 if (last_movem_reg != -1)
3191 {
3192 int n_saved
3193 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
3194
3195 /* It is a win to use a side-effect assignment for
3196 64 <= size <= 128. But side-effect on movem was
3197 not usable for CRIS v0..3. Also only do it if
3198 side-effects insns are allowed. */
3199 if ((last_movem_reg + 1) * 4 + size >= 64
3200 && (last_movem_reg + 1) * 4 + size <= 128
3201 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
3202 && TARGET_SIDE_EFFECT_PREFIXES)
3203 {
3204 mem
3205 = gen_rtx_MEM (SImode,
3206 plus_constant (Pmode, stack_pointer_rtx,
3207 -(n_saved * 4 + size)));
3208 set_mem_alias_set (mem, get_frame_alias_set ());
3209 insn
3210 = cris_emit_movem_store (mem, GEN_INT (n_saved),
3211 -(n_saved * 4 + size),
3212 true);
3213 }
3214 else
3215 {
3216 insn
3217 = gen_rtx_SET (stack_pointer_rtx,
3218 plus_constant (Pmode, stack_pointer_rtx,
3219 -(n_saved * 4 + size)));
3220 insn = emit_insn (insn);
3221 RTX_FRAME_RELATED_P (insn) = 1;
3222
3223 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3224 set_mem_alias_set (mem, get_frame_alias_set ());
3225 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
3226 0, true);
3227 }
3228
3229 framesize += n_saved * 4 + size;
3230 last_movem_reg = -1;
3231 size = 0;
3232 }
3233
3234 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3235 plus_constant (Pmode,
3236 stack_pointer_rtx,
3237 -4 - size)));
3238 RTX_FRAME_RELATED_P (insn) = 1;
3239
3240 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3241 set_mem_alias_set (mem, get_frame_alias_set ());
3242 insn = emit_move_insn (mem, gen_raw_REG (SImode, regno));
3243 RTX_FRAME_RELATED_P (insn) = 1;
3244
3245 framesize += 4 + size;
3246 size = 0;
3247 }
3248 }
3249 }
3250
3251 /* Check after, if we could movem all registers. This is the normal case. */
3252 if (last_movem_reg != -1)
3253 {
3254 int n_saved
3255 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
3256
3257 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3258 do it if side-effects insns are allowed. */
3259 if ((last_movem_reg + 1) * 4 + size >= 64
3260 && (last_movem_reg + 1) * 4 + size <= 128
3261 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
3262 && TARGET_SIDE_EFFECT_PREFIXES)
3263 {
3264 mem
3265 = gen_rtx_MEM (SImode,
3266 plus_constant (Pmode, stack_pointer_rtx,
3267 -(n_saved * 4 + size)));
3268 set_mem_alias_set (mem, get_frame_alias_set ());
3269 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
3270 -(n_saved * 4 + size), true);
3271 }
3272 else
3273 {
3274 insn
3275 = gen_rtx_SET (stack_pointer_rtx,
3276 plus_constant (Pmode, stack_pointer_rtx,
3277 -(n_saved * 4 + size)));
3278 insn = emit_insn (insn);
3279 RTX_FRAME_RELATED_P (insn) = 1;
3280
3281 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3282 set_mem_alias_set (mem, get_frame_alias_set ());
3283 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true);
3284 }
3285
3286 framesize += n_saved * 4 + size;
3287 /* We have to put outgoing argument space after regs. */
3288 if (cfoa_size)
3289 {
3290 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3291 plus_constant (Pmode,
3292 stack_pointer_rtx,
3293 -cfoa_size)));
3294 RTX_FRAME_RELATED_P (insn) = 1;
3295 framesize += cfoa_size;
3296 }
3297 }
3298 else if ((size + cfoa_size) > 0)
3299 {
3300 insn = emit_insn (gen_rtx_SET (stack_pointer_rtx,
3301 plus_constant (Pmode,
3302 stack_pointer_rtx,
3303 -(cfoa_size + size))));
3304 RTX_FRAME_RELATED_P (insn) = 1;
3305 framesize += size + cfoa_size;
3306 }
3307
3308 /* Set up the PIC register, if it is used. */
3309 if (got_really_used)
3310 {
3311 rtx got
3312 = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT);
3313 emit_move_insn (pic_offset_table_rtx, got);
3314
3315 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3316 follow exceptional paths and tries to delete the GOT load as
3317 unused, if it isn't used on the non-exceptional paths. Other
3318 ports have similar or other cover-ups, or plain bugs marking
3319 the GOT register load as maybe-dead. To see this, remove the
3320 line below and try libsupc++/vec.cc or a trivial
3321 "static void y (); void x () {try {y ();} catch (...) {}}". */
3322 emit_use (pic_offset_table_rtx);
3323 }
3324
3325 if (cris_max_stackframe && framesize > cris_max_stackframe)
3326 warning (0, "stackframe too big: %d bytes", framesize);
3327 }
3328
3329 /* The expander for the epilogue pattern. */
3330
3331 void
cris_expand_epilogue(void)3332 cris_expand_epilogue (void)
3333 {
3334 int regno;
3335 int size = get_frame_size ();
3336 int last_movem_reg = -1;
3337 int argspace_offset = crtl->outgoing_args_size;
3338 int pretend = crtl->args.pretend_args_size;
3339 rtx mem;
3340 bool return_address_on_stack = cris_return_address_on_stack ();
3341 /* A reference may have been optimized out
3342 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3343 so check that it's still used. */
3344 int got_really_used = false;
3345 int n_movem_regs = 0;
3346
3347 if (!TARGET_PROLOGUE_EPILOGUE)
3348 return;
3349
3350 if (crtl->uses_pic_offset_table)
3351 {
3352 /* A reference may have been optimized out (like the abort () in
3353 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3354 it's still used. */
3355 push_topmost_sequence ();
3356 got_really_used
3357 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL);
3358 pop_topmost_sequence ();
3359 }
3360
3361 /* Align byte count of stack frame. */
3362 if (TARGET_STACK_ALIGN)
3363 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
3364
3365 /* Check how many saved regs we can movem. They start at r0 and must
3366 be contiguous. */
3367 for (regno = 0;
3368 regno < FIRST_PSEUDO_REGISTER;
3369 regno++)
3370 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3371 {
3372 n_movem_regs++;
3373
3374 if (regno == last_movem_reg + 1)
3375 last_movem_reg = regno;
3376 else
3377 break;
3378 }
3379
3380 /* If there was only one register that really needed to be saved
3381 through movem, don't use movem. */
3382 if (n_movem_regs == 1)
3383 last_movem_reg = -1;
3384
3385 /* Now emit "normal" move insns for all regs higher than the movem
3386 regs. */
3387 for (regno = FIRST_PSEUDO_REGISTER - 1;
3388 regno > last_movem_reg;
3389 regno--)
3390 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3391 {
3392 rtx insn;
3393
3394 if (argspace_offset)
3395 {
3396 /* There is an area for outgoing parameters located before
3397 the saved registers. We have to adjust for that. */
3398 emit_insn (gen_rtx_SET (stack_pointer_rtx,
3399 plus_constant (Pmode, stack_pointer_rtx,
3400 argspace_offset)));
3401 /* Make sure we only do this once. */
3402 argspace_offset = 0;
3403 }
3404
3405 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3406 stack_pointer_rtx));
3407 set_mem_alias_set (mem, get_frame_alias_set ());
3408 insn = emit_move_insn (gen_raw_REG (SImode, regno), mem);
3409
3410 /* Whenever we emit insns with post-incremented addresses
3411 ourselves, we must add a post-inc note manually. */
3412 REG_NOTES (insn)
3413 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3414 }
3415
3416 /* If we have any movem-restore, do it now. */
3417 if (last_movem_reg != -1)
3418 {
3419 rtx insn;
3420
3421 if (argspace_offset)
3422 {
3423 emit_insn (gen_rtx_SET (stack_pointer_rtx,
3424 plus_constant (Pmode, stack_pointer_rtx,
3425 argspace_offset)));
3426 argspace_offset = 0;
3427 }
3428
3429 mem = gen_rtx_MEM (SImode,
3430 gen_rtx_POST_INC (SImode, stack_pointer_rtx));
3431 set_mem_alias_set (mem, get_frame_alias_set ());
3432 insn
3433 = emit_insn (cris_gen_movem_load (mem,
3434 GEN_INT (last_movem_reg + 1), 0));
3435 /* Whenever we emit insns with post-incremented addresses
3436 ourselves, we must add a post-inc note manually. */
3437 if (side_effects_p (PATTERN (insn)))
3438 REG_NOTES (insn)
3439 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3440 }
3441
3442 /* If we don't clobber all of the allocated stack area (we've already
3443 deallocated saved registers), GCC might want to schedule loads from
3444 the stack to *after* the stack-pointer restore, which introduces an
3445 interrupt race condition. This happened for the initial-value
3446 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3447 other failure for that test). It also happened for the stack slot
3448 for the return value in (one version of)
3449 linux/fs/dcache.c:__d_lookup, at least with "-O2
3450 -fno-omit-frame-pointer". */
3451
3452 /* Restore frame pointer if necessary. */
3453 if (frame_pointer_needed)
3454 {
3455 rtx insn;
3456
3457 emit_insn (gen_cris_frame_deallocated_barrier ());
3458
3459 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
3460 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3461 stack_pointer_rtx));
3462 set_mem_alias_set (mem, get_frame_alias_set ());
3463 insn = emit_move_insn (frame_pointer_rtx, mem);
3464
3465 /* Whenever we emit insns with post-incremented addresses
3466 ourselves, we must add a post-inc note manually. */
3467 REG_NOTES (insn)
3468 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3469 }
3470 else if ((size + argspace_offset) != 0)
3471 {
3472 emit_insn (gen_cris_frame_deallocated_barrier ());
3473
3474 /* If there was no frame-pointer to restore sp from, we must
3475 explicitly deallocate local variables. */
3476
3477 /* Handle space for outgoing parameters that hasn't been handled
3478 yet. */
3479 size += argspace_offset;
3480
3481 emit_insn (gen_rtx_SET (stack_pointer_rtx,
3482 plus_constant (Pmode, stack_pointer_rtx, size)));
3483 }
3484
3485 /* If this function has no pushed register parameters
3486 (stdargs/varargs), and if it is not a leaf function, then we have
3487 the return address on the stack. */
3488 if (return_address_on_stack && pretend == 0)
3489 {
3490 if (TARGET_V32 || crtl->calls_eh_return)
3491 {
3492 rtx mem;
3493 rtx insn;
3494 rtx srpreg = gen_raw_REG (SImode, CRIS_SRP_REGNUM);
3495 mem = gen_rtx_MEM (SImode,
3496 gen_rtx_POST_INC (SImode,
3497 stack_pointer_rtx));
3498 set_mem_alias_set (mem, get_frame_alias_set ());
3499 insn = emit_move_insn (srpreg, mem);
3500
3501 /* Whenever we emit insns with post-incremented addresses
3502 ourselves, we must add a post-inc note manually. */
3503 REG_NOTES (insn)
3504 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3505
3506 if (crtl->calls_eh_return)
3507 emit_insn (gen_addsi3 (stack_pointer_rtx,
3508 stack_pointer_rtx,
3509 gen_raw_REG (SImode, CRIS_STACKADJ_REG)));
3510 cris_expand_return (false);
3511 }
3512 else
3513 cris_expand_return (true);
3514
3515 return;
3516 }
3517
3518 /* If we pushed some register parameters, then adjust the stack for
3519 them. */
3520 if (pretend != 0)
3521 {
3522 /* If SRP is stored on the way, we need to restore it first. */
3523 if (return_address_on_stack)
3524 {
3525 rtx mem;
3526 rtx srpreg = gen_raw_REG (SImode, CRIS_SRP_REGNUM);
3527 rtx insn;
3528
3529 mem = gen_rtx_MEM (SImode,
3530 gen_rtx_POST_INC (SImode,
3531 stack_pointer_rtx));
3532 set_mem_alias_set (mem, get_frame_alias_set ());
3533 insn = emit_move_insn (srpreg, mem);
3534
3535 /* Whenever we emit insns with post-incremented addresses
3536 ourselves, we must add a post-inc note manually. */
3537 REG_NOTES (insn)
3538 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3539 }
3540
3541 emit_insn (gen_rtx_SET (stack_pointer_rtx,
3542 plus_constant (Pmode, stack_pointer_rtx,
3543 pretend)));
3544 }
3545
3546 /* Perform the "physical" unwinding that the EH machinery calculated. */
3547 if (crtl->calls_eh_return)
3548 emit_insn (gen_addsi3 (stack_pointer_rtx,
3549 stack_pointer_rtx,
3550 gen_raw_REG (SImode, CRIS_STACKADJ_REG)));
3551 cris_expand_return (false);
3552 }
3553
3554 /* Worker function for generating movem from mem for load_multiple. */
3555
3556 rtx
cris_gen_movem_load(rtx src,rtx nregs_rtx,int nprefix)3557 cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix)
3558 {
3559 int nregs = INTVAL (nregs_rtx);
3560 rtvec vec;
3561 int eltno = 1;
3562 int i;
3563 rtx srcreg = XEXP (src, 0);
3564 unsigned int regno = nregs - 1;
3565 int regno_inc = -1;
3566
3567 if (TARGET_V32)
3568 {
3569 regno = 0;
3570 regno_inc = 1;
3571 }
3572
3573 if (GET_CODE (srcreg) == POST_INC)
3574 srcreg = XEXP (srcreg, 0);
3575
3576 CRIS_ASSERT (REG_P (srcreg));
3577
3578 /* Don't use movem for just one insn. The insns are equivalent except
3579 for the pipeline hazard (on v32); movem does not forward the loaded
3580 registers so there's a three cycles penalty for their use. */
3581 if (nregs == 1)
3582 return gen_movsi (gen_rtx_REG (SImode, 0), src);
3583
3584 vec = rtvec_alloc (nprefix + nregs
3585 + (GET_CODE (XEXP (src, 0)) == POST_INC));
3586
3587 if (GET_CODE (XEXP (src, 0)) == POST_INC)
3588 {
3589 RTVEC_ELT (vec, nprefix + 1)
3590 = gen_rtx_SET (srcreg, plus_constant (Pmode, srcreg, nregs * 4));
3591 eltno++;
3592 }
3593
3594 src = replace_equiv_address (src, srcreg);
3595 RTVEC_ELT (vec, nprefix)
3596 = gen_rtx_SET (gen_rtx_REG (SImode, regno), src);
3597 regno += regno_inc;
3598
3599 for (i = 1; i < nregs; i++, eltno++)
3600 {
3601 RTVEC_ELT (vec, nprefix + eltno)
3602 = gen_rtx_SET (gen_rtx_REG (SImode, regno),
3603 adjust_address_nv (src, SImode, i * 4));
3604 regno += regno_inc;
3605 }
3606
3607 return gen_rtx_PARALLEL (VOIDmode, vec);
3608 }
3609
3610 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3611 are added that the dwarf2 machinery understands. */
3612
3613 rtx
cris_emit_movem_store(rtx dest,rtx nregs_rtx,int increment,bool frame_related)3614 cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment,
3615 bool frame_related)
3616 {
3617 int nregs = INTVAL (nregs_rtx);
3618 rtvec vec;
3619 int eltno = 1;
3620 int i;
3621 rtx insn;
3622 rtx destreg = XEXP (dest, 0);
3623 unsigned int regno = nregs - 1;
3624 int regno_inc = -1;
3625
3626 if (TARGET_V32)
3627 {
3628 regno = 0;
3629 regno_inc = 1;
3630 }
3631
3632 if (GET_CODE (destreg) == POST_INC)
3633 increment += nregs * 4;
3634
3635 if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS)
3636 destreg = XEXP (destreg, 0);
3637
3638 CRIS_ASSERT (REG_P (destreg));
3639
3640 /* Don't use movem for just one insn. The insns are equivalent except
3641 for the pipeline hazard (on v32); movem does not forward the loaded
3642 registers so there's a three cycles penalty for use. */
3643 if (nregs == 1)
3644 {
3645 rtx mov = gen_rtx_SET (dest, gen_rtx_REG (SImode, 0));
3646
3647 if (increment == 0)
3648 {
3649 insn = emit_insn (mov);
3650 if (frame_related)
3651 RTX_FRAME_RELATED_P (insn) = 1;
3652 return insn;
3653 }
3654
3655 /* If there was a request for a side-effect, create the ordinary
3656 parallel. */
3657 vec = rtvec_alloc (2);
3658
3659 RTVEC_ELT (vec, 0) = mov;
3660 RTVEC_ELT (vec, 1) = gen_rtx_SET (destreg, plus_constant (Pmode, destreg,
3661 increment));
3662 if (frame_related)
3663 {
3664 RTX_FRAME_RELATED_P (mov) = 1;
3665 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3666 }
3667 }
3668 else
3669 {
3670 vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0));
3671 RTVEC_ELT (vec, 0)
3672 = gen_rtx_SET (replace_equiv_address (dest,
3673 plus_constant (Pmode, destreg,
3674 increment)),
3675 gen_rtx_REG (SImode, regno));
3676 regno += regno_inc;
3677
3678 /* The dwarf2 info wants this mark on each component in a parallel
3679 that's part of the prologue (though it's optional on the first
3680 component). */
3681 if (frame_related)
3682 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1;
3683
3684 if (increment != 0)
3685 {
3686 RTVEC_ELT (vec, 1)
3687 = gen_rtx_SET (destreg, plus_constant (Pmode, destreg,
3688 increment != 0
3689 ? increment : nregs * 4));
3690 eltno++;
3691
3692 if (frame_related)
3693 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3694
3695 /* Don't call adjust_address_nv on a post-incremented address if
3696 we can help it. */
3697 if (GET_CODE (XEXP (dest, 0)) == POST_INC)
3698 dest = replace_equiv_address (dest, destreg);
3699 }
3700
3701 for (i = 1; i < nregs; i++, eltno++)
3702 {
3703 RTVEC_ELT (vec, eltno)
3704 = gen_rtx_SET (adjust_address_nv (dest, SImode, i * 4),
3705 gen_rtx_REG (SImode, regno));
3706 if (frame_related)
3707 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1;
3708 regno += regno_inc;
3709 }
3710 }
3711
3712 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
3713
3714 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3715 we need to keep the stack adjustment separate, after the
3716 MEM-setters. Else the stack-adjustment in the second component of
3717 the parallel would be mishandled; the offsets for the SETs that
3718 follow it would be wrong. We prepare for this by adding a
3719 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3720 followed by the increment. Note that we have FRAME_RELATED_P on
3721 all the SETs, including the original stack adjustment SET in the
3722 parallel. */
3723 if (frame_related)
3724 {
3725 if (increment != 0)
3726 {
3727 rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1));
3728 XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0));
3729 for (i = 1; i < nregs; i++)
3730 XVECEXP (seq, 0, i)
3731 = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1));
3732 XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1));
3733 add_reg_note (insn, REG_FRAME_RELATED_EXPR, seq);
3734 }
3735
3736 RTX_FRAME_RELATED_P (insn) = 1;
3737 }
3738
3739 return insn;
3740 }
3741
3742 /* Worker function for expanding the address for PIC function calls. */
3743
3744 void
cris_expand_pic_call_address(rtx * opp,rtx * markerp)3745 cris_expand_pic_call_address (rtx *opp, rtx *markerp)
3746 {
3747 rtx op = *opp;
3748
3749 gcc_assert (flag_pic && MEM_P (op));
3750 op = XEXP (op, 0);
3751
3752 /* It might be that code can be generated that jumps to 0 (or to a
3753 specific address). Don't die on that. (There is a
3754 testcase.) */
3755 if (CONSTANT_P (op) && !CONST_INT_P (op))
3756 {
3757 enum cris_symbol_type t = cris_symbol_type_of (op);
3758
3759 CRIS_ASSERT (can_create_pseudo_p ());
3760
3761 /* For local symbols (non-PLT), just get the plain symbol
3762 reference into a register. For symbols that can be PLT, make
3763 them PLT. */
3764 if (t == cris_rel_symbol)
3765 {
3766 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3767 into a register caused performance regression for 3.2.1,
3768 observable in __floatdidf and elsewhere in libgcc. */
3769 if (TARGET_V32)
3770 {
3771 rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op);
3772 HOST_WIDE_INT offs = get_integer_term (op);
3773
3774 /* We can't get calls to sym+N, N integer, can we? */
3775 gcc_assert (offs == 0);
3776
3777 op = gen_rtx_CONST (Pmode,
3778 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
3779 CRIS_UNSPEC_PCREL));
3780 }
3781 else
3782 op = force_reg (Pmode, op);
3783
3784 /* A local call. */
3785 *markerp = const0_rtx;
3786 }
3787 else if (t == cris_got_symbol)
3788 {
3789 if (TARGET_AVOID_GOTPLT)
3790 {
3791 /* Change a "jsr sym" into (allocate register rM, rO)
3792 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM"
3793 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3794 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))"
3795 for v32. */
3796 rtx tem, rm, ro;
3797
3798 crtl->uses_pic_offset_table = 1;
3799 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3800 TARGET_V32
3801 ? CRIS_UNSPEC_PLT_PCREL
3802 : CRIS_UNSPEC_PLT_GOTREL);
3803 tem = gen_rtx_CONST (Pmode, tem);
3804 if (TARGET_V32)
3805 op = tem;
3806 else
3807 {
3808 rm = gen_reg_rtx (Pmode);
3809 emit_move_insn (rm, tem);
3810 ro = gen_reg_rtx (Pmode);
3811 if (expand_binop (Pmode, add_optab, rm,
3812 pic_offset_table_rtx,
3813 ro, 0, OPTAB_LIB_WIDEN) != ro)
3814 internal_error ("expand_binop failed in movsi got");
3815 op = ro;
3816 }
3817 }
3818 else
3819 {
3820 /* Change a "jsr sym" into (allocate register rM, rO)
3821 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3822 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3823 marked as not trapping and not aliasing. No "move.d
3824 [rO],rP" as that would invite to re-use of a value
3825 that should not be reused. FIXME: Need a peephole2
3826 for cases when this is cse:d from the call, to change
3827 back to just get the PLT entry address, so we don't
3828 resolve the same symbol over and over (the memory
3829 access of the PLTGOT isn't constant). */
3830 rtx tem, mem, rm, ro;
3831
3832 gcc_assert (can_create_pseudo_p ());
3833 crtl->uses_pic_offset_table = 1;
3834 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3835 CRIS_UNSPEC_PLTGOTREAD);
3836 rm = gen_reg_rtx (Pmode);
3837 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3838 ro = gen_reg_rtx (Pmode);
3839 if (expand_binop (Pmode, add_optab, rm,
3840 pic_offset_table_rtx,
3841 ro, 0, OPTAB_LIB_WIDEN) != ro)
3842 internal_error ("expand_binop failed in movsi got");
3843 mem = gen_rtx_MEM (Pmode, ro);
3844
3845 /* This MEM doesn't alias anything. Whether it aliases
3846 other same symbols is unimportant. */
3847 set_mem_alias_set (mem, new_alias_set ());
3848 MEM_NOTRAP_P (mem) = 1;
3849 op = mem;
3850 }
3851
3852 /* We need to prepare this call to go through the PLT; we
3853 need to make GOT available. */
3854 *markerp = pic_offset_table_rtx;
3855 }
3856 else
3857 /* Can't possibly get anything else for a function-call, right? */
3858 fatal_insn ("unidentifiable call op", op);
3859
3860 /* If the validizing variant is called, it will try to validize
3861 the address as a valid any-operand constant, but as it's only
3862 valid for calls and moves, it will fail and always be forced
3863 into a register. */
3864 *opp = replace_equiv_address_nv (*opp, op);
3865 }
3866 else
3867 /* Can't tell what locality a call to a non-constant address has;
3868 better make the GOT register alive at it.
3869 FIXME: Can we see whether the register has known constant
3870 contents? */
3871 *markerp = pic_offset_table_rtx;
3872 }
3873
3874 /* Make sure operands are in the right order for an addsi3 insn as
3875 generated by a define_split. Nothing but REG_P as the first
3876 operand is recognized by addsi3 after reload. OPERANDS contains
3877 the operands, with the first at OPERANDS[N] and the second at
3878 OPERANDS[N+1]. */
3879
3880 void
cris_order_for_addsi3(rtx * operands,int n)3881 cris_order_for_addsi3 (rtx *operands, int n)
3882 {
3883 if (!REG_P (operands[n]))
3884 {
3885 rtx tem = operands[n];
3886 operands[n] = operands[n + 1];
3887 operands[n + 1] = tem;
3888 }
3889 }
3890
3891 /* Use from within code, from e.g. PRINT_OPERAND and
3892 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3893 different things depending on whether code operand or constant is
3894 emitted. */
3895
3896 static void
cris_output_addr_const(FILE * file,rtx x)3897 cris_output_addr_const (FILE *file, rtx x)
3898 {
3899 in_code++;
3900 output_addr_const (file, x);
3901 in_code--;
3902 }
3903
3904 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3905
3906 void
cris_asm_output_symbol_ref(FILE * file,rtx x)3907 cris_asm_output_symbol_ref (FILE *file, rtx x)
3908 {
3909 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3910
3911 if (flag_pic && in_code > 0)
3912 {
3913 const char *origstr = XSTR (x, 0);
3914 const char *str;
3915 str = (* targetm.strip_name_encoding) (origstr);
3916 assemble_name (file, str);
3917
3918 /* Sanity check. */
3919 if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3920 output_operand_lossage ("PIC register isn't set up");
3921 }
3922 else
3923 assemble_name (file, XSTR (x, 0));
3924 }
3925
3926 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3927
3928 void
cris_asm_output_label_ref(FILE * file,char * buf)3929 cris_asm_output_label_ref (FILE *file, char *buf)
3930 {
3931 if (flag_pic && in_code > 0)
3932 {
3933 assemble_name (file, buf);
3934
3935 /* Sanity check. */
3936 if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3937 internal_error ("emitting PIC operand, but PIC register "
3938 "isn%'t set up");
3939 }
3940 else
3941 assemble_name (file, buf);
3942 }
3943
3944 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3945
3946 static bool
cris_output_addr_const_extra(FILE * file,rtx xconst)3947 cris_output_addr_const_extra (FILE *file, rtx xconst)
3948 {
3949 switch (GET_CODE (xconst))
3950 {
3951 rtx x;
3952
3953 case UNSPEC:
3954 x = XVECEXP (xconst, 0, 0);
3955 CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
3956 || GET_CODE (x) == LABEL_REF
3957 || GET_CODE (x) == CONST);
3958 output_addr_const (file, x);
3959 switch (XINT (xconst, 1))
3960 {
3961 case CRIS_UNSPEC_PCREL:
3962 /* We only get this with -fpic/PIC to tell it apart from an
3963 invalid symbol. We can't tell here, but it should only
3964 be the operand of a call or movsi. */
3965 gcc_assert (TARGET_V32 && flag_pic);
3966 break;
3967
3968 case CRIS_UNSPEC_PLT_PCREL:
3969 gcc_assert (TARGET_V32);
3970 fprintf (file, ":PLT");
3971 break;
3972
3973 case CRIS_UNSPEC_PLT_GOTREL:
3974 gcc_assert (!TARGET_V32);
3975 fprintf (file, ":PLTG");
3976 break;
3977
3978 case CRIS_UNSPEC_GOTREL:
3979 gcc_assert (!TARGET_V32);
3980 fprintf (file, ":GOTOFF");
3981 break;
3982
3983 case CRIS_UNSPEC_GOTREAD:
3984 if (flag_pic == 1)
3985 fprintf (file, ":GOT16");
3986 else
3987 fprintf (file, ":GOT");
3988 break;
3989
3990 case CRIS_UNSPEC_PLTGOTREAD:
3991 if (flag_pic == 1)
3992 fprintf (file, CRIS_GOTPLT_SUFFIX "16");
3993 else
3994 fprintf (file, CRIS_GOTPLT_SUFFIX);
3995 break;
3996
3997 default:
3998 gcc_unreachable ();
3999 }
4000 return true;
4001
4002 default:
4003 return false;
4004 }
4005 }
4006
4007 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4008
4009 static rtx
cris_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED,int incoming ATTRIBUTE_UNUSED)4010 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
4011 int incoming ATTRIBUTE_UNUSED)
4012 {
4013 return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM);
4014 }
4015
4016 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4017
4018 static void
cris_setup_incoming_varargs(cumulative_args_t ca_v,machine_mode mode ATTRIBUTE_UNUSED,tree type ATTRIBUTE_UNUSED,int * pretend_arg_size,int second_time)4019 cris_setup_incoming_varargs (cumulative_args_t ca_v,
4020 machine_mode mode ATTRIBUTE_UNUSED,
4021 tree type ATTRIBUTE_UNUSED,
4022 int *pretend_arg_size,
4023 int second_time)
4024 {
4025 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
4026
4027 if (ca->regs < CRIS_MAX_ARGS_IN_REGS)
4028 {
4029 int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs;
4030 cfun->machine->stdarg_regs = stdarg_regs;
4031 *pretend_arg_size = stdarg_regs * 4;
4032 }
4033
4034 if (TARGET_PDEBUG)
4035 fprintf (asm_out_file,
4036 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
4037 ca->regs, *pretend_arg_size, second_time);
4038 }
4039
4040 /* Return true if TYPE must be passed by invisible reference.
4041 For cris, we pass <= 8 bytes by value, others by reference. */
4042
4043 static bool
cris_pass_by_reference(cumulative_args_t ca ATTRIBUTE_UNUSED,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)4044 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
4045 machine_mode mode, const_tree type,
4046 bool named ATTRIBUTE_UNUSED)
4047 {
4048 return (targetm.calls.must_pass_in_stack (mode, type)
4049 || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8);
4050 }
4051
4052 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4053 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4054 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4055
4056 machine_mode
cris_promote_function_mode(const_tree type ATTRIBUTE_UNUSED,machine_mode mode,int * punsignedp ATTRIBUTE_UNUSED,const_tree fntype ATTRIBUTE_UNUSED,int for_return)4057 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
4058 machine_mode mode,
4059 int *punsignedp ATTRIBUTE_UNUSED,
4060 const_tree fntype ATTRIBUTE_UNUSED,
4061 int for_return)
4062 {
4063 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4064 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4065 Maybe pointless as of now, but let's keep the old behavior. */
4066 if (for_return == 1)
4067 return mode;
4068 return CRIS_PROMOTED_MODE (mode, *punsignedp, type);
4069 }
4070
4071 /* Atomic types require alignment to be at least their "natural" size. */
4072
4073 static unsigned int
cris_atomic_align_for_mode(machine_mode mode)4074 cris_atomic_align_for_mode (machine_mode mode)
4075 {
4076 return GET_MODE_BITSIZE (mode);
4077 }
4078
4079 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4080 time being. */
4081
4082 static rtx
cris_function_value(const_tree type,const_tree func ATTRIBUTE_UNUSED,bool outgoing ATTRIBUTE_UNUSED)4083 cris_function_value(const_tree type,
4084 const_tree func ATTRIBUTE_UNUSED,
4085 bool outgoing ATTRIBUTE_UNUSED)
4086 {
4087 return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG);
4088 }
4089
4090 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4091 time being. */
4092
4093 static rtx
cris_libcall_value(machine_mode mode,const_rtx fun ATTRIBUTE_UNUSED)4094 cris_libcall_value (machine_mode mode,
4095 const_rtx fun ATTRIBUTE_UNUSED)
4096 {
4097 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG);
4098 }
4099
4100 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4101 time being. */
4102
4103 static bool
cris_function_value_regno_p(const unsigned int regno)4104 cris_function_value_regno_p (const unsigned int regno)
4105 {
4106 return (regno == CRIS_FIRST_ARG_REG);
4107 }
4108
4109 static int
cris_arg_partial_bytes(cumulative_args_t ca,machine_mode mode,tree type,bool named ATTRIBUTE_UNUSED)4110 cris_arg_partial_bytes (cumulative_args_t ca, machine_mode mode,
4111 tree type, bool named ATTRIBUTE_UNUSED)
4112 {
4113 if (get_cumulative_args (ca)->regs == CRIS_MAX_ARGS_IN_REGS - 1
4114 && !targetm.calls.must_pass_in_stack (mode, type)
4115 && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4
4116 && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8)
4117 return UNITS_PER_WORD;
4118 else
4119 return 0;
4120 }
4121
4122 static rtx
cris_function_arg_1(cumulative_args_t ca_v,machine_mode mode ATTRIBUTE_UNUSED,const_tree type ATTRIBUTE_UNUSED,bool named,bool incoming)4123 cris_function_arg_1 (cumulative_args_t ca_v,
4124 machine_mode mode ATTRIBUTE_UNUSED,
4125 const_tree type ATTRIBUTE_UNUSED,
4126 bool named, bool incoming)
4127 {
4128 const CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
4129
4130 if ((!incoming || named) && ca->regs < CRIS_MAX_ARGS_IN_REGS)
4131 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG + ca->regs);
4132 else
4133 return NULL_RTX;
4134 }
4135
4136 /* Worker function for TARGET_FUNCTION_ARG.
4137 The void_type_node is sent as a "closing" call. */
4138
4139 static rtx
cris_function_arg(cumulative_args_t ca,machine_mode mode,const_tree type,bool named)4140 cris_function_arg (cumulative_args_t ca, machine_mode mode,
4141 const_tree type, bool named)
4142 {
4143 return cris_function_arg_1 (ca, mode, type, named, false);
4144 }
4145
4146 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4147
4148 The differences between this and the previous, is that this one checks
4149 that an argument is named, since incoming stdarg/varargs arguments are
4150 pushed onto the stack, and we don't have to check against the "closing"
4151 void_type_node TYPE parameter. */
4152
4153 static rtx
cris_function_incoming_arg(cumulative_args_t ca,machine_mode mode,const_tree type,bool named)4154 cris_function_incoming_arg (cumulative_args_t ca, machine_mode mode,
4155 const_tree type, bool named)
4156 {
4157 return cris_function_arg_1 (ca, mode, type, named, true);
4158 }
4159
4160 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4161
4162 static void
cris_function_arg_advance(cumulative_args_t ca_v,machine_mode mode,const_tree type,bool named ATTRIBUTE_UNUSED)4163 cris_function_arg_advance (cumulative_args_t ca_v, machine_mode mode,
4164 const_tree type, bool named ATTRIBUTE_UNUSED)
4165 {
4166 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
4167
4168 ca->regs += (3 + CRIS_FUNCTION_ARG_SIZE (mode, type)) / 4;
4169 }
4170
4171 /* Worker function for TARGET_MD_ASM_ADJUST. */
4172
4173 static rtx_insn *
cris_md_asm_adjust(vec<rtx> & outputs,vec<rtx> & inputs,vec<const char * > & constraints,vec<rtx> & clobbers,HARD_REG_SET & clobbered_regs)4174 cris_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &inputs,
4175 vec<const char *> &constraints,
4176 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
4177 {
4178 /* For the time being, all asms clobber condition codes.
4179 Revisit when there's a reasonable use for inputs/outputs
4180 that mention condition codes. */
4181 clobbers.safe_push (gen_rtx_REG (CCmode, CRIS_CC0_REGNUM));
4182 SET_HARD_REG_BIT (clobbered_regs, CRIS_CC0_REGNUM);
4183
4184 /* Determine if the source using MOF. If it is, automatically
4185 clobbering MOF would cause it to have impossible constraints. */
4186
4187 /* Look for a use of the MOF constraint letter: h. */
4188 for (unsigned i = 0, n = constraints.length(); i < n; ++i)
4189 if (strchr (constraints[i], 'h') != NULL)
4190 return NULL;
4191
4192 /* Look for an output or an input that touches MOF. */
4193 rtx mof_reg = gen_rtx_REG (SImode, CRIS_MOF_REGNUM);
4194 for (unsigned i = 0, n = outputs.length(); i < n; ++i)
4195 if (reg_overlap_mentioned_p (mof_reg, outputs[i]))
4196 return NULL;
4197 for (unsigned i = 0, n = inputs.length(); i < n; ++i)
4198 if (reg_overlap_mentioned_p (mof_reg, inputs[i]))
4199 return NULL;
4200
4201 /* No direct reference to MOF or its constraint.
4202 Clobber it for backward compatibility. */
4203 clobbers.safe_push (mof_reg);
4204 SET_HARD_REG_BIT (clobbered_regs, CRIS_MOF_REGNUM);
4205 return NULL;
4206 }
4207
4208 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4209
4210 Really only needed if the stack frame has variable length (alloca
4211 or variable sized local arguments (GNU C extension). See PR39499 and
4212 PR38609 for the reason this isn't just 0. */
4213
4214 bool
cris_frame_pointer_required(void)4215 cris_frame_pointer_required (void)
4216 {
4217 return !crtl->sp_is_unchanging;
4218 }
4219
4220 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4221
4222 This looks too complicated, and it is. I assigned r7 to be the
4223 static chain register, but it is call-saved, so we have to save it,
4224 and come back to restore it after the call, so we have to save srp...
4225 Anyway, trampolines are rare enough that we can cope with this
4226 somewhat lack of elegance.
4227 (Do not be tempted to "straighten up" whitespace in the asms; the
4228 assembler #NO_APP state mandates strict spacing). */
4229 /* ??? See the i386 regparm=3 implementation that pushes the static
4230 chain value to the stack in the trampoline, and uses a call-saved
4231 register when called directly. */
4232
4233 static void
cris_asm_trampoline_template(FILE * f)4234 cris_asm_trampoline_template (FILE *f)
4235 {
4236 if (TARGET_V32)
4237 {
4238 /* This normally-unused nop insn acts as an instruction to
4239 the simulator to flush its instruction cache. None of
4240 the other instructions in the trampoline template suits
4241 as a trigger for V32. The pc-relative addressing mode
4242 works nicely as a trigger for V10.
4243 FIXME: Have specific V32 template (possibly avoiding the
4244 use of a special instruction). */
4245 fprintf (f, "\tclearf x\n");
4246 /* We have to use a register as an intermediate, choosing
4247 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4248 so we can use it for address indirection and jsr target. */
4249 fprintf (f, "\tmove $r1,$mof\n");
4250 /* +4 */
4251 fprintf (f, "\tmove.d 0,$r1\n");
4252 fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]);
4253 fprintf (f, "\taddq 6,$r1\n");
4254 fprintf (f, "\tmove $mof,[$r1]\n");
4255 fprintf (f, "\taddq 6,$r1\n");
4256 fprintf (f, "\tmove $srp,[$r1]\n");
4257 /* +20 */
4258 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4259 /* +26 */
4260 fprintf (f, "\tmove.d 0,$r1\n");
4261 fprintf (f, "\tjsr $r1\n");
4262 fprintf (f, "\tsetf\n");
4263 /* +36 */
4264 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4265 /* +42 */
4266 fprintf (f, "\tmove.d 0,$r1\n");
4267 /* +48 */
4268 fprintf (f, "\tmove.d 0,$r9\n");
4269 fprintf (f, "\tjump $r9\n");
4270 fprintf (f, "\tsetf\n");
4271 }
4272 else
4273 {
4274 fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]);
4275 fprintf (f, "\tmove $srp,[$pc+22]\n");
4276 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4277 fprintf (f, "\tjsr 0\n");
4278 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4279 fprintf (f, "\tjump 0\n");
4280 }
4281 }
4282
4283 /* Implement TARGET_TRAMPOLINE_INIT. */
4284
4285 static void
cris_trampoline_init(rtx m_tramp,tree fndecl,rtx chain_value)4286 cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
4287 {
4288 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
4289 rtx tramp = XEXP (m_tramp, 0);
4290 rtx mem;
4291
4292 emit_block_move (m_tramp, assemble_trampoline_template (),
4293 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
4294
4295 if (TARGET_V32)
4296 {
4297 mem = adjust_address (m_tramp, SImode, 6);
4298 emit_move_insn (mem, plus_constant (Pmode, tramp, 38));
4299 mem = adjust_address (m_tramp, SImode, 22);
4300 emit_move_insn (mem, chain_value);
4301 mem = adjust_address (m_tramp, SImode, 28);
4302 emit_move_insn (mem, fnaddr);
4303 }
4304 else
4305 {
4306 mem = adjust_address (m_tramp, SImode, 10);
4307 emit_move_insn (mem, chain_value);
4308 mem = adjust_address (m_tramp, SImode, 16);
4309 emit_move_insn (mem, fnaddr);
4310 }
4311
4312 /* Note that there is no need to do anything with the cache for
4313 sake of a trampoline. */
4314 }
4315
4316 /* Implement TARGET_HARD_REGNO_NREGS.
4317
4318 The VOIDmode test is so we can omit mode on anonymous insns. FIXME:
4319 Still needed in 2.9x, at least for Axis-20000319. */
4320
4321 static unsigned int
cris_hard_regno_nregs(unsigned int,machine_mode mode)4322 cris_hard_regno_nregs (unsigned int, machine_mode mode)
4323 {
4324 if (mode == VOIDmode)
4325 return 1;
4326 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD);
4327 }
4328
4329 /* Implement TARGET_HARD_REGNO_MODE_OK.
4330
4331 CRIS permits all registers to hold all modes. Well, except for the
4332 condition-code register. And we can't hold larger-than-register size
4333 modes in the last special register that can hold a full 32 bits. */
4334 static bool
cris_hard_regno_mode_ok(unsigned int regno,machine_mode mode)4335 cris_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
4336 {
4337 return ((mode == CCmode || regno != CRIS_CC0_REGNUM)
4338 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
4339 || (regno != CRIS_MOF_REGNUM && regno != CRIS_ACR_REGNUM)));
4340 }
4341
4342 /* Return the preferred minimum alignment for a static object. */
4343
4344 static HOST_WIDE_INT
cris_preferred_minimum_alignment(void)4345 cris_preferred_minimum_alignment (void)
4346 {
4347 if (!TARGET_CONST_ALIGN)
4348 return 8;
4349 if (TARGET_ALIGN_BY_32)
4350 return 32;
4351 return 16;
4352 }
4353
4354 /* Implement TARGET_STATIC_RTX_ALIGNMENT. */
4355
4356 static HOST_WIDE_INT
cris_static_rtx_alignment(machine_mode mode)4357 cris_static_rtx_alignment (machine_mode mode)
4358 {
4359 return MAX (cris_preferred_minimum_alignment (), GET_MODE_ALIGNMENT (mode));
4360 }
4361
4362 /* Implement TARGET_CONSTANT_ALIGNMENT. Note that this hook has the
4363 effect of making gcc believe that ALL references to constant stuff
4364 (in code segment, like strings) have this alignment. That is a rather
4365 rushed assumption. Luckily we do not care about the "alignment"
4366 operand to builtin memcpy (only place where it counts), so it doesn't
4367 affect any bad spots. */
4368
4369 static HOST_WIDE_INT
cris_constant_alignment(const_tree,HOST_WIDE_INT basic_align)4370 cris_constant_alignment (const_tree, HOST_WIDE_INT basic_align)
4371 {
4372 return MAX (cris_preferred_minimum_alignment (), basic_align);
4373 }
4374
4375 #if 0
4376 /* Various small functions to replace macros. Only called from a
4377 debugger. They might collide with gcc functions or system functions,
4378 so only emit them when '#if 1' above. */
4379
4380 enum rtx_code Get_code (rtx);
4381
4382 enum rtx_code
4383 Get_code (rtx x)
4384 {
4385 return GET_CODE (x);
4386 }
4387
4388 const char *Get_mode (rtx);
4389
4390 const char *
4391 Get_mode (rtx x)
4392 {
4393 return GET_MODE_NAME (GET_MODE (x));
4394 }
4395
4396 rtx Xexp (rtx, int);
4397
4398 rtx
4399 Xexp (rtx x, int n)
4400 {
4401 return XEXP (x, n);
4402 }
4403
4404 rtx Xvecexp (rtx, int, int);
4405
4406 rtx
4407 Xvecexp (rtx x, int n, int m)
4408 {
4409 return XVECEXP (x, n, m);
4410 }
4411
4412 int Get_rtx_len (rtx);
4413
4414 int
4415 Get_rtx_len (rtx x)
4416 {
4417 return GET_RTX_LENGTH (GET_CODE (x));
4418 }
4419
4420 /* Use upper-case to distinguish from local variables that are sometimes
4421 called next_insn and prev_insn. */
4422
4423 rtx Next_insn (rtx);
4424
4425 rtx
4426 Next_insn (rtx insn)
4427 {
4428 return NEXT_INSN (insn);
4429 }
4430
4431 rtx Prev_insn (rtx);
4432
4433 rtx
4434 Prev_insn (rtx insn)
4435 {
4436 return PREV_INSN (insn);
4437 }
4438 #endif
4439
4440 #include "gt-cris.h"
4441
4442 /*
4443 * Local variables:
4444 * eval: (c-set-style "gnu")
4445 * indent-tabs-mode: t
4446 * End:
4447 */
4448