1;; Code and mode itertator and attribute definitions for the ARM backend 2;; Copyright (C) 2010-2019 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21 22;;---------------------------------------------------------------------------- 23;; Mode iterators 24;;---------------------------------------------------------------------------- 25 26;; A list of modes that are exactly 64 bits in size. This is used to expand 27;; some splits that are the same for all modes when operating on ARM 28;; registers. 29(define_mode_iterator ANY64 [DI DF V8QI V4HI V4HF V2SI V2SF]) 30 31(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) 32 33;; A list of integer modes that are up to one word long 34(define_mode_iterator QHSI [QI HI SI]) 35 36;; A list of integer modes that are half and one word long 37(define_mode_iterator HSI [HI SI]) 38 39;; A list of integer modes that are less than a word 40(define_mode_iterator NARROW [QI HI]) 41 42;; A list of all the integer modes up to 64bit 43(define_mode_iterator QHSD [QI HI SI DI]) 44 45;; A list of the 32bit and 64bit integer modes 46(define_mode_iterator SIDI [SI DI]) 47 48;; A list of atomic compare and swap success return modes 49(define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")]) 50 51;; A list of modes which the VFP unit can handle 52(define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")]) 53 54;; Integer element sizes implemented by IWMMXT. 55(define_mode_iterator VMMX [V2SI V4HI V8QI]) 56 57(define_mode_iterator VMMX2 [V4HI V2SI]) 58 59;; Integer element sizes for shifts. 60(define_mode_iterator VSHFT [V4HI V2SI DI]) 61 62;; Integer and float modes supported by Neon and IWMMXT. 63(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) 64 65;; Integer and float modes supported by Neon and IWMMXT, except V2DI. 66(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) 67 68;; Integer modes supported by Neon and IWMMXT 69(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) 70 71;; Integer modes supported by Neon and IWMMXT, except V2DI 72(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) 73 74;; Double-width vector modes, on which we support arithmetic (no HF!) 75(define_mode_iterator VD [V8QI V4HI V2SI V2SF]) 76 77;; Double-width vector modes plus 64-bit elements for vreinterpret + vcreate. 78(define_mode_iterator VD_RE [V8QI V4HI V2SI V2SF DI]) 79 80;; Double-width vector modes plus 64-bit elements. 81(define_mode_iterator VDX [V8QI V4HI V4HF V2SI V2SF DI]) 82 83;; Double-width vector modes, with V4HF - for vldN_lane and vstN_lane. 84(define_mode_iterator VD_LANE [V8QI V4HI V4HF V2SI V2SF]) 85 86;; Double-width vector modes without floating-point elements. 87(define_mode_iterator VDI [V8QI V4HI V2SI]) 88 89;; Quad-width vector modes supporting arithmetic (no HF!). 90(define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) 91 92;; Quad-width vector modes, including V8HF. 93(define_mode_iterator VQ2 [V16QI V8HI V8HF V4SI V4SF]) 94 95;; Quad-width vector modes with 16- or 32-bit elements 96(define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF]) 97 98;; Quad-width vector modes plus 64-bit elements. 99(define_mode_iterator VQX [V16QI V8HI V8HF V4SI V4SF V2DI]) 100 101;; Quad-width vector modes without floating-point elements. 102(define_mode_iterator VQI [V16QI V8HI V4SI]) 103 104;; Quad-width vector modes, with TImode added, for moves. 105(define_mode_iterator VQXMOV [V16QI V8HI V8HF V4SI V4SF V2DI TI]) 106 107;; Opaque structure types wider than TImode. 108(define_mode_iterator VSTRUCT [EI OI CI XI]) 109 110;; Opaque structure types used in table lookups (except vtbl1/vtbx1). 111(define_mode_iterator VTAB [TI EI OI]) 112 113;; Widenable modes. 114(define_mode_iterator VW [V8QI V4HI V2SI]) 115 116;; Narrowable modes. 117(define_mode_iterator VN [V8HI V4SI V2DI]) 118 119;; All supported vector modes (except singleton DImode). 120(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI]) 121 122;; All supported floating-point vector modes (except V2DF). 123(define_mode_iterator VF [(V4HF "TARGET_NEON_FP16INST") 124 (V8HF "TARGET_NEON_FP16INST") V2SF V4SF]) 125 126;; Double vector modes. 127(define_mode_iterator VDF [V2SF V4HF]) 128 129;; Quad vector Float modes with half/single elements. 130(define_mode_iterator VQ_HSF [V8HF V4SF]) 131 132 133;; All supported vector modes (except those with 64-bit integer elements). 134(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) 135 136;; All supported vector modes including 16-bit float modes. 137(define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF 138 V8HF V4HF]) 139 140;; Supported integer vector modes (not 64 bit elements). 141(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) 142 143;; Supported integer vector modes (not singleton DI) 144(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) 145 146;; Vector modes, including 64-bit integer elements. 147(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI 148 V4HF V8HF V2SF V4SF DI V2DI]) 149 150;; Vector modes including 64-bit integer elements, but no floats. 151(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) 152 153;; Vector modes for H, S and D types. 154(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) 155 156;; Vector modes for float->int conversions. 157(define_mode_iterator VCVTF [V2SF V4SF]) 158 159;; Vector modes form int->float conversions. 160(define_mode_iterator VCVTI [V2SI V4SI]) 161 162;; Vector modes for int->half conversions. 163(define_mode_iterator VCVTHI [V4HI V8HI]) 164 165;; Vector modes for doubleword multiply-accumulate, etc. insns. 166(define_mode_iterator VMD [V4HI V2SI V2SF]) 167 168;; Vector modes for quadword multiply-accumulate, etc. insns. 169(define_mode_iterator VMQ [V8HI V4SI V4SF]) 170 171;; Above modes combined. 172(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) 173 174;; As VMD, but integer modes only. 175(define_mode_iterator VMDI [V4HI V2SI]) 176 177;; As VMQ, but integer modes only. 178(define_mode_iterator VMQI [V8HI V4SI]) 179 180;; Above modes combined. 181(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) 182 183;; Modes with 8-bit and 16-bit elements. 184(define_mode_iterator VX [V8QI V4HI V16QI V8HI]) 185 186;; Modes with 8-bit elements. 187(define_mode_iterator VE [V8QI V16QI]) 188 189;; Modes with 64-bit elements only. 190(define_mode_iterator V64 [DI V2DI]) 191 192;; Modes with 32-bit elements only. 193(define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) 194 195;; Modes with 8-bit, 16-bit and 32-bit elements. 196(define_mode_iterator VU [V16QI V8HI V4SI]) 197 198;; Vector modes for 16-bit floating-point support. 199(define_mode_iterator VH [V8HF V4HF]) 200 201;; Iterators used for fixed-point support. 202(define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA]) 203 204(define_mode_iterator ADDSUB [V4QQ V2HQ V2HA]) 205 206(define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA]) 207 208(define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA]) 209 210(define_mode_iterator QMUL [HQ HA]) 211 212;; Modes for polynomial or float values. 213(define_mode_iterator VPF [V8QI V16QI V2SF V4SF]) 214 215;;---------------------------------------------------------------------------- 216;; Code iterators 217;;---------------------------------------------------------------------------- 218 219;; A list of condition codes used in compare instructions where 220;; the carry flag from the addition is used instead of doing the 221;; compare a second time. 222(define_code_iterator LTUGEU [ltu geu]) 223 224;; The signed gt, ge comparisons 225(define_code_iterator GTGE [gt ge]) 226 227;; The signed gt, ge, lt, le comparisons 228(define_code_iterator GLTE [gt ge lt le]) 229 230;; The unsigned gt, ge comparisons 231(define_code_iterator GTUGEU [gtu geu]) 232 233;; Comparisons for vc<cmp> 234(define_code_iterator COMPARISONS [eq gt ge le lt]) 235 236;; A list of ... 237(define_code_iterator IOR_XOR [ior xor]) 238 239;; Operations on two halves of a quadword vector. 240(define_code_iterator VQH_OPS [plus smin smax umin umax]) 241 242;; Operations on two halves of a quadword vector, 243;; without unsigned variants (for use with *SFmode pattern). 244(define_code_iterator VQHS_OPS [plus smin smax]) 245 246;; A list of widening operators 247(define_code_iterator SE [sign_extend zero_extend]) 248 249;; Right shifts 250(define_code_iterator RSHIFTS [ashiftrt lshiftrt]) 251 252;; Iterator for integer conversions 253(define_code_iterator FIXUORS [fix unsigned_fix]) 254 255;; Binary operators whose second operand can be shifted. 256(define_code_iterator SHIFTABLE_OPS [plus minus ior xor and]) 257 258;; Operations on the sign of a number. 259(define_code_iterator ABSNEG [abs neg]) 260 261;; The PLUS and MINUS operators. 262(define_code_iterator PLUSMINUS [plus minus]) 263 264;; Conversions. 265(define_code_iterator FCVT [unsigned_float float]) 266 267;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows 268;; a stack pointer opoerand. The minus operation is a candidate for an rsub 269;; and hence only plus is supported. 270(define_code_attr t2_binop0 271 [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) 272 273;; The instruction to use when a SHIFTABLE_OPS has a shift operation as 274;; its first operand. 275(define_code_attr arith_shift_insn 276 [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) 277 278(define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") 279 (gtu "gt") (geu "ge")]) 280 281(define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")]) 282 283(define_code_attr vfml_op [(plus "a") (minus "s")]) 284 285;;---------------------------------------------------------------------------- 286;; Int iterators 287;;---------------------------------------------------------------------------- 288 289(define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM 290 UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) 291 292(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE 293 UNSPEC_VCLT UNSPEC_VCLE]) 294 295(define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT]) 296 297(define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT 298 UNSPEC_VCALE UNSPEC_VCALT]) 299 300(define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA]) 301 302(define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM 303 UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) 304 305(define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA]) 306 307(define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U]) 308 309(define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U]) 310 311(define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U 312 UNSPEC_VHADD_S UNSPEC_VHADD_U]) 313 314(define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U]) 315 316(define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN]) 317 318(define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U]) 319 320(define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE]) 321 322(define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U]) 323 324(define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE]) 325 326(define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH]) 327 328(define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE]) 329 330(define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P]) 331 332(define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE]) 333 334(define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U]) 335 336(define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U]) 337 338(define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U]) 339 340(define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U]) 341 342(define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN]) 343 344(define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U]) 345 346(define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U]) 347 348(define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U 349 UNSPEC_VMIN UNSPEC_VMIN_U]) 350 351(define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN]) 352 353(define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM]) 354 355(define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U]) 356 357(define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U]) 358 359(define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U 360 UNSPEC_VPMIN UNSPEC_VPMIN_U]) 361 362(define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN]) 363 364(define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U]) 365 366(define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N]) 367 368(define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N]) 369 370(define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N]) 371 372(define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U 373 UNSPEC_VCVTM_S UNSPEC_VCVTM_U 374 UNSPEC_VCVTN_S UNSPEC_VCVTN_U 375 UNSPEC_VCVTP_S UNSPEC_VCVTP_U]) 376 377(define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U]) 378 379;; Operators for FP16 instructions. 380(define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA 381 UNSPEC_VRNDM UNSPEC_VRNDN 382 UNSPEC_VRNDP UNSPEC_VRNDX]) 383 384(define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U]) 385 386(define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U]) 387 388(define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U 389 UNSPEC_VRSHL_S UNSPEC_VRSHL_U]) 390 391(define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U 392 UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U]) 393 394(define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N 395 UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N]) 396 397(define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N]) 398 399(define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N 400 UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N]) 401 402(define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N]) 403 404(define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N]) 405 406(define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N]) 407 408(define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N 409 UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N]) 410 411(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W 412 UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW]) 413 414(define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC]) 415 416(define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE 417 UNSPEC_SHA1SU1 UNSPEC_SHA256SU0]) 418 419(define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H 420 UNSPEC_SHA256H2 UNSPEC_SHA256SU1]) 421 422(define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M 423 UNSPEC_SHA1P]) 424 425(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH]) 426 427(define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE]) 428 429(define_int_iterator DOTPROD [UNSPEC_DOT_S UNSPEC_DOT_U]) 430 431(define_int_iterator VFMLHALVES [UNSPEC_VFML_LO UNSPEC_VFML_HI]) 432 433(define_int_iterator VCADD [UNSPEC_VCADD90 UNSPEC_VCADD270]) 434(define_int_iterator VCMLA [UNSPEC_VCMLA UNSPEC_VCMLA90 UNSPEC_VCMLA180 UNSPEC_VCMLA270]) 435 436;;---------------------------------------------------------------------------- 437;; Mode attributes 438;;---------------------------------------------------------------------------- 439 440;; Determine name of atomic compare and swap from success result mode. This 441;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. 442(define_mode_attr arch [(CC_Z "32") (SI "t1")]) 443 444;; Determine element size suffix from vector mode. 445(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) 446 447;; vtbl<n> suffix for NEON vector modes. 448(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) 449 450;; (Opposite) mode to convert to/from for NEON mode conversions. 451(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") 452 (V4SI "V4SF") (V4SF "V4SI")]) 453 454;; As above but in lower case. 455(define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") 456 (V4SI "v4sf") (V4SF "v4si")]) 457 458;; (Opposite) mode to convert to/from for vector-half mode conversions. 459(define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI") 460 (V8HI "V8HF") (V8HF "V8HI")]) 461 462;; Define element mode for each vector mode. 463(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") 464 (V4HI "HI") (V8HI "HI") 465 (V4HF "HF") (V8HF "HF") 466 (V2SI "SI") (V4SI "SI") 467 (V2SF "SF") (V4SF "SF") 468 (DI "DI") (V2DI "DI")]) 469 470;; As above but in lower case. 471(define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi") 472 (V4HI "hi") (V8HI "hi") 473 (V4HF "hf") (V8HF "hf") 474 (V2SI "si") (V4SI "si") 475 (V2SF "sf") (V4SF "sf") 476 (DI "di") (V2DI "di")]) 477 478;; Element modes for vector extraction, padded up to register size. 479 480(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") 481 (V4HI "SI") (V8HI "SI") 482 (V2SI "SI") (V4SI "SI") 483 (V2SF "SF") (V4SF "SF") 484 (DI "DI") (V2DI "DI")]) 485 486;; Mode of pair of elements for each vector mode, to define transfer 487;; size for structure lane/dup loads and stores. 488(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") 489 (V4HI "SI") (V8HI "SI") 490 (V4HF "SF") (V8HF "SF") 491 (V2SI "V2SI") (V4SI "V2SI") 492 (V2SF "V2SF") (V4SF "V2SF") 493 (DI "V2DI") (V2DI "V2DI")]) 494 495;; Mode mapping for VFM[A,S]L instructions. 496(define_mode_attr VFML [(V2SF "V4HF") (V4SF "V8HF")]) 497 498;; Mode mapping for VFM[A,S]L instructions for the vec_select result. 499(define_mode_attr VFMLSEL [(V2SF "V2HF") (V4SF "V4HF")]) 500 501;; Mode mapping for VFM[A,S]L instructions for some awkward lane-wise forms. 502(define_mode_attr VFMLSEL2 [(V2SF "V8HF") (V4SF "V4HF")]) 503 504;; Same as the above, but lowercase. 505(define_mode_attr vfmlsel2 [(V2SF "v8hf") (V4SF "v4hf")]) 506 507;; Similar, for three elements. 508(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") 509 (V4HI "BLK") (V8HI "BLK") 510 (V4HF "BLK") (V8HF "BLK") 511 (V2SI "BLK") (V4SI "BLK") 512 (V2SF "BLK") (V4SF "BLK") 513 (DI "EI") (V2DI "EI")]) 514 515;; Similar, for four elements. 516(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") 517 (V4HI "V4HI") (V8HI "V4HI") 518 (V4HF "V4HF") (V8HF "V4HF") 519 (V2SI "V4SI") (V4SI "V4SI") 520 (V2SF "V4SF") (V4SF "V4SF") 521 (DI "OI") (V2DI "OI")]) 522 523;; Register width from element mode 524(define_mode_attr V_reg [(V8QI "P") (V16QI "q") 525 (V4HI "P") (V8HI "q") 526 (V4HF "P") (V8HF "q") 527 (V2SI "P") (V4SI "q") 528 (V2SF "P") (V4SF "q") 529 (DI "P") (V2DI "q") 530 (V2HF "") (SF "") 531 (DF "P") (HF "")]) 532 533;; Output template to select the high VFP register of a mult-register value. 534(define_mode_attr V_hi [(V2SF "p") (V4SF "f")]) 535 536;; Output template to select the low VFP register of a mult-register value. 537(define_mode_attr V_lo [(V2SF "") (V4SF "e")]) 538 539;; Helper attribute for printing output templates for awkward forms of 540;; vfmlal/vfmlsl intrinsics. 541(define_mode_attr V_lane_reg [(V2SF "") (V4SF "P")]) 542 543;; Wider modes with the same number of elements. 544(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) 545 546;; Narrower modes with the same number of elements. 547(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) 548 549;; Narrower modes with double the number of elements. 550(define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI") 551 (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) 552 553;; Modes with half the number of equal-sized elements. 554(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") 555 (V8HF "V4HF") (V4SI "V2SI") 556 (V4SF "V2SF") (V2DF "DF") 557 (V2DI "DI") (V4HF "HF")]) 558 559;; Same, but lower-case. 560(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") 561 (V4SI "v2si") (V4SF "v2sf") 562 (V2DI "di")]) 563 564;; Modes with twice the number of equal-sized elements. 565(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") 566 (V2SI "V4SI") (V4HF "V8HF") 567 (V2SF "V4SF") (DF "V2DF") 568 (DI "V2DI")]) 569 570;; Same, but lower-case. 571(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") 572 (V2SI "v4si") (V2SF "v4sf") 573 (DI "v2di")]) 574 575;; Modes with double-width elements. 576(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") 577 (V4HI "V2SI") (V8HI "V4SI") 578 (V2SI "DI") (V4SI "V2DI")]) 579 580;; Double-sized modes with the same element size. 581;; Used for neon_vdup_lane, where the second operand is double-sized 582;; even when the first one is quad. 583(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") 584 (V4SI "V2SI") (V4SF "V2SF") 585 (V8QI "V8QI") (V4HI "V4HI") 586 (V2SI "V2SI") (V2SF "V2SF") 587 (V8HF "V4HF") (V4HF "V4HF")]) 588 589;; Mode of result of comparison operations (and bit-select operand 1). 590(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") 591 (V4HI "V4HI") (V8HI "V8HI") 592 (V2SI "V2SI") (V4SI "V4SI") 593 (V4HF "V4HI") (V8HF "V8HI") 594 (V2SF "V2SI") (V4SF "V4SI") 595 (DI "DI") (V2DI "V2DI")]) 596 597(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") 598 (V4HI "v4hi") (V8HI "v8hi") 599 (V2SI "v2si") (V4SI "v4si") 600 (DI "di") (V2DI "v2di") 601 (V2SF "v2si") (V4SF "v4si")]) 602 603;; Get element type from double-width mode, for operations where we 604;; don't care about signedness. 605(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") 606 (V4HI "i16") (V8HI "i16") 607 (V2SI "i32") (V4SI "i32") 608 (DI "i64") (V2DI "i64") 609 (V2SF "f32") (V4SF "f32") 610 (SF "f32") (DF "f64") 611 (HF "f16") (V4HF "f16") 612 (V8HF "f16")]) 613 614;; Same, but for operations which work on signed values. 615(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") 616 (V4HI "s16") (V8HI "s16") 617 (V2SI "s32") (V4SI "s32") 618 (DI "s64") (V2DI "s64") 619 (V2SF "f32") (V4SF "f32") 620 (HF "f16") (V4HF "f16") 621 (V8HF "f16")]) 622 623;; Same, but for operations which work on unsigned values. 624(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") 625 (V4HI "u16") (V8HI "u16") 626 (V2SI "u32") (V4SI "u32") 627 (DI "u64") (V2DI "u64") 628 (V2SF "f32") (V4SF "f32")]) 629 630;; Element types for extraction of unsigned scalars. 631(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") 632 (V4HI "u16") (V8HI "u16") 633 (V2SI "32") (V4SI "32") 634 (V4HF "u16") (V8HF "u16") 635 (V2SF "32") (V4SF "32")]) 636 637(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") 638 (V4HI "16") (V8HI "16") 639 (V2SI "32") (V4SI "32") 640 (DI "64") (V2DI "64") 641 (V4HF "16") (V8HF "16") 642 (V2SF "32") (V4SF "32")]) 643 644(define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b") 645 (V4HI "h") (V8HI "h") 646 (V2SI "s") (V4SI "s") 647 (DI "d") (V2DI "d") 648 (V2SF "s") (V4SF "s") 649 (V2SF "s") (V4SF "s")]) 650 651(define_mode_attr VH_elem_ch [(V4HI "s") (V8HI "s") 652 (V4HF "s") (V8HF "s") 653 (HF "s")]) 654 655;; Element sizes for duplicating ARM registers to all elements of a vector. 656(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) 657 658;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) 659(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") 660 (V4HI "TI") (V8HI "OI") 661 (V2SI "TI") (V4SI "OI") 662 (V2SF "TI") (V4SF "OI") 663 (DI "TI") (V2DI "OI")]) 664 665;; Same, but lower-case. 666(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") 667 (V4HI "ti") (V8HI "oi") 668 (V2SI "ti") (V4SI "oi") 669 (V2SF "ti") (V4SF "oi") 670 (DI "ti") (V2DI "oi")]) 671 672;; Extra suffix on some 64-bit insn names (to avoid collision with standard 673;; names which we don't want to define). 674(define_mode_attr V_suf64 [(V8QI "") (V16QI "") 675 (V4HI "") (V8HI "") 676 (V2SI "") (V4SI "") 677 (V2SF "") (V4SF "") 678 (DI "_neon") (V2DI "")]) 679 680 681;; Scalars to be presented to scalar multiplication instructions 682;; must satisfy the following constraints. 683;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. 684;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. 685 686;; This mode attribute is used to obtain the correct register constraints. 687 688(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") 689 (V8HI "x") (V4SI "t") (V4SF "t") 690 (V8HF "x") (V4HF "x")]) 691 692;; Predicates used for setting type for neon instructions 693 694(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") 695 (V4HI "false") (V8HI "false") 696 (V2SI "false") (V4SI "false") 697 (V4HF "true") (V8HF "true") 698 (V2SF "true") (V4SF "true") 699 (DI "false") (V2DI "false")]) 700 701(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") 702 (V4HI "true") (V8HI "true") 703 (V2SI "false") (V4SI "false") 704 (V2SF "false") (V4SF "false") 705 (DI "false") (V2DI "false")]) 706 707(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") 708 (V4HI "true") (V8HI "false") 709 (V2SI "true") (V4SI "false") 710 (V2SF "true") (V4SF "false") 711 (DI "true") (V2DI "false") 712 (V4HF "true") (V8HF "false")]) 713 714(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") 715 (V4HF "4") (V8HF "8") 716 (V4HI "4") (V8HI "8") 717 (V2SI "2") (V4SI "4") 718 (V2SF "2") (V4SF "4") 719 (DI "1") (V2DI "2") 720 (DF "1") (V2DF "2")]) 721 722;; Same as V_widen, but lower-case. 723(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) 724 725;; Widen. Result is half the number of elements, but widened to double-width. 726(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) 727 728;; Conditions to be used in extend<mode>di patterns. 729(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) 730(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") 731 (QI "&& arm_arch6")]) 732(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") 733 (HI "nonimmediate_operand") 734 (QI "nonimmediate_operand")]) 735(define_mode_attr qhs_extenddi_op [(SI "s_register_operand") 736 (HI "nonimmediate_operand") 737 (QI "arm_reg_or_extendqisi_mem_op")]) 738(define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")]) 739(define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")]) 740 741;; Mode attributes used for fixed-point support. 742(define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") 743 (V2UHA "16") (UHA "16") 744 (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16") 745 (V2HA "16") (HA "16") (SQ "") (SA "")]) 746 747;; Mode attribute for vshll. 748(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) 749 750;; Mode attributes used for VFP support. 751(define_mode_attr F_constraint [(SF "t") (DF "w")]) 752(define_mode_attr vfp_type [(SF "s") (DF "d")]) 753(define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")]) 754(define_mode_attr VF_constraint [(V4HF "t") (V8HF "t") (V2SF "t") (V4SF "w")]) 755 756;; Mode attribute used to build the "type" attribute. 757(define_mode_attr q [(V8QI "") (V16QI "_q") 758 (V4HI "") (V8HI "_q") 759 (V2SI "") (V4SI "_q") 760 (V4HF "") (V8HF "_q") 761 (V2SF "") (V4SF "_q") 762 (V4HF "") (V8HF "_q") 763 (DI "") (V2DI "_q") 764 (DF "") (V2DF "_q") 765 (HF "")]) 766 767(define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")]) 768 769(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")]) 770(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")]) 771 772;;---------------------------------------------------------------------------- 773;; Code attributes 774;;---------------------------------------------------------------------------- 775 776;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. 777(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") 778 (umin "vmin") (umax "vmax")]) 779 780;; Type attributes for vqh_ops and vqhs_ops iterators. 781(define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") 782 (umin "minmax") (umax "minmax")]) 783 784;; Signs of above, where relevant. 785(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") 786 (umax "u")]) 787 788(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) 789(define_code_attr optab [(ltu "ltu") (geu "geu")]) 790 791;; Assembler mnemonics for signedness of widening operations. 792(define_code_attr US [(sign_extend "s") (zero_extend "u")]) 793 794;; Signedness suffix for float->fixed conversions. Empty for signed 795;; conversion. 796(define_code_attr su_optab [(fix "") (unsigned_fix "u")]) 797 798;; Sign prefix to use in instruction type suffixes, i.e. s32, u32. 799(define_code_attr su [(fix "s") (unsigned_fix "u")]) 800 801;; Right shifts 802(define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) 803(define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) 804 805;; String reprentations of operations on the sign of a number. 806(define_code_attr absneg_str [(abs "abs") (neg "neg")]) 807 808;; Conversions. 809(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")]) 810 811(define_code_attr float_sup [(unsigned_float "u") (float "s")]) 812 813(define_code_attr float_SUP [(unsigned_float "U") (float "S")]) 814 815;;---------------------------------------------------------------------------- 816;; Int attributes 817;;---------------------------------------------------------------------------- 818 819;; Mapping between vector UNSPEC operations and the signed ('s'), 820;; unsigned ('u'), poly ('p') or float ('f') nature of their data type. 821(define_int_attr sup [ 822 (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u") 823 (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u") 824 (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u") 825 (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u") 826 (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u") 827 (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u") 828 (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u") 829 (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u") 830 (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u") 831 (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p") 832 (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u") 833 (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u") 834 (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u") 835 (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u") 836 (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u") 837 (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u") 838 (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u") 839 (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u") 840 (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u") 841 (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u") 842 (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u") 843 (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u") 844 (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u") 845 (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u") 846 (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u") 847 (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u") 848 (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u") 849 (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u") 850 (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u") 851 (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u") 852 (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u") 853 (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u") 854 (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u") 855 (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u") 856 (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u") 857 (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u") 858 (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u") 859 (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u") 860 (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u") 861 (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u") 862 (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u") 863 (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u") 864 (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u") 865 (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u") 866 (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u") 867 (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u") 868 (UNSPEC_DOT_S "s") (UNSPEC_DOT_U "u") 869]) 870 871(define_int_attr vfml_half 872 [(UNSPEC_VFML_HI "high") (UNSPEC_VFML_LO "low")]) 873 874(define_int_attr vfml_half_selector 875 [(UNSPEC_VFML_HI "true") (UNSPEC_VFML_LO "false")]) 876 877(define_int_attr vcvth_op 878 [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a") 879 (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m") 880 (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n") 881 (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")]) 882 883(define_int_attr fp16_rnd_str 884 [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda") 885 (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn") 886 (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")]) 887 888(define_int_attr fp16_rnd_insn 889 [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta") 890 (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn") 891 (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")]) 892 893(define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt") 894 (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le") 895 (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge") 896 (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le") 897 (UNSPEC_VCALT "lt")]) 898 899(define_int_attr r [ 900 (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r") 901 (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "") 902 (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r") 903 (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r") 904 (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r") 905 (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r") 906]) 907 908(define_int_attr maxmin [ 909 (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max") 910 (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min") 911 (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max") 912 (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min") 913]) 914 915(define_int_attr fmaxmin [ 916 (UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")]) 917 918(define_int_attr fmaxmin_op [ 919 (UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm") 920]) 921 922(define_int_attr shift_op [ 923 (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl") 924 (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl") 925 (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl") 926 (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl") 927 (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr") 928 (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr") 929 (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn") 930 (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn") 931 (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn") 932 (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun") 933 (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra") 934 (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra") 935]) 936 937;; Standard names for floating point to integral rounding instructions. 938(define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil") 939 (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor") 940 (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")]) 941 942;; Suffixes for vrint instructions specifying rounding modes. 943(define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p") 944 (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m") 945 (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")]) 946 947;; Some of the vrint instuctions are predicable. 948(define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no") 949 (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") 950 (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) 951 952(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") 953 (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") 954 (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) 955 956(define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") 957 (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") 958 (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) 959 960(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") 961 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb") 962 (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")]) 963 964(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") 965 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI") 966 (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")]) 967 968(define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc") 969 (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd") 970 (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1") 971 (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c") 972 (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p") 973 (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h") 974 (UNSPEC_SHA256H2 "sha256h2") 975 (UNSPEC_SHA256SU1 "sha256su1")]) 976 977(define_int_attr crypto_type 978 [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese") 979 (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc") 980 (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow") 981 (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast") 982 (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow") 983 (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast") 984 (UNSPEC_SHA256SU1 "crypto_sha256_slow")]) 985 986(define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8") 987 (UNSPEC_AESIMC "8") (UNSPEC_AESD "8") 988 (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32") 989 (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32") 990 (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32") 991 (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32") 992 (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")]) 993 994(define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI") 995 (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI") 996 (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI") 997 (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI") 998 (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI") 999 (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI") 1000 (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")]) 1001 1002(define_int_attr rot [(UNSPEC_VCADD90 "90") 1003 (UNSPEC_VCADD270 "270") 1004 (UNSPEC_VCMLA "0") 1005 (UNSPEC_VCMLA90 "90") 1006 (UNSPEC_VCMLA180 "180") 1007 (UNSPEC_VCMLA270 "270")]) 1008 1009;; Both kinds of return insn. 1010(define_code_iterator RETURNS [return simple_return]) 1011(define_code_attr return_str [(return "") (simple_return "simple_")]) 1012(define_code_attr return_simple_p [(return "false") (simple_return "true")]) 1013(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") 1014 (simple_return " && use_simple_return_p ()")]) 1015(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") 1016 (simple_return " && use_simple_return_p ()")]) 1017 1018;; Attributes for VQRDMLAH/VQRDMLSH 1019(define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")]) 1020 1021;; Attributes for VFMA_LANE/ VFMS_LANE 1022(define_int_attr neon_vfm_lane_as 1023 [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")]) 1024 1025;; An iterator for the CDP coprocessor instructions 1026(define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2]) 1027(define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")]) 1028(define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")]) 1029 1030;; An iterator for the LDC coprocessor instruction 1031(define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2 1032 VUNSPEC_LDCL VUNSPEC_LDC2L]) 1033(define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2") 1034 (VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")]) 1035(define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2") 1036 (VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")]) 1037 1038;; An iterator for the STC coprocessor instructions 1039(define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2 1040 VUNSPEC_STCL VUNSPEC_STC2L]) 1041(define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2") 1042 (VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")]) 1043(define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2") 1044 (VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")]) 1045 1046;; An iterator for the MCR coprocessor instructions 1047(define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2]) 1048 1049(define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")]) 1050(define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")]) 1051 1052;; An iterator for the MRC coprocessor instructions 1053(define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2]) 1054 1055(define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")]) 1056(define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")]) 1057 1058;; An iterator for the MCRR coprocessor instructions 1059(define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2]) 1060 1061(define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")]) 1062(define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")]) 1063 1064;; An iterator for the MRRC coprocessor instructions 1065(define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2]) 1066 1067(define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")]) 1068(define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")]) 1069 1070(define_int_attr opsuffix [(UNSPEC_DOT_S "s8") 1071 (UNSPEC_DOT_U "u8")]) 1072