1;; Mips.md Machine Description for MIPS based processors 2;; Copyright (C) 1989-2019 Free Software Foundation, Inc. 3;; Contributed by A. Lichnewsky, lich@inria.inria.fr 4;; Changes by Michael Meissner, meissner@osf.org 5;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 6;; Brendan Eich, brendan@microunity.com. 7 8;; This file is part of GCC. 9 10;; GCC is free software; you can redistribute it and/or modify 11;; it under the terms of the GNU General Public License as published by 12;; the Free Software Foundation; either version 3, or (at your option) 13;; any later version. 14 15;; GCC is distributed in the hope that it will be useful, 16;; but WITHOUT ANY WARRANTY; without even the implied warranty of 17;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18;; GNU General Public License for more details. 19 20;; You should have received a copy of the GNU General Public License 21;; along with GCC; see the file COPYING3. If not see 22;; <http://www.gnu.org/licenses/>. 23 24(define_enum "processor" [ 25 r3000 26 4kc 27 4kp 28 5kc 29 5kf 30 20kc 31 24kc 32 24kf2_1 33 24kf1_1 34 74kc 35 74kf2_1 36 74kf1_1 37 74kf3_2 38 loongson_2e 39 loongson_2f 40 gs464 41 gs464e 42 gs264e 43 m4k 44 octeon 45 octeon2 46 octeon3 47 r3900 48 r6000 49 r4000 50 r4100 51 r4111 52 r4120 53 r4130 54 r4300 55 r4600 56 r4650 57 r4700 58 r5000 59 r5400 60 r5500 61 r5900 62 r7000 63 r8000 64 r9000 65 r10000 66 sb1 67 sb1a 68 sr71000 69 xlr 70 xlp 71 p5600 72 m5100 73 i6400 74 p6600 75]) 76 77(define_c_enum "unspec" [ 78 ;; Unaligned accesses. 79 UNSPEC_LOAD_LEFT 80 UNSPEC_LOAD_RIGHT 81 UNSPEC_STORE_LEFT 82 UNSPEC_STORE_RIGHT 83 84 ;; Integer operations that are too cumbersome to describe directly. 85 UNSPEC_WSBH 86 UNSPEC_DSBH 87 UNSPEC_DSHD 88 89 ;; Floating-point moves. 90 UNSPEC_LOAD_LOW 91 UNSPEC_LOAD_HIGH 92 UNSPEC_STORE_WORD 93 UNSPEC_MFHC1 94 UNSPEC_MTHC1 95 96 ;; Floating-point environment. 97 UNSPEC_GET_FCSR 98 UNSPEC_SET_FCSR 99 100 ;; HI/LO moves. 101 UNSPEC_MFHI 102 UNSPEC_MTHI 103 UNSPEC_SET_HILO 104 105 ;; GP manipulation. 106 UNSPEC_LOADGP 107 UNSPEC_COPYGP 108 UNSPEC_MOVE_GP 109 UNSPEC_POTENTIAL_CPRESTORE 110 UNSPEC_CPRESTORE 111 UNSPEC_RESTORE_GP 112 UNSPEC_EH_RETURN 113 UNSPEC_GP 114 UNSPEC_SET_GOT_VERSION 115 UNSPEC_UPDATE_GOT_VERSION 116 117 ;; Symbolic accesses. 118 UNSPEC_LOAD_CALL 119 UNSPEC_LOAD_GOT 120 UNSPEC_TLS_LDM 121 UNSPEC_TLS_GET_TP 122 UNSPEC_UNSHIFTED_HIGH 123 124 ;; MIPS16 constant pools. 125 UNSPEC_ALIGN 126 UNSPEC_CONSTTABLE 127 UNSPEC_CONSTTABLE_END 128 UNSPEC_CONSTTABLE_INT 129 UNSPEC_CONSTTABLE_FLOAT 130 131 ;; Blockage and synchronisation. 132 UNSPEC_BLOCKAGE 133 UNSPEC_CLEAR_HAZARD 134 UNSPEC_RDHWR 135 UNSPEC_SYNCI 136 UNSPEC_SYNC 137 138 ;; Cache manipulation. 139 UNSPEC_MIPS_CACHE 140 UNSPEC_R10K_CACHE_BARRIER 141 142 ;; Interrupt handling. 143 UNSPEC_ERET 144 UNSPEC_DERET 145 UNSPEC_DI 146 UNSPEC_EHB 147 UNSPEC_RDPGPR 148 UNSPEC_COP0 149 150 ;; Used in a call expression in place of args_size. It's present for PIC 151 ;; indirect calls where it contains args_size and the function symbol. 152 UNSPEC_CALL_ATTR 153 154 ;; MIPS16 casesi jump table dispatch. 155 UNSPEC_CASESI_DISPATCH 156 157 ;; Stack checking. 158 UNSPEC_PROBE_STACK_RANGE 159 160 ;; The `.insn' pseudo-op. 161 UNSPEC_INSN_PSEUDO 162]) 163 164(define_constants 165 [(TLS_GET_TP_REGNUM 3) 166 (GET_FCSR_REGNUM 2) 167 (SET_FCSR_REGNUM 4) 168 (PIC_FUNCTION_ADDR_REGNUM 25) 169 (RETURN_ADDR_REGNUM 31) 170 (CPRESTORE_SLOT_REGNUM 76) 171 (GOT_VERSION_REGNUM 79) 172 173 ;; PIC long branch sequences are never longer than 100 bytes. 174 (MAX_PIC_BRANCH_LENGTH 100) 175 ] 176) 177 178(include "predicates.md") 179(include "constraints.md") 180 181;; .................... 182;; 183;; Attributes 184;; 185;; .................... 186 187(define_attr "got" "unset,xgot_high,load" 188 (const_string "unset")) 189 190;; For jal instructions, this attribute is DIRECT when the target address 191;; is symbolic and INDIRECT when it is a register. 192(define_attr "jal" "unset,direct,indirect" 193 (const_string "unset")) 194 195;; This attribute is YES if the instruction is a jal macro (not a 196;; real jal instruction). 197;; 198;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes 199;; an instruction to restore $gp. Direct jals are also macros for 200;; !TARGET_ABSOLUTE_JUMPS because they first load the target address 201;; into a register. 202(define_attr "jal_macro" "no,yes" 203 (cond [(eq_attr "jal" "direct") 204 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS 205 ? JAL_MACRO_YES : JAL_MACRO_NO)") 206 (eq_attr "jal" "indirect") 207 (symbol_ref "(TARGET_CALL_CLOBBERED_GP 208 ? JAL_MACRO_YES : JAL_MACRO_NO)")] 209 (const_string "no"))) 210 211;; Classification of moves, extensions and truncations. Most values 212;; are as for "type" (see below) but there are also the following 213;; move-specific values: 214;; 215;; constN move an N-constraint integer into a MIPS16 register 216;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed 217;; to produce a sign-extended DEST, even if SRC is not 218;; properly sign-extended 219;; ext_ins EXT, DEXT, INS or DINS instruction 220;; andi a single ANDI instruction 221;; loadpool move a constant into a MIPS16 register by loading it 222;; from the pool 223;; shift_shift a shift left followed by a shift right 224;; 225;; This attribute is used to determine the instruction's length and 226;; scheduling type. For doubleword moves, the attribute always describes 227;; the split instructions; in some cases, it is more appropriate for the 228;; scheduling type to be "multi" instead. 229(define_attr "move_type" 230 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove, 231 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool, 232 shift_shift" 233 (const_string "unknown")) 234 235(define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor,simd_add" 236 (const_string "unknown")) 237 238;; Main data type used by the insn 239(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW, 240 V2DI,V4SI,V8HI,V16QI,V2DF,V4SF" 241 (const_string "unknown")) 242 243;; True if the main data type is twice the size of a word. 244(define_attr "dword_mode" "no,yes" 245 (cond [(and (eq_attr "mode" "DI,DF") 246 (not (match_test "TARGET_64BIT"))) 247 (const_string "yes") 248 249 (and (eq_attr "mode" "TI,TF") 250 (match_test "TARGET_64BIT")) 251 (const_string "yes")] 252 (const_string "no"))) 253 254;; True if the main data type is four times of the size of a word. 255(define_attr "qword_mode" "no,yes" 256 (cond [(and (eq_attr "mode" "TI,TF") 257 (not (match_test "TARGET_64BIT"))) 258 (const_string "yes")] 259 (const_string "no"))) 260 261;; Attributes describing a sync loop. These loops have the form: 262;; 263;; if (RELEASE_BARRIER == YES) sync 264;; 1: OLDVAL = *MEM 265;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2 266;; CMP = 0 [delay slot] 267;; $TMP1 = OLDVAL & EXCLUSIVE_MASK 268;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2) 269;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK) 270;; $AT |= $TMP1 | $TMP3 271;; if (!commit (*MEM = $AT)) goto 1. 272;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot] 273;; CMP = 1 274;; if (ACQUIRE_BARRIER == YES) sync 275;; 2: 276;; 277;; where "$" values are temporaries and where the other values are 278;; specified by the attributes below. Values are specified as operand 279;; numbers and insns are specified as enums. If no operand number is 280;; specified, the following values are used instead: 281;; 282;; - OLDVAL: $AT 283;; - CMP: NONE 284;; - NEWVAL: $AT 285;; - INCLUSIVE_MASK: -1 286;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK 287;; - EXCLUSIVE_MASK: 0 288;; 289;; MEM and INSN1_OP2 are required. 290;; 291;; Ideally, the operand attributes would be integers, with -1 meaning "none", 292;; but the gen* programs don't yet support that. 293(define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none")) 294(define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none")) 295(define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none")) 296(define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none")) 297(define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none")) 298(define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none")) 299(define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none")) 300(define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none")) 301(define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori" 302 (const_string "move")) 303(define_attr "sync_insn2" "nop,and,xor,not" 304 (const_string "nop")) 305;; Memory model specifier. 306;; "0"-"9" values specify the operand that stores the memory model value. 307;; "10" specifies MEMMODEL_ACQ_REL, 308;; "11" specifies MEMMODEL_ACQUIRE. 309(define_attr "sync_memmodel" "" (const_int 10)) 310 311;; Accumulator operand for madd patterns. 312(define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none")) 313 314;; Classification of each insn. 315;; branch conditional branch 316;; jump unconditional jump 317;; call unconditional call 318;; load load instruction(s) 319;; fpload floating point load 320;; fpidxload floating point indexed load 321;; store store instruction(s) 322;; fpstore floating point store 323;; fpidxstore floating point indexed store 324;; prefetch memory prefetch (register + offset) 325;; prefetchx memory indexed prefetch (register + register) 326;; condmove conditional moves 327;; mtc transfer to coprocessor 328;; mfc transfer from coprocessor 329;; mthi transfer to a hi register 330;; mtlo transfer to a lo register 331;; mfhi transfer from a hi register 332;; mflo transfer from a lo register 333;; const load constant 334;; arith integer arithmetic instructions 335;; logical integer logical instructions 336;; shift integer shift instructions 337;; slt set less than instructions 338;; signext sign extend instructions 339;; clz the clz and clo instructions 340;; pop the pop instruction 341;; trap trap if instructions 342;; imul integer multiply 2 operands 343;; imul3 integer multiply 3 operands 344;; imul3nc integer multiply 3 operands without clobbering HI/LO 345;; imadd integer multiply-add 346;; idiv integer divide 2 operands 347;; idiv3 integer divide 3 operands 348;; move integer register move ({,D}ADD{,U} with rt = 0) 349;; fmove floating point register move 350;; fadd floating point add/subtract 351;; fmul floating point multiply 352;; fmadd floating point multiply-add 353;; fdiv floating point divide 354;; frdiv floating point reciprocal divide 355;; frdiv1 floating point reciprocal divide step 1 356;; frdiv2 floating point reciprocal divide step 2 357;; fabs floating point absolute value 358;; fneg floating point negation 359;; fcmp floating point compare 360;; fcvt floating point convert 361;; fsqrt floating point square root 362;; frsqrt floating point reciprocal square root 363;; frsqrt1 floating point reciprocal square root step1 364;; frsqrt2 floating point reciprocal square root step2 365;; dspmac DSP MAC instructions not saturating the accumulator 366;; dspmacsat DSP MAC instructions that saturate the accumulator 367;; accext DSP accumulator extract instructions 368;; accmod DSP accumulator modify instructions 369;; dspalu DSP ALU instructions not saturating the result 370;; dspalusat DSP ALU instructions that saturate the result 371;; multi multiword sequence (or user asm statements) 372;; atomic atomic memory update instruction 373;; syncloop memory atomic operation implemented as a sync loop 374;; nop no operation 375;; ghost an instruction that produces no real code 376;; multimem microMIPS multiword load and store 377(define_attr "type" 378 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, 379 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical, 380 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, 381 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, 382 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat, 383 multi,atomic,syncloop,nop,ghost,multimem, 384 simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd, 385 simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp, 386 simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill, 387 simd_permute,simd_shf,simd_sat,simd_pcnt,simd_copy,simd_branch,simd_cmsa, 388 simd_fminmax,simd_logic,simd_move,simd_load,simd_store" 389 (cond [(eq_attr "jal" "!unset") (const_string "call") 390 (eq_attr "got" "load") (const_string "load") 391 392 (eq_attr "alu_type" "add,sub") (const_string "arith") 393 394 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical") 395 396 ;; If a doubleword move uses these expensive instructions, 397 ;; it is usually better to schedule them in the same way 398 ;; as the singleword form, rather than as "multi". 399 (eq_attr "move_type" "load") (const_string "load") 400 (eq_attr "move_type" "fpload") (const_string "fpload") 401 (eq_attr "move_type" "store") (const_string "store") 402 (eq_attr "move_type" "fpstore") (const_string "fpstore") 403 (eq_attr "move_type" "mtc") (const_string "mtc") 404 (eq_attr "move_type" "mfc") (const_string "mfc") 405 (eq_attr "move_type" "mtlo") (const_string "mtlo") 406 (eq_attr "move_type" "mflo") (const_string "mflo") 407 408 ;; These types of move are always single insns. 409 (eq_attr "move_type" "imul") (const_string "imul") 410 (eq_attr "move_type" "fmove") (const_string "fmove") 411 (eq_attr "move_type" "loadpool") (const_string "load") 412 (eq_attr "move_type" "signext") (const_string "signext") 413 (eq_attr "move_type" "ext_ins") (const_string "arith") 414 (eq_attr "move_type" "arith") (const_string "arith") 415 (eq_attr "move_type" "logical") (const_string "logical") 416 (eq_attr "move_type" "sll0") (const_string "shift") 417 (eq_attr "move_type" "andi") (const_string "logical") 418 419 ;; These types of move are always split. 420 (eq_attr "move_type" "constN,shift_shift") 421 (const_string "multi") 422 423 ;; These types of move are split for quadword modes only. 424 (and (eq_attr "move_type" "move,const") 425 (eq_attr "qword_mode" "yes")) 426 (const_string "multi") 427 428 ;; These types of move are split for doubleword modes only. 429 (and (eq_attr "move_type" "move,const") 430 (eq_attr "dword_mode" "yes")) 431 (const_string "multi") 432 (eq_attr "move_type" "move") (const_string "move") 433 (eq_attr "move_type" "const") (const_string "const") 434 (eq_attr "sync_mem" "!none") (const_string "syncloop")] 435 (const_string "unknown"))) 436 437(define_attr "compact_form" "always,maybe,never" 438 (cond [(eq_attr "jal" "direct") 439 (const_string "always") 440 (eq_attr "jal" "indirect") 441 (const_string "maybe") 442 (eq_attr "type" "jump") 443 (const_string "maybe")] 444 (const_string "never"))) 445 446;; Mode for conversion types (fcvt) 447;; I2S integer to float single (SI/DI to SF) 448;; I2D integer to float double (SI/DI to DF) 449;; S2I float to integer (SF to SI/DI) 450;; D2I float to integer (DF to SI/DI) 451;; D2S double to float single 452;; S2D float single to double 453 454(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D" 455 (const_string "unknown")) 456 457;; Is this an extended instruction in mips16 mode? 458(define_attr "extended_mips16" "no,yes" 459 (if_then_else (ior ;; In general, constant-pool loads are extended 460 ;; instructions. We don't yet optimize for 16-bit 461 ;; PC-relative references. 462 (eq_attr "move_type" "sll0,loadpool") 463 (eq_attr "jal" "direct") 464 (eq_attr "got" "load")) 465 (const_string "yes") 466 (const_string "no"))) 467 468(define_attr "compression" "none,all,micromips32,micromips" 469 (const_string "none")) 470 471(define_attr "enabled" "no,yes" 472 (cond [;; The o32 FPXX and FP64A ABI extensions prohibit direct moves between 473 ;; GR_REG and FR_REG for 64-bit values. 474 (and (eq_attr "move_type" "mtc,mfc") 475 (match_test "(TARGET_FLOATXX && !ISA_HAS_MXHC1) 476 || TARGET_O32_FP64A_ABI") 477 (eq_attr "dword_mode" "yes")) 478 (const_string "no") 479 (and (eq_attr "compression" "micromips32,micromips") 480 (match_test "!TARGET_MICROMIPS")) 481 (const_string "no")] 482 (const_string "yes"))) 483 484;; The number of individual instructions that a non-branch pattern generates, 485;; using units of BASE_INSN_LENGTH. 486(define_attr "insn_count" "" 487 (cond [;; "Ghost" instructions occupy no space. 488 (eq_attr "type" "ghost") 489 (const_int 0) 490 491 ;; Extended instructions count as 2. 492 (and (eq_attr "extended_mips16" "yes") 493 (match_test "TARGET_MIPS16")) 494 (const_int 2) 495 496 ;; A GOT load followed by an add of $gp. This is not used for MIPS16. 497 (eq_attr "got" "xgot_high") 498 (const_int 2) 499 500 ;; SHIFT_SHIFTs are decomposed into two separate instructions. 501 ;; They are extended instructions on MIPS16 targets. 502 (eq_attr "move_type" "shift_shift") 503 (if_then_else (match_test "TARGET_MIPS16") 504 (const_int 4) 505 (const_int 2)) 506 507 ;; Check for doubleword moves that are decomposed into two 508 ;; instructions. The individual instructions are unextended 509 ;; MIPS16 ones. 510 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move") 511 (eq_attr "dword_mode" "yes")) 512 (const_int 2) 513 514 ;; Check for quadword moves that are decomposed into four 515 ;; instructions. 516 (and (eq_attr "move_type" "mtc,mfc,move") 517 (eq_attr "qword_mode" "yes")) 518 (const_int 4) 519 520 ;; Constants, loads and stores are handled by external routines. 521 (and (eq_attr "move_type" "const,constN") 522 (eq_attr "dword_mode" "yes")) 523 (symbol_ref "mips_split_const_insns (operands[1])") 524 (eq_attr "move_type" "const,constN") 525 (symbol_ref "mips_const_insns (operands[1])") 526 (eq_attr "move_type" "load,fpload") 527 (symbol_ref "mips_load_store_insns (operands[1], insn)") 528 (eq_attr "move_type" "store,fpstore") 529 (symbol_ref "mips_load_store_insns (operands[0], insn) 530 + (TARGET_FIX_24K ? 1 : 0)") 531 532 ;; In the worst case, a call macro will take 8 instructions: 533 ;; 534 ;; lui $25,%call_hi(FOO) 535 ;; addu $25,$25,$28 536 ;; lw $25,%call_lo(FOO)($25) 537 ;; nop 538 ;; jalr $25 539 ;; nop 540 ;; lw $gp,X($sp) 541 ;; nop 542 (eq_attr "jal_macro" "yes") 543 (const_int 8) 544 545 ;; Various VR4120 errata require a nop to be inserted after a macc 546 ;; instruction. The assembler does this for us, so account for 547 ;; the worst-case length here. 548 (and (eq_attr "type" "imadd") 549 (match_test "TARGET_FIX_VR4120")) 550 (const_int 2) 551 552 ;; VR4120 errata MD(4): if there are consecutive dmult instructions, 553 ;; the result of the second one is missed. The assembler should work 554 ;; around this by inserting a nop after the first dmult. 555 (and (eq_attr "type" "imul,imul3") 556 (eq_attr "mode" "DI") 557 (match_test "TARGET_FIX_VR4120")) 558 (const_int 2) 559 560 (eq_attr "type" "idiv,idiv3") 561 (symbol_ref "mips_idiv_insns (GET_MODE (PATTERN (insn)))") 562 563 (not (eq_attr "sync_mem" "none")) 564 (symbol_ref "mips_sync_loop_insns (insn, operands)")] 565 (const_int 1))) 566 567;; Length of instruction in bytes. The default is derived from "insn_count", 568;; but there are special cases for branches (which must be handled here) 569;; and for compressed single instructions. 570(define_attr "length" "" 571 (cond [(and (ior (eq_attr "compression" "micromips,all") 572 (and (eq_attr "compression" "micromips32") 573 (eq_attr "mode" "SI,SF"))) 574 (eq_attr "dword_mode" "no") 575 (match_test "TARGET_MICROMIPS")) 576 (const_int 2) 577 578 ;; Direct microMIPS branch instructions have a range of 579 ;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc]. 580 ;; If a branch is outside this range, we have a choice of two 581 ;; sequences. 582 ;; 583 ;; For PIC, an out-of-range branch like: 584 ;; 585 ;; bne r1,r2,target 586 ;; dslot 587 ;; 588 ;; becomes the equivalent of: 589 ;; 590 ;; beq r1,r2,1f 591 ;; dslot 592 ;; la $at,target 593 ;; jr $at 594 ;; nop 595 ;; 1: 596 ;; 597 ;; The non-PIC case is similar except that we use a direct 598 ;; jump instead of an la/jr pair. Since the target of this 599 ;; jump is an absolute 28-bit bit address (the other bits 600 ;; coming from the address of the delay slot) this form cannot 601 ;; cross a 256MB boundary. We could provide the option of 602 ;; using la/jr in this case too, but we do not do so at 603 ;; present. 604 ;; 605 ;; The value we specify here does not account for the delay slot 606 ;; instruction, whose length is added separately. If the RTL 607 ;; pattern has no explicit delay slot, mips_adjust_insn_length 608 ;; will add the length of the implicit nop. The range of 609 ;; [-0x20000, 0x1fffc] from the address of the delay slot 610 ;; therefore translates to a range of: 611 ;; 612 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)] 613 ;; == [-0x1fffc, 0x1fff8] 614 ;; 615 ;; from the shorten_branches reference address. 616 (and (eq_attr "type" "branch") 617 (not (match_test "TARGET_MIPS16"))) 618 (cond [;; Any variant can handle the 17-bit range. 619 (and (le (minus (match_dup 0) (pc)) (const_int 65532)) 620 (le (minus (pc) (match_dup 0)) (const_int 65534))) 621 (const_int 4) 622 623 ;; The 18-bit range is OK other than for microMIPS. 624 (and (not (match_test "TARGET_MICROMIPS")) 625 (and (le (minus (match_dup 0) (pc)) (const_int 131064)) 626 (le (minus (pc) (match_dup 0)) (const_int 131068)))) 627 (const_int 4) 628 629 ;; The non-PIC case: branch, first delay slot, and J. 630 (match_test "TARGET_ABSOLUTE_JUMPS") 631 (const_int 12)] 632 633 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate. 634 ;; mips_adjust_insn_length substitutes the correct length. 635 ;; 636 ;; Note that we can't simply use (symbol_ref ...) here 637 ;; because genattrtab needs to know the maximum length 638 ;; of an insn. 639 (const_int MAX_PIC_BRANCH_LENGTH)) 640 641 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe] 642 ;; from the address of the following instruction, which leads 643 ;; to a range of: 644 ;; 645 ;; [-(0x100 - sizeof (branch)), 0xfe] 646 ;; == [-0xfe, 0xfe] 647 ;; 648 ;; from the shorten_branches reference address. Extended branches 649 ;; likewise have a range of [-0x10000, 0xfffe] from the address 650 ;; of the following instruction, which leads to a range of: 651 ;; 652 ;; [-(0x10000 - sizeof (branch)), 0xfffe] 653 ;; == [-0xfffc, 0xfffe] 654 ;; 655 ;; from the reference address. 656 ;; 657 ;; When a branch is out of range, mips_reorg splits it into a form 658 ;; that uses in-range branches. There are four basic sequences: 659 ;; 660 ;; (1) Absolute addressing with a readable text segment 661 ;; (32-bit addresses): 662 ;; 663 ;; b... foo 2 bytes 664 ;; move $1,$2 2 bytes 665 ;; lw $2,label 2 bytes 666 ;; jr $2 2 bytes 667 ;; move $2,$1 2 bytes 668 ;; .align 2 0 or 2 bytes 669 ;; label: 670 ;; .word target 4 bytes 671 ;; foo: 672 ;; (16 bytes in the worst case) 673 ;; 674 ;; (2) Absolute addressing with a readable text segment 675 ;; (64-bit addresses): 676 ;; 677 ;; b... foo 2 bytes 678 ;; move $1,$2 2 bytes 679 ;; ld $2,label 2 bytes 680 ;; jr $2 2 bytes 681 ;; move $2,$1 2 bytes 682 ;; .align 3 0 to 6 bytes 683 ;; label: 684 ;; .dword target 8 bytes 685 ;; foo: 686 ;; (24 bytes in the worst case) 687 ;; 688 ;; (3) Absolute addressing without a readable text segment 689 ;; (which requires 32-bit addresses at present): 690 ;; 691 ;; b... foo 2 bytes 692 ;; move $1,$2 2 bytes 693 ;; lui $2,%hi(target) 4 bytes 694 ;; sll $2,8 2 bytes 695 ;; sll $2,8 2 bytes 696 ;; addiu $2,%lo(target) 4 bytes 697 ;; jr $2 2 bytes 698 ;; move $2,$1 2 bytes 699 ;; foo: 700 ;; (20 bytes) 701 ;; 702 ;; (4) PIC addressing (which requires 32-bit addresses at present): 703 ;; 704 ;; b... foo 2 bytes 705 ;; move $1,$2 2 bytes 706 ;; lw $2,cprestore 0, 2 or 4 bytes 707 ;; lw $2,%got(target)($2) 4 bytes 708 ;; addiu $2,%lo(target) 4 bytes 709 ;; jr $2 2 bytes 710 ;; move $2,$1 2 bytes 711 ;; foo: 712 ;; (20 bytes in the worst case) 713 (and (eq_attr "type" "branch") 714 (match_test "TARGET_MIPS16")) 715 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254)) 716 (le (minus (pc) (match_dup 0)) (const_int 254))) 717 (const_int 2) 718 (and (le (minus (match_dup 0) (pc)) (const_int 65534)) 719 (le (minus (pc) (match_dup 0)) (const_int 65532))) 720 (const_int 4) 721 (and (match_test "TARGET_ABICALLS") 722 (not (match_test "TARGET_ABSOLUTE_ABICALLS"))) 723 (const_int 20) 724 (match_test "Pmode == SImode") 725 (const_int 16) 726 ] (const_int 24))] 727 (symbol_ref "get_attr_insn_count (insn) * BASE_INSN_LENGTH"))) 728 729;; Attribute describing the processor. 730(define_enum_attr "cpu" "processor" 731 (const (symbol_ref "mips_tune"))) 732 733;; The type of hardware hazard associated with this instruction. 734;; DELAY means that the next instruction cannot read the result 735;; of this one. HILO means that the next two instructions cannot 736;; write to HI or LO. 737(define_attr "hazard" "none,delay,hilo,forbidden_slot" 738 (cond [(and (eq_attr "type" "load,fpload,fpidxload") 739 (match_test "ISA_HAS_LOAD_DELAY")) 740 (const_string "delay") 741 742 (and (eq_attr "type" "mfc,mtc") 743 (match_test "ISA_HAS_XFER_DELAY")) 744 (const_string "delay") 745 746 (and (eq_attr "type" "fcmp") 747 (match_test "ISA_HAS_FCMP_DELAY")) 748 (const_string "delay") 749 750 ;; The r4000 multiplication patterns include an mflo instruction. 751 (and (eq_attr "type" "imul") 752 (match_test "TARGET_FIX_R4000")) 753 (const_string "hilo") 754 755 (and (eq_attr "type" "mfhi,mflo") 756 (not (match_test "ISA_HAS_HILO_INTERLOCKS"))) 757 (const_string "hilo")] 758 (const_string "none"))) 759 760;; Can the instruction be put into a delay slot? 761(define_attr "can_delay" "no,yes" 762 (if_then_else (and (eq_attr "type" "!branch,call,jump") 763 (eq_attr "hazard" "none") 764 (match_test "get_attr_insn_count (insn) == 1")) 765 (const_string "yes") 766 (const_string "no"))) 767 768;; Attribute defining whether or not we can use the branch-likely 769;; instructions. 770(define_attr "branch_likely" "no,yes" 771 (if_then_else (match_test "GENERATE_BRANCHLIKELY") 772 (const_string "yes") 773 (const_string "no"))) 774 775;; True if an instruction might assign to hi or lo when reloaded. 776;; This is used by the TUNE_MACC_CHAINS code. 777(define_attr "may_clobber_hilo" "no,yes" 778 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo") 779 (const_string "yes") 780 (const_string "no"))) 781 782;; Describe a user's asm statement. 783(define_asm_attributes 784 [(set_attr "type" "multi") 785 (set_attr "can_delay" "no")]) 786 787;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated 788;; from the same template. 789(define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) 790 791;; A copy of GPR that can be used when a pattern has two independent 792;; modes. 793(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) 794 795(define_mode_iterator MOVEP1 [SI SF]) 796(define_mode_iterator MOVEP2 [SI SF]) 797(define_mode_iterator JOIN_MODE [HI 798 SI 799 (SF "TARGET_HARD_FLOAT") 800 (DF "TARGET_HARD_FLOAT 801 && TARGET_DOUBLE_FLOAT")]) 802 803;; This mode iterator allows :HILO to be used as the mode of the 804;; concatenated HI and LO registers. 805(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")]) 806 807;; This mode iterator allows :P to be used for patterns that operate on 808;; pointer-sized quantities. Exactly one of the two alternatives will match. 809(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 810 811;; This mode iterator allows :MOVECC to be used anywhere that a 812;; conditional-move-type condition is needed. 813(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") 814 (CC "TARGET_HARD_FLOAT 815 && !TARGET_LOONGSON_2EF 816 && !TARGET_MIPS5900")]) 817 818;; This mode iterator allows :FPCC to be used anywhere that an FP condition 819;; is needed. 820(define_mode_iterator FPCC [(CC "!ISA_HAS_CCF") 821 (CCF "ISA_HAS_CCF")]) 822 823;; 32-bit integer moves for which we provide move patterns. 824(define_mode_iterator IMOVE32 825 [SI 826 (V2HI "TARGET_DSP") 827 (V4QI "TARGET_DSP") 828 (V2HQ "TARGET_DSP") 829 (V2UHQ "TARGET_DSP") 830 (V2HA "TARGET_DSP") 831 (V2UHA "TARGET_DSP") 832 (V4QQ "TARGET_DSP") 833 (V4UQQ "TARGET_DSP")]) 834 835;; 64-bit modes for which we provide move patterns. 836(define_mode_iterator MOVE64 837 [DI DF 838 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT") 839 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI") 840 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI") 841 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI")]) 842 843;; 128-bit modes for which we provide move patterns on 64-bit targets. 844(define_mode_iterator MOVE128 [TI TF]) 845 846;; This mode iterator allows the QI and HI extension patterns to be 847;; defined from the same template. 848(define_mode_iterator SHORT [QI HI]) 849 850;; Likewise the 64-bit truncate-and-shift patterns. 851(define_mode_iterator SUBDI [QI HI SI]) 852 853;; This mode iterator allows :ANYF to be used wherever a scalar or vector 854;; floating-point mode is allowed. 855(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") 856 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT") 857 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")]) 858 859;; Like ANYF, but only applies to scalar modes. 860(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT") 861 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")]) 862 863;; A floating-point mode for which moves involving FPRs may need to be split. 864(define_mode_iterator SPLITF 865 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") 866 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") 867 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT") 868 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_MMI") 869 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_MMI") 870 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_MMI") 871 (TF "TARGET_64BIT && TARGET_FLOAT64")]) 872 873;; In GPR templates, a string like "<d>subu" will expand to "subu" in the 874;; 32-bit version and "dsubu" in the 64-bit version. 875(define_mode_attr d [(SI "") (DI "d") 876 (QQ "") (HQ "") (SQ "") (DQ "d") 877 (UQQ "") (UHQ "") (USQ "") (UDQ "d") 878 (HA "") (SA "") (DA "d") 879 (UHA "") (USA "") (UDA "d")]) 880 881;; Same as d but upper-case. 882(define_mode_attr D [(SI "") (DI "D") 883 (QQ "") (HQ "") (SQ "") (DQ "D") 884 (UQQ "") (UHQ "") (USQ "") (UDQ "D") 885 (HA "") (SA "") (DA "D") 886 (UHA "") (USA "") (UDA "D")]) 887 888;; This attribute gives the length suffix for a load or store instruction. 889;; The same suffixes work for zero and sign extensions. 890(define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")]) 891(define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")]) 892 893;; This attributes gives the mode mask of a SHORT. 894(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")]) 895 896;; Mode attributes for GPR loads. 897(define_mode_attr load [(SI "lw") (DI "ld")]) 898;; Instruction names for stores. 899(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")]) 900 901;; Similarly for MIPS IV indexed FPR loads and stores. 902(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")]) 903(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")]) 904 905;; The unextended ranges of the MIPS16 addiu and daddiu instructions 906;; are different. Some forms of unextended addiu have an 8-bit immediate 907;; field but the equivalent daddiu has only a 5-bit field. 908(define_mode_attr si8_di5 [(SI "8") (DI "5")]) 909 910;; This attribute gives the best constraint to use for registers of 911;; a given mode. 912(define_mode_attr reg [(SI "d") (DI "d") (CC "z") (CCF "f")]) 913 914;; This attribute gives the format suffix for floating-point operations. 915(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")]) 916 917;; This attribute gives the upper-case mode name for one unit of a 918;; floating-point mode or vector mode. 919(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF") (V4SF "SF") 920 (V16QI "QI") (V8HI "HI") (V4SI "SI") (V2DI "DI") 921 (V2DF "DF")]) 922 923;; As above, but in lower case. 924(define_mode_attr unitmode [(SF "sf") (DF "df") (V2SF "sf") (V4SF "sf") 925 (V16QI "qi") (V8QI "qi") (V8HI "hi") (V4HI "hi") 926 (V4SI "si") (V2SI "si") (V2DI "di") (V2DF "df")]) 927 928;; This attribute gives the integer mode that has the same size as a 929;; fixed-point mode. 930(define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI") 931 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI") 932 (HA "HI") (SA "SI") (DA "DI") 933 (UHA "HI") (USA "SI") (UDA "DI") 934 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI") 935 (V2HQ "SI") (V2HA "SI")]) 936 937;; This attribute gives the integer mode that has half the size of 938;; the controlling mode. 939(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI") 940 (V2SI "SI") (V4HI "SI") (V8QI "SI") 941 (TF "DI")]) 942 943;; This attribute works around the early SB-1 rev2 core "F2" erratum: 944;; 945;; In certain cases, div.s and div.ps may have a rounding error 946;; and/or wrong inexact flag. 947;; 948;; Therefore, we only allow div.s if not working around SB-1 rev2 949;; errata or if a slight loss of precision is OK. 950(define_mode_attr divide_condition 951 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations") 952 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")]) 953 954;; This attribute gives the conditions under which SQRT.fmt instructions 955;; can be used. 956(define_mode_attr sqrt_condition 957 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")]) 958 959;; This attribute provides the correct mnemonic for each FP condition mode. 960(define_mode_attr fpcmp [(CC "c") (CCF "cmp")]) 961 962;; This code iterator allows signed and unsigned widening multiplications 963;; to use the same template. 964(define_code_iterator any_extend [sign_extend zero_extend]) 965 966;; This code iterator allows the two right shift instructions to be 967;; generated from the same template. 968(define_code_iterator any_shiftrt [ashiftrt lshiftrt]) 969 970;; This code iterator allows the three shift instructions to be generated 971;; from the same template. 972(define_code_iterator any_shift [ashift ashiftrt lshiftrt]) 973 974;; This code iterator allows unsigned and signed division to be generated 975;; from the same template. 976(define_code_iterator any_div [div udiv]) 977 978;; This code iterator allows unsigned and signed modulus to be generated 979;; from the same template. 980(define_code_iterator any_mod [mod umod]) 981 982;; This code iterator allows addition and subtraction to be generated 983;; from the same template. 984(define_code_iterator addsub [plus minus]) 985 986;; This code iterator allows all native floating-point comparisons to be 987;; generated from the same template. 988(define_code_iterator fcond [unordered uneq unlt unle eq lt le 989 (ordered "ISA_HAS_CCF") 990 (ltgt "ISA_HAS_CCF") 991 (ne "ISA_HAS_CCF")]) 992 993;; This code iterator is used for comparisons that can be implemented 994;; by swapping the operands. 995(define_code_iterator swapped_fcond [ge gt unge ungt]) 996 997;; Equality operators. 998(define_code_iterator equality_op [eq ne]) 999 1000;; These code iterators allow the signed and unsigned scc operations to use 1001;; the same template. 1002(define_code_iterator any_gt [gt gtu]) 1003(define_code_iterator any_ge [ge geu]) 1004(define_code_iterator any_lt [lt ltu]) 1005(define_code_iterator any_le [le leu]) 1006 1007(define_code_iterator any_return [return simple_return]) 1008 1009;; <u> expands to an empty string when doing a signed operation and 1010;; "u" when doing an unsigned operation. 1011(define_code_attr u [(sign_extend "") (zero_extend "u") 1012 (div "") (udiv "u") 1013 (mod "") (umod "u") 1014 (gt "") (gtu "u") 1015 (ge "") (geu "u") 1016 (lt "") (ltu "u") 1017 (le "") (leu "u")]) 1018 1019;; <U> is like <u> except uppercase. 1020(define_code_attr U [(sign_extend "") (zero_extend "U")]) 1021 1022;; <su> is like <u>, but the signed form expands to "s" rather than "". 1023(define_code_attr su [(sign_extend "s") (zero_extend "u")]) 1024 1025;; <optab> expands to the name of the optab for a particular code. 1026(define_code_attr optab [(ashift "ashl") 1027 (ashiftrt "ashr") 1028 (lshiftrt "lshr") 1029 (ior "ior") 1030 (xor "xor") 1031 (and "and") 1032 (plus "add") 1033 (minus "sub") 1034 (return "return") 1035 (simple_return "simple_return")]) 1036 1037;; <insn> expands to the name of the insn that implements a particular code. 1038(define_code_attr insn [(ashift "sll") 1039 (ashiftrt "sra") 1040 (lshiftrt "srl") 1041 (ior "or") 1042 (xor "xor") 1043 (and "and") 1044 (plus "addu") 1045 (minus "subu")]) 1046 1047;; <immediate_insn> expands to the name of the insn that implements 1048;; a particular code to operate on immediate values. 1049(define_code_attr immediate_insn [(ior "ori") 1050 (xor "xori") 1051 (and "andi")]) 1052 1053(define_code_attr shift_compression [(ashift "micromips32") 1054 (lshiftrt "micromips32") 1055 (ashiftrt "none")]) 1056 1057;; <fcond> is the c.cond.fmt condition associated with a particular code. 1058(define_code_attr fcond [(unordered "un") 1059 (uneq "ueq") 1060 (unlt "ult") 1061 (unle "ule") 1062 (eq "eq") 1063 (lt "lt") 1064 (le "le") 1065 (ordered "or") 1066 (ltgt "ne") 1067 (ne "une")]) 1068 1069;; Similar, but for swapped conditions. 1070(define_code_attr swapped_fcond [(ge "le") 1071 (gt "lt") 1072 (unge "ule") 1073 (ungt "ult")]) 1074 1075;; The value of the bit when the branch is taken for branch_bit patterns. 1076;; Comparison is always against zero so this depends on the operator. 1077(define_code_attr bbv [(eq "0") (ne "1")]) 1078 1079;; This is the inverse value of bbv. 1080(define_code_attr bbinv [(eq "1") (ne "0")]) 1081 1082;; The sel mnemonic to use depending on the condition test. 1083(define_code_attr sel [(eq "seleqz") (ne "selnez")]) 1084(define_code_attr selinv [(eq "selnez") (ne "seleqz")]) 1085 1086;; ......................... 1087;; 1088;; Branch, call and jump delay slots 1089;; 1090;; ......................... 1091 1092(define_delay (and (eq_attr "type" "branch") 1093 (not (match_test "TARGET_MIPS16")) 1094 (eq_attr "branch_likely" "yes")) 1095 [(eq_attr "can_delay" "yes") 1096 (nil) 1097 (eq_attr "can_delay" "yes")]) 1098 1099;; Branches that have delay slots and don't have likely variants do 1100;; not annul on false. 1101(define_delay (and (eq_attr "type" "branch") 1102 (not (match_test "TARGET_MIPS16")) 1103 (ior (match_test "TARGET_CB_NEVER") 1104 (and (eq_attr "compact_form" "maybe") 1105 (not (match_test "TARGET_CB_ALWAYS"))) 1106 (eq_attr "compact_form" "never")) 1107 (eq_attr "branch_likely" "no")) 1108 [(eq_attr "can_delay" "yes") 1109 (nil) 1110 (nil)]) 1111 1112(define_delay (and (eq_attr "type" "jump") 1113 (ior (match_test "TARGET_CB_NEVER") 1114 (and (eq_attr "compact_form" "maybe") 1115 (not (match_test "TARGET_CB_ALWAYS"))) 1116 (eq_attr "compact_form" "never"))) 1117 [(eq_attr "can_delay" "yes") 1118 (nil) 1119 (nil)]) 1120 1121;; Call type instructions should never have a compact form as the 1122;; type is only used for MIPS16 patterns. For safety put the compact 1123;; branch detection condition in anyway. 1124(define_delay (and (eq_attr "type" "call") 1125 (eq_attr "jal_macro" "no") 1126 (ior (match_test "TARGET_CB_NEVER") 1127 (and (eq_attr "compact_form" "maybe") 1128 (not (match_test "TARGET_CB_ALWAYS"))) 1129 (eq_attr "compact_form" "never"))) 1130 [(eq_attr "can_delay" "yes") 1131 (nil) 1132 (nil)]) 1133 1134;; Pipeline descriptions. 1135;; 1136;; generic.md provides a fallback for processors without a specific 1137;; pipeline description. It is derived from the old define_function_unit 1138;; version and uses the "alu" and "imuldiv" units declared below. 1139;; 1140;; Some of the processor-specific files are also derived from old 1141;; define_function_unit descriptions and simply override the parts of 1142;; generic.md that don't apply. The other processor-specific files 1143;; are self-contained. 1144(define_automaton "alu,imuldiv") 1145 1146(define_cpu_unit "alu" "alu") 1147(define_cpu_unit "imuldiv" "imuldiv") 1148 1149;; Ghost instructions produce no real code and introduce no hazards. 1150;; They exist purely to express an effect on dataflow. 1151(define_insn_reservation "ghost" 0 1152 (eq_attr "type" "ghost") 1153 "nothing") 1154 1155(include "i6400.md") 1156(include "p5600.md") 1157(include "m5100.md") 1158(include "p6600.md") 1159(include "4k.md") 1160(include "5k.md") 1161(include "20kc.md") 1162(include "24k.md") 1163(include "74k.md") 1164(include "3000.md") 1165(include "4000.md") 1166(include "4100.md") 1167(include "4130.md") 1168(include "4300.md") 1169(include "4600.md") 1170(include "5000.md") 1171(include "5400.md") 1172(include "5500.md") 1173(include "6000.md") 1174(include "7000.md") 1175(include "9000.md") 1176(include "10000.md") 1177(include "loongson2ef.md") 1178(include "gs464.md") 1179(include "gs464e.md") 1180(include "gs264e.md") 1181(include "octeon.md") 1182(include "sb1.md") 1183(include "sr71k.md") 1184(include "xlr.md") 1185(include "xlp.md") 1186(include "generic.md") 1187 1188;; 1189;; .................... 1190;; 1191;; CONDITIONAL TRAPS 1192;; 1193;; .................... 1194;; 1195 1196(define_insn "trap" 1197 [(trap_if (const_int 1) (const_int 0))] 1198 "" 1199{ 1200 if (ISA_HAS_COND_TRAP) 1201 return "teq\t$0,$0"; 1202 else if (TARGET_MIPS16) 1203 return "break 0"; 1204 else 1205 return "break"; 1206} 1207 [(set_attr "type" "trap")]) 1208 1209(define_expand "ctrap<mode>4" 1210 [(trap_if (match_operator 0 "comparison_operator" 1211 [(match_operand:GPR 1 "reg_or_0_operand") 1212 (match_operand:GPR 2 "arith_operand")]) 1213 (match_operand 3 "const_0_operand"))] 1214 "ISA_HAS_COND_TRAPI || ISA_HAS_COND_TRAP" 1215{ 1216 mips_expand_conditional_trap (operands[0]); 1217 DONE; 1218}) 1219 1220(define_insn "*conditional_trap_reg<mode>" 1221 [(trap_if (match_operator:GPR 0 "trap_comparison_operator" 1222 [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 1223 (match_operand:GPR 2 "reg_or_0_operand" "dJ")]) 1224 (const_int 0))] 1225 "ISA_HAS_COND_TRAP && !ISA_HAS_COND_TRAPI" 1226 "t%C0\t%z1,%2" 1227 [(set_attr "type" "trap")]) 1228 1229(define_insn "*conditional_trap<mode>" 1230 [(trap_if (match_operator:GPR 0 "trap_comparison_operator" 1231 [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 1232 (match_operand:GPR 2 "arith_operand" "dI")]) 1233 (const_int 0))] 1234 "ISA_HAS_COND_TRAPI" 1235 "t%C0\t%z1,%2" 1236 [(set_attr "type" "trap")]) 1237 1238;; 1239;; .................... 1240;; 1241;; ADDITION 1242;; 1243;; .................... 1244;; 1245 1246(define_insn "add<mode>3" 1247 [(set (match_operand:ANYF 0 "register_operand" "=f") 1248 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f") 1249 (match_operand:ANYF 2 "register_operand" "f")))] 1250 "" 1251 "add.<fmt>\t%0,%1,%2" 1252 [(set_attr "type" "fadd") 1253 (set_attr "mode" "<UNITMODE>")]) 1254 1255(define_expand "add<mode>3" 1256 [(set (match_operand:GPR 0 "register_operand") 1257 (plus:GPR (match_operand:GPR 1 "register_operand") 1258 (match_operand:GPR 2 "arith_operand")))] 1259 "") 1260 1261(define_insn "*add<mode>3" 1262 [(set (match_operand:GPR 0 "register_operand" "=!u,d,!u,!u,!ks,!d,d") 1263 (plus:GPR (match_operand:GPR 1 "register_operand" "!u,d,!u,!ks,!ks,0,d") 1264 (match_operand:GPR 2 "arith_operand" "!u,d,Uead,Uuw6,Uesp,Usb4,Q")))] 1265 "!TARGET_MIPS16" 1266{ 1267 if (which_alternative == 0 1268 || which_alternative == 1) 1269 return "<d>addu\t%0,%1,%2"; 1270 else 1271 return "<d>addiu\t%0,%1,%2"; 1272} 1273 [(set_attr "alu_type" "add") 1274 (set_attr "compression" "micromips32,*,micromips32,micromips32,micromips32,micromips32,*") 1275 (set_attr "mode" "<MODE>")]) 1276 1277(define_insn "*add<mode>3_mips16" 1278 [(set (match_operand:GPR 0 "register_operand" "=ks,ks,d,d,d,d,d,d,d") 1279 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,ks,ks,0,0,d,d,d") 1280 (match_operand:GPR 2 "arith_operand" "Usd8,Q,Uuw<si8_di5>,Q,Usb<si8_di5>,Q,Usb4,O,d")))] 1281 "TARGET_MIPS16" 1282 "@ 1283 <d>addiu\t%0,%2 1284 <d>addiu\t%0,%2 1285 <d>addiu\t%0,%1,%2 1286 <d>addiu\t%0,%1,%2 1287 <d>addiu\t%0,%2 1288 <d>addiu\t%0,%2 1289 <d>addiu\t%0,%1,%2 1290 <d>addiu\t%0,%1,%2 1291 <d>addu\t%0,%1,%2" 1292 [(set_attr "alu_type" "add") 1293 (set_attr "mode" "<MODE>") 1294 (set_attr "extended_mips16" "no,yes,no,yes,no,yes,no,yes,no")]) 1295 1296;; On the mips16, we can sometimes split an add of a constant which is 1297;; a 4 byte instruction into two adds which are both 2 byte 1298;; instructions. There are two cases: one where we are adding a 1299;; constant plus a register to another register, and one where we are 1300;; simply adding a constant to a register. 1301 1302(define_split 1303 [(set (match_operand:SI 0 "d_operand") 1304 (plus:SI (match_dup 0) 1305 (match_operand:SI 1 "const_int_operand")))] 1306 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 1307 && ((INTVAL (operands[1]) > 0x7f 1308 && INTVAL (operands[1]) <= 0x7f + 0x7f) 1309 || (INTVAL (operands[1]) < - 0x80 1310 && INTVAL (operands[1]) >= - 0x80 - 0x80))" 1311 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 1312 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 1313{ 1314 HOST_WIDE_INT val = INTVAL (operands[1]); 1315 1316 if (val >= 0) 1317 { 1318 operands[1] = GEN_INT (0x7f); 1319 operands[2] = GEN_INT (val - 0x7f); 1320 } 1321 else 1322 { 1323 operands[1] = GEN_INT (- 0x80); 1324 operands[2] = GEN_INT (val + 0x80); 1325 } 1326}) 1327 1328(define_split 1329 [(set (match_operand:SI 0 "d_operand") 1330 (plus:SI (match_operand:SI 1 "d_operand") 1331 (match_operand:SI 2 "const_int_operand")))] 1332 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 1333 && REGNO (operands[0]) != REGNO (operands[1]) 1334 && ((INTVAL (operands[2]) > 0x7 1335 && INTVAL (operands[2]) <= 0x7 + 0x7f) 1336 || (INTVAL (operands[2]) < - 0x8 1337 && INTVAL (operands[2]) >= - 0x8 - 0x80))" 1338 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) 1339 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] 1340{ 1341 HOST_WIDE_INT val = INTVAL (operands[2]); 1342 1343 if (val >= 0) 1344 { 1345 operands[2] = GEN_INT (0x7); 1346 operands[3] = GEN_INT (val - 0x7); 1347 } 1348 else 1349 { 1350 operands[2] = GEN_INT (- 0x8); 1351 operands[3] = GEN_INT (val + 0x8); 1352 } 1353}) 1354 1355(define_split 1356 [(set (match_operand:DI 0 "d_operand") 1357 (plus:DI (match_dup 0) 1358 (match_operand:DI 1 "const_int_operand")))] 1359 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE 1360 && ((INTVAL (operands[1]) > 0xf 1361 && INTVAL (operands[1]) <= 0xf + 0xf) 1362 || (INTVAL (operands[1]) < - 0x10 1363 && INTVAL (operands[1]) >= - 0x10 - 0x10))" 1364 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) 1365 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] 1366{ 1367 HOST_WIDE_INT val = INTVAL (operands[1]); 1368 1369 if (val >= 0) 1370 { 1371 operands[1] = GEN_INT (0xf); 1372 operands[2] = GEN_INT (val - 0xf); 1373 } 1374 else 1375 { 1376 operands[1] = GEN_INT (- 0x10); 1377 operands[2] = GEN_INT (val + 0x10); 1378 } 1379}) 1380 1381(define_split 1382 [(set (match_operand:DI 0 "d_operand") 1383 (plus:DI (match_operand:DI 1 "d_operand") 1384 (match_operand:DI 2 "const_int_operand")))] 1385 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE 1386 && REGNO (operands[0]) != REGNO (operands[1]) 1387 && ((INTVAL (operands[2]) > 0x7 1388 && INTVAL (operands[2]) <= 0x7 + 0xf) 1389 || (INTVAL (operands[2]) < - 0x8 1390 && INTVAL (operands[2]) >= - 0x8 - 0x10))" 1391 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) 1392 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 1393{ 1394 HOST_WIDE_INT val = INTVAL (operands[2]); 1395 1396 if (val >= 0) 1397 { 1398 operands[2] = GEN_INT (0x7); 1399 operands[3] = GEN_INT (val - 0x7); 1400 } 1401 else 1402 { 1403 operands[2] = GEN_INT (- 0x8); 1404 operands[3] = GEN_INT (val + 0x8); 1405 } 1406}) 1407 1408(define_insn "*addsi3_extended" 1409 [(set (match_operand:DI 0 "register_operand" "=d,d") 1410 (sign_extend:DI 1411 (plus:SI (match_operand:SI 1 "register_operand" "d,d") 1412 (match_operand:SI 2 "arith_operand" "d,Q"))))] 1413 "TARGET_64BIT && !TARGET_MIPS16" 1414 "@ 1415 addu\t%0,%1,%2 1416 addiu\t%0,%1,%2" 1417 [(set_attr "alu_type" "add") 1418 (set_attr "mode" "SI")]) 1419 1420;; Split this insn so that the addiu splitters can have a crack at it. 1421;; Use a conservative length estimate until the split. 1422(define_insn_and_split "*addsi3_extended_mips16" 1423 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 1424 (sign_extend:DI 1425 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d") 1426 (match_operand:SI 2 "arith_operand" "Q,O,d"))))] 1427 "TARGET_64BIT && TARGET_MIPS16" 1428 "#" 1429 "&& reload_completed" 1430 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))] 1431 { operands[3] = gen_lowpart (SImode, operands[0]); } 1432 [(set_attr "alu_type" "add") 1433 (set_attr "mode" "SI") 1434 (set_attr "extended_mips16" "yes")]) 1435 1436;; Combiner patterns for unsigned byte-add. 1437 1438(define_insn "*baddu_si_eb" 1439 [(set (match_operand:SI 0 "register_operand" "=d") 1440 (zero_extend:SI 1441 (subreg:QI 1442 (plus:SI (match_operand:SI 1 "register_operand" "d") 1443 (match_operand:SI 2 "register_operand" "d")) 3)))] 1444 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" 1445 "baddu\\t%0,%1,%2" 1446 [(set_attr "alu_type" "add")]) 1447 1448(define_insn "*baddu_si_el" 1449 [(set (match_operand:SI 0 "register_operand" "=d") 1450 (zero_extend:SI 1451 (subreg:QI 1452 (plus:SI (match_operand:SI 1 "register_operand" "d") 1453 (match_operand:SI 2 "register_operand" "d")) 0)))] 1454 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" 1455 "baddu\\t%0,%1,%2" 1456 [(set_attr "alu_type" "add")]) 1457 1458(define_insn "*baddu_di<mode>" 1459 [(set (match_operand:GPR 0 "register_operand" "=d") 1460 (zero_extend:GPR 1461 (truncate:QI 1462 (plus:DI (match_operand:DI 1 "register_operand" "d") 1463 (match_operand:DI 2 "register_operand" "d")))))] 1464 "ISA_HAS_BADDU && TARGET_64BIT" 1465 "baddu\\t%0,%1,%2" 1466 [(set_attr "alu_type" "add")]) 1467 1468;; 1469;; .................... 1470;; 1471;; SUBTRACTION 1472;; 1473;; .................... 1474;; 1475 1476(define_insn "sub<mode>3" 1477 [(set (match_operand:ANYF 0 "register_operand" "=f") 1478 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f") 1479 (match_operand:ANYF 2 "register_operand" "f")))] 1480 "" 1481 "sub.<fmt>\t%0,%1,%2" 1482 [(set_attr "type" "fadd") 1483 (set_attr "mode" "<UNITMODE>")]) 1484 1485(define_insn "sub<mode>3" 1486 [(set (match_operand:GPR 0 "register_operand" "=!u,d") 1487 (minus:GPR (match_operand:GPR 1 "register_operand" "!u,d") 1488 (match_operand:GPR 2 "register_operand" "!u,d")))] 1489 "" 1490 "<d>subu\t%0,%1,%2" 1491 [(set_attr "alu_type" "sub") 1492 (set_attr "compression" "micromips32,*") 1493 (set_attr "mode" "<MODE>")]) 1494 1495(define_insn "*subsi3_extended" 1496 [(set (match_operand:DI 0 "register_operand" "=d") 1497 (sign_extend:DI 1498 (minus:SI (match_operand:SI 1 "register_operand" "d") 1499 (match_operand:SI 2 "register_operand" "d"))))] 1500 "TARGET_64BIT" 1501 "subu\t%0,%1,%2" 1502 [(set_attr "alu_type" "sub") 1503 (set_attr "mode" "DI")]) 1504 1505;; 1506;; .................... 1507;; 1508;; MULTIPLICATION 1509;; 1510;; .................... 1511;; 1512 1513(define_expand "mul<mode>3" 1514 [(set (match_operand:SCALARF 0 "register_operand") 1515 (mult:SCALARF (match_operand:SCALARF 1 "register_operand") 1516 (match_operand:SCALARF 2 "register_operand")))] 1517 "" 1518 "") 1519 1520(define_insn "*mul<mode>3" 1521 [(set (match_operand:SCALARF 0 "register_operand" "=f") 1522 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f") 1523 (match_operand:SCALARF 2 "register_operand" "f")))] 1524 "!TARGET_4300_MUL_FIX" 1525 "mul.<fmt>\t%0,%1,%2" 1526 [(set_attr "type" "fmul") 1527 (set_attr "mode" "<MODE>")]) 1528 1529;; Early VR4300 silicon has a CPU bug where multiplies with certain 1530;; operands may corrupt immediately following multiplies. This is a 1531;; simple fix to insert NOPs. 1532 1533(define_insn "*mul<mode>3_r4300" 1534 [(set (match_operand:SCALARF 0 "register_operand" "=f") 1535 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f") 1536 (match_operand:SCALARF 2 "register_operand" "f")))] 1537 "TARGET_4300_MUL_FIX" 1538 "mul.<fmt>\t%0,%1,%2\;nop" 1539 [(set_attr "type" "fmul") 1540 (set_attr "mode" "<MODE>") 1541 (set_attr "insn_count" "2")]) 1542 1543(define_insn "mulv2sf3" 1544 [(set (match_operand:V2SF 0 "register_operand" "=f") 1545 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f") 1546 (match_operand:V2SF 2 "register_operand" "f")))] 1547 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 1548 "mul.ps\t%0,%1,%2" 1549 [(set_attr "type" "fmul") 1550 (set_attr "mode" "SF")]) 1551 1552;; The original R4000 has a cpu bug. If a double-word or a variable 1553;; shift executes while an integer multiplication is in progress, the 1554;; shift may give an incorrect result. Avoid this by keeping the mflo 1555;; with the mult on the R4000. 1556;; 1557;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" 1558;; (also valid for MIPS R4000MC processors): 1559;; 1560;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to 1561;; this errata description. 1562;; The following code sequence causes the R4000 to incorrectly 1563;; execute the Double Shift Right Arithmetic 32 (dsra32) 1564;; instruction. If the dsra32 instruction is executed during an 1565;; integer multiply, the dsra32 will only shift by the amount in 1566;; specified in the instruction rather than the amount plus 32 1567;; bits. 1568;; instruction 1: mult rs,rt integer multiply 1569;; instruction 2-12: dsra32 rd,rt,rs doubleword shift 1570;; right arithmetic + 32 1571;; Workaround: A dsra32 instruction placed after an integer 1572;; multiply should not be one of the 11 instructions after the 1573;; multiply instruction." 1574;; 1575;; and: 1576;; 1577;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by 1578;; the following description. 1579;; All extended shifts (shift by n+32) and variable shifts (32 and 1580;; 64-bit versions) may produce incorrect results under the 1581;; following conditions: 1582;; 1) An integer multiply is currently executing 1583;; 2) These types of shift instructions are executed immediately 1584;; following an integer divide instruction. 1585;; Workaround: 1586;; 1) Make sure no integer multiply is running wihen these 1587;; instruction are executed. If this cannot be predicted at 1588;; compile time, then insert a "mfhi" to R0 instruction 1589;; immediately after the integer multiply instruction. This 1590;; will cause the integer multiply to complete before the shift 1591;; is executed. 1592;; 2) Separate integer divide and these two classes of shift 1593;; instructions by another instruction or a noop." 1594;; 1595;; These processors have PRId values of 0x00004220 and 0x00004300, 1596;; respectively. 1597 1598(define_expand "mul<mode>3" 1599 [(set (match_operand:GPR 0 "register_operand") 1600 (mult:GPR (match_operand:GPR 1 "register_operand") 1601 (match_operand:GPR 2 "register_operand")))] 1602 "ISA_HAS_<D>MULT || ISA_HAS_R6<D>MUL" 1603{ 1604 rtx lo; 1605 1606 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>MUL) 1607 emit_insn (gen_mul<mode>3_mul3_nohilo (operands[0], operands[1], 1608 operands[2])); 1609 else if (ISA_HAS_<D>MUL3) 1610 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2])); 1611 else if (TARGET_MIPS16) 1612 { 1613 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM); 1614 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2])); 1615 emit_move_insn (operands[0], lo); 1616 } 1617 else if (TARGET_FIX_R4000) 1618 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2])); 1619 else 1620 emit_insn 1621 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2])); 1622 DONE; 1623}) 1624 1625(define_insn "mul<mode>3_mul3_nohilo" 1626 [(set (match_operand:GPR 0 "register_operand" "=d") 1627 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1628 (match_operand:GPR 2 "register_operand" "d")))] 1629 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>MUL" 1630{ 1631 if (TARGET_LOONGSON_2EF) 1632 return "<d>multu.g\t%0,%1,%2"; 1633 else if (TARGET_LOONGSON_EXT) 1634 return "gs<d>multu\t%0,%1,%2"; 1635 else 1636 return "<d>mul\t%0,%1,%2"; 1637} 1638 [(set_attr "type" "imul3nc") 1639 (set_attr "mode" "<MODE>")]) 1640 1641(define_insn "mul<mode>3_mul3" 1642 [(set (match_operand:GPR 0 "register_operand" "=d,l") 1643 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d") 1644 (match_operand:GPR 2 "register_operand" "d,d"))) 1645 (clobber (match_scratch:GPR 3 "=l,X"))] 1646 "ISA_HAS_<D>MUL3" 1647{ 1648 if (which_alternative == 1) 1649 return "<d>mult\t%1,%2"; 1650 if (<MODE>mode == SImode && (TARGET_MIPS3900 || TARGET_MIPS5900)) 1651 return "mult\t%0,%1,%2"; 1652 return "<d>mul\t%0,%1,%2"; 1653} 1654 [(set_attr "type" "imul3,imul") 1655 (set_attr "mode" "<MODE>")]) 1656 1657;; If a register gets allocated to LO, and we spill to memory, the reload 1658;; will include a move from LO to a GPR. Merge it into the multiplication 1659;; if it can set the GPR directly. 1660;; 1661;; Operand 0: LO 1662;; Operand 1: GPR (1st multiplication operand) 1663;; Operand 2: GPR (2nd multiplication operand) 1664;; Operand 3: GPR (destination) 1665(define_peephole2 1666 [(parallel 1667 [(set (match_operand:SI 0 "lo_operand") 1668 (mult:SI (match_operand:SI 1 "d_operand") 1669 (match_operand:SI 2 "d_operand"))) 1670 (clobber (scratch:SI))]) 1671 (set (match_operand:SI 3 "d_operand") 1672 (match_dup 0))] 1673 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])" 1674 [(parallel 1675 [(set (match_dup 3) 1676 (mult:SI (match_dup 1) 1677 (match_dup 2))) 1678 (clobber (match_dup 0))])]) 1679 1680(define_insn "mul<mode>3_internal" 1681 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l") 1682 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1683 (match_operand:GPR 2 "register_operand" "d")))] 1684 "ISA_HAS_<D>MULT && !TARGET_FIX_R4000" 1685 "<d>mult\t%1,%2" 1686 [(set_attr "type" "imul") 1687 (set_attr "mode" "<MODE>")]) 1688 1689(define_insn "mul<mode>3_r4000" 1690 [(set (match_operand:GPR 0 "register_operand" "=d") 1691 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1692 (match_operand:GPR 2 "register_operand" "d"))) 1693 (clobber (match_scratch:GPR 3 "=l"))] 1694 "ISA_HAS_<D>MULT && TARGET_FIX_R4000" 1695 "<d>mult\t%1,%2\;mflo\t%0" 1696 [(set_attr "type" "imul") 1697 (set_attr "mode" "<MODE>") 1698 (set_attr "insn_count" "2")]) 1699 1700;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead 1701;; of "mult; mflo". They have the same latency, but the first form gives 1702;; us an extra cycle to compute the operands. 1703 1704;; Operand 0: LO 1705;; Operand 1: GPR (1st multiplication operand) 1706;; Operand 2: GPR (2nd multiplication operand) 1707;; Operand 3: GPR (destination) 1708(define_peephole2 1709 [(set (match_operand:SI 0 "lo_operand") 1710 (mult:SI (match_operand:SI 1 "d_operand") 1711 (match_operand:SI 2 "d_operand"))) 1712 (set (match_operand:SI 3 "d_operand") 1713 (match_dup 0))] 1714 "ISA_HAS_MACC && !ISA_HAS_MUL3" 1715 [(set (match_dup 0) 1716 (const_int 0)) 1717 (parallel 1718 [(set (match_dup 0) 1719 (plus:SI (mult:SI (match_dup 1) 1720 (match_dup 2)) 1721 (match_dup 0))) 1722 (set (match_dup 3) 1723 (plus:SI (mult:SI (match_dup 1) 1724 (match_dup 2)) 1725 (match_dup 0)))])]) 1726 1727;; Multiply-accumulate patterns 1728 1729;; This pattern is first matched by combine, which tries to use the 1730;; pattern wherever it can. We don't know until later whether it 1731;; is actually profitable to use MADD over a "MUL; ADDIU" sequence, 1732;; so we need to keep both options open. 1733;; 1734;; The second alternative has a "?" marker because it is generally 1735;; one instruction more costly than the first alternative. This "?" 1736;; marker is enough to convey the relative costs to the register 1737;; allocator. 1738;; 1739;; However, reload counts reloads of operands 4 and 5 in the same way as 1740;; reloads of the other operands, even though operands 4 and 5 need no 1741;; copy instructions. Reload therefore thinks that the second alternative 1742;; is two reloads more costly than the first. We add "*?*?" to the first 1743;; alternative as a counterweight. 1744;; 1745;; LRA simulates reload but the cost of reloading scratches is lower 1746;; than of the classic reload. For the time being, removing the counterweight 1747;; for LRA is more profitable. 1748(define_insn "*mul_acc_si" 1749 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?") 1750 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") 1751 (match_operand:SI 2 "register_operand" "d,d,d")) 1752 (match_operand:SI 3 "register_operand" "0,0,d"))) 1753 (clobber (match_scratch:SI 4 "=X,X,l")) 1754 (clobber (match_scratch:SI 5 "=X,X,&d"))] 1755 "GENERATE_MADD_MSUB && !TARGET_MIPS16" 1756 "@ 1757 madd\t%1,%2 1758 madd\t%1,%2 1759 #" 1760 [(set_attr "type" "imadd") 1761 (set_attr "accum_in" "3") 1762 (set_attr "mode" "SI") 1763 (set_attr "insn_count" "1,1,2") 1764 (set (attr "enabled") 1765 (cond [(and (eq_attr "alternative" "0") 1766 (match_test "!mips_lra_flag")) 1767 (const_string "yes") 1768 (and (eq_attr "alternative" "1") 1769 (match_test "mips_lra_flag")) 1770 (const_string "yes") 1771 (eq_attr "alternative" "2") 1772 (const_string "yes")] 1773 (const_string "no")))]) 1774 1775;; The same idea applies here. The middle alternative needs one less 1776;; clobber than the final alternative, so we add "*?" as a counterweight. 1777(define_insn "*mul_acc_si_r3900" 1778 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d*?,d?") 1779 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d,d") 1780 (match_operand:SI 2 "register_operand" "d,d,d,d")) 1781 (match_operand:SI 3 "register_operand" "0,0,l,d"))) 1782 (clobber (match_scratch:SI 4 "=X,X,3,l")) 1783 (clobber (match_scratch:SI 5 "=X,X,X,&d"))] 1784 "TARGET_MIPS3900 && !TARGET_MIPS16" 1785 "@ 1786 madd\t%1,%2 1787 madd\t%1,%2 1788 madd\t%0,%1,%2 1789 #" 1790 [(set_attr "type" "imadd") 1791 (set_attr "accum_in" "3") 1792 (set_attr "mode" "SI") 1793 (set_attr "insn_count" "1,1,1,2") 1794 (set (attr "enabled") 1795 (cond [(and (eq_attr "alternative" "0") 1796 (match_test "!mips_lra_flag")) 1797 (const_string "yes") 1798 (and (eq_attr "alternative" "1") 1799 (match_test "mips_lra_flag")) 1800 (const_string "yes") 1801 (eq_attr "alternative" "2,3") 1802 (const_string "yes")] 1803 (const_string "no")))]) 1804 1805;; Split *mul_acc_si if both the source and destination accumulator 1806;; values are GPRs. 1807(define_split 1808 [(set (match_operand:SI 0 "d_operand") 1809 (plus:SI (mult:SI (match_operand:SI 1 "d_operand") 1810 (match_operand:SI 2 "d_operand")) 1811 (match_operand:SI 3 "d_operand"))) 1812 (clobber (match_operand:SI 4 "lo_operand")) 1813 (clobber (match_operand:SI 5 "d_operand"))] 1814 "reload_completed" 1815 [(parallel [(set (match_dup 5) 1816 (mult:SI (match_dup 1) (match_dup 2))) 1817 (clobber (match_dup 4))]) 1818 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))] 1819 "") 1820 1821(define_insn "*macc" 1822 [(set (match_operand:SI 0 "register_operand" "=l,d") 1823 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") 1824 (match_operand:SI 2 "register_operand" "d,d")) 1825 (match_operand:SI 3 "register_operand" "0,l"))) 1826 (clobber (match_scratch:SI 4 "=X,3"))] 1827 "ISA_HAS_MACC" 1828{ 1829 if (which_alternative == 1) 1830 return "macc\t%0,%1,%2"; 1831 else if (TARGET_MIPS5500) 1832 return "madd\t%1,%2"; 1833 else 1834 /* The VR4130 assumes that there is a two-cycle latency between a macc 1835 that "writes" to $0 and an instruction that reads from it. We avoid 1836 this by assigning to $1 instead. */ 1837 return "%[macc\t%@,%1,%2%]"; 1838} 1839 [(set_attr "type" "imadd") 1840 (set_attr "accum_in" "3") 1841 (set_attr "mode" "SI")]) 1842 1843(define_insn "*msac" 1844 [(set (match_operand:SI 0 "register_operand" "=l,d") 1845 (minus:SI (match_operand:SI 1 "register_operand" "0,l") 1846 (mult:SI (match_operand:SI 2 "register_operand" "d,d") 1847 (match_operand:SI 3 "register_operand" "d,d")))) 1848 (clobber (match_scratch:SI 4 "=X,1"))] 1849 "ISA_HAS_MSAC" 1850{ 1851 if (which_alternative == 1) 1852 return "msac\t%0,%2,%3"; 1853 else if (TARGET_MIPS5500) 1854 return "msub\t%2,%3"; 1855 else 1856 return "msac\t$0,%2,%3"; 1857} 1858 [(set_attr "type" "imadd") 1859 (set_attr "accum_in" "1") 1860 (set_attr "mode" "SI")]) 1861 1862;; An msac-like instruction implemented using negation and a macc. 1863(define_insn_and_split "*msac_using_macc" 1864 [(set (match_operand:SI 0 "register_operand" "=l,d") 1865 (minus:SI (match_operand:SI 1 "register_operand" "0,l") 1866 (mult:SI (match_operand:SI 2 "register_operand" "d,d") 1867 (match_operand:SI 3 "register_operand" "d,d")))) 1868 (clobber (match_scratch:SI 4 "=X,1")) 1869 (clobber (match_scratch:SI 5 "=d,d"))] 1870 "ISA_HAS_MACC && !ISA_HAS_MSAC" 1871 "#" 1872 "&& reload_completed" 1873 [(set (match_dup 5) 1874 (neg:SI (match_dup 3))) 1875 (parallel 1876 [(set (match_dup 0) 1877 (plus:SI (mult:SI (match_dup 2) 1878 (match_dup 5)) 1879 (match_dup 1))) 1880 (clobber (match_dup 4))])] 1881 "" 1882 [(set_attr "type" "imadd") 1883 (set_attr "accum_in" "1") 1884 (set_attr "insn_count" "2")]) 1885 1886;; Patterns generated by the define_peephole2 below. 1887 1888(define_insn "*macc2" 1889 [(set (match_operand:SI 0 "muldiv_target_operand" "=l") 1890 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") 1891 (match_operand:SI 2 "register_operand" "d")) 1892 (match_dup 0))) 1893 (set (match_operand:SI 3 "register_operand" "=d") 1894 (plus:SI (mult:SI (match_dup 1) 1895 (match_dup 2)) 1896 (match_dup 0)))] 1897 "ISA_HAS_MACC && reload_completed" 1898 "macc\t%3,%1,%2" 1899 [(set_attr "type" "imadd") 1900 (set_attr "accum_in" "0") 1901 (set_attr "mode" "SI")]) 1902 1903(define_insn "*msac2" 1904 [(set (match_operand:SI 0 "muldiv_target_operand" "=l") 1905 (minus:SI (match_dup 0) 1906 (mult:SI (match_operand:SI 1 "register_operand" "d") 1907 (match_operand:SI 2 "register_operand" "d")))) 1908 (set (match_operand:SI 3 "register_operand" "=d") 1909 (minus:SI (match_dup 0) 1910 (mult:SI (match_dup 1) 1911 (match_dup 2))))] 1912 "ISA_HAS_MSAC && reload_completed" 1913 "msac\t%3,%1,%2" 1914 [(set_attr "type" "imadd") 1915 (set_attr "accum_in" "0") 1916 (set_attr "mode" "SI")]) 1917 1918;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2> 1919;; Similarly msac. 1920;; 1921;; Operand 0: LO 1922;; Operand 1: macc/msac 1923;; Operand 2: GPR (destination) 1924(define_peephole2 1925 [(parallel 1926 [(set (match_operand:SI 0 "lo_operand") 1927 (match_operand:SI 1 "macc_msac_operand")) 1928 (clobber (scratch:SI))]) 1929 (set (match_operand:SI 2 "d_operand") 1930 (match_dup 0))] 1931 "" 1932 [(parallel [(set (match_dup 0) 1933 (match_dup 1)) 1934 (set (match_dup 2) 1935 (match_dup 1))])]) 1936 1937;; When we have a three-address multiplication instruction, it should 1938;; be faster to do a separate multiply and add, rather than moving 1939;; something into LO in order to use a macc instruction. 1940;; 1941;; This peephole needs a scratch register to cater for the case when one 1942;; of the multiplication operands is the same as the destination. 1943;; 1944;; Operand 0: GPR (scratch) 1945;; Operand 1: LO 1946;; Operand 2: GPR (addend) 1947;; Operand 3: GPR (destination) 1948;; Operand 4: macc/msac 1949;; Operand 5: new multiplication 1950;; Operand 6: new addition/subtraction 1951(define_peephole2 1952 [(match_scratch:SI 0 "d") 1953 (set (match_operand:SI 1 "lo_operand") 1954 (match_operand:SI 2 "d_operand")) 1955 (match_dup 0) 1956 (parallel 1957 [(set (match_operand:SI 3 "d_operand") 1958 (match_operand:SI 4 "macc_msac_operand")) 1959 (clobber (match_dup 1))])] 1960 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])" 1961 [(parallel [(set (match_dup 0) 1962 (match_dup 5)) 1963 (clobber (match_dup 1))]) 1964 (set (match_dup 3) 1965 (match_dup 6))] 1966{ 1967 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); 1968 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, 1969 operands[2], operands[0]); 1970}) 1971 1972;; Same as above, except LO is the initial target of the macc. 1973;; 1974;; Operand 0: GPR (scratch) 1975;; Operand 1: LO 1976;; Operand 2: GPR (addend) 1977;; Operand 3: macc/msac 1978;; Operand 4: GPR (destination) 1979;; Operand 5: new multiplication 1980;; Operand 6: new addition/subtraction 1981(define_peephole2 1982 [(match_scratch:SI 0 "d") 1983 (set (match_operand:SI 1 "lo_operand") 1984 (match_operand:SI 2 "d_operand")) 1985 (match_dup 0) 1986 (parallel 1987 [(set (match_dup 1) 1988 (match_operand:SI 3 "macc_msac_operand")) 1989 (clobber (scratch:SI))]) 1990 (match_dup 0) 1991 (set (match_operand:SI 4 "d_operand") 1992 (match_dup 1))] 1993 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])" 1994 [(parallel [(set (match_dup 0) 1995 (match_dup 5)) 1996 (clobber (match_dup 1))]) 1997 (set (match_dup 4) 1998 (match_dup 6))] 1999{ 2000 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1); 2001 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 2002 operands[2], operands[0]); 2003}) 2004 2005;; See the comment above *mul_add_si for details. 2006(define_insn "*mul_sub_si" 2007 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?") 2008 (minus:SI (match_operand:SI 1 "register_operand" "0,0,d") 2009 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") 2010 (match_operand:SI 3 "register_operand" "d,d,d")))) 2011 (clobber (match_scratch:SI 4 "=X,X,l")) 2012 (clobber (match_scratch:SI 5 "=X,X,&d"))] 2013 "GENERATE_MADD_MSUB" 2014 "@ 2015 msub\t%2,%3 2016 msub\t%2,%3 2017 #" 2018 [(set_attr "type" "imadd") 2019 (set_attr "accum_in" "1") 2020 (set_attr "mode" "SI") 2021 (set_attr "insn_count" "1,1,2") 2022 (set (attr "enabled") 2023 (cond [(and (eq_attr "alternative" "0") 2024 (match_test "!mips_lra_flag")) 2025 (const_string "yes") 2026 (and (eq_attr "alternative" "1") 2027 (match_test "mips_lra_flag")) 2028 (const_string "yes") 2029 (eq_attr "alternative" "2") 2030 (const_string "yes")] 2031 (const_string "no")))]) 2032 2033;; Split *mul_sub_si if both the source and destination accumulator 2034;; values are GPRs. 2035(define_split 2036 [(set (match_operand:SI 0 "d_operand") 2037 (minus:SI (match_operand:SI 1 "d_operand") 2038 (mult:SI (match_operand:SI 2 "d_operand") 2039 (match_operand:SI 3 "d_operand")))) 2040 (clobber (match_operand:SI 4 "lo_operand")) 2041 (clobber (match_operand:SI 5 "d_operand"))] 2042 "reload_completed" 2043 [(parallel [(set (match_dup 5) 2044 (mult:SI (match_dup 2) (match_dup 3))) 2045 (clobber (match_dup 4))]) 2046 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))] 2047 "") 2048 2049(define_insn "*muls" 2050 [(set (match_operand:SI 0 "register_operand" "=l,d") 2051 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") 2052 (match_operand:SI 2 "register_operand" "d,d")))) 2053 (clobber (match_scratch:SI 3 "=X,l"))] 2054 "ISA_HAS_MULS" 2055 "@ 2056 muls\t$0,%1,%2 2057 muls\t%0,%1,%2" 2058 [(set_attr "type" "imul,imul3") 2059 (set_attr "mode" "SI")]) 2060 2061(define_expand "<u>mulsidi3" 2062 [(set (match_operand:DI 0 "register_operand") 2063 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2064 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2065 "mips_mulsidi3_gen_fn (<CODE>) != NULL" 2066{ 2067 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>); 2068 emit_insn (fn (operands[0], operands[1], operands[2])); 2069 DONE; 2070}) 2071 2072(define_expand "<u>mulsidi3_32bit_r6" 2073 [(set (match_operand:DI 0 "register_operand") 2074 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2075 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2076 "!TARGET_64BIT && ISA_HAS_R6MUL" 2077{ 2078 rtx dest = gen_reg_rtx (DImode); 2079 rtx low = mips_subword (dest, 0); 2080 rtx high = mips_subword (dest, 1); 2081 2082 emit_insn (gen_mulsi3_mul3_nohilo (low, operands[1], operands[2])); 2083 emit_insn (gen_<su>mulsi3_highpart_r6 (high, operands[1], operands[2])); 2084 2085 emit_move_insn (mips_subword (operands[0], 0), low); 2086 emit_move_insn (mips_subword (operands[0], 1), high); 2087 DONE; 2088}) 2089 2090(define_expand "<u>mulsidi3_32bit_mips16" 2091 [(set (match_operand:DI 0 "register_operand") 2092 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2093 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2094 "!TARGET_64BIT && TARGET_MIPS16" 2095{ 2096 rtx hilo; 2097 2098 hilo = gen_rtx_REG (DImode, MD_REG_FIRST); 2099 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2])); 2100 emit_move_insn (operands[0], hilo); 2101 DONE; 2102}) 2103 2104;; As well as being named patterns, these instructions are used by the 2105;; __builtin_mips_mult<u>() functions. We must always make those functions 2106;; available if !TARGET_64BIT && ISA_HAS_DSP. 2107(define_insn "<u>mulsidi3_32bit" 2108 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") 2109 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2110 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] 2111 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP) && ISA_HAS_MULT" 2112{ 2113 if (ISA_HAS_DSP_MULT) 2114 return "mult<u>\t%q0,%1,%2"; 2115 else 2116 return "mult<u>\t%1,%2"; 2117} 2118 [(set_attr "type" "imul") 2119 (set_attr "mode" "SI")]) 2120 2121(define_insn "<u>mulsidi3_32bit_r4000" 2122 [(set (match_operand:DI 0 "register_operand" "=d") 2123 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2124 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2125 (clobber (match_scratch:DI 3 "=x"))] 2126 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP && ISA_HAS_MULT" 2127 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0" 2128 [(set_attr "type" "imul") 2129 (set_attr "mode" "SI") 2130 (set_attr "insn_count" "3")]) 2131 2132(define_insn_and_split "<u>mulsidi3_64bit" 2133 [(set (match_operand:DI 0 "register_operand" "=d") 2134 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2135 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2136 (clobber (match_scratch:TI 3 "=x")) 2137 (clobber (match_scratch:DI 4 "=d"))] 2138 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3 2139 && !TARGET_MIPS16 && ISA_HAS_MULT" 2140 "#" 2141 "&& reload_completed" 2142 [(const_int 0)] 2143{ 2144 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1], 2145 operands[2], operands[4])); 2146 DONE; 2147} 2148 [(set_attr "type" "imul") 2149 (set_attr "mode" "SI") 2150 (set (attr "insn_count") 2151 (if_then_else (match_test "ISA_HAS_EXT_INS") 2152 (const_int 4) 2153 (const_int 7)))]) 2154 2155(define_expand "<u>mulsidi3_64bit_mips16" 2156 [(set (match_operand:DI 0 "register_operand") 2157 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2158 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2159 "TARGET_64BIT && TARGET_MIPS16" 2160{ 2161 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1], 2162 operands[2], gen_reg_rtx (DImode))); 2163 DONE; 2164}) 2165 2166(define_expand "<u>mulsidi3_64bit_split" 2167 [(set (match_operand:DI 0 "register_operand") 2168 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2169 (any_extend:DI (match_operand:SI 2 "register_operand")))) 2170 (clobber (match_operand:DI 3 "register_operand"))] 2171 "" 2172{ 2173 rtx hilo; 2174 2175 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2176 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2])); 2177 2178 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM)); 2179 emit_insn (gen_mfhidi_ti (operands[3], hilo)); 2180 2181 if (ISA_HAS_EXT_INS) 2182 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32), 2183 operands[3])); 2184 else 2185 { 2186 /* Zero-extend the low part. */ 2187 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32)); 2188 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32)); 2189 2190 /* Shift the high part into place. */ 2191 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32)); 2192 2193 /* OR the two halves together. */ 2194 mips_emit_binary (IOR, operands[0], operands[0], operands[3]); 2195 } 2196 DONE; 2197}) 2198 2199(define_insn "<u>mulsidi3_64bit_hilo" 2200 [(set (match_operand:TI 0 "muldiv_target_operand" "=x") 2201 (unspec:TI 2202 [(mult:DI 2203 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2204 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))] 2205 UNSPEC_SET_HILO))] 2206 "TARGET_64BIT && !TARGET_FIX_R4000" 2207 "mult<u>\t%1,%2" 2208 [(set_attr "type" "imul") 2209 (set_attr "mode" "SI")]) 2210 2211;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn. 2212(define_insn "mulsidi3_64bit_dmul" 2213 [(set (match_operand:DI 0 "register_operand" "=d") 2214 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) 2215 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2216 (clobber (match_scratch:DI 3 "=l"))] 2217 "ISA_HAS_DMUL3" 2218 "dmul\t%0,%1,%2" 2219 [(set_attr "type" "imul3") 2220 (set_attr "mode" "DI")]) 2221 2222(define_insn "mulsidi3_64bit_r6dmul" 2223 [(set (match_operand:DI 0 "register_operand" "=d") 2224 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) 2225 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] 2226 "ISA_HAS_R6DMUL" 2227 "dmul\t%0,%1,%2" 2228 [(set_attr "type" "imul3nc") 2229 (set_attr "mode" "DI")]) 2230 2231;; Widening multiply with negation. 2232(define_insn "*muls<u>_di" 2233 [(set (match_operand:DI 0 "muldiv_target_operand" "=x") 2234 (neg:DI 2235 (mult:DI 2236 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2237 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] 2238 "!TARGET_64BIT && ISA_HAS_MULS" 2239 "muls<u>\t$0,%1,%2" 2240 [(set_attr "type" "imul") 2241 (set_attr "mode" "SI")]) 2242 2243;; As well as being named patterns, these instructions are used by the 2244;; __builtin_mips_msub<u>() functions. We must always make those functions 2245;; available if !TARGET_64BIT && ISA_HAS_DSP. 2246;; 2247;; This leads to a slight inconsistency. We honor any tuning overrides 2248;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp, 2249;; even if !ISA_HAS_DSP_MULT. 2250(define_insn "<u>msubsidi4" 2251 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") 2252 (minus:DI 2253 (match_operand:DI 3 "muldiv_target_operand" "0") 2254 (mult:DI 2255 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2256 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] 2257 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)" 2258{ 2259 if (ISA_HAS_DSP_MULT) 2260 return "msub<u>\t%q0,%1,%2"; 2261 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB) 2262 return "msub<u>\t%1,%2"; 2263 else 2264 return "msac<u>\t$0,%1,%2"; 2265} 2266 [(set_attr "type" "imadd") 2267 (set_attr "accum_in" "3") 2268 (set_attr "mode" "SI")]) 2269 2270;; _highpart patterns 2271 2272(define_expand "<su>mulsi3_highpart" 2273 [(set (match_operand:SI 0 "register_operand") 2274 (truncate:SI 2275 (lshiftrt:DI 2276 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2277 (any_extend:DI (match_operand:SI 2 "register_operand"))) 2278 (const_int 32))))] 2279 "" 2280{ 2281 if (ISA_HAS_MULHI) 2282 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0], 2283 operands[1], 2284 operands[2])); 2285 else if (TARGET_MIPS16) 2286 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1], 2287 operands[2])); 2288 else if (ISA_HAS_R6MUL) 2289 emit_insn (gen_<su>mulsi3_highpart_r6 (operands[0], operands[1], 2290 operands[2])); 2291 else 2292 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1], 2293 operands[2])); 2294 DONE; 2295}) 2296 2297(define_insn "<su>mulsi3_highpart_r6" 2298 [(set (match_operand:SI 0 "register_operand" "=d") 2299 (truncate:SI 2300 (lshiftrt:DI 2301 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2302 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2303 (const_int 32))))] 2304 "ISA_HAS_R6MUL" 2305 "muh<u>\t%0,%1,%2" 2306 [(set_attr "type" "imul3nc") 2307 (set_attr "mode" "SI")]) 2308 2309(define_insn_and_split "<su>mulsi3_highpart_internal" 2310 [(set (match_operand:SI 0 "register_operand" "=d") 2311 (truncate:SI 2312 (lshiftrt:DI 2313 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2314 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2315 (const_int 32)))) 2316 (clobber (match_scratch:SI 3 "=l"))] 2317 "ISA_HAS_MULT && !ISA_HAS_MULHI && !TARGET_MIPS16" 2318 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; } 2319 "&& reload_completed && !TARGET_FIX_R4000" 2320 [(const_int 0)] 2321{ 2322 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1], 2323 operands[2])); 2324 DONE; 2325} 2326 [(set_attr "type" "imul") 2327 (set_attr "mode" "SI") 2328 (set_attr "insn_count" "2")]) 2329 2330(define_expand "<su>mulsi3_highpart_split" 2331 [(set (match_operand:SI 0 "register_operand") 2332 (truncate:SI 2333 (lshiftrt:DI 2334 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2335 (any_extend:DI (match_operand:SI 2 "register_operand"))) 2336 (const_int 32))))] 2337 "" 2338{ 2339 rtx hilo; 2340 2341 if (TARGET_64BIT) 2342 { 2343 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2344 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2])); 2345 emit_insn (gen_mfhisi_ti (operands[0], hilo)); 2346 } 2347 else 2348 { 2349 hilo = gen_rtx_REG (DImode, MD_REG_FIRST); 2350 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2])); 2351 emit_insn (gen_mfhisi_di (operands[0], hilo)); 2352 } 2353 DONE; 2354}) 2355 2356(define_insn "<su>mulsi3_highpart_mulhi_internal" 2357 [(set (match_operand:SI 0 "register_operand" "=d") 2358 (truncate:SI 2359 (lshiftrt:DI 2360 (mult:DI 2361 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2362 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2363 (const_int 32)))) 2364 (clobber (match_scratch:SI 3 "=l"))] 2365 "ISA_HAS_MULHI" 2366 "mulhi<u>\t%0,%1,%2" 2367 [(set_attr "type" "imul3") 2368 (set_attr "mode" "SI")]) 2369 2370(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal" 2371 [(set (match_operand:SI 0 "register_operand" "=d") 2372 (truncate:SI 2373 (lshiftrt:DI 2374 (neg:DI 2375 (mult:DI 2376 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2377 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2378 (const_int 32)))) 2379 (clobber (match_scratch:SI 3 "=l"))] 2380 "ISA_HAS_MULHI" 2381 "mulshi<u>\t%0,%1,%2" 2382 [(set_attr "type" "imul3") 2383 (set_attr "mode" "SI")]) 2384 2385;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120 2386;; errata MD(0), which says that dmultu does not always produce the 2387;; correct result. 2388(define_expand "<su>muldi3_highpart" 2389 [(set (match_operand:DI 0 "register_operand") 2390 (truncate:DI 2391 (lshiftrt:TI 2392 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) 2393 (any_extend:TI (match_operand:DI 2 "register_operand"))) 2394 (const_int 64))))] 2395 "ISA_HAS_R6DMUL 2396 || (ISA_HAS_DMULT 2397 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120))" 2398{ 2399 if (TARGET_MIPS16) 2400 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1], 2401 operands[2])); 2402 else if (ISA_HAS_R6DMUL) 2403 emit_insn (gen_<su>muldi3_highpart_r6 (operands[0], operands[1], 2404 operands[2])); 2405 else 2406 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1], 2407 operands[2])); 2408 DONE; 2409}) 2410 2411(define_insn "<su>muldi3_highpart_r6" 2412 [(set (match_operand:DI 0 "register_operand" "=d") 2413 (truncate:DI 2414 (lshiftrt:TI 2415 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2416 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) 2417 (const_int 64))))] 2418 "ISA_HAS_R6DMUL" 2419 "dmuh<u>\t%0,%1,%2" 2420 [(set_attr "type" "imul3nc") 2421 (set_attr "mode" "DI")]) 2422 2423(define_insn_and_split "<su>muldi3_highpart_internal" 2424 [(set (match_operand:DI 0 "register_operand" "=d") 2425 (truncate:DI 2426 (lshiftrt:TI 2427 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2428 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) 2429 (const_int 64)))) 2430 (clobber (match_scratch:DI 3 "=l"))] 2431 "ISA_HAS_DMULT 2432 && !TARGET_MIPS16 2433 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2434 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; } 2435 "&& reload_completed && !TARGET_FIX_R4000" 2436 [(const_int 0)] 2437{ 2438 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1], 2439 operands[2])); 2440 DONE; 2441} 2442 [(set_attr "type" "imul") 2443 (set_attr "mode" "DI") 2444 (set_attr "insn_count" "2")]) 2445 2446(define_expand "<su>muldi3_highpart_split" 2447 [(set (match_operand:DI 0 "register_operand") 2448 (truncate:DI 2449 (lshiftrt:TI 2450 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) 2451 (any_extend:TI (match_operand:DI 2 "register_operand"))) 2452 (const_int 64))))] 2453 "" 2454{ 2455 rtx hilo; 2456 2457 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2458 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2])); 2459 emit_insn (gen_mfhidi_ti (operands[0], hilo)); 2460 DONE; 2461}) 2462 2463(define_expand "<u>mulditi3" 2464 [(set (match_operand:TI 0 "register_operand") 2465 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) 2466 (any_extend:TI (match_operand:DI 2 "register_operand"))))] 2467 "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2468{ 2469 rtx hilo; 2470 2471 if (TARGET_MIPS16) 2472 { 2473 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2474 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2])); 2475 emit_move_insn (operands[0], hilo); 2476 } 2477 else if (TARGET_FIX_R4000) 2478 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2])); 2479 else 2480 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1], 2481 operands[2])); 2482 DONE; 2483}) 2484 2485(define_insn "<u>mulditi3_internal" 2486 [(set (match_operand:TI 0 "muldiv_target_operand" "=x") 2487 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2488 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))] 2489 "ISA_HAS_DMULT 2490 && !TARGET_FIX_R4000 2491 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2492 "dmult<u>\t%1,%2" 2493 [(set_attr "type" "imul") 2494 (set_attr "mode" "DI")]) 2495 2496(define_insn "<u>mulditi3_r4000" 2497 [(set (match_operand:TI 0 "register_operand" "=d") 2498 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2499 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))) 2500 (clobber (match_scratch:TI 3 "=x"))] 2501 "ISA_HAS_DMULT 2502 && TARGET_FIX_R4000 2503 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2504 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0" 2505 [(set_attr "type" "imul") 2506 (set_attr "mode" "DI") 2507 (set_attr "insn_count" "3")]) 2508 2509;; The R4650 supports a 32-bit multiply/ 64-bit accumulate 2510;; instruction. The HI/LO registers are used as a 64-bit accumulator. 2511 2512(define_insn "madsi" 2513 [(set (match_operand:SI 0 "register_operand" "+l") 2514 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") 2515 (match_operand:SI 2 "register_operand" "d")) 2516 (match_dup 0)))] 2517 "TARGET_MAD" 2518 "mad\t%1,%2" 2519 [(set_attr "type" "imadd") 2520 (set_attr "accum_in" "0") 2521 (set_attr "mode" "SI")]) 2522 2523;; See the comment above <u>msubsidi4 for the relationship between 2524;; ISA_HAS_DSP and ISA_HAS_DSP_MULT. 2525(define_insn "<u>maddsidi4" 2526 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") 2527 (plus:DI 2528 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2529 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2530 (match_operand:DI 3 "muldiv_target_operand" "0")))] 2531 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP) 2532 && !TARGET_64BIT" 2533{ 2534 if (TARGET_MAD) 2535 return "mad<u>\t%1,%2"; 2536 else if (ISA_HAS_DSP_MULT) 2537 return "madd<u>\t%q0,%1,%2"; 2538 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500) 2539 return "madd<u>\t%1,%2"; 2540 else 2541 /* See comment in *macc. */ 2542 return "%[macc<u>\t%@,%1,%2%]"; 2543} 2544 [(set_attr "type" "imadd") 2545 (set_attr "accum_in" "3") 2546 (set_attr "mode" "SI")]) 2547 2548;; Floating point multiply accumulate instructions. 2549 2550(define_expand "fma<mode>4" 2551 [(set (match_operand:ANYF 0 "register_operand") 2552 (fma:ANYF (match_operand:ANYF 1 "register_operand") 2553 (match_operand:ANYF 2 "register_operand") 2554 (match_operand:ANYF 3 "register_operand")))] 2555 "ISA_HAS_FUSED_MADDF || ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4") 2556 2557(define_insn "*fma<mode>4_madd3" 2558 [(set (match_operand:ANYF 0 "register_operand" "=f") 2559 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2560 (match_operand:ANYF 2 "register_operand" "f") 2561 (match_operand:ANYF 3 "register_operand" "0")))] 2562 "ISA_HAS_FUSED_MADD3" 2563 "madd.<fmt>\t%0,%1,%2" 2564 [(set_attr "type" "fmadd") 2565 (set_attr "mode" "<UNITMODE>")]) 2566 2567(define_insn "*fma<mode>4_madd4" 2568 [(set (match_operand:ANYF 0 "register_operand" "=f") 2569 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2570 (match_operand:ANYF 2 "register_operand" "f") 2571 (match_operand:ANYF 3 "register_operand" "f")))] 2572 "ISA_HAS_FUSED_MADD4" 2573 "madd.<fmt>\t%0,%3,%1,%2" 2574 [(set_attr "type" "fmadd") 2575 (set_attr "mode" "<UNITMODE>")]) 2576 2577(define_insn "*fma<mode>4_maddf" 2578 [(set (match_operand:ANYF 0 "register_operand" "=f") 2579 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2580 (match_operand:ANYF 2 "register_operand" "f") 2581 (match_operand:ANYF 3 "register_operand" "0")))] 2582 "ISA_HAS_FUSED_MADDF" 2583 "maddf.<fmt>\t%0,%1,%2" 2584 [(set_attr "type" "fmadd") 2585 (set_attr "mode" "<UNITMODE>")]) 2586 2587;; The fms, fnma, and fnms instructions can be used even when HONOR_NANS 2588;; is true because while IEEE 754-2008 requires the negate operation to 2589;; negate the sign of a NAN and the MIPS neg instruction does not do this, 2590;; the fma part of the instruction has no requirement on how the sign of 2591;; a NAN is handled and so the final sign bit of the entire operation is 2592;; undefined. 2593 2594(define_expand "fms<mode>4" 2595 [(set (match_operand:ANYF 0 "register_operand") 2596 (fma:ANYF (match_operand:ANYF 1 "register_operand") 2597 (match_operand:ANYF 2 "register_operand") 2598 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))] 2599 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)") 2600 2601(define_insn "*fms<mode>4_msub3" 2602 [(set (match_operand:ANYF 0 "register_operand" "=f") 2603 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2604 (match_operand:ANYF 2 "register_operand" "f") 2605 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))] 2606 "ISA_HAS_FUSED_MADD3" 2607 "msub.<fmt>\t%0,%1,%2" 2608 [(set_attr "type" "fmadd") 2609 (set_attr "mode" "<UNITMODE>")]) 2610 2611(define_insn "*fms<mode>4_msub4" 2612 [(set (match_operand:ANYF 0 "register_operand" "=f") 2613 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2614 (match_operand:ANYF 2 "register_operand" "f") 2615 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))] 2616 "ISA_HAS_FUSED_MADD4" 2617 "msub.<fmt>\t%0,%3,%1,%2" 2618 [(set_attr "type" "fmadd") 2619 (set_attr "mode" "<UNITMODE>")]) 2620 2621;; fnma is defined in GCC as (fma (neg op1) op2 op3) 2622;; (-op1 * op2) + op3 ==> -(op1 * op2) + op3 ==> -((op1 * op2) - op3) 2623;; The mips nmsub instructions implement -((op1 * op2) - op3) 2624;; This transformation means we may return the wrong signed zero 2625;; so we check HONOR_SIGNED_ZEROS. 2626 2627(define_expand "fnma<mode>4" 2628 [(set (match_operand:ANYF 0 "register_operand") 2629 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand")) 2630 (match_operand:ANYF 2 "register_operand") 2631 (match_operand:ANYF 3 "register_operand")))] 2632 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4) 2633 && !HONOR_SIGNED_ZEROS (<MODE>mode)") 2634 2635(define_insn "*fnma<mode>4_nmsub3" 2636 [(set (match_operand:ANYF 0 "register_operand" "=f") 2637 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2638 (match_operand:ANYF 2 "register_operand" "f") 2639 (match_operand:ANYF 3 "register_operand" "0")))] 2640 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2641 "nmsub.<fmt>\t%0,%1,%2" 2642 [(set_attr "type" "fmadd") 2643 (set_attr "mode" "<UNITMODE>")]) 2644 2645(define_insn "*fnma<mode>4_nmsub4" 2646 [(set (match_operand:ANYF 0 "register_operand" "=f") 2647 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2648 (match_operand:ANYF 2 "register_operand" "f") 2649 (match_operand:ANYF 3 "register_operand" "f")))] 2650 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2651 "nmsub.<fmt>\t%0,%3,%1,%2" 2652 [(set_attr "type" "fmadd") 2653 (set_attr "mode" "<UNITMODE>")]) 2654 2655;; fnms is defined as: (fma (neg op1) op2 (neg op3)) 2656;; ((-op1) * op2) - op3 ==> -(op1 * op2) - op3 ==> -((op1 * op2) + op3) 2657;; The mips nmadd instructions implement -((op1 * op2) + op3) 2658;; This transformation means we may return the wrong signed zero 2659;; so we check HONOR_SIGNED_ZEROS. 2660 2661(define_expand "fnms<mode>4" 2662 [(set (match_operand:ANYF 0 "register_operand") 2663 (fma:ANYF 2664 (neg:ANYF (match_operand:ANYF 1 "register_operand")) 2665 (match_operand:ANYF 2 "register_operand") 2666 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))] 2667 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4) 2668 && !HONOR_SIGNED_ZEROS (<MODE>mode)") 2669 2670(define_insn "*fnms<mode>4_nmadd3" 2671 [(set (match_operand:ANYF 0 "register_operand" "=f") 2672 (fma:ANYF 2673 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2674 (match_operand:ANYF 2 "register_operand" "f") 2675 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))] 2676 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2677 "nmadd.<fmt>\t%0,%1,%2" 2678 [(set_attr "type" "fmadd") 2679 (set_attr "mode" "<UNITMODE>")]) 2680 2681(define_insn "*fnms<mode>4_nmadd4" 2682 [(set (match_operand:ANYF 0 "register_operand" "=f") 2683 (fma:ANYF 2684 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2685 (match_operand:ANYF 2 "register_operand" "f") 2686 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))] 2687 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2688 "nmadd.<fmt>\t%0,%3,%1,%2" 2689 [(set_attr "type" "fmadd") 2690 (set_attr "mode" "<UNITMODE>")]) 2691 2692;; Non-fused Floating point multiply accumulate instructions. 2693 2694;; These instructions are not fused and round in between the multiply 2695;; and the add (or subtract) so they are equivalent to the separate 2696;; multiply and add/sub instructions. 2697 2698(define_insn "*madd4<mode>" 2699 [(set (match_operand:ANYF 0 "register_operand" "=f") 2700 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2701 (match_operand:ANYF 2 "register_operand" "f")) 2702 (match_operand:ANYF 3 "register_operand" "f")))] 2703 "ISA_HAS_UNFUSED_MADD4" 2704 "madd.<fmt>\t%0,%3,%1,%2" 2705 [(set_attr "type" "fmadd") 2706 (set_attr "mode" "<UNITMODE>")]) 2707 2708(define_insn "*msub4<mode>" 2709 [(set (match_operand:ANYF 0 "register_operand" "=f") 2710 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2711 (match_operand:ANYF 2 "register_operand" "f")) 2712 (match_operand:ANYF 3 "register_operand" "f")))] 2713 "ISA_HAS_UNFUSED_MADD4" 2714 "msub.<fmt>\t%0,%3,%1,%2" 2715 [(set_attr "type" "fmadd") 2716 (set_attr "mode" "<UNITMODE>")]) 2717 2718;; Like with the fused fms, fnma, and fnms instructions, these unfused 2719;; instructions can be used even if HONOR_NANS is set because while 2720;; IEEE 754-2008 requires the negate operation to negate the sign of a 2721;; NAN and the MIPS neg instruction does not do this, the multiply and 2722;; add (or subtract) part of the instruction has no requirement on how 2723;; the sign of a NAN is handled and so the final sign bit of the entire 2724;; operation is undefined. 2725 2726(define_insn "*nmadd4<mode>" 2727 [(set (match_operand:ANYF 0 "register_operand" "=f") 2728 (neg:ANYF (plus:ANYF 2729 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2730 (match_operand:ANYF 2 "register_operand" "f")) 2731 (match_operand:ANYF 3 "register_operand" "f"))))] 2732 "ISA_HAS_UNFUSED_MADD4" 2733 "nmadd.<fmt>\t%0,%3,%1,%2" 2734 [(set_attr "type" "fmadd") 2735 (set_attr "mode" "<UNITMODE>")]) 2736 2737(define_insn "*nmsub4<mode>" 2738 [(set (match_operand:ANYF 0 "register_operand" "=f") 2739 (neg:ANYF (minus:ANYF 2740 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2741 (match_operand:ANYF 2 "register_operand" "f")) 2742 (match_operand:ANYF 3 "register_operand" "f"))))] 2743 "ISA_HAS_UNFUSED_MADD4" 2744 "nmsub.<fmt>\t%0,%3,%1,%2" 2745 [(set_attr "type" "fmadd") 2746 (set_attr "mode" "<UNITMODE>")]) 2747 2748;; Fast-math Non-fused Floating point multiply accumulate instructions. 2749 2750;; These instructions are not fused but the expressions they match are 2751;; not exactly what the instruction implements in the sense that they 2752;; may not generate the properly signed zeros. 2753 2754;; This instruction recognizes ((-op1) * op2) - op3 and generates an 2755;; nmadd which is really -((op1 * op2) + op3). They are equivalent 2756;; except for the sign bit when the result is zero or NaN. 2757 2758(define_insn "*nmadd4<mode>_fastmath" 2759 [(set (match_operand:ANYF 0 "register_operand" "=f") 2760 (minus:ANYF 2761 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2762 (match_operand:ANYF 2 "register_operand" "f")) 2763 (match_operand:ANYF 3 "register_operand" "f")))] 2764 "ISA_HAS_UNFUSED_MADD4 2765 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2766 "nmadd.<fmt>\t%0,%3,%1,%2" 2767 [(set_attr "type" "fmadd") 2768 (set_attr "mode" "<UNITMODE>")]) 2769 2770;; This instruction recognizes (op1 - (op2 * op3) and generates an 2771;; nmsub which is really -((op2 * op3) - op1). They are equivalent 2772;; except for the sign bit when the result is zero or NaN. 2773 2774(define_insn "*nmsub4<mode>_fastmath" 2775 [(set (match_operand:ANYF 0 "register_operand" "=f") 2776 (minus:ANYF 2777 (match_operand:ANYF 1 "register_operand" "f") 2778 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") 2779 (match_operand:ANYF 3 "register_operand" "f"))))] 2780 "ISA_HAS_UNFUSED_MADD4 2781 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2782 "nmsub.<fmt>\t%0,%1,%2,%3" 2783 [(set_attr "type" "fmadd") 2784 (set_attr "mode" "<UNITMODE>")]) 2785 2786;; 2787;; .................... 2788;; 2789;; DIVISION and REMAINDER 2790;; 2791;; .................... 2792;; 2793 2794(define_expand "div<mode>3" 2795 [(set (match_operand:ANYF 0 "register_operand") 2796 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand") 2797 (match_operand:ANYF 2 "register_operand")))] 2798 "<divide_condition>" 2799{ 2800 if (const_1_operand (operands[1], <MODE>mode)) 2801 if (!(ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) 2802 && flag_unsafe_math_optimizations)) 2803 operands[1] = force_reg (<MODE>mode, operands[1]); 2804}) 2805 2806;; These patterns work around the early SB-1 rev2 core "F1" erratum: 2807;; 2808;; If an mfc1 or dmfc1 happens to access the floating point register 2809;; file at the same time a long latency operation (div, sqrt, recip, 2810;; sqrt) iterates an intermediate result back through the floating 2811;; point register file bypass, then instead returning the correct 2812;; register value the mfc1 or dmfc1 operation returns the intermediate 2813;; result of the long latency operation. 2814;; 2815;; The workaround is to insert an unconditional 'mov' from/to the 2816;; long latency op destination register. 2817 2818(define_insn "*div<mode>3" 2819 [(set (match_operand:ANYF 0 "register_operand" "=f") 2820 (div:ANYF (match_operand:ANYF 1 "register_operand" "f") 2821 (match_operand:ANYF 2 "register_operand" "f")))] 2822 "<divide_condition>" 2823{ 2824 if (TARGET_FIX_SB1) 2825 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0"; 2826 else 2827 return "div.<fmt>\t%0,%1,%2"; 2828} 2829 [(set_attr "type" "fdiv") 2830 (set_attr "mode" "<UNITMODE>") 2831 (set (attr "insn_count") 2832 (if_then_else (match_test "TARGET_FIX_SB1") 2833 (const_int 2) 2834 (const_int 1)))]) 2835 2836(define_insn "*recip<mode>3" 2837 [(set (match_operand:ANYF 0 "register_operand" "=f") 2838 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 2839 (match_operand:ANYF 2 "register_operand" "f")))] 2840 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" 2841{ 2842 if (TARGET_FIX_SB1) 2843 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 2844 else 2845 return "recip.<fmt>\t%0,%2"; 2846} 2847 [(set_attr "type" "frdiv") 2848 (set_attr "mode" "<UNITMODE>") 2849 (set (attr "insn_count") 2850 (if_then_else (match_test "TARGET_FIX_SB1") 2851 (const_int 2) 2852 (const_int 1)))]) 2853 2854;; VR4120 errata MD(A1): signed division instructions do not work correctly 2855;; with negative operands. We use special libgcc functions instead. 2856(define_expand "divmod<mode>4" 2857 [(parallel 2858 [(set (match_operand:GPR 0 "register_operand") 2859 (div:GPR (match_operand:GPR 1 "register_operand") 2860 (match_operand:GPR 2 "register_operand"))) 2861 (set (match_operand:GPR 3 "register_operand") 2862 (mod:GPR (match_dup 1) 2863 (match_dup 2)))])] 2864 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120" 2865{ 2866 if (TARGET_MIPS16) 2867 { 2868 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM); 2869 emit_insn (gen_divmod<mode>4_mips16 (operands[0], operands[1], 2870 operands[2], operands[3], lo)); 2871 DONE; 2872 } 2873}) 2874 2875(define_insn_and_split "*divmod<mode>4" 2876 [(set (match_operand:GPR 0 "register_operand" "=l") 2877 (div:GPR (match_operand:GPR 1 "register_operand" "d") 2878 (match_operand:GPR 2 "register_operand" "d"))) 2879 (set (match_operand:GPR 3 "register_operand" "=d") 2880 (mod:GPR (match_dup 1) 2881 (match_dup 2)))] 2882 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && !TARGET_MIPS16" 2883 "#" 2884 "&& reload_completed" 2885 [(const_int 0)] 2886{ 2887 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2])); 2888 DONE; 2889} 2890 [(set_attr "type" "idiv") 2891 (set_attr "mode" "<MODE>") 2892 (set_attr "insn_count" "2")]) 2893 2894;; Expand generates divmod instructions for individual division and modulus 2895;; operations. We then rely on CSE to reuse earlier divmods where possible. 2896;; This means that, when generating MIPS16 code, it is better not to expose 2897;; the fixed LO register until after CSE has finished. However, it's still 2898;; better to split before register allocation, so that we don't allocate 2899;; one of the scarce MIPS16 registers to an unused result. 2900(define_insn_and_split "divmod<mode>4_mips16" 2901 [(set (match_operand:GPR 0 "register_operand" "=d") 2902 (div:GPR (match_operand:GPR 1 "register_operand" "d") 2903 (match_operand:GPR 2 "register_operand" "d"))) 2904 (set (match_operand:GPR 3 "register_operand" "=d") 2905 (mod:GPR (match_dup 1) 2906 (match_dup 2))) 2907 (clobber (match_operand:GPR 4 "lo_operand" "=l"))] 2908 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && TARGET_MIPS16" 2909 "#" 2910 "&& cse_not_expected" 2911 [(const_int 0)] 2912{ 2913 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2])); 2914 emit_move_insn (operands[0], operands[4]); 2915 DONE; 2916} 2917 [(set_attr "type" "idiv") 2918 (set_attr "mode" "<MODE>") 2919 (set_attr "insn_count" "3")]) 2920 2921(define_expand "udivmod<mode>4" 2922 [(parallel 2923 [(set (match_operand:GPR 0 "register_operand") 2924 (udiv:GPR (match_operand:GPR 1 "register_operand") 2925 (match_operand:GPR 2 "register_operand"))) 2926 (set (match_operand:GPR 3 "register_operand") 2927 (umod:GPR (match_dup 1) 2928 (match_dup 2)))])] 2929 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120" 2930{ 2931 if (TARGET_MIPS16) 2932 { 2933 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM); 2934 emit_insn (gen_udivmod<mode>4_mips16 (operands[0], operands[1], 2935 operands[2], operands[3], lo)); 2936 DONE; 2937 } 2938}) 2939 2940(define_insn_and_split "*udivmod<mode>4" 2941 [(set (match_operand:GPR 0 "register_operand" "=l") 2942 (udiv:GPR (match_operand:GPR 1 "register_operand" "d") 2943 (match_operand:GPR 2 "register_operand" "d"))) 2944 (set (match_operand:GPR 3 "register_operand" "=d") 2945 (umod:GPR (match_dup 1) 2946 (match_dup 2)))] 2947 "ISA_HAS_<D>DIV && !TARGET_MIPS16" 2948 "#" 2949 "reload_completed" 2950 [(const_int 0)] 2951{ 2952 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2])); 2953 DONE; 2954} 2955 [(set_attr "type" "idiv") 2956 (set_attr "mode" "<MODE>") 2957 (set_attr "insn_count" "2")]) 2958 2959;; See the comment above "divmod<mode>4_mips16" for the split timing. 2960(define_insn_and_split "udivmod<mode>4_mips16" 2961 [(set (match_operand:GPR 0 "register_operand" "=d") 2962 (udiv:GPR (match_operand:GPR 1 "register_operand" "d") 2963 (match_operand:GPR 2 "register_operand" "d"))) 2964 (set (match_operand:GPR 3 "register_operand" "=d") 2965 (umod:GPR (match_dup 1) 2966 (match_dup 2))) 2967 (clobber (match_operand:GPR 4 "lo_operand" "=l"))] 2968 "ISA_HAS_<D>DIV && TARGET_MIPS16" 2969 "#" 2970 "cse_not_expected" 2971 [(const_int 0)] 2972{ 2973 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2])); 2974 emit_move_insn (operands[0], operands[4]); 2975 DONE; 2976} 2977 [(set_attr "type" "idiv") 2978 (set_attr "mode" "<MODE>") 2979 (set_attr "insn_count" "3")]) 2980 2981(define_expand "<u>divmod<mode>4_split" 2982 [(set (match_operand:GPR 0 "register_operand") 2983 (any_mod:GPR (match_operand:GPR 1 "register_operand") 2984 (match_operand:GPR 2 "register_operand")))] 2985 "" 2986{ 2987 rtx hilo; 2988 2989 if (TARGET_64BIT) 2990 { 2991 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2992 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1], 2993 operands[2])); 2994 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo)); 2995 } 2996 else 2997 { 2998 hilo = gen_rtx_REG (DImode, MD_REG_FIRST); 2999 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1], 3000 operands[2])); 3001 emit_insn (gen_mfhi<mode>_di (operands[0], hilo)); 3002 } 3003 DONE; 3004}) 3005 3006(define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>" 3007 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x") 3008 (unspec:HILO 3009 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d") 3010 (match_operand:GPR 2 "register_operand" "d"))] 3011 UNSPEC_SET_HILO))] 3012 "ISA_HAS_<GPR:D>DIV" 3013 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); } 3014 [(set_attr "type" "idiv") 3015 (set_attr "mode" "<GPR:MODE>")]) 3016 3017;; Integer division and modulus. 3018 3019(define_insn "<u>div<mode>3" 3020 [(set (match_operand:GPR 0 "register_operand" "=&d") 3021 (any_div:GPR (match_operand:GPR 1 "register_operand" "d") 3022 (match_operand:GPR 2 "register_operand" "d")))] 3023 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>DIV" 3024 { 3025 if (TARGET_LOONGSON_2EF) 3026 return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands); 3027 else if (TARGET_LOONGSON_EXT) 3028 return mips_output_division ("gs<d>div<u>\t%0,%1,%2", operands); 3029 else 3030 return mips_output_division ("<d>div<u>\t%0,%1,%2", operands); 3031 } 3032 [(set_attr "type" "idiv3") 3033 (set_attr "mode" "<MODE>")]) 3034 3035(define_insn "<u>mod<mode>3" 3036 [(set (match_operand:GPR 0 "register_operand" "=&d") 3037 (any_mod:GPR (match_operand:GPR 1 "register_operand" "d") 3038 (match_operand:GPR 2 "register_operand" "d")))] 3039 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>DIV" 3040 { 3041 if (TARGET_LOONGSON_2EF) 3042 return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands); 3043 else if (TARGET_LOONGSON_EXT) 3044 return mips_output_division ("gs<d>mod<u>\t%0,%1,%2", operands); 3045 else 3046 return mips_output_division ("<d>mod<u>\t%0,%1,%2", operands); 3047 } 3048 [(set_attr "type" "idiv3") 3049 (set_attr "mode" "<MODE>")]) 3050 3051;; 3052;; .................... 3053;; 3054;; SQUARE ROOT 3055;; 3056;; .................... 3057 3058;; These patterns work around the early SB-1 rev2 core "F1" erratum (see 3059;; "*div[sd]f3" comment for details). 3060 3061(define_insn "sqrt<mode>2" 3062 [(set (match_operand:ANYF 0 "register_operand" "=f") 3063 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 3064 "<sqrt_condition>" 3065{ 3066 if (TARGET_FIX_SB1) 3067 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0"; 3068 else 3069 return "sqrt.<fmt>\t%0,%1"; 3070} 3071 [(set_attr "type" "fsqrt") 3072 (set_attr "mode" "<UNITMODE>") 3073 (set (attr "insn_count") 3074 (if_then_else (match_test "TARGET_FIX_SB1") 3075 (const_int 2) 3076 (const_int 1)))]) 3077 3078(define_insn "*rsqrt<mode>a" 3079 [(set (match_operand:ANYF 0 "register_operand" "=f") 3080 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 3081 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))] 3082 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" 3083{ 3084 if (TARGET_FIX_SB1) 3085 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 3086 else 3087 return "rsqrt.<fmt>\t%0,%2"; 3088} 3089 [(set_attr "type" "frsqrt") 3090 (set_attr "mode" "<UNITMODE>") 3091 (set (attr "insn_count") 3092 (if_then_else (match_test "TARGET_FIX_SB1") 3093 (const_int 2) 3094 (const_int 1)))]) 3095 3096(define_insn "*rsqrt<mode>b" 3097 [(set (match_operand:ANYF 0 "register_operand" "=f") 3098 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 3099 (match_operand:ANYF 2 "register_operand" "f"))))] 3100 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" 3101{ 3102 if (TARGET_FIX_SB1) 3103 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 3104 else 3105 return "rsqrt.<fmt>\t%0,%2"; 3106} 3107 [(set_attr "type" "frsqrt") 3108 (set_attr "mode" "<UNITMODE>") 3109 (set (attr "insn_count") 3110 (if_then_else (match_test "TARGET_FIX_SB1") 3111 (const_int 2) 3112 (const_int 1)))]) 3113 3114;; 3115;; .................... 3116;; 3117;; ABSOLUTE VALUE 3118;; 3119;; .................... 3120 3121;; Do not use the integer abs macro instruction, since that signals an 3122;; exception on -2147483648 (sigh). 3123 3124;; The "legacy" (as opposed to "2008") form of ABS.fmt is an arithmetic 3125;; instruction that treats all NaN inputs as invalid; it does not clear 3126;; their sign bit. We therefore can't use that form if the signs of 3127;; NaNs matter. 3128 3129(define_insn "abs<mode>2" 3130 [(set (match_operand:ANYF 0 "register_operand" "=f") 3131 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 3132 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)" 3133 "abs.<fmt>\t%0,%1" 3134 [(set_attr "type" "fabs") 3135 (set_attr "mode" "<UNITMODE>")]) 3136 3137;; 3138;; ................... 3139;; 3140;; Count leading zeroes. 3141;; 3142;; ................... 3143;; 3144 3145(define_insn "clz<mode>2" 3146 [(set (match_operand:GPR 0 "register_operand" "=d") 3147 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))] 3148 "ISA_HAS_CLZ_CLO" 3149 "<d>clz\t%0,%1" 3150 [(set_attr "type" "clz") 3151 (set_attr "mode" "<MODE>")]) 3152 3153;; 3154;; ................... 3155;; 3156;; Count trailing zeroes. 3157;; 3158;; ................... 3159;; 3160 3161(define_insn "ctz<mode>2" 3162 [(set (match_operand:GPR 0 "register_operand" "=d") 3163 (ctz:GPR (match_operand:GPR 1 "register_operand" "d")))] 3164 "ISA_HAS_CTZ_CTO" 3165 "<d>ctz\t%0,%1" 3166 [(set_attr "type" "clz") 3167 (set_attr "mode" "<MODE>")]) 3168 3169 3170;; 3171;; ................... 3172;; 3173;; Count number of set bits. 3174;; 3175;; ................... 3176;; 3177 3178(define_insn "popcount<mode>2" 3179 [(set (match_operand:GPR 0 "register_operand" "=d") 3180 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))] 3181 "ISA_HAS_POP" 3182 "<d>pop\t%0,%1" 3183 [(set_attr "type" "pop") 3184 (set_attr "mode" "<MODE>")]) 3185 3186;; The POP instruction is special as it does not take into account the upper 3187;; 32bits and is documented that way. 3188(define_insn "*popcountdi2_trunc" 3189 [(set (match_operand:SI 0 "register_operand" "=d") 3190 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))] 3191 "ISA_HAS_POP && TARGET_64BIT" 3192 "pop\t%0,%1" 3193 [(set_attr "type" "pop") 3194 (set_attr "mode" "SI")]) 3195 3196;; 3197;; .................... 3198;; 3199;; NEGATION and ONE'S COMPLEMENT 3200;; 3201;; .................... 3202 3203(define_insn "negsi2" 3204 [(set (match_operand:SI 0 "register_operand" "=d") 3205 (neg:SI (match_operand:SI 1 "register_operand" "d")))] 3206 "" 3207{ 3208 if (TARGET_MIPS16) 3209 return "neg\t%0,%1"; 3210 else 3211 return "subu\t%0,%.,%1"; 3212} 3213 [(set_attr "alu_type" "sub") 3214 (set_attr "mode" "SI")]) 3215 3216(define_insn "negdi2" 3217 [(set (match_operand:DI 0 "register_operand" "=d") 3218 (neg:DI (match_operand:DI 1 "register_operand" "d")))] 3219 "TARGET_64BIT && !TARGET_MIPS16" 3220 "dsubu\t%0,%.,%1" 3221 [(set_attr "alu_type" "sub") 3222 (set_attr "mode" "DI")]) 3223 3224;; The "legacy" (as opposed to "2008") form of NEG.fmt is an arithmetic 3225;; instruction that treats all NaN inputs as invalid; it does not flip 3226;; their sign bit. We therefore can't use that form if the signs of 3227;; NaNs matter. 3228 3229(define_insn "neg<mode>2" 3230 [(set (match_operand:ANYF 0 "register_operand" "=f") 3231 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 3232 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)" 3233 "neg.<fmt>\t%0,%1" 3234 [(set_attr "type" "fneg") 3235 (set_attr "mode" "<UNITMODE>")]) 3236 3237(define_insn "one_cmpl<mode>2" 3238 [(set (match_operand:GPR 0 "register_operand" "=!u,d") 3239 (not:GPR (match_operand:GPR 1 "register_operand" "!u,d")))] 3240 "" 3241{ 3242 if (TARGET_MIPS16) 3243 return "not\t%0,%1"; 3244 else 3245 return "nor\t%0,%.,%1"; 3246} 3247 [(set_attr "alu_type" "not") 3248 (set_attr "compression" "micromips,*") 3249 (set_attr "mode" "<MODE>")]) 3250 3251;; 3252;; .................... 3253;; 3254;; LOGICAL 3255;; 3256;; .................... 3257;; 3258 3259;; Many of these instructions use trivial define_expands, because we 3260;; want to use a different set of constraints when TARGET_MIPS16. 3261 3262(define_expand "and<mode>3" 3263 [(set (match_operand:GPR 0 "register_operand") 3264 (and:GPR (match_operand:GPR 1 "register_operand") 3265 (match_operand:GPR 2 "and_reg_operand")))]) 3266 3267;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a 3268;; zero_extendsidi2 because of TARGET_TRULY_NOOP_TRUNCATION, so handle these 3269;; here. Note that this variant does not trigger for SI mode because we 3270;; require a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical 3271;; sign-extended SImode value. 3272;; 3273;; These are possible combinations for operand 1 and 2. The table 3274;; includes both MIPS and MIPS16 cases. (r=register, mem=memory, 3275;; 16=MIPS16, x=match, S=split): 3276;; 3277;; \ op1 r/EXT r/!EXT mem r/16 mem/16 3278;; op2 3279;; 3280;; andi x x 3281;; 0xff x x x x 3282;; 0xffff x x x x 3283;; 0xffff_ffff x S x S x 3284;; low-bitmask x 3285;; register x x 3286;; register =op1 x 3287 3288(define_insn "*and<mode>3" 3289 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d") 3290 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d") 3291 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d")))] 3292 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])" 3293{ 3294 int len; 3295 3296 switch (which_alternative) 3297 { 3298 case 0: 3299 operands[1] = gen_lowpart (QImode, operands[1]); 3300 return "lbu\t%0,%1"; 3301 case 1: 3302 operands[1] = gen_lowpart (HImode, operands[1]); 3303 return "lhu\t%0,%1"; 3304 case 2: 3305 operands[1] = gen_lowpart (SImode, operands[1]); 3306 return "lwu\t%0,%1"; 3307 case 3: 3308 case 4: 3309 return "andi\t%0,%1,%x2"; 3310 case 5: 3311 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2])); 3312 operands[2] = GEN_INT (len); 3313 return "<d>ext\t%0,%1,0,%2"; 3314 case 6: 3315 return "#"; 3316 case 7: 3317 case 8: 3318 return "and\t%0,%1,%2"; 3319 default: 3320 gcc_unreachable (); 3321 } 3322} 3323 [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical") 3324 (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*") 3325 (set_attr "mode" "<MODE>")]) 3326 3327(define_insn "*and<mode>3_mips16" 3328 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") 3329 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0") 3330 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))] 3331 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])" 3332{ 3333 switch (which_alternative) 3334 { 3335 case 0: 3336 operands[1] = gen_lowpart (QImode, operands[1]); 3337 return "lbu\t%0,%1"; 3338 case 1: 3339 operands[1] = gen_lowpart (HImode, operands[1]); 3340 return "lhu\t%0,%1"; 3341 case 2: 3342 operands[1] = gen_lowpart (SImode, operands[1]); 3343 return "lwu\t%0,%1"; 3344 case 3: 3345 return "#"; 3346 case 4: 3347 return "and\t%0,%2"; 3348 default: 3349 gcc_unreachable (); 3350 } 3351} 3352 [(set_attr "move_type" "load,load,load,shift_shift,logical") 3353 (set_attr "mode" "<MODE>")]) 3354 3355(define_expand "ior<mode>3" 3356 [(set (match_operand:GPR 0 "register_operand") 3357 (ior:GPR (match_operand:GPR 1 "register_operand") 3358 (match_operand:GPR 2 "uns_arith_operand")))] 3359 "" 3360{ 3361 if (TARGET_MIPS16) 3362 operands[2] = force_reg (<MODE>mode, operands[2]); 3363}) 3364 3365(define_insn "*ior<mode>3" 3366 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") 3367 (ior:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") 3368 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))] 3369 "!TARGET_MIPS16" 3370 "@ 3371 or\t%0,%1,%2 3372 or\t%0,%1,%2 3373 ori\t%0,%1,%x2" 3374 [(set_attr "alu_type" "or") 3375 (set_attr "compression" "micromips,*,*") 3376 (set_attr "mode" "<MODE>")]) 3377 3378(define_insn "*ior<mode>3_mips16" 3379 [(set (match_operand:GPR 0 "register_operand" "=d") 3380 (ior:GPR (match_operand:GPR 1 "register_operand" "%0") 3381 (match_operand:GPR 2 "register_operand" "d")))] 3382 "TARGET_MIPS16" 3383 "or\t%0,%2" 3384 [(set_attr "alu_type" "or") 3385 (set_attr "mode" "<MODE>")]) 3386 3387(define_expand "xor<mode>3" 3388 [(set (match_operand:GPR 0 "register_operand") 3389 (xor:GPR (match_operand:GPR 1 "register_operand") 3390 (match_operand:GPR 2 "uns_arith_operand")))] 3391 "" 3392 "") 3393 3394(define_insn "*xor<mode>3" 3395 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") 3396 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") 3397 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))] 3398 "!TARGET_MIPS16" 3399 "@ 3400 xor\t%0,%1,%2 3401 xor\t%0,%1,%2 3402 xori\t%0,%1,%x2" 3403 [(set_attr "alu_type" "xor") 3404 (set_attr "compression" "micromips,*,*") 3405 (set_attr "mode" "<MODE>")]) 3406 3407(define_insn "*xor<mode>3_mips16" 3408 [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t") 3409 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d") 3410 (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d")))] 3411 "TARGET_MIPS16" 3412 "@ 3413 xor\t%0,%2 3414 cmpi\t%1,%2 3415 cmpi\t%1,%2 3416 cmp\t%1,%2" 3417 [(set_attr "alu_type" "xor") 3418 (set_attr "mode" "<MODE>") 3419 (set_attr "extended_mips16" "no,no,yes,no")]) 3420 3421(define_insn "*nor<mode>3" 3422 [(set (match_operand:GPR 0 "register_operand" "=d") 3423 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 3424 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))] 3425 "!TARGET_MIPS16" 3426 "nor\t%0,%1,%2" 3427 [(set_attr "alu_type" "nor") 3428 (set_attr "mode" "<MODE>")]) 3429 3430;; 3431;; .................... 3432;; 3433;; TRUNCATION 3434;; 3435;; .................... 3436 3437 3438 3439(define_insn "truncdfsf2" 3440 [(set (match_operand:SF 0 "register_operand" "=f") 3441 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] 3442 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3443 "cvt.s.d\t%0,%1" 3444 [(set_attr "type" "fcvt") 3445 (set_attr "cnv_mode" "D2S") 3446 (set_attr "mode" "SF")]) 3447 3448;; Integer truncation patterns. Truncating SImode values to smaller 3449;; modes is a no-op, as it is for most other GCC ports. Truncating 3450;; DImode values to SImode is not a no-op for TARGET_64BIT since we 3451;; need to make sure that the lower 32 bits are properly sign-extended 3452;; (see TARGET_TRULY_NOOP_TRUNCATION). Truncating DImode values into modes 3453;; smaller than SImode is equivalent to two separate truncations: 3454;; 3455;; A B 3456;; DI ---> HI == DI ---> SI ---> HI 3457;; DI ---> QI == DI ---> SI ---> QI 3458;; 3459;; Step A needs a real instruction but step B does not. 3460 3461(define_insn "truncdi<mode>2" 3462 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m") 3463 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))] 3464 "TARGET_64BIT" 3465 "@ 3466 sll\t%0,%1,0 3467 <store>\t%1,%0" 3468 [(set_attr "move_type" "sll0,store") 3469 (set_attr "mode" "SI")]) 3470 3471;; Combiner patterns to optimize shift/truncate combinations. 3472 3473(define_insn "*ashr_trunc<mode>" 3474 [(set (match_operand:SUBDI 0 "register_operand" "=d") 3475 (truncate:SUBDI 3476 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") 3477 (match_operand:DI 2 "const_arith_operand" ""))))] 3478 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)" 3479 "dsra\t%0,%1,%2" 3480 [(set_attr "type" "shift") 3481 (set_attr "mode" "<MODE>")]) 3482 3483(define_insn "*lshr32_trunc<mode>" 3484 [(set (match_operand:SUBDI 0 "register_operand" "=d") 3485 (truncate:SUBDI 3486 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") 3487 (const_int 32))))] 3488 "TARGET_64BIT && !TARGET_MIPS16" 3489 "dsra\t%0,%1,32" 3490 [(set_attr "type" "shift") 3491 (set_attr "mode" "<MODE>")]) 3492 3493;; Logical shift by more than 32 results in proper SI values so truncation is 3494;; removed by the middle end. Note that a logical shift by 32 is handled by 3495;; the previous pattern. 3496(define_insn "*<optab>_trunc<mode>_exts" 3497 [(set (match_operand:SUBDI 0 "register_operand" "=d") 3498 (truncate:SUBDI 3499 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d") 3500 (match_operand:DI 2 "const_arith_operand" ""))))] 3501 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32" 3502 "exts\t%0,%1,%2,31" 3503 [(set_attr "type" "arith") 3504 (set_attr "mode" "<MODE>")]) 3505 3506;; This could likely be generalized for any SUBDI mode, and any right 3507;; shift, but AFAICT this is used so rarely it is not worth the additional 3508;; complexity. 3509(define_insn "" 3510 [(set (match_operand:SI 0 "register_operand" "=d") 3511 (ashiftrt:SI 3512 (truncate:SI 3513 (ashift:DI (match_operand:DI 1 "register_operand" "d") 3514 (match_operand:DI 2 "const_arith_operand" ""))) 3515 (match_operand:DI 3 "const_arith_operand" "")))] 3516 "(ISA_HAS_EXTS && TARGET_64BIT 3517 && UINTVAL (operands[2]) < 32 && UINTVAL (operands[3]) < 32 3518 && UINTVAL (operands[3]) >= UINTVAL (operands[2]))" 3519 { 3520 rtx xoperands[4]; 3521 xoperands[0] = operands[0]; 3522 xoperands[1] = operands[1]; 3523 3524 /* The length of the field is the size of the outer mode less the outer 3525 shift constant. We fix the outer mode as SImode for simplicity. */ 3526 unsigned int right_shift = INTVAL (operands[3]); 3527 xoperands[3] = GEN_INT (32 - right_shift); 3528 3529 /* The field starts at the outer shift constant less the inner shift 3530 constant. */ 3531 unsigned int left_shift = INTVAL (operands[2]); 3532 xoperands[2] = GEN_INT (right_shift - left_shift); 3533 3534 /* Sanity checks. These constraints are taken from the MIPS ISA 3535 manual. */ 3536 gcc_assert (INTVAL (xoperands[2]) >= 0 && INTVAL (xoperands[2]) < 32); 3537 gcc_assert (INTVAL (xoperands[3]) > 0 && INTVAL (xoperands[3]) <= 32); 3538 gcc_assert (INTVAL (xoperands[2]) + INTVAL (xoperands[3]) > 0 3539 && INTVAL (xoperands[2]) + INTVAL (xoperands[3]) <= 32); 3540 3541 output_asm_insn ("exts\t%0,%1,%2,%m3", xoperands); 3542 return ""; 3543 } 3544 [(set_attr "type" "arith") 3545 (set_attr "mode" "SI")]) 3546 3547;; 3548;; .................... 3549;; 3550;; ZERO EXTENSION 3551;; 3552;; .................... 3553 3554;; Extension insns. 3555 3556(define_expand "zero_extendsidi2" 3557 [(set (match_operand:DI 0 "register_operand") 3558 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))] 3559 "TARGET_64BIT") 3560 3561(define_insn_and_split "*zero_extendsidi2" 3562 [(set (match_operand:DI 0 "register_operand" "=d,d") 3563 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] 3564 "TARGET_64BIT && !ISA_HAS_EXT_INS" 3565 "@ 3566 # 3567 lwu\t%0,%1" 3568 "&& reload_completed && REG_P (operands[1])" 3569 [(set (match_dup 0) 3570 (ashift:DI (match_dup 1) (const_int 32))) 3571 (set (match_dup 0) 3572 (lshiftrt:DI (match_dup 0) (const_int 32)))] 3573 { operands[1] = gen_lowpart (DImode, operands[1]); } 3574 [(set_attr "move_type" "shift_shift,load") 3575 (set_attr "mode" "DI")]) 3576 3577(define_insn "*zero_extendsidi2_dext" 3578 [(set (match_operand:DI 0 "register_operand" "=d,d") 3579 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] 3580 "TARGET_64BIT && ISA_HAS_EXT_INS" 3581 "@ 3582 dext\t%0,%1,0,32 3583 lwu\t%0,%1" 3584 [(set_attr "move_type" "arith,load") 3585 (set_attr "mode" "DI")]) 3586 3587;; See the comment before the *and<mode>3 pattern why this is generated by 3588;; combine. 3589 3590(define_split 3591 [(set (match_operand:DI 0 "register_operand") 3592 (and:DI (match_operand:DI 1 "register_operand") 3593 (const_int 4294967295)))] 3594 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed" 3595 [(set (match_dup 0) 3596 (ashift:DI (match_dup 1) (const_int 32))) 3597 (set (match_dup 0) 3598 (lshiftrt:DI (match_dup 0) (const_int 32)))]) 3599 3600(define_expand "zero_extend<SHORT:mode><GPR:mode>2" 3601 [(set (match_operand:GPR 0 "register_operand") 3602 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] 3603 "" 3604{ 3605 if (TARGET_MIPS16 && !GENERATE_MIPS16E 3606 && !memory_operand (operands[1], <SHORT:MODE>mode)) 3607 { 3608 emit_insn (gen_and<GPR:mode>3 (operands[0], 3609 gen_lowpart (<GPR:MODE>mode, operands[1]), 3610 force_reg (<GPR:MODE>mode, 3611 GEN_INT (<SHORT:mask>)))); 3612 DONE; 3613 } 3614}) 3615 3616(define_insn "*zero_extend<SHORT:mode><GPR:mode>2" 3617 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") 3618 (zero_extend:GPR 3619 (match_operand:SHORT 1 "nonimmediate_operand" "!u,d,m")))] 3620 "!TARGET_MIPS16" 3621 "@ 3622 andi\t%0,%1,<SHORT:mask> 3623 andi\t%0,%1,<SHORT:mask> 3624 l<SHORT:size>u\t%0,%1" 3625 [(set_attr "move_type" "andi,andi,load") 3626 (set_attr "compression" "micromips,*,*") 3627 (set_attr "mode" "<GPR:MODE>")]) 3628 3629(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e" 3630 [(set (match_operand:GPR 0 "register_operand" "=d") 3631 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))] 3632 "GENERATE_MIPS16E" 3633 "ze<SHORT:size>\t%0" 3634 ;; This instruction is effectively a special encoding of ANDI. 3635 [(set_attr "move_type" "andi") 3636 (set_attr "mode" "<GPR:MODE>")]) 3637 3638(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16" 3639 [(set (match_operand:GPR 0 "register_operand" "=d") 3640 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))] 3641 "TARGET_MIPS16" 3642 "l<SHORT:size>u\t%0,%1" 3643 [(set_attr "move_type" "load") 3644 (set_attr "mode" "<GPR:MODE>")]) 3645 3646(define_expand "zero_extendqihi2" 3647 [(set (match_operand:HI 0 "register_operand") 3648 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))] 3649 "" 3650{ 3651 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode)) 3652 { 3653 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]), 3654 operands[1])); 3655 DONE; 3656 } 3657}) 3658 3659(define_insn "*zero_extendqihi2" 3660 [(set (match_operand:HI 0 "register_operand" "=d,d") 3661 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 3662 "!TARGET_MIPS16" 3663 "@ 3664 andi\t%0,%1,0x00ff 3665 lbu\t%0,%1" 3666 [(set_attr "move_type" "andi,load") 3667 (set_attr "mode" "HI")]) 3668 3669(define_insn "*zero_extendqihi2_mips16" 3670 [(set (match_operand:HI 0 "register_operand" "=d") 3671 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 3672 "TARGET_MIPS16" 3673 "lbu\t%0,%1" 3674 [(set_attr "move_type" "load") 3675 (set_attr "mode" "HI")]) 3676 3677;; Combiner patterns to optimize truncate/zero_extend combinations. 3678 3679(define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>" 3680 [(set (match_operand:GPR 0 "register_operand" "=d") 3681 (zero_extend:GPR 3682 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3683 "TARGET_64BIT && !TARGET_MIPS16" 3684{ 3685 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode)); 3686 return "andi\t%0,%1,%x2"; 3687} 3688 [(set_attr "alu_type" "and") 3689 (set_attr "mode" "<GPR:MODE>")]) 3690 3691(define_insn "*zero_extendhi_truncqi" 3692 [(set (match_operand:HI 0 "register_operand" "=d") 3693 (zero_extend:HI 3694 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 3695 "TARGET_64BIT && !TARGET_MIPS16" 3696 "andi\t%0,%1,0xff" 3697 [(set_attr "alu_type" "and") 3698 (set_attr "mode" "HI")]) 3699 3700;; 3701;; .................... 3702;; 3703;; SIGN EXTENSION 3704;; 3705;; .................... 3706 3707;; Extension insns. 3708;; Those for integer source operand are ordered widest source type first. 3709 3710;; When TARGET_64BIT, all SImode integer and accumulator registers 3711;; should already be in sign-extended form (see TARGET_TRULY_NOOP_TRUNCATION 3712;; and truncdisi2). We can therefore get rid of register->register 3713;; instructions if we constrain the source to be in the same register as 3714;; the destination. 3715;; 3716;; Only the pre-reload scheduler sees the type of the register alternatives; 3717;; we split them into nothing before the post-reload scheduler runs. 3718;; These alternatives therefore have type "move" in order to reflect 3719;; what happens if the two pre-reload operands cannot be tied, and are 3720;; instead allocated two separate GPRs. We don't distinguish between 3721;; the GPR and LO cases because we don't usually know during pre-reload 3722;; scheduling whether an operand will be LO or not. 3723(define_insn_and_split "extendsidi2" 3724 [(set (match_operand:DI 0 "register_operand" "=d,l,d") 3725 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))] 3726 "TARGET_64BIT" 3727 "@ 3728 # 3729 # 3730 lw\t%0,%1" 3731 "&& reload_completed && register_operand (operands[1], VOIDmode)" 3732 [(const_int 0)] 3733{ 3734 emit_note (NOTE_INSN_DELETED); 3735 DONE; 3736} 3737 [(set_attr "move_type" "move,move,load") 3738 (set_attr "mode" "DI")]) 3739 3740(define_expand "extend<SHORT:mode><GPR:mode>2" 3741 [(set (match_operand:GPR 0 "register_operand") 3742 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] 3743 "") 3744 3745(define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e" 3746 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3747 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))] 3748 "GENERATE_MIPS16E" 3749 "@ 3750 se<SHORT:size>\t%0 3751 l<SHORT:size>\t%0,%1" 3752 [(set_attr "move_type" "signext,load") 3753 (set_attr "mode" "<GPR:MODE>")]) 3754 3755(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2" 3756 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3757 (sign_extend:GPR 3758 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] 3759 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E" 3760 "@ 3761 # 3762 l<SHORT:size>\t%0,%1" 3763 "&& reload_completed && REG_P (operands[1])" 3764 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2))) 3765 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))] 3766{ 3767 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]); 3768 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode) 3769 - GET_MODE_BITSIZE (<SHORT:MODE>mode)); 3770} 3771 [(set_attr "move_type" "shift_shift,load") 3772 (set_attr "mode" "<GPR:MODE>")]) 3773 3774(define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>" 3775 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3776 (sign_extend:GPR 3777 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] 3778 "ISA_HAS_SEB_SEH" 3779 "@ 3780 se<SHORT:size>\t%0,%1 3781 l<SHORT:size>\t%0,%1" 3782 [(set_attr "move_type" "signext,load") 3783 (set_attr "mode" "<GPR:MODE>")]) 3784 3785(define_expand "extendqihi2" 3786 [(set (match_operand:HI 0 "register_operand") 3787 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))] 3788 "") 3789 3790(define_insn "*extendqihi2_mips16e" 3791 [(set (match_operand:HI 0 "register_operand" "=d,d") 3792 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))] 3793 "GENERATE_MIPS16E" 3794 "@ 3795 seb\t%0 3796 lb\t%0,%1" 3797 [(set_attr "move_type" "signext,load") 3798 (set_attr "mode" "SI")]) 3799 3800(define_insn_and_split "*extendqihi2" 3801 [(set (match_operand:HI 0 "register_operand" "=d,d") 3802 (sign_extend:HI 3803 (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 3804 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E" 3805 "@ 3806 # 3807 lb\t%0,%1" 3808 "&& reload_completed && REG_P (operands[1])" 3809 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) 3810 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))] 3811{ 3812 operands[0] = gen_lowpart (SImode, operands[0]); 3813 operands[1] = gen_lowpart (SImode, operands[1]); 3814 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode) 3815 - GET_MODE_BITSIZE (QImode)); 3816} 3817 [(set_attr "move_type" "shift_shift,load") 3818 (set_attr "mode" "SI")]) 3819 3820(define_insn "*extendqihi2_seb" 3821 [(set (match_operand:HI 0 "register_operand" "=d,d") 3822 (sign_extend:HI 3823 (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 3824 "ISA_HAS_SEB_SEH" 3825 "@ 3826 seb\t%0,%1 3827 lb\t%0,%1" 3828 [(set_attr "move_type" "signext,load") 3829 (set_attr "mode" "SI")]) 3830 3831;; Combiner patterns for truncate/sign_extend combinations. The SI versions 3832;; use the shift/truncate patterns. 3833 3834(define_insn_and_split "*extenddi_truncate<mode>" 3835 [(set (match_operand:DI 0 "register_operand" "=d") 3836 (sign_extend:DI 3837 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3838 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS" 3839 "#" 3840 "&& reload_completed" 3841 [(set (match_dup 2) 3842 (ashift:DI (match_dup 1) 3843 (match_dup 3))) 3844 (set (match_dup 0) 3845 (ashiftrt:DI (match_dup 2) 3846 (match_dup 3)))] 3847{ 3848 operands[2] = gen_lowpart (DImode, operands[0]); 3849 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode)); 3850} 3851 [(set_attr "move_type" "shift_shift") 3852 (set_attr "mode" "DI")]) 3853 3854(define_insn_and_split "*extendsi_truncate<mode>" 3855 [(set (match_operand:SI 0 "register_operand" "=d") 3856 (sign_extend:SI 3857 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3858 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS" 3859 "#" 3860 "&& reload_completed" 3861 [(set (match_dup 2) 3862 (ashift:DI (match_dup 1) 3863 (match_dup 3))) 3864 (set (match_dup 0) 3865 (truncate:SI (ashiftrt:DI (match_dup 2) 3866 (match_dup 3))))] 3867{ 3868 operands[2] = gen_lowpart (DImode, operands[0]); 3869 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode)); 3870} 3871 [(set_attr "move_type" "shift_shift") 3872 (set_attr "mode" "SI")]) 3873 3874(define_insn_and_split "*extendhi_truncateqi" 3875 [(set (match_operand:HI 0 "register_operand" "=d") 3876 (sign_extend:HI 3877 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 3878 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS" 3879 "#" 3880 "&& reload_completed" 3881 [(set (match_dup 2) 3882 (ashift:DI (match_dup 1) 3883 (const_int 56))) 3884 (set (match_dup 0) 3885 (truncate:HI (ashiftrt:DI (match_dup 2) 3886 (const_int 56))))] 3887{ 3888 operands[2] = gen_lowpart (DImode, operands[0]); 3889} 3890 [(set_attr "move_type" "shift_shift") 3891 (set_attr "mode" "SI")]) 3892 3893(define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts" 3894 [(set (match_operand:GPR 0 "register_operand" "=d") 3895 (sign_extend:GPR 3896 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3897 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS" 3898{ 3899 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode)); 3900 return "exts\t%0,%1,0,%m2"; 3901} 3902 [(set_attr "type" "arith") 3903 (set_attr "mode" "<GPR:MODE>")]) 3904 3905(define_insn "*extendhi_truncateqi_exts" 3906 [(set (match_operand:HI 0 "register_operand" "=d") 3907 (sign_extend:HI 3908 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 3909 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS" 3910 "exts\t%0,%1,0,7" 3911 [(set_attr "type" "arith") 3912 (set_attr "mode" "SI")]) 3913 3914(define_insn "extendsfdf2" 3915 [(set (match_operand:DF 0 "register_operand" "=f") 3916 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 3917 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3918 "cvt.d.s\t%0,%1" 3919 [(set_attr "type" "fcvt") 3920 (set_attr "cnv_mode" "S2D") 3921 (set_attr "mode" "DF")]) 3922 3923;; 3924;; .................... 3925;; 3926;; CONVERSIONS 3927;; 3928;; .................... 3929 3930(define_expand "fix_truncdfsi2" 3931 [(set (match_operand:SI 0 "register_operand") 3932 (fix:SI (match_operand:DF 1 "register_operand")))] 3933 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3934{ 3935 if (!ISA_HAS_TRUNC_W) 3936 { 3937 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1])); 3938 DONE; 3939 } 3940}) 3941 3942(define_insn "fix_truncdfsi2_insn" 3943 [(set (match_operand:SI 0 "register_operand" "=f") 3944 (fix:SI (match_operand:DF 1 "register_operand" "f")))] 3945 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W" 3946 "trunc.w.d %0,%1" 3947 [(set_attr "type" "fcvt") 3948 (set_attr "mode" "DF") 3949 (set_attr "cnv_mode" "D2I")]) 3950 3951(define_insn "fix_truncdfsi2_macro" 3952 [(set (match_operand:SI 0 "register_operand" "=f") 3953 (fix:SI (match_operand:DF 1 "register_operand" "f"))) 3954 (clobber (match_scratch:DF 2 "=d"))] 3955 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W" 3956{ 3957 if (mips_nomacro.nesting_level > 0) 3958 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro"; 3959 else 3960 return "trunc.w.d %0,%1,%2"; 3961} 3962 [(set_attr "type" "fcvt") 3963 (set_attr "mode" "DF") 3964 (set_attr "cnv_mode" "D2I") 3965 (set_attr "insn_count" "9")]) 3966 3967(define_expand "fix_truncsfsi2" 3968 [(set (match_operand:SI 0 "register_operand") 3969 (fix:SI (match_operand:SF 1 "register_operand")))] 3970 "TARGET_HARD_FLOAT" 3971{ 3972 if (!ISA_HAS_TRUNC_W) 3973 { 3974 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1])); 3975 DONE; 3976 } 3977}) 3978 3979(define_insn "fix_truncsfsi2_insn" 3980 [(set (match_operand:SI 0 "register_operand" "=f") 3981 (fix:SI (match_operand:SF 1 "register_operand" "f")))] 3982 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W" 3983 "trunc.w.s %0,%1" 3984 [(set_attr "type" "fcvt") 3985 (set_attr "mode" "SF") 3986 (set_attr "cnv_mode" "S2I")]) 3987 3988(define_insn "fix_truncsfsi2_macro" 3989 [(set (match_operand:SI 0 "register_operand" "=f") 3990 (fix:SI (match_operand:SF 1 "register_operand" "f"))) 3991 (clobber (match_scratch:SF 2 "=d"))] 3992 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W" 3993{ 3994 if (mips_nomacro.nesting_level > 0) 3995 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro"; 3996 else 3997 return "trunc.w.s %0,%1,%2"; 3998} 3999 [(set_attr "type" "fcvt") 4000 (set_attr "mode" "SF") 4001 (set_attr "cnv_mode" "S2I") 4002 (set_attr "insn_count" "9")]) 4003 4004 4005(define_insn "fix_truncdfdi2" 4006 [(set (match_operand:DI 0 "register_operand" "=f") 4007 (fix:DI (match_operand:DF 1 "register_operand" "f")))] 4008 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 4009 "trunc.l.d %0,%1" 4010 [(set_attr "type" "fcvt") 4011 (set_attr "mode" "DF") 4012 (set_attr "cnv_mode" "D2I")]) 4013 4014 4015(define_insn "fix_truncsfdi2" 4016 [(set (match_operand:DI 0 "register_operand" "=f") 4017 (fix:DI (match_operand:SF 1 "register_operand" "f")))] 4018 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 4019 "trunc.l.s %0,%1" 4020 [(set_attr "type" "fcvt") 4021 (set_attr "mode" "SF") 4022 (set_attr "cnv_mode" "S2I")]) 4023 4024 4025(define_insn "floatsidf2" 4026 [(set (match_operand:DF 0 "register_operand" "=f") 4027 (float:DF (match_operand:SI 1 "register_operand" "f")))] 4028 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 4029 "cvt.d.w\t%0,%1" 4030 [(set_attr "type" "fcvt") 4031 (set_attr "mode" "DF") 4032 (set_attr "cnv_mode" "I2D")]) 4033 4034 4035(define_insn "floatdidf2" 4036 [(set (match_operand:DF 0 "register_operand" "=f") 4037 (float:DF (match_operand:DI 1 "register_operand" "f")))] 4038 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 4039 "cvt.d.l\t%0,%1" 4040 [(set_attr "type" "fcvt") 4041 (set_attr "mode" "DF") 4042 (set_attr "cnv_mode" "I2D")]) 4043 4044 4045(define_insn "floatsisf2" 4046 [(set (match_operand:SF 0 "register_operand" "=f") 4047 (float:SF (match_operand:SI 1 "register_operand" "f")))] 4048 "TARGET_HARD_FLOAT" 4049 "cvt.s.w\t%0,%1" 4050 [(set_attr "type" "fcvt") 4051 (set_attr "mode" "SF") 4052 (set_attr "cnv_mode" "I2S")]) 4053 4054 4055(define_insn "floatdisf2" 4056 [(set (match_operand:SF 0 "register_operand" "=f") 4057 (float:SF (match_operand:DI 1 "register_operand" "f")))] 4058 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 4059 "cvt.s.l\t%0,%1" 4060 [(set_attr "type" "fcvt") 4061 (set_attr "mode" "SF") 4062 (set_attr "cnv_mode" "I2S")]) 4063 4064 4065(define_expand "fixuns_truncdfsi2" 4066 [(set (match_operand:SI 0 "register_operand") 4067 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))] 4068 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 4069{ 4070 rtx reg1 = gen_reg_rtx (DFmode); 4071 rtx reg2 = gen_reg_rtx (DFmode); 4072 rtx reg3 = gen_reg_rtx (SImode); 4073 rtx_code_label *label1 = gen_label_rtx (); 4074 rtx_code_label *label2 = gen_label_rtx (); 4075 rtx test; 4076 REAL_VALUE_TYPE offset; 4077 4078 real_2expN (&offset, 31, DFmode); 4079 4080 if (reg1) /* Turn off complaints about unreached code. */ 4081 { 4082 mips_emit_move (reg1, const_double_from_real_value (offset, DFmode)); 4083 do_pending_stack_adjust (); 4084 4085 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 4086 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1)); 4087 4088 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1])); 4089 emit_jump_insn (gen_rtx_SET (pc_rtx, 4090 gen_rtx_LABEL_REF (VOIDmode, label2))); 4091 emit_barrier (); 4092 4093 emit_label (label1); 4094 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); 4095 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode 4096 (BITMASK_HIGH, SImode))); 4097 4098 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2)); 4099 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); 4100 4101 emit_label (label2); 4102 4103 /* Allow REG_NOTES to be set on last insn (labels don't have enough 4104 fields, and can't be used for REG_NOTES anyway). */ 4105 emit_use (stack_pointer_rtx); 4106 DONE; 4107 } 4108}) 4109 4110 4111(define_expand "fixuns_truncdfdi2" 4112 [(set (match_operand:DI 0 "register_operand") 4113 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))] 4114 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" 4115{ 4116 rtx reg1 = gen_reg_rtx (DFmode); 4117 rtx reg2 = gen_reg_rtx (DFmode); 4118 rtx reg3 = gen_reg_rtx (DImode); 4119 rtx_code_label *label1 = gen_label_rtx (); 4120 rtx_code_label *label2 = gen_label_rtx (); 4121 rtx test; 4122 REAL_VALUE_TYPE offset; 4123 4124 real_2expN (&offset, 63, DFmode); 4125 4126 mips_emit_move (reg1, const_double_from_real_value (offset, DFmode)); 4127 do_pending_stack_adjust (); 4128 4129 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 4130 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1)); 4131 4132 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1])); 4133 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2))); 4134 emit_barrier (); 4135 4136 emit_label (label1); 4137 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); 4138 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH)); 4139 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); 4140 4141 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2)); 4142 emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); 4143 4144 emit_label (label2); 4145 4146 /* Allow REG_NOTES to be set on last insn (labels don't have enough 4147 fields, and can't be used for REG_NOTES anyway). */ 4148 emit_use (stack_pointer_rtx); 4149 DONE; 4150}) 4151 4152 4153(define_expand "fixuns_truncsfsi2" 4154 [(set (match_operand:SI 0 "register_operand") 4155 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))] 4156 "TARGET_HARD_FLOAT" 4157{ 4158 rtx reg1 = gen_reg_rtx (SFmode); 4159 rtx reg2 = gen_reg_rtx (SFmode); 4160 rtx reg3 = gen_reg_rtx (SImode); 4161 rtx_code_label *label1 = gen_label_rtx (); 4162 rtx_code_label *label2 = gen_label_rtx (); 4163 rtx test; 4164 REAL_VALUE_TYPE offset; 4165 4166 real_2expN (&offset, 31, SFmode); 4167 4168 mips_emit_move (reg1, const_double_from_real_value (offset, SFmode)); 4169 do_pending_stack_adjust (); 4170 4171 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 4172 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1)); 4173 4174 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1])); 4175 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2))); 4176 emit_barrier (); 4177 4178 emit_label (label1); 4179 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); 4180 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode 4181 (BITMASK_HIGH, SImode))); 4182 4183 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2)); 4184 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); 4185 4186 emit_label (label2); 4187 4188 /* Allow REG_NOTES to be set on last insn (labels don't have enough 4189 fields, and can't be used for REG_NOTES anyway). */ 4190 emit_use (stack_pointer_rtx); 4191 DONE; 4192}) 4193 4194 4195(define_expand "fixuns_truncsfdi2" 4196 [(set (match_operand:DI 0 "register_operand") 4197 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))] 4198 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" 4199{ 4200 rtx reg1 = gen_reg_rtx (SFmode); 4201 rtx reg2 = gen_reg_rtx (SFmode); 4202 rtx reg3 = gen_reg_rtx (DImode); 4203 rtx_code_label *label1 = gen_label_rtx (); 4204 rtx_code_label *label2 = gen_label_rtx (); 4205 rtx test; 4206 REAL_VALUE_TYPE offset; 4207 4208 real_2expN (&offset, 63, SFmode); 4209 4210 mips_emit_move (reg1, const_double_from_real_value (offset, SFmode)); 4211 do_pending_stack_adjust (); 4212 4213 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 4214 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1)); 4215 4216 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1])); 4217 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2))); 4218 emit_barrier (); 4219 4220 emit_label (label1); 4221 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); 4222 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH)); 4223 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); 4224 4225 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2)); 4226 emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); 4227 4228 emit_label (label2); 4229 4230 /* Allow REG_NOTES to be set on last insn (labels don't have enough 4231 fields, and can't be used for REG_NOTES anyway). */ 4232 emit_use (stack_pointer_rtx); 4233 DONE; 4234}) 4235 4236;; 4237;; .................... 4238;; 4239;; DATA MOVEMENT 4240;; 4241;; .................... 4242 4243;; Bit field extract patterns which use lwl/lwr or ldl/ldr. 4244 4245(define_expand "extvmisalign<mode>" 4246 [(set (match_operand:GPR 0 "register_operand") 4247 (sign_extract:GPR (match_operand:BLK 1 "memory_operand") 4248 (match_operand 2 "const_int_operand") 4249 (match_operand 3 "const_int_operand")))] 4250 "ISA_HAS_LWL_LWR" 4251{ 4252 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], 4253 INTVAL (operands[2]), 4254 INTVAL (operands[3]), 4255 /*unsigned=*/ false)) 4256 DONE; 4257 else 4258 FAIL; 4259}) 4260 4261(define_expand "extv<mode>" 4262 [(set (match_operand:GPR 0 "register_operand") 4263 (sign_extract:GPR (match_operand:GPR 1 "register_operand") 4264 (match_operand 2 "const_int_operand") 4265 (match_operand 3 "const_int_operand")))] 4266 "ISA_HAS_EXTS" 4267{ 4268 if (UINTVAL (operands[2]) > 32) 4269 FAIL; 4270}) 4271 4272(define_insn "*extv<mode>" 4273 [(set (match_operand:GPR 0 "register_operand" "=d") 4274 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d") 4275 (match_operand 2 "const_int_operand" "") 4276 (match_operand 3 "const_int_operand" "")))] 4277 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32" 4278 "exts\t%0,%1,%3,%m2" 4279 [(set_attr "type" "arith") 4280 (set_attr "mode" "<MODE>")]) 4281 4282(define_expand "extzvmisalign<mode>" 4283 [(set (match_operand:GPR 0 "register_operand") 4284 (zero_extract:GPR (match_operand:BLK 1 "memory_operand") 4285 (match_operand 2 "const_int_operand") 4286 (match_operand 3 "const_int_operand")))] 4287 "ISA_HAS_LWL_LWR" 4288{ 4289 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], 4290 INTVAL (operands[2]), 4291 INTVAL (operands[3]), 4292 /*unsigned=*/ true)) 4293 DONE; 4294 else 4295 FAIL; 4296}) 4297 4298(define_expand "extzv<mode>" 4299 [(set (match_operand:GPR 0 "register_operand") 4300 (zero_extract:GPR (match_operand:GPR 1 "register_operand") 4301 (match_operand 2 "const_int_operand") 4302 (match_operand 3 "const_int_operand")))] 4303 "" 4304{ 4305 if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]), 4306 INTVAL (operands[3]))) 4307 FAIL; 4308}) 4309 4310(define_insn "*extzv<mode>" 4311 [(set (match_operand:GPR 0 "register_operand" "=d") 4312 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d") 4313 (match_operand 2 "const_int_operand" "") 4314 (match_operand 3 "const_int_operand" "")))] 4315 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]), 4316 INTVAL (operands[3]))" 4317 "<d>ext\t%0,%1,%3,%2" 4318 [(set_attr "type" "arith") 4319 (set_attr "mode" "<MODE>")]) 4320 4321(define_insn "*extzv_truncsi_exts" 4322 [(set (match_operand:SI 0 "register_operand" "=d") 4323 (truncate:SI 4324 (zero_extract:DI (match_operand:DI 1 "register_operand" "d") 4325 (match_operand 2 "const_int_operand" "") 4326 (match_operand 3 "const_int_operand" ""))))] 4327 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)" 4328 "exts\t%0,%1,%3,31" 4329 [(set_attr "type" "arith") 4330 (set_attr "mode" "SI")]) 4331 4332 4333(define_expand "insvmisalign<mode>" 4334 [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand") 4335 (match_operand 1 "const_int_operand") 4336 (match_operand 2 "const_int_operand")) 4337 (match_operand:GPR 3 "reg_or_0_operand"))] 4338 "ISA_HAS_LWL_LWR" 4339{ 4340 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3], 4341 INTVAL (operands[1]), 4342 INTVAL (operands[2]))) 4343 DONE; 4344 else 4345 FAIL; 4346}) 4347 4348(define_expand "insv<mode>" 4349 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand") 4350 (match_operand 1 "const_int_operand") 4351 (match_operand 2 "const_int_operand")) 4352 (match_operand:GPR 3 "reg_or_0_operand"))] 4353 "" 4354{ 4355 if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]), 4356 INTVAL (operands[2]))) 4357 FAIL; 4358}) 4359 4360(define_insn "*insv<mode>" 4361 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d") 4362 (match_operand:SI 1 "const_int_operand" "") 4363 (match_operand:SI 2 "const_int_operand" "")) 4364 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))] 4365 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]), 4366 INTVAL (operands[2]))" 4367 "<d>ins\t%0,%z3,%2,%1" 4368 [(set_attr "type" "arith") 4369 (set_attr "mode" "<MODE>")]) 4370 4371;; Combiner pattern for cins (clear and insert bit field). We can 4372;; implement mask-and-shift-left operation with this. Note that if 4373;; the upper bit of the mask is set in an SImode operation, the mask 4374;; itself will be sign-extended. mask_low_and_shift_len will 4375;; therefore be greater than our threshold of 32. 4376 4377(define_insn "*cins<mode>" 4378 [(set (match_operand:GPR 0 "register_operand" "=d") 4379 (and:GPR 4380 (ashift:GPR (match_operand:GPR 1 "register_operand" "d") 4381 (match_operand:GPR 2 "const_int_operand" "")) 4382 (match_operand:GPR 3 "const_int_operand" "")))] 4383 "ISA_HAS_CINS 4384 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)" 4385{ 4386 operands[3] = 4387 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2])); 4388 return "cins\t%0,%1,%2,%m3"; 4389} 4390 [(set_attr "type" "shift") 4391 (set_attr "mode" "<MODE>")]) 4392 4393;; Unaligned word moves generated by the bit field patterns. 4394;; 4395;; As far as the rtl is concerned, both the left-part and right-part 4396;; instructions can access the whole field. However, the real operand 4397;; refers to just the first or the last byte (depending on endianness). 4398;; We therefore use two memory operands to each instruction, one to 4399;; describe the rtl effect and one to use in the assembly output. 4400;; 4401;; Operands 0 and 1 are the rtl-level target and source respectively. 4402;; This allows us to use the standard length calculations for the "load" 4403;; and "store" type attributes. 4404 4405(define_insn "mov_<load>l" 4406 [(set (match_operand:GPR 0 "register_operand" "=d") 4407 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") 4408 (match_operand:QI 2 "memory_operand" "ZC")] 4409 UNSPEC_LOAD_LEFT))] 4410 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])" 4411 "<load>l\t%0,%2" 4412 [(set_attr "move_type" "load") 4413 (set_attr "mode" "<MODE>")]) 4414 4415(define_insn "mov_<load>r" 4416 [(set (match_operand:GPR 0 "register_operand" "=d") 4417 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") 4418 (match_operand:QI 2 "memory_operand" "ZC") 4419 (match_operand:GPR 3 "register_operand" "0")] 4420 UNSPEC_LOAD_RIGHT))] 4421 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])" 4422 "<load>r\t%0,%2" 4423 [(set_attr "move_type" "load") 4424 (set_attr "mode" "<MODE>")]) 4425 4426(define_insn "mov_<store>l" 4427 [(set (match_operand:BLK 0 "memory_operand" "=m") 4428 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 4429 (match_operand:QI 2 "memory_operand" "ZC")] 4430 UNSPEC_STORE_LEFT))] 4431 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])" 4432 "<store>l\t%z1,%2" 4433 [(set_attr "move_type" "store") 4434 (set_attr "mode" "<MODE>")]) 4435 4436(define_insn "mov_<store>r" 4437 [(set (match_operand:BLK 0 "memory_operand" "+m") 4438 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 4439 (match_operand:QI 2 "memory_operand" "ZC") 4440 (match_dup 0)] 4441 UNSPEC_STORE_RIGHT))] 4442 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])" 4443 "<store>r\t%z1,%2" 4444 [(set_attr "move_type" "store") 4445 (set_attr "mode" "<MODE>")]) 4446 4447;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE. 4448;; The required value is: 4449;; 4450;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16) 4451;; 4452;; which translates to: 4453;; 4454;; lui op0,%highest(op1) 4455;; daddiu op0,op0,%higher(op1) 4456;; dsll op0,op0,16 4457;; daddiu op0,op0,%hi(op1) 4458;; dsll op0,op0,16 4459;; 4460;; The split is deferred until after flow2 to allow the peephole2 below 4461;; to take effect. 4462(define_insn_and_split "*lea_high64" 4463 [(set (match_operand:DI 0 "register_operand" "=d") 4464 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))] 4465 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" 4466 "#" 4467 "&& epilogue_completed" 4468 [(set (match_dup 0) (high:DI (match_dup 2))) 4469 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2))) 4470 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16))) 4471 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3))) 4472 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))] 4473{ 4474 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH); 4475 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID); 4476} 4477 [(set_attr "insn_count" "5")]) 4478 4479;; Use a scratch register to reduce the latency of the above pattern 4480;; on superscalar machines. The optimized sequence is: 4481;; 4482;; lui op1,%highest(op2) 4483;; lui op0,%hi(op2) 4484;; daddiu op1,op1,%higher(op2) 4485;; dsll32 op1,op1,0 4486;; daddu op1,op1,op0 4487(define_peephole2 4488 [(set (match_operand:DI 1 "d_operand") 4489 (high:DI (match_operand:DI 2 "absolute_symbolic_operand"))) 4490 (match_scratch:DI 0 "d")] 4491 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" 4492 [(set (match_dup 1) (high:DI (match_dup 3))) 4493 (set (match_dup 0) (high:DI (match_dup 4))) 4494 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3))) 4495 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32))) 4496 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))] 4497{ 4498 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH); 4499 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW); 4500}) 4501 4502;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit 4503;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine 4504;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only 4505;; used once. We can then use the sequence: 4506;; 4507;; lui op0,%highest(op1) 4508;; lui op2,%hi(op1) 4509;; daddiu op0,op0,%higher(op1) 4510;; daddiu op2,op2,%lo(op1) 4511;; dsll32 op0,op0,0 4512;; daddu op0,op0,op2 4513;; 4514;; which takes 4 cycles on most superscalar targets. 4515(define_insn_and_split "*lea64" 4516 [(set (match_operand:DI 0 "register_operand" "=d") 4517 (match_operand:DI 1 "absolute_symbolic_operand" "")) 4518 (clobber (match_scratch:DI 2 "=&d"))] 4519 "!TARGET_MIPS16 4520 && TARGET_EXPLICIT_RELOCS 4521 && ABI_HAS_64BIT_SYMBOLS 4522 && cse_not_expected" 4523 "#" 4524 "&& reload_completed" 4525 [(set (match_dup 0) (high:DI (match_dup 3))) 4526 (set (match_dup 2) (high:DI (match_dup 4))) 4527 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3))) 4528 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4))) 4529 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) 4530 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] 4531{ 4532 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH); 4533 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW); 4534} 4535 [(set_attr "insn_count" "6")]) 4536 4537;; Split HIGHs into: 4538;; 4539;; li op0,%hi(sym) 4540;; sll op0,16 4541;; 4542;; on MIPS16 targets. 4543(define_split 4544 [(set (match_operand:P 0 "d_operand") 4545 (high:P (match_operand:P 1 "symbolic_operand_with_high")))] 4546 "TARGET_MIPS16 && reload_completed" 4547 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH)) 4548 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))]) 4549 4550(define_insn "*unshifted_high" 4551 [(set (match_operand:P 0 "d_operand" "=d") 4552 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")] 4553 UNSPEC_UNSHIFTED_HIGH))] 4554 "" 4555 "li\t%0,%h1" 4556 [(set_attr "extended_mips16" "yes")]) 4557 4558;; Insns to fetch a symbol from a big GOT. 4559 4560(define_insn_and_split "*xgot_hi<mode>" 4561 [(set (match_operand:P 0 "register_operand" "=d") 4562 (high:P (match_operand:P 1 "got_disp_operand" "")))] 4563 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT" 4564 "#" 4565 "&& reload_completed" 4566 [(set (match_dup 0) (high:P (match_dup 2))) 4567 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))] 4568{ 4569 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP); 4570 operands[3] = pic_offset_table_rtx; 4571} 4572 [(set_attr "got" "xgot_high") 4573 (set_attr "mode" "<MODE>")]) 4574 4575(define_insn_and_split "*xgot_lo<mode>" 4576 [(set (match_operand:P 0 "register_operand" "=d") 4577 (lo_sum:P (match_operand:P 1 "register_operand" "d") 4578 (match_operand:P 2 "got_disp_operand" "")))] 4579 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT" 4580 "#" 4581 "&& reload_completed" 4582 [(set (match_dup 0) 4583 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))] 4584 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); } 4585 [(set_attr "got" "load") 4586 (set_attr "mode" "<MODE>")]) 4587 4588;; Insns to fetch a symbol from a normal GOT. 4589 4590(define_insn_and_split "*got_disp<mode>" 4591 [(set (match_operand:P 0 "register_operand" "=d") 4592 (match_operand:P 1 "got_disp_operand" ""))] 4593 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]" 4594 "#" 4595 "&& reload_completed" 4596 [(set (match_dup 0) (match_dup 2))] 4597 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); } 4598 [(set_attr "got" "load") 4599 (set_attr "mode" "<MODE>")]) 4600 4601;; Insns for loading the "page" part of a page/ofst address from the GOT. 4602 4603(define_insn_and_split "*got_page<mode>" 4604 [(set (match_operand:P 0 "register_operand" "=d") 4605 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))] 4606 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]" 4607 "#" 4608 "&& reload_completed" 4609 [(set (match_dup 0) (match_dup 2))] 4610 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); } 4611 [(set_attr "got" "load") 4612 (set_attr "mode" "<MODE>")]) 4613 4614;; Convenience expander that generates the rhs of a load_got<mode> insn. 4615(define_expand "unspec_got_<mode>" 4616 [(unspec:P [(match_operand:P 0) 4617 (match_operand:P 1)] UNSPEC_LOAD_GOT)]) 4618 4619;; Lower-level instructions for loading an address from the GOT. 4620;; We could use MEMs, but an unspec gives more optimization 4621;; opportunities. 4622 4623(define_insn "load_got<mode>" 4624 [(set (match_operand:P 0 "register_operand" "=d") 4625 (unspec:P [(match_operand:P 1 "register_operand" "d") 4626 (match_operand:P 2 "immediate_operand" "")] 4627 UNSPEC_LOAD_GOT))] 4628 "" 4629 "<load>\t%0,%R2(%1)" 4630 [(set_attr "got" "load") 4631 (set_attr "mode" "<MODE>")]) 4632 4633;; Instructions for adding the low 16 bits of an address to a register. 4634;; Operand 2 is the address: mips_print_operand works out which relocation 4635;; should be applied. 4636 4637(define_insn "*low<mode>" 4638 [(set (match_operand:P 0 "register_operand" "=d") 4639 (lo_sum:P (match_operand:P 1 "register_operand" "d") 4640 (match_operand:P 2 "immediate_operand" "")))] 4641 "!TARGET_MIPS16" 4642 "<d>addiu\t%0,%1,%R2" 4643 [(set_attr "alu_type" "add") 4644 (set_attr "mode" "<MODE>")]) 4645 4646(define_insn "*low<mode>_mips16" 4647 [(set (match_operand:P 0 "register_operand" "=d") 4648 (lo_sum:P (match_operand:P 1 "register_operand" "0") 4649 (match_operand:P 2 "immediate_operand" "")))] 4650 "TARGET_MIPS16" 4651 "<d>addiu\t%0,%R2" 4652 [(set_attr "alu_type" "add") 4653 (set_attr "mode" "<MODE>") 4654 (set_attr "extended_mips16" "yes")]) 4655 4656;; Expose MIPS16 uses of the global pointer after reload if the function 4657;; is responsible for setting up the register itself. 4658(define_split 4659 [(set (match_operand:GPR 0 "d_operand") 4660 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))] 4661 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed" 4662 [(set (match_dup 0) (match_dup 1))] 4663 { operands[1] = pic_offset_table_rtx; }) 4664 4665;; Allow combine to split complex const_int load sequences, using operand 2 4666;; to store the intermediate results. See move_operand for details. 4667(define_split 4668 [(set (match_operand:GPR 0 "register_operand") 4669 (match_operand:GPR 1 "splittable_const_int_operand")) 4670 (clobber (match_operand:GPR 2 "register_operand"))] 4671 "" 4672 [(const_int 0)] 4673{ 4674 mips_move_integer (operands[2], operands[0], INTVAL (operands[1])); 4675 DONE; 4676}) 4677 4678;; Likewise, for symbolic operands. 4679(define_split 4680 [(set (match_operand:P 0 "register_operand") 4681 (match_operand:P 1)) 4682 (clobber (match_operand:P 2 "register_operand"))] 4683 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)" 4684 [(set (match_dup 0) (match_dup 3))] 4685{ 4686 mips_split_symbol (operands[2], operands[1], 4687 MAX_MACHINE_MODE, &operands[3]); 4688}) 4689 4690;; 64-bit integer moves 4691 4692;; Unlike most other insns, the move insns can't be split with 4693;; different predicates, because register spilling and other parts of 4694;; the compiler, have memoized the insn number already. 4695 4696(define_expand "movdi" 4697 [(set (match_operand:DI 0 "") 4698 (match_operand:DI 1 ""))] 4699 "" 4700{ 4701 if (mips_legitimize_move (DImode, operands[0], operands[1])) 4702 DONE; 4703}) 4704 4705;; For mips16, we need a special case to handle storing $31 into 4706;; memory, since we don't have a constraint to match $31. This 4707;; instruction can be generated by save_restore_insns. 4708 4709(define_insn "*mov<mode>_ra" 4710 [(set (match_operand:GPR 0 "stack_operand" "=m") 4711 (reg:GPR RETURN_ADDR_REGNUM))] 4712 "TARGET_MIPS16" 4713 "<store>\t$31,%0" 4714 [(set_attr "move_type" "store") 4715 (set_attr "mode" "<MODE>")]) 4716 4717(define_insn "*movdi_32bit" 4718 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m") 4719 (match_operand:DI 1 "move_operand" "d,i,m,d,*J,*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))] 4720 "!TARGET_64BIT && !TARGET_MIPS16 4721 && (register_operand (operands[0], DImode) 4722 || reg_or_0_operand (operands[1], DImode))" 4723 { return mips_output_move (operands[0], operands[1]); } 4724 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore") 4725 (set (attr "mode") 4726 (if_then_else (eq_attr "move_type" "imul") 4727 (const_string "SI") 4728 (const_string "DI")))]) 4729 4730(define_insn "*movdi_32bit_mips16" 4731 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 4732 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))] 4733 "!TARGET_64BIT && TARGET_MIPS16 4734 && (register_operand (operands[0], DImode) 4735 || register_operand (operands[1], DImode))" 4736 { return mips_output_move (operands[0], operands[1]); } 4737 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 4738 (set_attr "mode" "DI")]) 4739 4740(define_insn "*movdi_64bit" 4741 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m") 4742 (match_operand:DI 1 "move_operand" "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] 4743 "TARGET_64BIT && !TARGET_MIPS16 4744 && (register_operand (operands[0], DImode) 4745 || reg_or_0_operand (operands[1], DImode))" 4746 { return mips_output_move (operands[0], operands[1]); } 4747 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore") 4748 (set_attr "mode" "DI")]) 4749 4750(define_insn "*movdi_64bit_mips16" 4751 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") 4752 (match_operand:DI 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))] 4753 "TARGET_64BIT && TARGET_MIPS16 4754 && (register_operand (operands[0], DImode) 4755 || register_operand (operands[1], DImode))" 4756 { return mips_output_move (operands[0], operands[1]); } 4757 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo") 4758 (set_attr "mode" "DI")]) 4759 4760;; On the mips16, we can split ld $r,N($r) into an add and a load, 4761;; when the original load is a 4 byte instruction but the add and the 4762;; load are 2 2 byte instructions. 4763 4764(define_split 4765 [(set (match_operand:DI 0 "d_operand") 4766 (mem:DI (plus:DI (match_dup 0) 4767 (match_operand:DI 1 "const_int_operand"))))] 4768 "TARGET_64BIT && TARGET_MIPS16 && reload_completed 4769 && !TARGET_DEBUG_D_MODE 4770 && ((INTVAL (operands[1]) < 0 4771 && INTVAL (operands[1]) >= -0x10) 4772 || (INTVAL (operands[1]) >= 32 * 8 4773 && INTVAL (operands[1]) <= 31 * 8 + 0x8) 4774 || (INTVAL (operands[1]) >= 0 4775 && INTVAL (operands[1]) < 32 * 8 4776 && (INTVAL (operands[1]) & 7) != 0))" 4777 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) 4778 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))] 4779{ 4780 HOST_WIDE_INT val = INTVAL (operands[1]); 4781 4782 if (val < 0) 4783 operands[2] = const0_rtx; 4784 else if (val >= 32 * 8) 4785 { 4786 int off = val & 7; 4787 4788 operands[1] = GEN_INT (0x8 + off); 4789 operands[2] = GEN_INT (val - off - 0x8); 4790 } 4791 else 4792 { 4793 int off = val & 7; 4794 4795 operands[1] = GEN_INT (off); 4796 operands[2] = GEN_INT (val - off); 4797 } 4798}) 4799 4800;; 32-bit Integer moves 4801 4802;; Unlike most other insns, the move insns can't be split with 4803;; different predicates, because register spilling and other parts of 4804;; the compiler, have memoized the insn number already. 4805 4806(define_expand "mov<mode>" 4807 [(set (match_operand:IMOVE32 0 "") 4808 (match_operand:IMOVE32 1 ""))] 4809 "" 4810{ 4811 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1])) 4812 DONE; 4813}) 4814 4815;; The difference between these two is whether or not ints are allowed 4816;; in FP registers (off by default, use -mdebugh to enable). 4817 4818(define_insn "*mov<mode>_internal" 4819 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") 4820 (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!kbJ,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] 4821 "!TARGET_MIPS16 4822 && (register_operand (operands[0], <MODE>mode) 4823 || reg_or_0_operand (operands[1], <MODE>mode))" 4824 { return mips_output_move (operands[0], operands[1]); } 4825 [(set_attr "move_type" "move,move,const,const,const,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore") 4826 (set_attr "compression" "all,micromips,micromips,*,*,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*") 4827 (set_attr "mode" "SI")]) 4828 4829(define_insn "*mov<mode>_mips16" 4830 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") 4831 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))] 4832 "TARGET_MIPS16 4833 && (register_operand (operands[0], <MODE>mode) 4834 || register_operand (operands[1], <MODE>mode))" 4835 { return mips_output_move (operands[0], operands[1]); } 4836 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo") 4837 (set_attr "mode" "SI")]) 4838 4839;; On the mips16, we can split lw $r,N($r) into an add and a load, 4840;; when the original load is a 4 byte instruction but the add and the 4841;; load are 2 2 byte instructions. 4842 4843(define_split 4844 [(set (match_operand:SI 0 "d_operand") 4845 (mem:SI (plus:SI (match_dup 0) 4846 (match_operand:SI 1 "const_int_operand"))))] 4847 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4848 && ((INTVAL (operands[1]) < 0 4849 && INTVAL (operands[1]) >= -0x80) 4850 || (INTVAL (operands[1]) >= 32 * 4 4851 && INTVAL (operands[1]) <= 31 * 4 + 0x7c) 4852 || (INTVAL (operands[1]) >= 0 4853 && INTVAL (operands[1]) < 32 * 4 4854 && (INTVAL (operands[1]) & 3) != 0))" 4855 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 4856 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))] 4857{ 4858 HOST_WIDE_INT val = INTVAL (operands[1]); 4859 4860 if (val < 0) 4861 operands[2] = const0_rtx; 4862 else if (val >= 32 * 4) 4863 { 4864 int off = val & 3; 4865 4866 operands[1] = GEN_INT (0x7c + off); 4867 operands[2] = GEN_INT (val - off - 0x7c); 4868 } 4869 else 4870 { 4871 int off = val & 3; 4872 4873 operands[1] = GEN_INT (off); 4874 operands[2] = GEN_INT (val - off); 4875 } 4876}) 4877 4878;; On the mips16, we can split a load of certain constants into a load 4879;; and an add. This turns a 4 byte instruction into 2 2 byte 4880;; instructions. 4881 4882(define_split 4883 [(set (match_operand:SI 0 "d_operand") 4884 (match_operand:SI 1 "const_int_operand"))] 4885 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4886 && INTVAL (operands[1]) >= 0x100 4887 && INTVAL (operands[1]) <= 0xff + 0x7f" 4888 [(set (match_dup 0) (match_dup 1)) 4889 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 4890{ 4891 int val = INTVAL (operands[1]); 4892 4893 operands[1] = GEN_INT (0xff); 4894 operands[2] = GEN_INT (val - 0xff); 4895}) 4896 4897;; MIPS4 supports loading and storing a floating point register from 4898;; the sum of two general registers. We use two versions for each of 4899;; these four instructions: one where the two general registers are 4900;; SImode, and one where they are DImode. This is because general 4901;; registers will be in SImode when they hold 32-bit values, but, 4902;; since the 32-bit values are always sign extended, the [ls][wd]xc1 4903;; instructions will still work correctly. 4904 4905;; ??? Perhaps it would be better to support these instructions by 4906;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since 4907;; these instructions can only be used to load and store floating 4908;; point registers, that would probably cause trouble in reload. 4909 4910(define_insn "*<ANYF:loadx>_<P:mode>" 4911 [(set (match_operand:ANYF 0 "register_operand" "=f") 4912 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") 4913 (match_operand:P 2 "register_operand" "d"))))] 4914 "ISA_HAS_LXC1_SXC1" 4915 "<ANYF:loadx>\t%0,%1(%2)" 4916 [(set_attr "type" "fpidxload") 4917 (set_attr "mode" "<ANYF:UNITMODE>")]) 4918 4919(define_insn "*<ANYF:storex>_<P:mode>" 4920 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") 4921 (match_operand:P 2 "register_operand" "d"))) 4922 (match_operand:ANYF 0 "register_operand" "f"))] 4923 "ISA_HAS_LXC1_SXC1" 4924 "<ANYF:storex>\t%0,%1(%2)" 4925 [(set_attr "type" "fpidxstore") 4926 (set_attr "mode" "<ANYF:UNITMODE>")]) 4927 4928;; Scaled indexed address load. 4929;; Per md.texi, we only need to look for a pattern with multiply in the 4930;; address expression, not shift. 4931 4932(define_insn "*lwxs" 4933 [(set (match_operand:IMOVE32 0 "register_operand" "=d") 4934 (mem:IMOVE32 4935 (plus:P (mult:P (match_operand:P 1 "register_operand" "d") 4936 (const_int 4)) 4937 (match_operand:P 2 "register_operand" "d"))))] 4938 "ISA_HAS_LWXS" 4939 "lwxs\t%0,%1(%2)" 4940 [(set_attr "type" "load") 4941 (set_attr "mode" "SI")]) 4942 4943;; 16-bit Integer moves 4944 4945;; Unlike most other insns, the move insns can't be split with 4946;; different predicates, because register spilling and other parts of 4947;; the compiler, have memoized the insn number already. 4948;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. 4949 4950(define_expand "movhi" 4951 [(set (match_operand:HI 0 "") 4952 (match_operand:HI 1 ""))] 4953 "" 4954{ 4955 if (mips_legitimize_move (HImode, operands[0], operands[1])) 4956 DONE; 4957}) 4958 4959(define_insn "*movhi_internal" 4960 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d") 4961 (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!kbJ,dJ,*d*J,*a"))] 4962 "!TARGET_MIPS16 4963 && (register_operand (operands[0], HImode) 4964 || reg_or_0_operand (operands[1], HImode))" 4965 { return mips_output_move (operands[0], operands[1]); } 4966 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo") 4967 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*") 4968 (set_attr "mode" "HI")]) 4969 4970(define_insn "*movhi_mips16" 4971 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 4972 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] 4973 "TARGET_MIPS16 4974 && (register_operand (operands[0], HImode) 4975 || register_operand (operands[1], HImode))" 4976 { return mips_output_move (operands[0], operands[1]); } 4977 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 4978 (set_attr "mode" "HI")]) 4979 4980;; On the mips16, we can split lh $r,N($r) into an add and a load, 4981;; when the original load is a 4 byte instruction but the add and the 4982;; load are 2 2 byte instructions. 4983 4984(define_split 4985 [(set (match_operand:HI 0 "d_operand") 4986 (mem:HI (plus:SI (match_dup 0) 4987 (match_operand:SI 1 "const_int_operand"))))] 4988 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4989 && ((INTVAL (operands[1]) < 0 4990 && INTVAL (operands[1]) >= -0x80) 4991 || (INTVAL (operands[1]) >= 32 * 2 4992 && INTVAL (operands[1]) <= 31 * 2 + 0x7e) 4993 || (INTVAL (operands[1]) >= 0 4994 && INTVAL (operands[1]) < 32 * 2 4995 && (INTVAL (operands[1]) & 1) != 0))" 4996 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 4997 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))] 4998{ 4999 HOST_WIDE_INT val = INTVAL (operands[1]); 5000 5001 if (val < 0) 5002 operands[2] = const0_rtx; 5003 else if (val >= 32 * 2) 5004 { 5005 int off = val & 1; 5006 5007 operands[1] = GEN_INT (0x7e + off); 5008 operands[2] = GEN_INT (val - off - 0x7e); 5009 } 5010 else 5011 { 5012 int off = val & 1; 5013 5014 operands[1] = GEN_INT (off); 5015 operands[2] = GEN_INT (val - off); 5016 } 5017}) 5018 5019;; 8-bit Integer moves 5020 5021;; Unlike most other insns, the move insns can't be split with 5022;; different predicates, because register spilling and other parts of 5023;; the compiler, have memoized the insn number already. 5024;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. 5025 5026(define_expand "movqi" 5027 [(set (match_operand:QI 0 "") 5028 (match_operand:QI 1 ""))] 5029 "" 5030{ 5031 if (mips_legitimize_move (QImode, operands[0], operands[1])) 5032 DONE; 5033}) 5034 5035(define_insn "*movqi_internal" 5036 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d") 5037 (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!kbJ,dJ,*d*J,*a"))] 5038 "!TARGET_MIPS16 5039 && (register_operand (operands[0], QImode) 5040 || reg_or_0_operand (operands[1], QImode))" 5041 { return mips_output_move (operands[0], operands[1]); } 5042 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo") 5043 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*") 5044 (set_attr "mode" "QI")]) 5045 5046(define_insn "*movqi_mips16" 5047 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 5048 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] 5049 "TARGET_MIPS16 5050 && (register_operand (operands[0], QImode) 5051 || register_operand (operands[1], QImode))" 5052 { return mips_output_move (operands[0], operands[1]); } 5053 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 5054 (set_attr "mode" "QI")]) 5055 5056;; On the mips16, we can split lb $r,N($r) into an add and a load, 5057;; when the original load is a 4 byte instruction but the add and the 5058;; load are 2 2 byte instructions. 5059 5060(define_split 5061 [(set (match_operand:QI 0 "d_operand") 5062 (mem:QI (plus:SI (match_dup 0) 5063 (match_operand:SI 1 "const_int_operand"))))] 5064 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 5065 && ((INTVAL (operands[1]) < 0 5066 && INTVAL (operands[1]) >= -0x80) 5067 || (INTVAL (operands[1]) >= 32 5068 && INTVAL (operands[1]) <= 31 + 0x7f))" 5069 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 5070 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))] 5071{ 5072 HOST_WIDE_INT val = INTVAL (operands[1]); 5073 5074 if (val < 0) 5075 operands[2] = const0_rtx; 5076 else 5077 { 5078 operands[1] = GEN_INT (0x7f); 5079 operands[2] = GEN_INT (val - 0x7f); 5080 } 5081}) 5082 5083;; 32-bit floating point moves 5084 5085(define_expand "movsf" 5086 [(set (match_operand:SF 0 "") 5087 (match_operand:SF 1 ""))] 5088 "" 5089{ 5090 if (mips_legitimize_move (SFmode, operands[0], operands[1])) 5091 DONE; 5092}) 5093 5094(define_insn "movccf" 5095 [(set (match_operand:CCF 0 "nonimmediate_operand" "=f,f,m") 5096 (match_operand:CCF 1 "nonimmediate_operand" "f,m,f"))] 5097 "ISA_HAS_CCF" 5098 { return mips_output_move (operands[0], operands[1]); } 5099 [(set_attr "move_type" "fmove,fpload,fpstore")]) 5100 5101(define_insn "*movsf_hardfloat" 5102 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 5103 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))] 5104 "TARGET_HARD_FLOAT 5105 && (register_operand (operands[0], SFmode) 5106 || reg_or_0_operand (operands[1], SFmode))" 5107 { return mips_output_move (operands[0], operands[1]); } 5108 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") 5109 (set_attr "mode" "SF")]) 5110 5111(define_insn "*movsf_softfloat" 5112 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m") 5113 (match_operand:SF 1 "move_operand" "Gd,m,d"))] 5114 "TARGET_SOFT_FLOAT && !TARGET_MIPS16 5115 && (register_operand (operands[0], SFmode) 5116 || reg_or_0_operand (operands[1], SFmode))" 5117 { return mips_output_move (operands[0], operands[1]); } 5118 [(set_attr "move_type" "move,load,store") 5119 (set_attr "mode" "SF")]) 5120 5121(define_insn "*movsf_mips16" 5122 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m") 5123 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))] 5124 "TARGET_MIPS16 5125 && (register_operand (operands[0], SFmode) 5126 || register_operand (operands[1], SFmode))" 5127 { return mips_output_move (operands[0], operands[1]); } 5128 [(set_attr "move_type" "move,move,move,load,store") 5129 (set_attr "mode" "SF")]) 5130 5131;; 64-bit floating point moves 5132 5133(define_expand "movdf" 5134 [(set (match_operand:DF 0 "") 5135 (match_operand:DF 1 ""))] 5136 "" 5137{ 5138 if (mips_legitimize_move (DFmode, operands[0], operands[1])) 5139 DONE; 5140}) 5141 5142(define_insn "*movdf_hardfloat" 5143 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 5144 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))] 5145 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT 5146 && (register_operand (operands[0], DFmode) 5147 || reg_or_0_operand (operands[1], DFmode))" 5148 { return mips_output_move (operands[0], operands[1]); } 5149 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") 5150 (set_attr "mode" "DF")]) 5151 5152(define_insn "*movdf_softfloat" 5153 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m") 5154 (match_operand:DF 1 "move_operand" "dG,m,dG"))] 5155 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16 5156 && (register_operand (operands[0], DFmode) 5157 || reg_or_0_operand (operands[1], DFmode))" 5158 { return mips_output_move (operands[0], operands[1]); } 5159 [(set_attr "move_type" "move,load,store") 5160 (set_attr "mode" "DF")]) 5161 5162(define_insn "*movdf_mips16" 5163 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m") 5164 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))] 5165 "TARGET_MIPS16 5166 && (register_operand (operands[0], DFmode) 5167 || register_operand (operands[1], DFmode))" 5168 { return mips_output_move (operands[0], operands[1]); } 5169 [(set_attr "move_type" "move,move,move,load,store") 5170 (set_attr "mode" "DF")]) 5171 5172;; 128-bit integer moves 5173 5174(define_expand "movti" 5175 [(set (match_operand:TI 0) 5176 (match_operand:TI 1))] 5177 "TARGET_64BIT" 5178{ 5179 if (mips_legitimize_move (TImode, operands[0], operands[1])) 5180 DONE; 5181}) 5182 5183(define_insn "*movti" 5184 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d") 5185 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*J,*d,*a"))] 5186 "TARGET_64BIT 5187 && !TARGET_MIPS16 5188 && (register_operand (operands[0], TImode) 5189 || reg_or_0_operand (operands[1], TImode))" 5190 { return mips_output_move (operands[0], operands[1]); } 5191 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo") 5192 (set (attr "mode") 5193 (if_then_else (eq_attr "move_type" "imul") 5194 (const_string "SI") 5195 (const_string "TI")))]) 5196 5197(define_insn "*movti_mips16" 5198 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 5199 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] 5200 "TARGET_64BIT 5201 && TARGET_MIPS16 5202 && (register_operand (operands[0], TImode) 5203 || register_operand (operands[1], TImode))" 5204 "#" 5205 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 5206 (set_attr "mode" "TI")]) 5207 5208;; 128-bit floating point moves 5209 5210(define_expand "movtf" 5211 [(set (match_operand:TF 0) 5212 (match_operand:TF 1))] 5213 "TARGET_64BIT" 5214{ 5215 if (mips_legitimize_move (TFmode, operands[0], operands[1])) 5216 DONE; 5217}) 5218 5219;; This pattern handles both hard- and soft-float cases. 5220(define_insn "*movtf" 5221 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m") 5222 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))] 5223 "TARGET_64BIT 5224 && !TARGET_MIPS16 5225 && (register_operand (operands[0], TFmode) 5226 || reg_or_0_operand (operands[1], TFmode))" 5227 "#" 5228 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore") 5229 (set_attr "mode" "TF")]) 5230 5231(define_insn "*movtf_mips16" 5232 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m") 5233 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))] 5234 "TARGET_64BIT 5235 && TARGET_MIPS16 5236 && (register_operand (operands[0], TFmode) 5237 || register_operand (operands[1], TFmode))" 5238 "#" 5239 [(set_attr "move_type" "move,move,move,load,store") 5240 (set_attr "mode" "TF")]) 5241 5242(define_split 5243 [(set (match_operand:MOVE64 0 "nonimmediate_operand") 5244 (match_operand:MOVE64 1 "move_operand"))] 5245 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)" 5246 [(const_int 0)] 5247{ 5248 mips_split_move_insn (operands[0], operands[1], curr_insn); 5249 DONE; 5250}) 5251 5252(define_split 5253 [(set (match_operand:MOVE128 0 "nonimmediate_operand") 5254 (match_operand:MOVE128 1 "move_operand"))] 5255 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)" 5256 [(const_int 0)] 5257{ 5258 mips_split_move_insn (operands[0], operands[1], curr_insn); 5259 DONE; 5260}) 5261 5262;; When generating mips16 code, split moves of negative constants into 5263;; a positive "li" followed by a negation. 5264(define_split 5265 [(set (match_operand 0 "d_operand") 5266 (match_operand 1 "const_int_operand"))] 5267 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0" 5268 [(set (match_dup 2) 5269 (match_dup 3)) 5270 (set (match_dup 2) 5271 (neg:SI (match_dup 2)))] 5272{ 5273 operands[2] = gen_lowpart (SImode, operands[0]); 5274 operands[3] = GEN_INT (-INTVAL (operands[1])); 5275}) 5276 5277;; 64-bit paired-single floating point moves 5278 5279(define_expand "movv2sf" 5280 [(set (match_operand:V2SF 0) 5281 (match_operand:V2SF 1))] 5282 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 5283{ 5284 if (mips_legitimize_move (V2SFmode, operands[0], operands[1])) 5285 DONE; 5286}) 5287 5288(define_insn "*movv2sf" 5289 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 5290 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))] 5291 "TARGET_HARD_FLOAT 5292 && TARGET_PAIRED_SINGLE_FLOAT 5293 && (register_operand (operands[0], V2SFmode) 5294 || reg_or_0_operand (operands[1], V2SFmode))" 5295 { return mips_output_move (operands[0], operands[1]); } 5296 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") 5297 (set_attr "mode" "DF")]) 5298 5299;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p 5300;; for the reason why we can't just use (reg:GPR HI_REGNUM). 5301;; 5302;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI 5303;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards 5304;; and the errata related to -mfix-vr4130. 5305(define_insn "mfhi<GPR:mode>_<HILO:mode>" 5306 [(set (match_operand:GPR 0 "register_operand" "=d") 5307 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")] 5308 UNSPEC_MFHI))] 5309 "" 5310 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; } 5311 [(set_attr "type" "mfhi") 5312 (set_attr "mode" "<GPR:MODE>")]) 5313 5314;; Set the high part of a HI/LO value, given that the low part has 5315;; already been set. See mips_hard_regno_mode_ok_p for the reason 5316;; why we can't just use (reg:GPR HI_REGNUM). 5317(define_insn "mthi<GPR:mode>_<HILO:mode>" 5318 [(set (match_operand:HILO 0 "register_operand" "=x") 5319 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 5320 (match_operand:GPR 2 "register_operand" "l")] 5321 UNSPEC_MTHI))] 5322 "" 5323 "mthi\t%z1" 5324 [(set_attr "type" "mthi") 5325 (set_attr "mode" "SI")]) 5326 5327;; Emit a doubleword move in which exactly one of the operands is 5328;; a floating-point register. We can't just emit two normal moves 5329;; because of the constraints imposed by the FPU register model; 5330;; see mips_cannot_change_mode_class for details. Instead, we keep 5331;; the FPR whole and use special patterns to refer to each word of 5332;; the other operand. 5333 5334(define_expand "move_doubleword_fpr<mode>" 5335 [(set (match_operand:SPLITF 0) 5336 (match_operand:SPLITF 1))] 5337 "" 5338{ 5339 if (FP_REG_RTX_P (operands[0])) 5340 { 5341 rtx low = mips_subword (operands[1], 0); 5342 rtx high = mips_subword (operands[1], 1); 5343 emit_insn (gen_load_low<mode> (operands[0], low)); 5344 if (ISA_HAS_MXHC1 && !TARGET_64BIT) 5345 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0])); 5346 else 5347 emit_insn (gen_load_high<mode> (operands[0], high, operands[0])); 5348 } 5349 else 5350 { 5351 rtx low = mips_subword (operands[0], 0); 5352 rtx high = mips_subword (operands[0], 1); 5353 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx)); 5354 if (ISA_HAS_MXHC1 && !TARGET_64BIT) 5355 emit_insn (gen_mfhc1<mode> (high, operands[1])); 5356 else 5357 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx)); 5358 } 5359 DONE; 5360}) 5361 5362;; Load the low word of operand 0 with operand 1. 5363(define_insn "load_low<mode>" 5364 [(set (match_operand:SPLITF 0 "register_operand" "=f,f") 5365 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")] 5366 UNSPEC_LOAD_LOW))] 5367 "TARGET_HARD_FLOAT" 5368{ 5369 operands[0] = mips_subword (operands[0], 0); 5370 return mips_output_move (operands[0], operands[1]); 5371} 5372 [(set_attr "move_type" "mtc,fpload") 5373 (set_attr "mode" "<HALFMODE>")]) 5374 5375;; Load the high word of operand 0 from operand 1, preserving the value 5376;; in the low word. 5377(define_insn "load_high<mode>" 5378 [(set (match_operand:SPLITF 0 "register_operand" "=f,f") 5379 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m") 5380 (match_operand:SPLITF 2 "register_operand" "0,0")] 5381 UNSPEC_LOAD_HIGH))] 5382 "TARGET_HARD_FLOAT" 5383{ 5384 operands[0] = mips_subword (operands[0], 1); 5385 return mips_output_move (operands[0], operands[1]); 5386} 5387 [(set_attr "move_type" "mtc,fpload") 5388 (set_attr "mode" "<HALFMODE>")]) 5389 5390;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the 5391;; high word and 0 to store the low word. 5392(define_insn "store_word<mode>" 5393 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m") 5394 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f") 5395 (match_operand 2 "const_int_operand")] 5396 UNSPEC_STORE_WORD))] 5397 "TARGET_HARD_FLOAT" 5398{ 5399 operands[1] = mips_subword (operands[1], INTVAL (operands[2])); 5400 return mips_output_move (operands[0], operands[1]); 5401} 5402 [(set_attr "move_type" "mfc,fpstore") 5403 (set_attr "mode" "<HALFMODE>")]) 5404 5405;; Move operand 1 to the high word of operand 0 using mthc1, preserving the 5406;; value in the low word. 5407(define_insn "mthc1<mode>" 5408 [(set (match_operand:SPLITF 0 "register_operand" "=f") 5409 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ") 5410 (match_operand:SPLITF 2 "register_operand" "0")] 5411 UNSPEC_MTHC1))] 5412 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1" 5413 "mthc1\t%z1,%0" 5414 [(set_attr "move_type" "mtc") 5415 (set_attr "mode" "<HALFMODE>")]) 5416 5417;; Move high word of operand 1 to operand 0 using mfhc1. 5418(define_insn "mfhc1<mode>" 5419 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d") 5420 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")] 5421 UNSPEC_MFHC1))] 5422 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1" 5423 "mfhc1\t%0,%1" 5424 [(set_attr "move_type" "mfc") 5425 (set_attr "mode" "<HALFMODE>")]) 5426 5427;; Move a constant that satisfies CONST_GP_P into operand 0. 5428(define_expand "load_const_gp_<mode>" 5429 [(set (match_operand:P 0 "register_operand" "=d") 5430 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))]) 5431 5432;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset 5433;; of _gp from the start of this function. Operand 1 is the incoming 5434;; function address. 5435(define_insn_and_split "loadgp_newabi_<mode>" 5436 [(set (match_operand:P 0 "register_operand" "=&d") 5437 (unspec:P [(match_operand:P 1) 5438 (match_operand:P 2 "register_operand" "d")] 5439 UNSPEC_LOADGP))] 5440 "mips_current_loadgp_style () == LOADGP_NEWABI" 5441 { return mips_must_initialize_gp_p () ? "#" : ""; } 5442 "&& mips_must_initialize_gp_p ()" 5443 [(set (match_dup 0) (match_dup 3)) 5444 (set (match_dup 0) (match_dup 4)) 5445 (set (match_dup 0) (match_dup 5))] 5446{ 5447 operands[3] = gen_rtx_HIGH (Pmode, operands[1]); 5448 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]); 5449 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]); 5450} 5451 [(set_attr "type" "ghost")]) 5452 5453;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol. 5454(define_insn_and_split "loadgp_absolute_<mode>" 5455 [(set (match_operand:P 0 "register_operand" "=d") 5456 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))] 5457 "mips_current_loadgp_style () == LOADGP_ABSOLUTE" 5458 { return mips_must_initialize_gp_p () ? "#" : ""; } 5459 "&& mips_must_initialize_gp_p ()" 5460 [(const_int 0)] 5461{ 5462 mips_emit_move (operands[0], operands[1]); 5463 DONE; 5464} 5465 [(set_attr "type" "ghost")]) 5466 5467;; This blockage instruction prevents the gp load from being 5468;; scheduled after an implicit use of gp. It also prevents 5469;; the load from being deleted as dead. 5470(define_insn "loadgp_blockage" 5471 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)] 5472 "" 5473 "" 5474 [(set_attr "type" "ghost")]) 5475 5476;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol 5477;; and operand 1 is the __GOTT_INDEX__ symbol. 5478(define_insn_and_split "loadgp_rtp_<mode>" 5479 [(set (match_operand:P 0 "register_operand" "=d") 5480 (unspec:P [(match_operand:P 1 "symbol_ref_operand") 5481 (match_operand:P 2 "symbol_ref_operand")] 5482 UNSPEC_LOADGP))] 5483 "mips_current_loadgp_style () == LOADGP_RTP" 5484 { return mips_must_initialize_gp_p () ? "#" : ""; } 5485 "&& mips_must_initialize_gp_p ()" 5486 [(set (match_dup 0) (high:P (match_dup 3))) 5487 (set (match_dup 0) (unspec:P [(match_dup 0) 5488 (match_dup 3)] UNSPEC_LOAD_GOT)) 5489 (set (match_dup 0) (unspec:P [(match_dup 0) 5490 (match_dup 4)] UNSPEC_LOAD_GOT))] 5491{ 5492 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE); 5493 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF); 5494} 5495 [(set_attr "type" "ghost")]) 5496 5497;; Initialize the global pointer for MIPS16 code. Operand 0 is the 5498;; global pointer and operand 1 is the MIPS16 register that holds 5499;; the required value. 5500(define_insn_and_split "copygp_mips16_<mode>" 5501 [(set (match_operand:P 0 "register_operand" "=y") 5502 (unspec:P [(match_operand:P 1 "register_operand" "d")] 5503 UNSPEC_COPYGP))] 5504 "TARGET_MIPS16" 5505 { return mips_must_initialize_gp_p () ? "#" : ""; } 5506 "&& mips_must_initialize_gp_p ()" 5507 [(set (match_dup 0) (match_dup 1))] 5508 "" 5509 [(set_attr "type" "ghost")]) 5510 5511;; A placeholder for where the cprestore instruction should go, 5512;; if we decide we need one. Operand 0 and operand 1 are as for 5513;; "cprestore". Operand 2 is a register that holds the gp value. 5514;; 5515;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx, 5516;; otherwise any register that holds the correct value will do. 5517(define_insn_and_split "potential_cprestore_<mode>" 5518 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X") 5519 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i") 5520 (match_operand:P 2 "register_operand" "d,d")] 5521 UNSPEC_POTENTIAL_CPRESTORE)) 5522 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))] 5523 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx" 5524 { return mips_must_initialize_gp_p () ? "#" : ""; } 5525 "mips_must_initialize_gp_p ()" 5526 [(const_int 0)] 5527{ 5528 mips_save_gp_to_cprestore_slot (operands[0], operands[1], 5529 operands[2], operands[3]); 5530 DONE; 5531} 5532 [(set_attr "type" "ghost")]) 5533 5534;; Emit a .cprestore directive, which normally expands to a single store 5535;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM 5536;; for the cprestore slot. Operand 1 is the offset of the slot from 5537;; the stack pointer. (This is redundant with operand 0, but it makes 5538;; things a little simpler.) 5539(define_insn "cprestore_<mode>" 5540 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X") 5541 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i") 5542 (reg:P 28)] 5543 UNSPEC_CPRESTORE))] 5544 "TARGET_CPRESTORE_DIRECTIVE" 5545{ 5546 if (mips_nomacro.nesting_level > 0 && which_alternative == 1) 5547 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro"; 5548 else 5549 return ".cprestore\t%1"; 5550} 5551 [(set_attr "type" "store") 5552 (set_attr "insn_count" "1,3")]) 5553 5554(define_insn "use_cprestore_<mode>" 5555 [(set (reg:P CPRESTORE_SLOT_REGNUM) 5556 (match_operand:P 0 "cprestore_load_slot_operand"))] 5557 "" 5558 "" 5559 [(set_attr "type" "ghost")]) 5560 5561;; Expand in-line code to clear the instruction cache between operand[0] and 5562;; operand[1]. 5563(define_expand "clear_cache" 5564 [(match_operand 0 "pmode_register_operand") 5565 (match_operand 1 "pmode_register_operand")] 5566 "" 5567 " 5568{ 5569 if (TARGET_SYNCI) 5570 { 5571 mips_expand_synci_loop (operands[0], operands[1]); 5572 emit_insn (gen_sync ()); 5573 emit_insn (PMODE_INSN (gen_clear_hazard, ())); 5574 } 5575 else if (mips_cache_flush_func && mips_cache_flush_func[0]) 5576 { 5577 rtx len = gen_reg_rtx (Pmode); 5578 emit_insn (gen_sub3_insn (len, operands[1], operands[0])); 5579 MIPS_ICACHE_SYNC (operands[0], len); 5580 } 5581 DONE; 5582}") 5583 5584(define_insn "sync" 5585 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)] 5586 "GENERATE_SYNC" 5587 { return mips_output_sync (); }) 5588 5589(define_insn "synci" 5590 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")] 5591 UNSPEC_SYNCI)] 5592 "TARGET_SYNCI" 5593 "synci\t0(%0)") 5594 5595(define_insn "rdhwr_synci_step_<mode>" 5596 [(set (match_operand:P 0 "register_operand" "=d") 5597 (unspec_volatile [(const_int 1)] 5598 UNSPEC_RDHWR))] 5599 "ISA_HAS_SYNCI" 5600 "rdhwr\t%0,$1") 5601 5602(define_insn "clear_hazard_<mode>" 5603 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD) 5604 (clobber (reg:P RETURN_ADDR_REGNUM))] 5605 "ISA_HAS_SYNCI" 5606{ 5607 return "%(%<bal\t1f\n" 5608 "\tnop\n" 5609 "1:\t<d>addiu\t$31,$31,12\n" 5610 "\tjr.hb\t$31\n" 5611 "\tnop%>%)"; 5612} 5613 [(set_attr "insn_count" "5")]) 5614 5615;; Cache operations for R4000-style caches. 5616(define_insn "mips_cache" 5617 [(set (mem:BLK (scratch)) 5618 (unspec:BLK [(match_operand:SI 0 "const_int_operand") 5619 (match_operand:QI 1 "address_operand" "ZD")] 5620 UNSPEC_MIPS_CACHE))] 5621 "ISA_HAS_CACHE" 5622 "cache\t%X0,%a1") 5623 5624;; Similar, but with the operands hard-coded to an R10K cache barrier 5625;; operation. We keep the pattern distinct so that we can identify 5626;; cache operations inserted by -mr10k-cache-barrier=, and so that 5627;; the operation is never inserted into a delay slot. 5628(define_insn "r10k_cache_barrier" 5629 [(set (mem:BLK (scratch)) 5630 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))] 5631 "ISA_HAS_CACHE" 5632 "cache\t0x14,0(%$)" 5633 [(set_attr "can_delay" "no")]) 5634 5635;; Block moves, see mips.c for more details. 5636;; Argument 0 is the destination 5637;; Argument 1 is the source 5638;; Argument 2 is the length 5639;; Argument 3 is the alignment 5640 5641(define_expand "movmemsi" 5642 [(parallel [(set (match_operand:BLK 0 "general_operand") 5643 (match_operand:BLK 1 "general_operand")) 5644 (use (match_operand:SI 2 "")) 5645 (use (match_operand:SI 3 "const_int_operand"))])] 5646 "!TARGET_MIPS16 && !TARGET_MEMCPY" 5647{ 5648 if (mips_expand_block_move (operands[0], operands[1], operands[2])) 5649 DONE; 5650 else 5651 FAIL; 5652}) 5653 5654;; 5655;; .................... 5656;; 5657;; SHIFTS 5658;; 5659;; .................... 5660 5661(define_expand "<optab><mode>3" 5662 [(set (match_operand:GPR 0 "register_operand") 5663 (any_shift:GPR (match_operand:GPR 1 "register_operand") 5664 (match_operand:SI 2 "arith_operand")))] 5665 "" 5666{ 5667 /* On the mips16, a shift of more than 8 is a four byte instruction, 5668 so, for a shift between 8 and 16, it is just as fast to do two 5669 shifts of 8 or less. If there is a lot of shifting going on, we 5670 may win in CSE. Otherwise combine will put the shifts back 5671 together again. This can be called by mips_function_arg, so we must 5672 be careful not to allocate a new register if we've reached the 5673 reload pass. */ 5674 if (TARGET_MIPS16 5675 && optimize 5676 && CONST_INT_P (operands[2]) 5677 && INTVAL (operands[2]) > 8 5678 && INTVAL (operands[2]) <= 16 5679 && !reload_in_progress 5680 && !reload_completed) 5681 { 5682 rtx temp = gen_reg_rtx (<MODE>mode); 5683 5684 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8))); 5685 emit_insn (gen_<optab><mode>3 (operands[0], temp, 5686 GEN_INT (INTVAL (operands[2]) - 8))); 5687 DONE; 5688 } 5689}) 5690 5691(define_insn "*<optab><mode>3" 5692 [(set (match_operand:GPR 0 "register_operand" "=!u,d") 5693 (any_shift:GPR (match_operand:GPR 1 "register_operand" "!u,d") 5694 (match_operand:SI 2 "arith_operand" "Uib3,dI")))] 5695 "!TARGET_MIPS16" 5696{ 5697 if (CONST_INT_P (operands[2])) 5698 operands[2] = GEN_INT (INTVAL (operands[2]) 5699 & (GET_MODE_BITSIZE (<MODE>mode) - 1)); 5700 5701 return "<d><insn>\t%0,%1,%2"; 5702} 5703 [(set_attr "type" "shift") 5704 (set_attr "compression" "<shift_compression>,none") 5705 (set_attr "mode" "<MODE>")]) 5706 5707(define_insn "*<optab>si3_extend" 5708 [(set (match_operand:DI 0 "register_operand" "=d") 5709 (sign_extend:DI 5710 (any_shift:SI (match_operand:SI 1 "register_operand" "d") 5711 (match_operand:SI 2 "arith_operand" "dI"))))] 5712 "TARGET_64BIT && !TARGET_MIPS16" 5713{ 5714 if (CONST_INT_P (operands[2])) 5715 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 5716 5717 return "<insn>\t%0,%1,%2"; 5718} 5719 [(set_attr "type" "shift") 5720 (set_attr "mode" "SI")]) 5721 5722(define_insn "*<optab>si3_mips16" 5723 [(set (match_operand:SI 0 "register_operand" "=d,d,d") 5724 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d,d") 5725 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5726 "TARGET_MIPS16" 5727{ 5728 if (which_alternative == 0) 5729 return "<insn>\t%0,%2"; 5730 5731 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 5732 return "<insn>\t%0,%1,%2"; 5733} 5734 [(set_attr "type" "shift") 5735 (set_attr "mode" "SI") 5736 (set_attr "extended_mips16" "no,no,yes")]) 5737 5738(define_insn "<GPR:d>lsa" 5739 [(set (match_operand:GPR 0 "register_operand" "=d") 5740 (plus:GPR (ashift:GPR (match_operand:GPR 1 "register_operand" "d") 5741 (match_operand 2 "const_immlsa_operand" "")) 5742 (match_operand:GPR 3 "register_operand" "d")))] 5743 "ISA_HAS_<GPR:D>LSA" 5744 "<GPR:d>lsa\t%0,%1,%3,%2" 5745 [(set_attr "type" "arith") 5746 (set_attr "mode" "<GPR:MODE>")]) 5747 5748;; We need separate DImode MIPS16 patterns because of the irregularity 5749;; of right shifts. 5750(define_insn "*ashldi3_mips16" 5751 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5752 (ashift:DI (match_operand:DI 1 "register_operand" "0,d,d") 5753 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5754 "TARGET_64BIT && TARGET_MIPS16" 5755{ 5756 if (which_alternative == 0) 5757 return "dsll\t%0,%2"; 5758 5759 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 5760 return "dsll\t%0,%1,%2"; 5761} 5762 [(set_attr "type" "shift") 5763 (set_attr "mode" "DI") 5764 (set_attr "extended_mips16" "no,no,yes")]) 5765 5766(define_insn "*ashrdi3_mips16" 5767 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5768 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0") 5769 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5770 "TARGET_64BIT && TARGET_MIPS16" 5771{ 5772 if (CONST_INT_P (operands[2])) 5773 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 5774 5775 return "dsra\t%0,%2"; 5776} 5777 [(set_attr "type" "shift") 5778 (set_attr "mode" "DI") 5779 (set_attr "extended_mips16" "no,no,yes")]) 5780 5781(define_insn "*lshrdi3_mips16" 5782 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5783 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0") 5784 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5785 "TARGET_64BIT && TARGET_MIPS16" 5786{ 5787 if (CONST_INT_P (operands[2])) 5788 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 5789 5790 return "dsrl\t%0,%2"; 5791} 5792 [(set_attr "type" "shift") 5793 (set_attr "mode" "DI") 5794 (set_attr "extended_mips16" "no,no,yes")]) 5795 5796;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. 5797 5798(define_split 5799 [(set (match_operand:GPR 0 "d_operand") 5800 (any_shift:GPR (match_operand:GPR 1 "d_operand") 5801 (match_operand:GPR 2 "const_int_operand")))] 5802 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 5803 && INTVAL (operands[2]) > 8 5804 && INTVAL (operands[2]) <= 16" 5805 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8))) 5806 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))] 5807 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); }) 5808 5809;; If we load a byte on the mips16 as a bitfield, the resulting 5810;; sequence of instructions is too complicated for combine, because it 5811;; involves four instructions: a load, a shift, a constant load into a 5812;; register, and an and (the key problem here is that the mips16 does 5813;; not have and immediate). We recognize a shift of a load in order 5814;; to make it simple enough for combine to understand. 5815;; 5816;; The instruction count here is the worst case. 5817(define_insn_and_split "" 5818 [(set (match_operand:SI 0 "register_operand" "=d") 5819 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") 5820 (match_operand:SI 2 "immediate_operand" "I")))] 5821 "TARGET_MIPS16" 5822 "#" 5823 "" 5824 [(set (match_dup 0) (match_dup 1)) 5825 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] 5826 "" 5827 [(set_attr "type" "load") 5828 (set_attr "mode" "SI") 5829 (set (attr "insn_count") 5830 (symbol_ref "mips_load_store_insns (operands[1], insn) + 2"))]) 5831 5832(define_insn "rotr<mode>3" 5833 [(set (match_operand:GPR 0 "register_operand" "=d") 5834 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d") 5835 (match_operand:SI 2 "arith_operand" "dI")))] 5836 "ISA_HAS_ROR" 5837{ 5838 if (CONST_INT_P (operands[2])) 5839 operands[2] = GEN_INT (INTVAL (operands[2]) 5840 & (GET_MODE_BITSIZE (<MODE>mode) - 1)); 5841 5842 return "<d>ror\t%0,%1,%2"; 5843} 5844 [(set_attr "type" "shift") 5845 (set_attr "mode" "<MODE>")]) 5846 5847(define_insn "bswaphi2" 5848 [(set (match_operand:HI 0 "register_operand" "=d") 5849 (bswap:HI (match_operand:HI 1 "register_operand" "d")))] 5850 "ISA_HAS_WSBH" 5851 "wsbh\t%0,%1" 5852 [(set_attr "type" "shift")]) 5853 5854(define_insn_and_split "bswapsi2" 5855 [(set (match_operand:SI 0 "register_operand" "=d") 5856 (bswap:SI (match_operand:SI 1 "register_operand" "d")))] 5857 "ISA_HAS_WSBH && ISA_HAS_ROR" 5858 "#" 5859 "" 5860 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH)) 5861 (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] 5862 "" 5863 [(set_attr "insn_count" "2")]) 5864 5865(define_insn_and_split "bswapdi2" 5866 [(set (match_operand:DI 0 "register_operand" "=d") 5867 (bswap:DI (match_operand:DI 1 "register_operand" "d")))] 5868 "TARGET_64BIT && ISA_HAS_WSBH" 5869 "#" 5870 "" 5871 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH)) 5872 (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))] 5873 "" 5874 [(set_attr "insn_count" "2")]) 5875 5876(define_insn "wsbh" 5877 [(set (match_operand:SI 0 "register_operand" "=d") 5878 (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))] 5879 "ISA_HAS_WSBH" 5880 "wsbh\t%0,%1" 5881 [(set_attr "type" "shift")]) 5882 5883(define_insn "dsbh" 5884 [(set (match_operand:DI 0 "register_operand" "=d") 5885 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))] 5886 "TARGET_64BIT && ISA_HAS_WSBH" 5887 "dsbh\t%0,%1" 5888 [(set_attr "type" "shift")]) 5889 5890(define_insn "dshd" 5891 [(set (match_operand:DI 0 "register_operand" "=d") 5892 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))] 5893 "TARGET_64BIT && ISA_HAS_WSBH" 5894 "dshd\t%0,%1" 5895 [(set_attr "type" "shift")]) 5896 5897;; 5898;; .................... 5899;; 5900;; CONDITIONAL BRANCHES 5901;; 5902;; .................... 5903 5904;; Conditional branches on floating-point equality tests. 5905 5906(define_insn "*branch_fp_<mode>" 5907 [(set (pc) 5908 (if_then_else 5909 (match_operator 1 "equality_operator" 5910 [(match_operand:FPCC 2 "register_operand" "<reg>") 5911 (const_int 0)]) 5912 (label_ref (match_operand 0 "" "")) 5913 (pc)))] 5914 "TARGET_HARD_FLOAT" 5915{ 5916 return mips_output_conditional_branch (insn, operands, 5917 MIPS_BRANCH ("b%F1", "%Z2%0"), 5918 MIPS_BRANCH ("b%W1", "%Z2%0")); 5919} 5920 [(set_attr "type" "branch")]) 5921 5922(define_insn "*branch_fp_inverted_<mode>" 5923 [(set (pc) 5924 (if_then_else 5925 (match_operator 1 "equality_operator" 5926 [(match_operand:FPCC 2 "register_operand" "<reg>") 5927 (const_int 0)]) 5928 (pc) 5929 (label_ref (match_operand 0 "" ""))))] 5930 "TARGET_HARD_FLOAT" 5931{ 5932 return mips_output_conditional_branch (insn, operands, 5933 MIPS_BRANCH ("b%W1", "%Z2%0"), 5934 MIPS_BRANCH ("b%F1", "%Z2%0")); 5935} 5936 [(set_attr "type" "branch")]) 5937 5938;; Conditional branches on ordered comparisons with zero. 5939 5940(define_insn "*branch_order<mode>" 5941 [(set (pc) 5942 (if_then_else 5943 (match_operator 1 "order_operator" 5944 [(match_operand:GPR 2 "register_operand" "d,d") 5945 (match_operand:GPR 3 "reg_or_0_operand" "J,d")]) 5946 (label_ref (match_operand 0 "" "")) 5947 (pc)))] 5948 "!TARGET_MIPS16" 5949 { return mips_output_order_conditional_branch (insn, operands, false); } 5950 [(set_attr "type" "branch") 5951 (set_attr "compact_form" "maybe,always") 5952 (set_attr "hazard" "forbidden_slot")]) 5953 5954(define_insn "*branch_order<mode>_inverted" 5955 [(set (pc) 5956 (if_then_else 5957 (match_operator 1 "order_operator" 5958 [(match_operand:GPR 2 "register_operand" "d,d") 5959 (match_operand:GPR 3 "reg_or_0_operand" "J,d")]) 5960 (pc) 5961 (label_ref (match_operand 0 "" ""))))] 5962 "!TARGET_MIPS16" 5963 { return mips_output_order_conditional_branch (insn, operands, true); } 5964 [(set_attr "type" "branch") 5965 (set_attr "compact_form" "maybe,always") 5966 (set_attr "hazard" "forbidden_slot")]) 5967 5968;; Conditional branch on equality comparison. 5969 5970(define_insn "*branch_equality<mode>" 5971 [(set (pc) 5972 (if_then_else 5973 (match_operator 1 "equality_operator" 5974 [(match_operand:GPR 2 "register_operand" "d") 5975 (match_operand:GPR 3 "reg_or_0_operand" "dJ")]) 5976 (label_ref (match_operand 0 "" "")) 5977 (pc)))] 5978 "!TARGET_MIPS16" 5979 { return mips_output_equal_conditional_branch (insn, operands, false); } 5980 [(set_attr "type" "branch") 5981 (set_attr "compact_form" "maybe") 5982 (set_attr "hazard" "forbidden_slot")]) 5983 5984(define_insn "*branch_equality<mode>_inverted" 5985 [(set (pc) 5986 (if_then_else 5987 (match_operator 1 "equality_operator" 5988 [(match_operand:GPR 2 "register_operand" "d") 5989 (match_operand:GPR 3 "reg_or_0_operand" "dJ")]) 5990 (pc) 5991 (label_ref (match_operand 0 "" ""))))] 5992 "!TARGET_MIPS16" 5993 { return mips_output_equal_conditional_branch (insn, operands, true); } 5994 [(set_attr "type" "branch") 5995 (set_attr "compact_form" "maybe") 5996 (set_attr "hazard" "forbidden_slot")]) 5997 5998;; MIPS16 branches 5999 6000(define_insn "*branch_equality<mode>_mips16" 6001 [(set (pc) 6002 (if_then_else 6003 (match_operator 1 "equality_operator" 6004 [(match_operand:GPR 2 "register_operand" "d,t") 6005 (const_int 0)]) 6006 (label_ref (match_operand 0 "" "")) 6007 (pc)))] 6008 "TARGET_MIPS16" 6009 "@ 6010 b%C1z\t%2,%0 6011 bt%C1z\t%0" 6012 [(set_attr "type" "branch")]) 6013 6014(define_insn "*branch_equality<mode>_mips16_inverted" 6015 [(set (pc) 6016 (if_then_else 6017 (match_operator 1 "equality_operator" 6018 [(match_operand:GPR 2 "register_operand" "d,t") 6019 (const_int 0)]) 6020 (pc) 6021 (label_ref (match_operand 0 "" ""))))] 6022 "TARGET_MIPS16" 6023 "@ 6024 b%N1z\t%2,%0 6025 bt%N1z\t%0" 6026 [(set_attr "type" "branch")]) 6027 6028(define_expand "cbranch<mode>4" 6029 [(set (pc) 6030 (if_then_else (match_operator 0 "comparison_operator" 6031 [(match_operand:GPR 1 "register_operand") 6032 (match_operand:GPR 2 "nonmemory_operand")]) 6033 (label_ref (match_operand 3 "")) 6034 (pc)))] 6035 "" 6036{ 6037 mips_expand_conditional_branch (operands); 6038 DONE; 6039}) 6040 6041(define_expand "cbranch<mode>4" 6042 [(set (pc) 6043 (if_then_else (match_operator 0 "comparison_operator" 6044 [(match_operand:SCALARF 1 "register_operand") 6045 (match_operand:SCALARF 2 "register_operand")]) 6046 (label_ref (match_operand 3 "")) 6047 (pc)))] 6048 "" 6049{ 6050 mips_expand_conditional_branch (operands); 6051 DONE; 6052}) 6053 6054;; Used to implement built-in functions. 6055(define_expand "condjump" 6056 [(set (pc) 6057 (if_then_else (match_operand 0) 6058 (label_ref (match_operand 1)) 6059 (pc)))]) 6060 6061;; Branch if bit is set/clear. 6062 6063(define_insn "*branch_bit<bbv><mode>" 6064 [(set (pc) 6065 (if_then_else 6066 (equality_op (zero_extract:GPR 6067 (match_operand:GPR 1 "register_operand" "d") 6068 (const_int 1) 6069 (match_operand 2 "const_int_operand" "")) 6070 (const_int 0)) 6071 (label_ref (match_operand 0 "")) 6072 (pc)))] 6073 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" 6074{ 6075 return 6076 mips_output_conditional_branch (insn, operands, 6077 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"), 6078 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0")); 6079} 6080 [(set_attr "type" "branch") 6081 (set_attr "branch_likely" "no")]) 6082 6083(define_insn "*branch_bit<bbv><mode>_inverted" 6084 [(set (pc) 6085 (if_then_else 6086 (equality_op (zero_extract:GPR 6087 (match_operand:GPR 1 "register_operand" "d") 6088 (const_int 1) 6089 (match_operand 2 "const_int_operand" "")) 6090 (const_int 0)) 6091 (pc) 6092 (label_ref (match_operand 0 ""))))] 6093 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" 6094{ 6095 return 6096 mips_output_conditional_branch (insn, operands, 6097 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"), 6098 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0")); 6099} 6100 [(set_attr "type" "branch") 6101 (set_attr "branch_likely" "no")]) 6102 6103;; 6104;; .................... 6105;; 6106;; SETTING A REGISTER FROM A COMPARISON 6107;; 6108;; .................... 6109 6110;; Destination is always set in SI mode. 6111 6112(define_expand "cstore<mode>4" 6113 [(set (match_operand:SI 0 "register_operand") 6114 (match_operator:SI 1 "mips_cstore_operator" 6115 [(match_operand:GPR 2 "register_operand") 6116 (match_operand:GPR 3 "nonmemory_operand")]))] 6117 "" 6118{ 6119 mips_expand_scc (operands); 6120 DONE; 6121}) 6122 6123(define_insn "*seq_zero_<GPR:mode><GPR2:mode>" 6124 [(set (match_operand:GPR2 0 "register_operand" "=d") 6125 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d") 6126 (const_int 0)))] 6127 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE" 6128 "sltu\t%0,%1,1" 6129 [(set_attr "type" "slt") 6130 (set_attr "mode" "<GPR:MODE>")]) 6131 6132(define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16" 6133 [(set (match_operand:GPR2 0 "register_operand" "=t") 6134 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d") 6135 (const_int 0)))] 6136 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE" 6137 "sltu\t%1,1" 6138 [(set_attr "type" "slt") 6139 (set_attr "mode" "<GPR:MODE>")]) 6140 6141;; Generate sltiu unless using seq results in better code. 6142(define_insn "*seq_<GPR:mode><GPR2:mode>_seq" 6143 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d") 6144 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d") 6145 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))] 6146 "ISA_HAS_SEQ_SNE" 6147 "@ 6148 seq\t%0,%1,%2 6149 sltiu\t%0,%1,1 6150 seqi\t%0,%1,%2" 6151 [(set_attr "type" "slt") 6152 (set_attr "mode" "<GPR:MODE>")]) 6153 6154(define_insn "*sne_zero_<GPR:mode><GPR2:mode>" 6155 [(set (match_operand:GPR2 0 "register_operand" "=d") 6156 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d") 6157 (const_int 0)))] 6158 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE" 6159 "sltu\t%0,%.,%1" 6160 [(set_attr "type" "slt") 6161 (set_attr "mode" "<GPR:MODE>")]) 6162 6163;; Generate sltu unless using sne results in better code. 6164(define_insn "*sne_<GPR:mode><GPR2:mode>_sne" 6165 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d") 6166 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d") 6167 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))] 6168 "ISA_HAS_SEQ_SNE" 6169 "@ 6170 sne\t%0,%1,%2 6171 sltu\t%0,%.,%1 6172 snei\t%0,%1,%2" 6173 [(set_attr "type" "slt") 6174 (set_attr "mode" "<GPR:MODE>")]) 6175 6176(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>" 6177 [(set (match_operand:GPR2 0 "register_operand" "=d") 6178 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d") 6179 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] 6180 "!TARGET_MIPS16" 6181 "slt<u>\t%0,%z2,%1" 6182 [(set_attr "type" "slt") 6183 (set_attr "mode" "<GPR:MODE>")]) 6184 6185(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16" 6186 [(set (match_operand:GPR2 0 "register_operand" "=t") 6187 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d") 6188 (match_operand:GPR 2 "register_operand" "d")))] 6189 "TARGET_MIPS16" 6190 "slt<u>\t%2,%1" 6191 [(set_attr "type" "slt") 6192 (set_attr "mode" "<GPR:MODE>")]) 6193 6194(define_insn "*sge<u>_<GPR:mode><GPR2:mode>" 6195 [(set (match_operand:GPR2 0 "register_operand" "=d") 6196 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d") 6197 (const_int 1)))] 6198 "!TARGET_MIPS16" 6199 "slt<u>\t%0,%.,%1" 6200 [(set_attr "type" "slt") 6201 (set_attr "mode" "<GPR:MODE>")]) 6202 6203(define_insn "*slt<u>_<GPR:mode><GPR2:mode>" 6204 [(set (match_operand:GPR2 0 "register_operand" "=d") 6205 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d") 6206 (match_operand:GPR 2 "arith_operand" "dI")))] 6207 "!TARGET_MIPS16" 6208 "slt<u>\t%0,%1,%2" 6209 [(set_attr "type" "slt") 6210 (set_attr "mode" "<GPR:MODE>")]) 6211 6212(define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16" 6213 [(set (match_operand:GPR2 0 "register_operand" "=t,t,t") 6214 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d,d") 6215 (match_operand:GPR 2 "arith_operand" "d,Uub8,I")))] 6216 "TARGET_MIPS16" 6217 "slt<u>\t%1,%2" 6218 [(set_attr "type" "slt") 6219 (set_attr "mode" "<GPR:MODE>") 6220 (set_attr "extended_mips16" "no,no,yes")]) 6221 6222(define_insn "*sle<u>_<GPR:mode><GPR2:mode>" 6223 [(set (match_operand:GPR2 0 "register_operand" "=d") 6224 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d") 6225 (match_operand:GPR 2 "sle_operand" "")))] 6226 "!TARGET_MIPS16" 6227{ 6228 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 6229 return "slt<u>\t%0,%1,%2"; 6230} 6231 [(set_attr "type" "slt") 6232 (set_attr "mode" "<GPR:MODE>")]) 6233 6234(define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16" 6235 [(set (match_operand:GPR2 0 "register_operand" "=t,t") 6236 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d,d") 6237 (match_operand:GPR 2 "sle_operand" "Udb8,i")))] 6238 "TARGET_MIPS16" 6239{ 6240 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 6241 return "slt<u>\t%1,%2"; 6242} 6243 [(set_attr "type" "slt") 6244 (set_attr "mode" "<GPR:MODE>") 6245 (set_attr "extended_mips16" "no,yes")]) 6246 6247;; 6248;; .................... 6249;; 6250;; FLOATING POINT COMPARISONS 6251;; 6252;; .................... 6253 6254(define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>" 6255 [(set (match_operand:FPCC 0 "register_operand" "=<reg>") 6256 (fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f") 6257 (match_operand:SCALARF 2 "register_operand" "f")))] 6258 "" 6259 "<fpcmp>.<fcond>.<fmt>\t%Z0%1,%2" 6260 [(set_attr "type" "fcmp") 6261 (set_attr "mode" "FPSW")]) 6262 6263(define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>" 6264 [(set (match_operand:FPCC 0 "register_operand" "=<reg>") 6265 (swapped_fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f") 6266 (match_operand:SCALARF 2 "register_operand" "f")))] 6267 "" 6268 "<fpcmp>.<swapped_fcond>.<fmt>\t%Z0%2,%1" 6269 [(set_attr "type" "fcmp") 6270 (set_attr "mode" "FPSW")]) 6271 6272;; 6273;; .................... 6274;; 6275;; UNCONDITIONAL BRANCHES 6276;; 6277;; .................... 6278 6279;; Unconditional branches. 6280 6281(define_expand "jump" 6282 [(set (pc) 6283 (label_ref (match_operand 0)))]) 6284 6285(define_insn "*jump_absolute" 6286 [(set (pc) 6287 (label_ref (match_operand 0)))] 6288 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS" 6289{ 6290 if (get_attr_length (insn) <= 8) 6291 { 6292 if (TARGET_CB_MAYBE) 6293 return MIPS_ABSOLUTE_JUMP ("%*b%:\t%l0"); 6294 else 6295 return MIPS_ABSOLUTE_JUMP ("%*b\t%l0%/"); 6296 } 6297 else 6298 { 6299 if (TARGET_CB_MAYBE && !final_sequence) 6300 return MIPS_ABSOLUTE_JUMP ("%*bc\t%l0"); 6301 else 6302 return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/"); 6303 } 6304} 6305 [(set_attr "type" "branch") 6306 (set_attr "compact_form" "maybe")]) 6307 6308(define_insn "*jump_pic" 6309 [(set (pc) 6310 (label_ref (match_operand 0)))] 6311 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS" 6312{ 6313 if (get_attr_length (insn) <= 8) 6314 { 6315 if (TARGET_CB_MAYBE) 6316 return "%*b%:\t%l0"; 6317 else 6318 return "%*b\t%l0%/"; 6319 } 6320 else 6321 { 6322 mips_output_load_label (operands[0]); 6323 if (TARGET_CB_MAYBE) 6324 return "%*jr%:\t%@%]"; 6325 else 6326 return "%*jr\t%@%/%]"; 6327 } 6328} 6329 [(set_attr "type" "branch") 6330 (set_attr "compact_form" "maybe")]) 6331 6332;; We need a different insn for the mips16, because a mips16 branch 6333;; does not have a delay slot. 6334 6335(define_insn "*jump_mips16" 6336 [(set (pc) 6337 (label_ref (match_operand 0 "" "")))] 6338 "TARGET_MIPS16" 6339 "b\t%l0" 6340 [(set_attr "type" "branch") 6341 (set (attr "length") 6342 ;; This calculation is like the normal branch one, but the 6343 ;; range of the unextended instruction is [-0x800, 0x7fe] rather 6344 ;; than [-0x100, 0xfe]. This translates to a range of: 6345 ;; 6346 ;; [-(0x800 - sizeof (branch)), 0x7fe] 6347 ;; == [-0x7fe, 0x7fe] 6348 ;; 6349 ;; from the shorten_branches reference address. Long-branch 6350 ;; sequences will replace this one, so the minimum length 6351 ;; is one instruction shorter than for conditional branches. 6352 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046)) 6353 (le (minus (pc) (match_dup 0)) (const_int 2046))) 6354 (const_int 2) 6355 (and (le (minus (match_dup 0) (pc)) (const_int 65534)) 6356 (le (minus (pc) (match_dup 0)) (const_int 65532))) 6357 (const_int 4) 6358 (and (match_test "TARGET_ABICALLS") 6359 (not (match_test "TARGET_ABSOLUTE_ABICALLS"))) 6360 (const_int 18) 6361 (match_test "Pmode == SImode") 6362 (const_int 14) 6363 ] (const_int 22)))]) 6364 6365(define_expand "indirect_jump" 6366 [(set (pc) (match_operand 0 "register_operand"))] 6367 "" 6368{ 6369 operands[0] = force_reg (Pmode, operands[0]); 6370 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0]))); 6371 DONE; 6372}) 6373 6374(define_insn "indirect_jump_<mode>" 6375 [(set (pc) (match_operand:P 0 "register_operand" "d"))] 6376 "" 6377 { 6378 return mips_output_jump (operands, 0, -1, false); 6379 } 6380 [(set_attr "type" "jump") 6381 (set_attr "mode" "none")]) 6382 6383;; A combined jump-and-move instruction, used for MIPS16 long-branch 6384;; sequences. Having a dedicated pattern is more convenient than 6385;; creating a SEQUENCE for this special case. 6386(define_insn "indirect_jump_and_restore_<mode>" 6387 [(set (pc) (match_operand:P 1 "register_operand" "d")) 6388 (set (match_operand:P 0 "register_operand" "=d") 6389 (match_operand:P 2 "register_operand" "y"))] 6390 "" 6391 "%(%<jr\t%1\;move\t%0,%2%>%)" 6392 [(set_attr "type" "multi") 6393 (set_attr "extended_mips16" "yes")]) 6394 6395(define_expand "tablejump" 6396 [(set (pc) 6397 (match_operand 0 "register_operand")) 6398 (use (label_ref (match_operand 1 "")))] 6399 "!TARGET_MIPS16_SHORT_JUMP_TABLES" 6400{ 6401 if (TARGET_GPWORD) 6402 operands[0] = expand_binop (Pmode, add_optab, operands[0], 6403 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN); 6404 else if (TARGET_RTP_PIC) 6405 { 6406 /* When generating RTP PIC, we use case table entries that are relative 6407 to the start of the function. Add the function's address to the 6408 value we loaded. */ 6409 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM); 6410 operands[0] = expand_binop (ptr_mode, add_optab, operands[0], 6411 start, 0, 0, OPTAB_WIDEN); 6412 } 6413 6414 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1]))); 6415 DONE; 6416}) 6417 6418(define_insn "tablejump_<mode>" 6419 [(set (pc) 6420 (match_operand:P 0 "register_operand" "d")) 6421 (use (label_ref (match_operand 1 "" "")))] 6422 "" 6423 { 6424 return mips_output_jump (operands, 0, -1, false); 6425 } 6426 [(set_attr "type" "jump") 6427 (set_attr "mode" "none")]) 6428 6429;; For MIPS16, we don't know whether a given jump table will use short or 6430;; word-sized offsets until late in compilation, when we are able to determine 6431;; the sizes of the insns which comprise the containing function. This 6432;; necessitates the use of the casesi rather than the tablejump pattern, since 6433;; the latter tries to calculate the index of the offset to jump through early 6434;; in compilation, i.e. at expand time, when nothing is known about the 6435;; eventual function layout. 6436 6437(define_expand "casesi" 6438 [(match_operand:SI 0 "register_operand" "") ; index to jump on 6439 (match_operand:SI 1 "const_int_operand" "") ; lower bound 6440 (match_operand:SI 2 "const_int_operand" "") ; total range 6441 (match_operand 3 "" "") ; table label 6442 (match_operand 4 "" "")] ; out of range label 6443 "TARGET_MIPS16_SHORT_JUMP_TABLES" 6444{ 6445 if (operands[1] != const0_rtx) 6446 { 6447 rtx reg = gen_reg_rtx (SImode); 6448 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode); 6449 6450 if (!arith_operand (offset, SImode)) 6451 offset = force_reg (SImode, offset); 6452 6453 emit_insn (gen_addsi3 (reg, operands[0], offset)); 6454 operands[0] = reg; 6455 } 6456 6457 if (!arith_operand (operands[0], SImode)) 6458 operands[0] = force_reg (SImode, operands[0]); 6459 6460 emit_cmp_and_jump_insns (operands[0], operands[2], GTU, 6461 NULL_RTX, SImode, 1, operands[4]); 6462 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16, 6463 (operands[0], operands[3]))); 6464 DONE; 6465}) 6466 6467(define_insn "casesi_internal_mips16_<mode>" 6468 [(set (pc) 6469 (unspec:P [(match_operand:SI 0 "register_operand" "d") 6470 (label_ref (match_operand 1 "" ""))] 6471 UNSPEC_CASESI_DISPATCH)) 6472 (clobber (match_scratch:P 2 "=d")) 6473 (clobber (match_scratch:P 3 "=d"))] 6474 "TARGET_MIPS16_SHORT_JUMP_TABLES" 6475{ 6476 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1]))); 6477 6478 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); 6479 6480 switch (GET_MODE (diff_vec)) 6481 { 6482 case E_HImode: 6483 output_asm_insn ("sll\t%3,%0,1", operands); 6484 output_asm_insn ("<d>la\t%2,%1", operands); 6485 output_asm_insn ("<d>addu\t%3,%2,%3", operands); 6486 output_asm_insn ("lh\t%3,0(%3)", operands); 6487 break; 6488 6489 case E_SImode: 6490 output_asm_insn ("sll\t%3,%0,2", operands); 6491 output_asm_insn ("<d>la\t%2,%1", operands); 6492 output_asm_insn ("<d>addu\t%3,%2,%3", operands); 6493 output_asm_insn ("lw\t%3,0(%3)", operands); 6494 break; 6495 6496 default: 6497 gcc_unreachable (); 6498 } 6499 6500 output_asm_insn ("<d>addu\t%2,%2,%3", operands); 6501 6502 if (GENERATE_MIPS16E) 6503 return "jrc\t%2"; 6504 else 6505 return "jr\t%2"; 6506} 6507 [(set (attr "insn_count") 6508 (if_then_else (match_test "GENERATE_MIPS16E") 6509 (const_string "6") 6510 (const_string "7")))]) 6511 6512;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well. 6513;; While it is possible to either pull it off the stack (in the 6514;; o32 case) or recalculate it given t9 and our target label, 6515;; it takes 3 or 4 insns to do so. 6516 6517(define_expand "builtin_setjmp_setup" 6518 [(use (match_operand 0 "register_operand"))] 6519 "TARGET_USE_GOT" 6520{ 6521 rtx addr; 6522 6523 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3); 6524 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx); 6525 DONE; 6526}) 6527 6528;; Restore the gp that we saved above. Despite the earlier comment, it seems 6529;; that older code did recalculate the gp from $25. Continue to jump through 6530;; $25 for compatibility (we lose nothing by doing so). 6531 6532(define_expand "builtin_longjmp" 6533 [(use (match_operand 0 "register_operand"))] 6534 "TARGET_USE_GOT" 6535{ 6536 /* The elements of the buffer are, in order: */ 6537 int W = GET_MODE_SIZE (Pmode); 6538 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 6539 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W)); 6540 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W)); 6541 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W)); 6542 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); 6543 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx. 6544 The target is bound to be using $28 as the global pointer 6545 but the current function might not be. */ 6546 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM); 6547 6548 /* This bit is similar to expand_builtin_longjmp except that it 6549 restores $gp as well. */ 6550 mips_emit_move (hard_frame_pointer_rtx, fp); 6551 mips_emit_move (pv, lab); 6552 emit_stack_restore (SAVE_NONLOCAL, stack); 6553 mips_emit_move (gp, gpv); 6554 emit_use (hard_frame_pointer_rtx); 6555 emit_use (stack_pointer_rtx); 6556 emit_use (gp); 6557 emit_indirect_jump (pv); 6558 DONE; 6559}) 6560 6561;; 6562;; .................... 6563;; 6564;; Function prologue/epilogue 6565;; 6566;; .................... 6567;; 6568 6569(define_expand "prologue" 6570 [(const_int 1)] 6571 "" 6572{ 6573 mips_expand_prologue (); 6574 DONE; 6575}) 6576 6577;; Block any insns from being moved before this point, since the 6578;; profiling call to mcount can use various registers that aren't 6579;; saved or used to pass arguments. 6580 6581(define_insn "blockage" 6582 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)] 6583 "" 6584 "" 6585 [(set_attr "type" "ghost") 6586 (set_attr "mode" "none")]) 6587 6588(define_insn "probe_stack_range_<P:mode>" 6589 [(set (match_operand:P 0 "register_operand" "=d") 6590 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0") 6591 (match_operand:P 2 "register_operand" "d")] 6592 UNSPEC_PROBE_STACK_RANGE))] 6593 "" 6594 { return mips_output_probe_stack_range (operands[0], operands[2]); } 6595 [(set_attr "type" "unknown") 6596 (set_attr "can_delay" "no") 6597 (set_attr "mode" "<MODE>")]) 6598 6599(define_expand "epilogue" 6600 [(const_int 2)] 6601 "" 6602{ 6603 mips_expand_epilogue (false); 6604 DONE; 6605}) 6606 6607(define_expand "sibcall_epilogue" 6608 [(const_int 2)] 6609 "" 6610{ 6611 mips_expand_epilogue (true); 6612 DONE; 6613}) 6614 6615;; Trivial return. Make it look like a normal return insn as that 6616;; allows jump optimizations to work better. 6617 6618(define_expand "return" 6619 [(simple_return)] 6620 "mips_can_use_return_insn ()" 6621 { mips_expand_before_return (); }) 6622 6623(define_expand "simple_return" 6624 [(simple_return)] 6625 "" 6626 { mips_expand_before_return (); }) 6627 6628(define_insn "*<optab>" 6629 [(any_return)] 6630 "" 6631 { 6632 operands[0] = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); 6633 return mips_output_jump (operands, 0, -1, false); 6634 } 6635 [(set_attr "type" "jump") 6636 (set_attr "mode" "none")]) 6637 6638;; Normal return. 6639 6640(define_insn "<optab>_internal" 6641 [(any_return) 6642 (use (match_operand 0 "pmode_register_operand" ""))] 6643 "" 6644 { 6645 return mips_output_jump (operands, 0, -1, false); 6646 } 6647 [(set_attr "type" "jump") 6648 (set_attr "mode" "none")]) 6649 6650;; Exception return. 6651(define_insn "mips_eret" 6652 [(return) 6653 (unspec_volatile [(const_int 0)] UNSPEC_ERET)] 6654 "" 6655 "eret" 6656 [(set_attr "type" "trap") 6657 (set_attr "mode" "none")]) 6658 6659;; Debug exception return. 6660(define_insn "mips_deret" 6661 [(return) 6662 (unspec_volatile [(const_int 0)] UNSPEC_DERET)] 6663 "" 6664 "deret" 6665 [(set_attr "type" "trap") 6666 (set_attr "mode" "none")]) 6667 6668;; Disable interrupts. 6669(define_insn "mips_di" 6670 [(unspec_volatile [(const_int 0)] UNSPEC_DI)] 6671 "" 6672 "di" 6673 [(set_attr "type" "trap") 6674 (set_attr "mode" "none")]) 6675 6676;; Execution hazard barrier. 6677(define_insn "mips_ehb" 6678 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)] 6679 "" 6680 "ehb" 6681 [(set_attr "type" "trap") 6682 (set_attr "mode" "none")]) 6683 6684;; Read GPR from previous shadow register set. 6685(define_insn "mips_rdpgpr_<mode>" 6686 [(set (match_operand:P 0 "register_operand" "=d") 6687 (unspec_volatile:P [(match_operand:P 1 "register_operand" "d")] 6688 UNSPEC_RDPGPR))] 6689 "" 6690 "rdpgpr\t%0,%1" 6691 [(set_attr "type" "move") 6692 (set_attr "mode" "<MODE>")]) 6693 6694;; Move involving COP0 registers. 6695(define_insn "cop0_move" 6696 [(set (match_operand:SI 0 "register_operand" "=B,d") 6697 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")] 6698 UNSPEC_COP0))] 6699 "" 6700{ return mips_output_move (operands[0], operands[1]); } 6701 [(set_attr "type" "mtc,mfc") 6702 (set_attr "mode" "SI")]) 6703 6704;; This is used in compiling the unwind routines. 6705(define_expand "eh_return" 6706 [(use (match_operand 0 "general_operand"))] 6707 "" 6708{ 6709 if (GET_MODE (operands[0]) != word_mode) 6710 operands[0] = convert_to_mode (word_mode, operands[0], 0); 6711 if (TARGET_64BIT) 6712 emit_insn (gen_eh_set_lr_di (operands[0])); 6713 else 6714 emit_insn (gen_eh_set_lr_si (operands[0])); 6715 DONE; 6716}) 6717 6718;; Clobber the return address on the stack. We can't expand this 6719;; until we know where it will be put in the stack frame. 6720 6721(define_insn "eh_set_lr_si" 6722 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN) 6723 (clobber (match_scratch:SI 1 "=&d"))] 6724 "! TARGET_64BIT" 6725 "#") 6726 6727(define_insn "eh_set_lr_di" 6728 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN) 6729 (clobber (match_scratch:DI 1 "=&d"))] 6730 "TARGET_64BIT" 6731 "#") 6732 6733(define_split 6734 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN) 6735 (clobber (match_scratch 1))] 6736 "reload_completed" 6737 [(const_int 0)] 6738{ 6739 mips_set_return_address (operands[0], operands[1]); 6740 DONE; 6741}) 6742 6743(define_expand "exception_receiver" 6744 [(const_int 0)] 6745 "TARGET_USE_GOT" 6746{ 6747 /* See the comment above load_call<mode> for details. */ 6748 emit_insn (gen_set_got_version ()); 6749 6750 /* If we have a call-clobbered $gp, restore it from its save slot. */ 6751 if (HAVE_restore_gp_si) 6752 emit_insn (gen_restore_gp_si ()); 6753 else if (HAVE_restore_gp_di) 6754 emit_insn (gen_restore_gp_di ()); 6755 DONE; 6756}) 6757 6758(define_expand "nonlocal_goto_receiver" 6759 [(const_int 0)] 6760 "TARGET_USE_GOT" 6761{ 6762 /* See the comment above load_call<mode> for details. */ 6763 emit_insn (gen_set_got_version ()); 6764 DONE; 6765}) 6766 6767;; Restore $gp from its .cprestore stack slot. The instruction remains 6768;; volatile until all uses of $28 are exposed. 6769(define_insn_and_split "restore_gp_<mode>" 6770 [(set (reg:P 28) 6771 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP)) 6772 (clobber (match_scratch:P 0 "=&d"))] 6773 "TARGET_CALL_CLOBBERED_GP" 6774 "#" 6775 "&& epilogue_completed" 6776 [(const_int 0)] 6777{ 6778 mips_restore_gp_from_cprestore_slot (operands[0]); 6779 DONE; 6780} 6781 [(set_attr "type" "ghost")]) 6782 6783;; Move between $gp and its register save slot. 6784(define_insn_and_split "move_gp<mode>" 6785 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m") 6786 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")] 6787 UNSPEC_MOVE_GP))] 6788 "" 6789 { return mips_must_initialize_gp_p () ? "#" : ""; } 6790 "mips_must_initialize_gp_p ()" 6791 [(const_int 0)] 6792{ 6793 mips_emit_move (operands[0], operands[1]); 6794 DONE; 6795} 6796 [(set_attr "type" "ghost")]) 6797 6798;; 6799;; .................... 6800;; 6801;; FUNCTION CALLS 6802;; 6803;; .................... 6804 6805;; Instructions to load a call address from the GOT. The address might 6806;; point to a function or to a lazy binding stub. In the latter case, 6807;; the stub will use the dynamic linker to resolve the function, which 6808;; in turn will change the GOT entry to point to the function's real 6809;; address. 6810;; 6811;; This means that every call, even pure and constant ones, can 6812;; potentially modify the GOT entry. And once a stub has been called, 6813;; we must not call it again. 6814;; 6815;; We represent this restriction using an imaginary, fixed, call-saved 6816;; register called GOT_VERSION_REGNUM. The idea is to make the register 6817;; live throughout the function and to change its value after every 6818;; potential call site. This stops any rtx value that uses the register 6819;; from being computed before an earlier call. To do this, we: 6820;; 6821;; - Ensure that the register is live on entry to the function, 6822;; so that it is never thought to be used uninitalized. 6823;; 6824;; - Ensure that the register is live on exit from the function, 6825;; so that it is live throughout. 6826;; 6827;; - Make each call (lazily-bound or not) use the current value 6828;; of GOT_VERSION_REGNUM, so that updates of the register are 6829;; not moved across call boundaries. 6830;; 6831;; - Add "ghost" definitions of the register to the beginning of 6832;; blocks reached by EH and ABNORMAL_CALL edges, because those 6833;; edges may involve calls that normal paths don't. (E.g. the 6834;; unwinding code that handles a non-call exception may change 6835;; lazily-bound GOT entries.) We do this by making the 6836;; exception_receiver and nonlocal_goto_receiver expanders emit 6837;; a set_got_version instruction. 6838;; 6839;; - After each call (lazily-bound or not), use a "ghost" 6840;; update_got_version instruction to change the register's value. 6841;; This instruction mimics the _possible_ effect of the dynamic 6842;; resolver during the call and it remains live even if the call 6843;; itself becomes dead. 6844;; 6845;; - Leave GOT_VERSION_REGNUM out of all register classes. 6846;; The register is therefore not a valid register_operand 6847;; and cannot be moved to or from other registers. 6848 6849(define_insn "load_call<mode>" 6850 [(set (match_operand:P 0 "register_operand" "=d") 6851 (unspec:P [(match_operand:P 1 "register_operand" "d") 6852 (match_operand:P 2 "immediate_operand" "") 6853 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))] 6854 "TARGET_USE_GOT" 6855 "<load>\t%0,%R2(%1)" 6856 [(set_attr "got" "load") 6857 (set_attr "mode" "<MODE>")]) 6858 6859(define_insn "set_got_version" 6860 [(set (reg:SI GOT_VERSION_REGNUM) 6861 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))] 6862 "TARGET_USE_GOT" 6863 "" 6864 [(set_attr "type" "ghost")]) 6865 6866(define_insn "update_got_version" 6867 [(set (reg:SI GOT_VERSION_REGNUM) 6868 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))] 6869 "TARGET_USE_GOT" 6870 "" 6871 [(set_attr "type" "ghost")]) 6872 6873;; Sibling calls. All these patterns use jump instructions. 6874 6875;; If TARGET_SIBCALLS, call_insn_operand will only accept constant 6876;; addresses if a direct jump is acceptable. Since the 'S' constraint 6877;; is defined in terms of call_insn_operand, the same is true of the 6878;; constraints. 6879 6880;; When we use an indirect jump, we need a register that will be 6881;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces 6882;; us to use $25 for this purpose -- and $25 is never clobbered by the 6883;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG 6884;; as well. 6885 6886(define_expand "sibcall" 6887 [(parallel [(call (match_operand 0 "") 6888 (match_operand 1 "")) 6889 (use (match_operand 2 "")) ;; next_arg_reg 6890 (use (match_operand 3 ""))])] ;; struct_value_size_rtx 6891 "TARGET_SIBCALLS" 6892{ 6893 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0), 6894 operands[1], operands[2], false); 6895 DONE; 6896}) 6897 6898(define_insn "sibcall_internal" 6899 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S")) 6900 (match_operand 1 "" ""))] 6901 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 6902 { return mips_output_jump (operands, 0, 1, false); } 6903 [(set_attr "jal" "indirect,direct") 6904 (set_attr "jal_macro" "no")]) 6905 6906(define_expand "sibcall_value" 6907 [(parallel [(set (match_operand 0 "") 6908 (call (match_operand 1 "") 6909 (match_operand 2 ""))) 6910 (use (match_operand 3 ""))])] ;; next_arg_reg 6911 "TARGET_SIBCALLS" 6912{ 6913 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0), 6914 operands[2], operands[3], false); 6915 DONE; 6916}) 6917 6918(define_insn "sibcall_value_internal" 6919 [(set (match_operand 0 "register_operand" "") 6920 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) 6921 (match_operand 2 "" "")))] 6922 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 6923 { return mips_output_jump (operands, 1, 2, false); } 6924 [(set_attr "jal" "indirect,direct") 6925 (set_attr "jal_macro" "no")]) 6926 6927(define_insn "sibcall_value_multiple_internal" 6928 [(set (match_operand 0 "register_operand" "") 6929 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) 6930 (match_operand 2 "" ""))) 6931 (set (match_operand 3 "register_operand" "") 6932 (call (mem:SI (match_dup 1)) 6933 (match_dup 2)))] 6934 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 6935 { return mips_output_jump (operands, 1, 2, false); } 6936 [(set_attr "jal" "indirect,direct") 6937 (set_attr "jal_macro" "no")]) 6938 6939(define_expand "call" 6940 [(parallel [(call (match_operand 0 "") 6941 (match_operand 1 "")) 6942 (use (match_operand 2 "")) ;; next_arg_reg 6943 (use (match_operand 3 ""))])] ;; struct_value_size_rtx 6944 "" 6945{ 6946 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0), 6947 operands[1], operands[2], false); 6948 DONE; 6949}) 6950 6951;; This instruction directly corresponds to an assembly-language "jal". 6952;; There are four cases: 6953;; 6954;; - -mno-abicalls: 6955;; Both symbolic and register destinations are OK. The pattern 6956;; always expands to a single mips instruction. 6957;; 6958;; - -mabicalls/-mno-explicit-relocs: 6959;; Again, both symbolic and register destinations are OK. 6960;; The call is treated as a multi-instruction black box. 6961;; 6962;; - -mabicalls/-mexplicit-relocs with n32 or n64: 6963;; Only "jal $25" is allowed. This expands to a single "jalr $25" 6964;; instruction. 6965;; 6966;; - -mabicalls/-mexplicit-relocs with o32 or o64: 6967;; Only "jal $25" is allowed. The call is actually two instructions: 6968;; "jalr $25" followed by an insn to reload $gp. 6969;; 6970;; In the last case, we can generate the individual instructions with 6971;; a define_split. There are several things to be wary of: 6972;; 6973;; - We can't expose the load of $gp before reload. If we did, 6974;; it might get removed as dead, but reload can introduce new 6975;; uses of $gp by rematerializing constants. 6976;; 6977;; - We shouldn't restore $gp after calls that never return. 6978;; It isn't valid to insert instructions between a noreturn 6979;; call and the following barrier. 6980;; 6981;; - The splitter deliberately changes the liveness of $gp. The unsplit 6982;; instruction preserves $gp and so have no effect on its liveness. 6983;; But once we generate the separate insns, it becomes obvious that 6984;; $gp is not live on entry to the call. 6985;; 6986(define_insn_and_split "call_internal" 6987 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S")) 6988 (match_operand 1 "" "")) 6989 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6990 "" 6991 { 6992 return (TARGET_SPLIT_CALLS ? "#" 6993 : mips_output_jump (operands, 0, 1, true)); 6994 } 6995 "reload_completed && TARGET_SPLIT_CALLS" 6996 [(const_int 0)] 6997{ 6998 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1])); 6999 DONE; 7000} 7001 [(set_attr "jal" "indirect,direct")]) 7002 7003(define_insn "call_split" 7004 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S")) 7005 (match_operand 1 "" "")) 7006 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7007 (clobber (reg:SI 28))] 7008 "TARGET_SPLIT_CALLS" 7009 { return mips_output_jump (operands, 0, 1, true); } 7010 [(set_attr "jal" "indirect,direct") 7011 (set_attr "jal_macro" "no")]) 7012 7013;; A pattern for calls that must be made directly. It is used for 7014;; MIPS16 calls that the linker may need to redirect to a hard-float 7015;; stub; the linker relies on the call relocation type to detect when 7016;; such redirection is needed. 7017(define_insn_and_split "call_internal_direct" 7018 [(call (mem:SI (match_operand 0 "const_call_insn_operand")) 7019 (match_operand 1)) 7020 (const_int 1) 7021 (clobber (reg:SI RETURN_ADDR_REGNUM))] 7022 "" 7023 { 7024 return (TARGET_SPLIT_CALLS ? "#" 7025 : mips_output_jump (operands, 0, -1, true)); 7026 } 7027 "reload_completed && TARGET_SPLIT_CALLS" 7028 [(const_int 0)] 7029{ 7030 mips_split_call (curr_insn, 7031 gen_call_direct_split (operands[0], operands[1])); 7032 DONE; 7033} 7034 [(set_attr "jal" "direct")]) 7035 7036(define_insn "call_direct_split" 7037 [(call (mem:SI (match_operand 0 "const_call_insn_operand")) 7038 (match_operand 1)) 7039 (const_int 1) 7040 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7041 (clobber (reg:SI 28))] 7042 "TARGET_SPLIT_CALLS" 7043 { return mips_output_jump (operands, 0, -1, true); } 7044 [(set_attr "jal" "direct") 7045 (set_attr "jal_macro" "no")]) 7046 7047(define_expand "call_value" 7048 [(parallel [(set (match_operand 0 "") 7049 (call (match_operand 1 "") 7050 (match_operand 2 ""))) 7051 (use (match_operand 3 ""))])] ;; next_arg_reg 7052 "" 7053{ 7054 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0), 7055 operands[2], operands[3], false); 7056 DONE; 7057}) 7058 7059;; See comment for call_internal. 7060(define_insn_and_split "call_value_internal" 7061 [(set (match_operand 0 "register_operand" "") 7062 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 7063 (match_operand 2 "" ""))) 7064 (clobber (reg:SI RETURN_ADDR_REGNUM))] 7065 "" 7066 { 7067 return (TARGET_SPLIT_CALLS ? "#" 7068 : mips_output_jump (operands, 1, 2, true)); 7069 } 7070 "reload_completed && TARGET_SPLIT_CALLS" 7071 [(const_int 0)] 7072{ 7073 mips_split_call (curr_insn, 7074 gen_call_value_split (operands[0], operands[1], 7075 operands[2])); 7076 DONE; 7077} 7078 [(set_attr "jal" "indirect,direct")]) 7079 7080(define_insn "call_value_split" 7081 [(set (match_operand 0 "register_operand" "") 7082 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 7083 (match_operand 2 "" ""))) 7084 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7085 (clobber (reg:SI 28))] 7086 "TARGET_SPLIT_CALLS" 7087 { return mips_output_jump (operands, 1, 2, true); } 7088 [(set_attr "jal" "indirect,direct") 7089 (set_attr "jal_macro" "no")]) 7090 7091;; See call_internal_direct. 7092(define_insn_and_split "call_value_internal_direct" 7093 [(set (match_operand 0 "register_operand") 7094 (call (mem:SI (match_operand 1 "const_call_insn_operand")) 7095 (match_operand 2))) 7096 (const_int 1) 7097 (clobber (reg:SI RETURN_ADDR_REGNUM))] 7098 "" 7099 { 7100 return (TARGET_SPLIT_CALLS ? "#" 7101 : mips_output_jump (operands, 1, -1, true)); 7102 } 7103 "reload_completed && TARGET_SPLIT_CALLS" 7104 [(const_int 0)] 7105{ 7106 mips_split_call (curr_insn, 7107 gen_call_value_direct_split (operands[0], operands[1], 7108 operands[2])); 7109 DONE; 7110} 7111 [(set_attr "jal" "direct")]) 7112 7113(define_insn "call_value_direct_split" 7114 [(set (match_operand 0 "register_operand") 7115 (call (mem:SI (match_operand 1 "const_call_insn_operand")) 7116 (match_operand 2))) 7117 (const_int 1) 7118 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7119 (clobber (reg:SI 28))] 7120 "TARGET_SPLIT_CALLS" 7121 { return mips_output_jump (operands, 1, -1, true); } 7122 [(set_attr "jal" "direct") 7123 (set_attr "jal_macro" "no")]) 7124 7125;; See comment for call_internal. 7126(define_insn_and_split "call_value_multiple_internal" 7127 [(set (match_operand 0 "register_operand" "") 7128 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 7129 (match_operand 2 "" ""))) 7130 (set (match_operand 3 "register_operand" "") 7131 (call (mem:SI (match_dup 1)) 7132 (match_dup 2))) 7133 (clobber (reg:SI RETURN_ADDR_REGNUM))] 7134 "" 7135 { 7136 return (TARGET_SPLIT_CALLS ? "#" 7137 : mips_output_jump (operands, 1, 2, true)); 7138 } 7139 "reload_completed && TARGET_SPLIT_CALLS" 7140 [(const_int 0)] 7141{ 7142 mips_split_call (curr_insn, 7143 gen_call_value_multiple_split (operands[0], operands[1], 7144 operands[2], operands[3])); 7145 DONE; 7146} 7147 [(set_attr "jal" "indirect,direct")]) 7148 7149(define_insn "call_value_multiple_split" 7150 [(set (match_operand 0 "register_operand" "") 7151 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 7152 (match_operand 2 "" ""))) 7153 (set (match_operand 3 "register_operand" "") 7154 (call (mem:SI (match_dup 1)) 7155 (match_dup 2))) 7156 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7157 (clobber (reg:SI 28))] 7158 "TARGET_SPLIT_CALLS" 7159 { return mips_output_jump (operands, 1, 2, true); } 7160 [(set_attr "jal" "indirect,direct") 7161 (set_attr "jal_macro" "no")]) 7162 7163;; Call subroutine returning any type. 7164 7165(define_expand "untyped_call" 7166 [(parallel [(call (match_operand 0 "") 7167 (const_int 0)) 7168 (match_operand 1 "") 7169 (match_operand 2 "")])] 7170 "" 7171{ 7172 int i; 7173 7174 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 7175 7176 for (i = 0; i < XVECLEN (operands[2], 0); i++) 7177 { 7178 rtx set = XVECEXP (operands[2], 0, i); 7179 mips_emit_move (SET_DEST (set), SET_SRC (set)); 7180 } 7181 7182 emit_insn (gen_blockage ()); 7183 DONE; 7184}) 7185 7186;; 7187;; .................... 7188;; 7189;; MISC. 7190;; 7191;; .................... 7192;; 7193 7194 7195(define_insn "prefetch" 7196 [(prefetch (match_operand:QI 0 "address_operand" "ZD") 7197 (match_operand 1 "const_int_operand" "n") 7198 (match_operand 2 "const_int_operand" "n"))] 7199 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" 7200{ 7201 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT) 7202 { 7203 /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching. */ 7204 if (TARGET_64BIT) 7205 return "ld\t$0,%a0"; 7206 else 7207 return "lw\t$0,%a0"; 7208 } 7209 /* Loongson ext2 implementation pref instructions. */ 7210 if (TARGET_LOONGSON_EXT2) 7211 { 7212 operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1], 7213 operands[2]); 7214 return "pref\t%1, %a0"; 7215 } 7216 operands[1] = mips_prefetch_cookie (operands[1], operands[2]); 7217 return "pref\t%1,%a0"; 7218} 7219 [(set_attr "type" "prefetch")]) 7220 7221(define_insn "*prefetch_indexed_<mode>" 7222 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d") 7223 (match_operand:P 1 "register_operand" "d")) 7224 (match_operand 2 "const_int_operand" "n") 7225 (match_operand 3 "const_int_operand" "n"))] 7226 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 7227{ 7228 if (TARGET_LOONGSON_EXT) 7229 { 7230 /* Loongson Loongson ext use index load to $0 for prefetching. */ 7231 if (TARGET_64BIT) 7232 return "gsldx\t$0,0(%0,%1)"; 7233 else 7234 return "gslwx\t$0,0(%0,%1)"; 7235 } 7236 /* Loongson ext2 implementation pref instructions. */ 7237 if (TARGET_LOONGSON_EXT2) 7238 { 7239 operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2], 7240 operands[3]); 7241 return "prefx\t%2,%1(%0)"; 7242 } 7243 operands[2] = mips_prefetch_cookie (operands[2], operands[3]); 7244 return "prefx\t%2,%1(%0)"; 7245} 7246 [(set_attr "type" "prefetchx")]) 7247 7248(define_insn "nop" 7249 [(const_int 0)] 7250 "" 7251 "%(nop%)" 7252 [(set_attr "type" "nop") 7253 (set_attr "mode" "none")]) 7254 7255;; Like nop, but commented out when outside a .set noreorder block. 7256(define_insn "hazard_nop" 7257 [(const_int 1)] 7258 "" 7259 { 7260 if (mips_noreorder.nesting_level > 0) 7261 return "nop"; 7262 else 7263 return "#nop"; 7264 } 7265 [(set_attr "type" "nop")]) 7266 7267;; The `.insn' pseudo-op. 7268(define_insn "insn_pseudo" 7269 [(unspec_volatile [(const_int 0)] UNSPEC_INSN_PSEUDO)] 7270 "" 7271 ".insn" 7272 [(set_attr "mode" "none") 7273 (set_attr "insn_count" "0")]) 7274 7275;; MIPS4 Conditional move instructions. 7276 7277(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>" 7278 [(set (match_operand:GPR 0 "register_operand" "=d,d") 7279 (if_then_else:GPR 7280 (match_operator 4 "equality_operator" 7281 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") 7282 (const_int 0)]) 7283 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") 7284 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] 7285 "ISA_HAS_CONDMOVE" 7286 "@ 7287 mov%T4\t%0,%z2,%1 7288 mov%t4\t%0,%z3,%1" 7289 [(set_attr "type" "condmove") 7290 (set_attr "mode" "<GPR:MODE>")]) 7291 7292(define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne" 7293 [(set (match_operand:GPR 0 "register_operand" "=d,d") 7294 (if_then_else:GPR 7295 (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>") 7296 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") 7297 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] 7298 "ISA_HAS_CONDMOVE" 7299 "@ 7300 movn\t%0,%z2,%1 7301 movz\t%0,%z3,%1" 7302 [(set_attr "type" "condmove") 7303 (set_attr "mode" "<GPR:MODE>")]) 7304 7305(define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>" 7306 [(set (match_operand:SCALARF 0 "register_operand" "=f,f") 7307 (if_then_else:SCALARF 7308 (match_operator 4 "equality_operator" 7309 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") 7310 (const_int 0)]) 7311 (match_operand:SCALARF 2 "register_operand" "f,0") 7312 (match_operand:SCALARF 3 "register_operand" "0,f")))] 7313 "ISA_HAS_FP_CONDMOVE" 7314 "@ 7315 mov%T4.<fmt>\t%0,%2,%1 7316 mov%t4.<fmt>\t%0,%3,%1" 7317 [(set_attr "type" "condmove") 7318 (set_attr "mode" "<SCALARF:MODE>")]) 7319 7320(define_insn "*sel<code><GPR:mode>_using_<GPR2:mode>" 7321 [(set (match_operand:GPR 0 "register_operand" "=d,d") 7322 (if_then_else:GPR 7323 (equality_op:GPR2 (match_operand:GPR2 1 "register_operand" "d,d") 7324 (const_int 0)) 7325 (match_operand:GPR 2 "reg_or_0_operand" "d,J") 7326 (match_operand:GPR 3 "reg_or_0_operand" "J,d")))] 7327 "ISA_HAS_SEL 7328 && (register_operand (operands[2], <GPR:MODE>mode) 7329 != register_operand (operands[3], <GPR:MODE>mode))" 7330 "@ 7331 <sel>\t%0,%2,%1 7332 <selinv>\t%0,%3,%1" 7333 [(set_attr "type" "condmove") 7334 (set_attr "mode" "<GPR:MODE>")]) 7335 7336;; sel.fmt copies the 3rd argument when the 1st is non-zero and the 2nd 7337;; argument if the 1st is zero. This means operand 2 and 3 are 7338;; inverted in the instruction. 7339 7340(define_insn "*sel<mode>" 7341 [(set (match_operand:SCALARF 0 "register_operand" "=f,f,f") 7342 (if_then_else:SCALARF 7343 (ne:CCF (match_operand:CCF 1 "register_operand" "0,f,f") 7344 (const_int 0)) 7345 (match_operand:SCALARF 2 "reg_or_0_operand" "f,G,f") 7346 (match_operand:SCALARF 3 "reg_or_0_operand" "f,f,G")))] 7347 "ISA_HAS_SEL && ISA_HAS_CCF" 7348 "@ 7349 sel.<fmt>\t%0,%3,%2 7350 seleqz.<fmt>\t%0,%3,%1 7351 selnez.<fmt>\t%0,%2,%1" 7352 [(set_attr "type" "condmove") 7353 (set_attr "mode" "<SCALARF:MODE>")]) 7354 7355;; These are the main define_expand's used to make conditional moves. 7356 7357(define_expand "mov<mode>cc" 7358 [(set (match_dup 4) (match_operand 1 "comparison_operator")) 7359 (set (match_operand:GPR 0 "register_operand") 7360 (if_then_else:GPR (match_dup 5) 7361 (match_operand:GPR 2 "reg_or_0_operand") 7362 (match_operand:GPR 3 "reg_or_0_operand")))] 7363 "ISA_HAS_CONDMOVE || ISA_HAS_SEL" 7364{ 7365 if (!ISA_HAS_FP_CONDMOVE 7366 && !INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0)))) 7367 FAIL; 7368 7369 mips_expand_conditional_move (operands); 7370 DONE; 7371}) 7372 7373(define_expand "mov<mode>cc" 7374 [(set (match_dup 4) (match_operand 1 "comparison_operator")) 7375 (set (match_operand:SCALARF 0 "register_operand") 7376 (if_then_else:SCALARF (match_dup 5) 7377 (match_operand:SCALARF 2 "reg_or_0_operand") 7378 (match_operand:SCALARF 3 "reg_or_0_operand")))] 7379 "ISA_HAS_FP_CONDMOVE 7380 || (ISA_HAS_SEL && ISA_HAS_CCF)" 7381{ 7382 if (ISA_HAS_SEL && !FLOAT_MODE_P (GET_MODE (XEXP (operands[1], 0)))) 7383 FAIL; 7384 7385 /* Workaround an LRA bug which means that tied operands in the sel.fmt 7386 pattern lead to the double precision destination of sel.d getting 7387 reloaded with the full register file usable and the restrictions on 7388 whether the CCFmode input can be used in odd-numbered single-precision 7389 registers are ignored. For consistency reasons the CCF mode values 7390 must be guaranteed to only exist in the even-registers because of 7391 the unusual duality between single and double precision values. */ 7392 if (ISA_HAS_SEL && <MODE>mode == DFmode 7393 && (!TARGET_ODD_SPREG || TARGET_FLOATXX)) 7394 FAIL; 7395 7396 mips_expand_conditional_move (operands); 7397 DONE; 7398}) 7399 7400;; 7401;; .................... 7402;; 7403;; mips16 inline constant tables 7404;; 7405;; .................... 7406;; 7407 7408(define_insn "consttable" 7409 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 7410 UNSPEC_CONSTTABLE)] 7411 "" 7412 "" 7413 [(set_attr "mode" "none") 7414 (set_attr "insn_count" "0")]) 7415 7416(define_insn "consttable_end" 7417 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 7418 UNSPEC_CONSTTABLE_END)] 7419 "" 7420 "" 7421 [(set_attr "mode" "none") 7422 (set_attr "insn_count" "0")]) 7423 7424(define_insn "consttable_tls_reloc" 7425 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "") 7426 (match_operand 1 "const_int_operand" "")] 7427 UNSPEC_CONSTTABLE_INT)] 7428 "TARGET_MIPS16_PCREL_LOADS" 7429 { return mips_output_tls_reloc_directive (&operands[0]); } 7430 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))]) 7431 7432(define_insn "consttable_int" 7433 [(unspec_volatile [(match_operand 0 "consttable_operand" "") 7434 (match_operand 1 "const_int_operand" "")] 7435 UNSPEC_CONSTTABLE_INT)] 7436 "TARGET_MIPS16" 7437{ 7438 assemble_integer (mips_strip_unspec_address (operands[0]), 7439 INTVAL (operands[1]), 7440 BITS_PER_UNIT * INTVAL (operands[1]), 1); 7441 return ""; 7442} 7443 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))]) 7444 7445(define_insn "consttable_float" 7446 [(unspec_volatile [(match_operand 0 "consttable_operand" "")] 7447 UNSPEC_CONSTTABLE_FLOAT)] 7448 "TARGET_MIPS16" 7449{ 7450 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE); 7451 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]), 7452 as_a <scalar_float_mode> (GET_MODE (operands[0])), 7453 GET_MODE_BITSIZE (GET_MODE (operands[0]))); 7454 return ""; 7455} 7456 [(set (attr "length") 7457 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))]) 7458 7459(define_insn "align" 7460 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)] 7461 "" 7462 ".align\t%0" 7463 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))]) 7464 7465(define_split 7466 [(match_operand 0 "small_data_pattern")] 7467 "reload_completed" 7468 [(match_dup 0)] 7469 { operands[0] = mips_rewrite_small_data (operands[0]); }) 7470 7471;; 7472;; .................... 7473;; 7474;; MIPS16e Save/Restore 7475;; 7476;; .................... 7477;; 7478 7479(define_insn "*mips16e_save_restore" 7480 [(match_parallel 0 "" 7481 [(set (match_operand:SI 1 "register_operand") 7482 (plus:SI (match_dup 1) 7483 (match_operand:SI 2 "const_int_operand")))])] 7484 "operands[1] == stack_pointer_rtx 7485 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)" 7486 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); } 7487 [(set_attr "type" "arith") 7488 (set_attr "extended_mips16" "yes")]) 7489 7490;; Thread-Local Storage 7491 7492;; The TLS base pointer is accessed via "rdhwr $3, $29". No current 7493;; MIPS architecture defines this register, and no current 7494;; implementation provides it; instead, any OS which supports TLS is 7495;; expected to trap and emulate this instruction. rdhwr is part of the 7496;; MIPS 32r2 specification, but we use it on any architecture because 7497;; we expect it to be emulated. Use .set to force the assembler to 7498;; accept it. 7499;; 7500;; We do not use a constraint to force the destination to be $3 7501;; because $3 can appear explicitly as a function return value. 7502;; If we leave the use of $3 implicit in the constraints until 7503;; reload, we may end up making a $3 return value live across 7504;; the instruction, leading to a spill failure when reloading it. 7505(define_insn_and_split "tls_get_tp_<mode>" 7506 [(set (match_operand:P 0 "register_operand" "=d") 7507 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) 7508 (clobber (reg:P TLS_GET_TP_REGNUM))] 7509 "HAVE_AS_TLS && !TARGET_MIPS16" 7510 "#" 7511 "&& reload_completed" 7512 [(set (reg:P TLS_GET_TP_REGNUM) 7513 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) 7514 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))] 7515 "" 7516 [(set_attr "type" "unknown") 7517 (set_attr "mode" "<MODE>") 7518 (set_attr "insn_count" "2")]) 7519 7520(define_insn "*tls_get_tp_<mode>_split" 7521 [(set (reg:P TLS_GET_TP_REGNUM) 7522 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))] 7523 "HAVE_AS_TLS && !TARGET_MIPS16" 7524 { 7525 if (mips_isa_rev >= 2) 7526 return "rdhwr\t$3,$29"; 7527 7528 return ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"; 7529 } 7530 [(set_attr "type" "unknown") 7531 ; Since rdhwr always generates a trap for now, putting it in a delay 7532 ; slot would make the kernel's emulation of it much slower. 7533 (set_attr "can_delay" "no") 7534 (set_attr "mode" "<MODE>")]) 7535 7536;; In MIPS16 mode, the TLS base pointer is accessed by a 7537;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not 7538;; accessible in MIPS16. 7539;; 7540;; This is not represented as a call insn, to avoid the 7541;; unnecesarry clobbering of caller-save registers by a 7542;; function consisting only of: "rdhwr $3,$29; j $31; nop;" 7543;; 7544;; A $25 clobber is added to cater for a $25 load stub added by the 7545;; linker to __mips16_rdhwr when the call is made from non-PIC code. 7546 7547(define_insn_and_split "tls_get_tp_mips16_<mode>" 7548 [(set (match_operand:P 0 "register_operand" "=d") 7549 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")] 7550 UNSPEC_TLS_GET_TP)) 7551 (clobber (reg:P TLS_GET_TP_REGNUM)) 7552 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7553 (clobber (reg:P RETURN_ADDR_REGNUM))] 7554 "HAVE_AS_TLS && TARGET_MIPS16" 7555 "#" 7556 "&& reload_completed" 7557 [(parallel [(set (reg:P TLS_GET_TP_REGNUM) 7558 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP)) 7559 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7560 (clobber (reg:P RETURN_ADDR_REGNUM))]) 7561 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))] 7562 "" 7563 [(set_attr "type" "multi") 7564 (set_attr "insn_count" "4") 7565 (set_attr "mode" "<MODE>")]) 7566 7567(define_insn "*tls_get_tp_mips16_call_<mode>" 7568 [(set (reg:P TLS_GET_TP_REGNUM) 7569 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")] 7570 UNSPEC_TLS_GET_TP)) 7571 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7572 (clobber (reg:P RETURN_ADDR_REGNUM))] 7573 "HAVE_AS_TLS && TARGET_MIPS16" 7574 { return mips_output_jump (operands, 0, -1, true); } 7575 [(set_attr "type" "call") 7576 (set_attr "insn_count" "3") 7577 (set_attr "mode" "<MODE>")]) 7578 7579;; Named pattern for expanding thread pointer reference. 7580(define_expand "get_thread_pointer<mode>" 7581 [(match_operand:P 0 "register_operand" "=d")] 7582 "HAVE_AS_TLS" 7583{ 7584 mips_expand_thread_pointer (operands[0]); 7585 DONE; 7586}) 7587 7588;; __builtin_mips_get_fcsr: move the FCSR into operand 0. 7589(define_expand "mips_get_fcsr" 7590 [(set (match_operand:SI 0 "register_operand") 7591 (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] 7592 "TARGET_HARD_FLOAT_ABI" 7593{ 7594 if (TARGET_MIPS16) 7595 { 7596 mips16_expand_get_fcsr (operands[0]); 7597 DONE; 7598 } 7599}) 7600 7601(define_insn "*mips_get_fcsr" 7602 [(set (match_operand:SI 0 "register_operand" "=d") 7603 (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] 7604 "TARGET_HARD_FLOAT" 7605 "cfc1\t%0,$31") 7606 7607;; See tls_get_tp_mips16_<mode> for why this form is used. 7608(define_insn "mips_get_fcsr_mips16_<mode>" 7609 [(set (reg:SI GET_FCSR_REGNUM) 7610 (unspec:SI [(match_operand:P 0 "call_insn_operand" "dS")] 7611 UNSPEC_GET_FCSR)) 7612 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7613 (clobber (reg:P RETURN_ADDR_REGNUM))] 7614 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16" 7615 { return mips_output_jump (operands, 0, -1, true); } 7616 [(set_attr "type" "call") 7617 (set_attr "insn_count" "3")]) 7618 7619;; __builtin_mips_set_fcsr: move operand 0 into the FCSR. 7620(define_expand "mips_set_fcsr" 7621 [(unspec_volatile [(match_operand:SI 0 "register_operand")] 7622 UNSPEC_SET_FCSR)] 7623 "TARGET_HARD_FLOAT_ABI" 7624{ 7625 if (TARGET_MIPS16) 7626 { 7627 mips16_expand_set_fcsr (operands[0]); 7628 DONE; 7629 } 7630}) 7631 7632(define_insn "*mips_set_fcsr" 7633 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] 7634 UNSPEC_SET_FCSR)] 7635 "TARGET_HARD_FLOAT" 7636 "ctc1\t%0,$31") 7637 7638;; See tls_get_tp_mips16_<mode> for why this form is used. 7639(define_insn "mips_set_fcsr_mips16_<mode>" 7640 [(unspec_volatile:SI [(match_operand:P 0 "call_insn_operand" "dS") 7641 (reg:SI SET_FCSR_REGNUM)] UNSPEC_SET_FCSR) 7642 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7643 (clobber (reg:P RETURN_ADDR_REGNUM))] 7644 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16" 7645 { return mips_output_jump (operands, 0, -1, true); } 7646 [(set_attr "type" "call") 7647 (set_attr "insn_count" "3")]) 7648 7649;; Match paired HI/SI/SF/DFmode load/stores. 7650(define_insn "*join2_load_store<JOIN_MODE:mode>" 7651 [(set (match_operand:JOIN_MODE 0 "nonimmediate_operand" "=d,f,m,m") 7652 (match_operand:JOIN_MODE 1 "nonimmediate_operand" "m,m,d,f")) 7653 (set (match_operand:JOIN_MODE 2 "nonimmediate_operand" "=d,f,m,m") 7654 (match_operand:JOIN_MODE 3 "nonimmediate_operand" "m,m,d,f"))] 7655 "ENABLE_LD_ST_PAIRS && reload_completed" 7656 { 7657 bool load_p = (which_alternative == 0 || which_alternative == 1); 7658 /* Reg-renaming pass reuses base register if it is dead after bonded loads. 7659 Hardware does not bond those loads, even when they are consecutive. 7660 However, order of the loads need to be checked for correctness. */ 7661 if (!load_p || !reg_overlap_mentioned_p (operands[0], operands[1])) 7662 { 7663 output_asm_insn (mips_output_move (operands[0], operands[1]), 7664 operands); 7665 output_asm_insn (mips_output_move (operands[2], operands[3]), 7666 &operands[2]); 7667 } 7668 else 7669 { 7670 output_asm_insn (mips_output_move (operands[2], operands[3]), 7671 &operands[2]); 7672 output_asm_insn (mips_output_move (operands[0], operands[1]), 7673 operands); 7674 } 7675 return ""; 7676 } 7677 [(set_attr "move_type" "load,fpload,store,fpstore") 7678 (set_attr "insn_count" "2,2,2,2")]) 7679 7680;; 2 HI/SI/SF/DF loads are joined. 7681;; P5600 does not support bonding of two LBs, hence QI mode is not included. 7682;; The loads must be non-volatile as they might be reordered at the time of asm 7683;; generation. 7684(define_peephole2 7685 [(set (match_operand:JOIN_MODE 0 "register_operand") 7686 (match_operand:JOIN_MODE 1 "non_volatile_mem_operand")) 7687 (set (match_operand:JOIN_MODE 2 "register_operand") 7688 (match_operand:JOIN_MODE 3 "non_volatile_mem_operand"))] 7689 "ENABLE_LD_ST_PAIRS 7690 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, true)" 7691 [(parallel [(set (match_dup 0) 7692 (match_dup 1)) 7693 (set (match_dup 2) 7694 (match_dup 3))])] 7695 "") 7696 7697;; 2 HI/SI/SF/DF stores are joined. 7698;; P5600 does not support bonding of two SBs, hence QI mode is not included. 7699(define_peephole2 7700 [(set (match_operand:JOIN_MODE 0 "memory_operand") 7701 (match_operand:JOIN_MODE 1 "register_operand")) 7702 (set (match_operand:JOIN_MODE 2 "memory_operand") 7703 (match_operand:JOIN_MODE 3 "register_operand"))] 7704 "ENABLE_LD_ST_PAIRS 7705 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, false)" 7706 [(parallel [(set (match_dup 0) 7707 (match_dup 1)) 7708 (set (match_dup 2) 7709 (match_dup 3))])] 7710 "") 7711 7712;; Match paired HImode loads. 7713(define_insn "*join2_loadhi" 7714 [(set (match_operand:SI 0 "register_operand" "=r") 7715 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand" "m"))) 7716 (set (match_operand:SI 2 "register_operand" "=r") 7717 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand" "m")))] 7718 "ENABLE_LD_ST_PAIRS && reload_completed" 7719 { 7720 /* Reg-renaming pass reuses base register if it is dead after bonded loads. 7721 Hardware does not bond those loads, even when they are consecutive. 7722 However, order of the loads need to be checked for correctness. */ 7723 if (!reg_overlap_mentioned_p (operands[0], operands[1])) 7724 { 7725 output_asm_insn ("lh<u>\t%0,%1", operands); 7726 output_asm_insn ("lh<u>\t%2,%3", operands); 7727 } 7728 else 7729 { 7730 output_asm_insn ("lh<u>\t%2,%3", operands); 7731 output_asm_insn ("lh<u>\t%0,%1", operands); 7732 } 7733 7734 return ""; 7735 } 7736 [(set_attr "move_type" "load") 7737 (set_attr "insn_count" "2")]) 7738 7739 7740;; 2 HI loads are joined. 7741(define_peephole2 7742 [(set (match_operand:SI 0 "register_operand") 7743 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand"))) 7744 (set (match_operand:SI 2 "register_operand") 7745 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand")))] 7746 "ENABLE_LD_ST_PAIRS 7747 && mips_load_store_bonding_p (operands, HImode, true)" 7748 [(parallel [(set (match_dup 0) 7749 (any_extend:SI (match_dup 1))) 7750 (set (match_dup 2) 7751 (any_extend:SI (match_dup 3)))])] 7752 "") 7753 7754 7755;; Synchronization instructions. 7756 7757(include "sync.md") 7758 7759; The MIPS Paired-Single Floating Point and MIPS-3D Instructions. 7760 7761(include "mips-ps-3d.md") 7762 7763; The MIPS DSP Instructions. 7764 7765(include "mips-dsp.md") 7766 7767; The MIPS DSP REV 2 Instructions. 7768 7769(include "mips-dspr2.md") 7770 7771; MIPS fixed-point instructions. 7772(include "mips-fixed.md") 7773 7774; microMIPS patterns. 7775(include "micromips.md") 7776 7777; Loongson MultiMedia extensions Instructions (MMI) patterns. 7778(include "loongson-mmi.md") 7779 7780; The MIPS MSA Instructions. 7781(include "mips-msa.md") 7782 7783(define_c_enum "unspec" [ 7784 UNSPEC_ADDRESS_FIRST 7785]) 7786