1 /* Verify that overloaded built-ins for vec_insert() with long long
2 inputs produce the right codegen. */
3
4 /* { dg-do compile { target { powerpc*-*-linux* } } } */
5 /* { dg-require-effective-target powerpc_p8vector_ok } */
6 /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
7
8 #include <altivec.h>
9
10 vector bool long long
testbl_var(unsigned long long x,vector bool long long v,signed int i)11 testbl_var(unsigned long long x, vector bool long long v, signed int i)
12 {
13 return vec_insert(x, v, i);
14 }
15
16 vector signed long long
testsl_var(signed long long x,vector signed long long v,signed int i)17 testsl_var(signed long long x, vector signed long long v, signed int i)
18 {
19 return vec_insert(x, v, i);
20 }
21
22 vector unsigned long long
testul1_var(signed long long x,vector unsigned long long v,signed int i)23 testul1_var(signed long long x, vector unsigned long long v, signed int i)
24 {
25 return vec_insert(x, v, i);
26 }
27
28 vector unsigned long long
testul2_var(unsigned long long x,vector unsigned long long v,signed int i)29 testul2_var(unsigned long long x, vector unsigned long long v, signed int i)
30 {
31 return vec_insert(x, v, i);
32 }
33
34 vector bool long long
testbl_cst(unsigned long long x,vector bool long long v)35 testbl_cst(unsigned long long x, vector bool long long v)
36 {
37 return vec_insert(x, v, 12);
38 }
39
40 vector signed long long
testsl_cst(signed long long x,vector signed long long v)41 testsl_cst(signed long long x, vector signed long long v)
42 {
43 return vec_insert(x, v, 12);
44 }
45
46 vector unsigned long long
testul1_cst(signed long long x,vector unsigned long long v)47 testul1_cst(signed long long x, vector unsigned long long v)
48 {
49 return vec_insert(x, v, 12);
50 }
51
52 vector unsigned long long
testul2_cst(unsigned long long x,vector unsigned long long v)53 testul2_cst(unsigned long long x, vector unsigned long long v)
54 {
55 return vec_insert(x, v, 12);
56 }
57
58 /* Number of xxpermdi insns varies between power targets. ensure at least one. */
59 /* { dg-final { scan-assembler {\mxxpermdi\M} } } */
60
61 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 4 } } */
62
63 /* The number of addi instructions decreases on newer systems. Measured as 8 on
64 power7 and power8 targets, and drops to 4 on power9 targets that use the
65 newer stxv,lxv instructions. For this test ensure we get at least one. */
66 /* { dg-final { scan-assembler {\maddi\M} } } */
67 /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 4 } } */
68 /* { dg-final { scan-assembler-times {\mstdx\M} 4 { target lp64 } } } */
69 /* { dg-final { scan-assembler-times {\mstw\M} 8 { target ilp32 } } } */
70
71 /* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 4 } } */
72
73