1 /* Verify that overloaded built-ins for vec_min with int
2 inputs produce the right results. */
3
4 /* { dg-do compile } */
5 /* { dg-require-effective-target powerpc_altivec_ok } */
6 /* { dg-options "-maltivec -O2" } */
7
8 #include <altivec.h>
9
10 vector signed int
test3_min(vector signed int x,vector signed int y)11 test3_min (vector signed int x, vector signed int y)
12 {
13 return vec_min (x, y);
14 }
15
16 vector unsigned int
test6_min(vector unsigned int x,vector unsigned int y)17 test6_min (vector unsigned int x, vector unsigned int y)
18 {
19 return vec_min (x, y);
20 }
21
22 vector signed int
test3_max(vector signed int x,vector signed int y)23 test3_max (vector signed int x, vector signed int y)
24 {
25 return vec_max (x, y);
26 }
27
28 vector unsigned int
test6_max(vector unsigned int x,vector unsigned int y)29 test6_max (vector unsigned int x, vector unsigned int y)
30 {
31 return vec_max (x, y);
32 }
33
34 vector signed int
test4_min(vector bool int x,vector signed int y)35 test4_min (vector bool int x, vector signed int y)
36 {
37 return vec_min (x, y);
38 }
39
40 vector signed int
test5_min(vector signed int x,vector bool int y)41 test5_min (vector signed int x, vector bool int y)
42 {
43 return vec_min (x, y);
44 }
45
46 vector unsigned int
test7_min(vector bool int x,vector unsigned int y)47 test7_min (vector bool int x, vector unsigned int y)
48 {
49 return vec_min (x, y);
50 }
51
52 vector unsigned int
test8_min(vector unsigned int x,vector bool int y)53 test8_min (vector unsigned int x, vector bool int y)
54 {
55 return vec_min (x, y);
56 }
57
58 /* { dg-final { scan-assembler-times "vminsw" 3 } } */
59 /* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
60 /* { dg-final { scan-assembler-times "vminuw" 3 } } */
61 /* { dg-final { scan-assembler-times "vmaxuw" 1 } } */
62