1 /* Definitions of target machine for GNU compiler. 2 Matsushita MN10300 series 3 Copyright (C) 1996-2016 Free Software Foundation, Inc. 4 Contributed by Jeff Law (law@cygnus.com). 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #undef ASM_SPEC 23 #undef LIB_SPEC 24 #undef ENDFILE_SPEC 25 #undef LINK_SPEC 26 #define LINK_SPEC "%{mrelax:%{!r:--relax}}" 27 #undef STARTFILE_SPEC 28 #define STARTFILE_SPEC "%{!mno-crt0:%{!shared:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}" 29 30 /* Names to predefine in the preprocessor for this target machine. */ 31 32 #define TARGET_CPU_CPP_BUILTINS() \ 33 do \ 34 { \ 35 builtin_define ("__mn10300__"); \ 36 builtin_define ("__MN10300__"); \ 37 builtin_assert ("cpu=mn10300"); \ 38 builtin_assert ("machine=mn10300"); \ 39 \ 40 if (TARGET_AM34) \ 41 { \ 42 builtin_define ("__AM33__=4"); \ 43 builtin_define ("__AM34__"); \ 44 } \ 45 else if (TARGET_AM33_2) \ 46 { \ 47 builtin_define ("__AM33__=2"); \ 48 builtin_define ("__AM33_2__"); \ 49 } \ 50 else if (TARGET_AM33) \ 51 builtin_define ("__AM33__=1"); \ 52 \ 53 builtin_define (TARGET_ALLOW_LIW ? \ 54 "__LIW__" : "__NO_LIW__");\ 55 \ 56 builtin_define (TARGET_ALLOW_SETLB ? \ 57 "__SETLB__" : "__NO_SETLB__");\ 58 } \ 59 while (0) 60 61 #ifndef MN10300_OPTS_H 62 #include "config/mn10300/mn10300-opts.h" 63 #endif 64 65 extern enum processor_type mn10300_tune_cpu; 66 67 #define TARGET_AM33 (mn10300_processor >= PROCESSOR_AM33) 68 #define TARGET_AM33_2 (mn10300_processor >= PROCESSOR_AM33_2) 69 #define TARGET_AM34 (mn10300_processor >= PROCESSOR_AM34) 70 71 #ifndef PROCESSOR_DEFAULT 72 #define PROCESSOR_DEFAULT PROCESSOR_MN10300 73 #endif 74 75 76 /* Target machine storage layout */ 77 78 /* Define this if most significant bit is lowest numbered 79 in instructions that operate on numbered bit-fields. 80 This is not true on the Matsushita MN1003. */ 81 #define BITS_BIG_ENDIAN 0 82 83 /* Define this if most significant byte of a word is the lowest numbered. */ 84 /* This is not true on the Matsushita MN10300. */ 85 #define BYTES_BIG_ENDIAN 0 86 87 /* Define this if most significant word of a multiword number is lowest 88 numbered. 89 This is not true on the Matsushita MN10300. */ 90 #define WORDS_BIG_ENDIAN 0 91 92 /* Width of a word, in units (bytes). */ 93 #define UNITS_PER_WORD 4 94 95 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 96 #define PARM_BOUNDARY 32 97 98 /* The stack goes in 32-bit lumps. */ 99 #define STACK_BOUNDARY 32 100 101 /* Allocation boundary (in *bits*) for the code of a function. 102 8 is the minimum boundary; it's unclear if bigger alignments 103 would improve performance. */ 104 #define FUNCTION_BOUNDARY 8 105 106 /* No data type wants to be aligned rounder than this. */ 107 #define BIGGEST_ALIGNMENT 32 108 109 /* Alignment of field after `int : 0' in a structure. */ 110 #define EMPTY_FIELD_BOUNDARY 32 111 112 /* Define this if move instructions will actually fail to work 113 when given unaligned data. */ 114 #define STRICT_ALIGNMENT 1 115 116 /* Define this as 1 if `char' should by default be signed; else as 0. */ 117 #define DEFAULT_SIGNED_CHAR 0 118 119 #undef SIZE_TYPE 120 #define SIZE_TYPE "unsigned int" 121 122 #undef PTRDIFF_TYPE 123 #define PTRDIFF_TYPE "int" 124 125 #undef WCHAR_TYPE 126 #define WCHAR_TYPE "long int" 127 128 #undef WCHAR_TYPE_SIZE 129 #define WCHAR_TYPE_SIZE BITS_PER_WORD 130 131 /* Standard register usage. */ 132 133 /* Number of actual hardware registers. 134 The hardware registers are assigned numbers for the compiler 135 from 0 to just below FIRST_PSEUDO_REGISTER. 136 137 All registers that the compiler knows about must be given numbers, 138 even those that are not normally considered general registers. */ 139 140 #define FIRST_PSEUDO_REGISTER 52 141 142 /* Specify machine-specific register numbers. The commented out entries 143 are defined in mn10300.md. */ 144 #define FIRST_DATA_REGNUM 0 145 #define LAST_DATA_REGNUM 3 146 #define FIRST_ADDRESS_REGNUM 4 147 /* #define PIC_REG 6 */ 148 #define LAST_ADDRESS_REGNUM 8 149 /* #define SP_REG 9 */ 150 #define FIRST_EXTENDED_REGNUM 10 151 #define LAST_EXTENDED_REGNUM 17 152 #define FIRST_FP_REGNUM 18 153 #define LAST_FP_REGNUM 49 154 /* #define MDR_REG 50 */ 155 /* #define CC_REG 51 */ 156 #define FIRST_ARGUMENT_REGNUM 0 157 158 /* Specify the registers used for certain standard purposes. 159 The values of these macros are register numbers. */ 160 161 /* Register to use for pushing function arguments. */ 162 #define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) 163 164 /* Base register for access to local variables of the function. */ 165 #define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM - 1) 166 167 /* Base register for access to arguments of the function. This 168 is a fake register and will be eliminated into either the frame 169 pointer or stack pointer. */ 170 #define ARG_POINTER_REGNUM LAST_ADDRESS_REGNUM 171 172 /* Register in which static-chain is passed to a function. */ 173 #define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) 174 175 /* 1 for registers that have pervasive standard uses 176 and are not available for the register allocator. */ 177 178 #define FIXED_REGISTERS \ 179 { 0, 0, 0, 0, /* data regs */ \ 180 0, 0, 0, 0, /* addr regs */ \ 181 1, /* arg reg */ \ 182 1, /* sp reg */ \ 183 0, 0, 0, 0, 0, 0, 0, 0, /* extended regs */ \ 184 0, 0, /* fp regs (18-19) */ \ 185 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \ 186 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (30-39) */ \ 187 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (40-49) */ \ 188 0, /* mdr reg */ \ 189 1 /* cc reg */ \ 190 } 191 192 /* 1 for registers not available across function calls. 193 These must include the FIXED_REGISTERS and also any 194 registers that can be used without being saved. 195 The latter must include the registers where values are returned 196 and the register where structure-value addresses are passed. 197 Aside from that, you can include as many other registers as you 198 like. */ 199 200 #define CALL_USED_REGISTERS \ 201 { 1, 1, 0, 0, /* data regs */ \ 202 1, 1, 0, 0, /* addr regs */ \ 203 1, /* arg reg */ \ 204 1, /* sp reg */ \ 205 1, 1, 1, 1, 0, 0, 0, 0, /* extended regs */ \ 206 1, 1, /* fp regs (18-19) */ \ 207 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \ 208 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, /* fp regs (30-39) */ \ 209 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* fp regs (40-49) */ \ 210 1, /* mdr reg */ \ 211 1 /* cc reg */ \ 212 } 213 214 /* Note: The definition of CALL_REALLY_USED_REGISTERS is not 215 redundant. It is needed when compiling in PIC mode because 216 the a2 register becomes fixed (and hence must be marked as 217 call_used) but in order to preserve the ABI it is not marked 218 as call_really_used. */ 219 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS 220 221 #define REG_ALLOC_ORDER \ 222 { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9 \ 223 , 42, 43, 44, 45, 46, 47, 48, 49, 34, 35, 36, 37, 38, 39, 40, 41 \ 224 , 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 50, 51 \ 225 } 226 227 /* Return number of consecutive hard regs needed starting at reg REGNO 228 to hold something of mode MODE. 229 230 This is ordinarily the length in words of a value of mode MODE 231 but can be less for certain modes in special long registers. */ 232 233 #define HARD_REGNO_NREGS(REGNO, MODE) \ 234 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 235 236 /* Value is 1 if hard register REGNO can hold a value of machine-mode 237 MODE. */ 238 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 239 mn10300_hard_regno_mode_ok ((REGNO), (MODE)) 240 241 /* Value is 1 if it is a good idea to tie two pseudo registers 242 when one has mode MODE1 and one has mode MODE2. 243 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 244 for any hard reg, then this must be 0 for correct output. */ 245 #define MODES_TIEABLE_P(MODE1, MODE2) \ 246 mn10300_modes_tieable ((MODE1), (MODE2)) 247 248 /* 4 data, and effectively 3 address registers is small as far as I'm 249 concerned. */ 250 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 251 252 /* Define the classes of registers for register constraints in the 253 machine description. Also define ranges of constants. 254 255 One of the classes must always be named ALL_REGS and include all hard regs. 256 If there is more than one class, another class must be named NO_REGS 257 and contain no registers. 258 259 The name GENERAL_REGS must be the name of a class (or an alias for 260 another name such as ALL_REGS). This is the class of registers 261 that is allowed by "g" or "r" in a register constraint. 262 Also, registers outside this class are allocated only when 263 instructions express preferences for them. 264 265 The classes must be numbered in nondecreasing order; that is, 266 a larger-numbered class must never be contained completely 267 in a smaller-numbered class. 268 269 For any two classes, it is very desirable that there be another 270 class that represents their union. */ 271 272 enum reg_class 273 { 274 NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, SP_OR_ADDRESS_REGS, 275 EXTENDED_REGS, FP_REGS, FP_ACC_REGS, CC_REGS, MDR_REGS, 276 GENERAL_REGS, SP_OR_GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES 277 }; 278 279 #define N_REG_CLASSES (int) LIM_REG_CLASSES 280 281 /* Give names of register classes as strings for dump file. */ 282 283 #define REG_CLASS_NAMES \ 284 { "NO_REGS", "DATA_REGS", "ADDRESS_REGS", "SP_REGS", "SP_OR_ADDRESS_REGS", \ 285 "EXTENDED_REGS", "FP_REGS", "FP_ACC_REGS", "CC_REGS", "MDR_REGS", \ 286 "GENERAL_REGS", "SP_OR_GENERAL_REGS", "ALL_REGS", "LIM_REGS" \ 287 } 288 289 /* Define which registers fit in which classes. 290 This is an initializer for a vector of HARD_REG_SET 291 of length N_REG_CLASSES. */ 292 293 #define REG_CLASS_CONTENTS \ 294 { { 0, 0 }, /* No regs */ \ 295 { 0x0000000f, 0 }, /* DATA_REGS */ \ 296 { 0x000001f0, 0 }, /* ADDRESS_REGS */ \ 297 { 0x00000200, 0 }, /* SP_REGS */ \ 298 { 0x000003f0, 0 }, /* SP_OR_ADDRESS_REGS */ \ 299 { 0x0003fc00, 0 }, /* EXTENDED_REGS */ \ 300 { 0xfffc0000, 0x3ffff },/* FP_REGS */ \ 301 { 0x03fc0000, 0 }, /* FP_ACC_REGS */ \ 302 { 0x00000000, 0x80000 },/* CC_REGS */ \ 303 { 0x00000000, 0x40000 },/* MDR_REGS */ \ 304 { 0x0003fdff, 0 }, /* GENERAL_REGS */ \ 305 { 0x0003ffff, 0 }, /* SP_OR_GENERAL_REGS */ \ 306 { 0xffffffff, 0xfffff } /* ALL_REGS */ \ 307 } 308 309 /* The same information, inverted: 310 Return the class number of the smallest class containing 311 reg number REGNO. This could be a conditional expression 312 or could index an array. */ 313 314 #define REGNO_REG_CLASS(REGNO) \ 315 ((REGNO) <= LAST_DATA_REGNUM ? DATA_REGS : \ 316 (REGNO) <= LAST_ADDRESS_REGNUM ? ADDRESS_REGS : \ 317 (REGNO) == STACK_POINTER_REGNUM ? SP_REGS : \ 318 (REGNO) <= LAST_EXTENDED_REGNUM ? EXTENDED_REGS : \ 319 (REGNO) <= LAST_FP_REGNUM ? FP_REGS : \ 320 (REGNO) == MDR_REG ? MDR_REGS : \ 321 (REGNO) == CC_REG ? CC_REGS : \ 322 NO_REGS) 323 324 /* The class value for index registers, and the one for base regs. */ 325 #define INDEX_REG_CLASS \ 326 (TARGET_AM33 ? GENERAL_REGS : DATA_REGS) 327 #define BASE_REG_CLASS \ 328 (TARGET_AM33 ? SP_OR_GENERAL_REGS : SP_OR_ADDRESS_REGS) 329 330 /* Macros to check register numbers against specific register classes. */ 331 332 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 333 and check its validity for a certain class. 334 We have two alternate definitions for each of them. 335 The usual definition accepts all pseudo regs; the other rejects 336 them unless they have been allocated suitable hard regs. 337 The symbol REG_OK_STRICT causes the latter definition to be used. 338 339 Most source files want to accept pseudo regs in the hope that 340 they will get allocated to the class that the insn wants them to be in. 341 Source files for reload pass need to be strict. 342 After reload, it makes no difference, since pseudo regs have 343 been eliminated by then. */ 344 345 /* These assume that REGNO is a hard or pseudo reg number. 346 They give nonzero only if REGNO is a hard reg of the suitable class 347 or a pseudo reg currently allocated to a suitable hard reg. 348 Since they use reg_renumber, they are safe only once reg_renumber 349 has been allocated, which happens in reginfo.c during register 350 allocation. */ 351 352 #ifndef REG_OK_STRICT 353 # define REG_STRICT 0 354 #else 355 # define REG_STRICT 1 356 #endif 357 358 #define REGNO_DATA_P(regno, strict) \ 359 mn10300_regno_in_class_p (regno, DATA_REGS, strict) 360 #define REGNO_ADDRESS_P(regno, strict) \ 361 mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict) 362 #define REGNO_EXTENDED_P(regno, strict) \ 363 mn10300_regno_in_class_p (regno, EXTENDED_REGS, strict) 364 #define REGNO_GENERAL_P(regno, strict) \ 365 mn10300_regno_in_class_p (regno, GENERAL_REGS, strict) 366 367 #define REGNO_STRICT_OK_FOR_BASE_P(regno, strict) \ 368 mn10300_regno_in_class_p (regno, BASE_REG_CLASS, strict) 369 #define REGNO_OK_FOR_BASE_P(regno) \ 370 (REGNO_STRICT_OK_FOR_BASE_P ((regno), REG_STRICT)) 371 #define REG_OK_FOR_BASE_P(X) \ 372 (REGNO_OK_FOR_BASE_P (REGNO (X))) 373 374 #define REGNO_STRICT_OK_FOR_BIT_BASE_P(regno, strict) \ 375 mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict) 376 #define REGNO_OK_FOR_BIT_BASE_P(regno) \ 377 (REGNO_STRICT_OK_FOR_BIT_BASE_P ((regno), REG_STRICT)) 378 #define REG_OK_FOR_BIT_BASE_P(X) \ 379 (REGNO_OK_FOR_BIT_BASE_P (REGNO (X))) 380 381 #define REGNO_STRICT_OK_FOR_INDEX_P(regno, strict) \ 382 mn10300_regno_in_class_p (regno, INDEX_REG_CLASS, strict) 383 #define REGNO_OK_FOR_INDEX_P(regno) \ 384 (REGNO_STRICT_OK_FOR_INDEX_P ((regno), REG_STRICT)) 385 #define REG_OK_FOR_INDEX_P(X) \ 386 (REGNO_OK_FOR_INDEX_P (REGNO (X))) 387 388 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 389 (!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS) 390 391 /* A class that contains registers which the compiler must always 392 access in a mode that is the same size as the mode in which it 393 loaded the register. */ 394 #define CLASS_CANNOT_CHANGE_SIZE FP_REGS 395 396 /* Return 1 if VALUE is in the range specified. */ 397 398 #define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100) 399 #define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000) 400 401 402 /* Stack layout; function entry, exit and calling. */ 403 404 /* Define this if pushing a word on the stack 405 makes the stack pointer a smaller address. */ 406 407 #define STACK_GROWS_DOWNWARD 1 408 409 /* Define this to nonzero if the nominal address of the stack frame 410 is at the high-address end of the local variables; 411 that is, each additional local variable allocated 412 goes at a more negative offset in the frame. */ 413 414 #define FRAME_GROWS_DOWNWARD 1 415 416 /* Offset within stack frame to start allocating local variables at. 417 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 418 first local allocated. Otherwise, it is the offset to the BEGINNING 419 of the first local allocated. */ 420 421 #define STARTING_FRAME_OFFSET 0 422 423 /* Offset of first parameter from the argument pointer register value. */ 424 /* Is equal to the size of the saved fp + pc, even if an fp isn't 425 saved since the value is used before we know. */ 426 427 #define FIRST_PARM_OFFSET(FNDECL) 4 428 429 /* But the CFA is at the arg pointer directly, not at the first argument. */ 430 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 431 432 #define ELIMINABLE_REGS \ 433 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 434 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 435 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} 436 437 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 438 OFFSET = mn10300_initial_offset (FROM, TO) 439 440 /* We use d0/d1 for passing parameters, so allocate 8 bytes of space 441 for a register flushback area. */ 442 #define REG_PARM_STACK_SPACE(DECL) 8 443 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 444 #define ACCUMULATE_OUTGOING_ARGS 1 445 446 /* So we can allocate space for return pointers once for the function 447 instead of around every call. */ 448 #define STACK_POINTER_OFFSET 4 449 450 /* 1 if N is a possible register number for function argument passing. 451 On the MN10300, d0 and d1 are used in this way. */ 452 453 #define FUNCTION_ARG_REGNO_P(N) ((N) <= 1) 454 455 456 /* Define a data type for recording info about an argument list 457 during the scan of that argument list. This data type should 458 hold all necessary information about the function itself 459 and about the args processed so far, enough to enable macros 460 such as FUNCTION_ARG to determine where the next arg should go. 461 462 On the MN10300, this is a single integer, which is a number of bytes 463 of arguments scanned so far. */ 464 465 #define CUMULATIVE_ARGS struct cum_arg 466 467 struct cum_arg 468 { 469 int nbytes; 470 }; 471 472 /* Initialize a variable CUM of type CUMULATIVE_ARGS 473 for a call to a function whose data type is FNTYPE. 474 For a library call, FNTYPE is 0. 475 476 On the MN10300, the offset starts at 0. */ 477 478 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 479 ((CUM).nbytes = 0) 480 481 #define FUNCTION_VALUE_REGNO_P(N) mn10300_function_value_regno_p (N) 482 483 #define DEFAULT_PCC_STRUCT_RETURN 0 484 485 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 486 the stack pointer does not matter. The value is tested only in 487 functions that have frame pointers. 488 No definition is equivalent to always zero. */ 489 490 #define EXIT_IGNORE_STACK 1 491 492 /* Output assembler code to FILE to increment profiler label # LABELNO 493 for profiling a function entry. */ 494 495 #define FUNCTION_PROFILER(FILE, LABELNO) ; 496 497 /* Length in units of the trampoline for entering a nested function. */ 498 499 #define TRAMPOLINE_SIZE 16 500 #define TRAMPOLINE_ALIGNMENT 32 501 502 /* A C expression whose value is RTL representing the value of the return 503 address for the frame COUNT steps up from the current frame. 504 505 On the mn10300, the return address is not at a constant location 506 due to the frame layout. Luckily, it is at a constant offset from 507 the argument pointer, so we define RETURN_ADDR_RTX to return a 508 MEM using arg_pointer_rtx. Reload will replace arg_pointer_rtx 509 with a reference to the stack/frame pointer + an appropriate offset. */ 510 511 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 512 ((COUNT == 0) \ 513 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ 514 : (rtx) 0) 515 516 /* The return address is saved both in the stack and in MDR. Using 517 the stack location is handiest for what unwinding needs. */ 518 #define INCOMING_RETURN_ADDR_RTX \ 519 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 520 521 /* Maximum number of registers that can appear in a valid memory address. */ 522 523 #define MAX_REGS_PER_ADDRESS 2 524 525 526 /* We have post-increments. */ 527 #define HAVE_POST_INCREMENT TARGET_AM33 528 #define HAVE_POST_MODIFY_DISP TARGET_AM33 529 530 /* ... But we don't want to use them for block moves. Small offsets are 531 just as effective, at least for inline block move sizes, and appears 532 to produce cleaner code. */ 533 #define USE_LOAD_POST_INCREMENT(M) 0 534 #define USE_STORE_POST_INCREMENT(M) 0 535 536 /* Accept either REG or SUBREG where a register is valid. */ 537 538 #define RTX_OK_FOR_BASE_P(X, strict) \ 539 ((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X), \ 540 (strict))) \ 541 || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \ 542 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (SUBREG_REG (X)), \ 543 (strict)))) 544 545 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \ 546 do { \ 547 rtx new_x = mn10300_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \ 548 if (new_x) \ 549 { \ 550 X = new_x; \ 551 goto WIN; \ 552 } \ 553 } while (0) 554 555 556 /* Zero if this needs fixing up to become PIC. */ 557 558 #define LEGITIMATE_PIC_OPERAND_P(X) \ 559 mn10300_legitimate_pic_operand_p (X) 560 561 /* Register to hold the addressing base for 562 position independent code access to data items. */ 563 #define PIC_OFFSET_TABLE_REGNUM PIC_REG 564 565 /* The name of the pseudo-symbol representing the Global Offset Table. */ 566 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" 567 568 #define SYMBOLIC_CONST_P(X) \ 569 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ 570 && ! LEGITIMATE_PIC_OPERAND_P (X)) 571 572 /* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled. */ 573 #define MN10300_GLOBAL_P(X) (! SYMBOL_REF_FLAG (X)) 574 575 #define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (OP, X, Y) 576 #define REVERSIBLE_CC_MODE(MODE) 0 577 578 /* Nonzero if access to memory by bytes or half words is no faster 579 than accessing full words. */ 580 #define SLOW_BYTE_ACCESS 1 581 582 #define NO_FUNCTION_CSE 1 583 584 /* According expr.c, a value of around 6 should minimize code size, and 585 for the MN10300 series, that's our primary concern. */ 586 #define MOVE_RATIO(speed) 6 587 588 #define TEXT_SECTION_ASM_OP "\t.section .text" 589 #define DATA_SECTION_ASM_OP "\t.section .data" 590 #define BSS_SECTION_ASM_OP "\t.section .bss" 591 592 #define ASM_COMMENT_START "#" 593 594 /* Output to assembler file text saying following lines 595 may contain character constants, extra white space, comments, etc. */ 596 597 #define ASM_APP_ON "#APP\n" 598 599 /* Output to assembler file text saying following lines 600 no longer contain unusual constructs. */ 601 602 #define ASM_APP_OFF "#NO_APP\n" 603 604 #undef USER_LABEL_PREFIX 605 #define USER_LABEL_PREFIX "_" 606 607 /* This says how to output the assembler to define a global 608 uninitialized but not common symbol. 609 Try to use asm_output_bss to implement this macro. */ 610 611 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 612 asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) 613 614 /* Globalizing directive for a label. */ 615 #define GLOBAL_ASM_OP "\t.global " 616 617 /* This is how to output a reference to a user-level label named NAME. 618 `assemble_name' uses this. */ 619 620 #undef ASM_OUTPUT_LABELREF 621 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 622 asm_fprintf (FILE, "%U%s", (*targetm.strip_name_encoding) (NAME)) 623 624 /* This is how we tell the assembler that two symbols have the same value. */ 625 626 #define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \ 627 do \ 628 { \ 629 assemble_name (FILE, NAME1); \ 630 fputs (" = ", FILE); \ 631 assemble_name (FILE, NAME2); \ 632 fputc ('\n', FILE); \ 633 } \ 634 while (0) 635 636 /* How to refer to registers in assembler output. 637 This sequence is indexed by compiler's hard-register-number (see above). */ 638 639 #define REGISTER_NAMES \ 640 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \ 641 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" \ 642 , "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" \ 643 , "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15" \ 644 , "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23" \ 645 , "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" \ 646 , "mdr", "EPSW" \ 647 } 648 649 #define ADDITIONAL_REGISTER_NAMES \ 650 { {"r8", 4}, {"r9", 5}, {"r10", 6}, {"r11", 7}, \ 651 {"r12", 0}, {"r13", 1}, {"r14", 2}, {"r15", 3}, \ 652 {"e0", 10}, {"e1", 11}, {"e2", 12}, {"e3", 13}, \ 653 {"e4", 14}, {"e5", 15}, {"e6", 16}, {"e7", 17} \ 654 , {"fd0", 18}, {"fd2", 20}, {"fd4", 22}, {"fd6", 24} \ 655 , {"fd8", 26}, {"fd10", 28}, {"fd12", 30}, {"fd14", 32} \ 656 , {"fd16", 34}, {"fd18", 36}, {"fd20", 38}, {"fd22", 40} \ 657 , {"fd24", 42}, {"fd26", 44}, {"fd28", 46}, {"fd30", 48} \ 658 , {"cc", CC_REG} \ 659 } 660 661 /* Print an instruction operand X on file FILE. 662 look in mn10300.c for details */ 663 664 #define PRINT_OPERAND(FILE, X, CODE) \ 665 mn10300_print_operand (FILE, X, CODE) 666 667 /* Print a memory operand whose address is X, on file FILE. 668 This uses a function in output-vax.c. */ 669 670 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 671 mn10300_print_operand_address (FILE, ADDR) 672 673 /* This is how to output an element of a case-vector that is absolute. */ 674 675 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 676 fprintf (FILE, "\t%s .L%d\n", ".long", VALUE) 677 678 /* This is how to output an element of a case-vector that is relative. */ 679 680 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 681 fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) 682 683 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 684 if ((LOG) != 0) \ 685 fprintf (FILE, "\t.align %d\n", (LOG)) 686 687 /* We don't have to worry about dbx compatibility for the mn10300. */ 688 #define DEFAULT_GDB_EXTENSIONS 1 689 690 /* Use dwarf2 debugging info by default. */ 691 #undef PREFERRED_DEBUGGING_TYPE 692 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 693 #define DWARF2_DEBUGGING_INFO 1 694 #define DWARF2_ASM_LINE_DEBUG_INFO 1 695 696 /* Specify the machine mode that this machine uses 697 for the index in the tablejump instruction. */ 698 #define CASE_VECTOR_MODE Pmode 699 700 /* Define if operations between registers always perform the operation 701 on the full register even if a narrower mode is specified. */ 702 #define WORD_REGISTER_OPERATIONS 1 703 704 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 705 706 /* Max number of bytes we can move from memory to memory 707 in one reasonably fast instruction. */ 708 #define MOVE_MAX 4 709 710 /* Define if shifts truncate the shift count 711 which implies one can omit a sign-extension or zero-extension 712 of a shift count. */ 713 #define SHIFT_COUNT_TRUNCATED 1 714 715 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 716 is done just by pretending it is already truncated. */ 717 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 718 719 /* Specify the machine mode that pointers have. 720 After generation of rtl, the compiler makes no further distinction 721 between pointers and any other objects of this machine mode. */ 722 #define Pmode SImode 723 724 /* A function address in a call instruction 725 is a byte address (for indexing purposes) 726 so give the MEM rtx a byte's mode. */ 727 #define FUNCTION_MODE QImode 728 729 /* The assembler op to get a word. */ 730 731 #define FILE_ASM_OP "\t.file\n" 732 733