1;; Scheduling description for z900 (cpu 2064). 2;; Copyright (C) 2003-2016 Free Software Foundation, Inc. 3;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4;; Ulrich Weigand (uweigand@de.ibm.com). 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify it under 9;; the terms of the GNU General Public License as published by the Free 10;; Software Foundation; either version 3, or (at your option) any later 11;; version. 12 13;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 15;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16;; for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22;; 23;; References: 24;; The microarchitecture of the IBM eServer z900 processor. 25;; E.M. Schwarz et al. 26;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002. 27;; 28;; z900 (cpu 2064) pipeline 29;; 30;; dec 31;; --> | <--- 32;; LA bypass | agen | 33;; | | | 34;; --- c1 | Load bypass 35;; | | 36;; c2---- 37;; | 38;; e1 39;; | 40;; wr 41 42;; This scheduler description is also used for the g5 and g6. 43 44(define_automaton "z_ipu") 45(define_cpu_unit "z_e1" "z_ipu") 46(define_cpu_unit "z_wr" "z_ipu") 47 48 49(define_insn_reservation "z_la" 1 50 (and (eq_attr "cpu" "z900,g5,g6") 51 (eq_attr "type" "la")) 52 "z_e1,z_wr") 53 54(define_insn_reservation "z_larl" 1 55 (and (eq_attr "cpu" "z900,g5,g6") 56 (eq_attr "type" "larl")) 57 "z_e1,z_wr") 58 59(define_insn_reservation "z_load" 1 60 (and (eq_attr "cpu" "z900,g5,g6") 61 (eq_attr "type" "load")) 62 "z_e1,z_wr") 63 64(define_insn_reservation "z_store" 1 65 (and (eq_attr "cpu" "z900,g5,g6") 66 (eq_attr "type" "store")) 67 "z_e1,z_wr") 68 69(define_insn_reservation "z_sem" 2 70 (and (eq_attr "cpu" "z900,g5,g6") 71 (eq_attr "type" "sem")) 72 "z_e1*2,z_wr") 73 74(define_insn_reservation "z_call" 5 75 (and (eq_attr "cpu" "z900,g5,g6") 76 (eq_attr "type" "jsr")) 77 "z_e1*5,z_wr") 78 79(define_insn_reservation "z_mul" 5 80 (and (eq_attr "cpu" "g5,g6,z900") 81 (eq_attr "type" "imulsi,imulhi")) 82 "z_e1*5,z_wr") 83 84(define_insn_reservation "z_inf" 10 85 (and (eq_attr "cpu" "g5,g6,z900") 86 (eq_attr "type" "idiv,imuldi")) 87 "z_e1*10,z_wr") 88 89;; For everything else we check the atype flag. 90 91(define_insn_reservation "z_int" 1 92 (and (eq_attr "cpu" "z900,g5,g6") 93 (and (not (eq_attr "type" "la,larl,load,store,jsr")) 94 (eq_attr "atype" "reg"))) 95 "z_e1,z_wr") 96 97(define_insn_reservation "z_agen" 1 98 (and (eq_attr "cpu" "z900,g5,g6") 99 (and (not (eq_attr "type" "la,larl,load,store,jsr")) 100 (eq_attr "atype" "agen"))) 101 "z_e1,z_wr") 102 103;; 104;; s390_agen_dep_p returns 1, if a register is set in the 105;; first insn and used in the dependent insn to form a address. 106;; 107 108;; 109;; If an instruction uses a register to address memory, it needs 110;; to be set 5 cycles in advance. 111;; 112 113(define_bypass 5 "z_int,z_agen" 114 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 115 116;; 117;; A load type instruction uses a bypass to feed the result back 118;; to the address generation pipeline stage. 119;; 120 121(define_bypass 3 "z_load" 122 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 123 124;; 125;; A load address type instruction uses a bypass to feed the 126;; result back to the address generation pipeline stage. 127;; 128 129(define_bypass 2 "z_larl,z_la" 130 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 131 132 133 134 135 136