1 #objdump: -Dr -Mppc 2 #name: PowerPC test 2 3 4 .* 5 6 Disassembly of section \.text: 7 8 0+0000000 <foo>: 9 0: (60 00 00 00|00 00 00 60) nop 10 4: (60 00 00 00|00 00 00 60) nop 11 8: (60 00 00 00|00 00 00 60) nop 12 c: (48 00 00 04|04 00 00 48) b 10 <foo\+0x10> 13 10: (48 00 00 08|08 00 00 48) b 18 <foo\+0x18> 14 14: (48 00 00 00|00 00 00 48) b .* 15 14: R_PPC_REL24 x 16 18: (48 00 00 0.|0. 00 00 48) b .* 17 18: R_PPC_REL24 \.data\+0x4 18 1c: (48 00 00 00|00 00 00 48) b .* 19 1c: R_PPC_REL24 z 20 20: (48 00 00 ..|.. 00 00 48) b .* 21 20: R_PPC_REL24 z\+0x14 22 24: (48 00 00 04|04 00 00 48) b 28 <foo\+0x28> 23 28: (48 00 00 00|00 00 00 48) b .* 24 28: R_PPC_REL24 a 25 2c: (48 00 00 50|50 00 00 48) b 7c <apfour> 26 30: (48 00 00 0.|0. 00 00 48) b .* 27 30: R_PPC_REL24 a\+0x4 28 34: (48 00 00 4c|4c 00 00 48) b 80 <apfour\+0x4> 29 38: (48 00 00 00|00 00 00 48) b .* 30 38: R_PPC_LOCAL24PC a 31 3c: (48 00 00 40|40 00 00 48) b 7c <apfour> 32 \.\.\. 33 40: R_PPC_ADDR32 \.text\+0x40 34 44: R_PPC_ADDR32 \.text\+0x4c 35 48: R_PPC_REL32 x 36 4c: R_PPC_REL32 x\+0x4 37 50: R_PPC_REL32 z 38 54: R_PPC_REL32 \.data\+0x4 39 58: R_PPC_ADDR32 x 40 5c: R_PPC_ADDR32 \.data\+0x4 41 60: R_PPC_ADDR32 z 42 64: R_PPC_ADDR32 x-0x4 43 68: R_PPC_ADDR32 \.data 44 6c: R_PPC_ADDR32 z-0x4 45 70: (00 00 00 08|08 00 00 00) \.long 0x8 46 74: (00 00 00 08|08 00 00 00) \.long 0x8 47 48 0+0000078 <a>: 49 78: (00 00 00 00|00 00 00 00) \.long 0x0 50 78: R_PPC_ADDR32 a 51 52 0+000007c <apfour>: 53 \.\.\. 54 7c: R_PPC_ADDR32 \.text\+0x7c 55 80: R_PPC_ADDR32 \.text\+0x7c 56 84: (ff ff ff fc|fc ff ff ff) fnmsub f31,f31,f31,f31 57 \.\.\. 58 88: R_PPC_ADDR32 \.text\+0x7e 59 90: (60 00 00 00|00 00 00 60) nop 60 94: (40 a5 ff fc|fc ff a5 40) ble- cr1,90 <apfour\+0x14> 61 98: (41 a9 ff f8|f8 ff a9 41) bgt- cr2,90 <apfour\+0x14> 62 9c: (40 8d ff f4|f4 ff 8d 40) ble\+ cr3,90 <apfour\+0x14> 63 a0: (41 91 ff f0|f0 ff 91 41) bgt\+ cr4,90 <apfour\+0x14> 64 a4: (40 95 00 10|10 00 95 40) ble- cr5,b4 <nop> 65 a8: (41 99 00 0c|0c 00 99 41) bgt- cr6,b4 <nop> 66 ac: (40 bd 00 08|08 00 bd 40) ble\+ cr7,b4 <nop> 67 b0: (41 a1 00 04|04 00 a1 41) bgt\+ b4 <nop> 68 Disassembly of section \.data: 69 70 0+0000000 <x>: 71 0: 00 00 00 00 \.long 0x0 72 73 0+0000004 <y>: 74 4: 00 00 00 00 \.long 0x0 75