1 /****************************************************************************
2  ****************************************************************************
3  ***
4  ***   This header was automatically generated from a Linux kernel header
5  ***   of the same name, to make information necessary for userspace to
6  ***   call into the kernel available to libc.  It contains only constants,
7  ***   structures, and macros generated from the original header, and thus,
8  ***   contains no copyrightable information.
9  ***
10  ****************************************************************************
11  ****************************************************************************/
12 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
13 #define __ASM_ARCH_OMAP_HARDWARE_H
14 
15 #include <asm/sizes.h>
16 #ifndef __ASSEMBLER__
17 #include <asm/types.h>
18 #include <asm/arch/cpu.h>
19 #endif
20 #include <asm/arch/io.h>
21 #include <asm/arch/serial.h>
22 
23 #define OMAP_MPU_TIMER1_BASE (0xfffec500)
24 #define OMAP_MPU_TIMER2_BASE (0xfffec600)
25 #define OMAP_MPU_TIMER3_BASE (0xfffec700)
26 #define MPU_TIMER_FREE (1 << 6)
27 #define MPU_TIMER_CLOCK_ENABLE (1 << 5)
28 #define MPU_TIMER_AR (1 << 1)
29 #define MPU_TIMER_ST (1 << 0)
30 
31 #define CLKGEN_REG_BASE (0xfffece00)
32 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
33 #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
34 #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
35 #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
36 #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
37 #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
38 #define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
39 #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
40 
41 #define CK_RATEF 1
42 #define CK_IDLEF 2
43 #define CK_ENABLEF 4
44 #define CK_SELECTF 8
45 #define SETARM_IDLE_SHIFT
46 
47 #define DPLL_CTL (0xfffecf00)
48 
49 #define DSP_CONFIG_REG_BASE (0xe1008000)
50 #define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
51 #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
52 #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
53 #define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
54 
55 #define ULPD_REG_BASE (0xfffe0800)
56 #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
57 #define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
58 #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
59 #define DIS_USB_PVCI_CLK (1 << 5)
60 #define USB_MCLK_EN (1 << 4)
61 #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
62 #define SOFT_UDC_REQ (1 << 4)
63 #define SOFT_USB_CLK_REQ (1 << 3)
64 #define SOFT_DPLL_REQ (1 << 0)
65 #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
66 #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
67 #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
68 #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
69 #define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
70 #define DIS_MMC2_DPLL_REQ (1 << 11)
71 #define DIS_MMC1_DPLL_REQ (1 << 10)
72 #define DIS_UART3_DPLL_REQ (1 << 9)
73 #define DIS_UART2_DPLL_REQ (1 << 8)
74 #define DIS_UART1_DPLL_REQ (1 << 7)
75 #define DIS_USB_HOST_DPLL_REQ (1 << 6)
76 #define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
77 #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
78 
79 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
80 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
81 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
82 #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
83 #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
84 
85 #define MOD_CONF_CTRL_0 0xfffe1080
86 #define MOD_CONF_CTRL_1 0xfffe1110
87 
88 #define FUNC_MUX_CTRL_0 0xfffe1000
89 #define FUNC_MUX_CTRL_1 0xfffe1004
90 #define FUNC_MUX_CTRL_2 0xfffe1008
91 #define COMP_MODE_CTRL_0 0xfffe100c
92 #define FUNC_MUX_CTRL_3 0xfffe1010
93 #define FUNC_MUX_CTRL_4 0xfffe1014
94 #define FUNC_MUX_CTRL_5 0xfffe1018
95 #define FUNC_MUX_CTRL_6 0xfffe101C
96 #define FUNC_MUX_CTRL_7 0xfffe1020
97 #define FUNC_MUX_CTRL_8 0xfffe1024
98 #define FUNC_MUX_CTRL_9 0xfffe1028
99 #define FUNC_MUX_CTRL_A 0xfffe102C
100 #define FUNC_MUX_CTRL_B 0xfffe1030
101 #define FUNC_MUX_CTRL_C 0xfffe1034
102 #define FUNC_MUX_CTRL_D 0xfffe1038
103 #define PULL_DWN_CTRL_0 0xfffe1040
104 #define PULL_DWN_CTRL_1 0xfffe1044
105 #define PULL_DWN_CTRL_2 0xfffe1048
106 #define PULL_DWN_CTRL_3 0xfffe104c
107 #define PULL_DWN_CTRL_4 0xfffe10ac
108 
109 #define FUNC_MUX_CTRL_E 0xfffe1090
110 #define FUNC_MUX_CTRL_F 0xfffe1094
111 #define FUNC_MUX_CTRL_10 0xfffe1098
112 #define FUNC_MUX_CTRL_11 0xfffe109c
113 #define FUNC_MUX_CTRL_12 0xfffe10a0
114 #define PU_PD_SEL_0 0xfffe10b4
115 #define PU_PD_SEL_1 0xfffe10b8
116 #define PU_PD_SEL_2 0xfffe10bc
117 #define PU_PD_SEL_3 0xfffe10c0
118 #define PU_PD_SEL_4 0xfffe10c4
119 
120 #define OMAP_TIMER32K_BASE 0xFFFBC400
121 
122 #define TIPB_PUBLIC_CNTL_BASE 0xfffed300
123 #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
124 #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
125 #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
126 
127 #define MPUI_BASE (0xfffec900)
128 #define MPUI_CTRL (MPUI_BASE + 0x0)
129 #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
130 #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
131 #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
132 #define MPUI_STATUS_REG (MPUI_BASE + 0x10)
133 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
134 #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
135 #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
136 
137 #define OMAP_LPG1_BASE 0xfffbd000
138 #define OMAP_LPG2_BASE 0xfffbd800
139 #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
140 #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
141 #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
142 #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
143 
144 #define OMAP_PWL_BASE 0xfffb5800
145 #define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
146 #define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
147 
148 #include "omap730.h"
149 #include "omap1510.h"
150 #include "omap24xx.h"
151 #include "omap16xx.h"
152 
153 #ifndef __ASSEMBLER__
154 
155 #endif
156 
157 #endif
158