1// Inferno utils/5c/list.c 2// https://bitbucket.org/inferno-os/inferno-os/src/master/utils/5c/list.c 3// 4// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6// Portions Copyright © 1997-1999 Vita Nuova Limited 7// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8// Portions Copyright © 2004,2006 Bruce Ellis 9// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11// Portions Copyright © 2009 The Go Authors. All rights reserved. 12// 13// Permission is hereby granted, free of charge, to any person obtaining a copy 14// of this software and associated documentation files (the "Software"), to deal 15// in the Software without restriction, including without limitation the rights 16// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17// copies of the Software, and to permit persons to whom the Software is 18// furnished to do so, subject to the following conditions: 19// 20// The above copyright notice and this permission notice shall be included in 21// all copies or substantial portions of the Software. 22// 23// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29// THE SOFTWARE. 30 31package arm 32 33import ( 34 "cmd/internal/obj" 35 "fmt" 36) 37 38func init() { 39 obj.RegisterRegister(obj.RBaseARM, MAXREG, rconv) 40 obj.RegisterOpcode(obj.ABaseARM, Anames) 41 obj.RegisterRegisterList(obj.RegListARMLo, obj.RegListARMHi, rlconv) 42 obj.RegisterOpSuffix("arm", obj.CConvARM) 43} 44 45func rconv(r int) string { 46 if r == 0 { 47 return "NONE" 48 } 49 if r == REGG { 50 // Special case. 51 return "g" 52 } 53 if REG_R0 <= r && r <= REG_R15 { 54 return fmt.Sprintf("R%d", r-REG_R0) 55 } 56 if REG_F0 <= r && r <= REG_F15 { 57 return fmt.Sprintf("F%d", r-REG_F0) 58 } 59 60 switch r { 61 case REG_FPSR: 62 return "FPSR" 63 64 case REG_FPCR: 65 return "FPCR" 66 67 case REG_CPSR: 68 return "CPSR" 69 70 case REG_SPSR: 71 return "SPSR" 72 73 case REG_MB_SY: 74 return "MB_SY" 75 case REG_MB_ST: 76 return "MB_ST" 77 case REG_MB_ISH: 78 return "MB_ISH" 79 case REG_MB_ISHST: 80 return "MB_ISHST" 81 case REG_MB_NSH: 82 return "MB_NSH" 83 case REG_MB_NSHST: 84 return "MB_NSHST" 85 case REG_MB_OSH: 86 return "MB_OSH" 87 case REG_MB_OSHST: 88 return "MB_OSHST" 89 } 90 91 return fmt.Sprintf("Rgok(%d)", r-obj.RBaseARM) 92} 93 94func DRconv(a int) string { 95 s := "C_??" 96 if a >= C_NONE && a <= C_NCLASS { 97 s = cnames5[a] 98 } 99 var fp string 100 fp += s 101 return fp 102} 103 104func rlconv(list int64) string { 105 str := "" 106 for i := 0; i < 16; i++ { 107 if list&(1<<uint(i)) != 0 { 108 if str == "" { 109 str += "[" 110 } else { 111 str += "," 112 } 113 // This is ARM-specific; R10 is g. 114 if i == REGG-REG_R0 { 115 str += "g" 116 } else { 117 str += fmt.Sprintf("R%d", i) 118 } 119 } 120 } 121 122 str += "]" 123 return str 124} 125