1// Code generated from gen/*Ops.go; DO NOT EDIT.
2
3package ssa
4
5import (
6	"cmd/internal/obj"
7	"cmd/internal/obj/arm"
8	"cmd/internal/obj/arm64"
9	"cmd/internal/obj/mips"
10	"cmd/internal/obj/ppc64"
11	"cmd/internal/obj/riscv"
12	"cmd/internal/obj/s390x"
13	"cmd/internal/obj/wasm"
14	"cmd/internal/obj/x86"
15)
16
17const (
18	BlockInvalid BlockKind = iota
19
20	Block386EQ
21	Block386NE
22	Block386LT
23	Block386LE
24	Block386GT
25	Block386GE
26	Block386OS
27	Block386OC
28	Block386ULT
29	Block386ULE
30	Block386UGT
31	Block386UGE
32	Block386EQF
33	Block386NEF
34	Block386ORD
35	Block386NAN
36
37	BlockAMD64EQ
38	BlockAMD64NE
39	BlockAMD64LT
40	BlockAMD64LE
41	BlockAMD64GT
42	BlockAMD64GE
43	BlockAMD64OS
44	BlockAMD64OC
45	BlockAMD64ULT
46	BlockAMD64ULE
47	BlockAMD64UGT
48	BlockAMD64UGE
49	BlockAMD64EQF
50	BlockAMD64NEF
51	BlockAMD64ORD
52	BlockAMD64NAN
53
54	BlockARMEQ
55	BlockARMNE
56	BlockARMLT
57	BlockARMLE
58	BlockARMGT
59	BlockARMGE
60	BlockARMULT
61	BlockARMULE
62	BlockARMUGT
63	BlockARMUGE
64
65	BlockARM64EQ
66	BlockARM64NE
67	BlockARM64LT
68	BlockARM64LE
69	BlockARM64GT
70	BlockARM64GE
71	BlockARM64ULT
72	BlockARM64ULE
73	BlockARM64UGT
74	BlockARM64UGE
75	BlockARM64Z
76	BlockARM64NZ
77	BlockARM64ZW
78	BlockARM64NZW
79	BlockARM64TBZ
80	BlockARM64TBNZ
81	BlockARM64FLT
82	BlockARM64FLE
83	BlockARM64FGT
84	BlockARM64FGE
85
86	BlockMIPSEQ
87	BlockMIPSNE
88	BlockMIPSLTZ
89	BlockMIPSLEZ
90	BlockMIPSGTZ
91	BlockMIPSGEZ
92	BlockMIPSFPT
93	BlockMIPSFPF
94
95	BlockMIPS64EQ
96	BlockMIPS64NE
97	BlockMIPS64LTZ
98	BlockMIPS64LEZ
99	BlockMIPS64GTZ
100	BlockMIPS64GEZ
101	BlockMIPS64FPT
102	BlockMIPS64FPF
103
104	BlockPPC64EQ
105	BlockPPC64NE
106	BlockPPC64LT
107	BlockPPC64LE
108	BlockPPC64GT
109	BlockPPC64GE
110	BlockPPC64FLT
111	BlockPPC64FLE
112	BlockPPC64FGT
113	BlockPPC64FGE
114
115	BlockRISCV64BNE
116
117	BlockS390XBRC
118	BlockS390XCRJ
119	BlockS390XCGRJ
120	BlockS390XCLRJ
121	BlockS390XCLGRJ
122	BlockS390XCIJ
123	BlockS390XCGIJ
124	BlockS390XCLIJ
125	BlockS390XCLGIJ
126
127	BlockPlain
128	BlockIf
129	BlockDefer
130	BlockRet
131	BlockRetJmp
132	BlockExit
133	BlockFirst
134)
135
136var blockString = [...]string{
137	BlockInvalid: "BlockInvalid",
138
139	Block386EQ:  "EQ",
140	Block386NE:  "NE",
141	Block386LT:  "LT",
142	Block386LE:  "LE",
143	Block386GT:  "GT",
144	Block386GE:  "GE",
145	Block386OS:  "OS",
146	Block386OC:  "OC",
147	Block386ULT: "ULT",
148	Block386ULE: "ULE",
149	Block386UGT: "UGT",
150	Block386UGE: "UGE",
151	Block386EQF: "EQF",
152	Block386NEF: "NEF",
153	Block386ORD: "ORD",
154	Block386NAN: "NAN",
155
156	BlockAMD64EQ:  "EQ",
157	BlockAMD64NE:  "NE",
158	BlockAMD64LT:  "LT",
159	BlockAMD64LE:  "LE",
160	BlockAMD64GT:  "GT",
161	BlockAMD64GE:  "GE",
162	BlockAMD64OS:  "OS",
163	BlockAMD64OC:  "OC",
164	BlockAMD64ULT: "ULT",
165	BlockAMD64ULE: "ULE",
166	BlockAMD64UGT: "UGT",
167	BlockAMD64UGE: "UGE",
168	BlockAMD64EQF: "EQF",
169	BlockAMD64NEF: "NEF",
170	BlockAMD64ORD: "ORD",
171	BlockAMD64NAN: "NAN",
172
173	BlockARMEQ:  "EQ",
174	BlockARMNE:  "NE",
175	BlockARMLT:  "LT",
176	BlockARMLE:  "LE",
177	BlockARMGT:  "GT",
178	BlockARMGE:  "GE",
179	BlockARMULT: "ULT",
180	BlockARMULE: "ULE",
181	BlockARMUGT: "UGT",
182	BlockARMUGE: "UGE",
183
184	BlockARM64EQ:   "EQ",
185	BlockARM64NE:   "NE",
186	BlockARM64LT:   "LT",
187	BlockARM64LE:   "LE",
188	BlockARM64GT:   "GT",
189	BlockARM64GE:   "GE",
190	BlockARM64ULT:  "ULT",
191	BlockARM64ULE:  "ULE",
192	BlockARM64UGT:  "UGT",
193	BlockARM64UGE:  "UGE",
194	BlockARM64Z:    "Z",
195	BlockARM64NZ:   "NZ",
196	BlockARM64ZW:   "ZW",
197	BlockARM64NZW:  "NZW",
198	BlockARM64TBZ:  "TBZ",
199	BlockARM64TBNZ: "TBNZ",
200	BlockARM64FLT:  "FLT",
201	BlockARM64FLE:  "FLE",
202	BlockARM64FGT:  "FGT",
203	BlockARM64FGE:  "FGE",
204
205	BlockMIPSEQ:  "EQ",
206	BlockMIPSNE:  "NE",
207	BlockMIPSLTZ: "LTZ",
208	BlockMIPSLEZ: "LEZ",
209	BlockMIPSGTZ: "GTZ",
210	BlockMIPSGEZ: "GEZ",
211	BlockMIPSFPT: "FPT",
212	BlockMIPSFPF: "FPF",
213
214	BlockMIPS64EQ:  "EQ",
215	BlockMIPS64NE:  "NE",
216	BlockMIPS64LTZ: "LTZ",
217	BlockMIPS64LEZ: "LEZ",
218	BlockMIPS64GTZ: "GTZ",
219	BlockMIPS64GEZ: "GEZ",
220	BlockMIPS64FPT: "FPT",
221	BlockMIPS64FPF: "FPF",
222
223	BlockPPC64EQ:  "EQ",
224	BlockPPC64NE:  "NE",
225	BlockPPC64LT:  "LT",
226	BlockPPC64LE:  "LE",
227	BlockPPC64GT:  "GT",
228	BlockPPC64GE:  "GE",
229	BlockPPC64FLT: "FLT",
230	BlockPPC64FLE: "FLE",
231	BlockPPC64FGT: "FGT",
232	BlockPPC64FGE: "FGE",
233
234	BlockRISCV64BNE: "BNE",
235
236	BlockS390XBRC:   "BRC",
237	BlockS390XCRJ:   "CRJ",
238	BlockS390XCGRJ:  "CGRJ",
239	BlockS390XCLRJ:  "CLRJ",
240	BlockS390XCLGRJ: "CLGRJ",
241	BlockS390XCIJ:   "CIJ",
242	BlockS390XCGIJ:  "CGIJ",
243	BlockS390XCLIJ:  "CLIJ",
244	BlockS390XCLGIJ: "CLGIJ",
245
246	BlockPlain:  "Plain",
247	BlockIf:     "If",
248	BlockDefer:  "Defer",
249	BlockRet:    "Ret",
250	BlockRetJmp: "RetJmp",
251	BlockExit:   "Exit",
252	BlockFirst:  "First",
253}
254
255func (k BlockKind) String() string { return blockString[k] }
256func (k BlockKind) AuxIntType() string {
257	switch k {
258	case BlockS390XCIJ:
259		return "Int8"
260	case BlockS390XCGIJ:
261		return "Int8"
262	case BlockS390XCLIJ:
263		return "UInt8"
264	case BlockS390XCLGIJ:
265		return "UInt8"
266	}
267	return ""
268}
269
270const (
271	OpInvalid Op = iota
272
273	Op386ADDSS
274	Op386ADDSD
275	Op386SUBSS
276	Op386SUBSD
277	Op386MULSS
278	Op386MULSD
279	Op386DIVSS
280	Op386DIVSD
281	Op386MOVSSload
282	Op386MOVSDload
283	Op386MOVSSconst
284	Op386MOVSDconst
285	Op386MOVSSloadidx1
286	Op386MOVSSloadidx4
287	Op386MOVSDloadidx1
288	Op386MOVSDloadidx8
289	Op386MOVSSstore
290	Op386MOVSDstore
291	Op386MOVSSstoreidx1
292	Op386MOVSSstoreidx4
293	Op386MOVSDstoreidx1
294	Op386MOVSDstoreidx8
295	Op386ADDSSload
296	Op386ADDSDload
297	Op386SUBSSload
298	Op386SUBSDload
299	Op386MULSSload
300	Op386MULSDload
301	Op386DIVSSload
302	Op386DIVSDload
303	Op386ADDL
304	Op386ADDLconst
305	Op386ADDLcarry
306	Op386ADDLconstcarry
307	Op386ADCL
308	Op386ADCLconst
309	Op386SUBL
310	Op386SUBLconst
311	Op386SUBLcarry
312	Op386SUBLconstcarry
313	Op386SBBL
314	Op386SBBLconst
315	Op386MULL
316	Op386MULLconst
317	Op386MULLU
318	Op386HMULL
319	Op386HMULLU
320	Op386MULLQU
321	Op386AVGLU
322	Op386DIVL
323	Op386DIVW
324	Op386DIVLU
325	Op386DIVWU
326	Op386MODL
327	Op386MODW
328	Op386MODLU
329	Op386MODWU
330	Op386ANDL
331	Op386ANDLconst
332	Op386ORL
333	Op386ORLconst
334	Op386XORL
335	Op386XORLconst
336	Op386CMPL
337	Op386CMPW
338	Op386CMPB
339	Op386CMPLconst
340	Op386CMPWconst
341	Op386CMPBconst
342	Op386CMPLload
343	Op386CMPWload
344	Op386CMPBload
345	Op386CMPLconstload
346	Op386CMPWconstload
347	Op386CMPBconstload
348	Op386UCOMISS
349	Op386UCOMISD
350	Op386TESTL
351	Op386TESTW
352	Op386TESTB
353	Op386TESTLconst
354	Op386TESTWconst
355	Op386TESTBconst
356	Op386SHLL
357	Op386SHLLconst
358	Op386SHRL
359	Op386SHRW
360	Op386SHRB
361	Op386SHRLconst
362	Op386SHRWconst
363	Op386SHRBconst
364	Op386SARL
365	Op386SARW
366	Op386SARB
367	Op386SARLconst
368	Op386SARWconst
369	Op386SARBconst
370	Op386ROLLconst
371	Op386ROLWconst
372	Op386ROLBconst
373	Op386ADDLload
374	Op386SUBLload
375	Op386MULLload
376	Op386ANDLload
377	Op386ORLload
378	Op386XORLload
379	Op386ADDLloadidx4
380	Op386SUBLloadidx4
381	Op386MULLloadidx4
382	Op386ANDLloadidx4
383	Op386ORLloadidx4
384	Op386XORLloadidx4
385	Op386NEGL
386	Op386NOTL
387	Op386BSFL
388	Op386BSFW
389	Op386BSRL
390	Op386BSRW
391	Op386BSWAPL
392	Op386SQRTSD
393	Op386SBBLcarrymask
394	Op386SETEQ
395	Op386SETNE
396	Op386SETL
397	Op386SETLE
398	Op386SETG
399	Op386SETGE
400	Op386SETB
401	Op386SETBE
402	Op386SETA
403	Op386SETAE
404	Op386SETO
405	Op386SETEQF
406	Op386SETNEF
407	Op386SETORD
408	Op386SETNAN
409	Op386SETGF
410	Op386SETGEF
411	Op386MOVBLSX
412	Op386MOVBLZX
413	Op386MOVWLSX
414	Op386MOVWLZX
415	Op386MOVLconst
416	Op386CVTTSD2SL
417	Op386CVTTSS2SL
418	Op386CVTSL2SS
419	Op386CVTSL2SD
420	Op386CVTSD2SS
421	Op386CVTSS2SD
422	Op386PXOR
423	Op386LEAL
424	Op386LEAL1
425	Op386LEAL2
426	Op386LEAL4
427	Op386LEAL8
428	Op386MOVBload
429	Op386MOVBLSXload
430	Op386MOVWload
431	Op386MOVWLSXload
432	Op386MOVLload
433	Op386MOVBstore
434	Op386MOVWstore
435	Op386MOVLstore
436	Op386ADDLmodify
437	Op386SUBLmodify
438	Op386ANDLmodify
439	Op386ORLmodify
440	Op386XORLmodify
441	Op386ADDLmodifyidx4
442	Op386SUBLmodifyidx4
443	Op386ANDLmodifyidx4
444	Op386ORLmodifyidx4
445	Op386XORLmodifyidx4
446	Op386ADDLconstmodify
447	Op386ANDLconstmodify
448	Op386ORLconstmodify
449	Op386XORLconstmodify
450	Op386ADDLconstmodifyidx4
451	Op386ANDLconstmodifyidx4
452	Op386ORLconstmodifyidx4
453	Op386XORLconstmodifyidx4
454	Op386MOVBloadidx1
455	Op386MOVWloadidx1
456	Op386MOVWloadidx2
457	Op386MOVLloadidx1
458	Op386MOVLloadidx4
459	Op386MOVBstoreidx1
460	Op386MOVWstoreidx1
461	Op386MOVWstoreidx2
462	Op386MOVLstoreidx1
463	Op386MOVLstoreidx4
464	Op386MOVBstoreconst
465	Op386MOVWstoreconst
466	Op386MOVLstoreconst
467	Op386MOVBstoreconstidx1
468	Op386MOVWstoreconstidx1
469	Op386MOVWstoreconstidx2
470	Op386MOVLstoreconstidx1
471	Op386MOVLstoreconstidx4
472	Op386DUFFZERO
473	Op386REPSTOSL
474	Op386CALLstatic
475	Op386CALLclosure
476	Op386CALLinter
477	Op386DUFFCOPY
478	Op386REPMOVSL
479	Op386InvertFlags
480	Op386LoweredGetG
481	Op386LoweredGetClosurePtr
482	Op386LoweredGetCallerPC
483	Op386LoweredGetCallerSP
484	Op386LoweredNilCheck
485	Op386LoweredWB
486	Op386LoweredPanicBoundsA
487	Op386LoweredPanicBoundsB
488	Op386LoweredPanicBoundsC
489	Op386LoweredPanicExtendA
490	Op386LoweredPanicExtendB
491	Op386LoweredPanicExtendC
492	Op386FlagEQ
493	Op386FlagLT_ULT
494	Op386FlagLT_UGT
495	Op386FlagGT_UGT
496	Op386FlagGT_ULT
497	Op386FCHS
498	Op386MOVSSconst1
499	Op386MOVSDconst1
500	Op386MOVSSconst2
501	Op386MOVSDconst2
502
503	OpAMD64ADDSS
504	OpAMD64ADDSD
505	OpAMD64SUBSS
506	OpAMD64SUBSD
507	OpAMD64MULSS
508	OpAMD64MULSD
509	OpAMD64DIVSS
510	OpAMD64DIVSD
511	OpAMD64MOVSSload
512	OpAMD64MOVSDload
513	OpAMD64MOVSSconst
514	OpAMD64MOVSDconst
515	OpAMD64MOVSSloadidx1
516	OpAMD64MOVSSloadidx4
517	OpAMD64MOVSDloadidx1
518	OpAMD64MOVSDloadidx8
519	OpAMD64MOVSSstore
520	OpAMD64MOVSDstore
521	OpAMD64MOVSSstoreidx1
522	OpAMD64MOVSSstoreidx4
523	OpAMD64MOVSDstoreidx1
524	OpAMD64MOVSDstoreidx8
525	OpAMD64ADDSSload
526	OpAMD64ADDSDload
527	OpAMD64SUBSSload
528	OpAMD64SUBSDload
529	OpAMD64MULSSload
530	OpAMD64MULSDload
531	OpAMD64DIVSSload
532	OpAMD64DIVSDload
533	OpAMD64ADDQ
534	OpAMD64ADDL
535	OpAMD64ADDQconst
536	OpAMD64ADDLconst
537	OpAMD64ADDQconstmodify
538	OpAMD64ADDLconstmodify
539	OpAMD64SUBQ
540	OpAMD64SUBL
541	OpAMD64SUBQconst
542	OpAMD64SUBLconst
543	OpAMD64MULQ
544	OpAMD64MULL
545	OpAMD64MULQconst
546	OpAMD64MULLconst
547	OpAMD64MULLU
548	OpAMD64MULQU
549	OpAMD64HMULQ
550	OpAMD64HMULL
551	OpAMD64HMULQU
552	OpAMD64HMULLU
553	OpAMD64AVGQU
554	OpAMD64DIVQ
555	OpAMD64DIVL
556	OpAMD64DIVW
557	OpAMD64DIVQU
558	OpAMD64DIVLU
559	OpAMD64DIVWU
560	OpAMD64NEGLflags
561	OpAMD64ADDQcarry
562	OpAMD64ADCQ
563	OpAMD64ADDQconstcarry
564	OpAMD64ADCQconst
565	OpAMD64SUBQborrow
566	OpAMD64SBBQ
567	OpAMD64SUBQconstborrow
568	OpAMD64SBBQconst
569	OpAMD64MULQU2
570	OpAMD64DIVQU2
571	OpAMD64ANDQ
572	OpAMD64ANDL
573	OpAMD64ANDQconst
574	OpAMD64ANDLconst
575	OpAMD64ANDQconstmodify
576	OpAMD64ANDLconstmodify
577	OpAMD64ORQ
578	OpAMD64ORL
579	OpAMD64ORQconst
580	OpAMD64ORLconst
581	OpAMD64ORQconstmodify
582	OpAMD64ORLconstmodify
583	OpAMD64XORQ
584	OpAMD64XORL
585	OpAMD64XORQconst
586	OpAMD64XORLconst
587	OpAMD64XORQconstmodify
588	OpAMD64XORLconstmodify
589	OpAMD64CMPQ
590	OpAMD64CMPL
591	OpAMD64CMPW
592	OpAMD64CMPB
593	OpAMD64CMPQconst
594	OpAMD64CMPLconst
595	OpAMD64CMPWconst
596	OpAMD64CMPBconst
597	OpAMD64CMPQload
598	OpAMD64CMPLload
599	OpAMD64CMPWload
600	OpAMD64CMPBload
601	OpAMD64CMPQconstload
602	OpAMD64CMPLconstload
603	OpAMD64CMPWconstload
604	OpAMD64CMPBconstload
605	OpAMD64UCOMISS
606	OpAMD64UCOMISD
607	OpAMD64BTL
608	OpAMD64BTQ
609	OpAMD64BTCL
610	OpAMD64BTCQ
611	OpAMD64BTRL
612	OpAMD64BTRQ
613	OpAMD64BTSL
614	OpAMD64BTSQ
615	OpAMD64BTLconst
616	OpAMD64BTQconst
617	OpAMD64BTCLconst
618	OpAMD64BTCQconst
619	OpAMD64BTRLconst
620	OpAMD64BTRQconst
621	OpAMD64BTSLconst
622	OpAMD64BTSQconst
623	OpAMD64BTCQmodify
624	OpAMD64BTCLmodify
625	OpAMD64BTSQmodify
626	OpAMD64BTSLmodify
627	OpAMD64BTRQmodify
628	OpAMD64BTRLmodify
629	OpAMD64BTCQconstmodify
630	OpAMD64BTCLconstmodify
631	OpAMD64BTSQconstmodify
632	OpAMD64BTSLconstmodify
633	OpAMD64BTRQconstmodify
634	OpAMD64BTRLconstmodify
635	OpAMD64TESTQ
636	OpAMD64TESTL
637	OpAMD64TESTW
638	OpAMD64TESTB
639	OpAMD64TESTQconst
640	OpAMD64TESTLconst
641	OpAMD64TESTWconst
642	OpAMD64TESTBconst
643	OpAMD64SHLQ
644	OpAMD64SHLL
645	OpAMD64SHLQconst
646	OpAMD64SHLLconst
647	OpAMD64SHRQ
648	OpAMD64SHRL
649	OpAMD64SHRW
650	OpAMD64SHRB
651	OpAMD64SHRQconst
652	OpAMD64SHRLconst
653	OpAMD64SHRWconst
654	OpAMD64SHRBconst
655	OpAMD64SARQ
656	OpAMD64SARL
657	OpAMD64SARW
658	OpAMD64SARB
659	OpAMD64SARQconst
660	OpAMD64SARLconst
661	OpAMD64SARWconst
662	OpAMD64SARBconst
663	OpAMD64ROLQ
664	OpAMD64ROLL
665	OpAMD64ROLW
666	OpAMD64ROLB
667	OpAMD64RORQ
668	OpAMD64RORL
669	OpAMD64RORW
670	OpAMD64RORB
671	OpAMD64ROLQconst
672	OpAMD64ROLLconst
673	OpAMD64ROLWconst
674	OpAMD64ROLBconst
675	OpAMD64ADDLload
676	OpAMD64ADDQload
677	OpAMD64SUBQload
678	OpAMD64SUBLload
679	OpAMD64ANDLload
680	OpAMD64ANDQload
681	OpAMD64ORQload
682	OpAMD64ORLload
683	OpAMD64XORQload
684	OpAMD64XORLload
685	OpAMD64ADDQmodify
686	OpAMD64SUBQmodify
687	OpAMD64ANDQmodify
688	OpAMD64ORQmodify
689	OpAMD64XORQmodify
690	OpAMD64ADDLmodify
691	OpAMD64SUBLmodify
692	OpAMD64ANDLmodify
693	OpAMD64ORLmodify
694	OpAMD64XORLmodify
695	OpAMD64NEGQ
696	OpAMD64NEGL
697	OpAMD64NOTQ
698	OpAMD64NOTL
699	OpAMD64BSFQ
700	OpAMD64BSFL
701	OpAMD64BSRQ
702	OpAMD64BSRL
703	OpAMD64CMOVQEQ
704	OpAMD64CMOVQNE
705	OpAMD64CMOVQLT
706	OpAMD64CMOVQGT
707	OpAMD64CMOVQLE
708	OpAMD64CMOVQGE
709	OpAMD64CMOVQLS
710	OpAMD64CMOVQHI
711	OpAMD64CMOVQCC
712	OpAMD64CMOVQCS
713	OpAMD64CMOVLEQ
714	OpAMD64CMOVLNE
715	OpAMD64CMOVLLT
716	OpAMD64CMOVLGT
717	OpAMD64CMOVLLE
718	OpAMD64CMOVLGE
719	OpAMD64CMOVLLS
720	OpAMD64CMOVLHI
721	OpAMD64CMOVLCC
722	OpAMD64CMOVLCS
723	OpAMD64CMOVWEQ
724	OpAMD64CMOVWNE
725	OpAMD64CMOVWLT
726	OpAMD64CMOVWGT
727	OpAMD64CMOVWLE
728	OpAMD64CMOVWGE
729	OpAMD64CMOVWLS
730	OpAMD64CMOVWHI
731	OpAMD64CMOVWCC
732	OpAMD64CMOVWCS
733	OpAMD64CMOVQEQF
734	OpAMD64CMOVQNEF
735	OpAMD64CMOVQGTF
736	OpAMD64CMOVQGEF
737	OpAMD64CMOVLEQF
738	OpAMD64CMOVLNEF
739	OpAMD64CMOVLGTF
740	OpAMD64CMOVLGEF
741	OpAMD64CMOVWEQF
742	OpAMD64CMOVWNEF
743	OpAMD64CMOVWGTF
744	OpAMD64CMOVWGEF
745	OpAMD64BSWAPQ
746	OpAMD64BSWAPL
747	OpAMD64POPCNTQ
748	OpAMD64POPCNTL
749	OpAMD64SQRTSD
750	OpAMD64ROUNDSD
751	OpAMD64VFMADD231SD
752	OpAMD64SBBQcarrymask
753	OpAMD64SBBLcarrymask
754	OpAMD64SETEQ
755	OpAMD64SETNE
756	OpAMD64SETL
757	OpAMD64SETLE
758	OpAMD64SETG
759	OpAMD64SETGE
760	OpAMD64SETB
761	OpAMD64SETBE
762	OpAMD64SETA
763	OpAMD64SETAE
764	OpAMD64SETO
765	OpAMD64SETEQstore
766	OpAMD64SETNEstore
767	OpAMD64SETLstore
768	OpAMD64SETLEstore
769	OpAMD64SETGstore
770	OpAMD64SETGEstore
771	OpAMD64SETBstore
772	OpAMD64SETBEstore
773	OpAMD64SETAstore
774	OpAMD64SETAEstore
775	OpAMD64SETEQF
776	OpAMD64SETNEF
777	OpAMD64SETORD
778	OpAMD64SETNAN
779	OpAMD64SETGF
780	OpAMD64SETGEF
781	OpAMD64MOVBQSX
782	OpAMD64MOVBQZX
783	OpAMD64MOVWQSX
784	OpAMD64MOVWQZX
785	OpAMD64MOVLQSX
786	OpAMD64MOVLQZX
787	OpAMD64MOVLconst
788	OpAMD64MOVQconst
789	OpAMD64CVTTSD2SL
790	OpAMD64CVTTSD2SQ
791	OpAMD64CVTTSS2SL
792	OpAMD64CVTTSS2SQ
793	OpAMD64CVTSL2SS
794	OpAMD64CVTSL2SD
795	OpAMD64CVTSQ2SS
796	OpAMD64CVTSQ2SD
797	OpAMD64CVTSD2SS
798	OpAMD64CVTSS2SD
799	OpAMD64MOVQi2f
800	OpAMD64MOVQf2i
801	OpAMD64MOVLi2f
802	OpAMD64MOVLf2i
803	OpAMD64PXOR
804	OpAMD64LEAQ
805	OpAMD64LEAL
806	OpAMD64LEAW
807	OpAMD64LEAQ1
808	OpAMD64LEAL1
809	OpAMD64LEAW1
810	OpAMD64LEAQ2
811	OpAMD64LEAL2
812	OpAMD64LEAW2
813	OpAMD64LEAQ4
814	OpAMD64LEAL4
815	OpAMD64LEAW4
816	OpAMD64LEAQ8
817	OpAMD64LEAL8
818	OpAMD64LEAW8
819	OpAMD64MOVBload
820	OpAMD64MOVBQSXload
821	OpAMD64MOVWload
822	OpAMD64MOVWQSXload
823	OpAMD64MOVLload
824	OpAMD64MOVLQSXload
825	OpAMD64MOVQload
826	OpAMD64MOVBstore
827	OpAMD64MOVWstore
828	OpAMD64MOVLstore
829	OpAMD64MOVQstore
830	OpAMD64MOVOload
831	OpAMD64MOVOstore
832	OpAMD64MOVBloadidx1
833	OpAMD64MOVWloadidx1
834	OpAMD64MOVWloadidx2
835	OpAMD64MOVLloadidx1
836	OpAMD64MOVLloadidx4
837	OpAMD64MOVLloadidx8
838	OpAMD64MOVQloadidx1
839	OpAMD64MOVQloadidx8
840	OpAMD64MOVBstoreidx1
841	OpAMD64MOVWstoreidx1
842	OpAMD64MOVWstoreidx2
843	OpAMD64MOVLstoreidx1
844	OpAMD64MOVLstoreidx4
845	OpAMD64MOVLstoreidx8
846	OpAMD64MOVQstoreidx1
847	OpAMD64MOVQstoreidx8
848	OpAMD64MOVBstoreconst
849	OpAMD64MOVWstoreconst
850	OpAMD64MOVLstoreconst
851	OpAMD64MOVQstoreconst
852	OpAMD64MOVBstoreconstidx1
853	OpAMD64MOVWstoreconstidx1
854	OpAMD64MOVWstoreconstidx2
855	OpAMD64MOVLstoreconstidx1
856	OpAMD64MOVLstoreconstidx4
857	OpAMD64MOVQstoreconstidx1
858	OpAMD64MOVQstoreconstidx8
859	OpAMD64DUFFZERO
860	OpAMD64MOVOconst
861	OpAMD64REPSTOSQ
862	OpAMD64CALLstatic
863	OpAMD64CALLclosure
864	OpAMD64CALLinter
865	OpAMD64DUFFCOPY
866	OpAMD64REPMOVSQ
867	OpAMD64InvertFlags
868	OpAMD64LoweredGetG
869	OpAMD64LoweredGetClosurePtr
870	OpAMD64LoweredGetCallerPC
871	OpAMD64LoweredGetCallerSP
872	OpAMD64LoweredNilCheck
873	OpAMD64LoweredWB
874	OpAMD64LoweredPanicBoundsA
875	OpAMD64LoweredPanicBoundsB
876	OpAMD64LoweredPanicBoundsC
877	OpAMD64FlagEQ
878	OpAMD64FlagLT_ULT
879	OpAMD64FlagLT_UGT
880	OpAMD64FlagGT_UGT
881	OpAMD64FlagGT_ULT
882	OpAMD64MOVBatomicload
883	OpAMD64MOVLatomicload
884	OpAMD64MOVQatomicload
885	OpAMD64XCHGB
886	OpAMD64XCHGL
887	OpAMD64XCHGQ
888	OpAMD64XADDLlock
889	OpAMD64XADDQlock
890	OpAMD64AddTupleFirst32
891	OpAMD64AddTupleFirst64
892	OpAMD64CMPXCHGLlock
893	OpAMD64CMPXCHGQlock
894	OpAMD64ANDBlock
895	OpAMD64ORBlock
896
897	OpARMADD
898	OpARMADDconst
899	OpARMSUB
900	OpARMSUBconst
901	OpARMRSB
902	OpARMRSBconst
903	OpARMMUL
904	OpARMHMUL
905	OpARMHMULU
906	OpARMCALLudiv
907	OpARMADDS
908	OpARMADDSconst
909	OpARMADC
910	OpARMADCconst
911	OpARMSUBS
912	OpARMSUBSconst
913	OpARMRSBSconst
914	OpARMSBC
915	OpARMSBCconst
916	OpARMRSCconst
917	OpARMMULLU
918	OpARMMULA
919	OpARMMULS
920	OpARMADDF
921	OpARMADDD
922	OpARMSUBF
923	OpARMSUBD
924	OpARMMULF
925	OpARMMULD
926	OpARMNMULF
927	OpARMNMULD
928	OpARMDIVF
929	OpARMDIVD
930	OpARMMULAF
931	OpARMMULAD
932	OpARMMULSF
933	OpARMMULSD
934	OpARMFMULAD
935	OpARMAND
936	OpARMANDconst
937	OpARMOR
938	OpARMORconst
939	OpARMXOR
940	OpARMXORconst
941	OpARMBIC
942	OpARMBICconst
943	OpARMBFX
944	OpARMBFXU
945	OpARMMVN
946	OpARMNEGF
947	OpARMNEGD
948	OpARMSQRTD
949	OpARMABSD
950	OpARMCLZ
951	OpARMREV
952	OpARMREV16
953	OpARMRBIT
954	OpARMSLL
955	OpARMSLLconst
956	OpARMSRL
957	OpARMSRLconst
958	OpARMSRA
959	OpARMSRAconst
960	OpARMSRR
961	OpARMSRRconst
962	OpARMADDshiftLL
963	OpARMADDshiftRL
964	OpARMADDshiftRA
965	OpARMSUBshiftLL
966	OpARMSUBshiftRL
967	OpARMSUBshiftRA
968	OpARMRSBshiftLL
969	OpARMRSBshiftRL
970	OpARMRSBshiftRA
971	OpARMANDshiftLL
972	OpARMANDshiftRL
973	OpARMANDshiftRA
974	OpARMORshiftLL
975	OpARMORshiftRL
976	OpARMORshiftRA
977	OpARMXORshiftLL
978	OpARMXORshiftRL
979	OpARMXORshiftRA
980	OpARMXORshiftRR
981	OpARMBICshiftLL
982	OpARMBICshiftRL
983	OpARMBICshiftRA
984	OpARMMVNshiftLL
985	OpARMMVNshiftRL
986	OpARMMVNshiftRA
987	OpARMADCshiftLL
988	OpARMADCshiftRL
989	OpARMADCshiftRA
990	OpARMSBCshiftLL
991	OpARMSBCshiftRL
992	OpARMSBCshiftRA
993	OpARMRSCshiftLL
994	OpARMRSCshiftRL
995	OpARMRSCshiftRA
996	OpARMADDSshiftLL
997	OpARMADDSshiftRL
998	OpARMADDSshiftRA
999	OpARMSUBSshiftLL
1000	OpARMSUBSshiftRL
1001	OpARMSUBSshiftRA
1002	OpARMRSBSshiftLL
1003	OpARMRSBSshiftRL
1004	OpARMRSBSshiftRA
1005	OpARMADDshiftLLreg
1006	OpARMADDshiftRLreg
1007	OpARMADDshiftRAreg
1008	OpARMSUBshiftLLreg
1009	OpARMSUBshiftRLreg
1010	OpARMSUBshiftRAreg
1011	OpARMRSBshiftLLreg
1012	OpARMRSBshiftRLreg
1013	OpARMRSBshiftRAreg
1014	OpARMANDshiftLLreg
1015	OpARMANDshiftRLreg
1016	OpARMANDshiftRAreg
1017	OpARMORshiftLLreg
1018	OpARMORshiftRLreg
1019	OpARMORshiftRAreg
1020	OpARMXORshiftLLreg
1021	OpARMXORshiftRLreg
1022	OpARMXORshiftRAreg
1023	OpARMBICshiftLLreg
1024	OpARMBICshiftRLreg
1025	OpARMBICshiftRAreg
1026	OpARMMVNshiftLLreg
1027	OpARMMVNshiftRLreg
1028	OpARMMVNshiftRAreg
1029	OpARMADCshiftLLreg
1030	OpARMADCshiftRLreg
1031	OpARMADCshiftRAreg
1032	OpARMSBCshiftLLreg
1033	OpARMSBCshiftRLreg
1034	OpARMSBCshiftRAreg
1035	OpARMRSCshiftLLreg
1036	OpARMRSCshiftRLreg
1037	OpARMRSCshiftRAreg
1038	OpARMADDSshiftLLreg
1039	OpARMADDSshiftRLreg
1040	OpARMADDSshiftRAreg
1041	OpARMSUBSshiftLLreg
1042	OpARMSUBSshiftRLreg
1043	OpARMSUBSshiftRAreg
1044	OpARMRSBSshiftLLreg
1045	OpARMRSBSshiftRLreg
1046	OpARMRSBSshiftRAreg
1047	OpARMCMP
1048	OpARMCMPconst
1049	OpARMCMN
1050	OpARMCMNconst
1051	OpARMTST
1052	OpARMTSTconst
1053	OpARMTEQ
1054	OpARMTEQconst
1055	OpARMCMPF
1056	OpARMCMPD
1057	OpARMCMPshiftLL
1058	OpARMCMPshiftRL
1059	OpARMCMPshiftRA
1060	OpARMCMNshiftLL
1061	OpARMCMNshiftRL
1062	OpARMCMNshiftRA
1063	OpARMTSTshiftLL
1064	OpARMTSTshiftRL
1065	OpARMTSTshiftRA
1066	OpARMTEQshiftLL
1067	OpARMTEQshiftRL
1068	OpARMTEQshiftRA
1069	OpARMCMPshiftLLreg
1070	OpARMCMPshiftRLreg
1071	OpARMCMPshiftRAreg
1072	OpARMCMNshiftLLreg
1073	OpARMCMNshiftRLreg
1074	OpARMCMNshiftRAreg
1075	OpARMTSTshiftLLreg
1076	OpARMTSTshiftRLreg
1077	OpARMTSTshiftRAreg
1078	OpARMTEQshiftLLreg
1079	OpARMTEQshiftRLreg
1080	OpARMTEQshiftRAreg
1081	OpARMCMPF0
1082	OpARMCMPD0
1083	OpARMMOVWconst
1084	OpARMMOVFconst
1085	OpARMMOVDconst
1086	OpARMMOVWaddr
1087	OpARMMOVBload
1088	OpARMMOVBUload
1089	OpARMMOVHload
1090	OpARMMOVHUload
1091	OpARMMOVWload
1092	OpARMMOVFload
1093	OpARMMOVDload
1094	OpARMMOVBstore
1095	OpARMMOVHstore
1096	OpARMMOVWstore
1097	OpARMMOVFstore
1098	OpARMMOVDstore
1099	OpARMMOVWloadidx
1100	OpARMMOVWloadshiftLL
1101	OpARMMOVWloadshiftRL
1102	OpARMMOVWloadshiftRA
1103	OpARMMOVBUloadidx
1104	OpARMMOVBloadidx
1105	OpARMMOVHUloadidx
1106	OpARMMOVHloadidx
1107	OpARMMOVWstoreidx
1108	OpARMMOVWstoreshiftLL
1109	OpARMMOVWstoreshiftRL
1110	OpARMMOVWstoreshiftRA
1111	OpARMMOVBstoreidx
1112	OpARMMOVHstoreidx
1113	OpARMMOVBreg
1114	OpARMMOVBUreg
1115	OpARMMOVHreg
1116	OpARMMOVHUreg
1117	OpARMMOVWreg
1118	OpARMMOVWnop
1119	OpARMMOVWF
1120	OpARMMOVWD
1121	OpARMMOVWUF
1122	OpARMMOVWUD
1123	OpARMMOVFW
1124	OpARMMOVDW
1125	OpARMMOVFWU
1126	OpARMMOVDWU
1127	OpARMMOVFD
1128	OpARMMOVDF
1129	OpARMCMOVWHSconst
1130	OpARMCMOVWLSconst
1131	OpARMSRAcond
1132	OpARMCALLstatic
1133	OpARMCALLclosure
1134	OpARMCALLinter
1135	OpARMLoweredNilCheck
1136	OpARMEqual
1137	OpARMNotEqual
1138	OpARMLessThan
1139	OpARMLessEqual
1140	OpARMGreaterThan
1141	OpARMGreaterEqual
1142	OpARMLessThanU
1143	OpARMLessEqualU
1144	OpARMGreaterThanU
1145	OpARMGreaterEqualU
1146	OpARMDUFFZERO
1147	OpARMDUFFCOPY
1148	OpARMLoweredZero
1149	OpARMLoweredMove
1150	OpARMLoweredGetClosurePtr
1151	OpARMLoweredGetCallerSP
1152	OpARMLoweredGetCallerPC
1153	OpARMLoweredPanicBoundsA
1154	OpARMLoweredPanicBoundsB
1155	OpARMLoweredPanicBoundsC
1156	OpARMLoweredPanicExtendA
1157	OpARMLoweredPanicExtendB
1158	OpARMLoweredPanicExtendC
1159	OpARMFlagEQ
1160	OpARMFlagLT_ULT
1161	OpARMFlagLT_UGT
1162	OpARMFlagGT_UGT
1163	OpARMFlagGT_ULT
1164	OpARMInvertFlags
1165	OpARMLoweredWB
1166
1167	OpARM64ADCSflags
1168	OpARM64ADCzerocarry
1169	OpARM64ADD
1170	OpARM64ADDconst
1171	OpARM64ADDSconstflags
1172	OpARM64ADDSflags
1173	OpARM64SUB
1174	OpARM64SUBconst
1175	OpARM64SBCSflags
1176	OpARM64SUBSflags
1177	OpARM64MUL
1178	OpARM64MULW
1179	OpARM64MNEG
1180	OpARM64MNEGW
1181	OpARM64MULH
1182	OpARM64UMULH
1183	OpARM64MULL
1184	OpARM64UMULL
1185	OpARM64DIV
1186	OpARM64UDIV
1187	OpARM64DIVW
1188	OpARM64UDIVW
1189	OpARM64MOD
1190	OpARM64UMOD
1191	OpARM64MODW
1192	OpARM64UMODW
1193	OpARM64FADDS
1194	OpARM64FADDD
1195	OpARM64FSUBS
1196	OpARM64FSUBD
1197	OpARM64FMULS
1198	OpARM64FMULD
1199	OpARM64FNMULS
1200	OpARM64FNMULD
1201	OpARM64FDIVS
1202	OpARM64FDIVD
1203	OpARM64AND
1204	OpARM64ANDconst
1205	OpARM64OR
1206	OpARM64ORconst
1207	OpARM64XOR
1208	OpARM64XORconst
1209	OpARM64BIC
1210	OpARM64EON
1211	OpARM64ORN
1212	OpARM64LoweredMuluhilo
1213	OpARM64MVN
1214	OpARM64NEG
1215	OpARM64NEGSflags
1216	OpARM64NGCzerocarry
1217	OpARM64FABSD
1218	OpARM64FNEGS
1219	OpARM64FNEGD
1220	OpARM64FSQRTD
1221	OpARM64REV
1222	OpARM64REVW
1223	OpARM64REV16W
1224	OpARM64RBIT
1225	OpARM64RBITW
1226	OpARM64CLZ
1227	OpARM64CLZW
1228	OpARM64VCNT
1229	OpARM64VUADDLV
1230	OpARM64LoweredRound32F
1231	OpARM64LoweredRound64F
1232	OpARM64FMADDS
1233	OpARM64FMADDD
1234	OpARM64FNMADDS
1235	OpARM64FNMADDD
1236	OpARM64FMSUBS
1237	OpARM64FMSUBD
1238	OpARM64FNMSUBS
1239	OpARM64FNMSUBD
1240	OpARM64MADD
1241	OpARM64MADDW
1242	OpARM64MSUB
1243	OpARM64MSUBW
1244	OpARM64SLL
1245	OpARM64SLLconst
1246	OpARM64SRL
1247	OpARM64SRLconst
1248	OpARM64SRA
1249	OpARM64SRAconst
1250	OpARM64ROR
1251	OpARM64RORW
1252	OpARM64RORconst
1253	OpARM64RORWconst
1254	OpARM64EXTRconst
1255	OpARM64EXTRWconst
1256	OpARM64CMP
1257	OpARM64CMPconst
1258	OpARM64CMPW
1259	OpARM64CMPWconst
1260	OpARM64CMN
1261	OpARM64CMNconst
1262	OpARM64CMNW
1263	OpARM64CMNWconst
1264	OpARM64TST
1265	OpARM64TSTconst
1266	OpARM64TSTW
1267	OpARM64TSTWconst
1268	OpARM64FCMPS
1269	OpARM64FCMPD
1270	OpARM64FCMPS0
1271	OpARM64FCMPD0
1272	OpARM64MVNshiftLL
1273	OpARM64MVNshiftRL
1274	OpARM64MVNshiftRA
1275	OpARM64NEGshiftLL
1276	OpARM64NEGshiftRL
1277	OpARM64NEGshiftRA
1278	OpARM64ADDshiftLL
1279	OpARM64ADDshiftRL
1280	OpARM64ADDshiftRA
1281	OpARM64SUBshiftLL
1282	OpARM64SUBshiftRL
1283	OpARM64SUBshiftRA
1284	OpARM64ANDshiftLL
1285	OpARM64ANDshiftRL
1286	OpARM64ANDshiftRA
1287	OpARM64ORshiftLL
1288	OpARM64ORshiftRL
1289	OpARM64ORshiftRA
1290	OpARM64XORshiftLL
1291	OpARM64XORshiftRL
1292	OpARM64XORshiftRA
1293	OpARM64BICshiftLL
1294	OpARM64BICshiftRL
1295	OpARM64BICshiftRA
1296	OpARM64EONshiftLL
1297	OpARM64EONshiftRL
1298	OpARM64EONshiftRA
1299	OpARM64ORNshiftLL
1300	OpARM64ORNshiftRL
1301	OpARM64ORNshiftRA
1302	OpARM64CMPshiftLL
1303	OpARM64CMPshiftRL
1304	OpARM64CMPshiftRA
1305	OpARM64CMNshiftLL
1306	OpARM64CMNshiftRL
1307	OpARM64CMNshiftRA
1308	OpARM64TSTshiftLL
1309	OpARM64TSTshiftRL
1310	OpARM64TSTshiftRA
1311	OpARM64BFI
1312	OpARM64BFXIL
1313	OpARM64SBFIZ
1314	OpARM64SBFX
1315	OpARM64UBFIZ
1316	OpARM64UBFX
1317	OpARM64MOVDconst
1318	OpARM64FMOVSconst
1319	OpARM64FMOVDconst
1320	OpARM64MOVDaddr
1321	OpARM64MOVBload
1322	OpARM64MOVBUload
1323	OpARM64MOVHload
1324	OpARM64MOVHUload
1325	OpARM64MOVWload
1326	OpARM64MOVWUload
1327	OpARM64MOVDload
1328	OpARM64FMOVSload
1329	OpARM64FMOVDload
1330	OpARM64MOVDloadidx
1331	OpARM64MOVWloadidx
1332	OpARM64MOVWUloadidx
1333	OpARM64MOVHloadidx
1334	OpARM64MOVHUloadidx
1335	OpARM64MOVBloadidx
1336	OpARM64MOVBUloadidx
1337	OpARM64FMOVSloadidx
1338	OpARM64FMOVDloadidx
1339	OpARM64MOVHloadidx2
1340	OpARM64MOVHUloadidx2
1341	OpARM64MOVWloadidx4
1342	OpARM64MOVWUloadidx4
1343	OpARM64MOVDloadidx8
1344	OpARM64MOVBstore
1345	OpARM64MOVHstore
1346	OpARM64MOVWstore
1347	OpARM64MOVDstore
1348	OpARM64STP
1349	OpARM64FMOVSstore
1350	OpARM64FMOVDstore
1351	OpARM64MOVBstoreidx
1352	OpARM64MOVHstoreidx
1353	OpARM64MOVWstoreidx
1354	OpARM64MOVDstoreidx
1355	OpARM64FMOVSstoreidx
1356	OpARM64FMOVDstoreidx
1357	OpARM64MOVHstoreidx2
1358	OpARM64MOVWstoreidx4
1359	OpARM64MOVDstoreidx8
1360	OpARM64MOVBstorezero
1361	OpARM64MOVHstorezero
1362	OpARM64MOVWstorezero
1363	OpARM64MOVDstorezero
1364	OpARM64MOVQstorezero
1365	OpARM64MOVBstorezeroidx
1366	OpARM64MOVHstorezeroidx
1367	OpARM64MOVWstorezeroidx
1368	OpARM64MOVDstorezeroidx
1369	OpARM64MOVHstorezeroidx2
1370	OpARM64MOVWstorezeroidx4
1371	OpARM64MOVDstorezeroidx8
1372	OpARM64FMOVDgpfp
1373	OpARM64FMOVDfpgp
1374	OpARM64FMOVSgpfp
1375	OpARM64FMOVSfpgp
1376	OpARM64MOVBreg
1377	OpARM64MOVBUreg
1378	OpARM64MOVHreg
1379	OpARM64MOVHUreg
1380	OpARM64MOVWreg
1381	OpARM64MOVWUreg
1382	OpARM64MOVDreg
1383	OpARM64MOVDnop
1384	OpARM64SCVTFWS
1385	OpARM64SCVTFWD
1386	OpARM64UCVTFWS
1387	OpARM64UCVTFWD
1388	OpARM64SCVTFS
1389	OpARM64SCVTFD
1390	OpARM64UCVTFS
1391	OpARM64UCVTFD
1392	OpARM64FCVTZSSW
1393	OpARM64FCVTZSDW
1394	OpARM64FCVTZUSW
1395	OpARM64FCVTZUDW
1396	OpARM64FCVTZSS
1397	OpARM64FCVTZSD
1398	OpARM64FCVTZUS
1399	OpARM64FCVTZUD
1400	OpARM64FCVTSD
1401	OpARM64FCVTDS
1402	OpARM64FRINTAD
1403	OpARM64FRINTMD
1404	OpARM64FRINTND
1405	OpARM64FRINTPD
1406	OpARM64FRINTZD
1407	OpARM64CSEL
1408	OpARM64CSEL0
1409	OpARM64CALLstatic
1410	OpARM64CALLclosure
1411	OpARM64CALLinter
1412	OpARM64LoweredNilCheck
1413	OpARM64Equal
1414	OpARM64NotEqual
1415	OpARM64LessThan
1416	OpARM64LessEqual
1417	OpARM64GreaterThan
1418	OpARM64GreaterEqual
1419	OpARM64LessThanU
1420	OpARM64LessEqualU
1421	OpARM64GreaterThanU
1422	OpARM64GreaterEqualU
1423	OpARM64LessThanF
1424	OpARM64LessEqualF
1425	OpARM64GreaterThanF
1426	OpARM64GreaterEqualF
1427	OpARM64DUFFZERO
1428	OpARM64LoweredZero
1429	OpARM64DUFFCOPY
1430	OpARM64LoweredMove
1431	OpARM64LoweredGetClosurePtr
1432	OpARM64LoweredGetCallerSP
1433	OpARM64LoweredGetCallerPC
1434	OpARM64FlagEQ
1435	OpARM64FlagLT_ULT
1436	OpARM64FlagLT_UGT
1437	OpARM64FlagGT_UGT
1438	OpARM64FlagGT_ULT
1439	OpARM64InvertFlags
1440	OpARM64LDAR
1441	OpARM64LDARB
1442	OpARM64LDARW
1443	OpARM64STLRB
1444	OpARM64STLR
1445	OpARM64STLRW
1446	OpARM64LoweredAtomicExchange64
1447	OpARM64LoweredAtomicExchange32
1448	OpARM64LoweredAtomicAdd64
1449	OpARM64LoweredAtomicAdd32
1450	OpARM64LoweredAtomicAdd64Variant
1451	OpARM64LoweredAtomicAdd32Variant
1452	OpARM64LoweredAtomicCas64
1453	OpARM64LoweredAtomicCas32
1454	OpARM64LoweredAtomicAnd8
1455	OpARM64LoweredAtomicOr8
1456	OpARM64LoweredWB
1457	OpARM64LoweredPanicBoundsA
1458	OpARM64LoweredPanicBoundsB
1459	OpARM64LoweredPanicBoundsC
1460
1461	OpMIPSADD
1462	OpMIPSADDconst
1463	OpMIPSSUB
1464	OpMIPSSUBconst
1465	OpMIPSMUL
1466	OpMIPSMULT
1467	OpMIPSMULTU
1468	OpMIPSDIV
1469	OpMIPSDIVU
1470	OpMIPSADDF
1471	OpMIPSADDD
1472	OpMIPSSUBF
1473	OpMIPSSUBD
1474	OpMIPSMULF
1475	OpMIPSMULD
1476	OpMIPSDIVF
1477	OpMIPSDIVD
1478	OpMIPSAND
1479	OpMIPSANDconst
1480	OpMIPSOR
1481	OpMIPSORconst
1482	OpMIPSXOR
1483	OpMIPSXORconst
1484	OpMIPSNOR
1485	OpMIPSNORconst
1486	OpMIPSNEG
1487	OpMIPSNEGF
1488	OpMIPSNEGD
1489	OpMIPSSQRTD
1490	OpMIPSSLL
1491	OpMIPSSLLconst
1492	OpMIPSSRL
1493	OpMIPSSRLconst
1494	OpMIPSSRA
1495	OpMIPSSRAconst
1496	OpMIPSCLZ
1497	OpMIPSSGT
1498	OpMIPSSGTconst
1499	OpMIPSSGTzero
1500	OpMIPSSGTU
1501	OpMIPSSGTUconst
1502	OpMIPSSGTUzero
1503	OpMIPSCMPEQF
1504	OpMIPSCMPEQD
1505	OpMIPSCMPGEF
1506	OpMIPSCMPGED
1507	OpMIPSCMPGTF
1508	OpMIPSCMPGTD
1509	OpMIPSMOVWconst
1510	OpMIPSMOVFconst
1511	OpMIPSMOVDconst
1512	OpMIPSMOVWaddr
1513	OpMIPSMOVBload
1514	OpMIPSMOVBUload
1515	OpMIPSMOVHload
1516	OpMIPSMOVHUload
1517	OpMIPSMOVWload
1518	OpMIPSMOVFload
1519	OpMIPSMOVDload
1520	OpMIPSMOVBstore
1521	OpMIPSMOVHstore
1522	OpMIPSMOVWstore
1523	OpMIPSMOVFstore
1524	OpMIPSMOVDstore
1525	OpMIPSMOVBstorezero
1526	OpMIPSMOVHstorezero
1527	OpMIPSMOVWstorezero
1528	OpMIPSMOVBreg
1529	OpMIPSMOVBUreg
1530	OpMIPSMOVHreg
1531	OpMIPSMOVHUreg
1532	OpMIPSMOVWreg
1533	OpMIPSMOVWnop
1534	OpMIPSCMOVZ
1535	OpMIPSCMOVZzero
1536	OpMIPSMOVWF
1537	OpMIPSMOVWD
1538	OpMIPSTRUNCFW
1539	OpMIPSTRUNCDW
1540	OpMIPSMOVFD
1541	OpMIPSMOVDF
1542	OpMIPSCALLstatic
1543	OpMIPSCALLclosure
1544	OpMIPSCALLinter
1545	OpMIPSLoweredAtomicLoad8
1546	OpMIPSLoweredAtomicLoad32
1547	OpMIPSLoweredAtomicStore8
1548	OpMIPSLoweredAtomicStore32
1549	OpMIPSLoweredAtomicStorezero
1550	OpMIPSLoweredAtomicExchange
1551	OpMIPSLoweredAtomicAdd
1552	OpMIPSLoweredAtomicAddconst
1553	OpMIPSLoweredAtomicCas
1554	OpMIPSLoweredAtomicAnd
1555	OpMIPSLoweredAtomicOr
1556	OpMIPSLoweredZero
1557	OpMIPSLoweredMove
1558	OpMIPSLoweredNilCheck
1559	OpMIPSFPFlagTrue
1560	OpMIPSFPFlagFalse
1561	OpMIPSLoweredGetClosurePtr
1562	OpMIPSLoweredGetCallerSP
1563	OpMIPSLoweredGetCallerPC
1564	OpMIPSLoweredWB
1565	OpMIPSLoweredPanicBoundsA
1566	OpMIPSLoweredPanicBoundsB
1567	OpMIPSLoweredPanicBoundsC
1568	OpMIPSLoweredPanicExtendA
1569	OpMIPSLoweredPanicExtendB
1570	OpMIPSLoweredPanicExtendC
1571
1572	OpMIPS64ADDV
1573	OpMIPS64ADDVconst
1574	OpMIPS64SUBV
1575	OpMIPS64SUBVconst
1576	OpMIPS64MULV
1577	OpMIPS64MULVU
1578	OpMIPS64DIVV
1579	OpMIPS64DIVVU
1580	OpMIPS64ADDF
1581	OpMIPS64ADDD
1582	OpMIPS64SUBF
1583	OpMIPS64SUBD
1584	OpMIPS64MULF
1585	OpMIPS64MULD
1586	OpMIPS64DIVF
1587	OpMIPS64DIVD
1588	OpMIPS64AND
1589	OpMIPS64ANDconst
1590	OpMIPS64OR
1591	OpMIPS64ORconst
1592	OpMIPS64XOR
1593	OpMIPS64XORconst
1594	OpMIPS64NOR
1595	OpMIPS64NORconst
1596	OpMIPS64NEGV
1597	OpMIPS64NEGF
1598	OpMIPS64NEGD
1599	OpMIPS64SQRTD
1600	OpMIPS64SLLV
1601	OpMIPS64SLLVconst
1602	OpMIPS64SRLV
1603	OpMIPS64SRLVconst
1604	OpMIPS64SRAV
1605	OpMIPS64SRAVconst
1606	OpMIPS64SGT
1607	OpMIPS64SGTconst
1608	OpMIPS64SGTU
1609	OpMIPS64SGTUconst
1610	OpMIPS64CMPEQF
1611	OpMIPS64CMPEQD
1612	OpMIPS64CMPGEF
1613	OpMIPS64CMPGED
1614	OpMIPS64CMPGTF
1615	OpMIPS64CMPGTD
1616	OpMIPS64MOVVconst
1617	OpMIPS64MOVFconst
1618	OpMIPS64MOVDconst
1619	OpMIPS64MOVVaddr
1620	OpMIPS64MOVBload
1621	OpMIPS64MOVBUload
1622	OpMIPS64MOVHload
1623	OpMIPS64MOVHUload
1624	OpMIPS64MOVWload
1625	OpMIPS64MOVWUload
1626	OpMIPS64MOVVload
1627	OpMIPS64MOVFload
1628	OpMIPS64MOVDload
1629	OpMIPS64MOVBstore
1630	OpMIPS64MOVHstore
1631	OpMIPS64MOVWstore
1632	OpMIPS64MOVVstore
1633	OpMIPS64MOVFstore
1634	OpMIPS64MOVDstore
1635	OpMIPS64MOVBstorezero
1636	OpMIPS64MOVHstorezero
1637	OpMIPS64MOVWstorezero
1638	OpMIPS64MOVVstorezero
1639	OpMIPS64MOVBreg
1640	OpMIPS64MOVBUreg
1641	OpMIPS64MOVHreg
1642	OpMIPS64MOVHUreg
1643	OpMIPS64MOVWreg
1644	OpMIPS64MOVWUreg
1645	OpMIPS64MOVVreg
1646	OpMIPS64MOVVnop
1647	OpMIPS64MOVWF
1648	OpMIPS64MOVWD
1649	OpMIPS64MOVVF
1650	OpMIPS64MOVVD
1651	OpMIPS64TRUNCFW
1652	OpMIPS64TRUNCDW
1653	OpMIPS64TRUNCFV
1654	OpMIPS64TRUNCDV
1655	OpMIPS64MOVFD
1656	OpMIPS64MOVDF
1657	OpMIPS64CALLstatic
1658	OpMIPS64CALLclosure
1659	OpMIPS64CALLinter
1660	OpMIPS64DUFFZERO
1661	OpMIPS64DUFFCOPY
1662	OpMIPS64LoweredZero
1663	OpMIPS64LoweredMove
1664	OpMIPS64LoweredAtomicLoad8
1665	OpMIPS64LoweredAtomicLoad32
1666	OpMIPS64LoweredAtomicLoad64
1667	OpMIPS64LoweredAtomicStore8
1668	OpMIPS64LoweredAtomicStore32
1669	OpMIPS64LoweredAtomicStore64
1670	OpMIPS64LoweredAtomicStorezero32
1671	OpMIPS64LoweredAtomicStorezero64
1672	OpMIPS64LoweredAtomicExchange32
1673	OpMIPS64LoweredAtomicExchange64
1674	OpMIPS64LoweredAtomicAdd32
1675	OpMIPS64LoweredAtomicAdd64
1676	OpMIPS64LoweredAtomicAddconst32
1677	OpMIPS64LoweredAtomicAddconst64
1678	OpMIPS64LoweredAtomicCas32
1679	OpMIPS64LoweredAtomicCas64
1680	OpMIPS64LoweredNilCheck
1681	OpMIPS64FPFlagTrue
1682	OpMIPS64FPFlagFalse
1683	OpMIPS64LoweredGetClosurePtr
1684	OpMIPS64LoweredGetCallerSP
1685	OpMIPS64LoweredGetCallerPC
1686	OpMIPS64LoweredWB
1687	OpMIPS64LoweredPanicBoundsA
1688	OpMIPS64LoweredPanicBoundsB
1689	OpMIPS64LoweredPanicBoundsC
1690
1691	OpPPC64ADD
1692	OpPPC64ADDconst
1693	OpPPC64FADD
1694	OpPPC64FADDS
1695	OpPPC64SUB
1696	OpPPC64FSUB
1697	OpPPC64FSUBS
1698	OpPPC64MULLD
1699	OpPPC64MULLW
1700	OpPPC64MULHD
1701	OpPPC64MULHW
1702	OpPPC64MULHDU
1703	OpPPC64MULHWU
1704	OpPPC64LoweredMuluhilo
1705	OpPPC64FMUL
1706	OpPPC64FMULS
1707	OpPPC64FMADD
1708	OpPPC64FMADDS
1709	OpPPC64FMSUB
1710	OpPPC64FMSUBS
1711	OpPPC64SRAD
1712	OpPPC64SRAW
1713	OpPPC64SRD
1714	OpPPC64SRW
1715	OpPPC64SLD
1716	OpPPC64SLW
1717	OpPPC64ROTL
1718	OpPPC64ROTLW
1719	OpPPC64LoweredAdd64Carry
1720	OpPPC64ADDconstForCarry
1721	OpPPC64MaskIfNotCarry
1722	OpPPC64SRADconst
1723	OpPPC64SRAWconst
1724	OpPPC64SRDconst
1725	OpPPC64SRWconst
1726	OpPPC64SLDconst
1727	OpPPC64SLWconst
1728	OpPPC64ROTLconst
1729	OpPPC64ROTLWconst
1730	OpPPC64CNTLZD
1731	OpPPC64CNTLZW
1732	OpPPC64CNTTZD
1733	OpPPC64CNTTZW
1734	OpPPC64POPCNTD
1735	OpPPC64POPCNTW
1736	OpPPC64POPCNTB
1737	OpPPC64FDIV
1738	OpPPC64FDIVS
1739	OpPPC64DIVD
1740	OpPPC64DIVW
1741	OpPPC64DIVDU
1742	OpPPC64DIVWU
1743	OpPPC64FCTIDZ
1744	OpPPC64FCTIWZ
1745	OpPPC64FCFID
1746	OpPPC64FCFIDS
1747	OpPPC64FRSP
1748	OpPPC64MFVSRD
1749	OpPPC64MTVSRD
1750	OpPPC64AND
1751	OpPPC64ANDN
1752	OpPPC64ANDCC
1753	OpPPC64OR
1754	OpPPC64ORN
1755	OpPPC64ORCC
1756	OpPPC64NOR
1757	OpPPC64XOR
1758	OpPPC64XORCC
1759	OpPPC64EQV
1760	OpPPC64NEG
1761	OpPPC64FNEG
1762	OpPPC64FSQRT
1763	OpPPC64FSQRTS
1764	OpPPC64FFLOOR
1765	OpPPC64FCEIL
1766	OpPPC64FTRUNC
1767	OpPPC64FROUND
1768	OpPPC64FABS
1769	OpPPC64FNABS
1770	OpPPC64FCPSGN
1771	OpPPC64ORconst
1772	OpPPC64XORconst
1773	OpPPC64ANDconst
1774	OpPPC64ANDCCconst
1775	OpPPC64MOVBreg
1776	OpPPC64MOVBZreg
1777	OpPPC64MOVHreg
1778	OpPPC64MOVHZreg
1779	OpPPC64MOVWreg
1780	OpPPC64MOVWZreg
1781	OpPPC64MOVBZload
1782	OpPPC64MOVHload
1783	OpPPC64MOVHZload
1784	OpPPC64MOVWload
1785	OpPPC64MOVWZload
1786	OpPPC64MOVDload
1787	OpPPC64MOVDBRload
1788	OpPPC64MOVWBRload
1789	OpPPC64MOVHBRload
1790	OpPPC64MOVBZloadidx
1791	OpPPC64MOVHloadidx
1792	OpPPC64MOVHZloadidx
1793	OpPPC64MOVWloadidx
1794	OpPPC64MOVWZloadidx
1795	OpPPC64MOVDloadidx
1796	OpPPC64MOVHBRloadidx
1797	OpPPC64MOVWBRloadidx
1798	OpPPC64MOVDBRloadidx
1799	OpPPC64FMOVDloadidx
1800	OpPPC64FMOVSloadidx
1801	OpPPC64MOVDBRstore
1802	OpPPC64MOVWBRstore
1803	OpPPC64MOVHBRstore
1804	OpPPC64FMOVDload
1805	OpPPC64FMOVSload
1806	OpPPC64MOVBstore
1807	OpPPC64MOVHstore
1808	OpPPC64MOVWstore
1809	OpPPC64MOVDstore
1810	OpPPC64FMOVDstore
1811	OpPPC64FMOVSstore
1812	OpPPC64MOVBstoreidx
1813	OpPPC64MOVHstoreidx
1814	OpPPC64MOVWstoreidx
1815	OpPPC64MOVDstoreidx
1816	OpPPC64FMOVDstoreidx
1817	OpPPC64FMOVSstoreidx
1818	OpPPC64MOVHBRstoreidx
1819	OpPPC64MOVWBRstoreidx
1820	OpPPC64MOVDBRstoreidx
1821	OpPPC64MOVBstorezero
1822	OpPPC64MOVHstorezero
1823	OpPPC64MOVWstorezero
1824	OpPPC64MOVDstorezero
1825	OpPPC64MOVDaddr
1826	OpPPC64MOVDconst
1827	OpPPC64FMOVDconst
1828	OpPPC64FMOVSconst
1829	OpPPC64FCMPU
1830	OpPPC64CMP
1831	OpPPC64CMPU
1832	OpPPC64CMPW
1833	OpPPC64CMPWU
1834	OpPPC64CMPconst
1835	OpPPC64CMPUconst
1836	OpPPC64CMPWconst
1837	OpPPC64CMPWUconst
1838	OpPPC64ISEL
1839	OpPPC64ISELB
1840	OpPPC64Equal
1841	OpPPC64NotEqual
1842	OpPPC64LessThan
1843	OpPPC64FLessThan
1844	OpPPC64LessEqual
1845	OpPPC64FLessEqual
1846	OpPPC64GreaterThan
1847	OpPPC64FGreaterThan
1848	OpPPC64GreaterEqual
1849	OpPPC64FGreaterEqual
1850	OpPPC64LoweredGetClosurePtr
1851	OpPPC64LoweredGetCallerSP
1852	OpPPC64LoweredGetCallerPC
1853	OpPPC64LoweredNilCheck
1854	OpPPC64LoweredRound32F
1855	OpPPC64LoweredRound64F
1856	OpPPC64CALLstatic
1857	OpPPC64CALLclosure
1858	OpPPC64CALLinter
1859	OpPPC64LoweredZero
1860	OpPPC64LoweredMove
1861	OpPPC64LoweredAtomicStore8
1862	OpPPC64LoweredAtomicStore32
1863	OpPPC64LoweredAtomicStore64
1864	OpPPC64LoweredAtomicLoad8
1865	OpPPC64LoweredAtomicLoad32
1866	OpPPC64LoweredAtomicLoad64
1867	OpPPC64LoweredAtomicLoadPtr
1868	OpPPC64LoweredAtomicAdd32
1869	OpPPC64LoweredAtomicAdd64
1870	OpPPC64LoweredAtomicExchange32
1871	OpPPC64LoweredAtomicExchange64
1872	OpPPC64LoweredAtomicCas64
1873	OpPPC64LoweredAtomicCas32
1874	OpPPC64LoweredAtomicAnd8
1875	OpPPC64LoweredAtomicOr8
1876	OpPPC64LoweredWB
1877	OpPPC64LoweredPanicBoundsA
1878	OpPPC64LoweredPanicBoundsB
1879	OpPPC64LoweredPanicBoundsC
1880	OpPPC64InvertFlags
1881	OpPPC64FlagEQ
1882	OpPPC64FlagLT
1883	OpPPC64FlagGT
1884
1885	OpRISCV64ADD
1886	OpRISCV64ADDI
1887	OpRISCV64SUB
1888	OpRISCV64MUL
1889	OpRISCV64MULW
1890	OpRISCV64MULH
1891	OpRISCV64MULHU
1892	OpRISCV64DIV
1893	OpRISCV64DIVU
1894	OpRISCV64DIVW
1895	OpRISCV64DIVUW
1896	OpRISCV64REM
1897	OpRISCV64REMU
1898	OpRISCV64REMW
1899	OpRISCV64REMUW
1900	OpRISCV64MOVaddr
1901	OpRISCV64MOVBconst
1902	OpRISCV64MOVHconst
1903	OpRISCV64MOVWconst
1904	OpRISCV64MOVDconst
1905	OpRISCV64MOVBload
1906	OpRISCV64MOVHload
1907	OpRISCV64MOVWload
1908	OpRISCV64MOVDload
1909	OpRISCV64MOVBUload
1910	OpRISCV64MOVHUload
1911	OpRISCV64MOVWUload
1912	OpRISCV64MOVBstore
1913	OpRISCV64MOVHstore
1914	OpRISCV64MOVWstore
1915	OpRISCV64MOVDstore
1916	OpRISCV64SLL
1917	OpRISCV64SRA
1918	OpRISCV64SRL
1919	OpRISCV64SLLI
1920	OpRISCV64SRAI
1921	OpRISCV64SRLI
1922	OpRISCV64XOR
1923	OpRISCV64XORI
1924	OpRISCV64OR
1925	OpRISCV64ORI
1926	OpRISCV64AND
1927	OpRISCV64ANDI
1928	OpRISCV64SEQZ
1929	OpRISCV64SNEZ
1930	OpRISCV64SLT
1931	OpRISCV64SLTI
1932	OpRISCV64SLTU
1933	OpRISCV64SLTIU
1934	OpRISCV64MOVconvert
1935	OpRISCV64CALLstatic
1936	OpRISCV64CALLclosure
1937	OpRISCV64CALLinter
1938	OpRISCV64LoweredZero
1939	OpRISCV64LoweredMove
1940	OpRISCV64LoweredNilCheck
1941	OpRISCV64LoweredGetClosurePtr
1942	OpRISCV64LoweredGetCallerSP
1943	OpRISCV64LoweredGetCallerPC
1944	OpRISCV64LoweredWB
1945	OpRISCV64LoweredPanicBoundsA
1946	OpRISCV64LoweredPanicBoundsB
1947	OpRISCV64LoweredPanicBoundsC
1948	OpRISCV64FADDS
1949	OpRISCV64FSUBS
1950	OpRISCV64FMULS
1951	OpRISCV64FDIVS
1952	OpRISCV64FSQRTS
1953	OpRISCV64FNEGS
1954	OpRISCV64FMVSX
1955	OpRISCV64FCVTSW
1956	OpRISCV64FCVTSL
1957	OpRISCV64FCVTWS
1958	OpRISCV64FCVTLS
1959	OpRISCV64FMOVWload
1960	OpRISCV64FMOVWstore
1961	OpRISCV64FEQS
1962	OpRISCV64FNES
1963	OpRISCV64FLTS
1964	OpRISCV64FLES
1965	OpRISCV64FADDD
1966	OpRISCV64FSUBD
1967	OpRISCV64FMULD
1968	OpRISCV64FDIVD
1969	OpRISCV64FSQRTD
1970	OpRISCV64FNEGD
1971	OpRISCV64FMVDX
1972	OpRISCV64FCVTDW
1973	OpRISCV64FCVTDL
1974	OpRISCV64FCVTWD
1975	OpRISCV64FCVTLD
1976	OpRISCV64FCVTDS
1977	OpRISCV64FCVTSD
1978	OpRISCV64FMOVDload
1979	OpRISCV64FMOVDstore
1980	OpRISCV64FEQD
1981	OpRISCV64FNED
1982	OpRISCV64FLTD
1983	OpRISCV64FLED
1984
1985	OpS390XFADDS
1986	OpS390XFADD
1987	OpS390XFSUBS
1988	OpS390XFSUB
1989	OpS390XFMULS
1990	OpS390XFMUL
1991	OpS390XFDIVS
1992	OpS390XFDIV
1993	OpS390XFNEGS
1994	OpS390XFNEG
1995	OpS390XFMADDS
1996	OpS390XFMADD
1997	OpS390XFMSUBS
1998	OpS390XFMSUB
1999	OpS390XLPDFR
2000	OpS390XLNDFR
2001	OpS390XCPSDR
2002	OpS390XFIDBR
2003	OpS390XFMOVSload
2004	OpS390XFMOVDload
2005	OpS390XFMOVSconst
2006	OpS390XFMOVDconst
2007	OpS390XFMOVSloadidx
2008	OpS390XFMOVDloadidx
2009	OpS390XFMOVSstore
2010	OpS390XFMOVDstore
2011	OpS390XFMOVSstoreidx
2012	OpS390XFMOVDstoreidx
2013	OpS390XADD
2014	OpS390XADDW
2015	OpS390XADDconst
2016	OpS390XADDWconst
2017	OpS390XADDload
2018	OpS390XADDWload
2019	OpS390XSUB
2020	OpS390XSUBW
2021	OpS390XSUBconst
2022	OpS390XSUBWconst
2023	OpS390XSUBload
2024	OpS390XSUBWload
2025	OpS390XMULLD
2026	OpS390XMULLW
2027	OpS390XMULLDconst
2028	OpS390XMULLWconst
2029	OpS390XMULLDload
2030	OpS390XMULLWload
2031	OpS390XMULHD
2032	OpS390XMULHDU
2033	OpS390XDIVD
2034	OpS390XDIVW
2035	OpS390XDIVDU
2036	OpS390XDIVWU
2037	OpS390XMODD
2038	OpS390XMODW
2039	OpS390XMODDU
2040	OpS390XMODWU
2041	OpS390XAND
2042	OpS390XANDW
2043	OpS390XANDconst
2044	OpS390XANDWconst
2045	OpS390XANDload
2046	OpS390XANDWload
2047	OpS390XOR
2048	OpS390XORW
2049	OpS390XORconst
2050	OpS390XORWconst
2051	OpS390XORload
2052	OpS390XORWload
2053	OpS390XXOR
2054	OpS390XXORW
2055	OpS390XXORconst
2056	OpS390XXORWconst
2057	OpS390XXORload
2058	OpS390XXORWload
2059	OpS390XADDC
2060	OpS390XADDCconst
2061	OpS390XADDE
2062	OpS390XSUBC
2063	OpS390XSUBE
2064	OpS390XCMP
2065	OpS390XCMPW
2066	OpS390XCMPU
2067	OpS390XCMPWU
2068	OpS390XCMPconst
2069	OpS390XCMPWconst
2070	OpS390XCMPUconst
2071	OpS390XCMPWUconst
2072	OpS390XFCMPS
2073	OpS390XFCMP
2074	OpS390XSLD
2075	OpS390XSLW
2076	OpS390XSLDconst
2077	OpS390XSLWconst
2078	OpS390XSRD
2079	OpS390XSRW
2080	OpS390XSRDconst
2081	OpS390XSRWconst
2082	OpS390XSRAD
2083	OpS390XSRAW
2084	OpS390XSRADconst
2085	OpS390XSRAWconst
2086	OpS390XRLLG
2087	OpS390XRLL
2088	OpS390XRLLGconst
2089	OpS390XRLLconst
2090	OpS390XRXSBG
2091	OpS390XNEG
2092	OpS390XNEGW
2093	OpS390XNOT
2094	OpS390XNOTW
2095	OpS390XFSQRT
2096	OpS390XLOCGR
2097	OpS390XMOVBreg
2098	OpS390XMOVBZreg
2099	OpS390XMOVHreg
2100	OpS390XMOVHZreg
2101	OpS390XMOVWreg
2102	OpS390XMOVWZreg
2103	OpS390XMOVDconst
2104	OpS390XLDGR
2105	OpS390XLGDR
2106	OpS390XCFDBRA
2107	OpS390XCGDBRA
2108	OpS390XCFEBRA
2109	OpS390XCGEBRA
2110	OpS390XCEFBRA
2111	OpS390XCDFBRA
2112	OpS390XCEGBRA
2113	OpS390XCDGBRA
2114	OpS390XLEDBR
2115	OpS390XLDEBR
2116	OpS390XMOVDaddr
2117	OpS390XMOVDaddridx
2118	OpS390XMOVBZload
2119	OpS390XMOVBload
2120	OpS390XMOVHZload
2121	OpS390XMOVHload
2122	OpS390XMOVWZload
2123	OpS390XMOVWload
2124	OpS390XMOVDload
2125	OpS390XMOVWBR
2126	OpS390XMOVDBR
2127	OpS390XMOVHBRload
2128	OpS390XMOVWBRload
2129	OpS390XMOVDBRload
2130	OpS390XMOVBstore
2131	OpS390XMOVHstore
2132	OpS390XMOVWstore
2133	OpS390XMOVDstore
2134	OpS390XMOVHBRstore
2135	OpS390XMOVWBRstore
2136	OpS390XMOVDBRstore
2137	OpS390XMVC
2138	OpS390XMOVBZloadidx
2139	OpS390XMOVBloadidx
2140	OpS390XMOVHZloadidx
2141	OpS390XMOVHloadidx
2142	OpS390XMOVWZloadidx
2143	OpS390XMOVWloadidx
2144	OpS390XMOVDloadidx
2145	OpS390XMOVHBRloadidx
2146	OpS390XMOVWBRloadidx
2147	OpS390XMOVDBRloadidx
2148	OpS390XMOVBstoreidx
2149	OpS390XMOVHstoreidx
2150	OpS390XMOVWstoreidx
2151	OpS390XMOVDstoreidx
2152	OpS390XMOVHBRstoreidx
2153	OpS390XMOVWBRstoreidx
2154	OpS390XMOVDBRstoreidx
2155	OpS390XMOVBstoreconst
2156	OpS390XMOVHstoreconst
2157	OpS390XMOVWstoreconst
2158	OpS390XMOVDstoreconst
2159	OpS390XCLEAR
2160	OpS390XCALLstatic
2161	OpS390XCALLclosure
2162	OpS390XCALLinter
2163	OpS390XInvertFlags
2164	OpS390XLoweredGetG
2165	OpS390XLoweredGetClosurePtr
2166	OpS390XLoweredGetCallerSP
2167	OpS390XLoweredGetCallerPC
2168	OpS390XLoweredNilCheck
2169	OpS390XLoweredRound32F
2170	OpS390XLoweredRound64F
2171	OpS390XLoweredWB
2172	OpS390XLoweredPanicBoundsA
2173	OpS390XLoweredPanicBoundsB
2174	OpS390XLoweredPanicBoundsC
2175	OpS390XFlagEQ
2176	OpS390XFlagLT
2177	OpS390XFlagGT
2178	OpS390XFlagOV
2179	OpS390XSYNC
2180	OpS390XMOVBZatomicload
2181	OpS390XMOVWZatomicload
2182	OpS390XMOVDatomicload
2183	OpS390XMOVBatomicstore
2184	OpS390XMOVWatomicstore
2185	OpS390XMOVDatomicstore
2186	OpS390XLAA
2187	OpS390XLAAG
2188	OpS390XAddTupleFirst32
2189	OpS390XAddTupleFirst64
2190	OpS390XLAOfloor
2191	OpS390XLANfloor
2192	OpS390XLoweredAtomicCas32
2193	OpS390XLoweredAtomicCas64
2194	OpS390XLoweredAtomicExchange32
2195	OpS390XLoweredAtomicExchange64
2196	OpS390XFLOGR
2197	OpS390XPOPCNT
2198	OpS390XMLGR
2199	OpS390XSumBytes2
2200	OpS390XSumBytes4
2201	OpS390XSumBytes8
2202	OpS390XSTMG2
2203	OpS390XSTMG3
2204	OpS390XSTMG4
2205	OpS390XSTM2
2206	OpS390XSTM3
2207	OpS390XSTM4
2208	OpS390XLoweredMove
2209	OpS390XLoweredZero
2210
2211	OpWasmLoweredStaticCall
2212	OpWasmLoweredClosureCall
2213	OpWasmLoweredInterCall
2214	OpWasmLoweredAddr
2215	OpWasmLoweredMove
2216	OpWasmLoweredZero
2217	OpWasmLoweredGetClosurePtr
2218	OpWasmLoweredGetCallerPC
2219	OpWasmLoweredGetCallerSP
2220	OpWasmLoweredNilCheck
2221	OpWasmLoweredWB
2222	OpWasmLoweredConvert
2223	OpWasmSelect
2224	OpWasmI64Load8U
2225	OpWasmI64Load8S
2226	OpWasmI64Load16U
2227	OpWasmI64Load16S
2228	OpWasmI64Load32U
2229	OpWasmI64Load32S
2230	OpWasmI64Load
2231	OpWasmI64Store8
2232	OpWasmI64Store16
2233	OpWasmI64Store32
2234	OpWasmI64Store
2235	OpWasmF32Load
2236	OpWasmF64Load
2237	OpWasmF32Store
2238	OpWasmF64Store
2239	OpWasmI64Const
2240	OpWasmF32Const
2241	OpWasmF64Const
2242	OpWasmI64Eqz
2243	OpWasmI64Eq
2244	OpWasmI64Ne
2245	OpWasmI64LtS
2246	OpWasmI64LtU
2247	OpWasmI64GtS
2248	OpWasmI64GtU
2249	OpWasmI64LeS
2250	OpWasmI64LeU
2251	OpWasmI64GeS
2252	OpWasmI64GeU
2253	OpWasmF32Eq
2254	OpWasmF32Ne
2255	OpWasmF32Lt
2256	OpWasmF32Gt
2257	OpWasmF32Le
2258	OpWasmF32Ge
2259	OpWasmF64Eq
2260	OpWasmF64Ne
2261	OpWasmF64Lt
2262	OpWasmF64Gt
2263	OpWasmF64Le
2264	OpWasmF64Ge
2265	OpWasmI64Add
2266	OpWasmI64AddConst
2267	OpWasmI64Sub
2268	OpWasmI64Mul
2269	OpWasmI64DivS
2270	OpWasmI64DivU
2271	OpWasmI64RemS
2272	OpWasmI64RemU
2273	OpWasmI64And
2274	OpWasmI64Or
2275	OpWasmI64Xor
2276	OpWasmI64Shl
2277	OpWasmI64ShrS
2278	OpWasmI64ShrU
2279	OpWasmF32Neg
2280	OpWasmF32Add
2281	OpWasmF32Sub
2282	OpWasmF32Mul
2283	OpWasmF32Div
2284	OpWasmF64Neg
2285	OpWasmF64Add
2286	OpWasmF64Sub
2287	OpWasmF64Mul
2288	OpWasmF64Div
2289	OpWasmI64TruncSatF64S
2290	OpWasmI64TruncSatF64U
2291	OpWasmI64TruncSatF32S
2292	OpWasmI64TruncSatF32U
2293	OpWasmF32ConvertI64S
2294	OpWasmF32ConvertI64U
2295	OpWasmF64ConvertI64S
2296	OpWasmF64ConvertI64U
2297	OpWasmF32DemoteF64
2298	OpWasmF64PromoteF32
2299	OpWasmI64Extend8S
2300	OpWasmI64Extend16S
2301	OpWasmI64Extend32S
2302	OpWasmF32Sqrt
2303	OpWasmF32Trunc
2304	OpWasmF32Ceil
2305	OpWasmF32Floor
2306	OpWasmF32Nearest
2307	OpWasmF32Abs
2308	OpWasmF32Copysign
2309	OpWasmF64Sqrt
2310	OpWasmF64Trunc
2311	OpWasmF64Ceil
2312	OpWasmF64Floor
2313	OpWasmF64Nearest
2314	OpWasmF64Abs
2315	OpWasmF64Copysign
2316	OpWasmI64Ctz
2317	OpWasmI64Clz
2318	OpWasmI32Rotl
2319	OpWasmI64Rotl
2320	OpWasmI64Popcnt
2321
2322	OpAdd8
2323	OpAdd16
2324	OpAdd32
2325	OpAdd64
2326	OpAddPtr
2327	OpAdd32F
2328	OpAdd64F
2329	OpSub8
2330	OpSub16
2331	OpSub32
2332	OpSub64
2333	OpSubPtr
2334	OpSub32F
2335	OpSub64F
2336	OpMul8
2337	OpMul16
2338	OpMul32
2339	OpMul64
2340	OpMul32F
2341	OpMul64F
2342	OpDiv32F
2343	OpDiv64F
2344	OpHmul32
2345	OpHmul32u
2346	OpHmul64
2347	OpHmul64u
2348	OpMul32uhilo
2349	OpMul64uhilo
2350	OpMul32uover
2351	OpMul64uover
2352	OpAvg32u
2353	OpAvg64u
2354	OpDiv8
2355	OpDiv8u
2356	OpDiv16
2357	OpDiv16u
2358	OpDiv32
2359	OpDiv32u
2360	OpDiv64
2361	OpDiv64u
2362	OpDiv128u
2363	OpMod8
2364	OpMod8u
2365	OpMod16
2366	OpMod16u
2367	OpMod32
2368	OpMod32u
2369	OpMod64
2370	OpMod64u
2371	OpAnd8
2372	OpAnd16
2373	OpAnd32
2374	OpAnd64
2375	OpOr8
2376	OpOr16
2377	OpOr32
2378	OpOr64
2379	OpXor8
2380	OpXor16
2381	OpXor32
2382	OpXor64
2383	OpLsh8x8
2384	OpLsh8x16
2385	OpLsh8x32
2386	OpLsh8x64
2387	OpLsh16x8
2388	OpLsh16x16
2389	OpLsh16x32
2390	OpLsh16x64
2391	OpLsh32x8
2392	OpLsh32x16
2393	OpLsh32x32
2394	OpLsh32x64
2395	OpLsh64x8
2396	OpLsh64x16
2397	OpLsh64x32
2398	OpLsh64x64
2399	OpRsh8x8
2400	OpRsh8x16
2401	OpRsh8x32
2402	OpRsh8x64
2403	OpRsh16x8
2404	OpRsh16x16
2405	OpRsh16x32
2406	OpRsh16x64
2407	OpRsh32x8
2408	OpRsh32x16
2409	OpRsh32x32
2410	OpRsh32x64
2411	OpRsh64x8
2412	OpRsh64x16
2413	OpRsh64x32
2414	OpRsh64x64
2415	OpRsh8Ux8
2416	OpRsh8Ux16
2417	OpRsh8Ux32
2418	OpRsh8Ux64
2419	OpRsh16Ux8
2420	OpRsh16Ux16
2421	OpRsh16Ux32
2422	OpRsh16Ux64
2423	OpRsh32Ux8
2424	OpRsh32Ux16
2425	OpRsh32Ux32
2426	OpRsh32Ux64
2427	OpRsh64Ux8
2428	OpRsh64Ux16
2429	OpRsh64Ux32
2430	OpRsh64Ux64
2431	OpEq8
2432	OpEq16
2433	OpEq32
2434	OpEq64
2435	OpEqPtr
2436	OpEqInter
2437	OpEqSlice
2438	OpEq32F
2439	OpEq64F
2440	OpNeq8
2441	OpNeq16
2442	OpNeq32
2443	OpNeq64
2444	OpNeqPtr
2445	OpNeqInter
2446	OpNeqSlice
2447	OpNeq32F
2448	OpNeq64F
2449	OpLess8
2450	OpLess8U
2451	OpLess16
2452	OpLess16U
2453	OpLess32
2454	OpLess32U
2455	OpLess64
2456	OpLess64U
2457	OpLess32F
2458	OpLess64F
2459	OpLeq8
2460	OpLeq8U
2461	OpLeq16
2462	OpLeq16U
2463	OpLeq32
2464	OpLeq32U
2465	OpLeq64
2466	OpLeq64U
2467	OpLeq32F
2468	OpLeq64F
2469	OpGreater8
2470	OpGreater8U
2471	OpGreater16
2472	OpGreater16U
2473	OpGreater32
2474	OpGreater32U
2475	OpGreater64
2476	OpGreater64U
2477	OpGreater32F
2478	OpGreater64F
2479	OpGeq8
2480	OpGeq8U
2481	OpGeq16
2482	OpGeq16U
2483	OpGeq32
2484	OpGeq32U
2485	OpGeq64
2486	OpGeq64U
2487	OpGeq32F
2488	OpGeq64F
2489	OpCondSelect
2490	OpAndB
2491	OpOrB
2492	OpEqB
2493	OpNeqB
2494	OpNot
2495	OpNeg8
2496	OpNeg16
2497	OpNeg32
2498	OpNeg64
2499	OpNeg32F
2500	OpNeg64F
2501	OpCom8
2502	OpCom16
2503	OpCom32
2504	OpCom64
2505	OpCtz8
2506	OpCtz16
2507	OpCtz32
2508	OpCtz64
2509	OpCtz8NonZero
2510	OpCtz16NonZero
2511	OpCtz32NonZero
2512	OpCtz64NonZero
2513	OpBitLen8
2514	OpBitLen16
2515	OpBitLen32
2516	OpBitLen64
2517	OpBswap32
2518	OpBswap64
2519	OpBitRev8
2520	OpBitRev16
2521	OpBitRev32
2522	OpBitRev64
2523	OpPopCount8
2524	OpPopCount16
2525	OpPopCount32
2526	OpPopCount64
2527	OpRotateLeft8
2528	OpRotateLeft16
2529	OpRotateLeft32
2530	OpRotateLeft64
2531	OpSqrt
2532	OpFloor
2533	OpCeil
2534	OpTrunc
2535	OpRound
2536	OpRoundToEven
2537	OpAbs
2538	OpCopysign
2539	OpFMA
2540	OpPhi
2541	OpCopy
2542	OpConvert
2543	OpConstBool
2544	OpConstString
2545	OpConstNil
2546	OpConst8
2547	OpConst16
2548	OpConst32
2549	OpConst64
2550	OpConst32F
2551	OpConst64F
2552	OpConstInterface
2553	OpConstSlice
2554	OpInitMem
2555	OpArg
2556	OpAddr
2557	OpLocalAddr
2558	OpSP
2559	OpSB
2560	OpLoad
2561	OpStore
2562	OpMove
2563	OpZero
2564	OpStoreWB
2565	OpMoveWB
2566	OpZeroWB
2567	OpWB
2568	OpPanicBounds
2569	OpPanicExtend
2570	OpClosureCall
2571	OpStaticCall
2572	OpInterCall
2573	OpSignExt8to16
2574	OpSignExt8to32
2575	OpSignExt8to64
2576	OpSignExt16to32
2577	OpSignExt16to64
2578	OpSignExt32to64
2579	OpZeroExt8to16
2580	OpZeroExt8to32
2581	OpZeroExt8to64
2582	OpZeroExt16to32
2583	OpZeroExt16to64
2584	OpZeroExt32to64
2585	OpTrunc16to8
2586	OpTrunc32to8
2587	OpTrunc32to16
2588	OpTrunc64to8
2589	OpTrunc64to16
2590	OpTrunc64to32
2591	OpCvt32to32F
2592	OpCvt32to64F
2593	OpCvt64to32F
2594	OpCvt64to64F
2595	OpCvt32Fto32
2596	OpCvt32Fto64
2597	OpCvt64Fto32
2598	OpCvt64Fto64
2599	OpCvt32Fto64F
2600	OpCvt64Fto32F
2601	OpRound32F
2602	OpRound64F
2603	OpIsNonNil
2604	OpIsInBounds
2605	OpIsSliceInBounds
2606	OpNilCheck
2607	OpGetG
2608	OpGetClosurePtr
2609	OpGetCallerPC
2610	OpGetCallerSP
2611	OpPtrIndex
2612	OpOffPtr
2613	OpSliceMake
2614	OpSlicePtr
2615	OpSliceLen
2616	OpSliceCap
2617	OpComplexMake
2618	OpComplexReal
2619	OpComplexImag
2620	OpStringMake
2621	OpStringPtr
2622	OpStringLen
2623	OpIMake
2624	OpITab
2625	OpIData
2626	OpStructMake0
2627	OpStructMake1
2628	OpStructMake2
2629	OpStructMake3
2630	OpStructMake4
2631	OpStructSelect
2632	OpArrayMake0
2633	OpArrayMake1
2634	OpArraySelect
2635	OpStoreReg
2636	OpLoadReg
2637	OpFwdRef
2638	OpUnknown
2639	OpVarDef
2640	OpVarKill
2641	OpVarLive
2642	OpKeepAlive
2643	OpInlMark
2644	OpInt64Make
2645	OpInt64Hi
2646	OpInt64Lo
2647	OpAdd32carry
2648	OpAdd32withcarry
2649	OpSub32carry
2650	OpSub32withcarry
2651	OpAdd64carry
2652	OpSub64borrow
2653	OpSignmask
2654	OpZeromask
2655	OpSlicemask
2656	OpCvt32Uto32F
2657	OpCvt32Uto64F
2658	OpCvt32Fto32U
2659	OpCvt64Fto32U
2660	OpCvt64Uto32F
2661	OpCvt64Uto64F
2662	OpCvt32Fto64U
2663	OpCvt64Fto64U
2664	OpSelect0
2665	OpSelect1
2666	OpAtomicLoad8
2667	OpAtomicLoad32
2668	OpAtomicLoad64
2669	OpAtomicLoadPtr
2670	OpAtomicLoadAcq32
2671	OpAtomicStore8
2672	OpAtomicStore32
2673	OpAtomicStore64
2674	OpAtomicStorePtrNoWB
2675	OpAtomicStoreRel32
2676	OpAtomicExchange32
2677	OpAtomicExchange64
2678	OpAtomicAdd32
2679	OpAtomicAdd64
2680	OpAtomicCompareAndSwap32
2681	OpAtomicCompareAndSwap64
2682	OpAtomicCompareAndSwapRel32
2683	OpAtomicAnd8
2684	OpAtomicOr8
2685	OpAtomicAdd32Variant
2686	OpAtomicAdd64Variant
2687	OpClobber
2688)
2689
2690var opcodeTable = [...]opInfo{
2691	{name: "OpInvalid"},
2692
2693	{
2694		name:         "ADDSS",
2695		argLen:       2,
2696		commutative:  true,
2697		resultInArg0: true,
2698		usesScratch:  true,
2699		asm:          x86.AADDSS,
2700		reg: regInfo{
2701			inputs: []inputInfo{
2702				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2703				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2704			},
2705			outputs: []outputInfo{
2706				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2707			},
2708		},
2709	},
2710	{
2711		name:         "ADDSD",
2712		argLen:       2,
2713		commutative:  true,
2714		resultInArg0: true,
2715		asm:          x86.AADDSD,
2716		reg: regInfo{
2717			inputs: []inputInfo{
2718				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2719				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2720			},
2721			outputs: []outputInfo{
2722				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2723			},
2724		},
2725	},
2726	{
2727		name:         "SUBSS",
2728		argLen:       2,
2729		resultInArg0: true,
2730		usesScratch:  true,
2731		asm:          x86.ASUBSS,
2732		reg: regInfo{
2733			inputs: []inputInfo{
2734				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2735				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2736			},
2737			outputs: []outputInfo{
2738				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2739			},
2740		},
2741	},
2742	{
2743		name:         "SUBSD",
2744		argLen:       2,
2745		resultInArg0: true,
2746		asm:          x86.ASUBSD,
2747		reg: regInfo{
2748			inputs: []inputInfo{
2749				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2750				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2751			},
2752			outputs: []outputInfo{
2753				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2754			},
2755		},
2756	},
2757	{
2758		name:         "MULSS",
2759		argLen:       2,
2760		commutative:  true,
2761		resultInArg0: true,
2762		usesScratch:  true,
2763		asm:          x86.AMULSS,
2764		reg: regInfo{
2765			inputs: []inputInfo{
2766				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2767				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2768			},
2769			outputs: []outputInfo{
2770				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2771			},
2772		},
2773	},
2774	{
2775		name:         "MULSD",
2776		argLen:       2,
2777		commutative:  true,
2778		resultInArg0: true,
2779		asm:          x86.AMULSD,
2780		reg: regInfo{
2781			inputs: []inputInfo{
2782				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2783				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2784			},
2785			outputs: []outputInfo{
2786				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2787			},
2788		},
2789	},
2790	{
2791		name:         "DIVSS",
2792		argLen:       2,
2793		resultInArg0: true,
2794		usesScratch:  true,
2795		asm:          x86.ADIVSS,
2796		reg: regInfo{
2797			inputs: []inputInfo{
2798				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2799				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2800			},
2801			outputs: []outputInfo{
2802				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2803			},
2804		},
2805	},
2806	{
2807		name:         "DIVSD",
2808		argLen:       2,
2809		resultInArg0: true,
2810		asm:          x86.ADIVSD,
2811		reg: regInfo{
2812			inputs: []inputInfo{
2813				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2814				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2815			},
2816			outputs: []outputInfo{
2817				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2818			},
2819		},
2820	},
2821	{
2822		name:           "MOVSSload",
2823		auxType:        auxSymOff,
2824		argLen:         2,
2825		faultOnNilArg0: true,
2826		symEffect:      SymRead,
2827		asm:            x86.AMOVSS,
2828		reg: regInfo{
2829			inputs: []inputInfo{
2830				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2831			},
2832			outputs: []outputInfo{
2833				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2834			},
2835		},
2836	},
2837	{
2838		name:           "MOVSDload",
2839		auxType:        auxSymOff,
2840		argLen:         2,
2841		faultOnNilArg0: true,
2842		symEffect:      SymRead,
2843		asm:            x86.AMOVSD,
2844		reg: regInfo{
2845			inputs: []inputInfo{
2846				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2847			},
2848			outputs: []outputInfo{
2849				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2850			},
2851		},
2852	},
2853	{
2854		name:              "MOVSSconst",
2855		auxType:           auxFloat32,
2856		argLen:            0,
2857		rematerializeable: true,
2858		asm:               x86.AMOVSS,
2859		reg: regInfo{
2860			outputs: []outputInfo{
2861				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2862			},
2863		},
2864	},
2865	{
2866		name:              "MOVSDconst",
2867		auxType:           auxFloat64,
2868		argLen:            0,
2869		rematerializeable: true,
2870		asm:               x86.AMOVSD,
2871		reg: regInfo{
2872			outputs: []outputInfo{
2873				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2874			},
2875		},
2876	},
2877	{
2878		name:      "MOVSSloadidx1",
2879		auxType:   auxSymOff,
2880		argLen:    3,
2881		symEffect: SymRead,
2882		asm:       x86.AMOVSS,
2883		reg: regInfo{
2884			inputs: []inputInfo{
2885				{1, 255},   // AX CX DX BX SP BP SI DI
2886				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2887			},
2888			outputs: []outputInfo{
2889				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2890			},
2891		},
2892	},
2893	{
2894		name:      "MOVSSloadidx4",
2895		auxType:   auxSymOff,
2896		argLen:    3,
2897		symEffect: SymRead,
2898		asm:       x86.AMOVSS,
2899		reg: regInfo{
2900			inputs: []inputInfo{
2901				{1, 255},   // AX CX DX BX SP BP SI DI
2902				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2903			},
2904			outputs: []outputInfo{
2905				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2906			},
2907		},
2908	},
2909	{
2910		name:      "MOVSDloadidx1",
2911		auxType:   auxSymOff,
2912		argLen:    3,
2913		symEffect: SymRead,
2914		asm:       x86.AMOVSD,
2915		reg: regInfo{
2916			inputs: []inputInfo{
2917				{1, 255},   // AX CX DX BX SP BP SI DI
2918				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2919			},
2920			outputs: []outputInfo{
2921				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2922			},
2923		},
2924	},
2925	{
2926		name:      "MOVSDloadidx8",
2927		auxType:   auxSymOff,
2928		argLen:    3,
2929		symEffect: SymRead,
2930		asm:       x86.AMOVSD,
2931		reg: regInfo{
2932			inputs: []inputInfo{
2933				{1, 255},   // AX CX DX BX SP BP SI DI
2934				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2935			},
2936			outputs: []outputInfo{
2937				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2938			},
2939		},
2940	},
2941	{
2942		name:           "MOVSSstore",
2943		auxType:        auxSymOff,
2944		argLen:         3,
2945		faultOnNilArg0: true,
2946		symEffect:      SymWrite,
2947		asm:            x86.AMOVSS,
2948		reg: regInfo{
2949			inputs: []inputInfo{
2950				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2951				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2952			},
2953		},
2954	},
2955	{
2956		name:           "MOVSDstore",
2957		auxType:        auxSymOff,
2958		argLen:         3,
2959		faultOnNilArg0: true,
2960		symEffect:      SymWrite,
2961		asm:            x86.AMOVSD,
2962		reg: regInfo{
2963			inputs: []inputInfo{
2964				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2965				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2966			},
2967		},
2968	},
2969	{
2970		name:      "MOVSSstoreidx1",
2971		auxType:   auxSymOff,
2972		argLen:    4,
2973		symEffect: SymWrite,
2974		asm:       x86.AMOVSS,
2975		reg: regInfo{
2976			inputs: []inputInfo{
2977				{1, 255},   // AX CX DX BX SP BP SI DI
2978				{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2979				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2980			},
2981		},
2982	},
2983	{
2984		name:      "MOVSSstoreidx4",
2985		auxType:   auxSymOff,
2986		argLen:    4,
2987		symEffect: SymWrite,
2988		asm:       x86.AMOVSS,
2989		reg: regInfo{
2990			inputs: []inputInfo{
2991				{1, 255},   // AX CX DX BX SP BP SI DI
2992				{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2993				{0, 65791}, // AX CX DX BX SP BP SI DI SB
2994			},
2995		},
2996	},
2997	{
2998		name:      "MOVSDstoreidx1",
2999		auxType:   auxSymOff,
3000		argLen:    4,
3001		symEffect: SymWrite,
3002		asm:       x86.AMOVSD,
3003		reg: regInfo{
3004			inputs: []inputInfo{
3005				{1, 255},   // AX CX DX BX SP BP SI DI
3006				{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3007				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3008			},
3009		},
3010	},
3011	{
3012		name:      "MOVSDstoreidx8",
3013		auxType:   auxSymOff,
3014		argLen:    4,
3015		symEffect: SymWrite,
3016		asm:       x86.AMOVSD,
3017		reg: regInfo{
3018			inputs: []inputInfo{
3019				{1, 255},   // AX CX DX BX SP BP SI DI
3020				{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3021				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3022			},
3023		},
3024	},
3025	{
3026		name:           "ADDSSload",
3027		auxType:        auxSymOff,
3028		argLen:         3,
3029		resultInArg0:   true,
3030		faultOnNilArg1: true,
3031		symEffect:      SymRead,
3032		asm:            x86.AADDSS,
3033		reg: regInfo{
3034			inputs: []inputInfo{
3035				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3036				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3037			},
3038			outputs: []outputInfo{
3039				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3040			},
3041		},
3042	},
3043	{
3044		name:           "ADDSDload",
3045		auxType:        auxSymOff,
3046		argLen:         3,
3047		resultInArg0:   true,
3048		faultOnNilArg1: true,
3049		symEffect:      SymRead,
3050		asm:            x86.AADDSD,
3051		reg: regInfo{
3052			inputs: []inputInfo{
3053				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3054				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3055			},
3056			outputs: []outputInfo{
3057				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3058			},
3059		},
3060	},
3061	{
3062		name:           "SUBSSload",
3063		auxType:        auxSymOff,
3064		argLen:         3,
3065		resultInArg0:   true,
3066		faultOnNilArg1: true,
3067		symEffect:      SymRead,
3068		asm:            x86.ASUBSS,
3069		reg: regInfo{
3070			inputs: []inputInfo{
3071				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3072				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3073			},
3074			outputs: []outputInfo{
3075				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3076			},
3077		},
3078	},
3079	{
3080		name:           "SUBSDload",
3081		auxType:        auxSymOff,
3082		argLen:         3,
3083		resultInArg0:   true,
3084		faultOnNilArg1: true,
3085		symEffect:      SymRead,
3086		asm:            x86.ASUBSD,
3087		reg: regInfo{
3088			inputs: []inputInfo{
3089				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3090				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3091			},
3092			outputs: []outputInfo{
3093				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3094			},
3095		},
3096	},
3097	{
3098		name:           "MULSSload",
3099		auxType:        auxSymOff,
3100		argLen:         3,
3101		resultInArg0:   true,
3102		faultOnNilArg1: true,
3103		symEffect:      SymRead,
3104		asm:            x86.AMULSS,
3105		reg: regInfo{
3106			inputs: []inputInfo{
3107				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3108				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3109			},
3110			outputs: []outputInfo{
3111				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3112			},
3113		},
3114	},
3115	{
3116		name:           "MULSDload",
3117		auxType:        auxSymOff,
3118		argLen:         3,
3119		resultInArg0:   true,
3120		faultOnNilArg1: true,
3121		symEffect:      SymRead,
3122		asm:            x86.AMULSD,
3123		reg: regInfo{
3124			inputs: []inputInfo{
3125				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3126				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3127			},
3128			outputs: []outputInfo{
3129				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3130			},
3131		},
3132	},
3133	{
3134		name:           "DIVSSload",
3135		auxType:        auxSymOff,
3136		argLen:         3,
3137		resultInArg0:   true,
3138		faultOnNilArg1: true,
3139		symEffect:      SymRead,
3140		asm:            x86.ADIVSS,
3141		reg: regInfo{
3142			inputs: []inputInfo{
3143				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3144				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3145			},
3146			outputs: []outputInfo{
3147				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3148			},
3149		},
3150	},
3151	{
3152		name:           "DIVSDload",
3153		auxType:        auxSymOff,
3154		argLen:         3,
3155		resultInArg0:   true,
3156		faultOnNilArg1: true,
3157		symEffect:      SymRead,
3158		asm:            x86.ADIVSD,
3159		reg: regInfo{
3160			inputs: []inputInfo{
3161				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3162				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3163			},
3164			outputs: []outputInfo{
3165				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3166			},
3167		},
3168	},
3169	{
3170		name:         "ADDL",
3171		argLen:       2,
3172		commutative:  true,
3173		clobberFlags: true,
3174		asm:          x86.AADDL,
3175		reg: regInfo{
3176			inputs: []inputInfo{
3177				{1, 239}, // AX CX DX BX BP SI DI
3178				{0, 255}, // AX CX DX BX SP BP SI DI
3179			},
3180			outputs: []outputInfo{
3181				{0, 239}, // AX CX DX BX BP SI DI
3182			},
3183		},
3184	},
3185	{
3186		name:         "ADDLconst",
3187		auxType:      auxInt32,
3188		argLen:       1,
3189		clobberFlags: true,
3190		asm:          x86.AADDL,
3191		reg: regInfo{
3192			inputs: []inputInfo{
3193				{0, 255}, // AX CX DX BX SP BP SI DI
3194			},
3195			outputs: []outputInfo{
3196				{0, 239}, // AX CX DX BX BP SI DI
3197			},
3198		},
3199	},
3200	{
3201		name:         "ADDLcarry",
3202		argLen:       2,
3203		commutative:  true,
3204		resultInArg0: true,
3205		asm:          x86.AADDL,
3206		reg: regInfo{
3207			inputs: []inputInfo{
3208				{0, 239}, // AX CX DX BX BP SI DI
3209				{1, 239}, // AX CX DX BX BP SI DI
3210			},
3211			outputs: []outputInfo{
3212				{1, 0},
3213				{0, 239}, // AX CX DX BX BP SI DI
3214			},
3215		},
3216	},
3217	{
3218		name:         "ADDLconstcarry",
3219		auxType:      auxInt32,
3220		argLen:       1,
3221		resultInArg0: true,
3222		asm:          x86.AADDL,
3223		reg: regInfo{
3224			inputs: []inputInfo{
3225				{0, 239}, // AX CX DX BX BP SI DI
3226			},
3227			outputs: []outputInfo{
3228				{1, 0},
3229				{0, 239}, // AX CX DX BX BP SI DI
3230			},
3231		},
3232	},
3233	{
3234		name:         "ADCL",
3235		argLen:       3,
3236		commutative:  true,
3237		resultInArg0: true,
3238		clobberFlags: true,
3239		asm:          x86.AADCL,
3240		reg: regInfo{
3241			inputs: []inputInfo{
3242				{0, 239}, // AX CX DX BX BP SI DI
3243				{1, 239}, // AX CX DX BX BP SI DI
3244			},
3245			outputs: []outputInfo{
3246				{0, 239}, // AX CX DX BX BP SI DI
3247			},
3248		},
3249	},
3250	{
3251		name:         "ADCLconst",
3252		auxType:      auxInt32,
3253		argLen:       2,
3254		resultInArg0: true,
3255		clobberFlags: true,
3256		asm:          x86.AADCL,
3257		reg: regInfo{
3258			inputs: []inputInfo{
3259				{0, 239}, // AX CX DX BX BP SI DI
3260			},
3261			outputs: []outputInfo{
3262				{0, 239}, // AX CX DX BX BP SI DI
3263			},
3264		},
3265	},
3266	{
3267		name:         "SUBL",
3268		argLen:       2,
3269		resultInArg0: true,
3270		clobberFlags: true,
3271		asm:          x86.ASUBL,
3272		reg: regInfo{
3273			inputs: []inputInfo{
3274				{0, 239}, // AX CX DX BX BP SI DI
3275				{1, 239}, // AX CX DX BX BP SI DI
3276			},
3277			outputs: []outputInfo{
3278				{0, 239}, // AX CX DX BX BP SI DI
3279			},
3280		},
3281	},
3282	{
3283		name:         "SUBLconst",
3284		auxType:      auxInt32,
3285		argLen:       1,
3286		resultInArg0: true,
3287		clobberFlags: true,
3288		asm:          x86.ASUBL,
3289		reg: regInfo{
3290			inputs: []inputInfo{
3291				{0, 239}, // AX CX DX BX BP SI DI
3292			},
3293			outputs: []outputInfo{
3294				{0, 239}, // AX CX DX BX BP SI DI
3295			},
3296		},
3297	},
3298	{
3299		name:         "SUBLcarry",
3300		argLen:       2,
3301		resultInArg0: true,
3302		asm:          x86.ASUBL,
3303		reg: regInfo{
3304			inputs: []inputInfo{
3305				{0, 239}, // AX CX DX BX BP SI DI
3306				{1, 239}, // AX CX DX BX BP SI DI
3307			},
3308			outputs: []outputInfo{
3309				{1, 0},
3310				{0, 239}, // AX CX DX BX BP SI DI
3311			},
3312		},
3313	},
3314	{
3315		name:         "SUBLconstcarry",
3316		auxType:      auxInt32,
3317		argLen:       1,
3318		resultInArg0: true,
3319		asm:          x86.ASUBL,
3320		reg: regInfo{
3321			inputs: []inputInfo{
3322				{0, 239}, // AX CX DX BX BP SI DI
3323			},
3324			outputs: []outputInfo{
3325				{1, 0},
3326				{0, 239}, // AX CX DX BX BP SI DI
3327			},
3328		},
3329	},
3330	{
3331		name:         "SBBL",
3332		argLen:       3,
3333		resultInArg0: true,
3334		clobberFlags: true,
3335		asm:          x86.ASBBL,
3336		reg: regInfo{
3337			inputs: []inputInfo{
3338				{0, 239}, // AX CX DX BX BP SI DI
3339				{1, 239}, // AX CX DX BX BP SI DI
3340			},
3341			outputs: []outputInfo{
3342				{0, 239}, // AX CX DX BX BP SI DI
3343			},
3344		},
3345	},
3346	{
3347		name:         "SBBLconst",
3348		auxType:      auxInt32,
3349		argLen:       2,
3350		resultInArg0: true,
3351		clobberFlags: true,
3352		asm:          x86.ASBBL,
3353		reg: regInfo{
3354			inputs: []inputInfo{
3355				{0, 239}, // AX CX DX BX BP SI DI
3356			},
3357			outputs: []outputInfo{
3358				{0, 239}, // AX CX DX BX BP SI DI
3359			},
3360		},
3361	},
3362	{
3363		name:         "MULL",
3364		argLen:       2,
3365		commutative:  true,
3366		resultInArg0: true,
3367		clobberFlags: true,
3368		asm:          x86.AIMULL,
3369		reg: regInfo{
3370			inputs: []inputInfo{
3371				{0, 239}, // AX CX DX BX BP SI DI
3372				{1, 239}, // AX CX DX BX BP SI DI
3373			},
3374			outputs: []outputInfo{
3375				{0, 239}, // AX CX DX BX BP SI DI
3376			},
3377		},
3378	},
3379	{
3380		name:         "MULLconst",
3381		auxType:      auxInt32,
3382		argLen:       1,
3383		clobberFlags: true,
3384		asm:          x86.AIMUL3L,
3385		reg: regInfo{
3386			inputs: []inputInfo{
3387				{0, 239}, // AX CX DX BX BP SI DI
3388			},
3389			outputs: []outputInfo{
3390				{0, 239}, // AX CX DX BX BP SI DI
3391			},
3392		},
3393	},
3394	{
3395		name:         "MULLU",
3396		argLen:       2,
3397		commutative:  true,
3398		clobberFlags: true,
3399		asm:          x86.AMULL,
3400		reg: regInfo{
3401			inputs: []inputInfo{
3402				{0, 1},   // AX
3403				{1, 255}, // AX CX DX BX SP BP SI DI
3404			},
3405			clobbers: 4, // DX
3406			outputs: []outputInfo{
3407				{1, 0},
3408				{0, 1}, // AX
3409			},
3410		},
3411	},
3412	{
3413		name:         "HMULL",
3414		argLen:       2,
3415		commutative:  true,
3416		clobberFlags: true,
3417		asm:          x86.AIMULL,
3418		reg: regInfo{
3419			inputs: []inputInfo{
3420				{0, 1},   // AX
3421				{1, 255}, // AX CX DX BX SP BP SI DI
3422			},
3423			clobbers: 1, // AX
3424			outputs: []outputInfo{
3425				{0, 4}, // DX
3426			},
3427		},
3428	},
3429	{
3430		name:         "HMULLU",
3431		argLen:       2,
3432		commutative:  true,
3433		clobberFlags: true,
3434		asm:          x86.AMULL,
3435		reg: regInfo{
3436			inputs: []inputInfo{
3437				{0, 1},   // AX
3438				{1, 255}, // AX CX DX BX SP BP SI DI
3439			},
3440			clobbers: 1, // AX
3441			outputs: []outputInfo{
3442				{0, 4}, // DX
3443			},
3444		},
3445	},
3446	{
3447		name:         "MULLQU",
3448		argLen:       2,
3449		commutative:  true,
3450		clobberFlags: true,
3451		asm:          x86.AMULL,
3452		reg: regInfo{
3453			inputs: []inputInfo{
3454				{0, 1},   // AX
3455				{1, 255}, // AX CX DX BX SP BP SI DI
3456			},
3457			outputs: []outputInfo{
3458				{0, 4}, // DX
3459				{1, 1}, // AX
3460			},
3461		},
3462	},
3463	{
3464		name:         "AVGLU",
3465		argLen:       2,
3466		commutative:  true,
3467		resultInArg0: true,
3468		clobberFlags: true,
3469		reg: regInfo{
3470			inputs: []inputInfo{
3471				{0, 239}, // AX CX DX BX BP SI DI
3472				{1, 239}, // AX CX DX BX BP SI DI
3473			},
3474			outputs: []outputInfo{
3475				{0, 239}, // AX CX DX BX BP SI DI
3476			},
3477		},
3478	},
3479	{
3480		name:         "DIVL",
3481		auxType:      auxBool,
3482		argLen:       2,
3483		clobberFlags: true,
3484		asm:          x86.AIDIVL,
3485		reg: regInfo{
3486			inputs: []inputInfo{
3487				{0, 1},   // AX
3488				{1, 251}, // AX CX BX SP BP SI DI
3489			},
3490			clobbers: 4, // DX
3491			outputs: []outputInfo{
3492				{0, 1}, // AX
3493			},
3494		},
3495	},
3496	{
3497		name:         "DIVW",
3498		auxType:      auxBool,
3499		argLen:       2,
3500		clobberFlags: true,
3501		asm:          x86.AIDIVW,
3502		reg: regInfo{
3503			inputs: []inputInfo{
3504				{0, 1},   // AX
3505				{1, 251}, // AX CX BX SP BP SI DI
3506			},
3507			clobbers: 4, // DX
3508			outputs: []outputInfo{
3509				{0, 1}, // AX
3510			},
3511		},
3512	},
3513	{
3514		name:         "DIVLU",
3515		argLen:       2,
3516		clobberFlags: true,
3517		asm:          x86.ADIVL,
3518		reg: regInfo{
3519			inputs: []inputInfo{
3520				{0, 1},   // AX
3521				{1, 251}, // AX CX BX SP BP SI DI
3522			},
3523			clobbers: 4, // DX
3524			outputs: []outputInfo{
3525				{0, 1}, // AX
3526			},
3527		},
3528	},
3529	{
3530		name:         "DIVWU",
3531		argLen:       2,
3532		clobberFlags: true,
3533		asm:          x86.ADIVW,
3534		reg: regInfo{
3535			inputs: []inputInfo{
3536				{0, 1},   // AX
3537				{1, 251}, // AX CX BX SP BP SI DI
3538			},
3539			clobbers: 4, // DX
3540			outputs: []outputInfo{
3541				{0, 1}, // AX
3542			},
3543		},
3544	},
3545	{
3546		name:         "MODL",
3547		auxType:      auxBool,
3548		argLen:       2,
3549		clobberFlags: true,
3550		asm:          x86.AIDIVL,
3551		reg: regInfo{
3552			inputs: []inputInfo{
3553				{0, 1},   // AX
3554				{1, 251}, // AX CX BX SP BP SI DI
3555			},
3556			clobbers: 1, // AX
3557			outputs: []outputInfo{
3558				{0, 4}, // DX
3559			},
3560		},
3561	},
3562	{
3563		name:         "MODW",
3564		auxType:      auxBool,
3565		argLen:       2,
3566		clobberFlags: true,
3567		asm:          x86.AIDIVW,
3568		reg: regInfo{
3569			inputs: []inputInfo{
3570				{0, 1},   // AX
3571				{1, 251}, // AX CX BX SP BP SI DI
3572			},
3573			clobbers: 1, // AX
3574			outputs: []outputInfo{
3575				{0, 4}, // DX
3576			},
3577		},
3578	},
3579	{
3580		name:         "MODLU",
3581		argLen:       2,
3582		clobberFlags: true,
3583		asm:          x86.ADIVL,
3584		reg: regInfo{
3585			inputs: []inputInfo{
3586				{0, 1},   // AX
3587				{1, 251}, // AX CX BX SP BP SI DI
3588			},
3589			clobbers: 1, // AX
3590			outputs: []outputInfo{
3591				{0, 4}, // DX
3592			},
3593		},
3594	},
3595	{
3596		name:         "MODWU",
3597		argLen:       2,
3598		clobberFlags: true,
3599		asm:          x86.ADIVW,
3600		reg: regInfo{
3601			inputs: []inputInfo{
3602				{0, 1},   // AX
3603				{1, 251}, // AX CX BX SP BP SI DI
3604			},
3605			clobbers: 1, // AX
3606			outputs: []outputInfo{
3607				{0, 4}, // DX
3608			},
3609		},
3610	},
3611	{
3612		name:         "ANDL",
3613		argLen:       2,
3614		commutative:  true,
3615		resultInArg0: true,
3616		clobberFlags: true,
3617		asm:          x86.AANDL,
3618		reg: regInfo{
3619			inputs: []inputInfo{
3620				{0, 239}, // AX CX DX BX BP SI DI
3621				{1, 239}, // AX CX DX BX BP SI DI
3622			},
3623			outputs: []outputInfo{
3624				{0, 239}, // AX CX DX BX BP SI DI
3625			},
3626		},
3627	},
3628	{
3629		name:         "ANDLconst",
3630		auxType:      auxInt32,
3631		argLen:       1,
3632		resultInArg0: true,
3633		clobberFlags: true,
3634		asm:          x86.AANDL,
3635		reg: regInfo{
3636			inputs: []inputInfo{
3637				{0, 239}, // AX CX DX BX BP SI DI
3638			},
3639			outputs: []outputInfo{
3640				{0, 239}, // AX CX DX BX BP SI DI
3641			},
3642		},
3643	},
3644	{
3645		name:         "ORL",
3646		argLen:       2,
3647		commutative:  true,
3648		resultInArg0: true,
3649		clobberFlags: true,
3650		asm:          x86.AORL,
3651		reg: regInfo{
3652			inputs: []inputInfo{
3653				{0, 239}, // AX CX DX BX BP SI DI
3654				{1, 239}, // AX CX DX BX BP SI DI
3655			},
3656			outputs: []outputInfo{
3657				{0, 239}, // AX CX DX BX BP SI DI
3658			},
3659		},
3660	},
3661	{
3662		name:         "ORLconst",
3663		auxType:      auxInt32,
3664		argLen:       1,
3665		resultInArg0: true,
3666		clobberFlags: true,
3667		asm:          x86.AORL,
3668		reg: regInfo{
3669			inputs: []inputInfo{
3670				{0, 239}, // AX CX DX BX BP SI DI
3671			},
3672			outputs: []outputInfo{
3673				{0, 239}, // AX CX DX BX BP SI DI
3674			},
3675		},
3676	},
3677	{
3678		name:         "XORL",
3679		argLen:       2,
3680		commutative:  true,
3681		resultInArg0: true,
3682		clobberFlags: true,
3683		asm:          x86.AXORL,
3684		reg: regInfo{
3685			inputs: []inputInfo{
3686				{0, 239}, // AX CX DX BX BP SI DI
3687				{1, 239}, // AX CX DX BX BP SI DI
3688			},
3689			outputs: []outputInfo{
3690				{0, 239}, // AX CX DX BX BP SI DI
3691			},
3692		},
3693	},
3694	{
3695		name:         "XORLconst",
3696		auxType:      auxInt32,
3697		argLen:       1,
3698		resultInArg0: true,
3699		clobberFlags: true,
3700		asm:          x86.AXORL,
3701		reg: regInfo{
3702			inputs: []inputInfo{
3703				{0, 239}, // AX CX DX BX BP SI DI
3704			},
3705			outputs: []outputInfo{
3706				{0, 239}, // AX CX DX BX BP SI DI
3707			},
3708		},
3709	},
3710	{
3711		name:   "CMPL",
3712		argLen: 2,
3713		asm:    x86.ACMPL,
3714		reg: regInfo{
3715			inputs: []inputInfo{
3716				{0, 255}, // AX CX DX BX SP BP SI DI
3717				{1, 255}, // AX CX DX BX SP BP SI DI
3718			},
3719		},
3720	},
3721	{
3722		name:   "CMPW",
3723		argLen: 2,
3724		asm:    x86.ACMPW,
3725		reg: regInfo{
3726			inputs: []inputInfo{
3727				{0, 255}, // AX CX DX BX SP BP SI DI
3728				{1, 255}, // AX CX DX BX SP BP SI DI
3729			},
3730		},
3731	},
3732	{
3733		name:   "CMPB",
3734		argLen: 2,
3735		asm:    x86.ACMPB,
3736		reg: regInfo{
3737			inputs: []inputInfo{
3738				{0, 255}, // AX CX DX BX SP BP SI DI
3739				{1, 255}, // AX CX DX BX SP BP SI DI
3740			},
3741		},
3742	},
3743	{
3744		name:    "CMPLconst",
3745		auxType: auxInt32,
3746		argLen:  1,
3747		asm:     x86.ACMPL,
3748		reg: regInfo{
3749			inputs: []inputInfo{
3750				{0, 255}, // AX CX DX BX SP BP SI DI
3751			},
3752		},
3753	},
3754	{
3755		name:    "CMPWconst",
3756		auxType: auxInt16,
3757		argLen:  1,
3758		asm:     x86.ACMPW,
3759		reg: regInfo{
3760			inputs: []inputInfo{
3761				{0, 255}, // AX CX DX BX SP BP SI DI
3762			},
3763		},
3764	},
3765	{
3766		name:    "CMPBconst",
3767		auxType: auxInt8,
3768		argLen:  1,
3769		asm:     x86.ACMPB,
3770		reg: regInfo{
3771			inputs: []inputInfo{
3772				{0, 255}, // AX CX DX BX SP BP SI DI
3773			},
3774		},
3775	},
3776	{
3777		name:           "CMPLload",
3778		auxType:        auxSymOff,
3779		argLen:         3,
3780		faultOnNilArg0: true,
3781		symEffect:      SymRead,
3782		asm:            x86.ACMPL,
3783		reg: regInfo{
3784			inputs: []inputInfo{
3785				{1, 255},   // AX CX DX BX SP BP SI DI
3786				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3787			},
3788		},
3789	},
3790	{
3791		name:           "CMPWload",
3792		auxType:        auxSymOff,
3793		argLen:         3,
3794		faultOnNilArg0: true,
3795		symEffect:      SymRead,
3796		asm:            x86.ACMPW,
3797		reg: regInfo{
3798			inputs: []inputInfo{
3799				{1, 255},   // AX CX DX BX SP BP SI DI
3800				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3801			},
3802		},
3803	},
3804	{
3805		name:           "CMPBload",
3806		auxType:        auxSymOff,
3807		argLen:         3,
3808		faultOnNilArg0: true,
3809		symEffect:      SymRead,
3810		asm:            x86.ACMPB,
3811		reg: regInfo{
3812			inputs: []inputInfo{
3813				{1, 255},   // AX CX DX BX SP BP SI DI
3814				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3815			},
3816		},
3817	},
3818	{
3819		name:           "CMPLconstload",
3820		auxType:        auxSymValAndOff,
3821		argLen:         2,
3822		faultOnNilArg0: true,
3823		symEffect:      SymRead,
3824		asm:            x86.ACMPL,
3825		reg: regInfo{
3826			inputs: []inputInfo{
3827				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3828			},
3829		},
3830	},
3831	{
3832		name:           "CMPWconstload",
3833		auxType:        auxSymValAndOff,
3834		argLen:         2,
3835		faultOnNilArg0: true,
3836		symEffect:      SymRead,
3837		asm:            x86.ACMPW,
3838		reg: regInfo{
3839			inputs: []inputInfo{
3840				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3841			},
3842		},
3843	},
3844	{
3845		name:           "CMPBconstload",
3846		auxType:        auxSymValAndOff,
3847		argLen:         2,
3848		faultOnNilArg0: true,
3849		symEffect:      SymRead,
3850		asm:            x86.ACMPB,
3851		reg: regInfo{
3852			inputs: []inputInfo{
3853				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3854			},
3855		},
3856	},
3857	{
3858		name:        "UCOMISS",
3859		argLen:      2,
3860		usesScratch: true,
3861		asm:         x86.AUCOMISS,
3862		reg: regInfo{
3863			inputs: []inputInfo{
3864				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3865				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3866			},
3867		},
3868	},
3869	{
3870		name:        "UCOMISD",
3871		argLen:      2,
3872		usesScratch: true,
3873		asm:         x86.AUCOMISD,
3874		reg: regInfo{
3875			inputs: []inputInfo{
3876				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3877				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3878			},
3879		},
3880	},
3881	{
3882		name:        "TESTL",
3883		argLen:      2,
3884		commutative: true,
3885		asm:         x86.ATESTL,
3886		reg: regInfo{
3887			inputs: []inputInfo{
3888				{0, 255}, // AX CX DX BX SP BP SI DI
3889				{1, 255}, // AX CX DX BX SP BP SI DI
3890			},
3891		},
3892	},
3893	{
3894		name:        "TESTW",
3895		argLen:      2,
3896		commutative: true,
3897		asm:         x86.ATESTW,
3898		reg: regInfo{
3899			inputs: []inputInfo{
3900				{0, 255}, // AX CX DX BX SP BP SI DI
3901				{1, 255}, // AX CX DX BX SP BP SI DI
3902			},
3903		},
3904	},
3905	{
3906		name:        "TESTB",
3907		argLen:      2,
3908		commutative: true,
3909		asm:         x86.ATESTB,
3910		reg: regInfo{
3911			inputs: []inputInfo{
3912				{0, 255}, // AX CX DX BX SP BP SI DI
3913				{1, 255}, // AX CX DX BX SP BP SI DI
3914			},
3915		},
3916	},
3917	{
3918		name:    "TESTLconst",
3919		auxType: auxInt32,
3920		argLen:  1,
3921		asm:     x86.ATESTL,
3922		reg: regInfo{
3923			inputs: []inputInfo{
3924				{0, 255}, // AX CX DX BX SP BP SI DI
3925			},
3926		},
3927	},
3928	{
3929		name:    "TESTWconst",
3930		auxType: auxInt16,
3931		argLen:  1,
3932		asm:     x86.ATESTW,
3933		reg: regInfo{
3934			inputs: []inputInfo{
3935				{0, 255}, // AX CX DX BX SP BP SI DI
3936			},
3937		},
3938	},
3939	{
3940		name:    "TESTBconst",
3941		auxType: auxInt8,
3942		argLen:  1,
3943		asm:     x86.ATESTB,
3944		reg: regInfo{
3945			inputs: []inputInfo{
3946				{0, 255}, // AX CX DX BX SP BP SI DI
3947			},
3948		},
3949	},
3950	{
3951		name:         "SHLL",
3952		argLen:       2,
3953		resultInArg0: true,
3954		clobberFlags: true,
3955		asm:          x86.ASHLL,
3956		reg: regInfo{
3957			inputs: []inputInfo{
3958				{1, 2},   // CX
3959				{0, 239}, // AX CX DX BX BP SI DI
3960			},
3961			outputs: []outputInfo{
3962				{0, 239}, // AX CX DX BX BP SI DI
3963			},
3964		},
3965	},
3966	{
3967		name:         "SHLLconst",
3968		auxType:      auxInt32,
3969		argLen:       1,
3970		resultInArg0: true,
3971		clobberFlags: true,
3972		asm:          x86.ASHLL,
3973		reg: regInfo{
3974			inputs: []inputInfo{
3975				{0, 239}, // AX CX DX BX BP SI DI
3976			},
3977			outputs: []outputInfo{
3978				{0, 239}, // AX CX DX BX BP SI DI
3979			},
3980		},
3981	},
3982	{
3983		name:         "SHRL",
3984		argLen:       2,
3985		resultInArg0: true,
3986		clobberFlags: true,
3987		asm:          x86.ASHRL,
3988		reg: regInfo{
3989			inputs: []inputInfo{
3990				{1, 2},   // CX
3991				{0, 239}, // AX CX DX BX BP SI DI
3992			},
3993			outputs: []outputInfo{
3994				{0, 239}, // AX CX DX BX BP SI DI
3995			},
3996		},
3997	},
3998	{
3999		name:         "SHRW",
4000		argLen:       2,
4001		resultInArg0: true,
4002		clobberFlags: true,
4003		asm:          x86.ASHRW,
4004		reg: regInfo{
4005			inputs: []inputInfo{
4006				{1, 2},   // CX
4007				{0, 239}, // AX CX DX BX BP SI DI
4008			},
4009			outputs: []outputInfo{
4010				{0, 239}, // AX CX DX BX BP SI DI
4011			},
4012		},
4013	},
4014	{
4015		name:         "SHRB",
4016		argLen:       2,
4017		resultInArg0: true,
4018		clobberFlags: true,
4019		asm:          x86.ASHRB,
4020		reg: regInfo{
4021			inputs: []inputInfo{
4022				{1, 2},   // CX
4023				{0, 239}, // AX CX DX BX BP SI DI
4024			},
4025			outputs: []outputInfo{
4026				{0, 239}, // AX CX DX BX BP SI DI
4027			},
4028		},
4029	},
4030	{
4031		name:         "SHRLconst",
4032		auxType:      auxInt32,
4033		argLen:       1,
4034		resultInArg0: true,
4035		clobberFlags: true,
4036		asm:          x86.ASHRL,
4037		reg: regInfo{
4038			inputs: []inputInfo{
4039				{0, 239}, // AX CX DX BX BP SI DI
4040			},
4041			outputs: []outputInfo{
4042				{0, 239}, // AX CX DX BX BP SI DI
4043			},
4044		},
4045	},
4046	{
4047		name:         "SHRWconst",
4048		auxType:      auxInt16,
4049		argLen:       1,
4050		resultInArg0: true,
4051		clobberFlags: true,
4052		asm:          x86.ASHRW,
4053		reg: regInfo{
4054			inputs: []inputInfo{
4055				{0, 239}, // AX CX DX BX BP SI DI
4056			},
4057			outputs: []outputInfo{
4058				{0, 239}, // AX CX DX BX BP SI DI
4059			},
4060		},
4061	},
4062	{
4063		name:         "SHRBconst",
4064		auxType:      auxInt8,
4065		argLen:       1,
4066		resultInArg0: true,
4067		clobberFlags: true,
4068		asm:          x86.ASHRB,
4069		reg: regInfo{
4070			inputs: []inputInfo{
4071				{0, 239}, // AX CX DX BX BP SI DI
4072			},
4073			outputs: []outputInfo{
4074				{0, 239}, // AX CX DX BX BP SI DI
4075			},
4076		},
4077	},
4078	{
4079		name:         "SARL",
4080		argLen:       2,
4081		resultInArg0: true,
4082		clobberFlags: true,
4083		asm:          x86.ASARL,
4084		reg: regInfo{
4085			inputs: []inputInfo{
4086				{1, 2},   // CX
4087				{0, 239}, // AX CX DX BX BP SI DI
4088			},
4089			outputs: []outputInfo{
4090				{0, 239}, // AX CX DX BX BP SI DI
4091			},
4092		},
4093	},
4094	{
4095		name:         "SARW",
4096		argLen:       2,
4097		resultInArg0: true,
4098		clobberFlags: true,
4099		asm:          x86.ASARW,
4100		reg: regInfo{
4101			inputs: []inputInfo{
4102				{1, 2},   // CX
4103				{0, 239}, // AX CX DX BX BP SI DI
4104			},
4105			outputs: []outputInfo{
4106				{0, 239}, // AX CX DX BX BP SI DI
4107			},
4108		},
4109	},
4110	{
4111		name:         "SARB",
4112		argLen:       2,
4113		resultInArg0: true,
4114		clobberFlags: true,
4115		asm:          x86.ASARB,
4116		reg: regInfo{
4117			inputs: []inputInfo{
4118				{1, 2},   // CX
4119				{0, 239}, // AX CX DX BX BP SI DI
4120			},
4121			outputs: []outputInfo{
4122				{0, 239}, // AX CX DX BX BP SI DI
4123			},
4124		},
4125	},
4126	{
4127		name:         "SARLconst",
4128		auxType:      auxInt32,
4129		argLen:       1,
4130		resultInArg0: true,
4131		clobberFlags: true,
4132		asm:          x86.ASARL,
4133		reg: regInfo{
4134			inputs: []inputInfo{
4135				{0, 239}, // AX CX DX BX BP SI DI
4136			},
4137			outputs: []outputInfo{
4138				{0, 239}, // AX CX DX BX BP SI DI
4139			},
4140		},
4141	},
4142	{
4143		name:         "SARWconst",
4144		auxType:      auxInt16,
4145		argLen:       1,
4146		resultInArg0: true,
4147		clobberFlags: true,
4148		asm:          x86.ASARW,
4149		reg: regInfo{
4150			inputs: []inputInfo{
4151				{0, 239}, // AX CX DX BX BP SI DI
4152			},
4153			outputs: []outputInfo{
4154				{0, 239}, // AX CX DX BX BP SI DI
4155			},
4156		},
4157	},
4158	{
4159		name:         "SARBconst",
4160		auxType:      auxInt8,
4161		argLen:       1,
4162		resultInArg0: true,
4163		clobberFlags: true,
4164		asm:          x86.ASARB,
4165		reg: regInfo{
4166			inputs: []inputInfo{
4167				{0, 239}, // AX CX DX BX BP SI DI
4168			},
4169			outputs: []outputInfo{
4170				{0, 239}, // AX CX DX BX BP SI DI
4171			},
4172		},
4173	},
4174	{
4175		name:         "ROLLconst",
4176		auxType:      auxInt32,
4177		argLen:       1,
4178		resultInArg0: true,
4179		clobberFlags: true,
4180		asm:          x86.AROLL,
4181		reg: regInfo{
4182			inputs: []inputInfo{
4183				{0, 239}, // AX CX DX BX BP SI DI
4184			},
4185			outputs: []outputInfo{
4186				{0, 239}, // AX CX DX BX BP SI DI
4187			},
4188		},
4189	},
4190	{
4191		name:         "ROLWconst",
4192		auxType:      auxInt16,
4193		argLen:       1,
4194		resultInArg0: true,
4195		clobberFlags: true,
4196		asm:          x86.AROLW,
4197		reg: regInfo{
4198			inputs: []inputInfo{
4199				{0, 239}, // AX CX DX BX BP SI DI
4200			},
4201			outputs: []outputInfo{
4202				{0, 239}, // AX CX DX BX BP SI DI
4203			},
4204		},
4205	},
4206	{
4207		name:         "ROLBconst",
4208		auxType:      auxInt8,
4209		argLen:       1,
4210		resultInArg0: true,
4211		clobberFlags: true,
4212		asm:          x86.AROLB,
4213		reg: regInfo{
4214			inputs: []inputInfo{
4215				{0, 239}, // AX CX DX BX BP SI DI
4216			},
4217			outputs: []outputInfo{
4218				{0, 239}, // AX CX DX BX BP SI DI
4219			},
4220		},
4221	},
4222	{
4223		name:           "ADDLload",
4224		auxType:        auxSymOff,
4225		argLen:         3,
4226		resultInArg0:   true,
4227		clobberFlags:   true,
4228		faultOnNilArg1: true,
4229		symEffect:      SymRead,
4230		asm:            x86.AADDL,
4231		reg: regInfo{
4232			inputs: []inputInfo{
4233				{0, 239},   // AX CX DX BX BP SI DI
4234				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4235			},
4236			outputs: []outputInfo{
4237				{0, 239}, // AX CX DX BX BP SI DI
4238			},
4239		},
4240	},
4241	{
4242		name:           "SUBLload",
4243		auxType:        auxSymOff,
4244		argLen:         3,
4245		resultInArg0:   true,
4246		clobberFlags:   true,
4247		faultOnNilArg1: true,
4248		symEffect:      SymRead,
4249		asm:            x86.ASUBL,
4250		reg: regInfo{
4251			inputs: []inputInfo{
4252				{0, 239},   // AX CX DX BX BP SI DI
4253				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4254			},
4255			outputs: []outputInfo{
4256				{0, 239}, // AX CX DX BX BP SI DI
4257			},
4258		},
4259	},
4260	{
4261		name:           "MULLload",
4262		auxType:        auxSymOff,
4263		argLen:         3,
4264		resultInArg0:   true,
4265		clobberFlags:   true,
4266		faultOnNilArg1: true,
4267		symEffect:      SymRead,
4268		asm:            x86.AIMULL,
4269		reg: regInfo{
4270			inputs: []inputInfo{
4271				{0, 239},   // AX CX DX BX BP SI DI
4272				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4273			},
4274			outputs: []outputInfo{
4275				{0, 239}, // AX CX DX BX BP SI DI
4276			},
4277		},
4278	},
4279	{
4280		name:           "ANDLload",
4281		auxType:        auxSymOff,
4282		argLen:         3,
4283		resultInArg0:   true,
4284		clobberFlags:   true,
4285		faultOnNilArg1: true,
4286		symEffect:      SymRead,
4287		asm:            x86.AANDL,
4288		reg: regInfo{
4289			inputs: []inputInfo{
4290				{0, 239},   // AX CX DX BX BP SI DI
4291				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4292			},
4293			outputs: []outputInfo{
4294				{0, 239}, // AX CX DX BX BP SI DI
4295			},
4296		},
4297	},
4298	{
4299		name:           "ORLload",
4300		auxType:        auxSymOff,
4301		argLen:         3,
4302		resultInArg0:   true,
4303		clobberFlags:   true,
4304		faultOnNilArg1: true,
4305		symEffect:      SymRead,
4306		asm:            x86.AORL,
4307		reg: regInfo{
4308			inputs: []inputInfo{
4309				{0, 239},   // AX CX DX BX BP SI DI
4310				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4311			},
4312			outputs: []outputInfo{
4313				{0, 239}, // AX CX DX BX BP SI DI
4314			},
4315		},
4316	},
4317	{
4318		name:           "XORLload",
4319		auxType:        auxSymOff,
4320		argLen:         3,
4321		resultInArg0:   true,
4322		clobberFlags:   true,
4323		faultOnNilArg1: true,
4324		symEffect:      SymRead,
4325		asm:            x86.AXORL,
4326		reg: regInfo{
4327			inputs: []inputInfo{
4328				{0, 239},   // AX CX DX BX BP SI DI
4329				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4330			},
4331			outputs: []outputInfo{
4332				{0, 239}, // AX CX DX BX BP SI DI
4333			},
4334		},
4335	},
4336	{
4337		name:           "ADDLloadidx4",
4338		auxType:        auxSymOff,
4339		argLen:         4,
4340		resultInArg0:   true,
4341		clobberFlags:   true,
4342		faultOnNilArg1: true,
4343		symEffect:      SymRead,
4344		asm:            x86.AADDL,
4345		reg: regInfo{
4346			inputs: []inputInfo{
4347				{0, 239},   // AX CX DX BX BP SI DI
4348				{2, 255},   // AX CX DX BX SP BP SI DI
4349				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4350			},
4351			outputs: []outputInfo{
4352				{0, 239}, // AX CX DX BX BP SI DI
4353			},
4354		},
4355	},
4356	{
4357		name:           "SUBLloadidx4",
4358		auxType:        auxSymOff,
4359		argLen:         4,
4360		resultInArg0:   true,
4361		clobberFlags:   true,
4362		faultOnNilArg1: true,
4363		symEffect:      SymRead,
4364		asm:            x86.ASUBL,
4365		reg: regInfo{
4366			inputs: []inputInfo{
4367				{0, 239},   // AX CX DX BX BP SI DI
4368				{2, 255},   // AX CX DX BX SP BP SI DI
4369				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4370			},
4371			outputs: []outputInfo{
4372				{0, 239}, // AX CX DX BX BP SI DI
4373			},
4374		},
4375	},
4376	{
4377		name:           "MULLloadidx4",
4378		auxType:        auxSymOff,
4379		argLen:         4,
4380		resultInArg0:   true,
4381		clobberFlags:   true,
4382		faultOnNilArg1: true,
4383		symEffect:      SymRead,
4384		asm:            x86.AIMULL,
4385		reg: regInfo{
4386			inputs: []inputInfo{
4387				{0, 239},   // AX CX DX BX BP SI DI
4388				{2, 255},   // AX CX DX BX SP BP SI DI
4389				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4390			},
4391			outputs: []outputInfo{
4392				{0, 239}, // AX CX DX BX BP SI DI
4393			},
4394		},
4395	},
4396	{
4397		name:           "ANDLloadidx4",
4398		auxType:        auxSymOff,
4399		argLen:         4,
4400		resultInArg0:   true,
4401		clobberFlags:   true,
4402		faultOnNilArg1: true,
4403		symEffect:      SymRead,
4404		asm:            x86.AANDL,
4405		reg: regInfo{
4406			inputs: []inputInfo{
4407				{0, 239},   // AX CX DX BX BP SI DI
4408				{2, 255},   // AX CX DX BX SP BP SI DI
4409				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4410			},
4411			outputs: []outputInfo{
4412				{0, 239}, // AX CX DX BX BP SI DI
4413			},
4414		},
4415	},
4416	{
4417		name:           "ORLloadidx4",
4418		auxType:        auxSymOff,
4419		argLen:         4,
4420		resultInArg0:   true,
4421		clobberFlags:   true,
4422		faultOnNilArg1: true,
4423		symEffect:      SymRead,
4424		asm:            x86.AORL,
4425		reg: regInfo{
4426			inputs: []inputInfo{
4427				{0, 239},   // AX CX DX BX BP SI DI
4428				{2, 255},   // AX CX DX BX SP BP SI DI
4429				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4430			},
4431			outputs: []outputInfo{
4432				{0, 239}, // AX CX DX BX BP SI DI
4433			},
4434		},
4435	},
4436	{
4437		name:           "XORLloadidx4",
4438		auxType:        auxSymOff,
4439		argLen:         4,
4440		resultInArg0:   true,
4441		clobberFlags:   true,
4442		faultOnNilArg1: true,
4443		symEffect:      SymRead,
4444		asm:            x86.AXORL,
4445		reg: regInfo{
4446			inputs: []inputInfo{
4447				{0, 239},   // AX CX DX BX BP SI DI
4448				{2, 255},   // AX CX DX BX SP BP SI DI
4449				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4450			},
4451			outputs: []outputInfo{
4452				{0, 239}, // AX CX DX BX BP SI DI
4453			},
4454		},
4455	},
4456	{
4457		name:         "NEGL",
4458		argLen:       1,
4459		resultInArg0: true,
4460		clobberFlags: true,
4461		asm:          x86.ANEGL,
4462		reg: regInfo{
4463			inputs: []inputInfo{
4464				{0, 239}, // AX CX DX BX BP SI DI
4465			},
4466			outputs: []outputInfo{
4467				{0, 239}, // AX CX DX BX BP SI DI
4468			},
4469		},
4470	},
4471	{
4472		name:         "NOTL",
4473		argLen:       1,
4474		resultInArg0: true,
4475		clobberFlags: true,
4476		asm:          x86.ANOTL,
4477		reg: regInfo{
4478			inputs: []inputInfo{
4479				{0, 239}, // AX CX DX BX BP SI DI
4480			},
4481			outputs: []outputInfo{
4482				{0, 239}, // AX CX DX BX BP SI DI
4483			},
4484		},
4485	},
4486	{
4487		name:         "BSFL",
4488		argLen:       1,
4489		clobberFlags: true,
4490		asm:          x86.ABSFL,
4491		reg: regInfo{
4492			inputs: []inputInfo{
4493				{0, 239}, // AX CX DX BX BP SI DI
4494			},
4495			outputs: []outputInfo{
4496				{0, 239}, // AX CX DX BX BP SI DI
4497			},
4498		},
4499	},
4500	{
4501		name:         "BSFW",
4502		argLen:       1,
4503		clobberFlags: true,
4504		asm:          x86.ABSFW,
4505		reg: regInfo{
4506			inputs: []inputInfo{
4507				{0, 239}, // AX CX DX BX BP SI DI
4508			},
4509			outputs: []outputInfo{
4510				{0, 239}, // AX CX DX BX BP SI DI
4511			},
4512		},
4513	},
4514	{
4515		name:         "BSRL",
4516		argLen:       1,
4517		clobberFlags: true,
4518		asm:          x86.ABSRL,
4519		reg: regInfo{
4520			inputs: []inputInfo{
4521				{0, 239}, // AX CX DX BX BP SI DI
4522			},
4523			outputs: []outputInfo{
4524				{0, 239}, // AX CX DX BX BP SI DI
4525			},
4526		},
4527	},
4528	{
4529		name:         "BSRW",
4530		argLen:       1,
4531		clobberFlags: true,
4532		asm:          x86.ABSRW,
4533		reg: regInfo{
4534			inputs: []inputInfo{
4535				{0, 239}, // AX CX DX BX BP SI DI
4536			},
4537			outputs: []outputInfo{
4538				{0, 239}, // AX CX DX BX BP SI DI
4539			},
4540		},
4541	},
4542	{
4543		name:         "BSWAPL",
4544		argLen:       1,
4545		resultInArg0: true,
4546		clobberFlags: true,
4547		asm:          x86.ABSWAPL,
4548		reg: regInfo{
4549			inputs: []inputInfo{
4550				{0, 239}, // AX CX DX BX BP SI DI
4551			},
4552			outputs: []outputInfo{
4553				{0, 239}, // AX CX DX BX BP SI DI
4554			},
4555		},
4556	},
4557	{
4558		name:   "SQRTSD",
4559		argLen: 1,
4560		asm:    x86.ASQRTSD,
4561		reg: regInfo{
4562			inputs: []inputInfo{
4563				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4564			},
4565			outputs: []outputInfo{
4566				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4567			},
4568		},
4569	},
4570	{
4571		name:   "SBBLcarrymask",
4572		argLen: 1,
4573		asm:    x86.ASBBL,
4574		reg: regInfo{
4575			outputs: []outputInfo{
4576				{0, 239}, // AX CX DX BX BP SI DI
4577			},
4578		},
4579	},
4580	{
4581		name:   "SETEQ",
4582		argLen: 1,
4583		asm:    x86.ASETEQ,
4584		reg: regInfo{
4585			outputs: []outputInfo{
4586				{0, 239}, // AX CX DX BX BP SI DI
4587			},
4588		},
4589	},
4590	{
4591		name:   "SETNE",
4592		argLen: 1,
4593		asm:    x86.ASETNE,
4594		reg: regInfo{
4595			outputs: []outputInfo{
4596				{0, 239}, // AX CX DX BX BP SI DI
4597			},
4598		},
4599	},
4600	{
4601		name:   "SETL",
4602		argLen: 1,
4603		asm:    x86.ASETLT,
4604		reg: regInfo{
4605			outputs: []outputInfo{
4606				{0, 239}, // AX CX DX BX BP SI DI
4607			},
4608		},
4609	},
4610	{
4611		name:   "SETLE",
4612		argLen: 1,
4613		asm:    x86.ASETLE,
4614		reg: regInfo{
4615			outputs: []outputInfo{
4616				{0, 239}, // AX CX DX BX BP SI DI
4617			},
4618		},
4619	},
4620	{
4621		name:   "SETG",
4622		argLen: 1,
4623		asm:    x86.ASETGT,
4624		reg: regInfo{
4625			outputs: []outputInfo{
4626				{0, 239}, // AX CX DX BX BP SI DI
4627			},
4628		},
4629	},
4630	{
4631		name:   "SETGE",
4632		argLen: 1,
4633		asm:    x86.ASETGE,
4634		reg: regInfo{
4635			outputs: []outputInfo{
4636				{0, 239}, // AX CX DX BX BP SI DI
4637			},
4638		},
4639	},
4640	{
4641		name:   "SETB",
4642		argLen: 1,
4643		asm:    x86.ASETCS,
4644		reg: regInfo{
4645			outputs: []outputInfo{
4646				{0, 239}, // AX CX DX BX BP SI DI
4647			},
4648		},
4649	},
4650	{
4651		name:   "SETBE",
4652		argLen: 1,
4653		asm:    x86.ASETLS,
4654		reg: regInfo{
4655			outputs: []outputInfo{
4656				{0, 239}, // AX CX DX BX BP SI DI
4657			},
4658		},
4659	},
4660	{
4661		name:   "SETA",
4662		argLen: 1,
4663		asm:    x86.ASETHI,
4664		reg: regInfo{
4665			outputs: []outputInfo{
4666				{0, 239}, // AX CX DX BX BP SI DI
4667			},
4668		},
4669	},
4670	{
4671		name:   "SETAE",
4672		argLen: 1,
4673		asm:    x86.ASETCC,
4674		reg: regInfo{
4675			outputs: []outputInfo{
4676				{0, 239}, // AX CX DX BX BP SI DI
4677			},
4678		},
4679	},
4680	{
4681		name:   "SETO",
4682		argLen: 1,
4683		asm:    x86.ASETOS,
4684		reg: regInfo{
4685			outputs: []outputInfo{
4686				{0, 239}, // AX CX DX BX BP SI DI
4687			},
4688		},
4689	},
4690	{
4691		name:         "SETEQF",
4692		argLen:       1,
4693		clobberFlags: true,
4694		asm:          x86.ASETEQ,
4695		reg: regInfo{
4696			clobbers: 1, // AX
4697			outputs: []outputInfo{
4698				{0, 238}, // CX DX BX BP SI DI
4699			},
4700		},
4701	},
4702	{
4703		name:         "SETNEF",
4704		argLen:       1,
4705		clobberFlags: true,
4706		asm:          x86.ASETNE,
4707		reg: regInfo{
4708			clobbers: 1, // AX
4709			outputs: []outputInfo{
4710				{0, 238}, // CX DX BX BP SI DI
4711			},
4712		},
4713	},
4714	{
4715		name:   "SETORD",
4716		argLen: 1,
4717		asm:    x86.ASETPC,
4718		reg: regInfo{
4719			outputs: []outputInfo{
4720				{0, 239}, // AX CX DX BX BP SI DI
4721			},
4722		},
4723	},
4724	{
4725		name:   "SETNAN",
4726		argLen: 1,
4727		asm:    x86.ASETPS,
4728		reg: regInfo{
4729			outputs: []outputInfo{
4730				{0, 239}, // AX CX DX BX BP SI DI
4731			},
4732		},
4733	},
4734	{
4735		name:   "SETGF",
4736		argLen: 1,
4737		asm:    x86.ASETHI,
4738		reg: regInfo{
4739			outputs: []outputInfo{
4740				{0, 239}, // AX CX DX BX BP SI DI
4741			},
4742		},
4743	},
4744	{
4745		name:   "SETGEF",
4746		argLen: 1,
4747		asm:    x86.ASETCC,
4748		reg: regInfo{
4749			outputs: []outputInfo{
4750				{0, 239}, // AX CX DX BX BP SI DI
4751			},
4752		},
4753	},
4754	{
4755		name:   "MOVBLSX",
4756		argLen: 1,
4757		asm:    x86.AMOVBLSX,
4758		reg: regInfo{
4759			inputs: []inputInfo{
4760				{0, 239}, // AX CX DX BX BP SI DI
4761			},
4762			outputs: []outputInfo{
4763				{0, 239}, // AX CX DX BX BP SI DI
4764			},
4765		},
4766	},
4767	{
4768		name:   "MOVBLZX",
4769		argLen: 1,
4770		asm:    x86.AMOVBLZX,
4771		reg: regInfo{
4772			inputs: []inputInfo{
4773				{0, 239}, // AX CX DX BX BP SI DI
4774			},
4775			outputs: []outputInfo{
4776				{0, 239}, // AX CX DX BX BP SI DI
4777			},
4778		},
4779	},
4780	{
4781		name:   "MOVWLSX",
4782		argLen: 1,
4783		asm:    x86.AMOVWLSX,
4784		reg: regInfo{
4785			inputs: []inputInfo{
4786				{0, 239}, // AX CX DX BX BP SI DI
4787			},
4788			outputs: []outputInfo{
4789				{0, 239}, // AX CX DX BX BP SI DI
4790			},
4791		},
4792	},
4793	{
4794		name:   "MOVWLZX",
4795		argLen: 1,
4796		asm:    x86.AMOVWLZX,
4797		reg: regInfo{
4798			inputs: []inputInfo{
4799				{0, 239}, // AX CX DX BX BP SI DI
4800			},
4801			outputs: []outputInfo{
4802				{0, 239}, // AX CX DX BX BP SI DI
4803			},
4804		},
4805	},
4806	{
4807		name:              "MOVLconst",
4808		auxType:           auxInt32,
4809		argLen:            0,
4810		rematerializeable: true,
4811		asm:               x86.AMOVL,
4812		reg: regInfo{
4813			outputs: []outputInfo{
4814				{0, 239}, // AX CX DX BX BP SI DI
4815			},
4816		},
4817	},
4818	{
4819		name:        "CVTTSD2SL",
4820		argLen:      1,
4821		usesScratch: true,
4822		asm:         x86.ACVTTSD2SL,
4823		reg: regInfo{
4824			inputs: []inputInfo{
4825				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4826			},
4827			outputs: []outputInfo{
4828				{0, 239}, // AX CX DX BX BP SI DI
4829			},
4830		},
4831	},
4832	{
4833		name:        "CVTTSS2SL",
4834		argLen:      1,
4835		usesScratch: true,
4836		asm:         x86.ACVTTSS2SL,
4837		reg: regInfo{
4838			inputs: []inputInfo{
4839				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4840			},
4841			outputs: []outputInfo{
4842				{0, 239}, // AX CX DX BX BP SI DI
4843			},
4844		},
4845	},
4846	{
4847		name:        "CVTSL2SS",
4848		argLen:      1,
4849		usesScratch: true,
4850		asm:         x86.ACVTSL2SS,
4851		reg: regInfo{
4852			inputs: []inputInfo{
4853				{0, 239}, // AX CX DX BX BP SI DI
4854			},
4855			outputs: []outputInfo{
4856				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4857			},
4858		},
4859	},
4860	{
4861		name:        "CVTSL2SD",
4862		argLen:      1,
4863		usesScratch: true,
4864		asm:         x86.ACVTSL2SD,
4865		reg: regInfo{
4866			inputs: []inputInfo{
4867				{0, 239}, // AX CX DX BX BP SI DI
4868			},
4869			outputs: []outputInfo{
4870				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4871			},
4872		},
4873	},
4874	{
4875		name:        "CVTSD2SS",
4876		argLen:      1,
4877		usesScratch: true,
4878		asm:         x86.ACVTSD2SS,
4879		reg: regInfo{
4880			inputs: []inputInfo{
4881				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4882			},
4883			outputs: []outputInfo{
4884				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4885			},
4886		},
4887	},
4888	{
4889		name:   "CVTSS2SD",
4890		argLen: 1,
4891		asm:    x86.ACVTSS2SD,
4892		reg: regInfo{
4893			inputs: []inputInfo{
4894				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4895			},
4896			outputs: []outputInfo{
4897				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4898			},
4899		},
4900	},
4901	{
4902		name:         "PXOR",
4903		argLen:       2,
4904		commutative:  true,
4905		resultInArg0: true,
4906		asm:          x86.APXOR,
4907		reg: regInfo{
4908			inputs: []inputInfo{
4909				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4910				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4911			},
4912			outputs: []outputInfo{
4913				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4914			},
4915		},
4916	},
4917	{
4918		name:              "LEAL",
4919		auxType:           auxSymOff,
4920		argLen:            1,
4921		rematerializeable: true,
4922		symEffect:         SymAddr,
4923		reg: regInfo{
4924			inputs: []inputInfo{
4925				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4926			},
4927			outputs: []outputInfo{
4928				{0, 239}, // AX CX DX BX BP SI DI
4929			},
4930		},
4931	},
4932	{
4933		name:        "LEAL1",
4934		auxType:     auxSymOff,
4935		argLen:      2,
4936		commutative: true,
4937		symEffect:   SymAddr,
4938		reg: regInfo{
4939			inputs: []inputInfo{
4940				{1, 255},   // AX CX DX BX SP BP SI DI
4941				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4942			},
4943			outputs: []outputInfo{
4944				{0, 239}, // AX CX DX BX BP SI DI
4945			},
4946		},
4947	},
4948	{
4949		name:      "LEAL2",
4950		auxType:   auxSymOff,
4951		argLen:    2,
4952		symEffect: SymAddr,
4953		reg: regInfo{
4954			inputs: []inputInfo{
4955				{1, 255},   // AX CX DX BX SP BP SI DI
4956				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4957			},
4958			outputs: []outputInfo{
4959				{0, 239}, // AX CX DX BX BP SI DI
4960			},
4961		},
4962	},
4963	{
4964		name:      "LEAL4",
4965		auxType:   auxSymOff,
4966		argLen:    2,
4967		symEffect: SymAddr,
4968		reg: regInfo{
4969			inputs: []inputInfo{
4970				{1, 255},   // AX CX DX BX SP BP SI DI
4971				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4972			},
4973			outputs: []outputInfo{
4974				{0, 239}, // AX CX DX BX BP SI DI
4975			},
4976		},
4977	},
4978	{
4979		name:      "LEAL8",
4980		auxType:   auxSymOff,
4981		argLen:    2,
4982		symEffect: SymAddr,
4983		reg: regInfo{
4984			inputs: []inputInfo{
4985				{1, 255},   // AX CX DX BX SP BP SI DI
4986				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4987			},
4988			outputs: []outputInfo{
4989				{0, 239}, // AX CX DX BX BP SI DI
4990			},
4991		},
4992	},
4993	{
4994		name:           "MOVBload",
4995		auxType:        auxSymOff,
4996		argLen:         2,
4997		faultOnNilArg0: true,
4998		symEffect:      SymRead,
4999		asm:            x86.AMOVBLZX,
5000		reg: regInfo{
5001			inputs: []inputInfo{
5002				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5003			},
5004			outputs: []outputInfo{
5005				{0, 239}, // AX CX DX BX BP SI DI
5006			},
5007		},
5008	},
5009	{
5010		name:           "MOVBLSXload",
5011		auxType:        auxSymOff,
5012		argLen:         2,
5013		faultOnNilArg0: true,
5014		symEffect:      SymRead,
5015		asm:            x86.AMOVBLSX,
5016		reg: regInfo{
5017			inputs: []inputInfo{
5018				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5019			},
5020			outputs: []outputInfo{
5021				{0, 239}, // AX CX DX BX BP SI DI
5022			},
5023		},
5024	},
5025	{
5026		name:           "MOVWload",
5027		auxType:        auxSymOff,
5028		argLen:         2,
5029		faultOnNilArg0: true,
5030		symEffect:      SymRead,
5031		asm:            x86.AMOVWLZX,
5032		reg: regInfo{
5033			inputs: []inputInfo{
5034				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5035			},
5036			outputs: []outputInfo{
5037				{0, 239}, // AX CX DX BX BP SI DI
5038			},
5039		},
5040	},
5041	{
5042		name:           "MOVWLSXload",
5043		auxType:        auxSymOff,
5044		argLen:         2,
5045		faultOnNilArg0: true,
5046		symEffect:      SymRead,
5047		asm:            x86.AMOVWLSX,
5048		reg: regInfo{
5049			inputs: []inputInfo{
5050				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5051			},
5052			outputs: []outputInfo{
5053				{0, 239}, // AX CX DX BX BP SI DI
5054			},
5055		},
5056	},
5057	{
5058		name:           "MOVLload",
5059		auxType:        auxSymOff,
5060		argLen:         2,
5061		faultOnNilArg0: true,
5062		symEffect:      SymRead,
5063		asm:            x86.AMOVL,
5064		reg: regInfo{
5065			inputs: []inputInfo{
5066				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5067			},
5068			outputs: []outputInfo{
5069				{0, 239}, // AX CX DX BX BP SI DI
5070			},
5071		},
5072	},
5073	{
5074		name:           "MOVBstore",
5075		auxType:        auxSymOff,
5076		argLen:         3,
5077		faultOnNilArg0: true,
5078		symEffect:      SymWrite,
5079		asm:            x86.AMOVB,
5080		reg: regInfo{
5081			inputs: []inputInfo{
5082				{1, 255},   // AX CX DX BX SP BP SI DI
5083				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5084			},
5085		},
5086	},
5087	{
5088		name:           "MOVWstore",
5089		auxType:        auxSymOff,
5090		argLen:         3,
5091		faultOnNilArg0: true,
5092		symEffect:      SymWrite,
5093		asm:            x86.AMOVW,
5094		reg: regInfo{
5095			inputs: []inputInfo{
5096				{1, 255},   // AX CX DX BX SP BP SI DI
5097				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5098			},
5099		},
5100	},
5101	{
5102		name:           "MOVLstore",
5103		auxType:        auxSymOff,
5104		argLen:         3,
5105		faultOnNilArg0: true,
5106		symEffect:      SymWrite,
5107		asm:            x86.AMOVL,
5108		reg: regInfo{
5109			inputs: []inputInfo{
5110				{1, 255},   // AX CX DX BX SP BP SI DI
5111				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5112			},
5113		},
5114	},
5115	{
5116		name:           "ADDLmodify",
5117		auxType:        auxSymOff,
5118		argLen:         3,
5119		clobberFlags:   true,
5120		faultOnNilArg0: true,
5121		symEffect:      SymRead | SymWrite,
5122		asm:            x86.AADDL,
5123		reg: regInfo{
5124			inputs: []inputInfo{
5125				{1, 255},   // AX CX DX BX SP BP SI DI
5126				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5127			},
5128		},
5129	},
5130	{
5131		name:           "SUBLmodify",
5132		auxType:        auxSymOff,
5133		argLen:         3,
5134		clobberFlags:   true,
5135		faultOnNilArg0: true,
5136		symEffect:      SymRead | SymWrite,
5137		asm:            x86.ASUBL,
5138		reg: regInfo{
5139			inputs: []inputInfo{
5140				{1, 255},   // AX CX DX BX SP BP SI DI
5141				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5142			},
5143		},
5144	},
5145	{
5146		name:           "ANDLmodify",
5147		auxType:        auxSymOff,
5148		argLen:         3,
5149		clobberFlags:   true,
5150		faultOnNilArg0: true,
5151		symEffect:      SymRead | SymWrite,
5152		asm:            x86.AANDL,
5153		reg: regInfo{
5154			inputs: []inputInfo{
5155				{1, 255},   // AX CX DX BX SP BP SI DI
5156				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5157			},
5158		},
5159	},
5160	{
5161		name:           "ORLmodify",
5162		auxType:        auxSymOff,
5163		argLen:         3,
5164		clobberFlags:   true,
5165		faultOnNilArg0: true,
5166		symEffect:      SymRead | SymWrite,
5167		asm:            x86.AORL,
5168		reg: regInfo{
5169			inputs: []inputInfo{
5170				{1, 255},   // AX CX DX BX SP BP SI DI
5171				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5172			},
5173		},
5174	},
5175	{
5176		name:           "XORLmodify",
5177		auxType:        auxSymOff,
5178		argLen:         3,
5179		clobberFlags:   true,
5180		faultOnNilArg0: true,
5181		symEffect:      SymRead | SymWrite,
5182		asm:            x86.AXORL,
5183		reg: regInfo{
5184			inputs: []inputInfo{
5185				{1, 255},   // AX CX DX BX SP BP SI DI
5186				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5187			},
5188		},
5189	},
5190	{
5191		name:           "ADDLmodifyidx4",
5192		auxType:        auxSymOff,
5193		argLen:         4,
5194		clobberFlags:   true,
5195		faultOnNilArg0: true,
5196		symEffect:      SymRead | SymWrite,
5197		asm:            x86.AADDL,
5198		reg: regInfo{
5199			inputs: []inputInfo{
5200				{1, 255},   // AX CX DX BX SP BP SI DI
5201				{2, 255},   // AX CX DX BX SP BP SI DI
5202				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5203			},
5204		},
5205	},
5206	{
5207		name:           "SUBLmodifyidx4",
5208		auxType:        auxSymOff,
5209		argLen:         4,
5210		clobberFlags:   true,
5211		faultOnNilArg0: true,
5212		symEffect:      SymRead | SymWrite,
5213		asm:            x86.ASUBL,
5214		reg: regInfo{
5215			inputs: []inputInfo{
5216				{1, 255},   // AX CX DX BX SP BP SI DI
5217				{2, 255},   // AX CX DX BX SP BP SI DI
5218				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5219			},
5220		},
5221	},
5222	{
5223		name:           "ANDLmodifyidx4",
5224		auxType:        auxSymOff,
5225		argLen:         4,
5226		clobberFlags:   true,
5227		faultOnNilArg0: true,
5228		symEffect:      SymRead | SymWrite,
5229		asm:            x86.AANDL,
5230		reg: regInfo{
5231			inputs: []inputInfo{
5232				{1, 255},   // AX CX DX BX SP BP SI DI
5233				{2, 255},   // AX CX DX BX SP BP SI DI
5234				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5235			},
5236		},
5237	},
5238	{
5239		name:           "ORLmodifyidx4",
5240		auxType:        auxSymOff,
5241		argLen:         4,
5242		clobberFlags:   true,
5243		faultOnNilArg0: true,
5244		symEffect:      SymRead | SymWrite,
5245		asm:            x86.AORL,
5246		reg: regInfo{
5247			inputs: []inputInfo{
5248				{1, 255},   // AX CX DX BX SP BP SI DI
5249				{2, 255},   // AX CX DX BX SP BP SI DI
5250				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5251			},
5252		},
5253	},
5254	{
5255		name:           "XORLmodifyidx4",
5256		auxType:        auxSymOff,
5257		argLen:         4,
5258		clobberFlags:   true,
5259		faultOnNilArg0: true,
5260		symEffect:      SymRead | SymWrite,
5261		asm:            x86.AXORL,
5262		reg: regInfo{
5263			inputs: []inputInfo{
5264				{1, 255},   // AX CX DX BX SP BP SI DI
5265				{2, 255},   // AX CX DX BX SP BP SI DI
5266				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5267			},
5268		},
5269	},
5270	{
5271		name:           "ADDLconstmodify",
5272		auxType:        auxSymValAndOff,
5273		argLen:         2,
5274		clobberFlags:   true,
5275		faultOnNilArg0: true,
5276		symEffect:      SymRead | SymWrite,
5277		asm:            x86.AADDL,
5278		reg: regInfo{
5279			inputs: []inputInfo{
5280				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5281			},
5282		},
5283	},
5284	{
5285		name:           "ANDLconstmodify",
5286		auxType:        auxSymValAndOff,
5287		argLen:         2,
5288		clobberFlags:   true,
5289		faultOnNilArg0: true,
5290		symEffect:      SymRead | SymWrite,
5291		asm:            x86.AANDL,
5292		reg: regInfo{
5293			inputs: []inputInfo{
5294				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5295			},
5296		},
5297	},
5298	{
5299		name:           "ORLconstmodify",
5300		auxType:        auxSymValAndOff,
5301		argLen:         2,
5302		clobberFlags:   true,
5303		faultOnNilArg0: true,
5304		symEffect:      SymRead | SymWrite,
5305		asm:            x86.AORL,
5306		reg: regInfo{
5307			inputs: []inputInfo{
5308				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5309			},
5310		},
5311	},
5312	{
5313		name:           "XORLconstmodify",
5314		auxType:        auxSymValAndOff,
5315		argLen:         2,
5316		clobberFlags:   true,
5317		faultOnNilArg0: true,
5318		symEffect:      SymRead | SymWrite,
5319		asm:            x86.AXORL,
5320		reg: regInfo{
5321			inputs: []inputInfo{
5322				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5323			},
5324		},
5325	},
5326	{
5327		name:           "ADDLconstmodifyidx4",
5328		auxType:        auxSymValAndOff,
5329		argLen:         3,
5330		clobberFlags:   true,
5331		faultOnNilArg0: true,
5332		symEffect:      SymRead | SymWrite,
5333		asm:            x86.AADDL,
5334		reg: regInfo{
5335			inputs: []inputInfo{
5336				{1, 255},   // AX CX DX BX SP BP SI DI
5337				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5338			},
5339		},
5340	},
5341	{
5342		name:           "ANDLconstmodifyidx4",
5343		auxType:        auxSymValAndOff,
5344		argLen:         3,
5345		clobberFlags:   true,
5346		faultOnNilArg0: true,
5347		symEffect:      SymRead | SymWrite,
5348		asm:            x86.AANDL,
5349		reg: regInfo{
5350			inputs: []inputInfo{
5351				{1, 255},   // AX CX DX BX SP BP SI DI
5352				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5353			},
5354		},
5355	},
5356	{
5357		name:           "ORLconstmodifyidx4",
5358		auxType:        auxSymValAndOff,
5359		argLen:         3,
5360		clobberFlags:   true,
5361		faultOnNilArg0: true,
5362		symEffect:      SymRead | SymWrite,
5363		asm:            x86.AORL,
5364		reg: regInfo{
5365			inputs: []inputInfo{
5366				{1, 255},   // AX CX DX BX SP BP SI DI
5367				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5368			},
5369		},
5370	},
5371	{
5372		name:           "XORLconstmodifyidx4",
5373		auxType:        auxSymValAndOff,
5374		argLen:         3,
5375		clobberFlags:   true,
5376		faultOnNilArg0: true,
5377		symEffect:      SymRead | SymWrite,
5378		asm:            x86.AXORL,
5379		reg: regInfo{
5380			inputs: []inputInfo{
5381				{1, 255},   // AX CX DX BX SP BP SI DI
5382				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5383			},
5384		},
5385	},
5386	{
5387		name:        "MOVBloadidx1",
5388		auxType:     auxSymOff,
5389		argLen:      3,
5390		commutative: true,
5391		symEffect:   SymRead,
5392		asm:         x86.AMOVBLZX,
5393		reg: regInfo{
5394			inputs: []inputInfo{
5395				{1, 255},   // AX CX DX BX SP BP SI DI
5396				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5397			},
5398			outputs: []outputInfo{
5399				{0, 239}, // AX CX DX BX BP SI DI
5400			},
5401		},
5402	},
5403	{
5404		name:        "MOVWloadidx1",
5405		auxType:     auxSymOff,
5406		argLen:      3,
5407		commutative: true,
5408		symEffect:   SymRead,
5409		asm:         x86.AMOVWLZX,
5410		reg: regInfo{
5411			inputs: []inputInfo{
5412				{1, 255},   // AX CX DX BX SP BP SI DI
5413				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5414			},
5415			outputs: []outputInfo{
5416				{0, 239}, // AX CX DX BX BP SI DI
5417			},
5418		},
5419	},
5420	{
5421		name:      "MOVWloadidx2",
5422		auxType:   auxSymOff,
5423		argLen:    3,
5424		symEffect: SymRead,
5425		asm:       x86.AMOVWLZX,
5426		reg: regInfo{
5427			inputs: []inputInfo{
5428				{1, 255},   // AX CX DX BX SP BP SI DI
5429				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5430			},
5431			outputs: []outputInfo{
5432				{0, 239}, // AX CX DX BX BP SI DI
5433			},
5434		},
5435	},
5436	{
5437		name:        "MOVLloadidx1",
5438		auxType:     auxSymOff,
5439		argLen:      3,
5440		commutative: true,
5441		symEffect:   SymRead,
5442		asm:         x86.AMOVL,
5443		reg: regInfo{
5444			inputs: []inputInfo{
5445				{1, 255},   // AX CX DX BX SP BP SI DI
5446				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5447			},
5448			outputs: []outputInfo{
5449				{0, 239}, // AX CX DX BX BP SI DI
5450			},
5451		},
5452	},
5453	{
5454		name:      "MOVLloadidx4",
5455		auxType:   auxSymOff,
5456		argLen:    3,
5457		symEffect: SymRead,
5458		asm:       x86.AMOVL,
5459		reg: regInfo{
5460			inputs: []inputInfo{
5461				{1, 255},   // AX CX DX BX SP BP SI DI
5462				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5463			},
5464			outputs: []outputInfo{
5465				{0, 239}, // AX CX DX BX BP SI DI
5466			},
5467		},
5468	},
5469	{
5470		name:        "MOVBstoreidx1",
5471		auxType:     auxSymOff,
5472		argLen:      4,
5473		commutative: true,
5474		symEffect:   SymWrite,
5475		asm:         x86.AMOVB,
5476		reg: regInfo{
5477			inputs: []inputInfo{
5478				{1, 255},   // AX CX DX BX SP BP SI DI
5479				{2, 255},   // AX CX DX BX SP BP SI DI
5480				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5481			},
5482		},
5483	},
5484	{
5485		name:        "MOVWstoreidx1",
5486		auxType:     auxSymOff,
5487		argLen:      4,
5488		commutative: true,
5489		symEffect:   SymWrite,
5490		asm:         x86.AMOVW,
5491		reg: regInfo{
5492			inputs: []inputInfo{
5493				{1, 255},   // AX CX DX BX SP BP SI DI
5494				{2, 255},   // AX CX DX BX SP BP SI DI
5495				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5496			},
5497		},
5498	},
5499	{
5500		name:      "MOVWstoreidx2",
5501		auxType:   auxSymOff,
5502		argLen:    4,
5503		symEffect: SymWrite,
5504		asm:       x86.AMOVW,
5505		reg: regInfo{
5506			inputs: []inputInfo{
5507				{1, 255},   // AX CX DX BX SP BP SI DI
5508				{2, 255},   // AX CX DX BX SP BP SI DI
5509				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5510			},
5511		},
5512	},
5513	{
5514		name:        "MOVLstoreidx1",
5515		auxType:     auxSymOff,
5516		argLen:      4,
5517		commutative: true,
5518		symEffect:   SymWrite,
5519		asm:         x86.AMOVL,
5520		reg: regInfo{
5521			inputs: []inputInfo{
5522				{1, 255},   // AX CX DX BX SP BP SI DI
5523				{2, 255},   // AX CX DX BX SP BP SI DI
5524				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5525			},
5526		},
5527	},
5528	{
5529		name:      "MOVLstoreidx4",
5530		auxType:   auxSymOff,
5531		argLen:    4,
5532		symEffect: SymWrite,
5533		asm:       x86.AMOVL,
5534		reg: regInfo{
5535			inputs: []inputInfo{
5536				{1, 255},   // AX CX DX BX SP BP SI DI
5537				{2, 255},   // AX CX DX BX SP BP SI DI
5538				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5539			},
5540		},
5541	},
5542	{
5543		name:           "MOVBstoreconst",
5544		auxType:        auxSymValAndOff,
5545		argLen:         2,
5546		faultOnNilArg0: true,
5547		symEffect:      SymWrite,
5548		asm:            x86.AMOVB,
5549		reg: regInfo{
5550			inputs: []inputInfo{
5551				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5552			},
5553		},
5554	},
5555	{
5556		name:           "MOVWstoreconst",
5557		auxType:        auxSymValAndOff,
5558		argLen:         2,
5559		faultOnNilArg0: true,
5560		symEffect:      SymWrite,
5561		asm:            x86.AMOVW,
5562		reg: regInfo{
5563			inputs: []inputInfo{
5564				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5565			},
5566		},
5567	},
5568	{
5569		name:           "MOVLstoreconst",
5570		auxType:        auxSymValAndOff,
5571		argLen:         2,
5572		faultOnNilArg0: true,
5573		symEffect:      SymWrite,
5574		asm:            x86.AMOVL,
5575		reg: regInfo{
5576			inputs: []inputInfo{
5577				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5578			},
5579		},
5580	},
5581	{
5582		name:      "MOVBstoreconstidx1",
5583		auxType:   auxSymValAndOff,
5584		argLen:    3,
5585		symEffect: SymWrite,
5586		asm:       x86.AMOVB,
5587		reg: regInfo{
5588			inputs: []inputInfo{
5589				{1, 255},   // AX CX DX BX SP BP SI DI
5590				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5591			},
5592		},
5593	},
5594	{
5595		name:      "MOVWstoreconstidx1",
5596		auxType:   auxSymValAndOff,
5597		argLen:    3,
5598		symEffect: SymWrite,
5599		asm:       x86.AMOVW,
5600		reg: regInfo{
5601			inputs: []inputInfo{
5602				{1, 255},   // AX CX DX BX SP BP SI DI
5603				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5604			},
5605		},
5606	},
5607	{
5608		name:      "MOVWstoreconstidx2",
5609		auxType:   auxSymValAndOff,
5610		argLen:    3,
5611		symEffect: SymWrite,
5612		asm:       x86.AMOVW,
5613		reg: regInfo{
5614			inputs: []inputInfo{
5615				{1, 255},   // AX CX DX BX SP BP SI DI
5616				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5617			},
5618		},
5619	},
5620	{
5621		name:      "MOVLstoreconstidx1",
5622		auxType:   auxSymValAndOff,
5623		argLen:    3,
5624		symEffect: SymWrite,
5625		asm:       x86.AMOVL,
5626		reg: regInfo{
5627			inputs: []inputInfo{
5628				{1, 255},   // AX CX DX BX SP BP SI DI
5629				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5630			},
5631		},
5632	},
5633	{
5634		name:      "MOVLstoreconstidx4",
5635		auxType:   auxSymValAndOff,
5636		argLen:    3,
5637		symEffect: SymWrite,
5638		asm:       x86.AMOVL,
5639		reg: regInfo{
5640			inputs: []inputInfo{
5641				{1, 255},   // AX CX DX BX SP BP SI DI
5642				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5643			},
5644		},
5645	},
5646	{
5647		name:           "DUFFZERO",
5648		auxType:        auxInt64,
5649		argLen:         3,
5650		faultOnNilArg0: true,
5651		reg: regInfo{
5652			inputs: []inputInfo{
5653				{0, 128}, // DI
5654				{1, 1},   // AX
5655			},
5656			clobbers: 130, // CX DI
5657		},
5658	},
5659	{
5660		name:           "REPSTOSL",
5661		argLen:         4,
5662		faultOnNilArg0: true,
5663		reg: regInfo{
5664			inputs: []inputInfo{
5665				{0, 128}, // DI
5666				{1, 2},   // CX
5667				{2, 1},   // AX
5668			},
5669			clobbers: 130, // CX DI
5670		},
5671	},
5672	{
5673		name:         "CALLstatic",
5674		auxType:      auxSymOff,
5675		argLen:       1,
5676		clobberFlags: true,
5677		call:         true,
5678		symEffect:    SymNone,
5679		reg: regInfo{
5680			clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
5681		},
5682	},
5683	{
5684		name:         "CALLclosure",
5685		auxType:      auxInt64,
5686		argLen:       3,
5687		clobberFlags: true,
5688		call:         true,
5689		reg: regInfo{
5690			inputs: []inputInfo{
5691				{1, 4},   // DX
5692				{0, 255}, // AX CX DX BX SP BP SI DI
5693			},
5694			clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
5695		},
5696	},
5697	{
5698		name:         "CALLinter",
5699		auxType:      auxInt64,
5700		argLen:       2,
5701		clobberFlags: true,
5702		call:         true,
5703		reg: regInfo{
5704			inputs: []inputInfo{
5705				{0, 239}, // AX CX DX BX BP SI DI
5706			},
5707			clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
5708		},
5709	},
5710	{
5711		name:           "DUFFCOPY",
5712		auxType:        auxInt64,
5713		argLen:         3,
5714		clobberFlags:   true,
5715		faultOnNilArg0: true,
5716		faultOnNilArg1: true,
5717		reg: regInfo{
5718			inputs: []inputInfo{
5719				{0, 128}, // DI
5720				{1, 64},  // SI
5721			},
5722			clobbers: 194, // CX SI DI
5723		},
5724	},
5725	{
5726		name:           "REPMOVSL",
5727		argLen:         4,
5728		faultOnNilArg0: true,
5729		faultOnNilArg1: true,
5730		reg: regInfo{
5731			inputs: []inputInfo{
5732				{0, 128}, // DI
5733				{1, 64},  // SI
5734				{2, 2},   // CX
5735			},
5736			clobbers: 194, // CX SI DI
5737		},
5738	},
5739	{
5740		name:   "InvertFlags",
5741		argLen: 1,
5742		reg:    regInfo{},
5743	},
5744	{
5745		name:   "LoweredGetG",
5746		argLen: 1,
5747		reg: regInfo{
5748			outputs: []outputInfo{
5749				{0, 239}, // AX CX DX BX BP SI DI
5750			},
5751		},
5752	},
5753	{
5754		name:      "LoweredGetClosurePtr",
5755		argLen:    0,
5756		zeroWidth: true,
5757		reg: regInfo{
5758			outputs: []outputInfo{
5759				{0, 4}, // DX
5760			},
5761		},
5762	},
5763	{
5764		name:              "LoweredGetCallerPC",
5765		argLen:            0,
5766		rematerializeable: true,
5767		reg: regInfo{
5768			outputs: []outputInfo{
5769				{0, 239}, // AX CX DX BX BP SI DI
5770			},
5771		},
5772	},
5773	{
5774		name:              "LoweredGetCallerSP",
5775		argLen:            0,
5776		rematerializeable: true,
5777		reg: regInfo{
5778			outputs: []outputInfo{
5779				{0, 239}, // AX CX DX BX BP SI DI
5780			},
5781		},
5782	},
5783	{
5784		name:           "LoweredNilCheck",
5785		argLen:         2,
5786		clobberFlags:   true,
5787		nilCheck:       true,
5788		faultOnNilArg0: true,
5789		reg: regInfo{
5790			inputs: []inputInfo{
5791				{0, 255}, // AX CX DX BX SP BP SI DI
5792			},
5793		},
5794	},
5795	{
5796		name:         "LoweredWB",
5797		auxType:      auxSym,
5798		argLen:       3,
5799		clobberFlags: true,
5800		symEffect:    SymNone,
5801		reg: regInfo{
5802			inputs: []inputInfo{
5803				{0, 128}, // DI
5804				{1, 1},   // AX
5805			},
5806			clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7
5807		},
5808	},
5809	{
5810		name:    "LoweredPanicBoundsA",
5811		auxType: auxInt64,
5812		argLen:  3,
5813		reg: regInfo{
5814			inputs: []inputInfo{
5815				{0, 4}, // DX
5816				{1, 8}, // BX
5817			},
5818		},
5819	},
5820	{
5821		name:    "LoweredPanicBoundsB",
5822		auxType: auxInt64,
5823		argLen:  3,
5824		reg: regInfo{
5825			inputs: []inputInfo{
5826				{0, 2}, // CX
5827				{1, 4}, // DX
5828			},
5829		},
5830	},
5831	{
5832		name:    "LoweredPanicBoundsC",
5833		auxType: auxInt64,
5834		argLen:  3,
5835		reg: regInfo{
5836			inputs: []inputInfo{
5837				{0, 1}, // AX
5838				{1, 2}, // CX
5839			},
5840		},
5841	},
5842	{
5843		name:    "LoweredPanicExtendA",
5844		auxType: auxInt64,
5845		argLen:  4,
5846		reg: regInfo{
5847			inputs: []inputInfo{
5848				{0, 64}, // SI
5849				{1, 4},  // DX
5850				{2, 8},  // BX
5851			},
5852		},
5853	},
5854	{
5855		name:    "LoweredPanicExtendB",
5856		auxType: auxInt64,
5857		argLen:  4,
5858		reg: regInfo{
5859			inputs: []inputInfo{
5860				{0, 64}, // SI
5861				{1, 2},  // CX
5862				{2, 4},  // DX
5863			},
5864		},
5865	},
5866	{
5867		name:    "LoweredPanicExtendC",
5868		auxType: auxInt64,
5869		argLen:  4,
5870		reg: regInfo{
5871			inputs: []inputInfo{
5872				{0, 64}, // SI
5873				{1, 1},  // AX
5874				{2, 2},  // CX
5875			},
5876		},
5877	},
5878	{
5879		name:   "FlagEQ",
5880		argLen: 0,
5881		reg:    regInfo{},
5882	},
5883	{
5884		name:   "FlagLT_ULT",
5885		argLen: 0,
5886		reg:    regInfo{},
5887	},
5888	{
5889		name:   "FlagLT_UGT",
5890		argLen: 0,
5891		reg:    regInfo{},
5892	},
5893	{
5894		name:   "FlagGT_UGT",
5895		argLen: 0,
5896		reg:    regInfo{},
5897	},
5898	{
5899		name:   "FlagGT_ULT",
5900		argLen: 0,
5901		reg:    regInfo{},
5902	},
5903	{
5904		name:   "FCHS",
5905		argLen: 1,
5906		reg: regInfo{
5907			inputs: []inputInfo{
5908				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5909			},
5910			outputs: []outputInfo{
5911				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5912			},
5913		},
5914	},
5915	{
5916		name:    "MOVSSconst1",
5917		auxType: auxFloat32,
5918		argLen:  0,
5919		reg: regInfo{
5920			outputs: []outputInfo{
5921				{0, 239}, // AX CX DX BX BP SI DI
5922			},
5923		},
5924	},
5925	{
5926		name:    "MOVSDconst1",
5927		auxType: auxFloat64,
5928		argLen:  0,
5929		reg: regInfo{
5930			outputs: []outputInfo{
5931				{0, 239}, // AX CX DX BX BP SI DI
5932			},
5933		},
5934	},
5935	{
5936		name:   "MOVSSconst2",
5937		argLen: 1,
5938		asm:    x86.AMOVSS,
5939		reg: regInfo{
5940			inputs: []inputInfo{
5941				{0, 239}, // AX CX DX BX BP SI DI
5942			},
5943			outputs: []outputInfo{
5944				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5945			},
5946		},
5947	},
5948	{
5949		name:   "MOVSDconst2",
5950		argLen: 1,
5951		asm:    x86.AMOVSD,
5952		reg: regInfo{
5953			inputs: []inputInfo{
5954				{0, 239}, // AX CX DX BX BP SI DI
5955			},
5956			outputs: []outputInfo{
5957				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5958			},
5959		},
5960	},
5961
5962	{
5963		name:         "ADDSS",
5964		argLen:       2,
5965		commutative:  true,
5966		resultInArg0: true,
5967		asm:          x86.AADDSS,
5968		reg: regInfo{
5969			inputs: []inputInfo{
5970				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
5971				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
5972			},
5973			outputs: []outputInfo{
5974				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
5975			},
5976		},
5977	},
5978	{
5979		name:         "ADDSD",
5980		argLen:       2,
5981		commutative:  true,
5982		resultInArg0: true,
5983		asm:          x86.AADDSD,
5984		reg: regInfo{
5985			inputs: []inputInfo{
5986				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
5987				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
5988			},
5989			outputs: []outputInfo{
5990				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
5991			},
5992		},
5993	},
5994	{
5995		name:         "SUBSS",
5996		argLen:       2,
5997		resultInArg0: true,
5998		asm:          x86.ASUBSS,
5999		reg: regInfo{
6000			inputs: []inputInfo{
6001				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6002				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6003			},
6004			outputs: []outputInfo{
6005				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6006			},
6007		},
6008	},
6009	{
6010		name:         "SUBSD",
6011		argLen:       2,
6012		resultInArg0: true,
6013		asm:          x86.ASUBSD,
6014		reg: regInfo{
6015			inputs: []inputInfo{
6016				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6017				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6018			},
6019			outputs: []outputInfo{
6020				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6021			},
6022		},
6023	},
6024	{
6025		name:         "MULSS",
6026		argLen:       2,
6027		commutative:  true,
6028		resultInArg0: true,
6029		asm:          x86.AMULSS,
6030		reg: regInfo{
6031			inputs: []inputInfo{
6032				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6033				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6034			},
6035			outputs: []outputInfo{
6036				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6037			},
6038		},
6039	},
6040	{
6041		name:         "MULSD",
6042		argLen:       2,
6043		commutative:  true,
6044		resultInArg0: true,
6045		asm:          x86.AMULSD,
6046		reg: regInfo{
6047			inputs: []inputInfo{
6048				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6049				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6050			},
6051			outputs: []outputInfo{
6052				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6053			},
6054		},
6055	},
6056	{
6057		name:         "DIVSS",
6058		argLen:       2,
6059		resultInArg0: true,
6060		asm:          x86.ADIVSS,
6061		reg: regInfo{
6062			inputs: []inputInfo{
6063				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6064				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6065			},
6066			outputs: []outputInfo{
6067				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6068			},
6069		},
6070	},
6071	{
6072		name:         "DIVSD",
6073		argLen:       2,
6074		resultInArg0: true,
6075		asm:          x86.ADIVSD,
6076		reg: regInfo{
6077			inputs: []inputInfo{
6078				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6079				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6080			},
6081			outputs: []outputInfo{
6082				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6083			},
6084		},
6085	},
6086	{
6087		name:           "MOVSSload",
6088		auxType:        auxSymOff,
6089		argLen:         2,
6090		faultOnNilArg0: true,
6091		symEffect:      SymRead,
6092		asm:            x86.AMOVSS,
6093		reg: regInfo{
6094			inputs: []inputInfo{
6095				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6096			},
6097			outputs: []outputInfo{
6098				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6099			},
6100		},
6101	},
6102	{
6103		name:           "MOVSDload",
6104		auxType:        auxSymOff,
6105		argLen:         2,
6106		faultOnNilArg0: true,
6107		symEffect:      SymRead,
6108		asm:            x86.AMOVSD,
6109		reg: regInfo{
6110			inputs: []inputInfo{
6111				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6112			},
6113			outputs: []outputInfo{
6114				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6115			},
6116		},
6117	},
6118	{
6119		name:              "MOVSSconst",
6120		auxType:           auxFloat32,
6121		argLen:            0,
6122		rematerializeable: true,
6123		asm:               x86.AMOVSS,
6124		reg: regInfo{
6125			outputs: []outputInfo{
6126				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6127			},
6128		},
6129	},
6130	{
6131		name:              "MOVSDconst",
6132		auxType:           auxFloat64,
6133		argLen:            0,
6134		rematerializeable: true,
6135		asm:               x86.AMOVSD,
6136		reg: regInfo{
6137			outputs: []outputInfo{
6138				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6139			},
6140		},
6141	},
6142	{
6143		name:      "MOVSSloadidx1",
6144		auxType:   auxSymOff,
6145		argLen:    3,
6146		symEffect: SymRead,
6147		asm:       x86.AMOVSS,
6148		scale:     1,
6149		reg: regInfo{
6150			inputs: []inputInfo{
6151				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6152				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6153			},
6154			outputs: []outputInfo{
6155				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6156			},
6157		},
6158	},
6159	{
6160		name:      "MOVSSloadidx4",
6161		auxType:   auxSymOff,
6162		argLen:    3,
6163		symEffect: SymRead,
6164		asm:       x86.AMOVSS,
6165		scale:     4,
6166		reg: regInfo{
6167			inputs: []inputInfo{
6168				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6169				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6170			},
6171			outputs: []outputInfo{
6172				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6173			},
6174		},
6175	},
6176	{
6177		name:      "MOVSDloadidx1",
6178		auxType:   auxSymOff,
6179		argLen:    3,
6180		symEffect: SymRead,
6181		asm:       x86.AMOVSD,
6182		scale:     1,
6183		reg: regInfo{
6184			inputs: []inputInfo{
6185				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6186				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6187			},
6188			outputs: []outputInfo{
6189				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6190			},
6191		},
6192	},
6193	{
6194		name:      "MOVSDloadidx8",
6195		auxType:   auxSymOff,
6196		argLen:    3,
6197		symEffect: SymRead,
6198		asm:       x86.AMOVSD,
6199		scale:     8,
6200		reg: regInfo{
6201			inputs: []inputInfo{
6202				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6203				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6204			},
6205			outputs: []outputInfo{
6206				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6207			},
6208		},
6209	},
6210	{
6211		name:           "MOVSSstore",
6212		auxType:        auxSymOff,
6213		argLen:         3,
6214		faultOnNilArg0: true,
6215		symEffect:      SymWrite,
6216		asm:            x86.AMOVSS,
6217		reg: regInfo{
6218			inputs: []inputInfo{
6219				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6220				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6221			},
6222		},
6223	},
6224	{
6225		name:           "MOVSDstore",
6226		auxType:        auxSymOff,
6227		argLen:         3,
6228		faultOnNilArg0: true,
6229		symEffect:      SymWrite,
6230		asm:            x86.AMOVSD,
6231		reg: regInfo{
6232			inputs: []inputInfo{
6233				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6234				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6235			},
6236		},
6237	},
6238	{
6239		name:      "MOVSSstoreidx1",
6240		auxType:   auxSymOff,
6241		argLen:    4,
6242		symEffect: SymWrite,
6243		asm:       x86.AMOVSS,
6244		scale:     1,
6245		reg: regInfo{
6246			inputs: []inputInfo{
6247				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6248				{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6249				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6250			},
6251		},
6252	},
6253	{
6254		name:      "MOVSSstoreidx4",
6255		auxType:   auxSymOff,
6256		argLen:    4,
6257		symEffect: SymWrite,
6258		asm:       x86.AMOVSS,
6259		scale:     4,
6260		reg: regInfo{
6261			inputs: []inputInfo{
6262				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6263				{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6264				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6265			},
6266		},
6267	},
6268	{
6269		name:      "MOVSDstoreidx1",
6270		auxType:   auxSymOff,
6271		argLen:    4,
6272		symEffect: SymWrite,
6273		asm:       x86.AMOVSD,
6274		scale:     1,
6275		reg: regInfo{
6276			inputs: []inputInfo{
6277				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6278				{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6279				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6280			},
6281		},
6282	},
6283	{
6284		name:      "MOVSDstoreidx8",
6285		auxType:   auxSymOff,
6286		argLen:    4,
6287		symEffect: SymWrite,
6288		asm:       x86.AMOVSD,
6289		scale:     8,
6290		reg: regInfo{
6291			inputs: []inputInfo{
6292				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6293				{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6294				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6295			},
6296		},
6297	},
6298	{
6299		name:           "ADDSSload",
6300		auxType:        auxSymOff,
6301		argLen:         3,
6302		resultInArg0:   true,
6303		faultOnNilArg1: true,
6304		symEffect:      SymRead,
6305		asm:            x86.AADDSS,
6306		reg: regInfo{
6307			inputs: []inputInfo{
6308				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6309				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6310			},
6311			outputs: []outputInfo{
6312				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6313			},
6314		},
6315	},
6316	{
6317		name:           "ADDSDload",
6318		auxType:        auxSymOff,
6319		argLen:         3,
6320		resultInArg0:   true,
6321		faultOnNilArg1: true,
6322		symEffect:      SymRead,
6323		asm:            x86.AADDSD,
6324		reg: regInfo{
6325			inputs: []inputInfo{
6326				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6327				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6328			},
6329			outputs: []outputInfo{
6330				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6331			},
6332		},
6333	},
6334	{
6335		name:           "SUBSSload",
6336		auxType:        auxSymOff,
6337		argLen:         3,
6338		resultInArg0:   true,
6339		faultOnNilArg1: true,
6340		symEffect:      SymRead,
6341		asm:            x86.ASUBSS,
6342		reg: regInfo{
6343			inputs: []inputInfo{
6344				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6345				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6346			},
6347			outputs: []outputInfo{
6348				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6349			},
6350		},
6351	},
6352	{
6353		name:           "SUBSDload",
6354		auxType:        auxSymOff,
6355		argLen:         3,
6356		resultInArg0:   true,
6357		faultOnNilArg1: true,
6358		symEffect:      SymRead,
6359		asm:            x86.ASUBSD,
6360		reg: regInfo{
6361			inputs: []inputInfo{
6362				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6363				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6364			},
6365			outputs: []outputInfo{
6366				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6367			},
6368		},
6369	},
6370	{
6371		name:           "MULSSload",
6372		auxType:        auxSymOff,
6373		argLen:         3,
6374		resultInArg0:   true,
6375		faultOnNilArg1: true,
6376		symEffect:      SymRead,
6377		asm:            x86.AMULSS,
6378		reg: regInfo{
6379			inputs: []inputInfo{
6380				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6381				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6382			},
6383			outputs: []outputInfo{
6384				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6385			},
6386		},
6387	},
6388	{
6389		name:           "MULSDload",
6390		auxType:        auxSymOff,
6391		argLen:         3,
6392		resultInArg0:   true,
6393		faultOnNilArg1: true,
6394		symEffect:      SymRead,
6395		asm:            x86.AMULSD,
6396		reg: regInfo{
6397			inputs: []inputInfo{
6398				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6399				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6400			},
6401			outputs: []outputInfo{
6402				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6403			},
6404		},
6405	},
6406	{
6407		name:           "DIVSSload",
6408		auxType:        auxSymOff,
6409		argLen:         3,
6410		resultInArg0:   true,
6411		faultOnNilArg1: true,
6412		symEffect:      SymRead,
6413		asm:            x86.ADIVSS,
6414		reg: regInfo{
6415			inputs: []inputInfo{
6416				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6417				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6418			},
6419			outputs: []outputInfo{
6420				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6421			},
6422		},
6423	},
6424	{
6425		name:           "DIVSDload",
6426		auxType:        auxSymOff,
6427		argLen:         3,
6428		resultInArg0:   true,
6429		faultOnNilArg1: true,
6430		symEffect:      SymRead,
6431		asm:            x86.ADIVSD,
6432		reg: regInfo{
6433			inputs: []inputInfo{
6434				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6435				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6436			},
6437			outputs: []outputInfo{
6438				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
6439			},
6440		},
6441	},
6442	{
6443		name:         "ADDQ",
6444		argLen:       2,
6445		commutative:  true,
6446		clobberFlags: true,
6447		asm:          x86.AADDQ,
6448		reg: regInfo{
6449			inputs: []inputInfo{
6450				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6451				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6452			},
6453			outputs: []outputInfo{
6454				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6455			},
6456		},
6457	},
6458	{
6459		name:         "ADDL",
6460		argLen:       2,
6461		commutative:  true,
6462		clobberFlags: true,
6463		asm:          x86.AADDL,
6464		reg: regInfo{
6465			inputs: []inputInfo{
6466				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6467				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6468			},
6469			outputs: []outputInfo{
6470				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6471			},
6472		},
6473	},
6474	{
6475		name:         "ADDQconst",
6476		auxType:      auxInt32,
6477		argLen:       1,
6478		clobberFlags: true,
6479		asm:          x86.AADDQ,
6480		reg: regInfo{
6481			inputs: []inputInfo{
6482				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6483			},
6484			outputs: []outputInfo{
6485				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6486			},
6487		},
6488	},
6489	{
6490		name:         "ADDLconst",
6491		auxType:      auxInt32,
6492		argLen:       1,
6493		clobberFlags: true,
6494		asm:          x86.AADDL,
6495		reg: regInfo{
6496			inputs: []inputInfo{
6497				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6498			},
6499			outputs: []outputInfo{
6500				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6501			},
6502		},
6503	},
6504	{
6505		name:           "ADDQconstmodify",
6506		auxType:        auxSymValAndOff,
6507		argLen:         2,
6508		clobberFlags:   true,
6509		faultOnNilArg0: true,
6510		symEffect:      SymRead | SymWrite,
6511		asm:            x86.AADDQ,
6512		reg: regInfo{
6513			inputs: []inputInfo{
6514				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6515			},
6516		},
6517	},
6518	{
6519		name:           "ADDLconstmodify",
6520		auxType:        auxSymValAndOff,
6521		argLen:         2,
6522		clobberFlags:   true,
6523		faultOnNilArg0: true,
6524		symEffect:      SymRead | SymWrite,
6525		asm:            x86.AADDL,
6526		reg: regInfo{
6527			inputs: []inputInfo{
6528				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
6529			},
6530		},
6531	},
6532	{
6533		name:         "SUBQ",
6534		argLen:       2,
6535		resultInArg0: true,
6536		clobberFlags: true,
6537		asm:          x86.ASUBQ,
6538		reg: regInfo{
6539			inputs: []inputInfo{
6540				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6541				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6542			},
6543			outputs: []outputInfo{
6544				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6545			},
6546		},
6547	},
6548	{
6549		name:         "SUBL",
6550		argLen:       2,
6551		resultInArg0: true,
6552		clobberFlags: true,
6553		asm:          x86.ASUBL,
6554		reg: regInfo{
6555			inputs: []inputInfo{
6556				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6557				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6558			},
6559			outputs: []outputInfo{
6560				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6561			},
6562		},
6563	},
6564	{
6565		name:         "SUBQconst",
6566		auxType:      auxInt32,
6567		argLen:       1,
6568		resultInArg0: true,
6569		clobberFlags: true,
6570		asm:          x86.ASUBQ,
6571		reg: regInfo{
6572			inputs: []inputInfo{
6573				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6574			},
6575			outputs: []outputInfo{
6576				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6577			},
6578		},
6579	},
6580	{
6581		name:         "SUBLconst",
6582		auxType:      auxInt32,
6583		argLen:       1,
6584		resultInArg0: true,
6585		clobberFlags: true,
6586		asm:          x86.ASUBL,
6587		reg: regInfo{
6588			inputs: []inputInfo{
6589				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6590			},
6591			outputs: []outputInfo{
6592				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6593			},
6594		},
6595	},
6596	{
6597		name:         "MULQ",
6598		argLen:       2,
6599		commutative:  true,
6600		resultInArg0: true,
6601		clobberFlags: true,
6602		asm:          x86.AIMULQ,
6603		reg: regInfo{
6604			inputs: []inputInfo{
6605				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6606				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6607			},
6608			outputs: []outputInfo{
6609				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6610			},
6611		},
6612	},
6613	{
6614		name:         "MULL",
6615		argLen:       2,
6616		commutative:  true,
6617		resultInArg0: true,
6618		clobberFlags: true,
6619		asm:          x86.AIMULL,
6620		reg: regInfo{
6621			inputs: []inputInfo{
6622				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6623				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6624			},
6625			outputs: []outputInfo{
6626				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6627			},
6628		},
6629	},
6630	{
6631		name:         "MULQconst",
6632		auxType:      auxInt32,
6633		argLen:       1,
6634		clobberFlags: true,
6635		asm:          x86.AIMUL3Q,
6636		reg: regInfo{
6637			inputs: []inputInfo{
6638				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6639			},
6640			outputs: []outputInfo{
6641				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6642			},
6643		},
6644	},
6645	{
6646		name:         "MULLconst",
6647		auxType:      auxInt32,
6648		argLen:       1,
6649		clobberFlags: true,
6650		asm:          x86.AIMUL3L,
6651		reg: regInfo{
6652			inputs: []inputInfo{
6653				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6654			},
6655			outputs: []outputInfo{
6656				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6657			},
6658		},
6659	},
6660	{
6661		name:         "MULLU",
6662		argLen:       2,
6663		commutative:  true,
6664		clobberFlags: true,
6665		asm:          x86.AMULL,
6666		reg: regInfo{
6667			inputs: []inputInfo{
6668				{0, 1},     // AX
6669				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6670			},
6671			clobbers: 4, // DX
6672			outputs: []outputInfo{
6673				{1, 0},
6674				{0, 1}, // AX
6675			},
6676		},
6677	},
6678	{
6679		name:         "MULQU",
6680		argLen:       2,
6681		commutative:  true,
6682		clobberFlags: true,
6683		asm:          x86.AMULQ,
6684		reg: regInfo{
6685			inputs: []inputInfo{
6686				{0, 1},     // AX
6687				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6688			},
6689			clobbers: 4, // DX
6690			outputs: []outputInfo{
6691				{1, 0},
6692				{0, 1}, // AX
6693			},
6694		},
6695	},
6696	{
6697		name:         "HMULQ",
6698		argLen:       2,
6699		commutative:  true,
6700		clobberFlags: true,
6701		asm:          x86.AIMULQ,
6702		reg: regInfo{
6703			inputs: []inputInfo{
6704				{0, 1},     // AX
6705				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6706			},
6707			clobbers: 1, // AX
6708			outputs: []outputInfo{
6709				{0, 4}, // DX
6710			},
6711		},
6712	},
6713	{
6714		name:         "HMULL",
6715		argLen:       2,
6716		commutative:  true,
6717		clobberFlags: true,
6718		asm:          x86.AIMULL,
6719		reg: regInfo{
6720			inputs: []inputInfo{
6721				{0, 1},     // AX
6722				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6723			},
6724			clobbers: 1, // AX
6725			outputs: []outputInfo{
6726				{0, 4}, // DX
6727			},
6728		},
6729	},
6730	{
6731		name:         "HMULQU",
6732		argLen:       2,
6733		commutative:  true,
6734		clobberFlags: true,
6735		asm:          x86.AMULQ,
6736		reg: regInfo{
6737			inputs: []inputInfo{
6738				{0, 1},     // AX
6739				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6740			},
6741			clobbers: 1, // AX
6742			outputs: []outputInfo{
6743				{0, 4}, // DX
6744			},
6745		},
6746	},
6747	{
6748		name:         "HMULLU",
6749		argLen:       2,
6750		commutative:  true,
6751		clobberFlags: true,
6752		asm:          x86.AMULL,
6753		reg: regInfo{
6754			inputs: []inputInfo{
6755				{0, 1},     // AX
6756				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6757			},
6758			clobbers: 1, // AX
6759			outputs: []outputInfo{
6760				{0, 4}, // DX
6761			},
6762		},
6763	},
6764	{
6765		name:         "AVGQU",
6766		argLen:       2,
6767		commutative:  true,
6768		resultInArg0: true,
6769		clobberFlags: true,
6770		reg: regInfo{
6771			inputs: []inputInfo{
6772				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6773				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6774			},
6775			outputs: []outputInfo{
6776				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6777			},
6778		},
6779	},
6780	{
6781		name:         "DIVQ",
6782		auxType:      auxBool,
6783		argLen:       2,
6784		clobberFlags: true,
6785		asm:          x86.AIDIVQ,
6786		reg: regInfo{
6787			inputs: []inputInfo{
6788				{0, 1},     // AX
6789				{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6790			},
6791			outputs: []outputInfo{
6792				{0, 1}, // AX
6793				{1, 4}, // DX
6794			},
6795		},
6796	},
6797	{
6798		name:         "DIVL",
6799		auxType:      auxBool,
6800		argLen:       2,
6801		clobberFlags: true,
6802		asm:          x86.AIDIVL,
6803		reg: regInfo{
6804			inputs: []inputInfo{
6805				{0, 1},     // AX
6806				{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6807			},
6808			outputs: []outputInfo{
6809				{0, 1}, // AX
6810				{1, 4}, // DX
6811			},
6812		},
6813	},
6814	{
6815		name:         "DIVW",
6816		auxType:      auxBool,
6817		argLen:       2,
6818		clobberFlags: true,
6819		asm:          x86.AIDIVW,
6820		reg: regInfo{
6821			inputs: []inputInfo{
6822				{0, 1},     // AX
6823				{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6824			},
6825			outputs: []outputInfo{
6826				{0, 1}, // AX
6827				{1, 4}, // DX
6828			},
6829		},
6830	},
6831	{
6832		name:         "DIVQU",
6833		argLen:       2,
6834		clobberFlags: true,
6835		asm:          x86.ADIVQ,
6836		reg: regInfo{
6837			inputs: []inputInfo{
6838				{0, 1},     // AX
6839				{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6840			},
6841			outputs: []outputInfo{
6842				{0, 1}, // AX
6843				{1, 4}, // DX
6844			},
6845		},
6846	},
6847	{
6848		name:         "DIVLU",
6849		argLen:       2,
6850		clobberFlags: true,
6851		asm:          x86.ADIVL,
6852		reg: regInfo{
6853			inputs: []inputInfo{
6854				{0, 1},     // AX
6855				{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6856			},
6857			outputs: []outputInfo{
6858				{0, 1}, // AX
6859				{1, 4}, // DX
6860			},
6861		},
6862	},
6863	{
6864		name:         "DIVWU",
6865		argLen:       2,
6866		clobberFlags: true,
6867		asm:          x86.ADIVW,
6868		reg: regInfo{
6869			inputs: []inputInfo{
6870				{0, 1},     // AX
6871				{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6872			},
6873			outputs: []outputInfo{
6874				{0, 1}, // AX
6875				{1, 4}, // DX
6876			},
6877		},
6878	},
6879	{
6880		name:         "NEGLflags",
6881		argLen:       1,
6882		resultInArg0: true,
6883		asm:          x86.ANEGL,
6884		reg: regInfo{
6885			inputs: []inputInfo{
6886				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6887			},
6888			outputs: []outputInfo{
6889				{1, 0},
6890				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6891			},
6892		},
6893	},
6894	{
6895		name:         "ADDQcarry",
6896		argLen:       2,
6897		commutative:  true,
6898		resultInArg0: true,
6899		asm:          x86.AADDQ,
6900		reg: regInfo{
6901			inputs: []inputInfo{
6902				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6903				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6904			},
6905			outputs: []outputInfo{
6906				{1, 0},
6907				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6908			},
6909		},
6910	},
6911	{
6912		name:         "ADCQ",
6913		argLen:       3,
6914		commutative:  true,
6915		resultInArg0: true,
6916		asm:          x86.AADCQ,
6917		reg: regInfo{
6918			inputs: []inputInfo{
6919				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6920				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6921			},
6922			outputs: []outputInfo{
6923				{1, 0},
6924				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6925			},
6926		},
6927	},
6928	{
6929		name:         "ADDQconstcarry",
6930		auxType:      auxInt32,
6931		argLen:       1,
6932		resultInArg0: true,
6933		asm:          x86.AADDQ,
6934		reg: regInfo{
6935			inputs: []inputInfo{
6936				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6937			},
6938			outputs: []outputInfo{
6939				{1, 0},
6940				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6941			},
6942		},
6943	},
6944	{
6945		name:         "ADCQconst",
6946		auxType:      auxInt32,
6947		argLen:       2,
6948		resultInArg0: true,
6949		asm:          x86.AADCQ,
6950		reg: regInfo{
6951			inputs: []inputInfo{
6952				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6953			},
6954			outputs: []outputInfo{
6955				{1, 0},
6956				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6957			},
6958		},
6959	},
6960	{
6961		name:         "SUBQborrow",
6962		argLen:       2,
6963		resultInArg0: true,
6964		asm:          x86.ASUBQ,
6965		reg: regInfo{
6966			inputs: []inputInfo{
6967				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6968				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6969			},
6970			outputs: []outputInfo{
6971				{1, 0},
6972				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6973			},
6974		},
6975	},
6976	{
6977		name:         "SBBQ",
6978		argLen:       3,
6979		resultInArg0: true,
6980		asm:          x86.ASBBQ,
6981		reg: regInfo{
6982			inputs: []inputInfo{
6983				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6984				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6985			},
6986			outputs: []outputInfo{
6987				{1, 0},
6988				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
6989			},
6990		},
6991	},
6992	{
6993		name:         "SUBQconstborrow",
6994		auxType:      auxInt32,
6995		argLen:       1,
6996		resultInArg0: true,
6997		asm:          x86.ASUBQ,
6998		reg: regInfo{
6999			inputs: []inputInfo{
7000				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7001			},
7002			outputs: []outputInfo{
7003				{1, 0},
7004				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7005			},
7006		},
7007	},
7008	{
7009		name:         "SBBQconst",
7010		auxType:      auxInt32,
7011		argLen:       2,
7012		resultInArg0: true,
7013		asm:          x86.ASBBQ,
7014		reg: regInfo{
7015			inputs: []inputInfo{
7016				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7017			},
7018			outputs: []outputInfo{
7019				{1, 0},
7020				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7021			},
7022		},
7023	},
7024	{
7025		name:         "MULQU2",
7026		argLen:       2,
7027		commutative:  true,
7028		clobberFlags: true,
7029		asm:          x86.AMULQ,
7030		reg: regInfo{
7031			inputs: []inputInfo{
7032				{0, 1},     // AX
7033				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7034			},
7035			outputs: []outputInfo{
7036				{0, 4}, // DX
7037				{1, 1}, // AX
7038			},
7039		},
7040	},
7041	{
7042		name:         "DIVQU2",
7043		argLen:       3,
7044		clobberFlags: true,
7045		asm:          x86.ADIVQ,
7046		reg: regInfo{
7047			inputs: []inputInfo{
7048				{0, 4},     // DX
7049				{1, 1},     // AX
7050				{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7051			},
7052			outputs: []outputInfo{
7053				{0, 1}, // AX
7054				{1, 4}, // DX
7055			},
7056		},
7057	},
7058	{
7059		name:         "ANDQ",
7060		argLen:       2,
7061		commutative:  true,
7062		resultInArg0: true,
7063		clobberFlags: true,
7064		asm:          x86.AANDQ,
7065		reg: regInfo{
7066			inputs: []inputInfo{
7067				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7068				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7069			},
7070			outputs: []outputInfo{
7071				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7072			},
7073		},
7074	},
7075	{
7076		name:         "ANDL",
7077		argLen:       2,
7078		commutative:  true,
7079		resultInArg0: true,
7080		clobberFlags: true,
7081		asm:          x86.AANDL,
7082		reg: regInfo{
7083			inputs: []inputInfo{
7084				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7085				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7086			},
7087			outputs: []outputInfo{
7088				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7089			},
7090		},
7091	},
7092	{
7093		name:         "ANDQconst",
7094		auxType:      auxInt32,
7095		argLen:       1,
7096		resultInArg0: true,
7097		clobberFlags: true,
7098		asm:          x86.AANDQ,
7099		reg: regInfo{
7100			inputs: []inputInfo{
7101				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7102			},
7103			outputs: []outputInfo{
7104				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7105			},
7106		},
7107	},
7108	{
7109		name:         "ANDLconst",
7110		auxType:      auxInt32,
7111		argLen:       1,
7112		resultInArg0: true,
7113		clobberFlags: true,
7114		asm:          x86.AANDL,
7115		reg: regInfo{
7116			inputs: []inputInfo{
7117				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7118			},
7119			outputs: []outputInfo{
7120				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7121			},
7122		},
7123	},
7124	{
7125		name:           "ANDQconstmodify",
7126		auxType:        auxSymValAndOff,
7127		argLen:         2,
7128		clobberFlags:   true,
7129		faultOnNilArg0: true,
7130		symEffect:      SymRead | SymWrite,
7131		asm:            x86.AANDQ,
7132		reg: regInfo{
7133			inputs: []inputInfo{
7134				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7135			},
7136		},
7137	},
7138	{
7139		name:           "ANDLconstmodify",
7140		auxType:        auxSymValAndOff,
7141		argLen:         2,
7142		clobberFlags:   true,
7143		faultOnNilArg0: true,
7144		symEffect:      SymRead | SymWrite,
7145		asm:            x86.AANDL,
7146		reg: regInfo{
7147			inputs: []inputInfo{
7148				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7149			},
7150		},
7151	},
7152	{
7153		name:         "ORQ",
7154		argLen:       2,
7155		commutative:  true,
7156		resultInArg0: true,
7157		clobberFlags: true,
7158		asm:          x86.AORQ,
7159		reg: regInfo{
7160			inputs: []inputInfo{
7161				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7162				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7163			},
7164			outputs: []outputInfo{
7165				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7166			},
7167		},
7168	},
7169	{
7170		name:         "ORL",
7171		argLen:       2,
7172		commutative:  true,
7173		resultInArg0: true,
7174		clobberFlags: true,
7175		asm:          x86.AORL,
7176		reg: regInfo{
7177			inputs: []inputInfo{
7178				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7179				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7180			},
7181			outputs: []outputInfo{
7182				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7183			},
7184		},
7185	},
7186	{
7187		name:         "ORQconst",
7188		auxType:      auxInt32,
7189		argLen:       1,
7190		resultInArg0: true,
7191		clobberFlags: true,
7192		asm:          x86.AORQ,
7193		reg: regInfo{
7194			inputs: []inputInfo{
7195				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7196			},
7197			outputs: []outputInfo{
7198				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7199			},
7200		},
7201	},
7202	{
7203		name:         "ORLconst",
7204		auxType:      auxInt32,
7205		argLen:       1,
7206		resultInArg0: true,
7207		clobberFlags: true,
7208		asm:          x86.AORL,
7209		reg: regInfo{
7210			inputs: []inputInfo{
7211				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7212			},
7213			outputs: []outputInfo{
7214				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7215			},
7216		},
7217	},
7218	{
7219		name:           "ORQconstmodify",
7220		auxType:        auxSymValAndOff,
7221		argLen:         2,
7222		clobberFlags:   true,
7223		faultOnNilArg0: true,
7224		symEffect:      SymRead | SymWrite,
7225		asm:            x86.AORQ,
7226		reg: regInfo{
7227			inputs: []inputInfo{
7228				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7229			},
7230		},
7231	},
7232	{
7233		name:           "ORLconstmodify",
7234		auxType:        auxSymValAndOff,
7235		argLen:         2,
7236		clobberFlags:   true,
7237		faultOnNilArg0: true,
7238		symEffect:      SymRead | SymWrite,
7239		asm:            x86.AORL,
7240		reg: regInfo{
7241			inputs: []inputInfo{
7242				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7243			},
7244		},
7245	},
7246	{
7247		name:         "XORQ",
7248		argLen:       2,
7249		commutative:  true,
7250		resultInArg0: true,
7251		clobberFlags: true,
7252		asm:          x86.AXORQ,
7253		reg: regInfo{
7254			inputs: []inputInfo{
7255				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7256				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7257			},
7258			outputs: []outputInfo{
7259				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7260			},
7261		},
7262	},
7263	{
7264		name:         "XORL",
7265		argLen:       2,
7266		commutative:  true,
7267		resultInArg0: true,
7268		clobberFlags: true,
7269		asm:          x86.AXORL,
7270		reg: regInfo{
7271			inputs: []inputInfo{
7272				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7273				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7274			},
7275			outputs: []outputInfo{
7276				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7277			},
7278		},
7279	},
7280	{
7281		name:         "XORQconst",
7282		auxType:      auxInt32,
7283		argLen:       1,
7284		resultInArg0: true,
7285		clobberFlags: true,
7286		asm:          x86.AXORQ,
7287		reg: regInfo{
7288			inputs: []inputInfo{
7289				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7290			},
7291			outputs: []outputInfo{
7292				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7293			},
7294		},
7295	},
7296	{
7297		name:         "XORLconst",
7298		auxType:      auxInt32,
7299		argLen:       1,
7300		resultInArg0: true,
7301		clobberFlags: true,
7302		asm:          x86.AXORL,
7303		reg: regInfo{
7304			inputs: []inputInfo{
7305				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7306			},
7307			outputs: []outputInfo{
7308				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7309			},
7310		},
7311	},
7312	{
7313		name:           "XORQconstmodify",
7314		auxType:        auxSymValAndOff,
7315		argLen:         2,
7316		clobberFlags:   true,
7317		faultOnNilArg0: true,
7318		symEffect:      SymRead | SymWrite,
7319		asm:            x86.AXORQ,
7320		reg: regInfo{
7321			inputs: []inputInfo{
7322				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7323			},
7324		},
7325	},
7326	{
7327		name:           "XORLconstmodify",
7328		auxType:        auxSymValAndOff,
7329		argLen:         2,
7330		clobberFlags:   true,
7331		faultOnNilArg0: true,
7332		symEffect:      SymRead | SymWrite,
7333		asm:            x86.AXORL,
7334		reg: regInfo{
7335			inputs: []inputInfo{
7336				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7337			},
7338		},
7339	},
7340	{
7341		name:   "CMPQ",
7342		argLen: 2,
7343		asm:    x86.ACMPQ,
7344		reg: regInfo{
7345			inputs: []inputInfo{
7346				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7347				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7348			},
7349		},
7350	},
7351	{
7352		name:   "CMPL",
7353		argLen: 2,
7354		asm:    x86.ACMPL,
7355		reg: regInfo{
7356			inputs: []inputInfo{
7357				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7358				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7359			},
7360		},
7361	},
7362	{
7363		name:   "CMPW",
7364		argLen: 2,
7365		asm:    x86.ACMPW,
7366		reg: regInfo{
7367			inputs: []inputInfo{
7368				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7369				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7370			},
7371		},
7372	},
7373	{
7374		name:   "CMPB",
7375		argLen: 2,
7376		asm:    x86.ACMPB,
7377		reg: regInfo{
7378			inputs: []inputInfo{
7379				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7380				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7381			},
7382		},
7383	},
7384	{
7385		name:    "CMPQconst",
7386		auxType: auxInt32,
7387		argLen:  1,
7388		asm:     x86.ACMPQ,
7389		reg: regInfo{
7390			inputs: []inputInfo{
7391				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7392			},
7393		},
7394	},
7395	{
7396		name:    "CMPLconst",
7397		auxType: auxInt32,
7398		argLen:  1,
7399		asm:     x86.ACMPL,
7400		reg: regInfo{
7401			inputs: []inputInfo{
7402				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7403			},
7404		},
7405	},
7406	{
7407		name:    "CMPWconst",
7408		auxType: auxInt16,
7409		argLen:  1,
7410		asm:     x86.ACMPW,
7411		reg: regInfo{
7412			inputs: []inputInfo{
7413				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7414			},
7415		},
7416	},
7417	{
7418		name:    "CMPBconst",
7419		auxType: auxInt8,
7420		argLen:  1,
7421		asm:     x86.ACMPB,
7422		reg: regInfo{
7423			inputs: []inputInfo{
7424				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7425			},
7426		},
7427	},
7428	{
7429		name:           "CMPQload",
7430		auxType:        auxSymOff,
7431		argLen:         3,
7432		faultOnNilArg0: true,
7433		symEffect:      SymRead,
7434		asm:            x86.ACMPQ,
7435		reg: regInfo{
7436			inputs: []inputInfo{
7437				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7438				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7439			},
7440		},
7441	},
7442	{
7443		name:           "CMPLload",
7444		auxType:        auxSymOff,
7445		argLen:         3,
7446		faultOnNilArg0: true,
7447		symEffect:      SymRead,
7448		asm:            x86.ACMPL,
7449		reg: regInfo{
7450			inputs: []inputInfo{
7451				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7452				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7453			},
7454		},
7455	},
7456	{
7457		name:           "CMPWload",
7458		auxType:        auxSymOff,
7459		argLen:         3,
7460		faultOnNilArg0: true,
7461		symEffect:      SymRead,
7462		asm:            x86.ACMPW,
7463		reg: regInfo{
7464			inputs: []inputInfo{
7465				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7466				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7467			},
7468		},
7469	},
7470	{
7471		name:           "CMPBload",
7472		auxType:        auxSymOff,
7473		argLen:         3,
7474		faultOnNilArg0: true,
7475		symEffect:      SymRead,
7476		asm:            x86.ACMPB,
7477		reg: regInfo{
7478			inputs: []inputInfo{
7479				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7480				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7481			},
7482		},
7483	},
7484	{
7485		name:           "CMPQconstload",
7486		auxType:        auxSymValAndOff,
7487		argLen:         2,
7488		faultOnNilArg0: true,
7489		symEffect:      SymRead,
7490		asm:            x86.ACMPQ,
7491		reg: regInfo{
7492			inputs: []inputInfo{
7493				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7494			},
7495		},
7496	},
7497	{
7498		name:           "CMPLconstload",
7499		auxType:        auxSymValAndOff,
7500		argLen:         2,
7501		faultOnNilArg0: true,
7502		symEffect:      SymRead,
7503		asm:            x86.ACMPL,
7504		reg: regInfo{
7505			inputs: []inputInfo{
7506				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7507			},
7508		},
7509	},
7510	{
7511		name:           "CMPWconstload",
7512		auxType:        auxSymValAndOff,
7513		argLen:         2,
7514		faultOnNilArg0: true,
7515		symEffect:      SymRead,
7516		asm:            x86.ACMPW,
7517		reg: regInfo{
7518			inputs: []inputInfo{
7519				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7520			},
7521		},
7522	},
7523	{
7524		name:           "CMPBconstload",
7525		auxType:        auxSymValAndOff,
7526		argLen:         2,
7527		faultOnNilArg0: true,
7528		symEffect:      SymRead,
7529		asm:            x86.ACMPB,
7530		reg: regInfo{
7531			inputs: []inputInfo{
7532				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7533			},
7534		},
7535	},
7536	{
7537		name:   "UCOMISS",
7538		argLen: 2,
7539		asm:    x86.AUCOMISS,
7540		reg: regInfo{
7541			inputs: []inputInfo{
7542				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
7543				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
7544			},
7545		},
7546	},
7547	{
7548		name:   "UCOMISD",
7549		argLen: 2,
7550		asm:    x86.AUCOMISD,
7551		reg: regInfo{
7552			inputs: []inputInfo{
7553				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
7554				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
7555			},
7556		},
7557	},
7558	{
7559		name:   "BTL",
7560		argLen: 2,
7561		asm:    x86.ABTL,
7562		reg: regInfo{
7563			inputs: []inputInfo{
7564				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7565				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7566			},
7567		},
7568	},
7569	{
7570		name:   "BTQ",
7571		argLen: 2,
7572		asm:    x86.ABTQ,
7573		reg: regInfo{
7574			inputs: []inputInfo{
7575				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7576				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7577			},
7578		},
7579	},
7580	{
7581		name:         "BTCL",
7582		argLen:       2,
7583		resultInArg0: true,
7584		clobberFlags: true,
7585		asm:          x86.ABTCL,
7586		reg: regInfo{
7587			inputs: []inputInfo{
7588				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7589				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7590			},
7591			outputs: []outputInfo{
7592				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7593			},
7594		},
7595	},
7596	{
7597		name:         "BTCQ",
7598		argLen:       2,
7599		resultInArg0: true,
7600		clobberFlags: true,
7601		asm:          x86.ABTCQ,
7602		reg: regInfo{
7603			inputs: []inputInfo{
7604				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7605				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7606			},
7607			outputs: []outputInfo{
7608				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7609			},
7610		},
7611	},
7612	{
7613		name:         "BTRL",
7614		argLen:       2,
7615		resultInArg0: true,
7616		clobberFlags: true,
7617		asm:          x86.ABTRL,
7618		reg: regInfo{
7619			inputs: []inputInfo{
7620				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7621				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7622			},
7623			outputs: []outputInfo{
7624				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7625			},
7626		},
7627	},
7628	{
7629		name:         "BTRQ",
7630		argLen:       2,
7631		resultInArg0: true,
7632		clobberFlags: true,
7633		asm:          x86.ABTRQ,
7634		reg: regInfo{
7635			inputs: []inputInfo{
7636				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7637				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7638			},
7639			outputs: []outputInfo{
7640				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7641			},
7642		},
7643	},
7644	{
7645		name:         "BTSL",
7646		argLen:       2,
7647		resultInArg0: true,
7648		clobberFlags: true,
7649		asm:          x86.ABTSL,
7650		reg: regInfo{
7651			inputs: []inputInfo{
7652				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7653				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7654			},
7655			outputs: []outputInfo{
7656				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7657			},
7658		},
7659	},
7660	{
7661		name:         "BTSQ",
7662		argLen:       2,
7663		resultInArg0: true,
7664		clobberFlags: true,
7665		asm:          x86.ABTSQ,
7666		reg: regInfo{
7667			inputs: []inputInfo{
7668				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7669				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7670			},
7671			outputs: []outputInfo{
7672				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7673			},
7674		},
7675	},
7676	{
7677		name:    "BTLconst",
7678		auxType: auxInt8,
7679		argLen:  1,
7680		asm:     x86.ABTL,
7681		reg: regInfo{
7682			inputs: []inputInfo{
7683				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7684			},
7685		},
7686	},
7687	{
7688		name:    "BTQconst",
7689		auxType: auxInt8,
7690		argLen:  1,
7691		asm:     x86.ABTQ,
7692		reg: regInfo{
7693			inputs: []inputInfo{
7694				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7695			},
7696		},
7697	},
7698	{
7699		name:         "BTCLconst",
7700		auxType:      auxInt8,
7701		argLen:       1,
7702		resultInArg0: true,
7703		clobberFlags: true,
7704		asm:          x86.ABTCL,
7705		reg: regInfo{
7706			inputs: []inputInfo{
7707				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7708			},
7709			outputs: []outputInfo{
7710				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7711			},
7712		},
7713	},
7714	{
7715		name:         "BTCQconst",
7716		auxType:      auxInt8,
7717		argLen:       1,
7718		resultInArg0: true,
7719		clobberFlags: true,
7720		asm:          x86.ABTCQ,
7721		reg: regInfo{
7722			inputs: []inputInfo{
7723				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7724			},
7725			outputs: []outputInfo{
7726				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7727			},
7728		},
7729	},
7730	{
7731		name:         "BTRLconst",
7732		auxType:      auxInt8,
7733		argLen:       1,
7734		resultInArg0: true,
7735		clobberFlags: true,
7736		asm:          x86.ABTRL,
7737		reg: regInfo{
7738			inputs: []inputInfo{
7739				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7740			},
7741			outputs: []outputInfo{
7742				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7743			},
7744		},
7745	},
7746	{
7747		name:         "BTRQconst",
7748		auxType:      auxInt8,
7749		argLen:       1,
7750		resultInArg0: true,
7751		clobberFlags: true,
7752		asm:          x86.ABTRQ,
7753		reg: regInfo{
7754			inputs: []inputInfo{
7755				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7756			},
7757			outputs: []outputInfo{
7758				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7759			},
7760		},
7761	},
7762	{
7763		name:         "BTSLconst",
7764		auxType:      auxInt8,
7765		argLen:       1,
7766		resultInArg0: true,
7767		clobberFlags: true,
7768		asm:          x86.ABTSL,
7769		reg: regInfo{
7770			inputs: []inputInfo{
7771				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7772			},
7773			outputs: []outputInfo{
7774				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7775			},
7776		},
7777	},
7778	{
7779		name:         "BTSQconst",
7780		auxType:      auxInt8,
7781		argLen:       1,
7782		resultInArg0: true,
7783		clobberFlags: true,
7784		asm:          x86.ABTSQ,
7785		reg: regInfo{
7786			inputs: []inputInfo{
7787				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7788			},
7789			outputs: []outputInfo{
7790				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7791			},
7792		},
7793	},
7794	{
7795		name:           "BTCQmodify",
7796		auxType:        auxSymOff,
7797		argLen:         3,
7798		clobberFlags:   true,
7799		faultOnNilArg0: true,
7800		symEffect:      SymRead | SymWrite,
7801		asm:            x86.ABTCQ,
7802		reg: regInfo{
7803			inputs: []inputInfo{
7804				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7805				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7806			},
7807		},
7808	},
7809	{
7810		name:           "BTCLmodify",
7811		auxType:        auxSymOff,
7812		argLen:         3,
7813		clobberFlags:   true,
7814		faultOnNilArg0: true,
7815		symEffect:      SymRead | SymWrite,
7816		asm:            x86.ABTCL,
7817		reg: regInfo{
7818			inputs: []inputInfo{
7819				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7820				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7821			},
7822		},
7823	},
7824	{
7825		name:           "BTSQmodify",
7826		auxType:        auxSymOff,
7827		argLen:         3,
7828		clobberFlags:   true,
7829		faultOnNilArg0: true,
7830		symEffect:      SymRead | SymWrite,
7831		asm:            x86.ABTSQ,
7832		reg: regInfo{
7833			inputs: []inputInfo{
7834				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7835				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7836			},
7837		},
7838	},
7839	{
7840		name:           "BTSLmodify",
7841		auxType:        auxSymOff,
7842		argLen:         3,
7843		clobberFlags:   true,
7844		faultOnNilArg0: true,
7845		symEffect:      SymRead | SymWrite,
7846		asm:            x86.ABTSL,
7847		reg: regInfo{
7848			inputs: []inputInfo{
7849				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7850				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7851			},
7852		},
7853	},
7854	{
7855		name:           "BTRQmodify",
7856		auxType:        auxSymOff,
7857		argLen:         3,
7858		clobberFlags:   true,
7859		faultOnNilArg0: true,
7860		symEffect:      SymRead | SymWrite,
7861		asm:            x86.ABTRQ,
7862		reg: regInfo{
7863			inputs: []inputInfo{
7864				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7865				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7866			},
7867		},
7868	},
7869	{
7870		name:           "BTRLmodify",
7871		auxType:        auxSymOff,
7872		argLen:         3,
7873		clobberFlags:   true,
7874		faultOnNilArg0: true,
7875		symEffect:      SymRead | SymWrite,
7876		asm:            x86.ABTRL,
7877		reg: regInfo{
7878			inputs: []inputInfo{
7879				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7880				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7881			},
7882		},
7883	},
7884	{
7885		name:           "BTCQconstmodify",
7886		auxType:        auxSymValAndOff,
7887		argLen:         2,
7888		clobberFlags:   true,
7889		faultOnNilArg0: true,
7890		symEffect:      SymRead | SymWrite,
7891		asm:            x86.ABTCQ,
7892		reg: regInfo{
7893			inputs: []inputInfo{
7894				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7895			},
7896		},
7897	},
7898	{
7899		name:           "BTCLconstmodify",
7900		auxType:        auxSymValAndOff,
7901		argLen:         2,
7902		clobberFlags:   true,
7903		faultOnNilArg0: true,
7904		symEffect:      SymRead | SymWrite,
7905		asm:            x86.ABTCL,
7906		reg: regInfo{
7907			inputs: []inputInfo{
7908				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7909			},
7910		},
7911	},
7912	{
7913		name:           "BTSQconstmodify",
7914		auxType:        auxSymValAndOff,
7915		argLen:         2,
7916		clobberFlags:   true,
7917		faultOnNilArg0: true,
7918		symEffect:      SymRead | SymWrite,
7919		asm:            x86.ABTSQ,
7920		reg: regInfo{
7921			inputs: []inputInfo{
7922				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7923			},
7924		},
7925	},
7926	{
7927		name:           "BTSLconstmodify",
7928		auxType:        auxSymValAndOff,
7929		argLen:         2,
7930		clobberFlags:   true,
7931		faultOnNilArg0: true,
7932		symEffect:      SymRead | SymWrite,
7933		asm:            x86.ABTSL,
7934		reg: regInfo{
7935			inputs: []inputInfo{
7936				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7937			},
7938		},
7939	},
7940	{
7941		name:           "BTRQconstmodify",
7942		auxType:        auxSymValAndOff,
7943		argLen:         2,
7944		clobberFlags:   true,
7945		faultOnNilArg0: true,
7946		symEffect:      SymRead | SymWrite,
7947		asm:            x86.ABTRQ,
7948		reg: regInfo{
7949			inputs: []inputInfo{
7950				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7951			},
7952		},
7953	},
7954	{
7955		name:           "BTRLconstmodify",
7956		auxType:        auxSymValAndOff,
7957		argLen:         2,
7958		clobberFlags:   true,
7959		faultOnNilArg0: true,
7960		symEffect:      SymRead | SymWrite,
7961		asm:            x86.ABTRL,
7962		reg: regInfo{
7963			inputs: []inputInfo{
7964				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
7965			},
7966		},
7967	},
7968	{
7969		name:        "TESTQ",
7970		argLen:      2,
7971		commutative: true,
7972		asm:         x86.ATESTQ,
7973		reg: regInfo{
7974			inputs: []inputInfo{
7975				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7976				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7977			},
7978		},
7979	},
7980	{
7981		name:        "TESTL",
7982		argLen:      2,
7983		commutative: true,
7984		asm:         x86.ATESTL,
7985		reg: regInfo{
7986			inputs: []inputInfo{
7987				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7988				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
7989			},
7990		},
7991	},
7992	{
7993		name:        "TESTW",
7994		argLen:      2,
7995		commutative: true,
7996		asm:         x86.ATESTW,
7997		reg: regInfo{
7998			inputs: []inputInfo{
7999				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8000				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8001			},
8002		},
8003	},
8004	{
8005		name:        "TESTB",
8006		argLen:      2,
8007		commutative: true,
8008		asm:         x86.ATESTB,
8009		reg: regInfo{
8010			inputs: []inputInfo{
8011				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8012				{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8013			},
8014		},
8015	},
8016	{
8017		name:    "TESTQconst",
8018		auxType: auxInt32,
8019		argLen:  1,
8020		asm:     x86.ATESTQ,
8021		reg: regInfo{
8022			inputs: []inputInfo{
8023				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8024			},
8025		},
8026	},
8027	{
8028		name:    "TESTLconst",
8029		auxType: auxInt32,
8030		argLen:  1,
8031		asm:     x86.ATESTL,
8032		reg: regInfo{
8033			inputs: []inputInfo{
8034				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8035			},
8036		},
8037	},
8038	{
8039		name:    "TESTWconst",
8040		auxType: auxInt16,
8041		argLen:  1,
8042		asm:     x86.ATESTW,
8043		reg: regInfo{
8044			inputs: []inputInfo{
8045				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8046			},
8047		},
8048	},
8049	{
8050		name:    "TESTBconst",
8051		auxType: auxInt8,
8052		argLen:  1,
8053		asm:     x86.ATESTB,
8054		reg: regInfo{
8055			inputs: []inputInfo{
8056				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8057			},
8058		},
8059	},
8060	{
8061		name:         "SHLQ",
8062		argLen:       2,
8063		resultInArg0: true,
8064		clobberFlags: true,
8065		asm:          x86.ASHLQ,
8066		reg: regInfo{
8067			inputs: []inputInfo{
8068				{1, 2},     // CX
8069				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8070			},
8071			outputs: []outputInfo{
8072				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8073			},
8074		},
8075	},
8076	{
8077		name:         "SHLL",
8078		argLen:       2,
8079		resultInArg0: true,
8080		clobberFlags: true,
8081		asm:          x86.ASHLL,
8082		reg: regInfo{
8083			inputs: []inputInfo{
8084				{1, 2},     // CX
8085				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8086			},
8087			outputs: []outputInfo{
8088				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8089			},
8090		},
8091	},
8092	{
8093		name:         "SHLQconst",
8094		auxType:      auxInt8,
8095		argLen:       1,
8096		resultInArg0: true,
8097		clobberFlags: true,
8098		asm:          x86.ASHLQ,
8099		reg: regInfo{
8100			inputs: []inputInfo{
8101				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8102			},
8103			outputs: []outputInfo{
8104				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8105			},
8106		},
8107	},
8108	{
8109		name:         "SHLLconst",
8110		auxType:      auxInt8,
8111		argLen:       1,
8112		resultInArg0: true,
8113		clobberFlags: true,
8114		asm:          x86.ASHLL,
8115		reg: regInfo{
8116			inputs: []inputInfo{
8117				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8118			},
8119			outputs: []outputInfo{
8120				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8121			},
8122		},
8123	},
8124	{
8125		name:         "SHRQ",
8126		argLen:       2,
8127		resultInArg0: true,
8128		clobberFlags: true,
8129		asm:          x86.ASHRQ,
8130		reg: regInfo{
8131			inputs: []inputInfo{
8132				{1, 2},     // CX
8133				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8134			},
8135			outputs: []outputInfo{
8136				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8137			},
8138		},
8139	},
8140	{
8141		name:         "SHRL",
8142		argLen:       2,
8143		resultInArg0: true,
8144		clobberFlags: true,
8145		asm:          x86.ASHRL,
8146		reg: regInfo{
8147			inputs: []inputInfo{
8148				{1, 2},     // CX
8149				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8150			},
8151			outputs: []outputInfo{
8152				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8153			},
8154		},
8155	},
8156	{
8157		name:         "SHRW",
8158		argLen:       2,
8159		resultInArg0: true,
8160		clobberFlags: true,
8161		asm:          x86.ASHRW,
8162		reg: regInfo{
8163			inputs: []inputInfo{
8164				{1, 2},     // CX
8165				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8166			},
8167			outputs: []outputInfo{
8168				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8169			},
8170		},
8171	},
8172	{
8173		name:         "SHRB",
8174		argLen:       2,
8175		resultInArg0: true,
8176		clobberFlags: true,
8177		asm:          x86.ASHRB,
8178		reg: regInfo{
8179			inputs: []inputInfo{
8180				{1, 2},     // CX
8181				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8182			},
8183			outputs: []outputInfo{
8184				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8185			},
8186		},
8187	},
8188	{
8189		name:         "SHRQconst",
8190		auxType:      auxInt8,
8191		argLen:       1,
8192		resultInArg0: true,
8193		clobberFlags: true,
8194		asm:          x86.ASHRQ,
8195		reg: regInfo{
8196			inputs: []inputInfo{
8197				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8198			},
8199			outputs: []outputInfo{
8200				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8201			},
8202		},
8203	},
8204	{
8205		name:         "SHRLconst",
8206		auxType:      auxInt8,
8207		argLen:       1,
8208		resultInArg0: true,
8209		clobberFlags: true,
8210		asm:          x86.ASHRL,
8211		reg: regInfo{
8212			inputs: []inputInfo{
8213				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8214			},
8215			outputs: []outputInfo{
8216				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8217			},
8218		},
8219	},
8220	{
8221		name:         "SHRWconst",
8222		auxType:      auxInt8,
8223		argLen:       1,
8224		resultInArg0: true,
8225		clobberFlags: true,
8226		asm:          x86.ASHRW,
8227		reg: regInfo{
8228			inputs: []inputInfo{
8229				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8230			},
8231			outputs: []outputInfo{
8232				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8233			},
8234		},
8235	},
8236	{
8237		name:         "SHRBconst",
8238		auxType:      auxInt8,
8239		argLen:       1,
8240		resultInArg0: true,
8241		clobberFlags: true,
8242		asm:          x86.ASHRB,
8243		reg: regInfo{
8244			inputs: []inputInfo{
8245				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8246			},
8247			outputs: []outputInfo{
8248				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8249			},
8250		},
8251	},
8252	{
8253		name:         "SARQ",
8254		argLen:       2,
8255		resultInArg0: true,
8256		clobberFlags: true,
8257		asm:          x86.ASARQ,
8258		reg: regInfo{
8259			inputs: []inputInfo{
8260				{1, 2},     // CX
8261				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8262			},
8263			outputs: []outputInfo{
8264				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8265			},
8266		},
8267	},
8268	{
8269		name:         "SARL",
8270		argLen:       2,
8271		resultInArg0: true,
8272		clobberFlags: true,
8273		asm:          x86.ASARL,
8274		reg: regInfo{
8275			inputs: []inputInfo{
8276				{1, 2},     // CX
8277				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8278			},
8279			outputs: []outputInfo{
8280				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8281			},
8282		},
8283	},
8284	{
8285		name:         "SARW",
8286		argLen:       2,
8287		resultInArg0: true,
8288		clobberFlags: true,
8289		asm:          x86.ASARW,
8290		reg: regInfo{
8291			inputs: []inputInfo{
8292				{1, 2},     // CX
8293				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8294			},
8295			outputs: []outputInfo{
8296				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8297			},
8298		},
8299	},
8300	{
8301		name:         "SARB",
8302		argLen:       2,
8303		resultInArg0: true,
8304		clobberFlags: true,
8305		asm:          x86.ASARB,
8306		reg: regInfo{
8307			inputs: []inputInfo{
8308				{1, 2},     // CX
8309				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8310			},
8311			outputs: []outputInfo{
8312				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8313			},
8314		},
8315	},
8316	{
8317		name:         "SARQconst",
8318		auxType:      auxInt8,
8319		argLen:       1,
8320		resultInArg0: true,
8321		clobberFlags: true,
8322		asm:          x86.ASARQ,
8323		reg: regInfo{
8324			inputs: []inputInfo{
8325				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8326			},
8327			outputs: []outputInfo{
8328				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8329			},
8330		},
8331	},
8332	{
8333		name:         "SARLconst",
8334		auxType:      auxInt8,
8335		argLen:       1,
8336		resultInArg0: true,
8337		clobberFlags: true,
8338		asm:          x86.ASARL,
8339		reg: regInfo{
8340			inputs: []inputInfo{
8341				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8342			},
8343			outputs: []outputInfo{
8344				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8345			},
8346		},
8347	},
8348	{
8349		name:         "SARWconst",
8350		auxType:      auxInt8,
8351		argLen:       1,
8352		resultInArg0: true,
8353		clobberFlags: true,
8354		asm:          x86.ASARW,
8355		reg: regInfo{
8356			inputs: []inputInfo{
8357				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8358			},
8359			outputs: []outputInfo{
8360				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8361			},
8362		},
8363	},
8364	{
8365		name:         "SARBconst",
8366		auxType:      auxInt8,
8367		argLen:       1,
8368		resultInArg0: true,
8369		clobberFlags: true,
8370		asm:          x86.ASARB,
8371		reg: regInfo{
8372			inputs: []inputInfo{
8373				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8374			},
8375			outputs: []outputInfo{
8376				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8377			},
8378		},
8379	},
8380	{
8381		name:         "ROLQ",
8382		argLen:       2,
8383		resultInArg0: true,
8384		clobberFlags: true,
8385		asm:          x86.AROLQ,
8386		reg: regInfo{
8387			inputs: []inputInfo{
8388				{1, 2},     // CX
8389				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8390			},
8391			outputs: []outputInfo{
8392				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8393			},
8394		},
8395	},
8396	{
8397		name:         "ROLL",
8398		argLen:       2,
8399		resultInArg0: true,
8400		clobberFlags: true,
8401		asm:          x86.AROLL,
8402		reg: regInfo{
8403			inputs: []inputInfo{
8404				{1, 2},     // CX
8405				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8406			},
8407			outputs: []outputInfo{
8408				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8409			},
8410		},
8411	},
8412	{
8413		name:         "ROLW",
8414		argLen:       2,
8415		resultInArg0: true,
8416		clobberFlags: true,
8417		asm:          x86.AROLW,
8418		reg: regInfo{
8419			inputs: []inputInfo{
8420				{1, 2},     // CX
8421				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8422			},
8423			outputs: []outputInfo{
8424				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8425			},
8426		},
8427	},
8428	{
8429		name:         "ROLB",
8430		argLen:       2,
8431		resultInArg0: true,
8432		clobberFlags: true,
8433		asm:          x86.AROLB,
8434		reg: regInfo{
8435			inputs: []inputInfo{
8436				{1, 2},     // CX
8437				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8438			},
8439			outputs: []outputInfo{
8440				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8441			},
8442		},
8443	},
8444	{
8445		name:         "RORQ",
8446		argLen:       2,
8447		resultInArg0: true,
8448		clobberFlags: true,
8449		asm:          x86.ARORQ,
8450		reg: regInfo{
8451			inputs: []inputInfo{
8452				{1, 2},     // CX
8453				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8454			},
8455			outputs: []outputInfo{
8456				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8457			},
8458		},
8459	},
8460	{
8461		name:         "RORL",
8462		argLen:       2,
8463		resultInArg0: true,
8464		clobberFlags: true,
8465		asm:          x86.ARORL,
8466		reg: regInfo{
8467			inputs: []inputInfo{
8468				{1, 2},     // CX
8469				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8470			},
8471			outputs: []outputInfo{
8472				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8473			},
8474		},
8475	},
8476	{
8477		name:         "RORW",
8478		argLen:       2,
8479		resultInArg0: true,
8480		clobberFlags: true,
8481		asm:          x86.ARORW,
8482		reg: regInfo{
8483			inputs: []inputInfo{
8484				{1, 2},     // CX
8485				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8486			},
8487			outputs: []outputInfo{
8488				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8489			},
8490		},
8491	},
8492	{
8493		name:         "RORB",
8494		argLen:       2,
8495		resultInArg0: true,
8496		clobberFlags: true,
8497		asm:          x86.ARORB,
8498		reg: regInfo{
8499			inputs: []inputInfo{
8500				{1, 2},     // CX
8501				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8502			},
8503			outputs: []outputInfo{
8504				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8505			},
8506		},
8507	},
8508	{
8509		name:         "ROLQconst",
8510		auxType:      auxInt8,
8511		argLen:       1,
8512		resultInArg0: true,
8513		clobberFlags: true,
8514		asm:          x86.AROLQ,
8515		reg: regInfo{
8516			inputs: []inputInfo{
8517				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8518			},
8519			outputs: []outputInfo{
8520				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8521			},
8522		},
8523	},
8524	{
8525		name:         "ROLLconst",
8526		auxType:      auxInt8,
8527		argLen:       1,
8528		resultInArg0: true,
8529		clobberFlags: true,
8530		asm:          x86.AROLL,
8531		reg: regInfo{
8532			inputs: []inputInfo{
8533				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8534			},
8535			outputs: []outputInfo{
8536				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8537			},
8538		},
8539	},
8540	{
8541		name:         "ROLWconst",
8542		auxType:      auxInt8,
8543		argLen:       1,
8544		resultInArg0: true,
8545		clobberFlags: true,
8546		asm:          x86.AROLW,
8547		reg: regInfo{
8548			inputs: []inputInfo{
8549				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8550			},
8551			outputs: []outputInfo{
8552				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8553			},
8554		},
8555	},
8556	{
8557		name:         "ROLBconst",
8558		auxType:      auxInt8,
8559		argLen:       1,
8560		resultInArg0: true,
8561		clobberFlags: true,
8562		asm:          x86.AROLB,
8563		reg: regInfo{
8564			inputs: []inputInfo{
8565				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8566			},
8567			outputs: []outputInfo{
8568				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8569			},
8570		},
8571	},
8572	{
8573		name:           "ADDLload",
8574		auxType:        auxSymOff,
8575		argLen:         3,
8576		resultInArg0:   true,
8577		clobberFlags:   true,
8578		faultOnNilArg1: true,
8579		symEffect:      SymRead,
8580		asm:            x86.AADDL,
8581		reg: regInfo{
8582			inputs: []inputInfo{
8583				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8584				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8585			},
8586			outputs: []outputInfo{
8587				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8588			},
8589		},
8590	},
8591	{
8592		name:           "ADDQload",
8593		auxType:        auxSymOff,
8594		argLen:         3,
8595		resultInArg0:   true,
8596		clobberFlags:   true,
8597		faultOnNilArg1: true,
8598		symEffect:      SymRead,
8599		asm:            x86.AADDQ,
8600		reg: regInfo{
8601			inputs: []inputInfo{
8602				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8603				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8604			},
8605			outputs: []outputInfo{
8606				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8607			},
8608		},
8609	},
8610	{
8611		name:           "SUBQload",
8612		auxType:        auxSymOff,
8613		argLen:         3,
8614		resultInArg0:   true,
8615		clobberFlags:   true,
8616		faultOnNilArg1: true,
8617		symEffect:      SymRead,
8618		asm:            x86.ASUBQ,
8619		reg: regInfo{
8620			inputs: []inputInfo{
8621				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8622				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8623			},
8624			outputs: []outputInfo{
8625				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8626			},
8627		},
8628	},
8629	{
8630		name:           "SUBLload",
8631		auxType:        auxSymOff,
8632		argLen:         3,
8633		resultInArg0:   true,
8634		clobberFlags:   true,
8635		faultOnNilArg1: true,
8636		symEffect:      SymRead,
8637		asm:            x86.ASUBL,
8638		reg: regInfo{
8639			inputs: []inputInfo{
8640				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8641				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8642			},
8643			outputs: []outputInfo{
8644				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8645			},
8646		},
8647	},
8648	{
8649		name:           "ANDLload",
8650		auxType:        auxSymOff,
8651		argLen:         3,
8652		resultInArg0:   true,
8653		clobberFlags:   true,
8654		faultOnNilArg1: true,
8655		symEffect:      SymRead,
8656		asm:            x86.AANDL,
8657		reg: regInfo{
8658			inputs: []inputInfo{
8659				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8660				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8661			},
8662			outputs: []outputInfo{
8663				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8664			},
8665		},
8666	},
8667	{
8668		name:           "ANDQload",
8669		auxType:        auxSymOff,
8670		argLen:         3,
8671		resultInArg0:   true,
8672		clobberFlags:   true,
8673		faultOnNilArg1: true,
8674		symEffect:      SymRead,
8675		asm:            x86.AANDQ,
8676		reg: regInfo{
8677			inputs: []inputInfo{
8678				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8679				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8680			},
8681			outputs: []outputInfo{
8682				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8683			},
8684		},
8685	},
8686	{
8687		name:           "ORQload",
8688		auxType:        auxSymOff,
8689		argLen:         3,
8690		resultInArg0:   true,
8691		clobberFlags:   true,
8692		faultOnNilArg1: true,
8693		symEffect:      SymRead,
8694		asm:            x86.AORQ,
8695		reg: regInfo{
8696			inputs: []inputInfo{
8697				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8698				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8699			},
8700			outputs: []outputInfo{
8701				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8702			},
8703		},
8704	},
8705	{
8706		name:           "ORLload",
8707		auxType:        auxSymOff,
8708		argLen:         3,
8709		resultInArg0:   true,
8710		clobberFlags:   true,
8711		faultOnNilArg1: true,
8712		symEffect:      SymRead,
8713		asm:            x86.AORL,
8714		reg: regInfo{
8715			inputs: []inputInfo{
8716				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8717				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8718			},
8719			outputs: []outputInfo{
8720				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8721			},
8722		},
8723	},
8724	{
8725		name:           "XORQload",
8726		auxType:        auxSymOff,
8727		argLen:         3,
8728		resultInArg0:   true,
8729		clobberFlags:   true,
8730		faultOnNilArg1: true,
8731		symEffect:      SymRead,
8732		asm:            x86.AXORQ,
8733		reg: regInfo{
8734			inputs: []inputInfo{
8735				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8736				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8737			},
8738			outputs: []outputInfo{
8739				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8740			},
8741		},
8742	},
8743	{
8744		name:           "XORLload",
8745		auxType:        auxSymOff,
8746		argLen:         3,
8747		resultInArg0:   true,
8748		clobberFlags:   true,
8749		faultOnNilArg1: true,
8750		symEffect:      SymRead,
8751		asm:            x86.AXORL,
8752		reg: regInfo{
8753			inputs: []inputInfo{
8754				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8755				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8756			},
8757			outputs: []outputInfo{
8758				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8759			},
8760		},
8761	},
8762	{
8763		name:           "ADDQmodify",
8764		auxType:        auxSymOff,
8765		argLen:         3,
8766		clobberFlags:   true,
8767		faultOnNilArg0: true,
8768		symEffect:      SymRead | SymWrite,
8769		asm:            x86.AADDQ,
8770		reg: regInfo{
8771			inputs: []inputInfo{
8772				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8773				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8774			},
8775		},
8776	},
8777	{
8778		name:           "SUBQmodify",
8779		auxType:        auxSymOff,
8780		argLen:         3,
8781		clobberFlags:   true,
8782		faultOnNilArg0: true,
8783		symEffect:      SymRead | SymWrite,
8784		asm:            x86.ASUBQ,
8785		reg: regInfo{
8786			inputs: []inputInfo{
8787				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8788				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8789			},
8790		},
8791	},
8792	{
8793		name:           "ANDQmodify",
8794		auxType:        auxSymOff,
8795		argLen:         3,
8796		clobberFlags:   true,
8797		faultOnNilArg0: true,
8798		symEffect:      SymRead | SymWrite,
8799		asm:            x86.AANDQ,
8800		reg: regInfo{
8801			inputs: []inputInfo{
8802				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8803				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8804			},
8805		},
8806	},
8807	{
8808		name:           "ORQmodify",
8809		auxType:        auxSymOff,
8810		argLen:         3,
8811		clobberFlags:   true,
8812		faultOnNilArg0: true,
8813		symEffect:      SymRead | SymWrite,
8814		asm:            x86.AORQ,
8815		reg: regInfo{
8816			inputs: []inputInfo{
8817				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8818				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8819			},
8820		},
8821	},
8822	{
8823		name:           "XORQmodify",
8824		auxType:        auxSymOff,
8825		argLen:         3,
8826		clobberFlags:   true,
8827		faultOnNilArg0: true,
8828		symEffect:      SymRead | SymWrite,
8829		asm:            x86.AXORQ,
8830		reg: regInfo{
8831			inputs: []inputInfo{
8832				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8833				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8834			},
8835		},
8836	},
8837	{
8838		name:           "ADDLmodify",
8839		auxType:        auxSymOff,
8840		argLen:         3,
8841		clobberFlags:   true,
8842		faultOnNilArg0: true,
8843		symEffect:      SymRead | SymWrite,
8844		asm:            x86.AADDL,
8845		reg: regInfo{
8846			inputs: []inputInfo{
8847				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8848				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8849			},
8850		},
8851	},
8852	{
8853		name:           "SUBLmodify",
8854		auxType:        auxSymOff,
8855		argLen:         3,
8856		clobberFlags:   true,
8857		faultOnNilArg0: true,
8858		symEffect:      SymRead | SymWrite,
8859		asm:            x86.ASUBL,
8860		reg: regInfo{
8861			inputs: []inputInfo{
8862				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8863				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8864			},
8865		},
8866	},
8867	{
8868		name:           "ANDLmodify",
8869		auxType:        auxSymOff,
8870		argLen:         3,
8871		clobberFlags:   true,
8872		faultOnNilArg0: true,
8873		symEffect:      SymRead | SymWrite,
8874		asm:            x86.AANDL,
8875		reg: regInfo{
8876			inputs: []inputInfo{
8877				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8878				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8879			},
8880		},
8881	},
8882	{
8883		name:           "ORLmodify",
8884		auxType:        auxSymOff,
8885		argLen:         3,
8886		clobberFlags:   true,
8887		faultOnNilArg0: true,
8888		symEffect:      SymRead | SymWrite,
8889		asm:            x86.AORL,
8890		reg: regInfo{
8891			inputs: []inputInfo{
8892				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8893				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8894			},
8895		},
8896	},
8897	{
8898		name:           "XORLmodify",
8899		auxType:        auxSymOff,
8900		argLen:         3,
8901		clobberFlags:   true,
8902		faultOnNilArg0: true,
8903		symEffect:      SymRead | SymWrite,
8904		asm:            x86.AXORL,
8905		reg: regInfo{
8906			inputs: []inputInfo{
8907				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8908				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
8909			},
8910		},
8911	},
8912	{
8913		name:         "NEGQ",
8914		argLen:       1,
8915		resultInArg0: true,
8916		clobberFlags: true,
8917		asm:          x86.ANEGQ,
8918		reg: regInfo{
8919			inputs: []inputInfo{
8920				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8921			},
8922			outputs: []outputInfo{
8923				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8924			},
8925		},
8926	},
8927	{
8928		name:         "NEGL",
8929		argLen:       1,
8930		resultInArg0: true,
8931		clobberFlags: true,
8932		asm:          x86.ANEGL,
8933		reg: regInfo{
8934			inputs: []inputInfo{
8935				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8936			},
8937			outputs: []outputInfo{
8938				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8939			},
8940		},
8941	},
8942	{
8943		name:         "NOTQ",
8944		argLen:       1,
8945		resultInArg0: true,
8946		clobberFlags: true,
8947		asm:          x86.ANOTQ,
8948		reg: regInfo{
8949			inputs: []inputInfo{
8950				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8951			},
8952			outputs: []outputInfo{
8953				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8954			},
8955		},
8956	},
8957	{
8958		name:         "NOTL",
8959		argLen:       1,
8960		resultInArg0: true,
8961		clobberFlags: true,
8962		asm:          x86.ANOTL,
8963		reg: regInfo{
8964			inputs: []inputInfo{
8965				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8966			},
8967			outputs: []outputInfo{
8968				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8969			},
8970		},
8971	},
8972	{
8973		name:   "BSFQ",
8974		argLen: 1,
8975		asm:    x86.ABSFQ,
8976		reg: regInfo{
8977			inputs: []inputInfo{
8978				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8979			},
8980			outputs: []outputInfo{
8981				{1, 0},
8982				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8983			},
8984		},
8985	},
8986	{
8987		name:         "BSFL",
8988		argLen:       1,
8989		clobberFlags: true,
8990		asm:          x86.ABSFL,
8991		reg: regInfo{
8992			inputs: []inputInfo{
8993				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8994			},
8995			outputs: []outputInfo{
8996				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
8997			},
8998		},
8999	},
9000	{
9001		name:   "BSRQ",
9002		argLen: 1,
9003		asm:    x86.ABSRQ,
9004		reg: regInfo{
9005			inputs: []inputInfo{
9006				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9007			},
9008			outputs: []outputInfo{
9009				{1, 0},
9010				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9011			},
9012		},
9013	},
9014	{
9015		name:         "BSRL",
9016		argLen:       1,
9017		clobberFlags: true,
9018		asm:          x86.ABSRL,
9019		reg: regInfo{
9020			inputs: []inputInfo{
9021				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9022			},
9023			outputs: []outputInfo{
9024				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9025			},
9026		},
9027	},
9028	{
9029		name:         "CMOVQEQ",
9030		argLen:       3,
9031		resultInArg0: true,
9032		asm:          x86.ACMOVQEQ,
9033		reg: regInfo{
9034			inputs: []inputInfo{
9035				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9036				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9037			},
9038			outputs: []outputInfo{
9039				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9040			},
9041		},
9042	},
9043	{
9044		name:         "CMOVQNE",
9045		argLen:       3,
9046		resultInArg0: true,
9047		asm:          x86.ACMOVQNE,
9048		reg: regInfo{
9049			inputs: []inputInfo{
9050				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9051				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9052			},
9053			outputs: []outputInfo{
9054				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9055			},
9056		},
9057	},
9058	{
9059		name:         "CMOVQLT",
9060		argLen:       3,
9061		resultInArg0: true,
9062		asm:          x86.ACMOVQLT,
9063		reg: regInfo{
9064			inputs: []inputInfo{
9065				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9066				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9067			},
9068			outputs: []outputInfo{
9069				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9070			},
9071		},
9072	},
9073	{
9074		name:         "CMOVQGT",
9075		argLen:       3,
9076		resultInArg0: true,
9077		asm:          x86.ACMOVQGT,
9078		reg: regInfo{
9079			inputs: []inputInfo{
9080				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9081				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9082			},
9083			outputs: []outputInfo{
9084				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9085			},
9086		},
9087	},
9088	{
9089		name:         "CMOVQLE",
9090		argLen:       3,
9091		resultInArg0: true,
9092		asm:          x86.ACMOVQLE,
9093		reg: regInfo{
9094			inputs: []inputInfo{
9095				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9096				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9097			},
9098			outputs: []outputInfo{
9099				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9100			},
9101		},
9102	},
9103	{
9104		name:         "CMOVQGE",
9105		argLen:       3,
9106		resultInArg0: true,
9107		asm:          x86.ACMOVQGE,
9108		reg: regInfo{
9109			inputs: []inputInfo{
9110				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9111				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9112			},
9113			outputs: []outputInfo{
9114				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9115			},
9116		},
9117	},
9118	{
9119		name:         "CMOVQLS",
9120		argLen:       3,
9121		resultInArg0: true,
9122		asm:          x86.ACMOVQLS,
9123		reg: regInfo{
9124			inputs: []inputInfo{
9125				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9126				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9127			},
9128			outputs: []outputInfo{
9129				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9130			},
9131		},
9132	},
9133	{
9134		name:         "CMOVQHI",
9135		argLen:       3,
9136		resultInArg0: true,
9137		asm:          x86.ACMOVQHI,
9138		reg: regInfo{
9139			inputs: []inputInfo{
9140				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9141				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9142			},
9143			outputs: []outputInfo{
9144				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9145			},
9146		},
9147	},
9148	{
9149		name:         "CMOVQCC",
9150		argLen:       3,
9151		resultInArg0: true,
9152		asm:          x86.ACMOVQCC,
9153		reg: regInfo{
9154			inputs: []inputInfo{
9155				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9156				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9157			},
9158			outputs: []outputInfo{
9159				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9160			},
9161		},
9162	},
9163	{
9164		name:         "CMOVQCS",
9165		argLen:       3,
9166		resultInArg0: true,
9167		asm:          x86.ACMOVQCS,
9168		reg: regInfo{
9169			inputs: []inputInfo{
9170				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9171				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9172			},
9173			outputs: []outputInfo{
9174				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9175			},
9176		},
9177	},
9178	{
9179		name:         "CMOVLEQ",
9180		argLen:       3,
9181		resultInArg0: true,
9182		asm:          x86.ACMOVLEQ,
9183		reg: regInfo{
9184			inputs: []inputInfo{
9185				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9186				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9187			},
9188			outputs: []outputInfo{
9189				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9190			},
9191		},
9192	},
9193	{
9194		name:         "CMOVLNE",
9195		argLen:       3,
9196		resultInArg0: true,
9197		asm:          x86.ACMOVLNE,
9198		reg: regInfo{
9199			inputs: []inputInfo{
9200				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9201				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9202			},
9203			outputs: []outputInfo{
9204				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9205			},
9206		},
9207	},
9208	{
9209		name:         "CMOVLLT",
9210		argLen:       3,
9211		resultInArg0: true,
9212		asm:          x86.ACMOVLLT,
9213		reg: regInfo{
9214			inputs: []inputInfo{
9215				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9216				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9217			},
9218			outputs: []outputInfo{
9219				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9220			},
9221		},
9222	},
9223	{
9224		name:         "CMOVLGT",
9225		argLen:       3,
9226		resultInArg0: true,
9227		asm:          x86.ACMOVLGT,
9228		reg: regInfo{
9229			inputs: []inputInfo{
9230				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9231				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9232			},
9233			outputs: []outputInfo{
9234				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9235			},
9236		},
9237	},
9238	{
9239		name:         "CMOVLLE",
9240		argLen:       3,
9241		resultInArg0: true,
9242		asm:          x86.ACMOVLLE,
9243		reg: regInfo{
9244			inputs: []inputInfo{
9245				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9246				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9247			},
9248			outputs: []outputInfo{
9249				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9250			},
9251		},
9252	},
9253	{
9254		name:         "CMOVLGE",
9255		argLen:       3,
9256		resultInArg0: true,
9257		asm:          x86.ACMOVLGE,
9258		reg: regInfo{
9259			inputs: []inputInfo{
9260				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9261				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9262			},
9263			outputs: []outputInfo{
9264				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9265			},
9266		},
9267	},
9268	{
9269		name:         "CMOVLLS",
9270		argLen:       3,
9271		resultInArg0: true,
9272		asm:          x86.ACMOVLLS,
9273		reg: regInfo{
9274			inputs: []inputInfo{
9275				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9276				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9277			},
9278			outputs: []outputInfo{
9279				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9280			},
9281		},
9282	},
9283	{
9284		name:         "CMOVLHI",
9285		argLen:       3,
9286		resultInArg0: true,
9287		asm:          x86.ACMOVLHI,
9288		reg: regInfo{
9289			inputs: []inputInfo{
9290				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9291				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9292			},
9293			outputs: []outputInfo{
9294				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9295			},
9296		},
9297	},
9298	{
9299		name:         "CMOVLCC",
9300		argLen:       3,
9301		resultInArg0: true,
9302		asm:          x86.ACMOVLCC,
9303		reg: regInfo{
9304			inputs: []inputInfo{
9305				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9306				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9307			},
9308			outputs: []outputInfo{
9309				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9310			},
9311		},
9312	},
9313	{
9314		name:         "CMOVLCS",
9315		argLen:       3,
9316		resultInArg0: true,
9317		asm:          x86.ACMOVLCS,
9318		reg: regInfo{
9319			inputs: []inputInfo{
9320				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9321				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9322			},
9323			outputs: []outputInfo{
9324				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9325			},
9326		},
9327	},
9328	{
9329		name:         "CMOVWEQ",
9330		argLen:       3,
9331		resultInArg0: true,
9332		asm:          x86.ACMOVWEQ,
9333		reg: regInfo{
9334			inputs: []inputInfo{
9335				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9336				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9337			},
9338			outputs: []outputInfo{
9339				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9340			},
9341		},
9342	},
9343	{
9344		name:         "CMOVWNE",
9345		argLen:       3,
9346		resultInArg0: true,
9347		asm:          x86.ACMOVWNE,
9348		reg: regInfo{
9349			inputs: []inputInfo{
9350				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9351				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9352			},
9353			outputs: []outputInfo{
9354				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9355			},
9356		},
9357	},
9358	{
9359		name:         "CMOVWLT",
9360		argLen:       3,
9361		resultInArg0: true,
9362		asm:          x86.ACMOVWLT,
9363		reg: regInfo{
9364			inputs: []inputInfo{
9365				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9366				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9367			},
9368			outputs: []outputInfo{
9369				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9370			},
9371		},
9372	},
9373	{
9374		name:         "CMOVWGT",
9375		argLen:       3,
9376		resultInArg0: true,
9377		asm:          x86.ACMOVWGT,
9378		reg: regInfo{
9379			inputs: []inputInfo{
9380				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9381				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9382			},
9383			outputs: []outputInfo{
9384				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9385			},
9386		},
9387	},
9388	{
9389		name:         "CMOVWLE",
9390		argLen:       3,
9391		resultInArg0: true,
9392		asm:          x86.ACMOVWLE,
9393		reg: regInfo{
9394			inputs: []inputInfo{
9395				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9396				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9397			},
9398			outputs: []outputInfo{
9399				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9400			},
9401		},
9402	},
9403	{
9404		name:         "CMOVWGE",
9405		argLen:       3,
9406		resultInArg0: true,
9407		asm:          x86.ACMOVWGE,
9408		reg: regInfo{
9409			inputs: []inputInfo{
9410				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9411				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9412			},
9413			outputs: []outputInfo{
9414				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9415			},
9416		},
9417	},
9418	{
9419		name:         "CMOVWLS",
9420		argLen:       3,
9421		resultInArg0: true,
9422		asm:          x86.ACMOVWLS,
9423		reg: regInfo{
9424			inputs: []inputInfo{
9425				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9426				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9427			},
9428			outputs: []outputInfo{
9429				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9430			},
9431		},
9432	},
9433	{
9434		name:         "CMOVWHI",
9435		argLen:       3,
9436		resultInArg0: true,
9437		asm:          x86.ACMOVWHI,
9438		reg: regInfo{
9439			inputs: []inputInfo{
9440				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9441				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9442			},
9443			outputs: []outputInfo{
9444				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9445			},
9446		},
9447	},
9448	{
9449		name:         "CMOVWCC",
9450		argLen:       3,
9451		resultInArg0: true,
9452		asm:          x86.ACMOVWCC,
9453		reg: regInfo{
9454			inputs: []inputInfo{
9455				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9456				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9457			},
9458			outputs: []outputInfo{
9459				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9460			},
9461		},
9462	},
9463	{
9464		name:         "CMOVWCS",
9465		argLen:       3,
9466		resultInArg0: true,
9467		asm:          x86.ACMOVWCS,
9468		reg: regInfo{
9469			inputs: []inputInfo{
9470				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9471				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9472			},
9473			outputs: []outputInfo{
9474				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9475			},
9476		},
9477	},
9478	{
9479		name:         "CMOVQEQF",
9480		argLen:       3,
9481		resultInArg0: true,
9482		asm:          x86.ACMOVQNE,
9483		reg: regInfo{
9484			inputs: []inputInfo{
9485				{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9486				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9487			},
9488			clobbers: 1, // AX
9489			outputs: []outputInfo{
9490				{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9491			},
9492		},
9493	},
9494	{
9495		name:         "CMOVQNEF",
9496		argLen:       3,
9497		resultInArg0: true,
9498		asm:          x86.ACMOVQNE,
9499		reg: regInfo{
9500			inputs: []inputInfo{
9501				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9502				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9503			},
9504			outputs: []outputInfo{
9505				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9506			},
9507		},
9508	},
9509	{
9510		name:         "CMOVQGTF",
9511		argLen:       3,
9512		resultInArg0: true,
9513		asm:          x86.ACMOVQHI,
9514		reg: regInfo{
9515			inputs: []inputInfo{
9516				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9517				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9518			},
9519			outputs: []outputInfo{
9520				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9521			},
9522		},
9523	},
9524	{
9525		name:         "CMOVQGEF",
9526		argLen:       3,
9527		resultInArg0: true,
9528		asm:          x86.ACMOVQCC,
9529		reg: regInfo{
9530			inputs: []inputInfo{
9531				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9532				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9533			},
9534			outputs: []outputInfo{
9535				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9536			},
9537		},
9538	},
9539	{
9540		name:         "CMOVLEQF",
9541		argLen:       3,
9542		resultInArg0: true,
9543		asm:          x86.ACMOVLNE,
9544		reg: regInfo{
9545			inputs: []inputInfo{
9546				{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9547				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9548			},
9549			clobbers: 1, // AX
9550			outputs: []outputInfo{
9551				{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9552			},
9553		},
9554	},
9555	{
9556		name:         "CMOVLNEF",
9557		argLen:       3,
9558		resultInArg0: true,
9559		asm:          x86.ACMOVLNE,
9560		reg: regInfo{
9561			inputs: []inputInfo{
9562				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9563				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9564			},
9565			outputs: []outputInfo{
9566				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9567			},
9568		},
9569	},
9570	{
9571		name:         "CMOVLGTF",
9572		argLen:       3,
9573		resultInArg0: true,
9574		asm:          x86.ACMOVLHI,
9575		reg: regInfo{
9576			inputs: []inputInfo{
9577				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9578				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9579			},
9580			outputs: []outputInfo{
9581				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9582			},
9583		},
9584	},
9585	{
9586		name:         "CMOVLGEF",
9587		argLen:       3,
9588		resultInArg0: true,
9589		asm:          x86.ACMOVLCC,
9590		reg: regInfo{
9591			inputs: []inputInfo{
9592				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9593				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9594			},
9595			outputs: []outputInfo{
9596				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9597			},
9598		},
9599	},
9600	{
9601		name:         "CMOVWEQF",
9602		argLen:       3,
9603		resultInArg0: true,
9604		asm:          x86.ACMOVWNE,
9605		reg: regInfo{
9606			inputs: []inputInfo{
9607				{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9608				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9609			},
9610			clobbers: 1, // AX
9611			outputs: []outputInfo{
9612				{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9613			},
9614		},
9615	},
9616	{
9617		name:         "CMOVWNEF",
9618		argLen:       3,
9619		resultInArg0: true,
9620		asm:          x86.ACMOVWNE,
9621		reg: regInfo{
9622			inputs: []inputInfo{
9623				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9624				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9625			},
9626			outputs: []outputInfo{
9627				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9628			},
9629		},
9630	},
9631	{
9632		name:         "CMOVWGTF",
9633		argLen:       3,
9634		resultInArg0: true,
9635		asm:          x86.ACMOVWHI,
9636		reg: regInfo{
9637			inputs: []inputInfo{
9638				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9639				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9640			},
9641			outputs: []outputInfo{
9642				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9643			},
9644		},
9645	},
9646	{
9647		name:         "CMOVWGEF",
9648		argLen:       3,
9649		resultInArg0: true,
9650		asm:          x86.ACMOVWCC,
9651		reg: regInfo{
9652			inputs: []inputInfo{
9653				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9654				{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9655			},
9656			outputs: []outputInfo{
9657				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9658			},
9659		},
9660	},
9661	{
9662		name:         "BSWAPQ",
9663		argLen:       1,
9664		resultInArg0: true,
9665		clobberFlags: true,
9666		asm:          x86.ABSWAPQ,
9667		reg: regInfo{
9668			inputs: []inputInfo{
9669				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9670			},
9671			outputs: []outputInfo{
9672				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9673			},
9674		},
9675	},
9676	{
9677		name:         "BSWAPL",
9678		argLen:       1,
9679		resultInArg0: true,
9680		clobberFlags: true,
9681		asm:          x86.ABSWAPL,
9682		reg: regInfo{
9683			inputs: []inputInfo{
9684				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9685			},
9686			outputs: []outputInfo{
9687				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9688			},
9689		},
9690	},
9691	{
9692		name:         "POPCNTQ",
9693		argLen:       1,
9694		clobberFlags: true,
9695		asm:          x86.APOPCNTQ,
9696		reg: regInfo{
9697			inputs: []inputInfo{
9698				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9699			},
9700			outputs: []outputInfo{
9701				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9702			},
9703		},
9704	},
9705	{
9706		name:         "POPCNTL",
9707		argLen:       1,
9708		clobberFlags: true,
9709		asm:          x86.APOPCNTL,
9710		reg: regInfo{
9711			inputs: []inputInfo{
9712				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9713			},
9714			outputs: []outputInfo{
9715				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9716			},
9717		},
9718	},
9719	{
9720		name:   "SQRTSD",
9721		argLen: 1,
9722		asm:    x86.ASQRTSD,
9723		reg: regInfo{
9724			inputs: []inputInfo{
9725				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
9726			},
9727			outputs: []outputInfo{
9728				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
9729			},
9730		},
9731	},
9732	{
9733		name:    "ROUNDSD",
9734		auxType: auxInt8,
9735		argLen:  1,
9736		asm:     x86.AROUNDSD,
9737		reg: regInfo{
9738			inputs: []inputInfo{
9739				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
9740			},
9741			outputs: []outputInfo{
9742				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
9743			},
9744		},
9745	},
9746	{
9747		name:         "VFMADD231SD",
9748		argLen:       3,
9749		resultInArg0: true,
9750		asm:          x86.AVFMADD231SD,
9751		reg: regInfo{
9752			inputs: []inputInfo{
9753				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
9754				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
9755				{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
9756			},
9757			outputs: []outputInfo{
9758				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
9759			},
9760		},
9761	},
9762	{
9763		name:   "SBBQcarrymask",
9764		argLen: 1,
9765		asm:    x86.ASBBQ,
9766		reg: regInfo{
9767			outputs: []outputInfo{
9768				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9769			},
9770		},
9771	},
9772	{
9773		name:   "SBBLcarrymask",
9774		argLen: 1,
9775		asm:    x86.ASBBL,
9776		reg: regInfo{
9777			outputs: []outputInfo{
9778				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9779			},
9780		},
9781	},
9782	{
9783		name:   "SETEQ",
9784		argLen: 1,
9785		asm:    x86.ASETEQ,
9786		reg: regInfo{
9787			outputs: []outputInfo{
9788				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9789			},
9790		},
9791	},
9792	{
9793		name:   "SETNE",
9794		argLen: 1,
9795		asm:    x86.ASETNE,
9796		reg: regInfo{
9797			outputs: []outputInfo{
9798				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9799			},
9800		},
9801	},
9802	{
9803		name:   "SETL",
9804		argLen: 1,
9805		asm:    x86.ASETLT,
9806		reg: regInfo{
9807			outputs: []outputInfo{
9808				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9809			},
9810		},
9811	},
9812	{
9813		name:   "SETLE",
9814		argLen: 1,
9815		asm:    x86.ASETLE,
9816		reg: regInfo{
9817			outputs: []outputInfo{
9818				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9819			},
9820		},
9821	},
9822	{
9823		name:   "SETG",
9824		argLen: 1,
9825		asm:    x86.ASETGT,
9826		reg: regInfo{
9827			outputs: []outputInfo{
9828				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9829			},
9830		},
9831	},
9832	{
9833		name:   "SETGE",
9834		argLen: 1,
9835		asm:    x86.ASETGE,
9836		reg: regInfo{
9837			outputs: []outputInfo{
9838				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9839			},
9840		},
9841	},
9842	{
9843		name:   "SETB",
9844		argLen: 1,
9845		asm:    x86.ASETCS,
9846		reg: regInfo{
9847			outputs: []outputInfo{
9848				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9849			},
9850		},
9851	},
9852	{
9853		name:   "SETBE",
9854		argLen: 1,
9855		asm:    x86.ASETLS,
9856		reg: regInfo{
9857			outputs: []outputInfo{
9858				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9859			},
9860		},
9861	},
9862	{
9863		name:   "SETA",
9864		argLen: 1,
9865		asm:    x86.ASETHI,
9866		reg: regInfo{
9867			outputs: []outputInfo{
9868				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9869			},
9870		},
9871	},
9872	{
9873		name:   "SETAE",
9874		argLen: 1,
9875		asm:    x86.ASETCC,
9876		reg: regInfo{
9877			outputs: []outputInfo{
9878				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9879			},
9880		},
9881	},
9882	{
9883		name:   "SETO",
9884		argLen: 1,
9885		asm:    x86.ASETOS,
9886		reg: regInfo{
9887			outputs: []outputInfo{
9888				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
9889			},
9890		},
9891	},
9892	{
9893		name:           "SETEQstore",
9894		auxType:        auxSymOff,
9895		argLen:         3,
9896		faultOnNilArg0: true,
9897		symEffect:      SymWrite,
9898		asm:            x86.ASETEQ,
9899		reg: regInfo{
9900			inputs: []inputInfo{
9901				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
9902			},
9903		},
9904	},
9905	{
9906		name:           "SETNEstore",
9907		auxType:        auxSymOff,
9908		argLen:         3,
9909		faultOnNilArg0: true,
9910		symEffect:      SymWrite,
9911		asm:            x86.ASETNE,
9912		reg: regInfo{
9913			inputs: []inputInfo{
9914				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
9915			},
9916		},
9917	},
9918	{
9919		name:           "SETLstore",
9920		auxType:        auxSymOff,
9921		argLen:         3,
9922		faultOnNilArg0: true,
9923		symEffect:      SymWrite,
9924		asm:            x86.ASETLT,
9925		reg: regInfo{
9926			inputs: []inputInfo{
9927				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
9928			},
9929		},
9930	},
9931	{
9932		name:           "SETLEstore",
9933		auxType:        auxSymOff,
9934		argLen:         3,
9935		faultOnNilArg0: true,
9936		symEffect:      SymWrite,
9937		asm:            x86.ASETLE,
9938		reg: regInfo{
9939			inputs: []inputInfo{
9940				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
9941			},
9942		},
9943	},
9944	{
9945		name:           "SETGstore",
9946		auxType:        auxSymOff,
9947		argLen:         3,
9948		faultOnNilArg0: true,
9949		symEffect:      SymWrite,
9950		asm:            x86.ASETGT,
9951		reg: regInfo{
9952			inputs: []inputInfo{
9953				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
9954			},
9955		},
9956	},
9957	{
9958		name:           "SETGEstore",
9959		auxType:        auxSymOff,
9960		argLen:         3,
9961		faultOnNilArg0: true,
9962		symEffect:      SymWrite,
9963		asm:            x86.ASETGE,
9964		reg: regInfo{
9965			inputs: []inputInfo{
9966				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
9967			},
9968		},
9969	},
9970	{
9971		name:           "SETBstore",
9972		auxType:        auxSymOff,
9973		argLen:         3,
9974		faultOnNilArg0: true,
9975		symEffect:      SymWrite,
9976		asm:            x86.ASETCS,
9977		reg: regInfo{
9978			inputs: []inputInfo{
9979				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
9980			},
9981		},
9982	},
9983	{
9984		name:           "SETBEstore",
9985		auxType:        auxSymOff,
9986		argLen:         3,
9987		faultOnNilArg0: true,
9988		symEffect:      SymWrite,
9989		asm:            x86.ASETLS,
9990		reg: regInfo{
9991			inputs: []inputInfo{
9992				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
9993			},
9994		},
9995	},
9996	{
9997		name:           "SETAstore",
9998		auxType:        auxSymOff,
9999		argLen:         3,
10000		faultOnNilArg0: true,
10001		symEffect:      SymWrite,
10002		asm:            x86.ASETHI,
10003		reg: regInfo{
10004			inputs: []inputInfo{
10005				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10006			},
10007		},
10008	},
10009	{
10010		name:           "SETAEstore",
10011		auxType:        auxSymOff,
10012		argLen:         3,
10013		faultOnNilArg0: true,
10014		symEffect:      SymWrite,
10015		asm:            x86.ASETCC,
10016		reg: regInfo{
10017			inputs: []inputInfo{
10018				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10019			},
10020		},
10021	},
10022	{
10023		name:         "SETEQF",
10024		argLen:       1,
10025		clobberFlags: true,
10026		asm:          x86.ASETEQ,
10027		reg: regInfo{
10028			clobbers: 1, // AX
10029			outputs: []outputInfo{
10030				{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10031			},
10032		},
10033	},
10034	{
10035		name:         "SETNEF",
10036		argLen:       1,
10037		clobberFlags: true,
10038		asm:          x86.ASETNE,
10039		reg: regInfo{
10040			clobbers: 1, // AX
10041			outputs: []outputInfo{
10042				{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10043			},
10044		},
10045	},
10046	{
10047		name:   "SETORD",
10048		argLen: 1,
10049		asm:    x86.ASETPC,
10050		reg: regInfo{
10051			outputs: []outputInfo{
10052				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10053			},
10054		},
10055	},
10056	{
10057		name:   "SETNAN",
10058		argLen: 1,
10059		asm:    x86.ASETPS,
10060		reg: regInfo{
10061			outputs: []outputInfo{
10062				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10063			},
10064		},
10065	},
10066	{
10067		name:   "SETGF",
10068		argLen: 1,
10069		asm:    x86.ASETHI,
10070		reg: regInfo{
10071			outputs: []outputInfo{
10072				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10073			},
10074		},
10075	},
10076	{
10077		name:   "SETGEF",
10078		argLen: 1,
10079		asm:    x86.ASETCC,
10080		reg: regInfo{
10081			outputs: []outputInfo{
10082				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10083			},
10084		},
10085	},
10086	{
10087		name:   "MOVBQSX",
10088		argLen: 1,
10089		asm:    x86.AMOVBQSX,
10090		reg: regInfo{
10091			inputs: []inputInfo{
10092				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10093			},
10094			outputs: []outputInfo{
10095				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10096			},
10097		},
10098	},
10099	{
10100		name:   "MOVBQZX",
10101		argLen: 1,
10102		asm:    x86.AMOVBLZX,
10103		reg: regInfo{
10104			inputs: []inputInfo{
10105				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10106			},
10107			outputs: []outputInfo{
10108				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10109			},
10110		},
10111	},
10112	{
10113		name:   "MOVWQSX",
10114		argLen: 1,
10115		asm:    x86.AMOVWQSX,
10116		reg: regInfo{
10117			inputs: []inputInfo{
10118				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10119			},
10120			outputs: []outputInfo{
10121				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10122			},
10123		},
10124	},
10125	{
10126		name:   "MOVWQZX",
10127		argLen: 1,
10128		asm:    x86.AMOVWLZX,
10129		reg: regInfo{
10130			inputs: []inputInfo{
10131				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10132			},
10133			outputs: []outputInfo{
10134				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10135			},
10136		},
10137	},
10138	{
10139		name:   "MOVLQSX",
10140		argLen: 1,
10141		asm:    x86.AMOVLQSX,
10142		reg: regInfo{
10143			inputs: []inputInfo{
10144				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10145			},
10146			outputs: []outputInfo{
10147				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10148			},
10149		},
10150	},
10151	{
10152		name:   "MOVLQZX",
10153		argLen: 1,
10154		asm:    x86.AMOVL,
10155		reg: regInfo{
10156			inputs: []inputInfo{
10157				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10158			},
10159			outputs: []outputInfo{
10160				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10161			},
10162		},
10163	},
10164	{
10165		name:              "MOVLconst",
10166		auxType:           auxInt32,
10167		argLen:            0,
10168		rematerializeable: true,
10169		asm:               x86.AMOVL,
10170		reg: regInfo{
10171			outputs: []outputInfo{
10172				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10173			},
10174		},
10175	},
10176	{
10177		name:              "MOVQconst",
10178		auxType:           auxInt64,
10179		argLen:            0,
10180		rematerializeable: true,
10181		asm:               x86.AMOVQ,
10182		reg: regInfo{
10183			outputs: []outputInfo{
10184				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10185			},
10186		},
10187	},
10188	{
10189		name:   "CVTTSD2SL",
10190		argLen: 1,
10191		asm:    x86.ACVTTSD2SL,
10192		reg: regInfo{
10193			inputs: []inputInfo{
10194				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10195			},
10196			outputs: []outputInfo{
10197				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10198			},
10199		},
10200	},
10201	{
10202		name:   "CVTTSD2SQ",
10203		argLen: 1,
10204		asm:    x86.ACVTTSD2SQ,
10205		reg: regInfo{
10206			inputs: []inputInfo{
10207				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10208			},
10209			outputs: []outputInfo{
10210				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10211			},
10212		},
10213	},
10214	{
10215		name:   "CVTTSS2SL",
10216		argLen: 1,
10217		asm:    x86.ACVTTSS2SL,
10218		reg: regInfo{
10219			inputs: []inputInfo{
10220				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10221			},
10222			outputs: []outputInfo{
10223				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10224			},
10225		},
10226	},
10227	{
10228		name:   "CVTTSS2SQ",
10229		argLen: 1,
10230		asm:    x86.ACVTTSS2SQ,
10231		reg: regInfo{
10232			inputs: []inputInfo{
10233				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10234			},
10235			outputs: []outputInfo{
10236				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10237			},
10238		},
10239	},
10240	{
10241		name:   "CVTSL2SS",
10242		argLen: 1,
10243		asm:    x86.ACVTSL2SS,
10244		reg: regInfo{
10245			inputs: []inputInfo{
10246				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10247			},
10248			outputs: []outputInfo{
10249				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10250			},
10251		},
10252	},
10253	{
10254		name:   "CVTSL2SD",
10255		argLen: 1,
10256		asm:    x86.ACVTSL2SD,
10257		reg: regInfo{
10258			inputs: []inputInfo{
10259				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10260			},
10261			outputs: []outputInfo{
10262				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10263			},
10264		},
10265	},
10266	{
10267		name:   "CVTSQ2SS",
10268		argLen: 1,
10269		asm:    x86.ACVTSQ2SS,
10270		reg: regInfo{
10271			inputs: []inputInfo{
10272				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10273			},
10274			outputs: []outputInfo{
10275				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10276			},
10277		},
10278	},
10279	{
10280		name:   "CVTSQ2SD",
10281		argLen: 1,
10282		asm:    x86.ACVTSQ2SD,
10283		reg: regInfo{
10284			inputs: []inputInfo{
10285				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10286			},
10287			outputs: []outputInfo{
10288				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10289			},
10290		},
10291	},
10292	{
10293		name:   "CVTSD2SS",
10294		argLen: 1,
10295		asm:    x86.ACVTSD2SS,
10296		reg: regInfo{
10297			inputs: []inputInfo{
10298				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10299			},
10300			outputs: []outputInfo{
10301				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10302			},
10303		},
10304	},
10305	{
10306		name:   "CVTSS2SD",
10307		argLen: 1,
10308		asm:    x86.ACVTSS2SD,
10309		reg: regInfo{
10310			inputs: []inputInfo{
10311				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10312			},
10313			outputs: []outputInfo{
10314				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10315			},
10316		},
10317	},
10318	{
10319		name:   "MOVQi2f",
10320		argLen: 1,
10321		reg: regInfo{
10322			inputs: []inputInfo{
10323				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10324			},
10325			outputs: []outputInfo{
10326				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10327			},
10328		},
10329	},
10330	{
10331		name:   "MOVQf2i",
10332		argLen: 1,
10333		reg: regInfo{
10334			inputs: []inputInfo{
10335				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10336			},
10337			outputs: []outputInfo{
10338				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10339			},
10340		},
10341	},
10342	{
10343		name:   "MOVLi2f",
10344		argLen: 1,
10345		reg: regInfo{
10346			inputs: []inputInfo{
10347				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10348			},
10349			outputs: []outputInfo{
10350				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10351			},
10352		},
10353	},
10354	{
10355		name:   "MOVLf2i",
10356		argLen: 1,
10357		reg: regInfo{
10358			inputs: []inputInfo{
10359				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10360			},
10361			outputs: []outputInfo{
10362				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10363			},
10364		},
10365	},
10366	{
10367		name:         "PXOR",
10368		argLen:       2,
10369		commutative:  true,
10370		resultInArg0: true,
10371		asm:          x86.APXOR,
10372		reg: regInfo{
10373			inputs: []inputInfo{
10374				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10375				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10376			},
10377			outputs: []outputInfo{
10378				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10379			},
10380		},
10381	},
10382	{
10383		name:              "LEAQ",
10384		auxType:           auxSymOff,
10385		argLen:            1,
10386		rematerializeable: true,
10387		symEffect:         SymAddr,
10388		asm:               x86.ALEAQ,
10389		reg: regInfo{
10390			inputs: []inputInfo{
10391				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10392			},
10393			outputs: []outputInfo{
10394				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10395			},
10396		},
10397	},
10398	{
10399		name:              "LEAL",
10400		auxType:           auxSymOff,
10401		argLen:            1,
10402		rematerializeable: true,
10403		symEffect:         SymAddr,
10404		asm:               x86.ALEAL,
10405		reg: regInfo{
10406			inputs: []inputInfo{
10407				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10408			},
10409			outputs: []outputInfo{
10410				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10411			},
10412		},
10413	},
10414	{
10415		name:              "LEAW",
10416		auxType:           auxSymOff,
10417		argLen:            1,
10418		rematerializeable: true,
10419		symEffect:         SymAddr,
10420		asm:               x86.ALEAW,
10421		reg: regInfo{
10422			inputs: []inputInfo{
10423				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10424			},
10425			outputs: []outputInfo{
10426				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10427			},
10428		},
10429	},
10430	{
10431		name:        "LEAQ1",
10432		auxType:     auxSymOff,
10433		argLen:      2,
10434		commutative: true,
10435		symEffect:   SymAddr,
10436		asm:         x86.ALEAQ,
10437		scale:       1,
10438		reg: regInfo{
10439			inputs: []inputInfo{
10440				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10441				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10442			},
10443			outputs: []outputInfo{
10444				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10445			},
10446		},
10447	},
10448	{
10449		name:        "LEAL1",
10450		auxType:     auxSymOff,
10451		argLen:      2,
10452		commutative: true,
10453		symEffect:   SymAddr,
10454		asm:         x86.ALEAL,
10455		scale:       1,
10456		reg: regInfo{
10457			inputs: []inputInfo{
10458				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10459				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10460			},
10461			outputs: []outputInfo{
10462				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10463			},
10464		},
10465	},
10466	{
10467		name:        "LEAW1",
10468		auxType:     auxSymOff,
10469		argLen:      2,
10470		commutative: true,
10471		symEffect:   SymAddr,
10472		asm:         x86.ALEAW,
10473		scale:       1,
10474		reg: regInfo{
10475			inputs: []inputInfo{
10476				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10477				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10478			},
10479			outputs: []outputInfo{
10480				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10481			},
10482		},
10483	},
10484	{
10485		name:      "LEAQ2",
10486		auxType:   auxSymOff,
10487		argLen:    2,
10488		symEffect: SymAddr,
10489		asm:       x86.ALEAQ,
10490		scale:     2,
10491		reg: regInfo{
10492			inputs: []inputInfo{
10493				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10494				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10495			},
10496			outputs: []outputInfo{
10497				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10498			},
10499		},
10500	},
10501	{
10502		name:      "LEAL2",
10503		auxType:   auxSymOff,
10504		argLen:    2,
10505		symEffect: SymAddr,
10506		asm:       x86.ALEAL,
10507		scale:     2,
10508		reg: regInfo{
10509			inputs: []inputInfo{
10510				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10511				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10512			},
10513			outputs: []outputInfo{
10514				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10515			},
10516		},
10517	},
10518	{
10519		name:      "LEAW2",
10520		auxType:   auxSymOff,
10521		argLen:    2,
10522		symEffect: SymAddr,
10523		asm:       x86.ALEAW,
10524		scale:     2,
10525		reg: regInfo{
10526			inputs: []inputInfo{
10527				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10528				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10529			},
10530			outputs: []outputInfo{
10531				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10532			},
10533		},
10534	},
10535	{
10536		name:      "LEAQ4",
10537		auxType:   auxSymOff,
10538		argLen:    2,
10539		symEffect: SymAddr,
10540		asm:       x86.ALEAQ,
10541		scale:     4,
10542		reg: regInfo{
10543			inputs: []inputInfo{
10544				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10545				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10546			},
10547			outputs: []outputInfo{
10548				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10549			},
10550		},
10551	},
10552	{
10553		name:      "LEAL4",
10554		auxType:   auxSymOff,
10555		argLen:    2,
10556		symEffect: SymAddr,
10557		asm:       x86.ALEAL,
10558		scale:     4,
10559		reg: regInfo{
10560			inputs: []inputInfo{
10561				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10562				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10563			},
10564			outputs: []outputInfo{
10565				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10566			},
10567		},
10568	},
10569	{
10570		name:      "LEAW4",
10571		auxType:   auxSymOff,
10572		argLen:    2,
10573		symEffect: SymAddr,
10574		asm:       x86.ALEAW,
10575		scale:     4,
10576		reg: regInfo{
10577			inputs: []inputInfo{
10578				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10579				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10580			},
10581			outputs: []outputInfo{
10582				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10583			},
10584		},
10585	},
10586	{
10587		name:      "LEAQ8",
10588		auxType:   auxSymOff,
10589		argLen:    2,
10590		symEffect: SymAddr,
10591		asm:       x86.ALEAQ,
10592		scale:     8,
10593		reg: regInfo{
10594			inputs: []inputInfo{
10595				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10596				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10597			},
10598			outputs: []outputInfo{
10599				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10600			},
10601		},
10602	},
10603	{
10604		name:      "LEAL8",
10605		auxType:   auxSymOff,
10606		argLen:    2,
10607		symEffect: SymAddr,
10608		asm:       x86.ALEAL,
10609		scale:     8,
10610		reg: regInfo{
10611			inputs: []inputInfo{
10612				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10613				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10614			},
10615			outputs: []outputInfo{
10616				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10617			},
10618		},
10619	},
10620	{
10621		name:      "LEAW8",
10622		auxType:   auxSymOff,
10623		argLen:    2,
10624		symEffect: SymAddr,
10625		asm:       x86.ALEAW,
10626		scale:     8,
10627		reg: regInfo{
10628			inputs: []inputInfo{
10629				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10630				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10631			},
10632			outputs: []outputInfo{
10633				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10634			},
10635		},
10636	},
10637	{
10638		name:           "MOVBload",
10639		auxType:        auxSymOff,
10640		argLen:         2,
10641		faultOnNilArg0: true,
10642		symEffect:      SymRead,
10643		asm:            x86.AMOVBLZX,
10644		reg: regInfo{
10645			inputs: []inputInfo{
10646				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10647			},
10648			outputs: []outputInfo{
10649				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10650			},
10651		},
10652	},
10653	{
10654		name:           "MOVBQSXload",
10655		auxType:        auxSymOff,
10656		argLen:         2,
10657		faultOnNilArg0: true,
10658		symEffect:      SymRead,
10659		asm:            x86.AMOVBQSX,
10660		reg: regInfo{
10661			inputs: []inputInfo{
10662				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10663			},
10664			outputs: []outputInfo{
10665				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10666			},
10667		},
10668	},
10669	{
10670		name:           "MOVWload",
10671		auxType:        auxSymOff,
10672		argLen:         2,
10673		faultOnNilArg0: true,
10674		symEffect:      SymRead,
10675		asm:            x86.AMOVWLZX,
10676		reg: regInfo{
10677			inputs: []inputInfo{
10678				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10679			},
10680			outputs: []outputInfo{
10681				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10682			},
10683		},
10684	},
10685	{
10686		name:           "MOVWQSXload",
10687		auxType:        auxSymOff,
10688		argLen:         2,
10689		faultOnNilArg0: true,
10690		symEffect:      SymRead,
10691		asm:            x86.AMOVWQSX,
10692		reg: regInfo{
10693			inputs: []inputInfo{
10694				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10695			},
10696			outputs: []outputInfo{
10697				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10698			},
10699		},
10700	},
10701	{
10702		name:           "MOVLload",
10703		auxType:        auxSymOff,
10704		argLen:         2,
10705		faultOnNilArg0: true,
10706		symEffect:      SymRead,
10707		asm:            x86.AMOVL,
10708		reg: regInfo{
10709			inputs: []inputInfo{
10710				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10711			},
10712			outputs: []outputInfo{
10713				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10714			},
10715		},
10716	},
10717	{
10718		name:           "MOVLQSXload",
10719		auxType:        auxSymOff,
10720		argLen:         2,
10721		faultOnNilArg0: true,
10722		symEffect:      SymRead,
10723		asm:            x86.AMOVLQSX,
10724		reg: regInfo{
10725			inputs: []inputInfo{
10726				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10727			},
10728			outputs: []outputInfo{
10729				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10730			},
10731		},
10732	},
10733	{
10734		name:           "MOVQload",
10735		auxType:        auxSymOff,
10736		argLen:         2,
10737		faultOnNilArg0: true,
10738		symEffect:      SymRead,
10739		asm:            x86.AMOVQ,
10740		reg: regInfo{
10741			inputs: []inputInfo{
10742				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10743			},
10744			outputs: []outputInfo{
10745				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10746			},
10747		},
10748	},
10749	{
10750		name:           "MOVBstore",
10751		auxType:        auxSymOff,
10752		argLen:         3,
10753		faultOnNilArg0: true,
10754		symEffect:      SymWrite,
10755		asm:            x86.AMOVB,
10756		reg: regInfo{
10757			inputs: []inputInfo{
10758				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10759				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10760			},
10761		},
10762	},
10763	{
10764		name:           "MOVWstore",
10765		auxType:        auxSymOff,
10766		argLen:         3,
10767		faultOnNilArg0: true,
10768		symEffect:      SymWrite,
10769		asm:            x86.AMOVW,
10770		reg: regInfo{
10771			inputs: []inputInfo{
10772				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10773				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10774			},
10775		},
10776	},
10777	{
10778		name:           "MOVLstore",
10779		auxType:        auxSymOff,
10780		argLen:         3,
10781		faultOnNilArg0: true,
10782		symEffect:      SymWrite,
10783		asm:            x86.AMOVL,
10784		reg: regInfo{
10785			inputs: []inputInfo{
10786				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10787				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10788			},
10789		},
10790	},
10791	{
10792		name:           "MOVQstore",
10793		auxType:        auxSymOff,
10794		argLen:         3,
10795		faultOnNilArg0: true,
10796		symEffect:      SymWrite,
10797		asm:            x86.AMOVQ,
10798		reg: regInfo{
10799			inputs: []inputInfo{
10800				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10801				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10802			},
10803		},
10804	},
10805	{
10806		name:           "MOVOload",
10807		auxType:        auxSymOff,
10808		argLen:         2,
10809		faultOnNilArg0: true,
10810		symEffect:      SymRead,
10811		asm:            x86.AMOVUPS,
10812		reg: regInfo{
10813			inputs: []inputInfo{
10814				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10815			},
10816			outputs: []outputInfo{
10817				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10818			},
10819		},
10820	},
10821	{
10822		name:           "MOVOstore",
10823		auxType:        auxSymOff,
10824		argLen:         3,
10825		faultOnNilArg0: true,
10826		symEffect:      SymWrite,
10827		asm:            x86.AMOVUPS,
10828		reg: regInfo{
10829			inputs: []inputInfo{
10830				{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
10831				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10832			},
10833		},
10834	},
10835	{
10836		name:        "MOVBloadidx1",
10837		auxType:     auxSymOff,
10838		argLen:      3,
10839		commutative: true,
10840		symEffect:   SymRead,
10841		asm:         x86.AMOVBLZX,
10842		scale:       1,
10843		reg: regInfo{
10844			inputs: []inputInfo{
10845				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10846				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10847			},
10848			outputs: []outputInfo{
10849				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10850			},
10851		},
10852	},
10853	{
10854		name:        "MOVWloadidx1",
10855		auxType:     auxSymOff,
10856		argLen:      3,
10857		commutative: true,
10858		symEffect:   SymRead,
10859		asm:         x86.AMOVWLZX,
10860		scale:       1,
10861		reg: regInfo{
10862			inputs: []inputInfo{
10863				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10864				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10865			},
10866			outputs: []outputInfo{
10867				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10868			},
10869		},
10870	},
10871	{
10872		name:      "MOVWloadidx2",
10873		auxType:   auxSymOff,
10874		argLen:    3,
10875		symEffect: SymRead,
10876		asm:       x86.AMOVWLZX,
10877		scale:     2,
10878		reg: regInfo{
10879			inputs: []inputInfo{
10880				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10881				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10882			},
10883			outputs: []outputInfo{
10884				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10885			},
10886		},
10887	},
10888	{
10889		name:        "MOVLloadidx1",
10890		auxType:     auxSymOff,
10891		argLen:      3,
10892		commutative: true,
10893		symEffect:   SymRead,
10894		asm:         x86.AMOVL,
10895		scale:       1,
10896		reg: regInfo{
10897			inputs: []inputInfo{
10898				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10899				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10900			},
10901			outputs: []outputInfo{
10902				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10903			},
10904		},
10905	},
10906	{
10907		name:      "MOVLloadidx4",
10908		auxType:   auxSymOff,
10909		argLen:    3,
10910		symEffect: SymRead,
10911		asm:       x86.AMOVL,
10912		scale:     4,
10913		reg: regInfo{
10914			inputs: []inputInfo{
10915				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10916				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10917			},
10918			outputs: []outputInfo{
10919				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10920			},
10921		},
10922	},
10923	{
10924		name:      "MOVLloadidx8",
10925		auxType:   auxSymOff,
10926		argLen:    3,
10927		symEffect: SymRead,
10928		asm:       x86.AMOVL,
10929		scale:     8,
10930		reg: regInfo{
10931			inputs: []inputInfo{
10932				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10933				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10934			},
10935			outputs: []outputInfo{
10936				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10937			},
10938		},
10939	},
10940	{
10941		name:        "MOVQloadidx1",
10942		auxType:     auxSymOff,
10943		argLen:      3,
10944		commutative: true,
10945		symEffect:   SymRead,
10946		asm:         x86.AMOVQ,
10947		scale:       1,
10948		reg: regInfo{
10949			inputs: []inputInfo{
10950				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10951				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10952			},
10953			outputs: []outputInfo{
10954				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10955			},
10956		},
10957	},
10958	{
10959		name:      "MOVQloadidx8",
10960		auxType:   auxSymOff,
10961		argLen:    3,
10962		symEffect: SymRead,
10963		asm:       x86.AMOVQ,
10964		scale:     8,
10965		reg: regInfo{
10966			inputs: []inputInfo{
10967				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10968				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10969			},
10970			outputs: []outputInfo{
10971				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10972			},
10973		},
10974	},
10975	{
10976		name:      "MOVBstoreidx1",
10977		auxType:   auxSymOff,
10978		argLen:    4,
10979		symEffect: SymWrite,
10980		asm:       x86.AMOVB,
10981		scale:     1,
10982		reg: regInfo{
10983			inputs: []inputInfo{
10984				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10985				{2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
10986				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
10987			},
10988		},
10989	},
10990	{
10991		name:      "MOVWstoreidx1",
10992		auxType:   auxSymOff,
10993		argLen:    4,
10994		symEffect: SymWrite,
10995		asm:       x86.AMOVW,
10996		scale:     1,
10997		reg: regInfo{
10998			inputs: []inputInfo{
10999				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11000				{2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11001				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11002			},
11003		},
11004	},
11005	{
11006		name:      "MOVWstoreidx2",
11007		auxType:   auxSymOff,
11008		argLen:    4,
11009		symEffect: SymWrite,
11010		asm:       x86.AMOVW,
11011		scale:     2,
11012		reg: regInfo{
11013			inputs: []inputInfo{
11014				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11015				{2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11016				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11017			},
11018		},
11019	},
11020	{
11021		name:      "MOVLstoreidx1",
11022		auxType:   auxSymOff,
11023		argLen:    4,
11024		symEffect: SymWrite,
11025		asm:       x86.AMOVL,
11026		scale:     1,
11027		reg: regInfo{
11028			inputs: []inputInfo{
11029				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11030				{2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11031				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11032			},
11033		},
11034	},
11035	{
11036		name:      "MOVLstoreidx4",
11037		auxType:   auxSymOff,
11038		argLen:    4,
11039		symEffect: SymWrite,
11040		asm:       x86.AMOVL,
11041		scale:     4,
11042		reg: regInfo{
11043			inputs: []inputInfo{
11044				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11045				{2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11046				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11047			},
11048		},
11049	},
11050	{
11051		name:      "MOVLstoreidx8",
11052		auxType:   auxSymOff,
11053		argLen:    4,
11054		symEffect: SymWrite,
11055		asm:       x86.AMOVL,
11056		scale:     8,
11057		reg: regInfo{
11058			inputs: []inputInfo{
11059				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11060				{2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11061				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11062			},
11063		},
11064	},
11065	{
11066		name:      "MOVQstoreidx1",
11067		auxType:   auxSymOff,
11068		argLen:    4,
11069		symEffect: SymWrite,
11070		asm:       x86.AMOVQ,
11071		scale:     1,
11072		reg: regInfo{
11073			inputs: []inputInfo{
11074				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11075				{2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11076				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11077			},
11078		},
11079	},
11080	{
11081		name:      "MOVQstoreidx8",
11082		auxType:   auxSymOff,
11083		argLen:    4,
11084		symEffect: SymWrite,
11085		asm:       x86.AMOVQ,
11086		scale:     8,
11087		reg: regInfo{
11088			inputs: []inputInfo{
11089				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11090				{2, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11091				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11092			},
11093		},
11094	},
11095	{
11096		name:           "MOVBstoreconst",
11097		auxType:        auxSymValAndOff,
11098		argLen:         2,
11099		faultOnNilArg0: true,
11100		symEffect:      SymWrite,
11101		asm:            x86.AMOVB,
11102		reg: regInfo{
11103			inputs: []inputInfo{
11104				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11105			},
11106		},
11107	},
11108	{
11109		name:           "MOVWstoreconst",
11110		auxType:        auxSymValAndOff,
11111		argLen:         2,
11112		faultOnNilArg0: true,
11113		symEffect:      SymWrite,
11114		asm:            x86.AMOVW,
11115		reg: regInfo{
11116			inputs: []inputInfo{
11117				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11118			},
11119		},
11120	},
11121	{
11122		name:           "MOVLstoreconst",
11123		auxType:        auxSymValAndOff,
11124		argLen:         2,
11125		faultOnNilArg0: true,
11126		symEffect:      SymWrite,
11127		asm:            x86.AMOVL,
11128		reg: regInfo{
11129			inputs: []inputInfo{
11130				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11131			},
11132		},
11133	},
11134	{
11135		name:           "MOVQstoreconst",
11136		auxType:        auxSymValAndOff,
11137		argLen:         2,
11138		faultOnNilArg0: true,
11139		symEffect:      SymWrite,
11140		asm:            x86.AMOVQ,
11141		reg: regInfo{
11142			inputs: []inputInfo{
11143				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11144			},
11145		},
11146	},
11147	{
11148		name:      "MOVBstoreconstidx1",
11149		auxType:   auxSymValAndOff,
11150		argLen:    3,
11151		symEffect: SymWrite,
11152		asm:       x86.AMOVB,
11153		scale:     1,
11154		reg: regInfo{
11155			inputs: []inputInfo{
11156				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11157				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11158			},
11159		},
11160	},
11161	{
11162		name:      "MOVWstoreconstidx1",
11163		auxType:   auxSymValAndOff,
11164		argLen:    3,
11165		symEffect: SymWrite,
11166		asm:       x86.AMOVW,
11167		scale:     1,
11168		reg: regInfo{
11169			inputs: []inputInfo{
11170				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11171				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11172			},
11173		},
11174	},
11175	{
11176		name:      "MOVWstoreconstidx2",
11177		auxType:   auxSymValAndOff,
11178		argLen:    3,
11179		symEffect: SymWrite,
11180		asm:       x86.AMOVW,
11181		scale:     2,
11182		reg: regInfo{
11183			inputs: []inputInfo{
11184				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11185				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11186			},
11187		},
11188	},
11189	{
11190		name:      "MOVLstoreconstidx1",
11191		auxType:   auxSymValAndOff,
11192		argLen:    3,
11193		symEffect: SymWrite,
11194		asm:       x86.AMOVL,
11195		scale:     1,
11196		reg: regInfo{
11197			inputs: []inputInfo{
11198				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11199				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11200			},
11201		},
11202	},
11203	{
11204		name:      "MOVLstoreconstidx4",
11205		auxType:   auxSymValAndOff,
11206		argLen:    3,
11207		symEffect: SymWrite,
11208		asm:       x86.AMOVL,
11209		scale:     4,
11210		reg: regInfo{
11211			inputs: []inputInfo{
11212				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11213				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11214			},
11215		},
11216	},
11217	{
11218		name:      "MOVQstoreconstidx1",
11219		auxType:   auxSymValAndOff,
11220		argLen:    3,
11221		symEffect: SymWrite,
11222		asm:       x86.AMOVQ,
11223		scale:     1,
11224		reg: regInfo{
11225			inputs: []inputInfo{
11226				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11227				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11228			},
11229		},
11230	},
11231	{
11232		name:      "MOVQstoreconstidx8",
11233		auxType:   auxSymValAndOff,
11234		argLen:    3,
11235		symEffect: SymWrite,
11236		asm:       x86.AMOVQ,
11237		scale:     8,
11238		reg: regInfo{
11239			inputs: []inputInfo{
11240				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11241				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11242			},
11243		},
11244	},
11245	{
11246		name:           "DUFFZERO",
11247		auxType:        auxInt64,
11248		argLen:         3,
11249		faultOnNilArg0: true,
11250		reg: regInfo{
11251			inputs: []inputInfo{
11252				{0, 128},   // DI
11253				{1, 65536}, // X0
11254			},
11255			clobbers: 128, // DI
11256		},
11257	},
11258	{
11259		name:              "MOVOconst",
11260		auxType:           auxInt128,
11261		argLen:            0,
11262		rematerializeable: true,
11263		reg: regInfo{
11264			outputs: []outputInfo{
11265				{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
11266			},
11267		},
11268	},
11269	{
11270		name:           "REPSTOSQ",
11271		argLen:         4,
11272		faultOnNilArg0: true,
11273		reg: regInfo{
11274			inputs: []inputInfo{
11275				{0, 128}, // DI
11276				{1, 2},   // CX
11277				{2, 1},   // AX
11278			},
11279			clobbers: 130, // CX DI
11280		},
11281	},
11282	{
11283		name:         "CALLstatic",
11284		auxType:      auxSymOff,
11285		argLen:       1,
11286		clobberFlags: true,
11287		call:         true,
11288		symEffect:    SymNone,
11289		reg: regInfo{
11290			clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
11291		},
11292	},
11293	{
11294		name:         "CALLclosure",
11295		auxType:      auxInt64,
11296		argLen:       3,
11297		clobberFlags: true,
11298		call:         true,
11299		reg: regInfo{
11300			inputs: []inputInfo{
11301				{1, 4},     // DX
11302				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11303			},
11304			clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
11305		},
11306	},
11307	{
11308		name:         "CALLinter",
11309		auxType:      auxInt64,
11310		argLen:       2,
11311		clobberFlags: true,
11312		call:         true,
11313		reg: regInfo{
11314			inputs: []inputInfo{
11315				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11316			},
11317			clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
11318		},
11319	},
11320	{
11321		name:           "DUFFCOPY",
11322		auxType:        auxInt64,
11323		argLen:         3,
11324		clobberFlags:   true,
11325		faultOnNilArg0: true,
11326		faultOnNilArg1: true,
11327		reg: regInfo{
11328			inputs: []inputInfo{
11329				{0, 128}, // DI
11330				{1, 64},  // SI
11331			},
11332			clobbers: 65728, // SI DI X0
11333		},
11334	},
11335	{
11336		name:           "REPMOVSQ",
11337		argLen:         4,
11338		faultOnNilArg0: true,
11339		faultOnNilArg1: true,
11340		reg: regInfo{
11341			inputs: []inputInfo{
11342				{0, 128}, // DI
11343				{1, 64},  // SI
11344				{2, 2},   // CX
11345			},
11346			clobbers: 194, // CX SI DI
11347		},
11348	},
11349	{
11350		name:   "InvertFlags",
11351		argLen: 1,
11352		reg:    regInfo{},
11353	},
11354	{
11355		name:   "LoweredGetG",
11356		argLen: 1,
11357		reg: regInfo{
11358			outputs: []outputInfo{
11359				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11360			},
11361		},
11362	},
11363	{
11364		name:      "LoweredGetClosurePtr",
11365		argLen:    0,
11366		zeroWidth: true,
11367		reg: regInfo{
11368			outputs: []outputInfo{
11369				{0, 4}, // DX
11370			},
11371		},
11372	},
11373	{
11374		name:              "LoweredGetCallerPC",
11375		argLen:            0,
11376		rematerializeable: true,
11377		reg: regInfo{
11378			outputs: []outputInfo{
11379				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11380			},
11381		},
11382	},
11383	{
11384		name:              "LoweredGetCallerSP",
11385		argLen:            0,
11386		rematerializeable: true,
11387		reg: regInfo{
11388			outputs: []outputInfo{
11389				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11390			},
11391		},
11392	},
11393	{
11394		name:           "LoweredNilCheck",
11395		argLen:         2,
11396		clobberFlags:   true,
11397		nilCheck:       true,
11398		faultOnNilArg0: true,
11399		reg: regInfo{
11400			inputs: []inputInfo{
11401				{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11402			},
11403		},
11404	},
11405	{
11406		name:         "LoweredWB",
11407		auxType:      auxSym,
11408		argLen:       3,
11409		clobberFlags: true,
11410		symEffect:    SymNone,
11411		reg: regInfo{
11412			inputs: []inputInfo{
11413				{0, 128}, // DI
11414				{1, 1},   // AX
11415			},
11416			clobbers: 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
11417		},
11418	},
11419	{
11420		name:    "LoweredPanicBoundsA",
11421		auxType: auxInt64,
11422		argLen:  3,
11423		reg: regInfo{
11424			inputs: []inputInfo{
11425				{0, 4}, // DX
11426				{1, 8}, // BX
11427			},
11428		},
11429	},
11430	{
11431		name:    "LoweredPanicBoundsB",
11432		auxType: auxInt64,
11433		argLen:  3,
11434		reg: regInfo{
11435			inputs: []inputInfo{
11436				{0, 2}, // CX
11437				{1, 4}, // DX
11438			},
11439		},
11440	},
11441	{
11442		name:    "LoweredPanicBoundsC",
11443		auxType: auxInt64,
11444		argLen:  3,
11445		reg: regInfo{
11446			inputs: []inputInfo{
11447				{0, 1}, // AX
11448				{1, 2}, // CX
11449			},
11450		},
11451	},
11452	{
11453		name:   "FlagEQ",
11454		argLen: 0,
11455		reg:    regInfo{},
11456	},
11457	{
11458		name:   "FlagLT_ULT",
11459		argLen: 0,
11460		reg:    regInfo{},
11461	},
11462	{
11463		name:   "FlagLT_UGT",
11464		argLen: 0,
11465		reg:    regInfo{},
11466	},
11467	{
11468		name:   "FlagGT_UGT",
11469		argLen: 0,
11470		reg:    regInfo{},
11471	},
11472	{
11473		name:   "FlagGT_ULT",
11474		argLen: 0,
11475		reg:    regInfo{},
11476	},
11477	{
11478		name:           "MOVBatomicload",
11479		auxType:        auxSymOff,
11480		argLen:         2,
11481		faultOnNilArg0: true,
11482		symEffect:      SymRead,
11483		asm:            x86.AMOVB,
11484		reg: regInfo{
11485			inputs: []inputInfo{
11486				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11487			},
11488			outputs: []outputInfo{
11489				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11490			},
11491		},
11492	},
11493	{
11494		name:           "MOVLatomicload",
11495		auxType:        auxSymOff,
11496		argLen:         2,
11497		faultOnNilArg0: true,
11498		symEffect:      SymRead,
11499		asm:            x86.AMOVL,
11500		reg: regInfo{
11501			inputs: []inputInfo{
11502				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11503			},
11504			outputs: []outputInfo{
11505				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11506			},
11507		},
11508	},
11509	{
11510		name:           "MOVQatomicload",
11511		auxType:        auxSymOff,
11512		argLen:         2,
11513		faultOnNilArg0: true,
11514		symEffect:      SymRead,
11515		asm:            x86.AMOVQ,
11516		reg: regInfo{
11517			inputs: []inputInfo{
11518				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11519			},
11520			outputs: []outputInfo{
11521				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11522			},
11523		},
11524	},
11525	{
11526		name:           "XCHGB",
11527		auxType:        auxSymOff,
11528		argLen:         3,
11529		resultInArg0:   true,
11530		faultOnNilArg1: true,
11531		hasSideEffects: true,
11532		symEffect:      SymRdWr,
11533		asm:            x86.AXCHGB,
11534		reg: regInfo{
11535			inputs: []inputInfo{
11536				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11537				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11538			},
11539			outputs: []outputInfo{
11540				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11541			},
11542		},
11543	},
11544	{
11545		name:           "XCHGL",
11546		auxType:        auxSymOff,
11547		argLen:         3,
11548		resultInArg0:   true,
11549		faultOnNilArg1: true,
11550		hasSideEffects: true,
11551		symEffect:      SymRdWr,
11552		asm:            x86.AXCHGL,
11553		reg: regInfo{
11554			inputs: []inputInfo{
11555				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11556				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11557			},
11558			outputs: []outputInfo{
11559				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11560			},
11561		},
11562	},
11563	{
11564		name:           "XCHGQ",
11565		auxType:        auxSymOff,
11566		argLen:         3,
11567		resultInArg0:   true,
11568		faultOnNilArg1: true,
11569		hasSideEffects: true,
11570		symEffect:      SymRdWr,
11571		asm:            x86.AXCHGQ,
11572		reg: regInfo{
11573			inputs: []inputInfo{
11574				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11575				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11576			},
11577			outputs: []outputInfo{
11578				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11579			},
11580		},
11581	},
11582	{
11583		name:           "XADDLlock",
11584		auxType:        auxSymOff,
11585		argLen:         3,
11586		resultInArg0:   true,
11587		clobberFlags:   true,
11588		faultOnNilArg1: true,
11589		hasSideEffects: true,
11590		symEffect:      SymRdWr,
11591		asm:            x86.AXADDL,
11592		reg: regInfo{
11593			inputs: []inputInfo{
11594				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11595				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11596			},
11597			outputs: []outputInfo{
11598				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11599			},
11600		},
11601	},
11602	{
11603		name:           "XADDQlock",
11604		auxType:        auxSymOff,
11605		argLen:         3,
11606		resultInArg0:   true,
11607		clobberFlags:   true,
11608		faultOnNilArg1: true,
11609		hasSideEffects: true,
11610		symEffect:      SymRdWr,
11611		asm:            x86.AXADDQ,
11612		reg: regInfo{
11613			inputs: []inputInfo{
11614				{0, 65519},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11615				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11616			},
11617			outputs: []outputInfo{
11618				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11619			},
11620		},
11621	},
11622	{
11623		name:   "AddTupleFirst32",
11624		argLen: 2,
11625		reg:    regInfo{},
11626	},
11627	{
11628		name:   "AddTupleFirst64",
11629		argLen: 2,
11630		reg:    regInfo{},
11631	},
11632	{
11633		name:           "CMPXCHGLlock",
11634		auxType:        auxSymOff,
11635		argLen:         4,
11636		clobberFlags:   true,
11637		faultOnNilArg0: true,
11638		hasSideEffects: true,
11639		symEffect:      SymRdWr,
11640		asm:            x86.ACMPXCHGL,
11641		reg: regInfo{
11642			inputs: []inputInfo{
11643				{1, 1},     // AX
11644				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11645				{2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11646			},
11647			clobbers: 1, // AX
11648			outputs: []outputInfo{
11649				{1, 0},
11650				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11651			},
11652		},
11653	},
11654	{
11655		name:           "CMPXCHGQlock",
11656		auxType:        auxSymOff,
11657		argLen:         4,
11658		clobberFlags:   true,
11659		faultOnNilArg0: true,
11660		hasSideEffects: true,
11661		symEffect:      SymRdWr,
11662		asm:            x86.ACMPXCHGQ,
11663		reg: regInfo{
11664			inputs: []inputInfo{
11665				{1, 1},     // AX
11666				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11667				{2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11668			},
11669			clobbers: 1, // AX
11670			outputs: []outputInfo{
11671				{1, 0},
11672				{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11673			},
11674		},
11675	},
11676	{
11677		name:           "ANDBlock",
11678		auxType:        auxSymOff,
11679		argLen:         3,
11680		clobberFlags:   true,
11681		faultOnNilArg0: true,
11682		hasSideEffects: true,
11683		symEffect:      SymRdWr,
11684		asm:            x86.AANDB,
11685		reg: regInfo{
11686			inputs: []inputInfo{
11687				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11688				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11689			},
11690		},
11691	},
11692	{
11693		name:           "ORBlock",
11694		auxType:        auxSymOff,
11695		argLen:         3,
11696		clobberFlags:   true,
11697		faultOnNilArg0: true,
11698		hasSideEffects: true,
11699		symEffect:      SymRdWr,
11700		asm:            x86.AORB,
11701		reg: regInfo{
11702			inputs: []inputInfo{
11703				{1, 65535},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
11704				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
11705			},
11706		},
11707	},
11708
11709	{
11710		name:        "ADD",
11711		argLen:      2,
11712		commutative: true,
11713		asm:         arm.AADD,
11714		reg: regInfo{
11715			inputs: []inputInfo{
11716				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11717				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11718			},
11719			outputs: []outputInfo{
11720				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11721			},
11722		},
11723	},
11724	{
11725		name:    "ADDconst",
11726		auxType: auxInt32,
11727		argLen:  1,
11728		asm:     arm.AADD,
11729		reg: regInfo{
11730			inputs: []inputInfo{
11731				{0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14
11732			},
11733			outputs: []outputInfo{
11734				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11735			},
11736		},
11737	},
11738	{
11739		name:   "SUB",
11740		argLen: 2,
11741		asm:    arm.ASUB,
11742		reg: regInfo{
11743			inputs: []inputInfo{
11744				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11745				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11746			},
11747			outputs: []outputInfo{
11748				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11749			},
11750		},
11751	},
11752	{
11753		name:    "SUBconst",
11754		auxType: auxInt32,
11755		argLen:  1,
11756		asm:     arm.ASUB,
11757		reg: regInfo{
11758			inputs: []inputInfo{
11759				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11760			},
11761			outputs: []outputInfo{
11762				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11763			},
11764		},
11765	},
11766	{
11767		name:   "RSB",
11768		argLen: 2,
11769		asm:    arm.ARSB,
11770		reg: regInfo{
11771			inputs: []inputInfo{
11772				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11773				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11774			},
11775			outputs: []outputInfo{
11776				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11777			},
11778		},
11779	},
11780	{
11781		name:    "RSBconst",
11782		auxType: auxInt32,
11783		argLen:  1,
11784		asm:     arm.ARSB,
11785		reg: regInfo{
11786			inputs: []inputInfo{
11787				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11788			},
11789			outputs: []outputInfo{
11790				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11791			},
11792		},
11793	},
11794	{
11795		name:        "MUL",
11796		argLen:      2,
11797		commutative: true,
11798		asm:         arm.AMUL,
11799		reg: regInfo{
11800			inputs: []inputInfo{
11801				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11802				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11803			},
11804			outputs: []outputInfo{
11805				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11806			},
11807		},
11808	},
11809	{
11810		name:        "HMUL",
11811		argLen:      2,
11812		commutative: true,
11813		asm:         arm.AMULL,
11814		reg: regInfo{
11815			inputs: []inputInfo{
11816				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11817				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11818			},
11819			outputs: []outputInfo{
11820				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11821			},
11822		},
11823	},
11824	{
11825		name:        "HMULU",
11826		argLen:      2,
11827		commutative: true,
11828		asm:         arm.AMULLU,
11829		reg: regInfo{
11830			inputs: []inputInfo{
11831				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11832				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11833			},
11834			outputs: []outputInfo{
11835				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11836			},
11837		},
11838	},
11839	{
11840		name:         "CALLudiv",
11841		argLen:       2,
11842		clobberFlags: true,
11843		reg: regInfo{
11844			inputs: []inputInfo{
11845				{0, 2}, // R1
11846				{1, 1}, // R0
11847			},
11848			clobbers: 16396, // R2 R3 R14
11849			outputs: []outputInfo{
11850				{0, 1}, // R0
11851				{1, 2}, // R1
11852			},
11853		},
11854	},
11855	{
11856		name:        "ADDS",
11857		argLen:      2,
11858		commutative: true,
11859		asm:         arm.AADD,
11860		reg: regInfo{
11861			inputs: []inputInfo{
11862				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11863				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11864			},
11865			outputs: []outputInfo{
11866				{1, 0},
11867				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11868			},
11869		},
11870	},
11871	{
11872		name:    "ADDSconst",
11873		auxType: auxInt32,
11874		argLen:  1,
11875		asm:     arm.AADD,
11876		reg: regInfo{
11877			inputs: []inputInfo{
11878				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11879			},
11880			outputs: []outputInfo{
11881				{1, 0},
11882				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11883			},
11884		},
11885	},
11886	{
11887		name:        "ADC",
11888		argLen:      3,
11889		commutative: true,
11890		asm:         arm.AADC,
11891		reg: regInfo{
11892			inputs: []inputInfo{
11893				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11894				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11895			},
11896			outputs: []outputInfo{
11897				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11898			},
11899		},
11900	},
11901	{
11902		name:    "ADCconst",
11903		auxType: auxInt32,
11904		argLen:  2,
11905		asm:     arm.AADC,
11906		reg: regInfo{
11907			inputs: []inputInfo{
11908				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11909			},
11910			outputs: []outputInfo{
11911				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11912			},
11913		},
11914	},
11915	{
11916		name:   "SUBS",
11917		argLen: 2,
11918		asm:    arm.ASUB,
11919		reg: regInfo{
11920			inputs: []inputInfo{
11921				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11922				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11923			},
11924			outputs: []outputInfo{
11925				{1, 0},
11926				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11927			},
11928		},
11929	},
11930	{
11931		name:    "SUBSconst",
11932		auxType: auxInt32,
11933		argLen:  1,
11934		asm:     arm.ASUB,
11935		reg: regInfo{
11936			inputs: []inputInfo{
11937				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11938			},
11939			outputs: []outputInfo{
11940				{1, 0},
11941				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11942			},
11943		},
11944	},
11945	{
11946		name:    "RSBSconst",
11947		auxType: auxInt32,
11948		argLen:  1,
11949		asm:     arm.ARSB,
11950		reg: regInfo{
11951			inputs: []inputInfo{
11952				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
11953			},
11954			outputs: []outputInfo{
11955				{1, 0},
11956				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11957			},
11958		},
11959	},
11960	{
11961		name:   "SBC",
11962		argLen: 3,
11963		asm:    arm.ASBC,
11964		reg: regInfo{
11965			inputs: []inputInfo{
11966				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11967				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11968			},
11969			outputs: []outputInfo{
11970				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11971			},
11972		},
11973	},
11974	{
11975		name:    "SBCconst",
11976		auxType: auxInt32,
11977		argLen:  2,
11978		asm:     arm.ASBC,
11979		reg: regInfo{
11980			inputs: []inputInfo{
11981				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11982			},
11983			outputs: []outputInfo{
11984				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11985			},
11986		},
11987	},
11988	{
11989		name:    "RSCconst",
11990		auxType: auxInt32,
11991		argLen:  2,
11992		asm:     arm.ARSC,
11993		reg: regInfo{
11994			inputs: []inputInfo{
11995				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11996			},
11997			outputs: []outputInfo{
11998				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
11999			},
12000		},
12001	},
12002	{
12003		name:        "MULLU",
12004		argLen:      2,
12005		commutative: true,
12006		asm:         arm.AMULLU,
12007		reg: regInfo{
12008			inputs: []inputInfo{
12009				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12010				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12011			},
12012			outputs: []outputInfo{
12013				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12014				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12015			},
12016		},
12017	},
12018	{
12019		name:   "MULA",
12020		argLen: 3,
12021		asm:    arm.AMULA,
12022		reg: regInfo{
12023			inputs: []inputInfo{
12024				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12025				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12026				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12027			},
12028			outputs: []outputInfo{
12029				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12030			},
12031		},
12032	},
12033	{
12034		name:   "MULS",
12035		argLen: 3,
12036		asm:    arm.AMULS,
12037		reg: regInfo{
12038			inputs: []inputInfo{
12039				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12040				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12041				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12042			},
12043			outputs: []outputInfo{
12044				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12045			},
12046		},
12047	},
12048	{
12049		name:        "ADDF",
12050		argLen:      2,
12051		commutative: true,
12052		asm:         arm.AADDF,
12053		reg: regInfo{
12054			inputs: []inputInfo{
12055				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12056				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12057			},
12058			outputs: []outputInfo{
12059				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12060			},
12061		},
12062	},
12063	{
12064		name:        "ADDD",
12065		argLen:      2,
12066		commutative: true,
12067		asm:         arm.AADDD,
12068		reg: regInfo{
12069			inputs: []inputInfo{
12070				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12071				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12072			},
12073			outputs: []outputInfo{
12074				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12075			},
12076		},
12077	},
12078	{
12079		name:   "SUBF",
12080		argLen: 2,
12081		asm:    arm.ASUBF,
12082		reg: regInfo{
12083			inputs: []inputInfo{
12084				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12085				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12086			},
12087			outputs: []outputInfo{
12088				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12089			},
12090		},
12091	},
12092	{
12093		name:   "SUBD",
12094		argLen: 2,
12095		asm:    arm.ASUBD,
12096		reg: regInfo{
12097			inputs: []inputInfo{
12098				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12099				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12100			},
12101			outputs: []outputInfo{
12102				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12103			},
12104		},
12105	},
12106	{
12107		name:        "MULF",
12108		argLen:      2,
12109		commutative: true,
12110		asm:         arm.AMULF,
12111		reg: regInfo{
12112			inputs: []inputInfo{
12113				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12114				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12115			},
12116			outputs: []outputInfo{
12117				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12118			},
12119		},
12120	},
12121	{
12122		name:        "MULD",
12123		argLen:      2,
12124		commutative: true,
12125		asm:         arm.AMULD,
12126		reg: regInfo{
12127			inputs: []inputInfo{
12128				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12129				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12130			},
12131			outputs: []outputInfo{
12132				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12133			},
12134		},
12135	},
12136	{
12137		name:        "NMULF",
12138		argLen:      2,
12139		commutative: true,
12140		asm:         arm.ANMULF,
12141		reg: regInfo{
12142			inputs: []inputInfo{
12143				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12144				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12145			},
12146			outputs: []outputInfo{
12147				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12148			},
12149		},
12150	},
12151	{
12152		name:        "NMULD",
12153		argLen:      2,
12154		commutative: true,
12155		asm:         arm.ANMULD,
12156		reg: regInfo{
12157			inputs: []inputInfo{
12158				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12159				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12160			},
12161			outputs: []outputInfo{
12162				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12163			},
12164		},
12165	},
12166	{
12167		name:   "DIVF",
12168		argLen: 2,
12169		asm:    arm.ADIVF,
12170		reg: regInfo{
12171			inputs: []inputInfo{
12172				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12173				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12174			},
12175			outputs: []outputInfo{
12176				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12177			},
12178		},
12179	},
12180	{
12181		name:   "DIVD",
12182		argLen: 2,
12183		asm:    arm.ADIVD,
12184		reg: regInfo{
12185			inputs: []inputInfo{
12186				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12187				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12188			},
12189			outputs: []outputInfo{
12190				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12191			},
12192		},
12193	},
12194	{
12195		name:         "MULAF",
12196		argLen:       3,
12197		resultInArg0: true,
12198		asm:          arm.AMULAF,
12199		reg: regInfo{
12200			inputs: []inputInfo{
12201				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12202				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12203				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12204			},
12205			outputs: []outputInfo{
12206				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12207			},
12208		},
12209	},
12210	{
12211		name:         "MULAD",
12212		argLen:       3,
12213		resultInArg0: true,
12214		asm:          arm.AMULAD,
12215		reg: regInfo{
12216			inputs: []inputInfo{
12217				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12218				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12219				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12220			},
12221			outputs: []outputInfo{
12222				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12223			},
12224		},
12225	},
12226	{
12227		name:         "MULSF",
12228		argLen:       3,
12229		resultInArg0: true,
12230		asm:          arm.AMULSF,
12231		reg: regInfo{
12232			inputs: []inputInfo{
12233				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12234				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12235				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12236			},
12237			outputs: []outputInfo{
12238				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12239			},
12240		},
12241	},
12242	{
12243		name:         "MULSD",
12244		argLen:       3,
12245		resultInArg0: true,
12246		asm:          arm.AMULSD,
12247		reg: regInfo{
12248			inputs: []inputInfo{
12249				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12250				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12251				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12252			},
12253			outputs: []outputInfo{
12254				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12255			},
12256		},
12257	},
12258	{
12259		name:         "FMULAD",
12260		argLen:       3,
12261		resultInArg0: true,
12262		asm:          arm.AFMULAD,
12263		reg: regInfo{
12264			inputs: []inputInfo{
12265				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12266				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12267				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12268			},
12269			outputs: []outputInfo{
12270				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12271			},
12272		},
12273	},
12274	{
12275		name:        "AND",
12276		argLen:      2,
12277		commutative: true,
12278		asm:         arm.AAND,
12279		reg: regInfo{
12280			inputs: []inputInfo{
12281				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12282				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12283			},
12284			outputs: []outputInfo{
12285				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12286			},
12287		},
12288	},
12289	{
12290		name:    "ANDconst",
12291		auxType: auxInt32,
12292		argLen:  1,
12293		asm:     arm.AAND,
12294		reg: regInfo{
12295			inputs: []inputInfo{
12296				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12297			},
12298			outputs: []outputInfo{
12299				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12300			},
12301		},
12302	},
12303	{
12304		name:        "OR",
12305		argLen:      2,
12306		commutative: true,
12307		asm:         arm.AORR,
12308		reg: regInfo{
12309			inputs: []inputInfo{
12310				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12311				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12312			},
12313			outputs: []outputInfo{
12314				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12315			},
12316		},
12317	},
12318	{
12319		name:    "ORconst",
12320		auxType: auxInt32,
12321		argLen:  1,
12322		asm:     arm.AORR,
12323		reg: regInfo{
12324			inputs: []inputInfo{
12325				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12326			},
12327			outputs: []outputInfo{
12328				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12329			},
12330		},
12331	},
12332	{
12333		name:        "XOR",
12334		argLen:      2,
12335		commutative: true,
12336		asm:         arm.AEOR,
12337		reg: regInfo{
12338			inputs: []inputInfo{
12339				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12340				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12341			},
12342			outputs: []outputInfo{
12343				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12344			},
12345		},
12346	},
12347	{
12348		name:    "XORconst",
12349		auxType: auxInt32,
12350		argLen:  1,
12351		asm:     arm.AEOR,
12352		reg: regInfo{
12353			inputs: []inputInfo{
12354				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12355			},
12356			outputs: []outputInfo{
12357				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12358			},
12359		},
12360	},
12361	{
12362		name:   "BIC",
12363		argLen: 2,
12364		asm:    arm.ABIC,
12365		reg: regInfo{
12366			inputs: []inputInfo{
12367				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12368				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12369			},
12370			outputs: []outputInfo{
12371				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12372			},
12373		},
12374	},
12375	{
12376		name:    "BICconst",
12377		auxType: auxInt32,
12378		argLen:  1,
12379		asm:     arm.ABIC,
12380		reg: regInfo{
12381			inputs: []inputInfo{
12382				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12383			},
12384			outputs: []outputInfo{
12385				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12386			},
12387		},
12388	},
12389	{
12390		name:    "BFX",
12391		auxType: auxInt32,
12392		argLen:  1,
12393		asm:     arm.ABFX,
12394		reg: regInfo{
12395			inputs: []inputInfo{
12396				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12397			},
12398			outputs: []outputInfo{
12399				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12400			},
12401		},
12402	},
12403	{
12404		name:    "BFXU",
12405		auxType: auxInt32,
12406		argLen:  1,
12407		asm:     arm.ABFXU,
12408		reg: regInfo{
12409			inputs: []inputInfo{
12410				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12411			},
12412			outputs: []outputInfo{
12413				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12414			},
12415		},
12416	},
12417	{
12418		name:   "MVN",
12419		argLen: 1,
12420		asm:    arm.AMVN,
12421		reg: regInfo{
12422			inputs: []inputInfo{
12423				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12424			},
12425			outputs: []outputInfo{
12426				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12427			},
12428		},
12429	},
12430	{
12431		name:   "NEGF",
12432		argLen: 1,
12433		asm:    arm.ANEGF,
12434		reg: regInfo{
12435			inputs: []inputInfo{
12436				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12437			},
12438			outputs: []outputInfo{
12439				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12440			},
12441		},
12442	},
12443	{
12444		name:   "NEGD",
12445		argLen: 1,
12446		asm:    arm.ANEGD,
12447		reg: regInfo{
12448			inputs: []inputInfo{
12449				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12450			},
12451			outputs: []outputInfo{
12452				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12453			},
12454		},
12455	},
12456	{
12457		name:   "SQRTD",
12458		argLen: 1,
12459		asm:    arm.ASQRTD,
12460		reg: regInfo{
12461			inputs: []inputInfo{
12462				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12463			},
12464			outputs: []outputInfo{
12465				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12466			},
12467		},
12468	},
12469	{
12470		name:   "ABSD",
12471		argLen: 1,
12472		asm:    arm.AABSD,
12473		reg: regInfo{
12474			inputs: []inputInfo{
12475				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12476			},
12477			outputs: []outputInfo{
12478				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
12479			},
12480		},
12481	},
12482	{
12483		name:   "CLZ",
12484		argLen: 1,
12485		asm:    arm.ACLZ,
12486		reg: regInfo{
12487			inputs: []inputInfo{
12488				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12489			},
12490			outputs: []outputInfo{
12491				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12492			},
12493		},
12494	},
12495	{
12496		name:   "REV",
12497		argLen: 1,
12498		asm:    arm.AREV,
12499		reg: regInfo{
12500			inputs: []inputInfo{
12501				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12502			},
12503			outputs: []outputInfo{
12504				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12505			},
12506		},
12507	},
12508	{
12509		name:   "REV16",
12510		argLen: 1,
12511		asm:    arm.AREV16,
12512		reg: regInfo{
12513			inputs: []inputInfo{
12514				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12515			},
12516			outputs: []outputInfo{
12517				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12518			},
12519		},
12520	},
12521	{
12522		name:   "RBIT",
12523		argLen: 1,
12524		asm:    arm.ARBIT,
12525		reg: regInfo{
12526			inputs: []inputInfo{
12527				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12528			},
12529			outputs: []outputInfo{
12530				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12531			},
12532		},
12533	},
12534	{
12535		name:   "SLL",
12536		argLen: 2,
12537		asm:    arm.ASLL,
12538		reg: regInfo{
12539			inputs: []inputInfo{
12540				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12541				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12542			},
12543			outputs: []outputInfo{
12544				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12545			},
12546		},
12547	},
12548	{
12549		name:    "SLLconst",
12550		auxType: auxInt32,
12551		argLen:  1,
12552		asm:     arm.ASLL,
12553		reg: regInfo{
12554			inputs: []inputInfo{
12555				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12556			},
12557			outputs: []outputInfo{
12558				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12559			},
12560		},
12561	},
12562	{
12563		name:   "SRL",
12564		argLen: 2,
12565		asm:    arm.ASRL,
12566		reg: regInfo{
12567			inputs: []inputInfo{
12568				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12569				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12570			},
12571			outputs: []outputInfo{
12572				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12573			},
12574		},
12575	},
12576	{
12577		name:    "SRLconst",
12578		auxType: auxInt32,
12579		argLen:  1,
12580		asm:     arm.ASRL,
12581		reg: regInfo{
12582			inputs: []inputInfo{
12583				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12584			},
12585			outputs: []outputInfo{
12586				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12587			},
12588		},
12589	},
12590	{
12591		name:   "SRA",
12592		argLen: 2,
12593		asm:    arm.ASRA,
12594		reg: regInfo{
12595			inputs: []inputInfo{
12596				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12597				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12598			},
12599			outputs: []outputInfo{
12600				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12601			},
12602		},
12603	},
12604	{
12605		name:    "SRAconst",
12606		auxType: auxInt32,
12607		argLen:  1,
12608		asm:     arm.ASRA,
12609		reg: regInfo{
12610			inputs: []inputInfo{
12611				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12612			},
12613			outputs: []outputInfo{
12614				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12615			},
12616		},
12617	},
12618	{
12619		name:   "SRR",
12620		argLen: 2,
12621		reg: regInfo{
12622			inputs: []inputInfo{
12623				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12624				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12625			},
12626			outputs: []outputInfo{
12627				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12628			},
12629		},
12630	},
12631	{
12632		name:    "SRRconst",
12633		auxType: auxInt32,
12634		argLen:  1,
12635		reg: regInfo{
12636			inputs: []inputInfo{
12637				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12638			},
12639			outputs: []outputInfo{
12640				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12641			},
12642		},
12643	},
12644	{
12645		name:    "ADDshiftLL",
12646		auxType: auxInt32,
12647		argLen:  2,
12648		asm:     arm.AADD,
12649		reg: regInfo{
12650			inputs: []inputInfo{
12651				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12652				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12653			},
12654			outputs: []outputInfo{
12655				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12656			},
12657		},
12658	},
12659	{
12660		name:    "ADDshiftRL",
12661		auxType: auxInt32,
12662		argLen:  2,
12663		asm:     arm.AADD,
12664		reg: regInfo{
12665			inputs: []inputInfo{
12666				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12667				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12668			},
12669			outputs: []outputInfo{
12670				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12671			},
12672		},
12673	},
12674	{
12675		name:    "ADDshiftRA",
12676		auxType: auxInt32,
12677		argLen:  2,
12678		asm:     arm.AADD,
12679		reg: regInfo{
12680			inputs: []inputInfo{
12681				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12682				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12683			},
12684			outputs: []outputInfo{
12685				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12686			},
12687		},
12688	},
12689	{
12690		name:    "SUBshiftLL",
12691		auxType: auxInt32,
12692		argLen:  2,
12693		asm:     arm.ASUB,
12694		reg: regInfo{
12695			inputs: []inputInfo{
12696				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12697				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12698			},
12699			outputs: []outputInfo{
12700				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12701			},
12702		},
12703	},
12704	{
12705		name:    "SUBshiftRL",
12706		auxType: auxInt32,
12707		argLen:  2,
12708		asm:     arm.ASUB,
12709		reg: regInfo{
12710			inputs: []inputInfo{
12711				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12712				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12713			},
12714			outputs: []outputInfo{
12715				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12716			},
12717		},
12718	},
12719	{
12720		name:    "SUBshiftRA",
12721		auxType: auxInt32,
12722		argLen:  2,
12723		asm:     arm.ASUB,
12724		reg: regInfo{
12725			inputs: []inputInfo{
12726				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12727				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12728			},
12729			outputs: []outputInfo{
12730				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12731			},
12732		},
12733	},
12734	{
12735		name:    "RSBshiftLL",
12736		auxType: auxInt32,
12737		argLen:  2,
12738		asm:     arm.ARSB,
12739		reg: regInfo{
12740			inputs: []inputInfo{
12741				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12742				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12743			},
12744			outputs: []outputInfo{
12745				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12746			},
12747		},
12748	},
12749	{
12750		name:    "RSBshiftRL",
12751		auxType: auxInt32,
12752		argLen:  2,
12753		asm:     arm.ARSB,
12754		reg: regInfo{
12755			inputs: []inputInfo{
12756				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12757				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12758			},
12759			outputs: []outputInfo{
12760				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12761			},
12762		},
12763	},
12764	{
12765		name:    "RSBshiftRA",
12766		auxType: auxInt32,
12767		argLen:  2,
12768		asm:     arm.ARSB,
12769		reg: regInfo{
12770			inputs: []inputInfo{
12771				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12772				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12773			},
12774			outputs: []outputInfo{
12775				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12776			},
12777		},
12778	},
12779	{
12780		name:    "ANDshiftLL",
12781		auxType: auxInt32,
12782		argLen:  2,
12783		asm:     arm.AAND,
12784		reg: regInfo{
12785			inputs: []inputInfo{
12786				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12787				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12788			},
12789			outputs: []outputInfo{
12790				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12791			},
12792		},
12793	},
12794	{
12795		name:    "ANDshiftRL",
12796		auxType: auxInt32,
12797		argLen:  2,
12798		asm:     arm.AAND,
12799		reg: regInfo{
12800			inputs: []inputInfo{
12801				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12802				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12803			},
12804			outputs: []outputInfo{
12805				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12806			},
12807		},
12808	},
12809	{
12810		name:    "ANDshiftRA",
12811		auxType: auxInt32,
12812		argLen:  2,
12813		asm:     arm.AAND,
12814		reg: regInfo{
12815			inputs: []inputInfo{
12816				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12817				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12818			},
12819			outputs: []outputInfo{
12820				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12821			},
12822		},
12823	},
12824	{
12825		name:    "ORshiftLL",
12826		auxType: auxInt32,
12827		argLen:  2,
12828		asm:     arm.AORR,
12829		reg: regInfo{
12830			inputs: []inputInfo{
12831				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12832				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12833			},
12834			outputs: []outputInfo{
12835				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12836			},
12837		},
12838	},
12839	{
12840		name:    "ORshiftRL",
12841		auxType: auxInt32,
12842		argLen:  2,
12843		asm:     arm.AORR,
12844		reg: regInfo{
12845			inputs: []inputInfo{
12846				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12847				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12848			},
12849			outputs: []outputInfo{
12850				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12851			},
12852		},
12853	},
12854	{
12855		name:    "ORshiftRA",
12856		auxType: auxInt32,
12857		argLen:  2,
12858		asm:     arm.AORR,
12859		reg: regInfo{
12860			inputs: []inputInfo{
12861				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12862				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12863			},
12864			outputs: []outputInfo{
12865				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12866			},
12867		},
12868	},
12869	{
12870		name:    "XORshiftLL",
12871		auxType: auxInt32,
12872		argLen:  2,
12873		asm:     arm.AEOR,
12874		reg: regInfo{
12875			inputs: []inputInfo{
12876				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12877				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12878			},
12879			outputs: []outputInfo{
12880				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12881			},
12882		},
12883	},
12884	{
12885		name:    "XORshiftRL",
12886		auxType: auxInt32,
12887		argLen:  2,
12888		asm:     arm.AEOR,
12889		reg: regInfo{
12890			inputs: []inputInfo{
12891				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12892				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12893			},
12894			outputs: []outputInfo{
12895				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12896			},
12897		},
12898	},
12899	{
12900		name:    "XORshiftRA",
12901		auxType: auxInt32,
12902		argLen:  2,
12903		asm:     arm.AEOR,
12904		reg: regInfo{
12905			inputs: []inputInfo{
12906				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12907				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12908			},
12909			outputs: []outputInfo{
12910				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12911			},
12912		},
12913	},
12914	{
12915		name:    "XORshiftRR",
12916		auxType: auxInt32,
12917		argLen:  2,
12918		asm:     arm.AEOR,
12919		reg: regInfo{
12920			inputs: []inputInfo{
12921				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12922				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12923			},
12924			outputs: []outputInfo{
12925				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12926			},
12927		},
12928	},
12929	{
12930		name:    "BICshiftLL",
12931		auxType: auxInt32,
12932		argLen:  2,
12933		asm:     arm.ABIC,
12934		reg: regInfo{
12935			inputs: []inputInfo{
12936				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12937				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12938			},
12939			outputs: []outputInfo{
12940				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12941			},
12942		},
12943	},
12944	{
12945		name:    "BICshiftRL",
12946		auxType: auxInt32,
12947		argLen:  2,
12948		asm:     arm.ABIC,
12949		reg: regInfo{
12950			inputs: []inputInfo{
12951				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12952				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12953			},
12954			outputs: []outputInfo{
12955				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12956			},
12957		},
12958	},
12959	{
12960		name:    "BICshiftRA",
12961		auxType: auxInt32,
12962		argLen:  2,
12963		asm:     arm.ABIC,
12964		reg: regInfo{
12965			inputs: []inputInfo{
12966				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12967				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12968			},
12969			outputs: []outputInfo{
12970				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12971			},
12972		},
12973	},
12974	{
12975		name:    "MVNshiftLL",
12976		auxType: auxInt32,
12977		argLen:  1,
12978		asm:     arm.AMVN,
12979		reg: regInfo{
12980			inputs: []inputInfo{
12981				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12982			},
12983			outputs: []outputInfo{
12984				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12985			},
12986		},
12987	},
12988	{
12989		name:    "MVNshiftRL",
12990		auxType: auxInt32,
12991		argLen:  1,
12992		asm:     arm.AMVN,
12993		reg: regInfo{
12994			inputs: []inputInfo{
12995				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
12996			},
12997			outputs: []outputInfo{
12998				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
12999			},
13000		},
13001	},
13002	{
13003		name:    "MVNshiftRA",
13004		auxType: auxInt32,
13005		argLen:  1,
13006		asm:     arm.AMVN,
13007		reg: regInfo{
13008			inputs: []inputInfo{
13009				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13010			},
13011			outputs: []outputInfo{
13012				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13013			},
13014		},
13015	},
13016	{
13017		name:    "ADCshiftLL",
13018		auxType: auxInt32,
13019		argLen:  3,
13020		asm:     arm.AADC,
13021		reg: regInfo{
13022			inputs: []inputInfo{
13023				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13024				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13025			},
13026			outputs: []outputInfo{
13027				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13028			},
13029		},
13030	},
13031	{
13032		name:    "ADCshiftRL",
13033		auxType: auxInt32,
13034		argLen:  3,
13035		asm:     arm.AADC,
13036		reg: regInfo{
13037			inputs: []inputInfo{
13038				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13039				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13040			},
13041			outputs: []outputInfo{
13042				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13043			},
13044		},
13045	},
13046	{
13047		name:    "ADCshiftRA",
13048		auxType: auxInt32,
13049		argLen:  3,
13050		asm:     arm.AADC,
13051		reg: regInfo{
13052			inputs: []inputInfo{
13053				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13054				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13055			},
13056			outputs: []outputInfo{
13057				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13058			},
13059		},
13060	},
13061	{
13062		name:    "SBCshiftLL",
13063		auxType: auxInt32,
13064		argLen:  3,
13065		asm:     arm.ASBC,
13066		reg: regInfo{
13067			inputs: []inputInfo{
13068				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13069				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13070			},
13071			outputs: []outputInfo{
13072				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13073			},
13074		},
13075	},
13076	{
13077		name:    "SBCshiftRL",
13078		auxType: auxInt32,
13079		argLen:  3,
13080		asm:     arm.ASBC,
13081		reg: regInfo{
13082			inputs: []inputInfo{
13083				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13084				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13085			},
13086			outputs: []outputInfo{
13087				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13088			},
13089		},
13090	},
13091	{
13092		name:    "SBCshiftRA",
13093		auxType: auxInt32,
13094		argLen:  3,
13095		asm:     arm.ASBC,
13096		reg: regInfo{
13097			inputs: []inputInfo{
13098				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13099				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13100			},
13101			outputs: []outputInfo{
13102				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13103			},
13104		},
13105	},
13106	{
13107		name:    "RSCshiftLL",
13108		auxType: auxInt32,
13109		argLen:  3,
13110		asm:     arm.ARSC,
13111		reg: regInfo{
13112			inputs: []inputInfo{
13113				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13114				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13115			},
13116			outputs: []outputInfo{
13117				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13118			},
13119		},
13120	},
13121	{
13122		name:    "RSCshiftRL",
13123		auxType: auxInt32,
13124		argLen:  3,
13125		asm:     arm.ARSC,
13126		reg: regInfo{
13127			inputs: []inputInfo{
13128				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13129				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13130			},
13131			outputs: []outputInfo{
13132				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13133			},
13134		},
13135	},
13136	{
13137		name:    "RSCshiftRA",
13138		auxType: auxInt32,
13139		argLen:  3,
13140		asm:     arm.ARSC,
13141		reg: regInfo{
13142			inputs: []inputInfo{
13143				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13144				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13145			},
13146			outputs: []outputInfo{
13147				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13148			},
13149		},
13150	},
13151	{
13152		name:    "ADDSshiftLL",
13153		auxType: auxInt32,
13154		argLen:  2,
13155		asm:     arm.AADD,
13156		reg: regInfo{
13157			inputs: []inputInfo{
13158				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13159				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13160			},
13161			outputs: []outputInfo{
13162				{1, 0},
13163				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13164			},
13165		},
13166	},
13167	{
13168		name:    "ADDSshiftRL",
13169		auxType: auxInt32,
13170		argLen:  2,
13171		asm:     arm.AADD,
13172		reg: regInfo{
13173			inputs: []inputInfo{
13174				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13175				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13176			},
13177			outputs: []outputInfo{
13178				{1, 0},
13179				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13180			},
13181		},
13182	},
13183	{
13184		name:    "ADDSshiftRA",
13185		auxType: auxInt32,
13186		argLen:  2,
13187		asm:     arm.AADD,
13188		reg: regInfo{
13189			inputs: []inputInfo{
13190				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13191				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13192			},
13193			outputs: []outputInfo{
13194				{1, 0},
13195				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13196			},
13197		},
13198	},
13199	{
13200		name:    "SUBSshiftLL",
13201		auxType: auxInt32,
13202		argLen:  2,
13203		asm:     arm.ASUB,
13204		reg: regInfo{
13205			inputs: []inputInfo{
13206				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13207				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13208			},
13209			outputs: []outputInfo{
13210				{1, 0},
13211				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13212			},
13213		},
13214	},
13215	{
13216		name:    "SUBSshiftRL",
13217		auxType: auxInt32,
13218		argLen:  2,
13219		asm:     arm.ASUB,
13220		reg: regInfo{
13221			inputs: []inputInfo{
13222				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13223				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13224			},
13225			outputs: []outputInfo{
13226				{1, 0},
13227				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13228			},
13229		},
13230	},
13231	{
13232		name:    "SUBSshiftRA",
13233		auxType: auxInt32,
13234		argLen:  2,
13235		asm:     arm.ASUB,
13236		reg: regInfo{
13237			inputs: []inputInfo{
13238				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13239				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13240			},
13241			outputs: []outputInfo{
13242				{1, 0},
13243				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13244			},
13245		},
13246	},
13247	{
13248		name:    "RSBSshiftLL",
13249		auxType: auxInt32,
13250		argLen:  2,
13251		asm:     arm.ARSB,
13252		reg: regInfo{
13253			inputs: []inputInfo{
13254				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13255				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13256			},
13257			outputs: []outputInfo{
13258				{1, 0},
13259				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13260			},
13261		},
13262	},
13263	{
13264		name:    "RSBSshiftRL",
13265		auxType: auxInt32,
13266		argLen:  2,
13267		asm:     arm.ARSB,
13268		reg: regInfo{
13269			inputs: []inputInfo{
13270				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13271				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13272			},
13273			outputs: []outputInfo{
13274				{1, 0},
13275				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13276			},
13277		},
13278	},
13279	{
13280		name:    "RSBSshiftRA",
13281		auxType: auxInt32,
13282		argLen:  2,
13283		asm:     arm.ARSB,
13284		reg: regInfo{
13285			inputs: []inputInfo{
13286				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13287				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13288			},
13289			outputs: []outputInfo{
13290				{1, 0},
13291				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13292			},
13293		},
13294	},
13295	{
13296		name:   "ADDshiftLLreg",
13297		argLen: 3,
13298		asm:    arm.AADD,
13299		reg: regInfo{
13300			inputs: []inputInfo{
13301				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13302				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13303				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13304			},
13305			outputs: []outputInfo{
13306				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13307			},
13308		},
13309	},
13310	{
13311		name:   "ADDshiftRLreg",
13312		argLen: 3,
13313		asm:    arm.AADD,
13314		reg: regInfo{
13315			inputs: []inputInfo{
13316				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13317				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13318				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13319			},
13320			outputs: []outputInfo{
13321				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13322			},
13323		},
13324	},
13325	{
13326		name:   "ADDshiftRAreg",
13327		argLen: 3,
13328		asm:    arm.AADD,
13329		reg: regInfo{
13330			inputs: []inputInfo{
13331				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13332				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13333				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13334			},
13335			outputs: []outputInfo{
13336				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13337			},
13338		},
13339	},
13340	{
13341		name:   "SUBshiftLLreg",
13342		argLen: 3,
13343		asm:    arm.ASUB,
13344		reg: regInfo{
13345			inputs: []inputInfo{
13346				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13347				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13348				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13349			},
13350			outputs: []outputInfo{
13351				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13352			},
13353		},
13354	},
13355	{
13356		name:   "SUBshiftRLreg",
13357		argLen: 3,
13358		asm:    arm.ASUB,
13359		reg: regInfo{
13360			inputs: []inputInfo{
13361				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13362				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13363				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13364			},
13365			outputs: []outputInfo{
13366				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13367			},
13368		},
13369	},
13370	{
13371		name:   "SUBshiftRAreg",
13372		argLen: 3,
13373		asm:    arm.ASUB,
13374		reg: regInfo{
13375			inputs: []inputInfo{
13376				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13377				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13378				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13379			},
13380			outputs: []outputInfo{
13381				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13382			},
13383		},
13384	},
13385	{
13386		name:   "RSBshiftLLreg",
13387		argLen: 3,
13388		asm:    arm.ARSB,
13389		reg: regInfo{
13390			inputs: []inputInfo{
13391				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13392				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13393				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13394			},
13395			outputs: []outputInfo{
13396				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13397			},
13398		},
13399	},
13400	{
13401		name:   "RSBshiftRLreg",
13402		argLen: 3,
13403		asm:    arm.ARSB,
13404		reg: regInfo{
13405			inputs: []inputInfo{
13406				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13407				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13408				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13409			},
13410			outputs: []outputInfo{
13411				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13412			},
13413		},
13414	},
13415	{
13416		name:   "RSBshiftRAreg",
13417		argLen: 3,
13418		asm:    arm.ARSB,
13419		reg: regInfo{
13420			inputs: []inputInfo{
13421				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13422				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13423				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13424			},
13425			outputs: []outputInfo{
13426				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13427			},
13428		},
13429	},
13430	{
13431		name:   "ANDshiftLLreg",
13432		argLen: 3,
13433		asm:    arm.AAND,
13434		reg: regInfo{
13435			inputs: []inputInfo{
13436				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13437				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13438				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13439			},
13440			outputs: []outputInfo{
13441				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13442			},
13443		},
13444	},
13445	{
13446		name:   "ANDshiftRLreg",
13447		argLen: 3,
13448		asm:    arm.AAND,
13449		reg: regInfo{
13450			inputs: []inputInfo{
13451				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13452				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13453				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13454			},
13455			outputs: []outputInfo{
13456				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13457			},
13458		},
13459	},
13460	{
13461		name:   "ANDshiftRAreg",
13462		argLen: 3,
13463		asm:    arm.AAND,
13464		reg: regInfo{
13465			inputs: []inputInfo{
13466				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13467				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13468				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13469			},
13470			outputs: []outputInfo{
13471				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13472			},
13473		},
13474	},
13475	{
13476		name:   "ORshiftLLreg",
13477		argLen: 3,
13478		asm:    arm.AORR,
13479		reg: regInfo{
13480			inputs: []inputInfo{
13481				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13482				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13483				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13484			},
13485			outputs: []outputInfo{
13486				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13487			},
13488		},
13489	},
13490	{
13491		name:   "ORshiftRLreg",
13492		argLen: 3,
13493		asm:    arm.AORR,
13494		reg: regInfo{
13495			inputs: []inputInfo{
13496				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13497				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13498				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13499			},
13500			outputs: []outputInfo{
13501				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13502			},
13503		},
13504	},
13505	{
13506		name:   "ORshiftRAreg",
13507		argLen: 3,
13508		asm:    arm.AORR,
13509		reg: regInfo{
13510			inputs: []inputInfo{
13511				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13512				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13513				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13514			},
13515			outputs: []outputInfo{
13516				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13517			},
13518		},
13519	},
13520	{
13521		name:   "XORshiftLLreg",
13522		argLen: 3,
13523		asm:    arm.AEOR,
13524		reg: regInfo{
13525			inputs: []inputInfo{
13526				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13527				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13528				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13529			},
13530			outputs: []outputInfo{
13531				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13532			},
13533		},
13534	},
13535	{
13536		name:   "XORshiftRLreg",
13537		argLen: 3,
13538		asm:    arm.AEOR,
13539		reg: regInfo{
13540			inputs: []inputInfo{
13541				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13542				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13543				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13544			},
13545			outputs: []outputInfo{
13546				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13547			},
13548		},
13549	},
13550	{
13551		name:   "XORshiftRAreg",
13552		argLen: 3,
13553		asm:    arm.AEOR,
13554		reg: regInfo{
13555			inputs: []inputInfo{
13556				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13557				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13558				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13559			},
13560			outputs: []outputInfo{
13561				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13562			},
13563		},
13564	},
13565	{
13566		name:   "BICshiftLLreg",
13567		argLen: 3,
13568		asm:    arm.ABIC,
13569		reg: regInfo{
13570			inputs: []inputInfo{
13571				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13572				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13573				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13574			},
13575			outputs: []outputInfo{
13576				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13577			},
13578		},
13579	},
13580	{
13581		name:   "BICshiftRLreg",
13582		argLen: 3,
13583		asm:    arm.ABIC,
13584		reg: regInfo{
13585			inputs: []inputInfo{
13586				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13587				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13588				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13589			},
13590			outputs: []outputInfo{
13591				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13592			},
13593		},
13594	},
13595	{
13596		name:   "BICshiftRAreg",
13597		argLen: 3,
13598		asm:    arm.ABIC,
13599		reg: regInfo{
13600			inputs: []inputInfo{
13601				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13602				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13603				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13604			},
13605			outputs: []outputInfo{
13606				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13607			},
13608		},
13609	},
13610	{
13611		name:   "MVNshiftLLreg",
13612		argLen: 2,
13613		asm:    arm.AMVN,
13614		reg: regInfo{
13615			inputs: []inputInfo{
13616				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13617				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13618			},
13619			outputs: []outputInfo{
13620				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13621			},
13622		},
13623	},
13624	{
13625		name:   "MVNshiftRLreg",
13626		argLen: 2,
13627		asm:    arm.AMVN,
13628		reg: regInfo{
13629			inputs: []inputInfo{
13630				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13631				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13632			},
13633			outputs: []outputInfo{
13634				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13635			},
13636		},
13637	},
13638	{
13639		name:   "MVNshiftRAreg",
13640		argLen: 2,
13641		asm:    arm.AMVN,
13642		reg: regInfo{
13643			inputs: []inputInfo{
13644				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13645				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13646			},
13647			outputs: []outputInfo{
13648				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13649			},
13650		},
13651	},
13652	{
13653		name:   "ADCshiftLLreg",
13654		argLen: 4,
13655		asm:    arm.AADC,
13656		reg: regInfo{
13657			inputs: []inputInfo{
13658				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13659				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13660				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13661			},
13662			outputs: []outputInfo{
13663				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13664			},
13665		},
13666	},
13667	{
13668		name:   "ADCshiftRLreg",
13669		argLen: 4,
13670		asm:    arm.AADC,
13671		reg: regInfo{
13672			inputs: []inputInfo{
13673				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13674				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13675				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13676			},
13677			outputs: []outputInfo{
13678				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13679			},
13680		},
13681	},
13682	{
13683		name:   "ADCshiftRAreg",
13684		argLen: 4,
13685		asm:    arm.AADC,
13686		reg: regInfo{
13687			inputs: []inputInfo{
13688				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13689				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13690				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13691			},
13692			outputs: []outputInfo{
13693				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13694			},
13695		},
13696	},
13697	{
13698		name:   "SBCshiftLLreg",
13699		argLen: 4,
13700		asm:    arm.ASBC,
13701		reg: regInfo{
13702			inputs: []inputInfo{
13703				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13704				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13705				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13706			},
13707			outputs: []outputInfo{
13708				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13709			},
13710		},
13711	},
13712	{
13713		name:   "SBCshiftRLreg",
13714		argLen: 4,
13715		asm:    arm.ASBC,
13716		reg: regInfo{
13717			inputs: []inputInfo{
13718				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13719				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13720				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13721			},
13722			outputs: []outputInfo{
13723				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13724			},
13725		},
13726	},
13727	{
13728		name:   "SBCshiftRAreg",
13729		argLen: 4,
13730		asm:    arm.ASBC,
13731		reg: regInfo{
13732			inputs: []inputInfo{
13733				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13734				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13735				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13736			},
13737			outputs: []outputInfo{
13738				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13739			},
13740		},
13741	},
13742	{
13743		name:   "RSCshiftLLreg",
13744		argLen: 4,
13745		asm:    arm.ARSC,
13746		reg: regInfo{
13747			inputs: []inputInfo{
13748				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13749				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13750				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13751			},
13752			outputs: []outputInfo{
13753				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13754			},
13755		},
13756	},
13757	{
13758		name:   "RSCshiftRLreg",
13759		argLen: 4,
13760		asm:    arm.ARSC,
13761		reg: regInfo{
13762			inputs: []inputInfo{
13763				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13764				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13765				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13766			},
13767			outputs: []outputInfo{
13768				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13769			},
13770		},
13771	},
13772	{
13773		name:   "RSCshiftRAreg",
13774		argLen: 4,
13775		asm:    arm.ARSC,
13776		reg: regInfo{
13777			inputs: []inputInfo{
13778				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13779				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13780				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13781			},
13782			outputs: []outputInfo{
13783				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13784			},
13785		},
13786	},
13787	{
13788		name:   "ADDSshiftLLreg",
13789		argLen: 3,
13790		asm:    arm.AADD,
13791		reg: regInfo{
13792			inputs: []inputInfo{
13793				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13794				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13795				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13796			},
13797			outputs: []outputInfo{
13798				{1, 0},
13799				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13800			},
13801		},
13802	},
13803	{
13804		name:   "ADDSshiftRLreg",
13805		argLen: 3,
13806		asm:    arm.AADD,
13807		reg: regInfo{
13808			inputs: []inputInfo{
13809				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13810				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13811				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13812			},
13813			outputs: []outputInfo{
13814				{1, 0},
13815				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13816			},
13817		},
13818	},
13819	{
13820		name:   "ADDSshiftRAreg",
13821		argLen: 3,
13822		asm:    arm.AADD,
13823		reg: regInfo{
13824			inputs: []inputInfo{
13825				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13826				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13827				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13828			},
13829			outputs: []outputInfo{
13830				{1, 0},
13831				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13832			},
13833		},
13834	},
13835	{
13836		name:   "SUBSshiftLLreg",
13837		argLen: 3,
13838		asm:    arm.ASUB,
13839		reg: regInfo{
13840			inputs: []inputInfo{
13841				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13842				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13843				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13844			},
13845			outputs: []outputInfo{
13846				{1, 0},
13847				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13848			},
13849		},
13850	},
13851	{
13852		name:   "SUBSshiftRLreg",
13853		argLen: 3,
13854		asm:    arm.ASUB,
13855		reg: regInfo{
13856			inputs: []inputInfo{
13857				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13858				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13859				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13860			},
13861			outputs: []outputInfo{
13862				{1, 0},
13863				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13864			},
13865		},
13866	},
13867	{
13868		name:   "SUBSshiftRAreg",
13869		argLen: 3,
13870		asm:    arm.ASUB,
13871		reg: regInfo{
13872			inputs: []inputInfo{
13873				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13874				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13875				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13876			},
13877			outputs: []outputInfo{
13878				{1, 0},
13879				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13880			},
13881		},
13882	},
13883	{
13884		name:   "RSBSshiftLLreg",
13885		argLen: 3,
13886		asm:    arm.ARSB,
13887		reg: regInfo{
13888			inputs: []inputInfo{
13889				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13890				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13891				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13892			},
13893			outputs: []outputInfo{
13894				{1, 0},
13895				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13896			},
13897		},
13898	},
13899	{
13900		name:   "RSBSshiftRLreg",
13901		argLen: 3,
13902		asm:    arm.ARSB,
13903		reg: regInfo{
13904			inputs: []inputInfo{
13905				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13906				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13907				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13908			},
13909			outputs: []outputInfo{
13910				{1, 0},
13911				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13912			},
13913		},
13914	},
13915	{
13916		name:   "RSBSshiftRAreg",
13917		argLen: 3,
13918		asm:    arm.ARSB,
13919		reg: regInfo{
13920			inputs: []inputInfo{
13921				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13922				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13923				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13924			},
13925			outputs: []outputInfo{
13926				{1, 0},
13927				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13928			},
13929		},
13930	},
13931	{
13932		name:   "CMP",
13933		argLen: 2,
13934		asm:    arm.ACMP,
13935		reg: regInfo{
13936			inputs: []inputInfo{
13937				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13938				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13939			},
13940		},
13941	},
13942	{
13943		name:    "CMPconst",
13944		auxType: auxInt32,
13945		argLen:  1,
13946		asm:     arm.ACMP,
13947		reg: regInfo{
13948			inputs: []inputInfo{
13949				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13950			},
13951		},
13952	},
13953	{
13954		name:        "CMN",
13955		argLen:      2,
13956		commutative: true,
13957		asm:         arm.ACMN,
13958		reg: regInfo{
13959			inputs: []inputInfo{
13960				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13961				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13962			},
13963		},
13964	},
13965	{
13966		name:    "CMNconst",
13967		auxType: auxInt32,
13968		argLen:  1,
13969		asm:     arm.ACMN,
13970		reg: regInfo{
13971			inputs: []inputInfo{
13972				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13973			},
13974		},
13975	},
13976	{
13977		name:        "TST",
13978		argLen:      2,
13979		commutative: true,
13980		asm:         arm.ATST,
13981		reg: regInfo{
13982			inputs: []inputInfo{
13983				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13984				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13985			},
13986		},
13987	},
13988	{
13989		name:    "TSTconst",
13990		auxType: auxInt32,
13991		argLen:  1,
13992		asm:     arm.ATST,
13993		reg: regInfo{
13994			inputs: []inputInfo{
13995				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13996			},
13997		},
13998	},
13999	{
14000		name:        "TEQ",
14001		argLen:      2,
14002		commutative: true,
14003		asm:         arm.ATEQ,
14004		reg: regInfo{
14005			inputs: []inputInfo{
14006				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14007				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14008			},
14009		},
14010	},
14011	{
14012		name:    "TEQconst",
14013		auxType: auxInt32,
14014		argLen:  1,
14015		asm:     arm.ATEQ,
14016		reg: regInfo{
14017			inputs: []inputInfo{
14018				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14019			},
14020		},
14021	},
14022	{
14023		name:   "CMPF",
14024		argLen: 2,
14025		asm:    arm.ACMPF,
14026		reg: regInfo{
14027			inputs: []inputInfo{
14028				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14029				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14030			},
14031		},
14032	},
14033	{
14034		name:   "CMPD",
14035		argLen: 2,
14036		asm:    arm.ACMPD,
14037		reg: regInfo{
14038			inputs: []inputInfo{
14039				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14040				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14041			},
14042		},
14043	},
14044	{
14045		name:    "CMPshiftLL",
14046		auxType: auxInt32,
14047		argLen:  2,
14048		asm:     arm.ACMP,
14049		reg: regInfo{
14050			inputs: []inputInfo{
14051				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14052				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14053			},
14054		},
14055	},
14056	{
14057		name:    "CMPshiftRL",
14058		auxType: auxInt32,
14059		argLen:  2,
14060		asm:     arm.ACMP,
14061		reg: regInfo{
14062			inputs: []inputInfo{
14063				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14064				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14065			},
14066		},
14067	},
14068	{
14069		name:    "CMPshiftRA",
14070		auxType: auxInt32,
14071		argLen:  2,
14072		asm:     arm.ACMP,
14073		reg: regInfo{
14074			inputs: []inputInfo{
14075				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14076				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14077			},
14078		},
14079	},
14080	{
14081		name:    "CMNshiftLL",
14082		auxType: auxInt32,
14083		argLen:  2,
14084		asm:     arm.ACMN,
14085		reg: regInfo{
14086			inputs: []inputInfo{
14087				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14088				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14089			},
14090		},
14091	},
14092	{
14093		name:    "CMNshiftRL",
14094		auxType: auxInt32,
14095		argLen:  2,
14096		asm:     arm.ACMN,
14097		reg: regInfo{
14098			inputs: []inputInfo{
14099				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14100				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14101			},
14102		},
14103	},
14104	{
14105		name:    "CMNshiftRA",
14106		auxType: auxInt32,
14107		argLen:  2,
14108		asm:     arm.ACMN,
14109		reg: regInfo{
14110			inputs: []inputInfo{
14111				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14112				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14113			},
14114		},
14115	},
14116	{
14117		name:    "TSTshiftLL",
14118		auxType: auxInt32,
14119		argLen:  2,
14120		asm:     arm.ATST,
14121		reg: regInfo{
14122			inputs: []inputInfo{
14123				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14124				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14125			},
14126		},
14127	},
14128	{
14129		name:    "TSTshiftRL",
14130		auxType: auxInt32,
14131		argLen:  2,
14132		asm:     arm.ATST,
14133		reg: regInfo{
14134			inputs: []inputInfo{
14135				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14136				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14137			},
14138		},
14139	},
14140	{
14141		name:    "TSTshiftRA",
14142		auxType: auxInt32,
14143		argLen:  2,
14144		asm:     arm.ATST,
14145		reg: regInfo{
14146			inputs: []inputInfo{
14147				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14148				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14149			},
14150		},
14151	},
14152	{
14153		name:    "TEQshiftLL",
14154		auxType: auxInt32,
14155		argLen:  2,
14156		asm:     arm.ATEQ,
14157		reg: regInfo{
14158			inputs: []inputInfo{
14159				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14160				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14161			},
14162		},
14163	},
14164	{
14165		name:    "TEQshiftRL",
14166		auxType: auxInt32,
14167		argLen:  2,
14168		asm:     arm.ATEQ,
14169		reg: regInfo{
14170			inputs: []inputInfo{
14171				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14172				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14173			},
14174		},
14175	},
14176	{
14177		name:    "TEQshiftRA",
14178		auxType: auxInt32,
14179		argLen:  2,
14180		asm:     arm.ATEQ,
14181		reg: regInfo{
14182			inputs: []inputInfo{
14183				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14184				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14185			},
14186		},
14187	},
14188	{
14189		name:   "CMPshiftLLreg",
14190		argLen: 3,
14191		asm:    arm.ACMP,
14192		reg: regInfo{
14193			inputs: []inputInfo{
14194				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14195				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14196				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14197			},
14198		},
14199	},
14200	{
14201		name:   "CMPshiftRLreg",
14202		argLen: 3,
14203		asm:    arm.ACMP,
14204		reg: regInfo{
14205			inputs: []inputInfo{
14206				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14207				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14208				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14209			},
14210		},
14211	},
14212	{
14213		name:   "CMPshiftRAreg",
14214		argLen: 3,
14215		asm:    arm.ACMP,
14216		reg: regInfo{
14217			inputs: []inputInfo{
14218				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14219				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14220				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14221			},
14222		},
14223	},
14224	{
14225		name:   "CMNshiftLLreg",
14226		argLen: 3,
14227		asm:    arm.ACMN,
14228		reg: regInfo{
14229			inputs: []inputInfo{
14230				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14231				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14232				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14233			},
14234		},
14235	},
14236	{
14237		name:   "CMNshiftRLreg",
14238		argLen: 3,
14239		asm:    arm.ACMN,
14240		reg: regInfo{
14241			inputs: []inputInfo{
14242				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14243				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14244				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14245			},
14246		},
14247	},
14248	{
14249		name:   "CMNshiftRAreg",
14250		argLen: 3,
14251		asm:    arm.ACMN,
14252		reg: regInfo{
14253			inputs: []inputInfo{
14254				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14255				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14256				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14257			},
14258		},
14259	},
14260	{
14261		name:   "TSTshiftLLreg",
14262		argLen: 3,
14263		asm:    arm.ATST,
14264		reg: regInfo{
14265			inputs: []inputInfo{
14266				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14267				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14268				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14269			},
14270		},
14271	},
14272	{
14273		name:   "TSTshiftRLreg",
14274		argLen: 3,
14275		asm:    arm.ATST,
14276		reg: regInfo{
14277			inputs: []inputInfo{
14278				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14279				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14280				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14281			},
14282		},
14283	},
14284	{
14285		name:   "TSTshiftRAreg",
14286		argLen: 3,
14287		asm:    arm.ATST,
14288		reg: regInfo{
14289			inputs: []inputInfo{
14290				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14291				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14292				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14293			},
14294		},
14295	},
14296	{
14297		name:   "TEQshiftLLreg",
14298		argLen: 3,
14299		asm:    arm.ATEQ,
14300		reg: regInfo{
14301			inputs: []inputInfo{
14302				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14303				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14304				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14305			},
14306		},
14307	},
14308	{
14309		name:   "TEQshiftRLreg",
14310		argLen: 3,
14311		asm:    arm.ATEQ,
14312		reg: regInfo{
14313			inputs: []inputInfo{
14314				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14315				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14316				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14317			},
14318		},
14319	},
14320	{
14321		name:   "TEQshiftRAreg",
14322		argLen: 3,
14323		asm:    arm.ATEQ,
14324		reg: regInfo{
14325			inputs: []inputInfo{
14326				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14327				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14328				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14329			},
14330		},
14331	},
14332	{
14333		name:   "CMPF0",
14334		argLen: 1,
14335		asm:    arm.ACMPF,
14336		reg: regInfo{
14337			inputs: []inputInfo{
14338				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14339			},
14340		},
14341	},
14342	{
14343		name:   "CMPD0",
14344		argLen: 1,
14345		asm:    arm.ACMPD,
14346		reg: regInfo{
14347			inputs: []inputInfo{
14348				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14349			},
14350		},
14351	},
14352	{
14353		name:              "MOVWconst",
14354		auxType:           auxInt32,
14355		argLen:            0,
14356		rematerializeable: true,
14357		asm:               arm.AMOVW,
14358		reg: regInfo{
14359			outputs: []outputInfo{
14360				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14361			},
14362		},
14363	},
14364	{
14365		name:              "MOVFconst",
14366		auxType:           auxFloat64,
14367		argLen:            0,
14368		rematerializeable: true,
14369		asm:               arm.AMOVF,
14370		reg: regInfo{
14371			outputs: []outputInfo{
14372				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14373			},
14374		},
14375	},
14376	{
14377		name:              "MOVDconst",
14378		auxType:           auxFloat64,
14379		argLen:            0,
14380		rematerializeable: true,
14381		asm:               arm.AMOVD,
14382		reg: regInfo{
14383			outputs: []outputInfo{
14384				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14385			},
14386		},
14387	},
14388	{
14389		name:              "MOVWaddr",
14390		auxType:           auxSymOff,
14391		argLen:            1,
14392		rematerializeable: true,
14393		symEffect:         SymAddr,
14394		asm:               arm.AMOVW,
14395		reg: regInfo{
14396			inputs: []inputInfo{
14397				{0, 4294975488}, // SP SB
14398			},
14399			outputs: []outputInfo{
14400				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14401			},
14402		},
14403	},
14404	{
14405		name:           "MOVBload",
14406		auxType:        auxSymOff,
14407		argLen:         2,
14408		faultOnNilArg0: true,
14409		symEffect:      SymRead,
14410		asm:            arm.AMOVB,
14411		reg: regInfo{
14412			inputs: []inputInfo{
14413				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14414			},
14415			outputs: []outputInfo{
14416				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14417			},
14418		},
14419	},
14420	{
14421		name:           "MOVBUload",
14422		auxType:        auxSymOff,
14423		argLen:         2,
14424		faultOnNilArg0: true,
14425		symEffect:      SymRead,
14426		asm:            arm.AMOVBU,
14427		reg: regInfo{
14428			inputs: []inputInfo{
14429				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14430			},
14431			outputs: []outputInfo{
14432				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14433			},
14434		},
14435	},
14436	{
14437		name:           "MOVHload",
14438		auxType:        auxSymOff,
14439		argLen:         2,
14440		faultOnNilArg0: true,
14441		symEffect:      SymRead,
14442		asm:            arm.AMOVH,
14443		reg: regInfo{
14444			inputs: []inputInfo{
14445				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14446			},
14447			outputs: []outputInfo{
14448				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14449			},
14450		},
14451	},
14452	{
14453		name:           "MOVHUload",
14454		auxType:        auxSymOff,
14455		argLen:         2,
14456		faultOnNilArg0: true,
14457		symEffect:      SymRead,
14458		asm:            arm.AMOVHU,
14459		reg: regInfo{
14460			inputs: []inputInfo{
14461				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14462			},
14463			outputs: []outputInfo{
14464				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14465			},
14466		},
14467	},
14468	{
14469		name:           "MOVWload",
14470		auxType:        auxSymOff,
14471		argLen:         2,
14472		faultOnNilArg0: true,
14473		symEffect:      SymRead,
14474		asm:            arm.AMOVW,
14475		reg: regInfo{
14476			inputs: []inputInfo{
14477				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14478			},
14479			outputs: []outputInfo{
14480				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14481			},
14482		},
14483	},
14484	{
14485		name:           "MOVFload",
14486		auxType:        auxSymOff,
14487		argLen:         2,
14488		faultOnNilArg0: true,
14489		symEffect:      SymRead,
14490		asm:            arm.AMOVF,
14491		reg: regInfo{
14492			inputs: []inputInfo{
14493				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14494			},
14495			outputs: []outputInfo{
14496				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14497			},
14498		},
14499	},
14500	{
14501		name:           "MOVDload",
14502		auxType:        auxSymOff,
14503		argLen:         2,
14504		faultOnNilArg0: true,
14505		symEffect:      SymRead,
14506		asm:            arm.AMOVD,
14507		reg: regInfo{
14508			inputs: []inputInfo{
14509				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14510			},
14511			outputs: []outputInfo{
14512				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14513			},
14514		},
14515	},
14516	{
14517		name:           "MOVBstore",
14518		auxType:        auxSymOff,
14519		argLen:         3,
14520		faultOnNilArg0: true,
14521		symEffect:      SymWrite,
14522		asm:            arm.AMOVB,
14523		reg: regInfo{
14524			inputs: []inputInfo{
14525				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14526				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14527			},
14528		},
14529	},
14530	{
14531		name:           "MOVHstore",
14532		auxType:        auxSymOff,
14533		argLen:         3,
14534		faultOnNilArg0: true,
14535		symEffect:      SymWrite,
14536		asm:            arm.AMOVH,
14537		reg: regInfo{
14538			inputs: []inputInfo{
14539				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14540				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14541			},
14542		},
14543	},
14544	{
14545		name:           "MOVWstore",
14546		auxType:        auxSymOff,
14547		argLen:         3,
14548		faultOnNilArg0: true,
14549		symEffect:      SymWrite,
14550		asm:            arm.AMOVW,
14551		reg: regInfo{
14552			inputs: []inputInfo{
14553				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14554				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14555			},
14556		},
14557	},
14558	{
14559		name:           "MOVFstore",
14560		auxType:        auxSymOff,
14561		argLen:         3,
14562		faultOnNilArg0: true,
14563		symEffect:      SymWrite,
14564		asm:            arm.AMOVF,
14565		reg: regInfo{
14566			inputs: []inputInfo{
14567				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14568				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14569			},
14570		},
14571	},
14572	{
14573		name:           "MOVDstore",
14574		auxType:        auxSymOff,
14575		argLen:         3,
14576		faultOnNilArg0: true,
14577		symEffect:      SymWrite,
14578		asm:            arm.AMOVD,
14579		reg: regInfo{
14580			inputs: []inputInfo{
14581				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14582				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14583			},
14584		},
14585	},
14586	{
14587		name:   "MOVWloadidx",
14588		argLen: 3,
14589		asm:    arm.AMOVW,
14590		reg: regInfo{
14591			inputs: []inputInfo{
14592				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14593				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14594			},
14595			outputs: []outputInfo{
14596				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14597			},
14598		},
14599	},
14600	{
14601		name:    "MOVWloadshiftLL",
14602		auxType: auxInt32,
14603		argLen:  3,
14604		asm:     arm.AMOVW,
14605		reg: regInfo{
14606			inputs: []inputInfo{
14607				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14608				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14609			},
14610			outputs: []outputInfo{
14611				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14612			},
14613		},
14614	},
14615	{
14616		name:    "MOVWloadshiftRL",
14617		auxType: auxInt32,
14618		argLen:  3,
14619		asm:     arm.AMOVW,
14620		reg: regInfo{
14621			inputs: []inputInfo{
14622				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14623				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14624			},
14625			outputs: []outputInfo{
14626				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14627			},
14628		},
14629	},
14630	{
14631		name:    "MOVWloadshiftRA",
14632		auxType: auxInt32,
14633		argLen:  3,
14634		asm:     arm.AMOVW,
14635		reg: regInfo{
14636			inputs: []inputInfo{
14637				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14638				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14639			},
14640			outputs: []outputInfo{
14641				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14642			},
14643		},
14644	},
14645	{
14646		name:   "MOVBUloadidx",
14647		argLen: 3,
14648		asm:    arm.AMOVBU,
14649		reg: regInfo{
14650			inputs: []inputInfo{
14651				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14652				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14653			},
14654			outputs: []outputInfo{
14655				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14656			},
14657		},
14658	},
14659	{
14660		name:   "MOVBloadidx",
14661		argLen: 3,
14662		asm:    arm.AMOVB,
14663		reg: regInfo{
14664			inputs: []inputInfo{
14665				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14666				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14667			},
14668			outputs: []outputInfo{
14669				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14670			},
14671		},
14672	},
14673	{
14674		name:   "MOVHUloadidx",
14675		argLen: 3,
14676		asm:    arm.AMOVHU,
14677		reg: regInfo{
14678			inputs: []inputInfo{
14679				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14680				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14681			},
14682			outputs: []outputInfo{
14683				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14684			},
14685		},
14686	},
14687	{
14688		name:   "MOVHloadidx",
14689		argLen: 3,
14690		asm:    arm.AMOVH,
14691		reg: regInfo{
14692			inputs: []inputInfo{
14693				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14694				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14695			},
14696			outputs: []outputInfo{
14697				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14698			},
14699		},
14700	},
14701	{
14702		name:   "MOVWstoreidx",
14703		argLen: 4,
14704		asm:    arm.AMOVW,
14705		reg: regInfo{
14706			inputs: []inputInfo{
14707				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14708				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14709				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14710			},
14711		},
14712	},
14713	{
14714		name:    "MOVWstoreshiftLL",
14715		auxType: auxInt32,
14716		argLen:  4,
14717		asm:     arm.AMOVW,
14718		reg: regInfo{
14719			inputs: []inputInfo{
14720				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14721				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14722				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14723			},
14724		},
14725	},
14726	{
14727		name:    "MOVWstoreshiftRL",
14728		auxType: auxInt32,
14729		argLen:  4,
14730		asm:     arm.AMOVW,
14731		reg: regInfo{
14732			inputs: []inputInfo{
14733				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14734				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14735				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14736			},
14737		},
14738	},
14739	{
14740		name:    "MOVWstoreshiftRA",
14741		auxType: auxInt32,
14742		argLen:  4,
14743		asm:     arm.AMOVW,
14744		reg: regInfo{
14745			inputs: []inputInfo{
14746				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14747				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14748				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14749			},
14750		},
14751	},
14752	{
14753		name:   "MOVBstoreidx",
14754		argLen: 4,
14755		asm:    arm.AMOVB,
14756		reg: regInfo{
14757			inputs: []inputInfo{
14758				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14759				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14760				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14761			},
14762		},
14763	},
14764	{
14765		name:   "MOVHstoreidx",
14766		argLen: 4,
14767		asm:    arm.AMOVH,
14768		reg: regInfo{
14769			inputs: []inputInfo{
14770				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14771				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14772				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
14773			},
14774		},
14775	},
14776	{
14777		name:   "MOVBreg",
14778		argLen: 1,
14779		asm:    arm.AMOVBS,
14780		reg: regInfo{
14781			inputs: []inputInfo{
14782				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14783			},
14784			outputs: []outputInfo{
14785				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14786			},
14787		},
14788	},
14789	{
14790		name:   "MOVBUreg",
14791		argLen: 1,
14792		asm:    arm.AMOVBU,
14793		reg: regInfo{
14794			inputs: []inputInfo{
14795				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14796			},
14797			outputs: []outputInfo{
14798				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14799			},
14800		},
14801	},
14802	{
14803		name:   "MOVHreg",
14804		argLen: 1,
14805		asm:    arm.AMOVHS,
14806		reg: regInfo{
14807			inputs: []inputInfo{
14808				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14809			},
14810			outputs: []outputInfo{
14811				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14812			},
14813		},
14814	},
14815	{
14816		name:   "MOVHUreg",
14817		argLen: 1,
14818		asm:    arm.AMOVHU,
14819		reg: regInfo{
14820			inputs: []inputInfo{
14821				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14822			},
14823			outputs: []outputInfo{
14824				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14825			},
14826		},
14827	},
14828	{
14829		name:   "MOVWreg",
14830		argLen: 1,
14831		asm:    arm.AMOVW,
14832		reg: regInfo{
14833			inputs: []inputInfo{
14834				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14835			},
14836			outputs: []outputInfo{
14837				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14838			},
14839		},
14840	},
14841	{
14842		name:         "MOVWnop",
14843		argLen:       1,
14844		resultInArg0: true,
14845		reg: regInfo{
14846			inputs: []inputInfo{
14847				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14848			},
14849			outputs: []outputInfo{
14850				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14851			},
14852		},
14853	},
14854	{
14855		name:   "MOVWF",
14856		argLen: 1,
14857		asm:    arm.AMOVWF,
14858		reg: regInfo{
14859			inputs: []inputInfo{
14860				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14861			},
14862			clobbers: 2147483648, // F15
14863			outputs: []outputInfo{
14864				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14865			},
14866		},
14867	},
14868	{
14869		name:   "MOVWD",
14870		argLen: 1,
14871		asm:    arm.AMOVWD,
14872		reg: regInfo{
14873			inputs: []inputInfo{
14874				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14875			},
14876			clobbers: 2147483648, // F15
14877			outputs: []outputInfo{
14878				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14879			},
14880		},
14881	},
14882	{
14883		name:   "MOVWUF",
14884		argLen: 1,
14885		asm:    arm.AMOVWF,
14886		reg: regInfo{
14887			inputs: []inputInfo{
14888				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14889			},
14890			clobbers: 2147483648, // F15
14891			outputs: []outputInfo{
14892				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14893			},
14894		},
14895	},
14896	{
14897		name:   "MOVWUD",
14898		argLen: 1,
14899		asm:    arm.AMOVWD,
14900		reg: regInfo{
14901			inputs: []inputInfo{
14902				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14903			},
14904			clobbers: 2147483648, // F15
14905			outputs: []outputInfo{
14906				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14907			},
14908		},
14909	},
14910	{
14911		name:   "MOVFW",
14912		argLen: 1,
14913		asm:    arm.AMOVFW,
14914		reg: regInfo{
14915			inputs: []inputInfo{
14916				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14917			},
14918			clobbers: 2147483648, // F15
14919			outputs: []outputInfo{
14920				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14921			},
14922		},
14923	},
14924	{
14925		name:   "MOVDW",
14926		argLen: 1,
14927		asm:    arm.AMOVDW,
14928		reg: regInfo{
14929			inputs: []inputInfo{
14930				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14931			},
14932			clobbers: 2147483648, // F15
14933			outputs: []outputInfo{
14934				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14935			},
14936		},
14937	},
14938	{
14939		name:   "MOVFWU",
14940		argLen: 1,
14941		asm:    arm.AMOVFW,
14942		reg: regInfo{
14943			inputs: []inputInfo{
14944				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14945			},
14946			clobbers: 2147483648, // F15
14947			outputs: []outputInfo{
14948				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14949			},
14950		},
14951	},
14952	{
14953		name:   "MOVDWU",
14954		argLen: 1,
14955		asm:    arm.AMOVDW,
14956		reg: regInfo{
14957			inputs: []inputInfo{
14958				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14959			},
14960			clobbers: 2147483648, // F15
14961			outputs: []outputInfo{
14962				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14963			},
14964		},
14965	},
14966	{
14967		name:   "MOVFD",
14968		argLen: 1,
14969		asm:    arm.AMOVFD,
14970		reg: regInfo{
14971			inputs: []inputInfo{
14972				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14973			},
14974			outputs: []outputInfo{
14975				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14976			},
14977		},
14978	},
14979	{
14980		name:   "MOVDF",
14981		argLen: 1,
14982		asm:    arm.AMOVDF,
14983		reg: regInfo{
14984			inputs: []inputInfo{
14985				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14986			},
14987			outputs: []outputInfo{
14988				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14989			},
14990		},
14991	},
14992	{
14993		name:         "CMOVWHSconst",
14994		auxType:      auxInt32,
14995		argLen:       2,
14996		resultInArg0: true,
14997		asm:          arm.AMOVW,
14998		reg: regInfo{
14999			inputs: []inputInfo{
15000				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15001			},
15002			outputs: []outputInfo{
15003				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15004			},
15005		},
15006	},
15007	{
15008		name:         "CMOVWLSconst",
15009		auxType:      auxInt32,
15010		argLen:       2,
15011		resultInArg0: true,
15012		asm:          arm.AMOVW,
15013		reg: regInfo{
15014			inputs: []inputInfo{
15015				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15016			},
15017			outputs: []outputInfo{
15018				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15019			},
15020		},
15021	},
15022	{
15023		name:   "SRAcond",
15024		argLen: 3,
15025		asm:    arm.ASRA,
15026		reg: regInfo{
15027			inputs: []inputInfo{
15028				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15029				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15030			},
15031			outputs: []outputInfo{
15032				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15033			},
15034		},
15035	},
15036	{
15037		name:         "CALLstatic",
15038		auxType:      auxSymOff,
15039		argLen:       1,
15040		clobberFlags: true,
15041		call:         true,
15042		symEffect:    SymNone,
15043		reg: regInfo{
15044			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15045		},
15046	},
15047	{
15048		name:         "CALLclosure",
15049		auxType:      auxInt64,
15050		argLen:       3,
15051		clobberFlags: true,
15052		call:         true,
15053		reg: regInfo{
15054			inputs: []inputInfo{
15055				{1, 128},   // R7
15056				{0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14
15057			},
15058			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15059		},
15060	},
15061	{
15062		name:         "CALLinter",
15063		auxType:      auxInt64,
15064		argLen:       2,
15065		clobberFlags: true,
15066		call:         true,
15067		reg: regInfo{
15068			inputs: []inputInfo{
15069				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15070			},
15071			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15072		},
15073	},
15074	{
15075		name:           "LoweredNilCheck",
15076		argLen:         2,
15077		nilCheck:       true,
15078		faultOnNilArg0: true,
15079		reg: regInfo{
15080			inputs: []inputInfo{
15081				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15082			},
15083		},
15084	},
15085	{
15086		name:   "Equal",
15087		argLen: 1,
15088		reg: regInfo{
15089			outputs: []outputInfo{
15090				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15091			},
15092		},
15093	},
15094	{
15095		name:   "NotEqual",
15096		argLen: 1,
15097		reg: regInfo{
15098			outputs: []outputInfo{
15099				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15100			},
15101		},
15102	},
15103	{
15104		name:   "LessThan",
15105		argLen: 1,
15106		reg: regInfo{
15107			outputs: []outputInfo{
15108				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15109			},
15110		},
15111	},
15112	{
15113		name:   "LessEqual",
15114		argLen: 1,
15115		reg: regInfo{
15116			outputs: []outputInfo{
15117				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15118			},
15119		},
15120	},
15121	{
15122		name:   "GreaterThan",
15123		argLen: 1,
15124		reg: regInfo{
15125			outputs: []outputInfo{
15126				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15127			},
15128		},
15129	},
15130	{
15131		name:   "GreaterEqual",
15132		argLen: 1,
15133		reg: regInfo{
15134			outputs: []outputInfo{
15135				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15136			},
15137		},
15138	},
15139	{
15140		name:   "LessThanU",
15141		argLen: 1,
15142		reg: regInfo{
15143			outputs: []outputInfo{
15144				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15145			},
15146		},
15147	},
15148	{
15149		name:   "LessEqualU",
15150		argLen: 1,
15151		reg: regInfo{
15152			outputs: []outputInfo{
15153				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15154			},
15155		},
15156	},
15157	{
15158		name:   "GreaterThanU",
15159		argLen: 1,
15160		reg: regInfo{
15161			outputs: []outputInfo{
15162				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15163			},
15164		},
15165	},
15166	{
15167		name:   "GreaterEqualU",
15168		argLen: 1,
15169		reg: regInfo{
15170			outputs: []outputInfo{
15171				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15172			},
15173		},
15174	},
15175	{
15176		name:           "DUFFZERO",
15177		auxType:        auxInt64,
15178		argLen:         3,
15179		faultOnNilArg0: true,
15180		reg: regInfo{
15181			inputs: []inputInfo{
15182				{0, 2}, // R1
15183				{1, 1}, // R0
15184			},
15185			clobbers: 16386, // R1 R14
15186		},
15187	},
15188	{
15189		name:           "DUFFCOPY",
15190		auxType:        auxInt64,
15191		argLen:         3,
15192		faultOnNilArg0: true,
15193		faultOnNilArg1: true,
15194		reg: regInfo{
15195			inputs: []inputInfo{
15196				{0, 4}, // R2
15197				{1, 2}, // R1
15198			},
15199			clobbers: 16391, // R0 R1 R2 R14
15200		},
15201	},
15202	{
15203		name:           "LoweredZero",
15204		auxType:        auxInt64,
15205		argLen:         4,
15206		clobberFlags:   true,
15207		faultOnNilArg0: true,
15208		reg: regInfo{
15209			inputs: []inputInfo{
15210				{0, 2},     // R1
15211				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15212				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15213			},
15214			clobbers: 2, // R1
15215		},
15216	},
15217	{
15218		name:           "LoweredMove",
15219		auxType:        auxInt64,
15220		argLen:         4,
15221		clobberFlags:   true,
15222		faultOnNilArg0: true,
15223		faultOnNilArg1: true,
15224		reg: regInfo{
15225			inputs: []inputInfo{
15226				{0, 4},     // R2
15227				{1, 2},     // R1
15228				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15229			},
15230			clobbers: 6, // R1 R2
15231		},
15232	},
15233	{
15234		name:      "LoweredGetClosurePtr",
15235		argLen:    0,
15236		zeroWidth: true,
15237		reg: regInfo{
15238			outputs: []outputInfo{
15239				{0, 128}, // R7
15240			},
15241		},
15242	},
15243	{
15244		name:              "LoweredGetCallerSP",
15245		argLen:            0,
15246		rematerializeable: true,
15247		reg: regInfo{
15248			outputs: []outputInfo{
15249				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15250			},
15251		},
15252	},
15253	{
15254		name:              "LoweredGetCallerPC",
15255		argLen:            0,
15256		rematerializeable: true,
15257		reg: regInfo{
15258			outputs: []outputInfo{
15259				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15260			},
15261		},
15262	},
15263	{
15264		name:    "LoweredPanicBoundsA",
15265		auxType: auxInt64,
15266		argLen:  3,
15267		reg: regInfo{
15268			inputs: []inputInfo{
15269				{0, 4}, // R2
15270				{1, 8}, // R3
15271			},
15272		},
15273	},
15274	{
15275		name:    "LoweredPanicBoundsB",
15276		auxType: auxInt64,
15277		argLen:  3,
15278		reg: regInfo{
15279			inputs: []inputInfo{
15280				{0, 2}, // R1
15281				{1, 4}, // R2
15282			},
15283		},
15284	},
15285	{
15286		name:    "LoweredPanicBoundsC",
15287		auxType: auxInt64,
15288		argLen:  3,
15289		reg: regInfo{
15290			inputs: []inputInfo{
15291				{0, 1}, // R0
15292				{1, 2}, // R1
15293			},
15294		},
15295	},
15296	{
15297		name:    "LoweredPanicExtendA",
15298		auxType: auxInt64,
15299		argLen:  4,
15300		reg: regInfo{
15301			inputs: []inputInfo{
15302				{0, 16}, // R4
15303				{1, 4},  // R2
15304				{2, 8},  // R3
15305			},
15306		},
15307	},
15308	{
15309		name:    "LoweredPanicExtendB",
15310		auxType: auxInt64,
15311		argLen:  4,
15312		reg: regInfo{
15313			inputs: []inputInfo{
15314				{0, 16}, // R4
15315				{1, 2},  // R1
15316				{2, 4},  // R2
15317			},
15318		},
15319	},
15320	{
15321		name:    "LoweredPanicExtendC",
15322		auxType: auxInt64,
15323		argLen:  4,
15324		reg: regInfo{
15325			inputs: []inputInfo{
15326				{0, 16}, // R4
15327				{1, 1},  // R0
15328				{2, 2},  // R1
15329			},
15330		},
15331	},
15332	{
15333		name:   "FlagEQ",
15334		argLen: 0,
15335		reg:    regInfo{},
15336	},
15337	{
15338		name:   "FlagLT_ULT",
15339		argLen: 0,
15340		reg:    regInfo{},
15341	},
15342	{
15343		name:   "FlagLT_UGT",
15344		argLen: 0,
15345		reg:    regInfo{},
15346	},
15347	{
15348		name:   "FlagGT_UGT",
15349		argLen: 0,
15350		reg:    regInfo{},
15351	},
15352	{
15353		name:   "FlagGT_ULT",
15354		argLen: 0,
15355		reg:    regInfo{},
15356	},
15357	{
15358		name:   "InvertFlags",
15359		argLen: 1,
15360		reg:    regInfo{},
15361	},
15362	{
15363		name:         "LoweredWB",
15364		auxType:      auxSym,
15365		argLen:       3,
15366		clobberFlags: true,
15367		symEffect:    SymNone,
15368		reg: regInfo{
15369			inputs: []inputInfo{
15370				{0, 4}, // R2
15371				{1, 8}, // R3
15372			},
15373			clobbers: 4294918144, // R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
15374		},
15375	},
15376
15377	{
15378		name:        "ADCSflags",
15379		argLen:      3,
15380		commutative: true,
15381		asm:         arm64.AADCS,
15382		reg: regInfo{
15383			inputs: []inputInfo{
15384				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15385				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15386			},
15387			outputs: []outputInfo{
15388				{1, 0},
15389				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15390			},
15391		},
15392	},
15393	{
15394		name:   "ADCzerocarry",
15395		argLen: 1,
15396		asm:    arm64.AADC,
15397		reg: regInfo{
15398			outputs: []outputInfo{
15399				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15400			},
15401		},
15402	},
15403	{
15404		name:        "ADD",
15405		argLen:      2,
15406		commutative: true,
15407		asm:         arm64.AADD,
15408		reg: regInfo{
15409			inputs: []inputInfo{
15410				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15411				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15412			},
15413			outputs: []outputInfo{
15414				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15415			},
15416		},
15417	},
15418	{
15419		name:    "ADDconst",
15420		auxType: auxInt64,
15421		argLen:  1,
15422		asm:     arm64.AADD,
15423		reg: regInfo{
15424			inputs: []inputInfo{
15425				{0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP
15426			},
15427			outputs: []outputInfo{
15428				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15429			},
15430		},
15431	},
15432	{
15433		name:    "ADDSconstflags",
15434		auxType: auxInt64,
15435		argLen:  1,
15436		asm:     arm64.AADDS,
15437		reg: regInfo{
15438			inputs: []inputInfo{
15439				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15440			},
15441			outputs: []outputInfo{
15442				{1, 0},
15443				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15444			},
15445		},
15446	},
15447	{
15448		name:        "ADDSflags",
15449		argLen:      2,
15450		commutative: true,
15451		asm:         arm64.AADDS,
15452		reg: regInfo{
15453			inputs: []inputInfo{
15454				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15455				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15456			},
15457			outputs: []outputInfo{
15458				{1, 0},
15459				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15460			},
15461		},
15462	},
15463	{
15464		name:   "SUB",
15465		argLen: 2,
15466		asm:    arm64.ASUB,
15467		reg: regInfo{
15468			inputs: []inputInfo{
15469				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15470				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15471			},
15472			outputs: []outputInfo{
15473				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15474			},
15475		},
15476	},
15477	{
15478		name:    "SUBconst",
15479		auxType: auxInt64,
15480		argLen:  1,
15481		asm:     arm64.ASUB,
15482		reg: regInfo{
15483			inputs: []inputInfo{
15484				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15485			},
15486			outputs: []outputInfo{
15487				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15488			},
15489		},
15490	},
15491	{
15492		name:   "SBCSflags",
15493		argLen: 3,
15494		asm:    arm64.ASBCS,
15495		reg: regInfo{
15496			inputs: []inputInfo{
15497				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15498				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15499			},
15500			outputs: []outputInfo{
15501				{1, 0},
15502				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15503			},
15504		},
15505	},
15506	{
15507		name:   "SUBSflags",
15508		argLen: 2,
15509		asm:    arm64.ASUBS,
15510		reg: regInfo{
15511			inputs: []inputInfo{
15512				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15513				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15514			},
15515			outputs: []outputInfo{
15516				{1, 0},
15517				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15518			},
15519		},
15520	},
15521	{
15522		name:        "MUL",
15523		argLen:      2,
15524		commutative: true,
15525		asm:         arm64.AMUL,
15526		reg: regInfo{
15527			inputs: []inputInfo{
15528				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15529				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15530			},
15531			outputs: []outputInfo{
15532				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15533			},
15534		},
15535	},
15536	{
15537		name:        "MULW",
15538		argLen:      2,
15539		commutative: true,
15540		asm:         arm64.AMULW,
15541		reg: regInfo{
15542			inputs: []inputInfo{
15543				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15544				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15545			},
15546			outputs: []outputInfo{
15547				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15548			},
15549		},
15550	},
15551	{
15552		name:        "MNEG",
15553		argLen:      2,
15554		commutative: true,
15555		asm:         arm64.AMNEG,
15556		reg: regInfo{
15557			inputs: []inputInfo{
15558				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15559				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15560			},
15561			outputs: []outputInfo{
15562				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15563			},
15564		},
15565	},
15566	{
15567		name:        "MNEGW",
15568		argLen:      2,
15569		commutative: true,
15570		asm:         arm64.AMNEGW,
15571		reg: regInfo{
15572			inputs: []inputInfo{
15573				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15574				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15575			},
15576			outputs: []outputInfo{
15577				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15578			},
15579		},
15580	},
15581	{
15582		name:        "MULH",
15583		argLen:      2,
15584		commutative: true,
15585		asm:         arm64.ASMULH,
15586		reg: regInfo{
15587			inputs: []inputInfo{
15588				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15589				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15590			},
15591			outputs: []outputInfo{
15592				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15593			},
15594		},
15595	},
15596	{
15597		name:        "UMULH",
15598		argLen:      2,
15599		commutative: true,
15600		asm:         arm64.AUMULH,
15601		reg: regInfo{
15602			inputs: []inputInfo{
15603				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15604				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15605			},
15606			outputs: []outputInfo{
15607				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15608			},
15609		},
15610	},
15611	{
15612		name:        "MULL",
15613		argLen:      2,
15614		commutative: true,
15615		asm:         arm64.ASMULL,
15616		reg: regInfo{
15617			inputs: []inputInfo{
15618				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15619				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15620			},
15621			outputs: []outputInfo{
15622				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15623			},
15624		},
15625	},
15626	{
15627		name:        "UMULL",
15628		argLen:      2,
15629		commutative: true,
15630		asm:         arm64.AUMULL,
15631		reg: regInfo{
15632			inputs: []inputInfo{
15633				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15634				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15635			},
15636			outputs: []outputInfo{
15637				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15638			},
15639		},
15640	},
15641	{
15642		name:   "DIV",
15643		argLen: 2,
15644		asm:    arm64.ASDIV,
15645		reg: regInfo{
15646			inputs: []inputInfo{
15647				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15648				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15649			},
15650			outputs: []outputInfo{
15651				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15652			},
15653		},
15654	},
15655	{
15656		name:   "UDIV",
15657		argLen: 2,
15658		asm:    arm64.AUDIV,
15659		reg: regInfo{
15660			inputs: []inputInfo{
15661				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15662				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15663			},
15664			outputs: []outputInfo{
15665				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15666			},
15667		},
15668	},
15669	{
15670		name:   "DIVW",
15671		argLen: 2,
15672		asm:    arm64.ASDIVW,
15673		reg: regInfo{
15674			inputs: []inputInfo{
15675				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15676				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15677			},
15678			outputs: []outputInfo{
15679				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15680			},
15681		},
15682	},
15683	{
15684		name:   "UDIVW",
15685		argLen: 2,
15686		asm:    arm64.AUDIVW,
15687		reg: regInfo{
15688			inputs: []inputInfo{
15689				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15690				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15691			},
15692			outputs: []outputInfo{
15693				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15694			},
15695		},
15696	},
15697	{
15698		name:   "MOD",
15699		argLen: 2,
15700		asm:    arm64.AREM,
15701		reg: regInfo{
15702			inputs: []inputInfo{
15703				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15704				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15705			},
15706			outputs: []outputInfo{
15707				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15708			},
15709		},
15710	},
15711	{
15712		name:   "UMOD",
15713		argLen: 2,
15714		asm:    arm64.AUREM,
15715		reg: regInfo{
15716			inputs: []inputInfo{
15717				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15718				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15719			},
15720			outputs: []outputInfo{
15721				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15722			},
15723		},
15724	},
15725	{
15726		name:   "MODW",
15727		argLen: 2,
15728		asm:    arm64.AREMW,
15729		reg: regInfo{
15730			inputs: []inputInfo{
15731				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15732				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15733			},
15734			outputs: []outputInfo{
15735				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15736			},
15737		},
15738	},
15739	{
15740		name:   "UMODW",
15741		argLen: 2,
15742		asm:    arm64.AUREMW,
15743		reg: regInfo{
15744			inputs: []inputInfo{
15745				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15746				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15747			},
15748			outputs: []outputInfo{
15749				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15750			},
15751		},
15752	},
15753	{
15754		name:        "FADDS",
15755		argLen:      2,
15756		commutative: true,
15757		asm:         arm64.AFADDS,
15758		reg: regInfo{
15759			inputs: []inputInfo{
15760				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15761				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15762			},
15763			outputs: []outputInfo{
15764				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15765			},
15766		},
15767	},
15768	{
15769		name:        "FADDD",
15770		argLen:      2,
15771		commutative: true,
15772		asm:         arm64.AFADDD,
15773		reg: regInfo{
15774			inputs: []inputInfo{
15775				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15776				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15777			},
15778			outputs: []outputInfo{
15779				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15780			},
15781		},
15782	},
15783	{
15784		name:   "FSUBS",
15785		argLen: 2,
15786		asm:    arm64.AFSUBS,
15787		reg: regInfo{
15788			inputs: []inputInfo{
15789				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15790				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15791			},
15792			outputs: []outputInfo{
15793				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15794			},
15795		},
15796	},
15797	{
15798		name:   "FSUBD",
15799		argLen: 2,
15800		asm:    arm64.AFSUBD,
15801		reg: regInfo{
15802			inputs: []inputInfo{
15803				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15804				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15805			},
15806			outputs: []outputInfo{
15807				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15808			},
15809		},
15810	},
15811	{
15812		name:        "FMULS",
15813		argLen:      2,
15814		commutative: true,
15815		asm:         arm64.AFMULS,
15816		reg: regInfo{
15817			inputs: []inputInfo{
15818				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15819				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15820			},
15821			outputs: []outputInfo{
15822				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15823			},
15824		},
15825	},
15826	{
15827		name:        "FMULD",
15828		argLen:      2,
15829		commutative: true,
15830		asm:         arm64.AFMULD,
15831		reg: regInfo{
15832			inputs: []inputInfo{
15833				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15834				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15835			},
15836			outputs: []outputInfo{
15837				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15838			},
15839		},
15840	},
15841	{
15842		name:        "FNMULS",
15843		argLen:      2,
15844		commutative: true,
15845		asm:         arm64.AFNMULS,
15846		reg: regInfo{
15847			inputs: []inputInfo{
15848				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15849				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15850			},
15851			outputs: []outputInfo{
15852				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15853			},
15854		},
15855	},
15856	{
15857		name:        "FNMULD",
15858		argLen:      2,
15859		commutative: true,
15860		asm:         arm64.AFNMULD,
15861		reg: regInfo{
15862			inputs: []inputInfo{
15863				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15864				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15865			},
15866			outputs: []outputInfo{
15867				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15868			},
15869		},
15870	},
15871	{
15872		name:   "FDIVS",
15873		argLen: 2,
15874		asm:    arm64.AFDIVS,
15875		reg: regInfo{
15876			inputs: []inputInfo{
15877				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15878				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15879			},
15880			outputs: []outputInfo{
15881				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15882			},
15883		},
15884	},
15885	{
15886		name:   "FDIVD",
15887		argLen: 2,
15888		asm:    arm64.AFDIVD,
15889		reg: regInfo{
15890			inputs: []inputInfo{
15891				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15892				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15893			},
15894			outputs: []outputInfo{
15895				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
15896			},
15897		},
15898	},
15899	{
15900		name:        "AND",
15901		argLen:      2,
15902		commutative: true,
15903		asm:         arm64.AAND,
15904		reg: regInfo{
15905			inputs: []inputInfo{
15906				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15907				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15908			},
15909			outputs: []outputInfo{
15910				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15911			},
15912		},
15913	},
15914	{
15915		name:    "ANDconst",
15916		auxType: auxInt64,
15917		argLen:  1,
15918		asm:     arm64.AAND,
15919		reg: regInfo{
15920			inputs: []inputInfo{
15921				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15922			},
15923			outputs: []outputInfo{
15924				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15925			},
15926		},
15927	},
15928	{
15929		name:        "OR",
15930		argLen:      2,
15931		commutative: true,
15932		asm:         arm64.AORR,
15933		reg: regInfo{
15934			inputs: []inputInfo{
15935				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15936				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15937			},
15938			outputs: []outputInfo{
15939				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15940			},
15941		},
15942	},
15943	{
15944		name:    "ORconst",
15945		auxType: auxInt64,
15946		argLen:  1,
15947		asm:     arm64.AORR,
15948		reg: regInfo{
15949			inputs: []inputInfo{
15950				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15951			},
15952			outputs: []outputInfo{
15953				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15954			},
15955		},
15956	},
15957	{
15958		name:        "XOR",
15959		argLen:      2,
15960		commutative: true,
15961		asm:         arm64.AEOR,
15962		reg: regInfo{
15963			inputs: []inputInfo{
15964				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15965				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15966			},
15967			outputs: []outputInfo{
15968				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15969			},
15970		},
15971	},
15972	{
15973		name:    "XORconst",
15974		auxType: auxInt64,
15975		argLen:  1,
15976		asm:     arm64.AEOR,
15977		reg: regInfo{
15978			inputs: []inputInfo{
15979				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15980			},
15981			outputs: []outputInfo{
15982				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15983			},
15984		},
15985	},
15986	{
15987		name:   "BIC",
15988		argLen: 2,
15989		asm:    arm64.ABIC,
15990		reg: regInfo{
15991			inputs: []inputInfo{
15992				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15993				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
15994			},
15995			outputs: []outputInfo{
15996				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
15997			},
15998		},
15999	},
16000	{
16001		name:   "EON",
16002		argLen: 2,
16003		asm:    arm64.AEON,
16004		reg: regInfo{
16005			inputs: []inputInfo{
16006				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16007				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16008			},
16009			outputs: []outputInfo{
16010				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16011			},
16012		},
16013	},
16014	{
16015		name:   "ORN",
16016		argLen: 2,
16017		asm:    arm64.AORN,
16018		reg: regInfo{
16019			inputs: []inputInfo{
16020				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16021				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16022			},
16023			outputs: []outputInfo{
16024				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16025			},
16026		},
16027	},
16028	{
16029		name:            "LoweredMuluhilo",
16030		argLen:          2,
16031		resultNotInArgs: true,
16032		reg: regInfo{
16033			inputs: []inputInfo{
16034				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16035				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16036			},
16037			outputs: []outputInfo{
16038				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16039				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16040			},
16041		},
16042	},
16043	{
16044		name:   "MVN",
16045		argLen: 1,
16046		asm:    arm64.AMVN,
16047		reg: regInfo{
16048			inputs: []inputInfo{
16049				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16050			},
16051			outputs: []outputInfo{
16052				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16053			},
16054		},
16055	},
16056	{
16057		name:   "NEG",
16058		argLen: 1,
16059		asm:    arm64.ANEG,
16060		reg: regInfo{
16061			inputs: []inputInfo{
16062				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16063			},
16064			outputs: []outputInfo{
16065				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16066			},
16067		},
16068	},
16069	{
16070		name:   "NEGSflags",
16071		argLen: 1,
16072		asm:    arm64.ANEGS,
16073		reg: regInfo{
16074			inputs: []inputInfo{
16075				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16076			},
16077			outputs: []outputInfo{
16078				{1, 0},
16079				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16080			},
16081		},
16082	},
16083	{
16084		name:   "NGCzerocarry",
16085		argLen: 1,
16086		asm:    arm64.ANGC,
16087		reg: regInfo{
16088			outputs: []outputInfo{
16089				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16090			},
16091		},
16092	},
16093	{
16094		name:   "FABSD",
16095		argLen: 1,
16096		asm:    arm64.AFABSD,
16097		reg: regInfo{
16098			inputs: []inputInfo{
16099				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16100			},
16101			outputs: []outputInfo{
16102				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16103			},
16104		},
16105	},
16106	{
16107		name:   "FNEGS",
16108		argLen: 1,
16109		asm:    arm64.AFNEGS,
16110		reg: regInfo{
16111			inputs: []inputInfo{
16112				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16113			},
16114			outputs: []outputInfo{
16115				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16116			},
16117		},
16118	},
16119	{
16120		name:   "FNEGD",
16121		argLen: 1,
16122		asm:    arm64.AFNEGD,
16123		reg: regInfo{
16124			inputs: []inputInfo{
16125				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16126			},
16127			outputs: []outputInfo{
16128				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16129			},
16130		},
16131	},
16132	{
16133		name:   "FSQRTD",
16134		argLen: 1,
16135		asm:    arm64.AFSQRTD,
16136		reg: regInfo{
16137			inputs: []inputInfo{
16138				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16139			},
16140			outputs: []outputInfo{
16141				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16142			},
16143		},
16144	},
16145	{
16146		name:   "REV",
16147		argLen: 1,
16148		asm:    arm64.AREV,
16149		reg: regInfo{
16150			inputs: []inputInfo{
16151				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16152			},
16153			outputs: []outputInfo{
16154				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16155			},
16156		},
16157	},
16158	{
16159		name:   "REVW",
16160		argLen: 1,
16161		asm:    arm64.AREVW,
16162		reg: regInfo{
16163			inputs: []inputInfo{
16164				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16165			},
16166			outputs: []outputInfo{
16167				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16168			},
16169		},
16170	},
16171	{
16172		name:   "REV16W",
16173		argLen: 1,
16174		asm:    arm64.AREV16W,
16175		reg: regInfo{
16176			inputs: []inputInfo{
16177				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16178			},
16179			outputs: []outputInfo{
16180				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16181			},
16182		},
16183	},
16184	{
16185		name:   "RBIT",
16186		argLen: 1,
16187		asm:    arm64.ARBIT,
16188		reg: regInfo{
16189			inputs: []inputInfo{
16190				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16191			},
16192			outputs: []outputInfo{
16193				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16194			},
16195		},
16196	},
16197	{
16198		name:   "RBITW",
16199		argLen: 1,
16200		asm:    arm64.ARBITW,
16201		reg: regInfo{
16202			inputs: []inputInfo{
16203				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16204			},
16205			outputs: []outputInfo{
16206				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16207			},
16208		},
16209	},
16210	{
16211		name:   "CLZ",
16212		argLen: 1,
16213		asm:    arm64.ACLZ,
16214		reg: regInfo{
16215			inputs: []inputInfo{
16216				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16217			},
16218			outputs: []outputInfo{
16219				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16220			},
16221		},
16222	},
16223	{
16224		name:   "CLZW",
16225		argLen: 1,
16226		asm:    arm64.ACLZW,
16227		reg: regInfo{
16228			inputs: []inputInfo{
16229				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16230			},
16231			outputs: []outputInfo{
16232				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16233			},
16234		},
16235	},
16236	{
16237		name:   "VCNT",
16238		argLen: 1,
16239		asm:    arm64.AVCNT,
16240		reg: regInfo{
16241			inputs: []inputInfo{
16242				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16243			},
16244			outputs: []outputInfo{
16245				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16246			},
16247		},
16248	},
16249	{
16250		name:   "VUADDLV",
16251		argLen: 1,
16252		asm:    arm64.AVUADDLV,
16253		reg: regInfo{
16254			inputs: []inputInfo{
16255				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16256			},
16257			outputs: []outputInfo{
16258				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16259			},
16260		},
16261	},
16262	{
16263		name:         "LoweredRound32F",
16264		argLen:       1,
16265		resultInArg0: true,
16266		zeroWidth:    true,
16267		reg: regInfo{
16268			inputs: []inputInfo{
16269				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16270			},
16271			outputs: []outputInfo{
16272				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16273			},
16274		},
16275	},
16276	{
16277		name:         "LoweredRound64F",
16278		argLen:       1,
16279		resultInArg0: true,
16280		zeroWidth:    true,
16281		reg: regInfo{
16282			inputs: []inputInfo{
16283				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16284			},
16285			outputs: []outputInfo{
16286				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16287			},
16288		},
16289	},
16290	{
16291		name:   "FMADDS",
16292		argLen: 3,
16293		asm:    arm64.AFMADDS,
16294		reg: regInfo{
16295			inputs: []inputInfo{
16296				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16297				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16298				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16299			},
16300			outputs: []outputInfo{
16301				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16302			},
16303		},
16304	},
16305	{
16306		name:   "FMADDD",
16307		argLen: 3,
16308		asm:    arm64.AFMADDD,
16309		reg: regInfo{
16310			inputs: []inputInfo{
16311				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16312				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16313				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16314			},
16315			outputs: []outputInfo{
16316				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16317			},
16318		},
16319	},
16320	{
16321		name:   "FNMADDS",
16322		argLen: 3,
16323		asm:    arm64.AFNMADDS,
16324		reg: regInfo{
16325			inputs: []inputInfo{
16326				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16327				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16328				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16329			},
16330			outputs: []outputInfo{
16331				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16332			},
16333		},
16334	},
16335	{
16336		name:   "FNMADDD",
16337		argLen: 3,
16338		asm:    arm64.AFNMADDD,
16339		reg: regInfo{
16340			inputs: []inputInfo{
16341				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16342				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16343				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16344			},
16345			outputs: []outputInfo{
16346				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16347			},
16348		},
16349	},
16350	{
16351		name:   "FMSUBS",
16352		argLen: 3,
16353		asm:    arm64.AFMSUBS,
16354		reg: regInfo{
16355			inputs: []inputInfo{
16356				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16357				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16358				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16359			},
16360			outputs: []outputInfo{
16361				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16362			},
16363		},
16364	},
16365	{
16366		name:   "FMSUBD",
16367		argLen: 3,
16368		asm:    arm64.AFMSUBD,
16369		reg: regInfo{
16370			inputs: []inputInfo{
16371				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16372				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16373				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16374			},
16375			outputs: []outputInfo{
16376				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16377			},
16378		},
16379	},
16380	{
16381		name:   "FNMSUBS",
16382		argLen: 3,
16383		asm:    arm64.AFNMSUBS,
16384		reg: regInfo{
16385			inputs: []inputInfo{
16386				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16387				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16388				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16389			},
16390			outputs: []outputInfo{
16391				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16392			},
16393		},
16394	},
16395	{
16396		name:   "FNMSUBD",
16397		argLen: 3,
16398		asm:    arm64.AFNMSUBD,
16399		reg: regInfo{
16400			inputs: []inputInfo{
16401				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16402				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16403				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16404			},
16405			outputs: []outputInfo{
16406				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16407			},
16408		},
16409	},
16410	{
16411		name:   "MADD",
16412		argLen: 3,
16413		asm:    arm64.AMADD,
16414		reg: regInfo{
16415			inputs: []inputInfo{
16416				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16417				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16418				{2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16419			},
16420			outputs: []outputInfo{
16421				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16422			},
16423		},
16424	},
16425	{
16426		name:   "MADDW",
16427		argLen: 3,
16428		asm:    arm64.AMADDW,
16429		reg: regInfo{
16430			inputs: []inputInfo{
16431				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16432				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16433				{2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16434			},
16435			outputs: []outputInfo{
16436				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16437			},
16438		},
16439	},
16440	{
16441		name:   "MSUB",
16442		argLen: 3,
16443		asm:    arm64.AMSUB,
16444		reg: regInfo{
16445			inputs: []inputInfo{
16446				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16447				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16448				{2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16449			},
16450			outputs: []outputInfo{
16451				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16452			},
16453		},
16454	},
16455	{
16456		name:   "MSUBW",
16457		argLen: 3,
16458		asm:    arm64.AMSUBW,
16459		reg: regInfo{
16460			inputs: []inputInfo{
16461				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16462				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16463				{2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16464			},
16465			outputs: []outputInfo{
16466				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16467			},
16468		},
16469	},
16470	{
16471		name:   "SLL",
16472		argLen: 2,
16473		asm:    arm64.ALSL,
16474		reg: regInfo{
16475			inputs: []inputInfo{
16476				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16477				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16478			},
16479			outputs: []outputInfo{
16480				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16481			},
16482		},
16483	},
16484	{
16485		name:    "SLLconst",
16486		auxType: auxInt64,
16487		argLen:  1,
16488		asm:     arm64.ALSL,
16489		reg: regInfo{
16490			inputs: []inputInfo{
16491				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16492			},
16493			outputs: []outputInfo{
16494				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16495			},
16496		},
16497	},
16498	{
16499		name:   "SRL",
16500		argLen: 2,
16501		asm:    arm64.ALSR,
16502		reg: regInfo{
16503			inputs: []inputInfo{
16504				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16505				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16506			},
16507			outputs: []outputInfo{
16508				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16509			},
16510		},
16511	},
16512	{
16513		name:    "SRLconst",
16514		auxType: auxInt64,
16515		argLen:  1,
16516		asm:     arm64.ALSR,
16517		reg: regInfo{
16518			inputs: []inputInfo{
16519				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16520			},
16521			outputs: []outputInfo{
16522				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16523			},
16524		},
16525	},
16526	{
16527		name:   "SRA",
16528		argLen: 2,
16529		asm:    arm64.AASR,
16530		reg: regInfo{
16531			inputs: []inputInfo{
16532				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16533				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16534			},
16535			outputs: []outputInfo{
16536				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16537			},
16538		},
16539	},
16540	{
16541		name:    "SRAconst",
16542		auxType: auxInt64,
16543		argLen:  1,
16544		asm:     arm64.AASR,
16545		reg: regInfo{
16546			inputs: []inputInfo{
16547				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16548			},
16549			outputs: []outputInfo{
16550				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16551			},
16552		},
16553	},
16554	{
16555		name:   "ROR",
16556		argLen: 2,
16557		asm:    arm64.AROR,
16558		reg: regInfo{
16559			inputs: []inputInfo{
16560				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16561				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16562			},
16563			outputs: []outputInfo{
16564				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16565			},
16566		},
16567	},
16568	{
16569		name:   "RORW",
16570		argLen: 2,
16571		asm:    arm64.ARORW,
16572		reg: regInfo{
16573			inputs: []inputInfo{
16574				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16575				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16576			},
16577			outputs: []outputInfo{
16578				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16579			},
16580		},
16581	},
16582	{
16583		name:    "RORconst",
16584		auxType: auxInt64,
16585		argLen:  1,
16586		asm:     arm64.AROR,
16587		reg: regInfo{
16588			inputs: []inputInfo{
16589				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16590			},
16591			outputs: []outputInfo{
16592				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16593			},
16594		},
16595	},
16596	{
16597		name:    "RORWconst",
16598		auxType: auxInt64,
16599		argLen:  1,
16600		asm:     arm64.ARORW,
16601		reg: regInfo{
16602			inputs: []inputInfo{
16603				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16604			},
16605			outputs: []outputInfo{
16606				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16607			},
16608		},
16609	},
16610	{
16611		name:    "EXTRconst",
16612		auxType: auxInt64,
16613		argLen:  2,
16614		asm:     arm64.AEXTR,
16615		reg: regInfo{
16616			inputs: []inputInfo{
16617				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16618				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16619			},
16620			outputs: []outputInfo{
16621				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16622			},
16623		},
16624	},
16625	{
16626		name:    "EXTRWconst",
16627		auxType: auxInt64,
16628		argLen:  2,
16629		asm:     arm64.AEXTRW,
16630		reg: regInfo{
16631			inputs: []inputInfo{
16632				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16633				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16634			},
16635			outputs: []outputInfo{
16636				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16637			},
16638		},
16639	},
16640	{
16641		name:   "CMP",
16642		argLen: 2,
16643		asm:    arm64.ACMP,
16644		reg: regInfo{
16645			inputs: []inputInfo{
16646				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16647				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16648			},
16649		},
16650	},
16651	{
16652		name:    "CMPconst",
16653		auxType: auxInt64,
16654		argLen:  1,
16655		asm:     arm64.ACMP,
16656		reg: regInfo{
16657			inputs: []inputInfo{
16658				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16659			},
16660		},
16661	},
16662	{
16663		name:   "CMPW",
16664		argLen: 2,
16665		asm:    arm64.ACMPW,
16666		reg: regInfo{
16667			inputs: []inputInfo{
16668				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16669				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16670			},
16671		},
16672	},
16673	{
16674		name:    "CMPWconst",
16675		auxType: auxInt32,
16676		argLen:  1,
16677		asm:     arm64.ACMPW,
16678		reg: regInfo{
16679			inputs: []inputInfo{
16680				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16681			},
16682		},
16683	},
16684	{
16685		name:        "CMN",
16686		argLen:      2,
16687		commutative: true,
16688		asm:         arm64.ACMN,
16689		reg: regInfo{
16690			inputs: []inputInfo{
16691				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16692				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16693			},
16694		},
16695	},
16696	{
16697		name:    "CMNconst",
16698		auxType: auxInt64,
16699		argLen:  1,
16700		asm:     arm64.ACMN,
16701		reg: regInfo{
16702			inputs: []inputInfo{
16703				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16704			},
16705		},
16706	},
16707	{
16708		name:        "CMNW",
16709		argLen:      2,
16710		commutative: true,
16711		asm:         arm64.ACMNW,
16712		reg: regInfo{
16713			inputs: []inputInfo{
16714				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16715				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16716			},
16717		},
16718	},
16719	{
16720		name:    "CMNWconst",
16721		auxType: auxInt32,
16722		argLen:  1,
16723		asm:     arm64.ACMNW,
16724		reg: regInfo{
16725			inputs: []inputInfo{
16726				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16727			},
16728		},
16729	},
16730	{
16731		name:        "TST",
16732		argLen:      2,
16733		commutative: true,
16734		asm:         arm64.ATST,
16735		reg: regInfo{
16736			inputs: []inputInfo{
16737				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16738				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16739			},
16740		},
16741	},
16742	{
16743		name:    "TSTconst",
16744		auxType: auxInt64,
16745		argLen:  1,
16746		asm:     arm64.ATST,
16747		reg: regInfo{
16748			inputs: []inputInfo{
16749				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16750			},
16751		},
16752	},
16753	{
16754		name:        "TSTW",
16755		argLen:      2,
16756		commutative: true,
16757		asm:         arm64.ATSTW,
16758		reg: regInfo{
16759			inputs: []inputInfo{
16760				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16761				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16762			},
16763		},
16764	},
16765	{
16766		name:    "TSTWconst",
16767		auxType: auxInt32,
16768		argLen:  1,
16769		asm:     arm64.ATSTW,
16770		reg: regInfo{
16771			inputs: []inputInfo{
16772				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16773			},
16774		},
16775	},
16776	{
16777		name:   "FCMPS",
16778		argLen: 2,
16779		asm:    arm64.AFCMPS,
16780		reg: regInfo{
16781			inputs: []inputInfo{
16782				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16783				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16784			},
16785		},
16786	},
16787	{
16788		name:   "FCMPD",
16789		argLen: 2,
16790		asm:    arm64.AFCMPD,
16791		reg: regInfo{
16792			inputs: []inputInfo{
16793				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16794				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16795			},
16796		},
16797	},
16798	{
16799		name:   "FCMPS0",
16800		argLen: 1,
16801		asm:    arm64.AFCMPS,
16802		reg: regInfo{
16803			inputs: []inputInfo{
16804				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16805			},
16806		},
16807	},
16808	{
16809		name:   "FCMPD0",
16810		argLen: 1,
16811		asm:    arm64.AFCMPD,
16812		reg: regInfo{
16813			inputs: []inputInfo{
16814				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
16815			},
16816		},
16817	},
16818	{
16819		name:    "MVNshiftLL",
16820		auxType: auxInt64,
16821		argLen:  1,
16822		asm:     arm64.AMVN,
16823		reg: regInfo{
16824			inputs: []inputInfo{
16825				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16826			},
16827			outputs: []outputInfo{
16828				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16829			},
16830		},
16831	},
16832	{
16833		name:    "MVNshiftRL",
16834		auxType: auxInt64,
16835		argLen:  1,
16836		asm:     arm64.AMVN,
16837		reg: regInfo{
16838			inputs: []inputInfo{
16839				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16840			},
16841			outputs: []outputInfo{
16842				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16843			},
16844		},
16845	},
16846	{
16847		name:    "MVNshiftRA",
16848		auxType: auxInt64,
16849		argLen:  1,
16850		asm:     arm64.AMVN,
16851		reg: regInfo{
16852			inputs: []inputInfo{
16853				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16854			},
16855			outputs: []outputInfo{
16856				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16857			},
16858		},
16859	},
16860	{
16861		name:    "NEGshiftLL",
16862		auxType: auxInt64,
16863		argLen:  1,
16864		asm:     arm64.ANEG,
16865		reg: regInfo{
16866			inputs: []inputInfo{
16867				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16868			},
16869			outputs: []outputInfo{
16870				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16871			},
16872		},
16873	},
16874	{
16875		name:    "NEGshiftRL",
16876		auxType: auxInt64,
16877		argLen:  1,
16878		asm:     arm64.ANEG,
16879		reg: regInfo{
16880			inputs: []inputInfo{
16881				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16882			},
16883			outputs: []outputInfo{
16884				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16885			},
16886		},
16887	},
16888	{
16889		name:    "NEGshiftRA",
16890		auxType: auxInt64,
16891		argLen:  1,
16892		asm:     arm64.ANEG,
16893		reg: regInfo{
16894			inputs: []inputInfo{
16895				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16896			},
16897			outputs: []outputInfo{
16898				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16899			},
16900		},
16901	},
16902	{
16903		name:    "ADDshiftLL",
16904		auxType: auxInt64,
16905		argLen:  2,
16906		asm:     arm64.AADD,
16907		reg: regInfo{
16908			inputs: []inputInfo{
16909				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16910				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16911			},
16912			outputs: []outputInfo{
16913				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16914			},
16915		},
16916	},
16917	{
16918		name:    "ADDshiftRL",
16919		auxType: auxInt64,
16920		argLen:  2,
16921		asm:     arm64.AADD,
16922		reg: regInfo{
16923			inputs: []inputInfo{
16924				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16925				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16926			},
16927			outputs: []outputInfo{
16928				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16929			},
16930		},
16931	},
16932	{
16933		name:    "ADDshiftRA",
16934		auxType: auxInt64,
16935		argLen:  2,
16936		asm:     arm64.AADD,
16937		reg: regInfo{
16938			inputs: []inputInfo{
16939				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16940				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16941			},
16942			outputs: []outputInfo{
16943				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16944			},
16945		},
16946	},
16947	{
16948		name:    "SUBshiftLL",
16949		auxType: auxInt64,
16950		argLen:  2,
16951		asm:     arm64.ASUB,
16952		reg: regInfo{
16953			inputs: []inputInfo{
16954				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16955				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16956			},
16957			outputs: []outputInfo{
16958				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16959			},
16960		},
16961	},
16962	{
16963		name:    "SUBshiftRL",
16964		auxType: auxInt64,
16965		argLen:  2,
16966		asm:     arm64.ASUB,
16967		reg: regInfo{
16968			inputs: []inputInfo{
16969				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16970				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16971			},
16972			outputs: []outputInfo{
16973				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16974			},
16975		},
16976	},
16977	{
16978		name:    "SUBshiftRA",
16979		auxType: auxInt64,
16980		argLen:  2,
16981		asm:     arm64.ASUB,
16982		reg: regInfo{
16983			inputs: []inputInfo{
16984				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16985				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
16986			},
16987			outputs: []outputInfo{
16988				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
16989			},
16990		},
16991	},
16992	{
16993		name:    "ANDshiftLL",
16994		auxType: auxInt64,
16995		argLen:  2,
16996		asm:     arm64.AAND,
16997		reg: regInfo{
16998			inputs: []inputInfo{
16999				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17000				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17001			},
17002			outputs: []outputInfo{
17003				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17004			},
17005		},
17006	},
17007	{
17008		name:    "ANDshiftRL",
17009		auxType: auxInt64,
17010		argLen:  2,
17011		asm:     arm64.AAND,
17012		reg: regInfo{
17013			inputs: []inputInfo{
17014				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17015				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17016			},
17017			outputs: []outputInfo{
17018				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17019			},
17020		},
17021	},
17022	{
17023		name:    "ANDshiftRA",
17024		auxType: auxInt64,
17025		argLen:  2,
17026		asm:     arm64.AAND,
17027		reg: regInfo{
17028			inputs: []inputInfo{
17029				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17030				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17031			},
17032			outputs: []outputInfo{
17033				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17034			},
17035		},
17036	},
17037	{
17038		name:    "ORshiftLL",
17039		auxType: auxInt64,
17040		argLen:  2,
17041		asm:     arm64.AORR,
17042		reg: regInfo{
17043			inputs: []inputInfo{
17044				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17045				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17046			},
17047			outputs: []outputInfo{
17048				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17049			},
17050		},
17051	},
17052	{
17053		name:    "ORshiftRL",
17054		auxType: auxInt64,
17055		argLen:  2,
17056		asm:     arm64.AORR,
17057		reg: regInfo{
17058			inputs: []inputInfo{
17059				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17060				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17061			},
17062			outputs: []outputInfo{
17063				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17064			},
17065		},
17066	},
17067	{
17068		name:    "ORshiftRA",
17069		auxType: auxInt64,
17070		argLen:  2,
17071		asm:     arm64.AORR,
17072		reg: regInfo{
17073			inputs: []inputInfo{
17074				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17075				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17076			},
17077			outputs: []outputInfo{
17078				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17079			},
17080		},
17081	},
17082	{
17083		name:    "XORshiftLL",
17084		auxType: auxInt64,
17085		argLen:  2,
17086		asm:     arm64.AEOR,
17087		reg: regInfo{
17088			inputs: []inputInfo{
17089				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17090				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17091			},
17092			outputs: []outputInfo{
17093				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17094			},
17095		},
17096	},
17097	{
17098		name:    "XORshiftRL",
17099		auxType: auxInt64,
17100		argLen:  2,
17101		asm:     arm64.AEOR,
17102		reg: regInfo{
17103			inputs: []inputInfo{
17104				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17105				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17106			},
17107			outputs: []outputInfo{
17108				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17109			},
17110		},
17111	},
17112	{
17113		name:    "XORshiftRA",
17114		auxType: auxInt64,
17115		argLen:  2,
17116		asm:     arm64.AEOR,
17117		reg: regInfo{
17118			inputs: []inputInfo{
17119				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17120				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17121			},
17122			outputs: []outputInfo{
17123				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17124			},
17125		},
17126	},
17127	{
17128		name:    "BICshiftLL",
17129		auxType: auxInt64,
17130		argLen:  2,
17131		asm:     arm64.ABIC,
17132		reg: regInfo{
17133			inputs: []inputInfo{
17134				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17135				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17136			},
17137			outputs: []outputInfo{
17138				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17139			},
17140		},
17141	},
17142	{
17143		name:    "BICshiftRL",
17144		auxType: auxInt64,
17145		argLen:  2,
17146		asm:     arm64.ABIC,
17147		reg: regInfo{
17148			inputs: []inputInfo{
17149				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17150				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17151			},
17152			outputs: []outputInfo{
17153				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17154			},
17155		},
17156	},
17157	{
17158		name:    "BICshiftRA",
17159		auxType: auxInt64,
17160		argLen:  2,
17161		asm:     arm64.ABIC,
17162		reg: regInfo{
17163			inputs: []inputInfo{
17164				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17165				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17166			},
17167			outputs: []outputInfo{
17168				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17169			},
17170		},
17171	},
17172	{
17173		name:    "EONshiftLL",
17174		auxType: auxInt64,
17175		argLen:  2,
17176		asm:     arm64.AEON,
17177		reg: regInfo{
17178			inputs: []inputInfo{
17179				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17180				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17181			},
17182			outputs: []outputInfo{
17183				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17184			},
17185		},
17186	},
17187	{
17188		name:    "EONshiftRL",
17189		auxType: auxInt64,
17190		argLen:  2,
17191		asm:     arm64.AEON,
17192		reg: regInfo{
17193			inputs: []inputInfo{
17194				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17195				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17196			},
17197			outputs: []outputInfo{
17198				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17199			},
17200		},
17201	},
17202	{
17203		name:    "EONshiftRA",
17204		auxType: auxInt64,
17205		argLen:  2,
17206		asm:     arm64.AEON,
17207		reg: regInfo{
17208			inputs: []inputInfo{
17209				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17210				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17211			},
17212			outputs: []outputInfo{
17213				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17214			},
17215		},
17216	},
17217	{
17218		name:    "ORNshiftLL",
17219		auxType: auxInt64,
17220		argLen:  2,
17221		asm:     arm64.AORN,
17222		reg: regInfo{
17223			inputs: []inputInfo{
17224				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17225				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17226			},
17227			outputs: []outputInfo{
17228				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17229			},
17230		},
17231	},
17232	{
17233		name:    "ORNshiftRL",
17234		auxType: auxInt64,
17235		argLen:  2,
17236		asm:     arm64.AORN,
17237		reg: regInfo{
17238			inputs: []inputInfo{
17239				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17240				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17241			},
17242			outputs: []outputInfo{
17243				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17244			},
17245		},
17246	},
17247	{
17248		name:    "ORNshiftRA",
17249		auxType: auxInt64,
17250		argLen:  2,
17251		asm:     arm64.AORN,
17252		reg: regInfo{
17253			inputs: []inputInfo{
17254				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17255				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17256			},
17257			outputs: []outputInfo{
17258				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17259			},
17260		},
17261	},
17262	{
17263		name:    "CMPshiftLL",
17264		auxType: auxInt64,
17265		argLen:  2,
17266		asm:     arm64.ACMP,
17267		reg: regInfo{
17268			inputs: []inputInfo{
17269				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17270				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17271			},
17272		},
17273	},
17274	{
17275		name:    "CMPshiftRL",
17276		auxType: auxInt64,
17277		argLen:  2,
17278		asm:     arm64.ACMP,
17279		reg: regInfo{
17280			inputs: []inputInfo{
17281				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17282				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17283			},
17284		},
17285	},
17286	{
17287		name:    "CMPshiftRA",
17288		auxType: auxInt64,
17289		argLen:  2,
17290		asm:     arm64.ACMP,
17291		reg: regInfo{
17292			inputs: []inputInfo{
17293				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17294				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17295			},
17296		},
17297	},
17298	{
17299		name:    "CMNshiftLL",
17300		auxType: auxInt64,
17301		argLen:  2,
17302		asm:     arm64.ACMN,
17303		reg: regInfo{
17304			inputs: []inputInfo{
17305				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17306				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17307			},
17308		},
17309	},
17310	{
17311		name:    "CMNshiftRL",
17312		auxType: auxInt64,
17313		argLen:  2,
17314		asm:     arm64.ACMN,
17315		reg: regInfo{
17316			inputs: []inputInfo{
17317				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17318				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17319			},
17320		},
17321	},
17322	{
17323		name:    "CMNshiftRA",
17324		auxType: auxInt64,
17325		argLen:  2,
17326		asm:     arm64.ACMN,
17327		reg: regInfo{
17328			inputs: []inputInfo{
17329				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17330				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17331			},
17332		},
17333	},
17334	{
17335		name:    "TSTshiftLL",
17336		auxType: auxInt64,
17337		argLen:  2,
17338		asm:     arm64.ATST,
17339		reg: regInfo{
17340			inputs: []inputInfo{
17341				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17342				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17343			},
17344		},
17345	},
17346	{
17347		name:    "TSTshiftRL",
17348		auxType: auxInt64,
17349		argLen:  2,
17350		asm:     arm64.ATST,
17351		reg: regInfo{
17352			inputs: []inputInfo{
17353				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17354				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17355			},
17356		},
17357	},
17358	{
17359		name:    "TSTshiftRA",
17360		auxType: auxInt64,
17361		argLen:  2,
17362		asm:     arm64.ATST,
17363		reg: regInfo{
17364			inputs: []inputInfo{
17365				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17366				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17367			},
17368		},
17369	},
17370	{
17371		name:         "BFI",
17372		auxType:      auxInt64,
17373		argLen:       2,
17374		resultInArg0: true,
17375		asm:          arm64.ABFI,
17376		reg: regInfo{
17377			inputs: []inputInfo{
17378				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17379				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17380			},
17381			outputs: []outputInfo{
17382				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17383			},
17384		},
17385	},
17386	{
17387		name:         "BFXIL",
17388		auxType:      auxInt64,
17389		argLen:       2,
17390		resultInArg0: true,
17391		asm:          arm64.ABFXIL,
17392		reg: regInfo{
17393			inputs: []inputInfo{
17394				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17395				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17396			},
17397			outputs: []outputInfo{
17398				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17399			},
17400		},
17401	},
17402	{
17403		name:    "SBFIZ",
17404		auxType: auxInt64,
17405		argLen:  1,
17406		asm:     arm64.ASBFIZ,
17407		reg: regInfo{
17408			inputs: []inputInfo{
17409				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17410			},
17411			outputs: []outputInfo{
17412				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17413			},
17414		},
17415	},
17416	{
17417		name:    "SBFX",
17418		auxType: auxInt64,
17419		argLen:  1,
17420		asm:     arm64.ASBFX,
17421		reg: regInfo{
17422			inputs: []inputInfo{
17423				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17424			},
17425			outputs: []outputInfo{
17426				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17427			},
17428		},
17429	},
17430	{
17431		name:    "UBFIZ",
17432		auxType: auxInt64,
17433		argLen:  1,
17434		asm:     arm64.AUBFIZ,
17435		reg: regInfo{
17436			inputs: []inputInfo{
17437				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17438			},
17439			outputs: []outputInfo{
17440				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17441			},
17442		},
17443	},
17444	{
17445		name:    "UBFX",
17446		auxType: auxInt64,
17447		argLen:  1,
17448		asm:     arm64.AUBFX,
17449		reg: regInfo{
17450			inputs: []inputInfo{
17451				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17452			},
17453			outputs: []outputInfo{
17454				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17455			},
17456		},
17457	},
17458	{
17459		name:              "MOVDconst",
17460		auxType:           auxInt64,
17461		argLen:            0,
17462		rematerializeable: true,
17463		asm:               arm64.AMOVD,
17464		reg: regInfo{
17465			outputs: []outputInfo{
17466				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17467			},
17468		},
17469	},
17470	{
17471		name:              "FMOVSconst",
17472		auxType:           auxFloat64,
17473		argLen:            0,
17474		rematerializeable: true,
17475		asm:               arm64.AFMOVS,
17476		reg: regInfo{
17477			outputs: []outputInfo{
17478				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17479			},
17480		},
17481	},
17482	{
17483		name:              "FMOVDconst",
17484		auxType:           auxFloat64,
17485		argLen:            0,
17486		rematerializeable: true,
17487		asm:               arm64.AFMOVD,
17488		reg: regInfo{
17489			outputs: []outputInfo{
17490				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17491			},
17492		},
17493	},
17494	{
17495		name:              "MOVDaddr",
17496		auxType:           auxSymOff,
17497		argLen:            1,
17498		rematerializeable: true,
17499		symEffect:         SymAddr,
17500		asm:               arm64.AMOVD,
17501		reg: regInfo{
17502			inputs: []inputInfo{
17503				{0, 9223372037928517632}, // SP SB
17504			},
17505			outputs: []outputInfo{
17506				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17507			},
17508		},
17509	},
17510	{
17511		name:           "MOVBload",
17512		auxType:        auxSymOff,
17513		argLen:         2,
17514		faultOnNilArg0: true,
17515		symEffect:      SymRead,
17516		asm:            arm64.AMOVB,
17517		reg: regInfo{
17518			inputs: []inputInfo{
17519				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17520			},
17521			outputs: []outputInfo{
17522				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17523			},
17524		},
17525	},
17526	{
17527		name:           "MOVBUload",
17528		auxType:        auxSymOff,
17529		argLen:         2,
17530		faultOnNilArg0: true,
17531		symEffect:      SymRead,
17532		asm:            arm64.AMOVBU,
17533		reg: regInfo{
17534			inputs: []inputInfo{
17535				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17536			},
17537			outputs: []outputInfo{
17538				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17539			},
17540		},
17541	},
17542	{
17543		name:           "MOVHload",
17544		auxType:        auxSymOff,
17545		argLen:         2,
17546		faultOnNilArg0: true,
17547		symEffect:      SymRead,
17548		asm:            arm64.AMOVH,
17549		reg: regInfo{
17550			inputs: []inputInfo{
17551				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17552			},
17553			outputs: []outputInfo{
17554				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17555			},
17556		},
17557	},
17558	{
17559		name:           "MOVHUload",
17560		auxType:        auxSymOff,
17561		argLen:         2,
17562		faultOnNilArg0: true,
17563		symEffect:      SymRead,
17564		asm:            arm64.AMOVHU,
17565		reg: regInfo{
17566			inputs: []inputInfo{
17567				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17568			},
17569			outputs: []outputInfo{
17570				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17571			},
17572		},
17573	},
17574	{
17575		name:           "MOVWload",
17576		auxType:        auxSymOff,
17577		argLen:         2,
17578		faultOnNilArg0: true,
17579		symEffect:      SymRead,
17580		asm:            arm64.AMOVW,
17581		reg: regInfo{
17582			inputs: []inputInfo{
17583				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17584			},
17585			outputs: []outputInfo{
17586				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17587			},
17588		},
17589	},
17590	{
17591		name:           "MOVWUload",
17592		auxType:        auxSymOff,
17593		argLen:         2,
17594		faultOnNilArg0: true,
17595		symEffect:      SymRead,
17596		asm:            arm64.AMOVWU,
17597		reg: regInfo{
17598			inputs: []inputInfo{
17599				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17600			},
17601			outputs: []outputInfo{
17602				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17603			},
17604		},
17605	},
17606	{
17607		name:           "MOVDload",
17608		auxType:        auxSymOff,
17609		argLen:         2,
17610		faultOnNilArg0: true,
17611		symEffect:      SymRead,
17612		asm:            arm64.AMOVD,
17613		reg: regInfo{
17614			inputs: []inputInfo{
17615				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17616			},
17617			outputs: []outputInfo{
17618				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17619			},
17620		},
17621	},
17622	{
17623		name:           "FMOVSload",
17624		auxType:        auxSymOff,
17625		argLen:         2,
17626		faultOnNilArg0: true,
17627		symEffect:      SymRead,
17628		asm:            arm64.AFMOVS,
17629		reg: regInfo{
17630			inputs: []inputInfo{
17631				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17632			},
17633			outputs: []outputInfo{
17634				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17635			},
17636		},
17637	},
17638	{
17639		name:           "FMOVDload",
17640		auxType:        auxSymOff,
17641		argLen:         2,
17642		faultOnNilArg0: true,
17643		symEffect:      SymRead,
17644		asm:            arm64.AFMOVD,
17645		reg: regInfo{
17646			inputs: []inputInfo{
17647				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17648			},
17649			outputs: []outputInfo{
17650				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17651			},
17652		},
17653	},
17654	{
17655		name:   "MOVDloadidx",
17656		argLen: 3,
17657		asm:    arm64.AMOVD,
17658		reg: regInfo{
17659			inputs: []inputInfo{
17660				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17661				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17662			},
17663			outputs: []outputInfo{
17664				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17665			},
17666		},
17667	},
17668	{
17669		name:   "MOVWloadidx",
17670		argLen: 3,
17671		asm:    arm64.AMOVW,
17672		reg: regInfo{
17673			inputs: []inputInfo{
17674				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17675				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17676			},
17677			outputs: []outputInfo{
17678				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17679			},
17680		},
17681	},
17682	{
17683		name:   "MOVWUloadidx",
17684		argLen: 3,
17685		asm:    arm64.AMOVWU,
17686		reg: regInfo{
17687			inputs: []inputInfo{
17688				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17689				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17690			},
17691			outputs: []outputInfo{
17692				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17693			},
17694		},
17695	},
17696	{
17697		name:   "MOVHloadidx",
17698		argLen: 3,
17699		asm:    arm64.AMOVH,
17700		reg: regInfo{
17701			inputs: []inputInfo{
17702				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17703				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17704			},
17705			outputs: []outputInfo{
17706				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17707			},
17708		},
17709	},
17710	{
17711		name:   "MOVHUloadidx",
17712		argLen: 3,
17713		asm:    arm64.AMOVHU,
17714		reg: regInfo{
17715			inputs: []inputInfo{
17716				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17717				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17718			},
17719			outputs: []outputInfo{
17720				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17721			},
17722		},
17723	},
17724	{
17725		name:   "MOVBloadidx",
17726		argLen: 3,
17727		asm:    arm64.AMOVB,
17728		reg: regInfo{
17729			inputs: []inputInfo{
17730				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17731				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17732			},
17733			outputs: []outputInfo{
17734				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17735			},
17736		},
17737	},
17738	{
17739		name:   "MOVBUloadidx",
17740		argLen: 3,
17741		asm:    arm64.AMOVBU,
17742		reg: regInfo{
17743			inputs: []inputInfo{
17744				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17745				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17746			},
17747			outputs: []outputInfo{
17748				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17749			},
17750		},
17751	},
17752	{
17753		name:   "FMOVSloadidx",
17754		argLen: 3,
17755		asm:    arm64.AFMOVS,
17756		reg: regInfo{
17757			inputs: []inputInfo{
17758				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17759				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17760			},
17761			outputs: []outputInfo{
17762				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17763			},
17764		},
17765	},
17766	{
17767		name:   "FMOVDloadidx",
17768		argLen: 3,
17769		asm:    arm64.AFMOVD,
17770		reg: regInfo{
17771			inputs: []inputInfo{
17772				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17773				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17774			},
17775			outputs: []outputInfo{
17776				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17777			},
17778		},
17779	},
17780	{
17781		name:   "MOVHloadidx2",
17782		argLen: 3,
17783		asm:    arm64.AMOVH,
17784		reg: regInfo{
17785			inputs: []inputInfo{
17786				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17787				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17788			},
17789			outputs: []outputInfo{
17790				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17791			},
17792		},
17793	},
17794	{
17795		name:   "MOVHUloadidx2",
17796		argLen: 3,
17797		asm:    arm64.AMOVHU,
17798		reg: regInfo{
17799			inputs: []inputInfo{
17800				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17801				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17802			},
17803			outputs: []outputInfo{
17804				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17805			},
17806		},
17807	},
17808	{
17809		name:   "MOVWloadidx4",
17810		argLen: 3,
17811		asm:    arm64.AMOVW,
17812		reg: regInfo{
17813			inputs: []inputInfo{
17814				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17815				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17816			},
17817			outputs: []outputInfo{
17818				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17819			},
17820		},
17821	},
17822	{
17823		name:   "MOVWUloadidx4",
17824		argLen: 3,
17825		asm:    arm64.AMOVWU,
17826		reg: regInfo{
17827			inputs: []inputInfo{
17828				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17829				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17830			},
17831			outputs: []outputInfo{
17832				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17833			},
17834		},
17835	},
17836	{
17837		name:   "MOVDloadidx8",
17838		argLen: 3,
17839		asm:    arm64.AMOVD,
17840		reg: regInfo{
17841			inputs: []inputInfo{
17842				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17843				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17844			},
17845			outputs: []outputInfo{
17846				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17847			},
17848		},
17849	},
17850	{
17851		name:           "MOVBstore",
17852		auxType:        auxSymOff,
17853		argLen:         3,
17854		faultOnNilArg0: true,
17855		symEffect:      SymWrite,
17856		asm:            arm64.AMOVB,
17857		reg: regInfo{
17858			inputs: []inputInfo{
17859				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17860				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17861			},
17862		},
17863	},
17864	{
17865		name:           "MOVHstore",
17866		auxType:        auxSymOff,
17867		argLen:         3,
17868		faultOnNilArg0: true,
17869		symEffect:      SymWrite,
17870		asm:            arm64.AMOVH,
17871		reg: regInfo{
17872			inputs: []inputInfo{
17873				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17874				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17875			},
17876		},
17877	},
17878	{
17879		name:           "MOVWstore",
17880		auxType:        auxSymOff,
17881		argLen:         3,
17882		faultOnNilArg0: true,
17883		symEffect:      SymWrite,
17884		asm:            arm64.AMOVW,
17885		reg: regInfo{
17886			inputs: []inputInfo{
17887				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17888				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17889			},
17890		},
17891	},
17892	{
17893		name:           "MOVDstore",
17894		auxType:        auxSymOff,
17895		argLen:         3,
17896		faultOnNilArg0: true,
17897		symEffect:      SymWrite,
17898		asm:            arm64.AMOVD,
17899		reg: regInfo{
17900			inputs: []inputInfo{
17901				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17902				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17903			},
17904		},
17905	},
17906	{
17907		name:           "STP",
17908		auxType:        auxSymOff,
17909		argLen:         4,
17910		faultOnNilArg0: true,
17911		symEffect:      SymWrite,
17912		asm:            arm64.ASTP,
17913		reg: regInfo{
17914			inputs: []inputInfo{
17915				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17916				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17917				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17918			},
17919		},
17920	},
17921	{
17922		name:           "FMOVSstore",
17923		auxType:        auxSymOff,
17924		argLen:         3,
17925		faultOnNilArg0: true,
17926		symEffect:      SymWrite,
17927		asm:            arm64.AFMOVS,
17928		reg: regInfo{
17929			inputs: []inputInfo{
17930				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17931				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17932			},
17933		},
17934	},
17935	{
17936		name:           "FMOVDstore",
17937		auxType:        auxSymOff,
17938		argLen:         3,
17939		faultOnNilArg0: true,
17940		symEffect:      SymWrite,
17941		asm:            arm64.AFMOVD,
17942		reg: regInfo{
17943			inputs: []inputInfo{
17944				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17945				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17946			},
17947		},
17948	},
17949	{
17950		name:   "MOVBstoreidx",
17951		argLen: 4,
17952		asm:    arm64.AMOVB,
17953		reg: regInfo{
17954			inputs: []inputInfo{
17955				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17956				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17957				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17958			},
17959		},
17960	},
17961	{
17962		name:   "MOVHstoreidx",
17963		argLen: 4,
17964		asm:    arm64.AMOVH,
17965		reg: regInfo{
17966			inputs: []inputInfo{
17967				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17968				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17969				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17970			},
17971		},
17972	},
17973	{
17974		name:   "MOVWstoreidx",
17975		argLen: 4,
17976		asm:    arm64.AMOVW,
17977		reg: regInfo{
17978			inputs: []inputInfo{
17979				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17980				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17981				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17982			},
17983		},
17984	},
17985	{
17986		name:   "MOVDstoreidx",
17987		argLen: 4,
17988		asm:    arm64.AMOVD,
17989		reg: regInfo{
17990			inputs: []inputInfo{
17991				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17992				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17993				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
17994			},
17995		},
17996	},
17997	{
17998		name:   "FMOVSstoreidx",
17999		argLen: 4,
18000		asm:    arm64.AFMOVS,
18001		reg: regInfo{
18002			inputs: []inputInfo{
18003				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18004				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18005				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18006			},
18007		},
18008	},
18009	{
18010		name:   "FMOVDstoreidx",
18011		argLen: 4,
18012		asm:    arm64.AFMOVD,
18013		reg: regInfo{
18014			inputs: []inputInfo{
18015				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18016				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18017				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18018			},
18019		},
18020	},
18021	{
18022		name:   "MOVHstoreidx2",
18023		argLen: 4,
18024		asm:    arm64.AMOVH,
18025		reg: regInfo{
18026			inputs: []inputInfo{
18027				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18028				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18029				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18030			},
18031		},
18032	},
18033	{
18034		name:   "MOVWstoreidx4",
18035		argLen: 4,
18036		asm:    arm64.AMOVW,
18037		reg: regInfo{
18038			inputs: []inputInfo{
18039				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18040				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18041				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18042			},
18043		},
18044	},
18045	{
18046		name:   "MOVDstoreidx8",
18047		argLen: 4,
18048		asm:    arm64.AMOVD,
18049		reg: regInfo{
18050			inputs: []inputInfo{
18051				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18052				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18053				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18054			},
18055		},
18056	},
18057	{
18058		name:           "MOVBstorezero",
18059		auxType:        auxSymOff,
18060		argLen:         2,
18061		faultOnNilArg0: true,
18062		symEffect:      SymWrite,
18063		asm:            arm64.AMOVB,
18064		reg: regInfo{
18065			inputs: []inputInfo{
18066				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18067			},
18068		},
18069	},
18070	{
18071		name:           "MOVHstorezero",
18072		auxType:        auxSymOff,
18073		argLen:         2,
18074		faultOnNilArg0: true,
18075		symEffect:      SymWrite,
18076		asm:            arm64.AMOVH,
18077		reg: regInfo{
18078			inputs: []inputInfo{
18079				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18080			},
18081		},
18082	},
18083	{
18084		name:           "MOVWstorezero",
18085		auxType:        auxSymOff,
18086		argLen:         2,
18087		faultOnNilArg0: true,
18088		symEffect:      SymWrite,
18089		asm:            arm64.AMOVW,
18090		reg: regInfo{
18091			inputs: []inputInfo{
18092				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18093			},
18094		},
18095	},
18096	{
18097		name:           "MOVDstorezero",
18098		auxType:        auxSymOff,
18099		argLen:         2,
18100		faultOnNilArg0: true,
18101		symEffect:      SymWrite,
18102		asm:            arm64.AMOVD,
18103		reg: regInfo{
18104			inputs: []inputInfo{
18105				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18106			},
18107		},
18108	},
18109	{
18110		name:           "MOVQstorezero",
18111		auxType:        auxSymOff,
18112		argLen:         2,
18113		faultOnNilArg0: true,
18114		symEffect:      SymWrite,
18115		asm:            arm64.ASTP,
18116		reg: regInfo{
18117			inputs: []inputInfo{
18118				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18119			},
18120		},
18121	},
18122	{
18123		name:   "MOVBstorezeroidx",
18124		argLen: 3,
18125		asm:    arm64.AMOVB,
18126		reg: regInfo{
18127			inputs: []inputInfo{
18128				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18129				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18130			},
18131		},
18132	},
18133	{
18134		name:   "MOVHstorezeroidx",
18135		argLen: 3,
18136		asm:    arm64.AMOVH,
18137		reg: regInfo{
18138			inputs: []inputInfo{
18139				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18140				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18141			},
18142		},
18143	},
18144	{
18145		name:   "MOVWstorezeroidx",
18146		argLen: 3,
18147		asm:    arm64.AMOVW,
18148		reg: regInfo{
18149			inputs: []inputInfo{
18150				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18151				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18152			},
18153		},
18154	},
18155	{
18156		name:   "MOVDstorezeroidx",
18157		argLen: 3,
18158		asm:    arm64.AMOVD,
18159		reg: regInfo{
18160			inputs: []inputInfo{
18161				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18162				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18163			},
18164		},
18165	},
18166	{
18167		name:   "MOVHstorezeroidx2",
18168		argLen: 3,
18169		asm:    arm64.AMOVH,
18170		reg: regInfo{
18171			inputs: []inputInfo{
18172				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18173				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18174			},
18175		},
18176	},
18177	{
18178		name:   "MOVWstorezeroidx4",
18179		argLen: 3,
18180		asm:    arm64.AMOVW,
18181		reg: regInfo{
18182			inputs: []inputInfo{
18183				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18184				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18185			},
18186		},
18187	},
18188	{
18189		name:   "MOVDstorezeroidx8",
18190		argLen: 3,
18191		asm:    arm64.AMOVD,
18192		reg: regInfo{
18193			inputs: []inputInfo{
18194				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18195				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18196			},
18197		},
18198	},
18199	{
18200		name:   "FMOVDgpfp",
18201		argLen: 1,
18202		asm:    arm64.AFMOVD,
18203		reg: regInfo{
18204			inputs: []inputInfo{
18205				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18206			},
18207			outputs: []outputInfo{
18208				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18209			},
18210		},
18211	},
18212	{
18213		name:   "FMOVDfpgp",
18214		argLen: 1,
18215		asm:    arm64.AFMOVD,
18216		reg: regInfo{
18217			inputs: []inputInfo{
18218				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18219			},
18220			outputs: []outputInfo{
18221				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18222			},
18223		},
18224	},
18225	{
18226		name:   "FMOVSgpfp",
18227		argLen: 1,
18228		asm:    arm64.AFMOVS,
18229		reg: regInfo{
18230			inputs: []inputInfo{
18231				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18232			},
18233			outputs: []outputInfo{
18234				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18235			},
18236		},
18237	},
18238	{
18239		name:   "FMOVSfpgp",
18240		argLen: 1,
18241		asm:    arm64.AFMOVS,
18242		reg: regInfo{
18243			inputs: []inputInfo{
18244				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18245			},
18246			outputs: []outputInfo{
18247				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18248			},
18249		},
18250	},
18251	{
18252		name:   "MOVBreg",
18253		argLen: 1,
18254		asm:    arm64.AMOVB,
18255		reg: regInfo{
18256			inputs: []inputInfo{
18257				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18258			},
18259			outputs: []outputInfo{
18260				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18261			},
18262		},
18263	},
18264	{
18265		name:   "MOVBUreg",
18266		argLen: 1,
18267		asm:    arm64.AMOVBU,
18268		reg: regInfo{
18269			inputs: []inputInfo{
18270				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18271			},
18272			outputs: []outputInfo{
18273				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18274			},
18275		},
18276	},
18277	{
18278		name:   "MOVHreg",
18279		argLen: 1,
18280		asm:    arm64.AMOVH,
18281		reg: regInfo{
18282			inputs: []inputInfo{
18283				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18284			},
18285			outputs: []outputInfo{
18286				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18287			},
18288		},
18289	},
18290	{
18291		name:   "MOVHUreg",
18292		argLen: 1,
18293		asm:    arm64.AMOVHU,
18294		reg: regInfo{
18295			inputs: []inputInfo{
18296				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18297			},
18298			outputs: []outputInfo{
18299				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18300			},
18301		},
18302	},
18303	{
18304		name:   "MOVWreg",
18305		argLen: 1,
18306		asm:    arm64.AMOVW,
18307		reg: regInfo{
18308			inputs: []inputInfo{
18309				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18310			},
18311			outputs: []outputInfo{
18312				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18313			},
18314		},
18315	},
18316	{
18317		name:   "MOVWUreg",
18318		argLen: 1,
18319		asm:    arm64.AMOVWU,
18320		reg: regInfo{
18321			inputs: []inputInfo{
18322				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18323			},
18324			outputs: []outputInfo{
18325				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18326			},
18327		},
18328	},
18329	{
18330		name:   "MOVDreg",
18331		argLen: 1,
18332		asm:    arm64.AMOVD,
18333		reg: regInfo{
18334			inputs: []inputInfo{
18335				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18336			},
18337			outputs: []outputInfo{
18338				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18339			},
18340		},
18341	},
18342	{
18343		name:         "MOVDnop",
18344		argLen:       1,
18345		resultInArg0: true,
18346		reg: regInfo{
18347			inputs: []inputInfo{
18348				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18349			},
18350			outputs: []outputInfo{
18351				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18352			},
18353		},
18354	},
18355	{
18356		name:   "SCVTFWS",
18357		argLen: 1,
18358		asm:    arm64.ASCVTFWS,
18359		reg: regInfo{
18360			inputs: []inputInfo{
18361				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18362			},
18363			outputs: []outputInfo{
18364				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18365			},
18366		},
18367	},
18368	{
18369		name:   "SCVTFWD",
18370		argLen: 1,
18371		asm:    arm64.ASCVTFWD,
18372		reg: regInfo{
18373			inputs: []inputInfo{
18374				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18375			},
18376			outputs: []outputInfo{
18377				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18378			},
18379		},
18380	},
18381	{
18382		name:   "UCVTFWS",
18383		argLen: 1,
18384		asm:    arm64.AUCVTFWS,
18385		reg: regInfo{
18386			inputs: []inputInfo{
18387				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18388			},
18389			outputs: []outputInfo{
18390				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18391			},
18392		},
18393	},
18394	{
18395		name:   "UCVTFWD",
18396		argLen: 1,
18397		asm:    arm64.AUCVTFWD,
18398		reg: regInfo{
18399			inputs: []inputInfo{
18400				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18401			},
18402			outputs: []outputInfo{
18403				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18404			},
18405		},
18406	},
18407	{
18408		name:   "SCVTFS",
18409		argLen: 1,
18410		asm:    arm64.ASCVTFS,
18411		reg: regInfo{
18412			inputs: []inputInfo{
18413				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18414			},
18415			outputs: []outputInfo{
18416				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18417			},
18418		},
18419	},
18420	{
18421		name:   "SCVTFD",
18422		argLen: 1,
18423		asm:    arm64.ASCVTFD,
18424		reg: regInfo{
18425			inputs: []inputInfo{
18426				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18427			},
18428			outputs: []outputInfo{
18429				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18430			},
18431		},
18432	},
18433	{
18434		name:   "UCVTFS",
18435		argLen: 1,
18436		asm:    arm64.AUCVTFS,
18437		reg: regInfo{
18438			inputs: []inputInfo{
18439				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18440			},
18441			outputs: []outputInfo{
18442				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18443			},
18444		},
18445	},
18446	{
18447		name:   "UCVTFD",
18448		argLen: 1,
18449		asm:    arm64.AUCVTFD,
18450		reg: regInfo{
18451			inputs: []inputInfo{
18452				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18453			},
18454			outputs: []outputInfo{
18455				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18456			},
18457		},
18458	},
18459	{
18460		name:   "FCVTZSSW",
18461		argLen: 1,
18462		asm:    arm64.AFCVTZSSW,
18463		reg: regInfo{
18464			inputs: []inputInfo{
18465				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18466			},
18467			outputs: []outputInfo{
18468				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18469			},
18470		},
18471	},
18472	{
18473		name:   "FCVTZSDW",
18474		argLen: 1,
18475		asm:    arm64.AFCVTZSDW,
18476		reg: regInfo{
18477			inputs: []inputInfo{
18478				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18479			},
18480			outputs: []outputInfo{
18481				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18482			},
18483		},
18484	},
18485	{
18486		name:   "FCVTZUSW",
18487		argLen: 1,
18488		asm:    arm64.AFCVTZUSW,
18489		reg: regInfo{
18490			inputs: []inputInfo{
18491				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18492			},
18493			outputs: []outputInfo{
18494				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18495			},
18496		},
18497	},
18498	{
18499		name:   "FCVTZUDW",
18500		argLen: 1,
18501		asm:    arm64.AFCVTZUDW,
18502		reg: regInfo{
18503			inputs: []inputInfo{
18504				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18505			},
18506			outputs: []outputInfo{
18507				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18508			},
18509		},
18510	},
18511	{
18512		name:   "FCVTZSS",
18513		argLen: 1,
18514		asm:    arm64.AFCVTZSS,
18515		reg: regInfo{
18516			inputs: []inputInfo{
18517				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18518			},
18519			outputs: []outputInfo{
18520				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18521			},
18522		},
18523	},
18524	{
18525		name:   "FCVTZSD",
18526		argLen: 1,
18527		asm:    arm64.AFCVTZSD,
18528		reg: regInfo{
18529			inputs: []inputInfo{
18530				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18531			},
18532			outputs: []outputInfo{
18533				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18534			},
18535		},
18536	},
18537	{
18538		name:   "FCVTZUS",
18539		argLen: 1,
18540		asm:    arm64.AFCVTZUS,
18541		reg: regInfo{
18542			inputs: []inputInfo{
18543				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18544			},
18545			outputs: []outputInfo{
18546				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18547			},
18548		},
18549	},
18550	{
18551		name:   "FCVTZUD",
18552		argLen: 1,
18553		asm:    arm64.AFCVTZUD,
18554		reg: regInfo{
18555			inputs: []inputInfo{
18556				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18557			},
18558			outputs: []outputInfo{
18559				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18560			},
18561		},
18562	},
18563	{
18564		name:   "FCVTSD",
18565		argLen: 1,
18566		asm:    arm64.AFCVTSD,
18567		reg: regInfo{
18568			inputs: []inputInfo{
18569				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18570			},
18571			outputs: []outputInfo{
18572				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18573			},
18574		},
18575	},
18576	{
18577		name:   "FCVTDS",
18578		argLen: 1,
18579		asm:    arm64.AFCVTDS,
18580		reg: regInfo{
18581			inputs: []inputInfo{
18582				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18583			},
18584			outputs: []outputInfo{
18585				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18586			},
18587		},
18588	},
18589	{
18590		name:   "FRINTAD",
18591		argLen: 1,
18592		asm:    arm64.AFRINTAD,
18593		reg: regInfo{
18594			inputs: []inputInfo{
18595				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18596			},
18597			outputs: []outputInfo{
18598				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18599			},
18600		},
18601	},
18602	{
18603		name:   "FRINTMD",
18604		argLen: 1,
18605		asm:    arm64.AFRINTMD,
18606		reg: regInfo{
18607			inputs: []inputInfo{
18608				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18609			},
18610			outputs: []outputInfo{
18611				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18612			},
18613		},
18614	},
18615	{
18616		name:   "FRINTND",
18617		argLen: 1,
18618		asm:    arm64.AFRINTND,
18619		reg: regInfo{
18620			inputs: []inputInfo{
18621				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18622			},
18623			outputs: []outputInfo{
18624				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18625			},
18626		},
18627	},
18628	{
18629		name:   "FRINTPD",
18630		argLen: 1,
18631		asm:    arm64.AFRINTPD,
18632		reg: regInfo{
18633			inputs: []inputInfo{
18634				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18635			},
18636			outputs: []outputInfo{
18637				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18638			},
18639		},
18640	},
18641	{
18642		name:   "FRINTZD",
18643		argLen: 1,
18644		asm:    arm64.AFRINTZD,
18645		reg: regInfo{
18646			inputs: []inputInfo{
18647				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18648			},
18649			outputs: []outputInfo{
18650				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18651			},
18652		},
18653	},
18654	{
18655		name:    "CSEL",
18656		auxType: auxCCop,
18657		argLen:  3,
18658		asm:     arm64.ACSEL,
18659		reg: regInfo{
18660			inputs: []inputInfo{
18661				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18662				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18663			},
18664			outputs: []outputInfo{
18665				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18666			},
18667		},
18668	},
18669	{
18670		name:    "CSEL0",
18671		auxType: auxCCop,
18672		argLen:  2,
18673		asm:     arm64.ACSEL,
18674		reg: regInfo{
18675			inputs: []inputInfo{
18676				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18677			},
18678			outputs: []outputInfo{
18679				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18680			},
18681		},
18682	},
18683	{
18684		name:         "CALLstatic",
18685		auxType:      auxSymOff,
18686		argLen:       1,
18687		clobberFlags: true,
18688		call:         true,
18689		symEffect:    SymNone,
18690		reg: regInfo{
18691			clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18692		},
18693	},
18694	{
18695		name:         "CALLclosure",
18696		auxType:      auxInt64,
18697		argLen:       3,
18698		clobberFlags: true,
18699		call:         true,
18700		reg: regInfo{
18701			inputs: []inputInfo{
18702				{1, 67108864},   // R26
18703				{0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP
18704			},
18705			clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18706		},
18707	},
18708	{
18709		name:         "CALLinter",
18710		auxType:      auxInt64,
18711		argLen:       2,
18712		clobberFlags: true,
18713		call:         true,
18714		reg: regInfo{
18715			inputs: []inputInfo{
18716				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18717			},
18718			clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18719		},
18720	},
18721	{
18722		name:           "LoweredNilCheck",
18723		argLen:         2,
18724		nilCheck:       true,
18725		faultOnNilArg0: true,
18726		reg: regInfo{
18727			inputs: []inputInfo{
18728				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18729			},
18730		},
18731	},
18732	{
18733		name:   "Equal",
18734		argLen: 1,
18735		reg: regInfo{
18736			outputs: []outputInfo{
18737				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18738			},
18739		},
18740	},
18741	{
18742		name:   "NotEqual",
18743		argLen: 1,
18744		reg: regInfo{
18745			outputs: []outputInfo{
18746				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18747			},
18748		},
18749	},
18750	{
18751		name:   "LessThan",
18752		argLen: 1,
18753		reg: regInfo{
18754			outputs: []outputInfo{
18755				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18756			},
18757		},
18758	},
18759	{
18760		name:   "LessEqual",
18761		argLen: 1,
18762		reg: regInfo{
18763			outputs: []outputInfo{
18764				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18765			},
18766		},
18767	},
18768	{
18769		name:   "GreaterThan",
18770		argLen: 1,
18771		reg: regInfo{
18772			outputs: []outputInfo{
18773				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18774			},
18775		},
18776	},
18777	{
18778		name:   "GreaterEqual",
18779		argLen: 1,
18780		reg: regInfo{
18781			outputs: []outputInfo{
18782				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18783			},
18784		},
18785	},
18786	{
18787		name:   "LessThanU",
18788		argLen: 1,
18789		reg: regInfo{
18790			outputs: []outputInfo{
18791				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18792			},
18793		},
18794	},
18795	{
18796		name:   "LessEqualU",
18797		argLen: 1,
18798		reg: regInfo{
18799			outputs: []outputInfo{
18800				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18801			},
18802		},
18803	},
18804	{
18805		name:   "GreaterThanU",
18806		argLen: 1,
18807		reg: regInfo{
18808			outputs: []outputInfo{
18809				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18810			},
18811		},
18812	},
18813	{
18814		name:   "GreaterEqualU",
18815		argLen: 1,
18816		reg: regInfo{
18817			outputs: []outputInfo{
18818				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18819			},
18820		},
18821	},
18822	{
18823		name:   "LessThanF",
18824		argLen: 1,
18825		reg: regInfo{
18826			outputs: []outputInfo{
18827				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18828			},
18829		},
18830	},
18831	{
18832		name:   "LessEqualF",
18833		argLen: 1,
18834		reg: regInfo{
18835			outputs: []outputInfo{
18836				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18837			},
18838		},
18839	},
18840	{
18841		name:   "GreaterThanF",
18842		argLen: 1,
18843		reg: regInfo{
18844			outputs: []outputInfo{
18845				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18846			},
18847		},
18848	},
18849	{
18850		name:   "GreaterEqualF",
18851		argLen: 1,
18852		reg: regInfo{
18853			outputs: []outputInfo{
18854				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18855			},
18856		},
18857	},
18858	{
18859		name:           "DUFFZERO",
18860		auxType:        auxInt64,
18861		argLen:         2,
18862		faultOnNilArg0: true,
18863		reg: regInfo{
18864			inputs: []inputInfo{
18865				{0, 1048576}, // R20
18866			},
18867			clobbers: 537919488, // R20 R30
18868		},
18869	},
18870	{
18871		name:           "LoweredZero",
18872		argLen:         3,
18873		clobberFlags:   true,
18874		faultOnNilArg0: true,
18875		reg: regInfo{
18876			inputs: []inputInfo{
18877				{0, 65536},     // R16
18878				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18879			},
18880			clobbers: 65536, // R16
18881		},
18882	},
18883	{
18884		name:           "DUFFCOPY",
18885		auxType:        auxInt64,
18886		argLen:         3,
18887		faultOnNilArg0: true,
18888		faultOnNilArg1: true,
18889		reg: regInfo{
18890			inputs: []inputInfo{
18891				{0, 2097152}, // R21
18892				{1, 1048576}, // R20
18893			},
18894			clobbers: 607125504, // R20 R21 R26 R30
18895		},
18896	},
18897	{
18898		name:           "LoweredMove",
18899		argLen:         4,
18900		clobberFlags:   true,
18901		faultOnNilArg0: true,
18902		faultOnNilArg1: true,
18903		reg: regInfo{
18904			inputs: []inputInfo{
18905				{0, 131072},    // R17
18906				{1, 65536},     // R16
18907				{2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18908			},
18909			clobbers: 196608, // R16 R17
18910		},
18911	},
18912	{
18913		name:      "LoweredGetClosurePtr",
18914		argLen:    0,
18915		zeroWidth: true,
18916		reg: regInfo{
18917			outputs: []outputInfo{
18918				{0, 67108864}, // R26
18919			},
18920		},
18921	},
18922	{
18923		name:              "LoweredGetCallerSP",
18924		argLen:            0,
18925		rematerializeable: true,
18926		reg: regInfo{
18927			outputs: []outputInfo{
18928				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18929			},
18930		},
18931	},
18932	{
18933		name:              "LoweredGetCallerPC",
18934		argLen:            0,
18935		rematerializeable: true,
18936		reg: regInfo{
18937			outputs: []outputInfo{
18938				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18939			},
18940		},
18941	},
18942	{
18943		name:   "FlagEQ",
18944		argLen: 0,
18945		reg:    regInfo{},
18946	},
18947	{
18948		name:   "FlagLT_ULT",
18949		argLen: 0,
18950		reg:    regInfo{},
18951	},
18952	{
18953		name:   "FlagLT_UGT",
18954		argLen: 0,
18955		reg:    regInfo{},
18956	},
18957	{
18958		name:   "FlagGT_UGT",
18959		argLen: 0,
18960		reg:    regInfo{},
18961	},
18962	{
18963		name:   "FlagGT_ULT",
18964		argLen: 0,
18965		reg:    regInfo{},
18966	},
18967	{
18968		name:   "InvertFlags",
18969		argLen: 1,
18970		reg:    regInfo{},
18971	},
18972	{
18973		name:           "LDAR",
18974		argLen:         2,
18975		faultOnNilArg0: true,
18976		asm:            arm64.ALDAR,
18977		reg: regInfo{
18978			inputs: []inputInfo{
18979				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18980			},
18981			outputs: []outputInfo{
18982				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18983			},
18984		},
18985	},
18986	{
18987		name:           "LDARB",
18988		argLen:         2,
18989		faultOnNilArg0: true,
18990		asm:            arm64.ALDARB,
18991		reg: regInfo{
18992			inputs: []inputInfo{
18993				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
18994			},
18995			outputs: []outputInfo{
18996				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18997			},
18998		},
18999	},
19000	{
19001		name:           "LDARW",
19002		argLen:         2,
19003		faultOnNilArg0: true,
19004		asm:            arm64.ALDARW,
19005		reg: regInfo{
19006			inputs: []inputInfo{
19007				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19008			},
19009			outputs: []outputInfo{
19010				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19011			},
19012		},
19013	},
19014	{
19015		name:           "STLRB",
19016		argLen:         3,
19017		faultOnNilArg0: true,
19018		hasSideEffects: true,
19019		asm:            arm64.ASTLRB,
19020		reg: regInfo{
19021			inputs: []inputInfo{
19022				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19023				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19024			},
19025		},
19026	},
19027	{
19028		name:           "STLR",
19029		argLen:         3,
19030		faultOnNilArg0: true,
19031		hasSideEffects: true,
19032		asm:            arm64.ASTLR,
19033		reg: regInfo{
19034			inputs: []inputInfo{
19035				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19036				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19037			},
19038		},
19039	},
19040	{
19041		name:           "STLRW",
19042		argLen:         3,
19043		faultOnNilArg0: true,
19044		hasSideEffects: true,
19045		asm:            arm64.ASTLRW,
19046		reg: regInfo{
19047			inputs: []inputInfo{
19048				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19049				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19050			},
19051		},
19052	},
19053	{
19054		name:            "LoweredAtomicExchange64",
19055		argLen:          3,
19056		resultNotInArgs: true,
19057		faultOnNilArg0:  true,
19058		hasSideEffects:  true,
19059		unsafePoint:     true,
19060		reg: regInfo{
19061			inputs: []inputInfo{
19062				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19063				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19064			},
19065			outputs: []outputInfo{
19066				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19067			},
19068		},
19069	},
19070	{
19071		name:            "LoweredAtomicExchange32",
19072		argLen:          3,
19073		resultNotInArgs: true,
19074		faultOnNilArg0:  true,
19075		hasSideEffects:  true,
19076		unsafePoint:     true,
19077		reg: regInfo{
19078			inputs: []inputInfo{
19079				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19080				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19081			},
19082			outputs: []outputInfo{
19083				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19084			},
19085		},
19086	},
19087	{
19088		name:            "LoweredAtomicAdd64",
19089		argLen:          3,
19090		resultNotInArgs: true,
19091		faultOnNilArg0:  true,
19092		hasSideEffects:  true,
19093		unsafePoint:     true,
19094		reg: regInfo{
19095			inputs: []inputInfo{
19096				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19097				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19098			},
19099			outputs: []outputInfo{
19100				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19101			},
19102		},
19103	},
19104	{
19105		name:            "LoweredAtomicAdd32",
19106		argLen:          3,
19107		resultNotInArgs: true,
19108		faultOnNilArg0:  true,
19109		hasSideEffects:  true,
19110		unsafePoint:     true,
19111		reg: regInfo{
19112			inputs: []inputInfo{
19113				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19114				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19115			},
19116			outputs: []outputInfo{
19117				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19118			},
19119		},
19120	},
19121	{
19122		name:            "LoweredAtomicAdd64Variant",
19123		argLen:          3,
19124		resultNotInArgs: true,
19125		faultOnNilArg0:  true,
19126		hasSideEffects:  true,
19127		reg: regInfo{
19128			inputs: []inputInfo{
19129				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19130				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19131			},
19132			outputs: []outputInfo{
19133				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19134			},
19135		},
19136	},
19137	{
19138		name:            "LoweredAtomicAdd32Variant",
19139		argLen:          3,
19140		resultNotInArgs: true,
19141		faultOnNilArg0:  true,
19142		hasSideEffects:  true,
19143		reg: regInfo{
19144			inputs: []inputInfo{
19145				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19146				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19147			},
19148			outputs: []outputInfo{
19149				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19150			},
19151		},
19152	},
19153	{
19154		name:            "LoweredAtomicCas64",
19155		argLen:          4,
19156		resultNotInArgs: true,
19157		clobberFlags:    true,
19158		faultOnNilArg0:  true,
19159		hasSideEffects:  true,
19160		unsafePoint:     true,
19161		reg: regInfo{
19162			inputs: []inputInfo{
19163				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19164				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19165				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19166			},
19167			outputs: []outputInfo{
19168				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19169			},
19170		},
19171	},
19172	{
19173		name:            "LoweredAtomicCas32",
19174		argLen:          4,
19175		resultNotInArgs: true,
19176		clobberFlags:    true,
19177		faultOnNilArg0:  true,
19178		hasSideEffects:  true,
19179		unsafePoint:     true,
19180		reg: regInfo{
19181			inputs: []inputInfo{
19182				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19183				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19184				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19185			},
19186			outputs: []outputInfo{
19187				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19188			},
19189		},
19190	},
19191	{
19192		name:            "LoweredAtomicAnd8",
19193		argLen:          3,
19194		resultNotInArgs: true,
19195		faultOnNilArg0:  true,
19196		hasSideEffects:  true,
19197		unsafePoint:     true,
19198		asm:             arm64.AAND,
19199		reg: regInfo{
19200			inputs: []inputInfo{
19201				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19202				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19203			},
19204			outputs: []outputInfo{
19205				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19206			},
19207		},
19208	},
19209	{
19210		name:            "LoweredAtomicOr8",
19211		argLen:          3,
19212		resultNotInArgs: true,
19213		faultOnNilArg0:  true,
19214		hasSideEffects:  true,
19215		unsafePoint:     true,
19216		asm:             arm64.AORR,
19217		reg: regInfo{
19218			inputs: []inputInfo{
19219				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19220				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19221			},
19222			outputs: []outputInfo{
19223				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19224			},
19225		},
19226	},
19227	{
19228		name:         "LoweredWB",
19229		auxType:      auxSym,
19230		argLen:       3,
19231		clobberFlags: true,
19232		symEffect:    SymNone,
19233		reg: regInfo{
19234			inputs: []inputInfo{
19235				{0, 4}, // R2
19236				{1, 8}, // R3
19237			},
19238			clobbers: 9223372035244163072, // R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19239		},
19240	},
19241	{
19242		name:    "LoweredPanicBoundsA",
19243		auxType: auxInt64,
19244		argLen:  3,
19245		reg: regInfo{
19246			inputs: []inputInfo{
19247				{0, 4}, // R2
19248				{1, 8}, // R3
19249			},
19250		},
19251	},
19252	{
19253		name:    "LoweredPanicBoundsB",
19254		auxType: auxInt64,
19255		argLen:  3,
19256		reg: regInfo{
19257			inputs: []inputInfo{
19258				{0, 2}, // R1
19259				{1, 4}, // R2
19260			},
19261		},
19262	},
19263	{
19264		name:    "LoweredPanicBoundsC",
19265		auxType: auxInt64,
19266		argLen:  3,
19267		reg: regInfo{
19268			inputs: []inputInfo{
19269				{0, 1}, // R0
19270				{1, 2}, // R1
19271			},
19272		},
19273	},
19274
19275	{
19276		name:        "ADD",
19277		argLen:      2,
19278		commutative: true,
19279		asm:         mips.AADDU,
19280		reg: regInfo{
19281			inputs: []inputInfo{
19282				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19283				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19284			},
19285			outputs: []outputInfo{
19286				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19287			},
19288		},
19289	},
19290	{
19291		name:    "ADDconst",
19292		auxType: auxInt32,
19293		argLen:  1,
19294		asm:     mips.AADDU,
19295		reg: regInfo{
19296			inputs: []inputInfo{
19297				{0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
19298			},
19299			outputs: []outputInfo{
19300				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19301			},
19302		},
19303	},
19304	{
19305		name:   "SUB",
19306		argLen: 2,
19307		asm:    mips.ASUBU,
19308		reg: regInfo{
19309			inputs: []inputInfo{
19310				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19311				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19312			},
19313			outputs: []outputInfo{
19314				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19315			},
19316		},
19317	},
19318	{
19319		name:    "SUBconst",
19320		auxType: auxInt32,
19321		argLen:  1,
19322		asm:     mips.ASUBU,
19323		reg: regInfo{
19324			inputs: []inputInfo{
19325				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19326			},
19327			outputs: []outputInfo{
19328				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19329			},
19330		},
19331	},
19332	{
19333		name:        "MUL",
19334		argLen:      2,
19335		commutative: true,
19336		asm:         mips.AMUL,
19337		reg: regInfo{
19338			inputs: []inputInfo{
19339				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19340				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19341			},
19342			clobbers: 105553116266496, // HI LO
19343			outputs: []outputInfo{
19344				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19345			},
19346		},
19347	},
19348	{
19349		name:        "MULT",
19350		argLen:      2,
19351		commutative: true,
19352		asm:         mips.AMUL,
19353		reg: regInfo{
19354			inputs: []inputInfo{
19355				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19356				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19357			},
19358			outputs: []outputInfo{
19359				{0, 35184372088832}, // HI
19360				{1, 70368744177664}, // LO
19361			},
19362		},
19363	},
19364	{
19365		name:        "MULTU",
19366		argLen:      2,
19367		commutative: true,
19368		asm:         mips.AMULU,
19369		reg: regInfo{
19370			inputs: []inputInfo{
19371				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19372				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19373			},
19374			outputs: []outputInfo{
19375				{0, 35184372088832}, // HI
19376				{1, 70368744177664}, // LO
19377			},
19378		},
19379	},
19380	{
19381		name:   "DIV",
19382		argLen: 2,
19383		asm:    mips.ADIV,
19384		reg: regInfo{
19385			inputs: []inputInfo{
19386				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19387				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19388			},
19389			outputs: []outputInfo{
19390				{0, 35184372088832}, // HI
19391				{1, 70368744177664}, // LO
19392			},
19393		},
19394	},
19395	{
19396		name:   "DIVU",
19397		argLen: 2,
19398		asm:    mips.ADIVU,
19399		reg: regInfo{
19400			inputs: []inputInfo{
19401				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19402				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19403			},
19404			outputs: []outputInfo{
19405				{0, 35184372088832}, // HI
19406				{1, 70368744177664}, // LO
19407			},
19408		},
19409	},
19410	{
19411		name:        "ADDF",
19412		argLen:      2,
19413		commutative: true,
19414		asm:         mips.AADDF,
19415		reg: regInfo{
19416			inputs: []inputInfo{
19417				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19418				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19419			},
19420			outputs: []outputInfo{
19421				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19422			},
19423		},
19424	},
19425	{
19426		name:        "ADDD",
19427		argLen:      2,
19428		commutative: true,
19429		asm:         mips.AADDD,
19430		reg: regInfo{
19431			inputs: []inputInfo{
19432				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19433				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19434			},
19435			outputs: []outputInfo{
19436				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19437			},
19438		},
19439	},
19440	{
19441		name:   "SUBF",
19442		argLen: 2,
19443		asm:    mips.ASUBF,
19444		reg: regInfo{
19445			inputs: []inputInfo{
19446				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19447				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19448			},
19449			outputs: []outputInfo{
19450				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19451			},
19452		},
19453	},
19454	{
19455		name:   "SUBD",
19456		argLen: 2,
19457		asm:    mips.ASUBD,
19458		reg: regInfo{
19459			inputs: []inputInfo{
19460				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19461				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19462			},
19463			outputs: []outputInfo{
19464				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19465			},
19466		},
19467	},
19468	{
19469		name:        "MULF",
19470		argLen:      2,
19471		commutative: true,
19472		asm:         mips.AMULF,
19473		reg: regInfo{
19474			inputs: []inputInfo{
19475				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19476				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19477			},
19478			outputs: []outputInfo{
19479				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19480			},
19481		},
19482	},
19483	{
19484		name:        "MULD",
19485		argLen:      2,
19486		commutative: true,
19487		asm:         mips.AMULD,
19488		reg: regInfo{
19489			inputs: []inputInfo{
19490				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19491				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19492			},
19493			outputs: []outputInfo{
19494				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19495			},
19496		},
19497	},
19498	{
19499		name:   "DIVF",
19500		argLen: 2,
19501		asm:    mips.ADIVF,
19502		reg: regInfo{
19503			inputs: []inputInfo{
19504				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19505				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19506			},
19507			outputs: []outputInfo{
19508				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19509			},
19510		},
19511	},
19512	{
19513		name:   "DIVD",
19514		argLen: 2,
19515		asm:    mips.ADIVD,
19516		reg: regInfo{
19517			inputs: []inputInfo{
19518				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19519				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19520			},
19521			outputs: []outputInfo{
19522				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19523			},
19524		},
19525	},
19526	{
19527		name:        "AND",
19528		argLen:      2,
19529		commutative: true,
19530		asm:         mips.AAND,
19531		reg: regInfo{
19532			inputs: []inputInfo{
19533				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19534				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19535			},
19536			outputs: []outputInfo{
19537				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19538			},
19539		},
19540	},
19541	{
19542		name:    "ANDconst",
19543		auxType: auxInt32,
19544		argLen:  1,
19545		asm:     mips.AAND,
19546		reg: regInfo{
19547			inputs: []inputInfo{
19548				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19549			},
19550			outputs: []outputInfo{
19551				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19552			},
19553		},
19554	},
19555	{
19556		name:        "OR",
19557		argLen:      2,
19558		commutative: true,
19559		asm:         mips.AOR,
19560		reg: regInfo{
19561			inputs: []inputInfo{
19562				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19563				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19564			},
19565			outputs: []outputInfo{
19566				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19567			},
19568		},
19569	},
19570	{
19571		name:    "ORconst",
19572		auxType: auxInt32,
19573		argLen:  1,
19574		asm:     mips.AOR,
19575		reg: regInfo{
19576			inputs: []inputInfo{
19577				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19578			},
19579			outputs: []outputInfo{
19580				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19581			},
19582		},
19583	},
19584	{
19585		name:        "XOR",
19586		argLen:      2,
19587		commutative: true,
19588		asm:         mips.AXOR,
19589		reg: regInfo{
19590			inputs: []inputInfo{
19591				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19592				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19593			},
19594			outputs: []outputInfo{
19595				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19596			},
19597		},
19598	},
19599	{
19600		name:    "XORconst",
19601		auxType: auxInt32,
19602		argLen:  1,
19603		asm:     mips.AXOR,
19604		reg: regInfo{
19605			inputs: []inputInfo{
19606				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19607			},
19608			outputs: []outputInfo{
19609				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19610			},
19611		},
19612	},
19613	{
19614		name:        "NOR",
19615		argLen:      2,
19616		commutative: true,
19617		asm:         mips.ANOR,
19618		reg: regInfo{
19619			inputs: []inputInfo{
19620				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19621				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19622			},
19623			outputs: []outputInfo{
19624				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19625			},
19626		},
19627	},
19628	{
19629		name:    "NORconst",
19630		auxType: auxInt32,
19631		argLen:  1,
19632		asm:     mips.ANOR,
19633		reg: regInfo{
19634			inputs: []inputInfo{
19635				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19636			},
19637			outputs: []outputInfo{
19638				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19639			},
19640		},
19641	},
19642	{
19643		name:   "NEG",
19644		argLen: 1,
19645		reg: regInfo{
19646			inputs: []inputInfo{
19647				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19648			},
19649			outputs: []outputInfo{
19650				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19651			},
19652		},
19653	},
19654	{
19655		name:   "NEGF",
19656		argLen: 1,
19657		asm:    mips.ANEGF,
19658		reg: regInfo{
19659			inputs: []inputInfo{
19660				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19661			},
19662			outputs: []outputInfo{
19663				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19664			},
19665		},
19666	},
19667	{
19668		name:   "NEGD",
19669		argLen: 1,
19670		asm:    mips.ANEGD,
19671		reg: regInfo{
19672			inputs: []inputInfo{
19673				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19674			},
19675			outputs: []outputInfo{
19676				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19677			},
19678		},
19679	},
19680	{
19681		name:   "SQRTD",
19682		argLen: 1,
19683		asm:    mips.ASQRTD,
19684		reg: regInfo{
19685			inputs: []inputInfo{
19686				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19687			},
19688			outputs: []outputInfo{
19689				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19690			},
19691		},
19692	},
19693	{
19694		name:   "SLL",
19695		argLen: 2,
19696		asm:    mips.ASLL,
19697		reg: regInfo{
19698			inputs: []inputInfo{
19699				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19700				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19701			},
19702			outputs: []outputInfo{
19703				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19704			},
19705		},
19706	},
19707	{
19708		name:    "SLLconst",
19709		auxType: auxInt32,
19710		argLen:  1,
19711		asm:     mips.ASLL,
19712		reg: regInfo{
19713			inputs: []inputInfo{
19714				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19715			},
19716			outputs: []outputInfo{
19717				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19718			},
19719		},
19720	},
19721	{
19722		name:   "SRL",
19723		argLen: 2,
19724		asm:    mips.ASRL,
19725		reg: regInfo{
19726			inputs: []inputInfo{
19727				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19728				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19729			},
19730			outputs: []outputInfo{
19731				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19732			},
19733		},
19734	},
19735	{
19736		name:    "SRLconst",
19737		auxType: auxInt32,
19738		argLen:  1,
19739		asm:     mips.ASRL,
19740		reg: regInfo{
19741			inputs: []inputInfo{
19742				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19743			},
19744			outputs: []outputInfo{
19745				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19746			},
19747		},
19748	},
19749	{
19750		name:   "SRA",
19751		argLen: 2,
19752		asm:    mips.ASRA,
19753		reg: regInfo{
19754			inputs: []inputInfo{
19755				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19756				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19757			},
19758			outputs: []outputInfo{
19759				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19760			},
19761		},
19762	},
19763	{
19764		name:    "SRAconst",
19765		auxType: auxInt32,
19766		argLen:  1,
19767		asm:     mips.ASRA,
19768		reg: regInfo{
19769			inputs: []inputInfo{
19770				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19771			},
19772			outputs: []outputInfo{
19773				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19774			},
19775		},
19776	},
19777	{
19778		name:   "CLZ",
19779		argLen: 1,
19780		asm:    mips.ACLZ,
19781		reg: regInfo{
19782			inputs: []inputInfo{
19783				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19784			},
19785			outputs: []outputInfo{
19786				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19787			},
19788		},
19789	},
19790	{
19791		name:   "SGT",
19792		argLen: 2,
19793		asm:    mips.ASGT,
19794		reg: regInfo{
19795			inputs: []inputInfo{
19796				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19797				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19798			},
19799			outputs: []outputInfo{
19800				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19801			},
19802		},
19803	},
19804	{
19805		name:    "SGTconst",
19806		auxType: auxInt32,
19807		argLen:  1,
19808		asm:     mips.ASGT,
19809		reg: regInfo{
19810			inputs: []inputInfo{
19811				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19812			},
19813			outputs: []outputInfo{
19814				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19815			},
19816		},
19817	},
19818	{
19819		name:   "SGTzero",
19820		argLen: 1,
19821		asm:    mips.ASGT,
19822		reg: regInfo{
19823			inputs: []inputInfo{
19824				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19825			},
19826			outputs: []outputInfo{
19827				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19828			},
19829		},
19830	},
19831	{
19832		name:   "SGTU",
19833		argLen: 2,
19834		asm:    mips.ASGTU,
19835		reg: regInfo{
19836			inputs: []inputInfo{
19837				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19838				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19839			},
19840			outputs: []outputInfo{
19841				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19842			},
19843		},
19844	},
19845	{
19846		name:    "SGTUconst",
19847		auxType: auxInt32,
19848		argLen:  1,
19849		asm:     mips.ASGTU,
19850		reg: regInfo{
19851			inputs: []inputInfo{
19852				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19853			},
19854			outputs: []outputInfo{
19855				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19856			},
19857		},
19858	},
19859	{
19860		name:   "SGTUzero",
19861		argLen: 1,
19862		asm:    mips.ASGTU,
19863		reg: regInfo{
19864			inputs: []inputInfo{
19865				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
19866			},
19867			outputs: []outputInfo{
19868				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19869			},
19870		},
19871	},
19872	{
19873		name:   "CMPEQF",
19874		argLen: 2,
19875		asm:    mips.ACMPEQF,
19876		reg: regInfo{
19877			inputs: []inputInfo{
19878				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19879				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19880			},
19881		},
19882	},
19883	{
19884		name:   "CMPEQD",
19885		argLen: 2,
19886		asm:    mips.ACMPEQD,
19887		reg: regInfo{
19888			inputs: []inputInfo{
19889				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19890				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19891			},
19892		},
19893	},
19894	{
19895		name:   "CMPGEF",
19896		argLen: 2,
19897		asm:    mips.ACMPGEF,
19898		reg: regInfo{
19899			inputs: []inputInfo{
19900				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19901				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19902			},
19903		},
19904	},
19905	{
19906		name:   "CMPGED",
19907		argLen: 2,
19908		asm:    mips.ACMPGED,
19909		reg: regInfo{
19910			inputs: []inputInfo{
19911				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19912				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19913			},
19914		},
19915	},
19916	{
19917		name:   "CMPGTF",
19918		argLen: 2,
19919		asm:    mips.ACMPGTF,
19920		reg: regInfo{
19921			inputs: []inputInfo{
19922				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19923				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19924			},
19925		},
19926	},
19927	{
19928		name:   "CMPGTD",
19929		argLen: 2,
19930		asm:    mips.ACMPGTD,
19931		reg: regInfo{
19932			inputs: []inputInfo{
19933				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19934				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19935			},
19936		},
19937	},
19938	{
19939		name:              "MOVWconst",
19940		auxType:           auxInt32,
19941		argLen:            0,
19942		rematerializeable: true,
19943		asm:               mips.AMOVW,
19944		reg: regInfo{
19945			outputs: []outputInfo{
19946				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19947			},
19948		},
19949	},
19950	{
19951		name:              "MOVFconst",
19952		auxType:           auxFloat32,
19953		argLen:            0,
19954		rematerializeable: true,
19955		asm:               mips.AMOVF,
19956		reg: regInfo{
19957			outputs: []outputInfo{
19958				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19959			},
19960		},
19961	},
19962	{
19963		name:              "MOVDconst",
19964		auxType:           auxFloat64,
19965		argLen:            0,
19966		rematerializeable: true,
19967		asm:               mips.AMOVD,
19968		reg: regInfo{
19969			outputs: []outputInfo{
19970				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
19971			},
19972		},
19973	},
19974	{
19975		name:              "MOVWaddr",
19976		auxType:           auxSymOff,
19977		argLen:            1,
19978		rematerializeable: true,
19979		symEffect:         SymAddr,
19980		asm:               mips.AMOVW,
19981		reg: regInfo{
19982			inputs: []inputInfo{
19983				{0, 140737555464192}, // SP SB
19984			},
19985			outputs: []outputInfo{
19986				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
19987			},
19988		},
19989	},
19990	{
19991		name:           "MOVBload",
19992		auxType:        auxSymOff,
19993		argLen:         2,
19994		faultOnNilArg0: true,
19995		symEffect:      SymRead,
19996		asm:            mips.AMOVB,
19997		reg: regInfo{
19998			inputs: []inputInfo{
19999				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20000			},
20001			outputs: []outputInfo{
20002				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20003			},
20004		},
20005	},
20006	{
20007		name:           "MOVBUload",
20008		auxType:        auxSymOff,
20009		argLen:         2,
20010		faultOnNilArg0: true,
20011		symEffect:      SymRead,
20012		asm:            mips.AMOVBU,
20013		reg: regInfo{
20014			inputs: []inputInfo{
20015				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20016			},
20017			outputs: []outputInfo{
20018				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20019			},
20020		},
20021	},
20022	{
20023		name:           "MOVHload",
20024		auxType:        auxSymOff,
20025		argLen:         2,
20026		faultOnNilArg0: true,
20027		symEffect:      SymRead,
20028		asm:            mips.AMOVH,
20029		reg: regInfo{
20030			inputs: []inputInfo{
20031				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20032			},
20033			outputs: []outputInfo{
20034				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20035			},
20036		},
20037	},
20038	{
20039		name:           "MOVHUload",
20040		auxType:        auxSymOff,
20041		argLen:         2,
20042		faultOnNilArg0: true,
20043		symEffect:      SymRead,
20044		asm:            mips.AMOVHU,
20045		reg: regInfo{
20046			inputs: []inputInfo{
20047				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20048			},
20049			outputs: []outputInfo{
20050				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20051			},
20052		},
20053	},
20054	{
20055		name:           "MOVWload",
20056		auxType:        auxSymOff,
20057		argLen:         2,
20058		faultOnNilArg0: true,
20059		symEffect:      SymRead,
20060		asm:            mips.AMOVW,
20061		reg: regInfo{
20062			inputs: []inputInfo{
20063				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20064			},
20065			outputs: []outputInfo{
20066				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20067			},
20068		},
20069	},
20070	{
20071		name:           "MOVFload",
20072		auxType:        auxSymOff,
20073		argLen:         2,
20074		faultOnNilArg0: true,
20075		symEffect:      SymRead,
20076		asm:            mips.AMOVF,
20077		reg: regInfo{
20078			inputs: []inputInfo{
20079				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20080			},
20081			outputs: []outputInfo{
20082				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20083			},
20084		},
20085	},
20086	{
20087		name:           "MOVDload",
20088		auxType:        auxSymOff,
20089		argLen:         2,
20090		faultOnNilArg0: true,
20091		symEffect:      SymRead,
20092		asm:            mips.AMOVD,
20093		reg: regInfo{
20094			inputs: []inputInfo{
20095				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20096			},
20097			outputs: []outputInfo{
20098				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20099			},
20100		},
20101	},
20102	{
20103		name:           "MOVBstore",
20104		auxType:        auxSymOff,
20105		argLen:         3,
20106		faultOnNilArg0: true,
20107		symEffect:      SymWrite,
20108		asm:            mips.AMOVB,
20109		reg: regInfo{
20110			inputs: []inputInfo{
20111				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20112				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20113			},
20114		},
20115	},
20116	{
20117		name:           "MOVHstore",
20118		auxType:        auxSymOff,
20119		argLen:         3,
20120		faultOnNilArg0: true,
20121		symEffect:      SymWrite,
20122		asm:            mips.AMOVH,
20123		reg: regInfo{
20124			inputs: []inputInfo{
20125				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20126				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20127			},
20128		},
20129	},
20130	{
20131		name:           "MOVWstore",
20132		auxType:        auxSymOff,
20133		argLen:         3,
20134		faultOnNilArg0: true,
20135		symEffect:      SymWrite,
20136		asm:            mips.AMOVW,
20137		reg: regInfo{
20138			inputs: []inputInfo{
20139				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20140				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20141			},
20142		},
20143	},
20144	{
20145		name:           "MOVFstore",
20146		auxType:        auxSymOff,
20147		argLen:         3,
20148		faultOnNilArg0: true,
20149		symEffect:      SymWrite,
20150		asm:            mips.AMOVF,
20151		reg: regInfo{
20152			inputs: []inputInfo{
20153				{1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20154				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20155			},
20156		},
20157	},
20158	{
20159		name:           "MOVDstore",
20160		auxType:        auxSymOff,
20161		argLen:         3,
20162		faultOnNilArg0: true,
20163		symEffect:      SymWrite,
20164		asm:            mips.AMOVD,
20165		reg: regInfo{
20166			inputs: []inputInfo{
20167				{1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20168				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20169			},
20170		},
20171	},
20172	{
20173		name:           "MOVBstorezero",
20174		auxType:        auxSymOff,
20175		argLen:         2,
20176		faultOnNilArg0: true,
20177		symEffect:      SymWrite,
20178		asm:            mips.AMOVB,
20179		reg: regInfo{
20180			inputs: []inputInfo{
20181				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20182			},
20183		},
20184	},
20185	{
20186		name:           "MOVHstorezero",
20187		auxType:        auxSymOff,
20188		argLen:         2,
20189		faultOnNilArg0: true,
20190		symEffect:      SymWrite,
20191		asm:            mips.AMOVH,
20192		reg: regInfo{
20193			inputs: []inputInfo{
20194				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20195			},
20196		},
20197	},
20198	{
20199		name:           "MOVWstorezero",
20200		auxType:        auxSymOff,
20201		argLen:         2,
20202		faultOnNilArg0: true,
20203		symEffect:      SymWrite,
20204		asm:            mips.AMOVW,
20205		reg: regInfo{
20206			inputs: []inputInfo{
20207				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20208			},
20209		},
20210	},
20211	{
20212		name:   "MOVBreg",
20213		argLen: 1,
20214		asm:    mips.AMOVB,
20215		reg: regInfo{
20216			inputs: []inputInfo{
20217				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20218			},
20219			outputs: []outputInfo{
20220				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20221			},
20222		},
20223	},
20224	{
20225		name:   "MOVBUreg",
20226		argLen: 1,
20227		asm:    mips.AMOVBU,
20228		reg: regInfo{
20229			inputs: []inputInfo{
20230				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20231			},
20232			outputs: []outputInfo{
20233				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20234			},
20235		},
20236	},
20237	{
20238		name:   "MOVHreg",
20239		argLen: 1,
20240		asm:    mips.AMOVH,
20241		reg: regInfo{
20242			inputs: []inputInfo{
20243				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20244			},
20245			outputs: []outputInfo{
20246				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20247			},
20248		},
20249	},
20250	{
20251		name:   "MOVHUreg",
20252		argLen: 1,
20253		asm:    mips.AMOVHU,
20254		reg: regInfo{
20255			inputs: []inputInfo{
20256				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20257			},
20258			outputs: []outputInfo{
20259				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20260			},
20261		},
20262	},
20263	{
20264		name:   "MOVWreg",
20265		argLen: 1,
20266		asm:    mips.AMOVW,
20267		reg: regInfo{
20268			inputs: []inputInfo{
20269				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20270			},
20271			outputs: []outputInfo{
20272				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20273			},
20274		},
20275	},
20276	{
20277		name:         "MOVWnop",
20278		argLen:       1,
20279		resultInArg0: true,
20280		reg: regInfo{
20281			inputs: []inputInfo{
20282				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20283			},
20284			outputs: []outputInfo{
20285				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20286			},
20287		},
20288	},
20289	{
20290		name:         "CMOVZ",
20291		argLen:       3,
20292		resultInArg0: true,
20293		asm:          mips.ACMOVZ,
20294		reg: regInfo{
20295			inputs: []inputInfo{
20296				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20297				{1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20298				{2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20299			},
20300			outputs: []outputInfo{
20301				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20302			},
20303		},
20304	},
20305	{
20306		name:         "CMOVZzero",
20307		argLen:       2,
20308		resultInArg0: true,
20309		asm:          mips.ACMOVZ,
20310		reg: regInfo{
20311			inputs: []inputInfo{
20312				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20313				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20314			},
20315			outputs: []outputInfo{
20316				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20317			},
20318		},
20319	},
20320	{
20321		name:   "MOVWF",
20322		argLen: 1,
20323		asm:    mips.AMOVWF,
20324		reg: regInfo{
20325			inputs: []inputInfo{
20326				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20327			},
20328			outputs: []outputInfo{
20329				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20330			},
20331		},
20332	},
20333	{
20334		name:   "MOVWD",
20335		argLen: 1,
20336		asm:    mips.AMOVWD,
20337		reg: regInfo{
20338			inputs: []inputInfo{
20339				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20340			},
20341			outputs: []outputInfo{
20342				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20343			},
20344		},
20345	},
20346	{
20347		name:   "TRUNCFW",
20348		argLen: 1,
20349		asm:    mips.ATRUNCFW,
20350		reg: regInfo{
20351			inputs: []inputInfo{
20352				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20353			},
20354			outputs: []outputInfo{
20355				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20356			},
20357		},
20358	},
20359	{
20360		name:   "TRUNCDW",
20361		argLen: 1,
20362		asm:    mips.ATRUNCDW,
20363		reg: regInfo{
20364			inputs: []inputInfo{
20365				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20366			},
20367			outputs: []outputInfo{
20368				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20369			},
20370		},
20371	},
20372	{
20373		name:   "MOVFD",
20374		argLen: 1,
20375		asm:    mips.AMOVFD,
20376		reg: regInfo{
20377			inputs: []inputInfo{
20378				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20379			},
20380			outputs: []outputInfo{
20381				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20382			},
20383		},
20384	},
20385	{
20386		name:   "MOVDF",
20387		argLen: 1,
20388		asm:    mips.AMOVDF,
20389		reg: regInfo{
20390			inputs: []inputInfo{
20391				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20392			},
20393			outputs: []outputInfo{
20394				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
20395			},
20396		},
20397	},
20398	{
20399		name:         "CALLstatic",
20400		auxType:      auxSymOff,
20401		argLen:       1,
20402		clobberFlags: true,
20403		call:         true,
20404		symEffect:    SymNone,
20405		reg: regInfo{
20406			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
20407		},
20408	},
20409	{
20410		name:         "CALLclosure",
20411		auxType:      auxInt64,
20412		argLen:       3,
20413		clobberFlags: true,
20414		call:         true,
20415		reg: regInfo{
20416			inputs: []inputInfo{
20417				{1, 4194304},   // R22
20418				{0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
20419			},
20420			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
20421		},
20422	},
20423	{
20424		name:         "CALLinter",
20425		auxType:      auxInt64,
20426		argLen:       2,
20427		clobberFlags: true,
20428		call:         true,
20429		reg: regInfo{
20430			inputs: []inputInfo{
20431				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20432			},
20433			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
20434		},
20435	},
20436	{
20437		name:           "LoweredAtomicLoad8",
20438		argLen:         2,
20439		faultOnNilArg0: true,
20440		reg: regInfo{
20441			inputs: []inputInfo{
20442				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20443			},
20444			outputs: []outputInfo{
20445				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20446			},
20447		},
20448	},
20449	{
20450		name:           "LoweredAtomicLoad32",
20451		argLen:         2,
20452		faultOnNilArg0: true,
20453		reg: regInfo{
20454			inputs: []inputInfo{
20455				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20456			},
20457			outputs: []outputInfo{
20458				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20459			},
20460		},
20461	},
20462	{
20463		name:           "LoweredAtomicStore8",
20464		argLen:         3,
20465		faultOnNilArg0: true,
20466		hasSideEffects: true,
20467		reg: regInfo{
20468			inputs: []inputInfo{
20469				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20470				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20471			},
20472		},
20473	},
20474	{
20475		name:           "LoweredAtomicStore32",
20476		argLen:         3,
20477		faultOnNilArg0: true,
20478		hasSideEffects: true,
20479		reg: regInfo{
20480			inputs: []inputInfo{
20481				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20482				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20483			},
20484		},
20485	},
20486	{
20487		name:           "LoweredAtomicStorezero",
20488		argLen:         2,
20489		faultOnNilArg0: true,
20490		hasSideEffects: true,
20491		reg: regInfo{
20492			inputs: []inputInfo{
20493				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20494			},
20495		},
20496	},
20497	{
20498		name:            "LoweredAtomicExchange",
20499		argLen:          3,
20500		resultNotInArgs: true,
20501		faultOnNilArg0:  true,
20502		hasSideEffects:  true,
20503		unsafePoint:     true,
20504		reg: regInfo{
20505			inputs: []inputInfo{
20506				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20507				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20508			},
20509			outputs: []outputInfo{
20510				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20511			},
20512		},
20513	},
20514	{
20515		name:            "LoweredAtomicAdd",
20516		argLen:          3,
20517		resultNotInArgs: true,
20518		faultOnNilArg0:  true,
20519		hasSideEffects:  true,
20520		unsafePoint:     true,
20521		reg: regInfo{
20522			inputs: []inputInfo{
20523				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20524				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20525			},
20526			outputs: []outputInfo{
20527				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20528			},
20529		},
20530	},
20531	{
20532		name:            "LoweredAtomicAddconst",
20533		auxType:         auxInt32,
20534		argLen:          2,
20535		resultNotInArgs: true,
20536		faultOnNilArg0:  true,
20537		hasSideEffects:  true,
20538		unsafePoint:     true,
20539		reg: regInfo{
20540			inputs: []inputInfo{
20541				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20542			},
20543			outputs: []outputInfo{
20544				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20545			},
20546		},
20547	},
20548	{
20549		name:            "LoweredAtomicCas",
20550		argLen:          4,
20551		resultNotInArgs: true,
20552		faultOnNilArg0:  true,
20553		hasSideEffects:  true,
20554		unsafePoint:     true,
20555		reg: regInfo{
20556			inputs: []inputInfo{
20557				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20558				{2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20559				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20560			},
20561			outputs: []outputInfo{
20562				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20563			},
20564		},
20565	},
20566	{
20567		name:           "LoweredAtomicAnd",
20568		argLen:         3,
20569		faultOnNilArg0: true,
20570		hasSideEffects: true,
20571		unsafePoint:    true,
20572		asm:            mips.AAND,
20573		reg: regInfo{
20574			inputs: []inputInfo{
20575				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20576				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20577			},
20578		},
20579	},
20580	{
20581		name:           "LoweredAtomicOr",
20582		argLen:         3,
20583		faultOnNilArg0: true,
20584		hasSideEffects: true,
20585		unsafePoint:    true,
20586		asm:            mips.AOR,
20587		reg: regInfo{
20588			inputs: []inputInfo{
20589				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20590				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
20591			},
20592		},
20593	},
20594	{
20595		name:           "LoweredZero",
20596		auxType:        auxInt32,
20597		argLen:         3,
20598		faultOnNilArg0: true,
20599		reg: regInfo{
20600			inputs: []inputInfo{
20601				{0, 2},         // R1
20602				{1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20603			},
20604			clobbers: 2, // R1
20605		},
20606	},
20607	{
20608		name:           "LoweredMove",
20609		auxType:        auxInt32,
20610		argLen:         4,
20611		faultOnNilArg0: true,
20612		faultOnNilArg1: true,
20613		reg: regInfo{
20614			inputs: []inputInfo{
20615				{0, 4},         // R2
20616				{1, 2},         // R1
20617				{2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20618			},
20619			clobbers: 6, // R1 R2
20620		},
20621	},
20622	{
20623		name:           "LoweredNilCheck",
20624		argLen:         2,
20625		nilCheck:       true,
20626		faultOnNilArg0: true,
20627		reg: regInfo{
20628			inputs: []inputInfo{
20629				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
20630			},
20631		},
20632	},
20633	{
20634		name:   "FPFlagTrue",
20635		argLen: 1,
20636		reg: regInfo{
20637			outputs: []outputInfo{
20638				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20639			},
20640		},
20641	},
20642	{
20643		name:   "FPFlagFalse",
20644		argLen: 1,
20645		reg: regInfo{
20646			outputs: []outputInfo{
20647				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20648			},
20649		},
20650	},
20651	{
20652		name:      "LoweredGetClosurePtr",
20653		argLen:    0,
20654		zeroWidth: true,
20655		reg: regInfo{
20656			outputs: []outputInfo{
20657				{0, 4194304}, // R22
20658			},
20659		},
20660	},
20661	{
20662		name:              "LoweredGetCallerSP",
20663		argLen:            0,
20664		rematerializeable: true,
20665		reg: regInfo{
20666			outputs: []outputInfo{
20667				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20668			},
20669		},
20670	},
20671	{
20672		name:              "LoweredGetCallerPC",
20673		argLen:            0,
20674		rematerializeable: true,
20675		reg: regInfo{
20676			outputs: []outputInfo{
20677				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
20678			},
20679		},
20680	},
20681	{
20682		name:         "LoweredWB",
20683		auxType:      auxSym,
20684		argLen:       3,
20685		clobberFlags: true,
20686		symEffect:    SymNone,
20687		reg: regInfo{
20688			inputs: []inputInfo{
20689				{0, 1048576}, // R20
20690				{1, 2097152}, // R21
20691			},
20692			clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
20693		},
20694	},
20695	{
20696		name:    "LoweredPanicBoundsA",
20697		auxType: auxInt64,
20698		argLen:  3,
20699		reg: regInfo{
20700			inputs: []inputInfo{
20701				{0, 8},  // R3
20702				{1, 16}, // R4
20703			},
20704		},
20705	},
20706	{
20707		name:    "LoweredPanicBoundsB",
20708		auxType: auxInt64,
20709		argLen:  3,
20710		reg: regInfo{
20711			inputs: []inputInfo{
20712				{0, 4}, // R2
20713				{1, 8}, // R3
20714			},
20715		},
20716	},
20717	{
20718		name:    "LoweredPanicBoundsC",
20719		auxType: auxInt64,
20720		argLen:  3,
20721		reg: regInfo{
20722			inputs: []inputInfo{
20723				{0, 2}, // R1
20724				{1, 4}, // R2
20725			},
20726		},
20727	},
20728	{
20729		name:    "LoweredPanicExtendA",
20730		auxType: auxInt64,
20731		argLen:  4,
20732		reg: regInfo{
20733			inputs: []inputInfo{
20734				{0, 32}, // R5
20735				{1, 8},  // R3
20736				{2, 16}, // R4
20737			},
20738		},
20739	},
20740	{
20741		name:    "LoweredPanicExtendB",
20742		auxType: auxInt64,
20743		argLen:  4,
20744		reg: regInfo{
20745			inputs: []inputInfo{
20746				{0, 32}, // R5
20747				{1, 4},  // R2
20748				{2, 8},  // R3
20749			},
20750		},
20751	},
20752	{
20753		name:    "LoweredPanicExtendC",
20754		auxType: auxInt64,
20755		argLen:  4,
20756		reg: regInfo{
20757			inputs: []inputInfo{
20758				{0, 32}, // R5
20759				{1, 2},  // R1
20760				{2, 4},  // R2
20761			},
20762		},
20763	},
20764
20765	{
20766		name:        "ADDV",
20767		argLen:      2,
20768		commutative: true,
20769		asm:         mips.AADDVU,
20770		reg: regInfo{
20771			inputs: []inputInfo{
20772				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20773				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20774			},
20775			outputs: []outputInfo{
20776				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
20777			},
20778		},
20779	},
20780	{
20781		name:    "ADDVconst",
20782		auxType: auxInt64,
20783		argLen:  1,
20784		asm:     mips.AADDVU,
20785		reg: regInfo{
20786			inputs: []inputInfo{
20787				{0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
20788			},
20789			outputs: []outputInfo{
20790				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
20791			},
20792		},
20793	},
20794	{
20795		name:   "SUBV",
20796		argLen: 2,
20797		asm:    mips.ASUBVU,
20798		reg: regInfo{
20799			inputs: []inputInfo{
20800				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20801				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20802			},
20803			outputs: []outputInfo{
20804				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
20805			},
20806		},
20807	},
20808	{
20809		name:    "SUBVconst",
20810		auxType: auxInt64,
20811		argLen:  1,
20812		asm:     mips.ASUBVU,
20813		reg: regInfo{
20814			inputs: []inputInfo{
20815				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20816			},
20817			outputs: []outputInfo{
20818				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
20819			},
20820		},
20821	},
20822	{
20823		name:        "MULV",
20824		argLen:      2,
20825		commutative: true,
20826		asm:         mips.AMULV,
20827		reg: regInfo{
20828			inputs: []inputInfo{
20829				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20830				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20831			},
20832			outputs: []outputInfo{
20833				{0, 1152921504606846976}, // HI
20834				{1, 2305843009213693952}, // LO
20835			},
20836		},
20837	},
20838	{
20839		name:        "MULVU",
20840		argLen:      2,
20841		commutative: true,
20842		asm:         mips.AMULVU,
20843		reg: regInfo{
20844			inputs: []inputInfo{
20845				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20846				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20847			},
20848			outputs: []outputInfo{
20849				{0, 1152921504606846976}, // HI
20850				{1, 2305843009213693952}, // LO
20851			},
20852		},
20853	},
20854	{
20855		name:   "DIVV",
20856		argLen: 2,
20857		asm:    mips.ADIVV,
20858		reg: regInfo{
20859			inputs: []inputInfo{
20860				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20861				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20862			},
20863			outputs: []outputInfo{
20864				{0, 1152921504606846976}, // HI
20865				{1, 2305843009213693952}, // LO
20866			},
20867		},
20868	},
20869	{
20870		name:   "DIVVU",
20871		argLen: 2,
20872		asm:    mips.ADIVVU,
20873		reg: regInfo{
20874			inputs: []inputInfo{
20875				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20876				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
20877			},
20878			outputs: []outputInfo{
20879				{0, 1152921504606846976}, // HI
20880				{1, 2305843009213693952}, // LO
20881			},
20882		},
20883	},
20884	{
20885		name:        "ADDF",
20886		argLen:      2,
20887		commutative: true,
20888		asm:         mips.AADDF,
20889		reg: regInfo{
20890			inputs: []inputInfo{
20891				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20892				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20893			},
20894			outputs: []outputInfo{
20895				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20896			},
20897		},
20898	},
20899	{
20900		name:        "ADDD",
20901		argLen:      2,
20902		commutative: true,
20903		asm:         mips.AADDD,
20904		reg: regInfo{
20905			inputs: []inputInfo{
20906				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20907				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20908			},
20909			outputs: []outputInfo{
20910				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20911			},
20912		},
20913	},
20914	{
20915		name:   "SUBF",
20916		argLen: 2,
20917		asm:    mips.ASUBF,
20918		reg: regInfo{
20919			inputs: []inputInfo{
20920				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20921				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20922			},
20923			outputs: []outputInfo{
20924				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20925			},
20926		},
20927	},
20928	{
20929		name:   "SUBD",
20930		argLen: 2,
20931		asm:    mips.ASUBD,
20932		reg: regInfo{
20933			inputs: []inputInfo{
20934				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20935				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20936			},
20937			outputs: []outputInfo{
20938				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20939			},
20940		},
20941	},
20942	{
20943		name:        "MULF",
20944		argLen:      2,
20945		commutative: true,
20946		asm:         mips.AMULF,
20947		reg: regInfo{
20948			inputs: []inputInfo{
20949				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20950				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20951			},
20952			outputs: []outputInfo{
20953				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20954			},
20955		},
20956	},
20957	{
20958		name:        "MULD",
20959		argLen:      2,
20960		commutative: true,
20961		asm:         mips.AMULD,
20962		reg: regInfo{
20963			inputs: []inputInfo{
20964				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20965				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20966			},
20967			outputs: []outputInfo{
20968				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20969			},
20970		},
20971	},
20972	{
20973		name:   "DIVF",
20974		argLen: 2,
20975		asm:    mips.ADIVF,
20976		reg: regInfo{
20977			inputs: []inputInfo{
20978				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20979				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20980			},
20981			outputs: []outputInfo{
20982				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20983			},
20984		},
20985	},
20986	{
20987		name:   "DIVD",
20988		argLen: 2,
20989		asm:    mips.ADIVD,
20990		reg: regInfo{
20991			inputs: []inputInfo{
20992				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20993				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20994			},
20995			outputs: []outputInfo{
20996				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20997			},
20998		},
20999	},
21000	{
21001		name:        "AND",
21002		argLen:      2,
21003		commutative: true,
21004		asm:         mips.AAND,
21005		reg: regInfo{
21006			inputs: []inputInfo{
21007				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21008				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21009			},
21010			outputs: []outputInfo{
21011				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21012			},
21013		},
21014	},
21015	{
21016		name:    "ANDconst",
21017		auxType: auxInt64,
21018		argLen:  1,
21019		asm:     mips.AAND,
21020		reg: regInfo{
21021			inputs: []inputInfo{
21022				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21023			},
21024			outputs: []outputInfo{
21025				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21026			},
21027		},
21028	},
21029	{
21030		name:        "OR",
21031		argLen:      2,
21032		commutative: true,
21033		asm:         mips.AOR,
21034		reg: regInfo{
21035			inputs: []inputInfo{
21036				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21037				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21038			},
21039			outputs: []outputInfo{
21040				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21041			},
21042		},
21043	},
21044	{
21045		name:    "ORconst",
21046		auxType: auxInt64,
21047		argLen:  1,
21048		asm:     mips.AOR,
21049		reg: regInfo{
21050			inputs: []inputInfo{
21051				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21052			},
21053			outputs: []outputInfo{
21054				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21055			},
21056		},
21057	},
21058	{
21059		name:        "XOR",
21060		argLen:      2,
21061		commutative: true,
21062		asm:         mips.AXOR,
21063		reg: regInfo{
21064			inputs: []inputInfo{
21065				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21066				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21067			},
21068			outputs: []outputInfo{
21069				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21070			},
21071		},
21072	},
21073	{
21074		name:    "XORconst",
21075		auxType: auxInt64,
21076		argLen:  1,
21077		asm:     mips.AXOR,
21078		reg: regInfo{
21079			inputs: []inputInfo{
21080				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21081			},
21082			outputs: []outputInfo{
21083				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21084			},
21085		},
21086	},
21087	{
21088		name:        "NOR",
21089		argLen:      2,
21090		commutative: true,
21091		asm:         mips.ANOR,
21092		reg: regInfo{
21093			inputs: []inputInfo{
21094				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21095				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21096			},
21097			outputs: []outputInfo{
21098				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21099			},
21100		},
21101	},
21102	{
21103		name:    "NORconst",
21104		auxType: auxInt64,
21105		argLen:  1,
21106		asm:     mips.ANOR,
21107		reg: regInfo{
21108			inputs: []inputInfo{
21109				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21110			},
21111			outputs: []outputInfo{
21112				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21113			},
21114		},
21115	},
21116	{
21117		name:   "NEGV",
21118		argLen: 1,
21119		reg: regInfo{
21120			inputs: []inputInfo{
21121				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21122			},
21123			outputs: []outputInfo{
21124				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21125			},
21126		},
21127	},
21128	{
21129		name:   "NEGF",
21130		argLen: 1,
21131		asm:    mips.ANEGF,
21132		reg: regInfo{
21133			inputs: []inputInfo{
21134				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21135			},
21136			outputs: []outputInfo{
21137				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21138			},
21139		},
21140	},
21141	{
21142		name:   "NEGD",
21143		argLen: 1,
21144		asm:    mips.ANEGD,
21145		reg: regInfo{
21146			inputs: []inputInfo{
21147				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21148			},
21149			outputs: []outputInfo{
21150				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21151			},
21152		},
21153	},
21154	{
21155		name:   "SQRTD",
21156		argLen: 1,
21157		asm:    mips.ASQRTD,
21158		reg: regInfo{
21159			inputs: []inputInfo{
21160				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21161			},
21162			outputs: []outputInfo{
21163				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21164			},
21165		},
21166	},
21167	{
21168		name:   "SLLV",
21169		argLen: 2,
21170		asm:    mips.ASLLV,
21171		reg: regInfo{
21172			inputs: []inputInfo{
21173				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21174				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21175			},
21176			outputs: []outputInfo{
21177				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21178			},
21179		},
21180	},
21181	{
21182		name:    "SLLVconst",
21183		auxType: auxInt64,
21184		argLen:  1,
21185		asm:     mips.ASLLV,
21186		reg: regInfo{
21187			inputs: []inputInfo{
21188				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21189			},
21190			outputs: []outputInfo{
21191				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21192			},
21193		},
21194	},
21195	{
21196		name:   "SRLV",
21197		argLen: 2,
21198		asm:    mips.ASRLV,
21199		reg: regInfo{
21200			inputs: []inputInfo{
21201				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21202				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21203			},
21204			outputs: []outputInfo{
21205				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21206			},
21207		},
21208	},
21209	{
21210		name:    "SRLVconst",
21211		auxType: auxInt64,
21212		argLen:  1,
21213		asm:     mips.ASRLV,
21214		reg: regInfo{
21215			inputs: []inputInfo{
21216				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21217			},
21218			outputs: []outputInfo{
21219				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21220			},
21221		},
21222	},
21223	{
21224		name:   "SRAV",
21225		argLen: 2,
21226		asm:    mips.ASRAV,
21227		reg: regInfo{
21228			inputs: []inputInfo{
21229				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21230				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21231			},
21232			outputs: []outputInfo{
21233				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21234			},
21235		},
21236	},
21237	{
21238		name:    "SRAVconst",
21239		auxType: auxInt64,
21240		argLen:  1,
21241		asm:     mips.ASRAV,
21242		reg: regInfo{
21243			inputs: []inputInfo{
21244				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21245			},
21246			outputs: []outputInfo{
21247				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21248			},
21249		},
21250	},
21251	{
21252		name:   "SGT",
21253		argLen: 2,
21254		asm:    mips.ASGT,
21255		reg: regInfo{
21256			inputs: []inputInfo{
21257				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21258				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21259			},
21260			outputs: []outputInfo{
21261				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21262			},
21263		},
21264	},
21265	{
21266		name:    "SGTconst",
21267		auxType: auxInt64,
21268		argLen:  1,
21269		asm:     mips.ASGT,
21270		reg: regInfo{
21271			inputs: []inputInfo{
21272				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21273			},
21274			outputs: []outputInfo{
21275				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21276			},
21277		},
21278	},
21279	{
21280		name:   "SGTU",
21281		argLen: 2,
21282		asm:    mips.ASGTU,
21283		reg: regInfo{
21284			inputs: []inputInfo{
21285				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21286				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21287			},
21288			outputs: []outputInfo{
21289				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21290			},
21291		},
21292	},
21293	{
21294		name:    "SGTUconst",
21295		auxType: auxInt64,
21296		argLen:  1,
21297		asm:     mips.ASGTU,
21298		reg: regInfo{
21299			inputs: []inputInfo{
21300				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21301			},
21302			outputs: []outputInfo{
21303				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21304			},
21305		},
21306	},
21307	{
21308		name:   "CMPEQF",
21309		argLen: 2,
21310		asm:    mips.ACMPEQF,
21311		reg: regInfo{
21312			inputs: []inputInfo{
21313				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21314				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21315			},
21316		},
21317	},
21318	{
21319		name:   "CMPEQD",
21320		argLen: 2,
21321		asm:    mips.ACMPEQD,
21322		reg: regInfo{
21323			inputs: []inputInfo{
21324				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21325				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21326			},
21327		},
21328	},
21329	{
21330		name:   "CMPGEF",
21331		argLen: 2,
21332		asm:    mips.ACMPGEF,
21333		reg: regInfo{
21334			inputs: []inputInfo{
21335				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21336				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21337			},
21338		},
21339	},
21340	{
21341		name:   "CMPGED",
21342		argLen: 2,
21343		asm:    mips.ACMPGED,
21344		reg: regInfo{
21345			inputs: []inputInfo{
21346				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21347				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21348			},
21349		},
21350	},
21351	{
21352		name:   "CMPGTF",
21353		argLen: 2,
21354		asm:    mips.ACMPGTF,
21355		reg: regInfo{
21356			inputs: []inputInfo{
21357				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21358				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21359			},
21360		},
21361	},
21362	{
21363		name:   "CMPGTD",
21364		argLen: 2,
21365		asm:    mips.ACMPGTD,
21366		reg: regInfo{
21367			inputs: []inputInfo{
21368				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21369				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21370			},
21371		},
21372	},
21373	{
21374		name:              "MOVVconst",
21375		auxType:           auxInt64,
21376		argLen:            0,
21377		rematerializeable: true,
21378		asm:               mips.AMOVV,
21379		reg: regInfo{
21380			outputs: []outputInfo{
21381				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21382			},
21383		},
21384	},
21385	{
21386		name:              "MOVFconst",
21387		auxType:           auxFloat64,
21388		argLen:            0,
21389		rematerializeable: true,
21390		asm:               mips.AMOVF,
21391		reg: regInfo{
21392			outputs: []outputInfo{
21393				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21394			},
21395		},
21396	},
21397	{
21398		name:              "MOVDconst",
21399		auxType:           auxFloat64,
21400		argLen:            0,
21401		rematerializeable: true,
21402		asm:               mips.AMOVD,
21403		reg: regInfo{
21404			outputs: []outputInfo{
21405				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21406			},
21407		},
21408	},
21409	{
21410		name:              "MOVVaddr",
21411		auxType:           auxSymOff,
21412		argLen:            1,
21413		rematerializeable: true,
21414		symEffect:         SymAddr,
21415		asm:               mips.AMOVV,
21416		reg: regInfo{
21417			inputs: []inputInfo{
21418				{0, 4611686018460942336}, // SP SB
21419			},
21420			outputs: []outputInfo{
21421				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21422			},
21423		},
21424	},
21425	{
21426		name:           "MOVBload",
21427		auxType:        auxSymOff,
21428		argLen:         2,
21429		faultOnNilArg0: true,
21430		symEffect:      SymRead,
21431		asm:            mips.AMOVB,
21432		reg: regInfo{
21433			inputs: []inputInfo{
21434				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21435			},
21436			outputs: []outputInfo{
21437				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21438			},
21439		},
21440	},
21441	{
21442		name:           "MOVBUload",
21443		auxType:        auxSymOff,
21444		argLen:         2,
21445		faultOnNilArg0: true,
21446		symEffect:      SymRead,
21447		asm:            mips.AMOVBU,
21448		reg: regInfo{
21449			inputs: []inputInfo{
21450				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21451			},
21452			outputs: []outputInfo{
21453				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21454			},
21455		},
21456	},
21457	{
21458		name:           "MOVHload",
21459		auxType:        auxSymOff,
21460		argLen:         2,
21461		faultOnNilArg0: true,
21462		symEffect:      SymRead,
21463		asm:            mips.AMOVH,
21464		reg: regInfo{
21465			inputs: []inputInfo{
21466				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21467			},
21468			outputs: []outputInfo{
21469				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21470			},
21471		},
21472	},
21473	{
21474		name:           "MOVHUload",
21475		auxType:        auxSymOff,
21476		argLen:         2,
21477		faultOnNilArg0: true,
21478		symEffect:      SymRead,
21479		asm:            mips.AMOVHU,
21480		reg: regInfo{
21481			inputs: []inputInfo{
21482				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21483			},
21484			outputs: []outputInfo{
21485				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21486			},
21487		},
21488	},
21489	{
21490		name:           "MOVWload",
21491		auxType:        auxSymOff,
21492		argLen:         2,
21493		faultOnNilArg0: true,
21494		symEffect:      SymRead,
21495		asm:            mips.AMOVW,
21496		reg: regInfo{
21497			inputs: []inputInfo{
21498				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21499			},
21500			outputs: []outputInfo{
21501				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21502			},
21503		},
21504	},
21505	{
21506		name:           "MOVWUload",
21507		auxType:        auxSymOff,
21508		argLen:         2,
21509		faultOnNilArg0: true,
21510		symEffect:      SymRead,
21511		asm:            mips.AMOVWU,
21512		reg: regInfo{
21513			inputs: []inputInfo{
21514				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21515			},
21516			outputs: []outputInfo{
21517				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21518			},
21519		},
21520	},
21521	{
21522		name:           "MOVVload",
21523		auxType:        auxSymOff,
21524		argLen:         2,
21525		faultOnNilArg0: true,
21526		symEffect:      SymRead,
21527		asm:            mips.AMOVV,
21528		reg: regInfo{
21529			inputs: []inputInfo{
21530				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21531			},
21532			outputs: []outputInfo{
21533				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21534			},
21535		},
21536	},
21537	{
21538		name:           "MOVFload",
21539		auxType:        auxSymOff,
21540		argLen:         2,
21541		faultOnNilArg0: true,
21542		symEffect:      SymRead,
21543		asm:            mips.AMOVF,
21544		reg: regInfo{
21545			inputs: []inputInfo{
21546				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21547			},
21548			outputs: []outputInfo{
21549				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21550			},
21551		},
21552	},
21553	{
21554		name:           "MOVDload",
21555		auxType:        auxSymOff,
21556		argLen:         2,
21557		faultOnNilArg0: true,
21558		symEffect:      SymRead,
21559		asm:            mips.AMOVD,
21560		reg: regInfo{
21561			inputs: []inputInfo{
21562				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21563			},
21564			outputs: []outputInfo{
21565				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21566			},
21567		},
21568	},
21569	{
21570		name:           "MOVBstore",
21571		auxType:        auxSymOff,
21572		argLen:         3,
21573		faultOnNilArg0: true,
21574		symEffect:      SymWrite,
21575		asm:            mips.AMOVB,
21576		reg: regInfo{
21577			inputs: []inputInfo{
21578				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21579				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21580			},
21581		},
21582	},
21583	{
21584		name:           "MOVHstore",
21585		auxType:        auxSymOff,
21586		argLen:         3,
21587		faultOnNilArg0: true,
21588		symEffect:      SymWrite,
21589		asm:            mips.AMOVH,
21590		reg: regInfo{
21591			inputs: []inputInfo{
21592				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21593				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21594			},
21595		},
21596	},
21597	{
21598		name:           "MOVWstore",
21599		auxType:        auxSymOff,
21600		argLen:         3,
21601		faultOnNilArg0: true,
21602		symEffect:      SymWrite,
21603		asm:            mips.AMOVW,
21604		reg: regInfo{
21605			inputs: []inputInfo{
21606				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21607				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21608			},
21609		},
21610	},
21611	{
21612		name:           "MOVVstore",
21613		auxType:        auxSymOff,
21614		argLen:         3,
21615		faultOnNilArg0: true,
21616		symEffect:      SymWrite,
21617		asm:            mips.AMOVV,
21618		reg: regInfo{
21619			inputs: []inputInfo{
21620				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21621				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21622			},
21623		},
21624	},
21625	{
21626		name:           "MOVFstore",
21627		auxType:        auxSymOff,
21628		argLen:         3,
21629		faultOnNilArg0: true,
21630		symEffect:      SymWrite,
21631		asm:            mips.AMOVF,
21632		reg: regInfo{
21633			inputs: []inputInfo{
21634				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21635				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21636			},
21637		},
21638	},
21639	{
21640		name:           "MOVDstore",
21641		auxType:        auxSymOff,
21642		argLen:         3,
21643		faultOnNilArg0: true,
21644		symEffect:      SymWrite,
21645		asm:            mips.AMOVD,
21646		reg: regInfo{
21647			inputs: []inputInfo{
21648				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21649				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21650			},
21651		},
21652	},
21653	{
21654		name:           "MOVBstorezero",
21655		auxType:        auxSymOff,
21656		argLen:         2,
21657		faultOnNilArg0: true,
21658		symEffect:      SymWrite,
21659		asm:            mips.AMOVB,
21660		reg: regInfo{
21661			inputs: []inputInfo{
21662				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21663			},
21664		},
21665	},
21666	{
21667		name:           "MOVHstorezero",
21668		auxType:        auxSymOff,
21669		argLen:         2,
21670		faultOnNilArg0: true,
21671		symEffect:      SymWrite,
21672		asm:            mips.AMOVH,
21673		reg: regInfo{
21674			inputs: []inputInfo{
21675				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21676			},
21677		},
21678	},
21679	{
21680		name:           "MOVWstorezero",
21681		auxType:        auxSymOff,
21682		argLen:         2,
21683		faultOnNilArg0: true,
21684		symEffect:      SymWrite,
21685		asm:            mips.AMOVW,
21686		reg: regInfo{
21687			inputs: []inputInfo{
21688				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21689			},
21690		},
21691	},
21692	{
21693		name:           "MOVVstorezero",
21694		auxType:        auxSymOff,
21695		argLen:         2,
21696		faultOnNilArg0: true,
21697		symEffect:      SymWrite,
21698		asm:            mips.AMOVV,
21699		reg: regInfo{
21700			inputs: []inputInfo{
21701				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
21702			},
21703		},
21704	},
21705	{
21706		name:   "MOVBreg",
21707		argLen: 1,
21708		asm:    mips.AMOVB,
21709		reg: regInfo{
21710			inputs: []inputInfo{
21711				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21712			},
21713			outputs: []outputInfo{
21714				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21715			},
21716		},
21717	},
21718	{
21719		name:   "MOVBUreg",
21720		argLen: 1,
21721		asm:    mips.AMOVBU,
21722		reg: regInfo{
21723			inputs: []inputInfo{
21724				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21725			},
21726			outputs: []outputInfo{
21727				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21728			},
21729		},
21730	},
21731	{
21732		name:   "MOVHreg",
21733		argLen: 1,
21734		asm:    mips.AMOVH,
21735		reg: regInfo{
21736			inputs: []inputInfo{
21737				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21738			},
21739			outputs: []outputInfo{
21740				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21741			},
21742		},
21743	},
21744	{
21745		name:   "MOVHUreg",
21746		argLen: 1,
21747		asm:    mips.AMOVHU,
21748		reg: regInfo{
21749			inputs: []inputInfo{
21750				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21751			},
21752			outputs: []outputInfo{
21753				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21754			},
21755		},
21756	},
21757	{
21758		name:   "MOVWreg",
21759		argLen: 1,
21760		asm:    mips.AMOVW,
21761		reg: regInfo{
21762			inputs: []inputInfo{
21763				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21764			},
21765			outputs: []outputInfo{
21766				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21767			},
21768		},
21769	},
21770	{
21771		name:   "MOVWUreg",
21772		argLen: 1,
21773		asm:    mips.AMOVWU,
21774		reg: regInfo{
21775			inputs: []inputInfo{
21776				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21777			},
21778			outputs: []outputInfo{
21779				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21780			},
21781		},
21782	},
21783	{
21784		name:   "MOVVreg",
21785		argLen: 1,
21786		asm:    mips.AMOVV,
21787		reg: regInfo{
21788			inputs: []inputInfo{
21789				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
21790			},
21791			outputs: []outputInfo{
21792				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21793			},
21794		},
21795	},
21796	{
21797		name:         "MOVVnop",
21798		argLen:       1,
21799		resultInArg0: true,
21800		reg: regInfo{
21801			inputs: []inputInfo{
21802				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21803			},
21804			outputs: []outputInfo{
21805				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21806			},
21807		},
21808	},
21809	{
21810		name:   "MOVWF",
21811		argLen: 1,
21812		asm:    mips.AMOVWF,
21813		reg: regInfo{
21814			inputs: []inputInfo{
21815				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21816			},
21817			outputs: []outputInfo{
21818				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21819			},
21820		},
21821	},
21822	{
21823		name:   "MOVWD",
21824		argLen: 1,
21825		asm:    mips.AMOVWD,
21826		reg: regInfo{
21827			inputs: []inputInfo{
21828				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21829			},
21830			outputs: []outputInfo{
21831				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21832			},
21833		},
21834	},
21835	{
21836		name:   "MOVVF",
21837		argLen: 1,
21838		asm:    mips.AMOVVF,
21839		reg: regInfo{
21840			inputs: []inputInfo{
21841				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21842			},
21843			outputs: []outputInfo{
21844				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21845			},
21846		},
21847	},
21848	{
21849		name:   "MOVVD",
21850		argLen: 1,
21851		asm:    mips.AMOVVD,
21852		reg: regInfo{
21853			inputs: []inputInfo{
21854				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21855			},
21856			outputs: []outputInfo{
21857				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21858			},
21859		},
21860	},
21861	{
21862		name:   "TRUNCFW",
21863		argLen: 1,
21864		asm:    mips.ATRUNCFW,
21865		reg: regInfo{
21866			inputs: []inputInfo{
21867				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21868			},
21869			outputs: []outputInfo{
21870				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21871			},
21872		},
21873	},
21874	{
21875		name:   "TRUNCDW",
21876		argLen: 1,
21877		asm:    mips.ATRUNCDW,
21878		reg: regInfo{
21879			inputs: []inputInfo{
21880				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21881			},
21882			outputs: []outputInfo{
21883				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21884			},
21885		},
21886	},
21887	{
21888		name:   "TRUNCFV",
21889		argLen: 1,
21890		asm:    mips.ATRUNCFV,
21891		reg: regInfo{
21892			inputs: []inputInfo{
21893				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21894			},
21895			outputs: []outputInfo{
21896				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21897			},
21898		},
21899	},
21900	{
21901		name:   "TRUNCDV",
21902		argLen: 1,
21903		asm:    mips.ATRUNCDV,
21904		reg: regInfo{
21905			inputs: []inputInfo{
21906				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21907			},
21908			outputs: []outputInfo{
21909				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21910			},
21911		},
21912	},
21913	{
21914		name:   "MOVFD",
21915		argLen: 1,
21916		asm:    mips.AMOVFD,
21917		reg: regInfo{
21918			inputs: []inputInfo{
21919				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21920			},
21921			outputs: []outputInfo{
21922				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21923			},
21924		},
21925	},
21926	{
21927		name:   "MOVDF",
21928		argLen: 1,
21929		asm:    mips.AMOVDF,
21930		reg: regInfo{
21931			inputs: []inputInfo{
21932				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21933			},
21934			outputs: []outputInfo{
21935				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21936			},
21937		},
21938	},
21939	{
21940		name:         "CALLstatic",
21941		auxType:      auxSymOff,
21942		argLen:       1,
21943		clobberFlags: true,
21944		call:         true,
21945		symEffect:    SymNone,
21946		reg: regInfo{
21947			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
21948		},
21949	},
21950	{
21951		name:         "CALLclosure",
21952		auxType:      auxInt64,
21953		argLen:       3,
21954		clobberFlags: true,
21955		call:         true,
21956		reg: regInfo{
21957			inputs: []inputInfo{
21958				{1, 4194304},   // R22
21959				{0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
21960			},
21961			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
21962		},
21963	},
21964	{
21965		name:         "CALLinter",
21966		auxType:      auxInt64,
21967		argLen:       2,
21968		clobberFlags: true,
21969		call:         true,
21970		reg: regInfo{
21971			inputs: []inputInfo{
21972				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21973			},
21974			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
21975		},
21976	},
21977	{
21978		name:           "DUFFZERO",
21979		auxType:        auxInt64,
21980		argLen:         2,
21981		faultOnNilArg0: true,
21982		reg: regInfo{
21983			inputs: []inputInfo{
21984				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
21985			},
21986			clobbers: 134217730, // R1 R31
21987		},
21988	},
21989	{
21990		name:           "DUFFCOPY",
21991		auxType:        auxInt64,
21992		argLen:         3,
21993		faultOnNilArg0: true,
21994		faultOnNilArg1: true,
21995		reg: regInfo{
21996			inputs: []inputInfo{
21997				{0, 4}, // R2
21998				{1, 2}, // R1
21999			},
22000			clobbers: 134217734, // R1 R2 R31
22001		},
22002	},
22003	{
22004		name:           "LoweredZero",
22005		auxType:        auxInt64,
22006		argLen:         3,
22007		clobberFlags:   true,
22008		faultOnNilArg0: true,
22009		reg: regInfo{
22010			inputs: []inputInfo{
22011				{0, 2},         // R1
22012				{1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22013			},
22014			clobbers: 2, // R1
22015		},
22016	},
22017	{
22018		name:           "LoweredMove",
22019		auxType:        auxInt64,
22020		argLen:         4,
22021		clobberFlags:   true,
22022		faultOnNilArg0: true,
22023		faultOnNilArg1: true,
22024		reg: regInfo{
22025			inputs: []inputInfo{
22026				{0, 4},         // R2
22027				{1, 2},         // R1
22028				{2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22029			},
22030			clobbers: 6, // R1 R2
22031		},
22032	},
22033	{
22034		name:           "LoweredAtomicLoad8",
22035		argLen:         2,
22036		faultOnNilArg0: true,
22037		reg: regInfo{
22038			inputs: []inputInfo{
22039				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22040			},
22041			outputs: []outputInfo{
22042				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22043			},
22044		},
22045	},
22046	{
22047		name:           "LoweredAtomicLoad32",
22048		argLen:         2,
22049		faultOnNilArg0: true,
22050		reg: regInfo{
22051			inputs: []inputInfo{
22052				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22053			},
22054			outputs: []outputInfo{
22055				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22056			},
22057		},
22058	},
22059	{
22060		name:           "LoweredAtomicLoad64",
22061		argLen:         2,
22062		faultOnNilArg0: true,
22063		reg: regInfo{
22064			inputs: []inputInfo{
22065				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22066			},
22067			outputs: []outputInfo{
22068				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22069			},
22070		},
22071	},
22072	{
22073		name:           "LoweredAtomicStore8",
22074		argLen:         3,
22075		faultOnNilArg0: true,
22076		hasSideEffects: true,
22077		reg: regInfo{
22078			inputs: []inputInfo{
22079				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22080				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22081			},
22082		},
22083	},
22084	{
22085		name:           "LoweredAtomicStore32",
22086		argLen:         3,
22087		faultOnNilArg0: true,
22088		hasSideEffects: true,
22089		reg: regInfo{
22090			inputs: []inputInfo{
22091				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22092				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22093			},
22094		},
22095	},
22096	{
22097		name:           "LoweredAtomicStore64",
22098		argLen:         3,
22099		faultOnNilArg0: true,
22100		hasSideEffects: true,
22101		reg: regInfo{
22102			inputs: []inputInfo{
22103				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22104				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22105			},
22106		},
22107	},
22108	{
22109		name:           "LoweredAtomicStorezero32",
22110		argLen:         2,
22111		faultOnNilArg0: true,
22112		hasSideEffects: true,
22113		reg: regInfo{
22114			inputs: []inputInfo{
22115				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22116			},
22117		},
22118	},
22119	{
22120		name:           "LoweredAtomicStorezero64",
22121		argLen:         2,
22122		faultOnNilArg0: true,
22123		hasSideEffects: true,
22124		reg: regInfo{
22125			inputs: []inputInfo{
22126				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22127			},
22128		},
22129	},
22130	{
22131		name:            "LoweredAtomicExchange32",
22132		argLen:          3,
22133		resultNotInArgs: true,
22134		faultOnNilArg0:  true,
22135		hasSideEffects:  true,
22136		unsafePoint:     true,
22137		reg: regInfo{
22138			inputs: []inputInfo{
22139				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22140				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22141			},
22142			outputs: []outputInfo{
22143				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22144			},
22145		},
22146	},
22147	{
22148		name:            "LoweredAtomicExchange64",
22149		argLen:          3,
22150		resultNotInArgs: true,
22151		faultOnNilArg0:  true,
22152		hasSideEffects:  true,
22153		unsafePoint:     true,
22154		reg: regInfo{
22155			inputs: []inputInfo{
22156				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22157				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22158			},
22159			outputs: []outputInfo{
22160				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22161			},
22162		},
22163	},
22164	{
22165		name:            "LoweredAtomicAdd32",
22166		argLen:          3,
22167		resultNotInArgs: true,
22168		faultOnNilArg0:  true,
22169		hasSideEffects:  true,
22170		unsafePoint:     true,
22171		reg: regInfo{
22172			inputs: []inputInfo{
22173				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22174				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22175			},
22176			outputs: []outputInfo{
22177				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22178			},
22179		},
22180	},
22181	{
22182		name:            "LoweredAtomicAdd64",
22183		argLen:          3,
22184		resultNotInArgs: true,
22185		faultOnNilArg0:  true,
22186		hasSideEffects:  true,
22187		unsafePoint:     true,
22188		reg: regInfo{
22189			inputs: []inputInfo{
22190				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22191				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22192			},
22193			outputs: []outputInfo{
22194				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22195			},
22196		},
22197	},
22198	{
22199		name:            "LoweredAtomicAddconst32",
22200		auxType:         auxInt32,
22201		argLen:          2,
22202		resultNotInArgs: true,
22203		faultOnNilArg0:  true,
22204		hasSideEffects:  true,
22205		unsafePoint:     true,
22206		reg: regInfo{
22207			inputs: []inputInfo{
22208				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22209			},
22210			outputs: []outputInfo{
22211				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22212			},
22213		},
22214	},
22215	{
22216		name:            "LoweredAtomicAddconst64",
22217		auxType:         auxInt64,
22218		argLen:          2,
22219		resultNotInArgs: true,
22220		faultOnNilArg0:  true,
22221		hasSideEffects:  true,
22222		unsafePoint:     true,
22223		reg: regInfo{
22224			inputs: []inputInfo{
22225				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22226			},
22227			outputs: []outputInfo{
22228				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22229			},
22230		},
22231	},
22232	{
22233		name:            "LoweredAtomicCas32",
22234		argLen:          4,
22235		resultNotInArgs: true,
22236		faultOnNilArg0:  true,
22237		hasSideEffects:  true,
22238		unsafePoint:     true,
22239		reg: regInfo{
22240			inputs: []inputInfo{
22241				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22242				{2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22243				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22244			},
22245			outputs: []outputInfo{
22246				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22247			},
22248		},
22249	},
22250	{
22251		name:            "LoweredAtomicCas64",
22252		argLen:          4,
22253		resultNotInArgs: true,
22254		faultOnNilArg0:  true,
22255		hasSideEffects:  true,
22256		unsafePoint:     true,
22257		reg: regInfo{
22258			inputs: []inputInfo{
22259				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22260				{2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22261				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
22262			},
22263			outputs: []outputInfo{
22264				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22265			},
22266		},
22267	},
22268	{
22269		name:           "LoweredNilCheck",
22270		argLen:         2,
22271		nilCheck:       true,
22272		faultOnNilArg0: true,
22273		reg: regInfo{
22274			inputs: []inputInfo{
22275				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
22276			},
22277		},
22278	},
22279	{
22280		name:   "FPFlagTrue",
22281		argLen: 1,
22282		reg: regInfo{
22283			outputs: []outputInfo{
22284				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22285			},
22286		},
22287	},
22288	{
22289		name:   "FPFlagFalse",
22290		argLen: 1,
22291		reg: regInfo{
22292			outputs: []outputInfo{
22293				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22294			},
22295		},
22296	},
22297	{
22298		name:      "LoweredGetClosurePtr",
22299		argLen:    0,
22300		zeroWidth: true,
22301		reg: regInfo{
22302			outputs: []outputInfo{
22303				{0, 4194304}, // R22
22304			},
22305		},
22306	},
22307	{
22308		name:              "LoweredGetCallerSP",
22309		argLen:            0,
22310		rematerializeable: true,
22311		reg: regInfo{
22312			outputs: []outputInfo{
22313				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22314			},
22315		},
22316	},
22317	{
22318		name:              "LoweredGetCallerPC",
22319		argLen:            0,
22320		rematerializeable: true,
22321		reg: regInfo{
22322			outputs: []outputInfo{
22323				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
22324			},
22325		},
22326	},
22327	{
22328		name:         "LoweredWB",
22329		auxType:      auxSym,
22330		argLen:       3,
22331		clobberFlags: true,
22332		symEffect:    SymNone,
22333		reg: regInfo{
22334			inputs: []inputInfo{
22335				{0, 1048576}, // R20
22336				{1, 2097152}, // R21
22337			},
22338			clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
22339		},
22340	},
22341	{
22342		name:    "LoweredPanicBoundsA",
22343		auxType: auxInt64,
22344		argLen:  3,
22345		reg: regInfo{
22346			inputs: []inputInfo{
22347				{0, 8},  // R3
22348				{1, 16}, // R4
22349			},
22350		},
22351	},
22352	{
22353		name:    "LoweredPanicBoundsB",
22354		auxType: auxInt64,
22355		argLen:  3,
22356		reg: regInfo{
22357			inputs: []inputInfo{
22358				{0, 4}, // R2
22359				{1, 8}, // R3
22360			},
22361		},
22362	},
22363	{
22364		name:    "LoweredPanicBoundsC",
22365		auxType: auxInt64,
22366		argLen:  3,
22367		reg: regInfo{
22368			inputs: []inputInfo{
22369				{0, 2}, // R1
22370				{1, 4}, // R2
22371			},
22372		},
22373	},
22374
22375	{
22376		name:        "ADD",
22377		argLen:      2,
22378		commutative: true,
22379		asm:         ppc64.AADD,
22380		reg: regInfo{
22381			inputs: []inputInfo{
22382				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22383				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22384			},
22385			outputs: []outputInfo{
22386				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22387			},
22388		},
22389	},
22390	{
22391		name:    "ADDconst",
22392		auxType: auxInt64,
22393		argLen:  1,
22394		asm:     ppc64.AADD,
22395		reg: regInfo{
22396			inputs: []inputInfo{
22397				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22398			},
22399			outputs: []outputInfo{
22400				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22401			},
22402		},
22403	},
22404	{
22405		name:        "FADD",
22406		argLen:      2,
22407		commutative: true,
22408		asm:         ppc64.AFADD,
22409		reg: regInfo{
22410			inputs: []inputInfo{
22411				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22412				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22413			},
22414			outputs: []outputInfo{
22415				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22416			},
22417		},
22418	},
22419	{
22420		name:        "FADDS",
22421		argLen:      2,
22422		commutative: true,
22423		asm:         ppc64.AFADDS,
22424		reg: regInfo{
22425			inputs: []inputInfo{
22426				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22427				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22428			},
22429			outputs: []outputInfo{
22430				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22431			},
22432		},
22433	},
22434	{
22435		name:   "SUB",
22436		argLen: 2,
22437		asm:    ppc64.ASUB,
22438		reg: regInfo{
22439			inputs: []inputInfo{
22440				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22441				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22442			},
22443			outputs: []outputInfo{
22444				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22445			},
22446		},
22447	},
22448	{
22449		name:   "FSUB",
22450		argLen: 2,
22451		asm:    ppc64.AFSUB,
22452		reg: regInfo{
22453			inputs: []inputInfo{
22454				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22455				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22456			},
22457			outputs: []outputInfo{
22458				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22459			},
22460		},
22461	},
22462	{
22463		name:   "FSUBS",
22464		argLen: 2,
22465		asm:    ppc64.AFSUBS,
22466		reg: regInfo{
22467			inputs: []inputInfo{
22468				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22469				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22470			},
22471			outputs: []outputInfo{
22472				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22473			},
22474		},
22475	},
22476	{
22477		name:        "MULLD",
22478		argLen:      2,
22479		commutative: true,
22480		asm:         ppc64.AMULLD,
22481		reg: regInfo{
22482			inputs: []inputInfo{
22483				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22484				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22485			},
22486			outputs: []outputInfo{
22487				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22488			},
22489		},
22490	},
22491	{
22492		name:        "MULLW",
22493		argLen:      2,
22494		commutative: true,
22495		asm:         ppc64.AMULLW,
22496		reg: regInfo{
22497			inputs: []inputInfo{
22498				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22499				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22500			},
22501			outputs: []outputInfo{
22502				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22503			},
22504		},
22505	},
22506	{
22507		name:        "MULHD",
22508		argLen:      2,
22509		commutative: true,
22510		asm:         ppc64.AMULHD,
22511		reg: regInfo{
22512			inputs: []inputInfo{
22513				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22514				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22515			},
22516			outputs: []outputInfo{
22517				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22518			},
22519		},
22520	},
22521	{
22522		name:        "MULHW",
22523		argLen:      2,
22524		commutative: true,
22525		asm:         ppc64.AMULHW,
22526		reg: regInfo{
22527			inputs: []inputInfo{
22528				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22529				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22530			},
22531			outputs: []outputInfo{
22532				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22533			},
22534		},
22535	},
22536	{
22537		name:        "MULHDU",
22538		argLen:      2,
22539		commutative: true,
22540		asm:         ppc64.AMULHDU,
22541		reg: regInfo{
22542			inputs: []inputInfo{
22543				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22544				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22545			},
22546			outputs: []outputInfo{
22547				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22548			},
22549		},
22550	},
22551	{
22552		name:        "MULHWU",
22553		argLen:      2,
22554		commutative: true,
22555		asm:         ppc64.AMULHWU,
22556		reg: regInfo{
22557			inputs: []inputInfo{
22558				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22559				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22560			},
22561			outputs: []outputInfo{
22562				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22563			},
22564		},
22565	},
22566	{
22567		name:            "LoweredMuluhilo",
22568		argLen:          2,
22569		resultNotInArgs: true,
22570		reg: regInfo{
22571			inputs: []inputInfo{
22572				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22573				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22574			},
22575			outputs: []outputInfo{
22576				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22577				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22578			},
22579		},
22580	},
22581	{
22582		name:        "FMUL",
22583		argLen:      2,
22584		commutative: true,
22585		asm:         ppc64.AFMUL,
22586		reg: regInfo{
22587			inputs: []inputInfo{
22588				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22589				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22590			},
22591			outputs: []outputInfo{
22592				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22593			},
22594		},
22595	},
22596	{
22597		name:        "FMULS",
22598		argLen:      2,
22599		commutative: true,
22600		asm:         ppc64.AFMULS,
22601		reg: regInfo{
22602			inputs: []inputInfo{
22603				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22604				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22605			},
22606			outputs: []outputInfo{
22607				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22608			},
22609		},
22610	},
22611	{
22612		name:   "FMADD",
22613		argLen: 3,
22614		asm:    ppc64.AFMADD,
22615		reg: regInfo{
22616			inputs: []inputInfo{
22617				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22618				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22619				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22620			},
22621			outputs: []outputInfo{
22622				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22623			},
22624		},
22625	},
22626	{
22627		name:   "FMADDS",
22628		argLen: 3,
22629		asm:    ppc64.AFMADDS,
22630		reg: regInfo{
22631			inputs: []inputInfo{
22632				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22633				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22634				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22635			},
22636			outputs: []outputInfo{
22637				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22638			},
22639		},
22640	},
22641	{
22642		name:   "FMSUB",
22643		argLen: 3,
22644		asm:    ppc64.AFMSUB,
22645		reg: regInfo{
22646			inputs: []inputInfo{
22647				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22648				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22649				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22650			},
22651			outputs: []outputInfo{
22652				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22653			},
22654		},
22655	},
22656	{
22657		name:   "FMSUBS",
22658		argLen: 3,
22659		asm:    ppc64.AFMSUBS,
22660		reg: regInfo{
22661			inputs: []inputInfo{
22662				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22663				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22664				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22665			},
22666			outputs: []outputInfo{
22667				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
22668			},
22669		},
22670	},
22671	{
22672		name:   "SRAD",
22673		argLen: 2,
22674		asm:    ppc64.ASRAD,
22675		reg: regInfo{
22676			inputs: []inputInfo{
22677				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22678				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22679			},
22680			outputs: []outputInfo{
22681				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22682			},
22683		},
22684	},
22685	{
22686		name:   "SRAW",
22687		argLen: 2,
22688		asm:    ppc64.ASRAW,
22689		reg: regInfo{
22690			inputs: []inputInfo{
22691				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22692				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22693			},
22694			outputs: []outputInfo{
22695				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22696			},
22697		},
22698	},
22699	{
22700		name:   "SRD",
22701		argLen: 2,
22702		asm:    ppc64.ASRD,
22703		reg: regInfo{
22704			inputs: []inputInfo{
22705				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22706				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22707			},
22708			outputs: []outputInfo{
22709				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22710			},
22711		},
22712	},
22713	{
22714		name:   "SRW",
22715		argLen: 2,
22716		asm:    ppc64.ASRW,
22717		reg: regInfo{
22718			inputs: []inputInfo{
22719				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22720				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22721			},
22722			outputs: []outputInfo{
22723				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22724			},
22725		},
22726	},
22727	{
22728		name:   "SLD",
22729		argLen: 2,
22730		asm:    ppc64.ASLD,
22731		reg: regInfo{
22732			inputs: []inputInfo{
22733				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22734				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22735			},
22736			outputs: []outputInfo{
22737				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22738			},
22739		},
22740	},
22741	{
22742		name:   "SLW",
22743		argLen: 2,
22744		asm:    ppc64.ASLW,
22745		reg: regInfo{
22746			inputs: []inputInfo{
22747				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22748				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22749			},
22750			outputs: []outputInfo{
22751				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22752			},
22753		},
22754	},
22755	{
22756		name:   "ROTL",
22757		argLen: 2,
22758		asm:    ppc64.AROTL,
22759		reg: regInfo{
22760			inputs: []inputInfo{
22761				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22762				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22763			},
22764			outputs: []outputInfo{
22765				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22766			},
22767		},
22768	},
22769	{
22770		name:   "ROTLW",
22771		argLen: 2,
22772		asm:    ppc64.AROTLW,
22773		reg: regInfo{
22774			inputs: []inputInfo{
22775				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22776				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22777			},
22778			outputs: []outputInfo{
22779				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22780			},
22781		},
22782	},
22783	{
22784		name:            "LoweredAdd64Carry",
22785		argLen:          3,
22786		resultNotInArgs: true,
22787		reg: regInfo{
22788			inputs: []inputInfo{
22789				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22790				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22791				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22792			},
22793			outputs: []outputInfo{
22794				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22795				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22796			},
22797		},
22798	},
22799	{
22800		name:    "ADDconstForCarry",
22801		auxType: auxInt16,
22802		argLen:  1,
22803		asm:     ppc64.AADDC,
22804		reg: regInfo{
22805			inputs: []inputInfo{
22806				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22807			},
22808			clobbers: 2147483648, // R31
22809		},
22810	},
22811	{
22812		name:   "MaskIfNotCarry",
22813		argLen: 1,
22814		asm:    ppc64.AADDME,
22815		reg: regInfo{
22816			outputs: []outputInfo{
22817				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22818			},
22819		},
22820	},
22821	{
22822		name:    "SRADconst",
22823		auxType: auxInt64,
22824		argLen:  1,
22825		asm:     ppc64.ASRAD,
22826		reg: regInfo{
22827			inputs: []inputInfo{
22828				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22829			},
22830			outputs: []outputInfo{
22831				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22832			},
22833		},
22834	},
22835	{
22836		name:    "SRAWconst",
22837		auxType: auxInt64,
22838		argLen:  1,
22839		asm:     ppc64.ASRAW,
22840		reg: regInfo{
22841			inputs: []inputInfo{
22842				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22843			},
22844			outputs: []outputInfo{
22845				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22846			},
22847		},
22848	},
22849	{
22850		name:    "SRDconst",
22851		auxType: auxInt64,
22852		argLen:  1,
22853		asm:     ppc64.ASRD,
22854		reg: regInfo{
22855			inputs: []inputInfo{
22856				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22857			},
22858			outputs: []outputInfo{
22859				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22860			},
22861		},
22862	},
22863	{
22864		name:    "SRWconst",
22865		auxType: auxInt64,
22866		argLen:  1,
22867		asm:     ppc64.ASRW,
22868		reg: regInfo{
22869			inputs: []inputInfo{
22870				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22871			},
22872			outputs: []outputInfo{
22873				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22874			},
22875		},
22876	},
22877	{
22878		name:    "SLDconst",
22879		auxType: auxInt64,
22880		argLen:  1,
22881		asm:     ppc64.ASLD,
22882		reg: regInfo{
22883			inputs: []inputInfo{
22884				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22885			},
22886			outputs: []outputInfo{
22887				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22888			},
22889		},
22890	},
22891	{
22892		name:    "SLWconst",
22893		auxType: auxInt64,
22894		argLen:  1,
22895		asm:     ppc64.ASLW,
22896		reg: regInfo{
22897			inputs: []inputInfo{
22898				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22899			},
22900			outputs: []outputInfo{
22901				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22902			},
22903		},
22904	},
22905	{
22906		name:    "ROTLconst",
22907		auxType: auxInt64,
22908		argLen:  1,
22909		asm:     ppc64.AROTL,
22910		reg: regInfo{
22911			inputs: []inputInfo{
22912				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22913			},
22914			outputs: []outputInfo{
22915				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22916			},
22917		},
22918	},
22919	{
22920		name:    "ROTLWconst",
22921		auxType: auxInt64,
22922		argLen:  1,
22923		asm:     ppc64.AROTLW,
22924		reg: regInfo{
22925			inputs: []inputInfo{
22926				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22927			},
22928			outputs: []outputInfo{
22929				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22930			},
22931		},
22932	},
22933	{
22934		name:         "CNTLZD",
22935		argLen:       1,
22936		clobberFlags: true,
22937		asm:          ppc64.ACNTLZD,
22938		reg: regInfo{
22939			inputs: []inputInfo{
22940				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22941			},
22942			outputs: []outputInfo{
22943				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22944			},
22945		},
22946	},
22947	{
22948		name:         "CNTLZW",
22949		argLen:       1,
22950		clobberFlags: true,
22951		asm:          ppc64.ACNTLZW,
22952		reg: regInfo{
22953			inputs: []inputInfo{
22954				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22955			},
22956			outputs: []outputInfo{
22957				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22958			},
22959		},
22960	},
22961	{
22962		name:   "CNTTZD",
22963		argLen: 1,
22964		asm:    ppc64.ACNTTZD,
22965		reg: regInfo{
22966			inputs: []inputInfo{
22967				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22968			},
22969			outputs: []outputInfo{
22970				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22971			},
22972		},
22973	},
22974	{
22975		name:   "CNTTZW",
22976		argLen: 1,
22977		asm:    ppc64.ACNTTZW,
22978		reg: regInfo{
22979			inputs: []inputInfo{
22980				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22981			},
22982			outputs: []outputInfo{
22983				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22984			},
22985		},
22986	},
22987	{
22988		name:   "POPCNTD",
22989		argLen: 1,
22990		asm:    ppc64.APOPCNTD,
22991		reg: regInfo{
22992			inputs: []inputInfo{
22993				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22994			},
22995			outputs: []outputInfo{
22996				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
22997			},
22998		},
22999	},
23000	{
23001		name:   "POPCNTW",
23002		argLen: 1,
23003		asm:    ppc64.APOPCNTW,
23004		reg: regInfo{
23005			inputs: []inputInfo{
23006				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23007			},
23008			outputs: []outputInfo{
23009				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23010			},
23011		},
23012	},
23013	{
23014		name:   "POPCNTB",
23015		argLen: 1,
23016		asm:    ppc64.APOPCNTB,
23017		reg: regInfo{
23018			inputs: []inputInfo{
23019				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23020			},
23021			outputs: []outputInfo{
23022				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23023			},
23024		},
23025	},
23026	{
23027		name:   "FDIV",
23028		argLen: 2,
23029		asm:    ppc64.AFDIV,
23030		reg: regInfo{
23031			inputs: []inputInfo{
23032				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23033				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23034			},
23035			outputs: []outputInfo{
23036				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23037			},
23038		},
23039	},
23040	{
23041		name:   "FDIVS",
23042		argLen: 2,
23043		asm:    ppc64.AFDIVS,
23044		reg: regInfo{
23045			inputs: []inputInfo{
23046				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23047				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23048			},
23049			outputs: []outputInfo{
23050				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23051			},
23052		},
23053	},
23054	{
23055		name:   "DIVD",
23056		argLen: 2,
23057		asm:    ppc64.ADIVD,
23058		reg: regInfo{
23059			inputs: []inputInfo{
23060				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23061				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23062			},
23063			outputs: []outputInfo{
23064				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23065			},
23066		},
23067	},
23068	{
23069		name:   "DIVW",
23070		argLen: 2,
23071		asm:    ppc64.ADIVW,
23072		reg: regInfo{
23073			inputs: []inputInfo{
23074				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23075				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23076			},
23077			outputs: []outputInfo{
23078				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23079			},
23080		},
23081	},
23082	{
23083		name:   "DIVDU",
23084		argLen: 2,
23085		asm:    ppc64.ADIVDU,
23086		reg: regInfo{
23087			inputs: []inputInfo{
23088				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23089				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23090			},
23091			outputs: []outputInfo{
23092				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23093			},
23094		},
23095	},
23096	{
23097		name:   "DIVWU",
23098		argLen: 2,
23099		asm:    ppc64.ADIVWU,
23100		reg: regInfo{
23101			inputs: []inputInfo{
23102				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23103				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23104			},
23105			outputs: []outputInfo{
23106				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23107			},
23108		},
23109	},
23110	{
23111		name:   "FCTIDZ",
23112		argLen: 1,
23113		asm:    ppc64.AFCTIDZ,
23114		reg: regInfo{
23115			inputs: []inputInfo{
23116				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23117			},
23118			outputs: []outputInfo{
23119				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23120			},
23121		},
23122	},
23123	{
23124		name:   "FCTIWZ",
23125		argLen: 1,
23126		asm:    ppc64.AFCTIWZ,
23127		reg: regInfo{
23128			inputs: []inputInfo{
23129				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23130			},
23131			outputs: []outputInfo{
23132				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23133			},
23134		},
23135	},
23136	{
23137		name:   "FCFID",
23138		argLen: 1,
23139		asm:    ppc64.AFCFID,
23140		reg: regInfo{
23141			inputs: []inputInfo{
23142				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23143			},
23144			outputs: []outputInfo{
23145				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23146			},
23147		},
23148	},
23149	{
23150		name:   "FCFIDS",
23151		argLen: 1,
23152		asm:    ppc64.AFCFIDS,
23153		reg: regInfo{
23154			inputs: []inputInfo{
23155				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23156			},
23157			outputs: []outputInfo{
23158				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23159			},
23160		},
23161	},
23162	{
23163		name:   "FRSP",
23164		argLen: 1,
23165		asm:    ppc64.AFRSP,
23166		reg: regInfo{
23167			inputs: []inputInfo{
23168				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23169			},
23170			outputs: []outputInfo{
23171				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23172			},
23173		},
23174	},
23175	{
23176		name:   "MFVSRD",
23177		argLen: 1,
23178		asm:    ppc64.AMFVSRD,
23179		reg: regInfo{
23180			inputs: []inputInfo{
23181				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23182			},
23183			outputs: []outputInfo{
23184				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23185			},
23186		},
23187	},
23188	{
23189		name:   "MTVSRD",
23190		argLen: 1,
23191		asm:    ppc64.AMTVSRD,
23192		reg: regInfo{
23193			inputs: []inputInfo{
23194				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23195			},
23196			outputs: []outputInfo{
23197				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23198			},
23199		},
23200	},
23201	{
23202		name:        "AND",
23203		argLen:      2,
23204		commutative: true,
23205		asm:         ppc64.AAND,
23206		reg: regInfo{
23207			inputs: []inputInfo{
23208				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23209				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23210			},
23211			outputs: []outputInfo{
23212				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23213			},
23214		},
23215	},
23216	{
23217		name:   "ANDN",
23218		argLen: 2,
23219		asm:    ppc64.AANDN,
23220		reg: regInfo{
23221			inputs: []inputInfo{
23222				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23223				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23224			},
23225			outputs: []outputInfo{
23226				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23227			},
23228		},
23229	},
23230	{
23231		name:        "ANDCC",
23232		argLen:      2,
23233		commutative: true,
23234		asm:         ppc64.AANDCC,
23235		reg: regInfo{
23236			inputs: []inputInfo{
23237				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23238				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23239			},
23240		},
23241	},
23242	{
23243		name:        "OR",
23244		argLen:      2,
23245		commutative: true,
23246		asm:         ppc64.AOR,
23247		reg: regInfo{
23248			inputs: []inputInfo{
23249				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23250				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23251			},
23252			outputs: []outputInfo{
23253				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23254			},
23255		},
23256	},
23257	{
23258		name:   "ORN",
23259		argLen: 2,
23260		asm:    ppc64.AORN,
23261		reg: regInfo{
23262			inputs: []inputInfo{
23263				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23264				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23265			},
23266			outputs: []outputInfo{
23267				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23268			},
23269		},
23270	},
23271	{
23272		name:        "ORCC",
23273		argLen:      2,
23274		commutative: true,
23275		asm:         ppc64.AORCC,
23276		reg: regInfo{
23277			inputs: []inputInfo{
23278				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23279				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23280			},
23281		},
23282	},
23283	{
23284		name:        "NOR",
23285		argLen:      2,
23286		commutative: true,
23287		asm:         ppc64.ANOR,
23288		reg: regInfo{
23289			inputs: []inputInfo{
23290				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23291				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23292			},
23293			outputs: []outputInfo{
23294				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23295			},
23296		},
23297	},
23298	{
23299		name:        "XOR",
23300		argLen:      2,
23301		commutative: true,
23302		asm:         ppc64.AXOR,
23303		reg: regInfo{
23304			inputs: []inputInfo{
23305				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23306				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23307			},
23308			outputs: []outputInfo{
23309				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23310			},
23311		},
23312	},
23313	{
23314		name:        "XORCC",
23315		argLen:      2,
23316		commutative: true,
23317		asm:         ppc64.AXORCC,
23318		reg: regInfo{
23319			inputs: []inputInfo{
23320				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23321				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23322			},
23323		},
23324	},
23325	{
23326		name:        "EQV",
23327		argLen:      2,
23328		commutative: true,
23329		asm:         ppc64.AEQV,
23330		reg: regInfo{
23331			inputs: []inputInfo{
23332				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23333				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23334			},
23335			outputs: []outputInfo{
23336				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23337			},
23338		},
23339	},
23340	{
23341		name:   "NEG",
23342		argLen: 1,
23343		asm:    ppc64.ANEG,
23344		reg: regInfo{
23345			inputs: []inputInfo{
23346				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23347			},
23348			outputs: []outputInfo{
23349				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23350			},
23351		},
23352	},
23353	{
23354		name:   "FNEG",
23355		argLen: 1,
23356		asm:    ppc64.AFNEG,
23357		reg: regInfo{
23358			inputs: []inputInfo{
23359				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23360			},
23361			outputs: []outputInfo{
23362				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23363			},
23364		},
23365	},
23366	{
23367		name:   "FSQRT",
23368		argLen: 1,
23369		asm:    ppc64.AFSQRT,
23370		reg: regInfo{
23371			inputs: []inputInfo{
23372				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23373			},
23374			outputs: []outputInfo{
23375				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23376			},
23377		},
23378	},
23379	{
23380		name:   "FSQRTS",
23381		argLen: 1,
23382		asm:    ppc64.AFSQRTS,
23383		reg: regInfo{
23384			inputs: []inputInfo{
23385				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23386			},
23387			outputs: []outputInfo{
23388				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23389			},
23390		},
23391	},
23392	{
23393		name:   "FFLOOR",
23394		argLen: 1,
23395		asm:    ppc64.AFRIM,
23396		reg: regInfo{
23397			inputs: []inputInfo{
23398				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23399			},
23400			outputs: []outputInfo{
23401				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23402			},
23403		},
23404	},
23405	{
23406		name:   "FCEIL",
23407		argLen: 1,
23408		asm:    ppc64.AFRIP,
23409		reg: regInfo{
23410			inputs: []inputInfo{
23411				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23412			},
23413			outputs: []outputInfo{
23414				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23415			},
23416		},
23417	},
23418	{
23419		name:   "FTRUNC",
23420		argLen: 1,
23421		asm:    ppc64.AFRIZ,
23422		reg: regInfo{
23423			inputs: []inputInfo{
23424				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23425			},
23426			outputs: []outputInfo{
23427				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23428			},
23429		},
23430	},
23431	{
23432		name:   "FROUND",
23433		argLen: 1,
23434		asm:    ppc64.AFRIN,
23435		reg: regInfo{
23436			inputs: []inputInfo{
23437				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23438			},
23439			outputs: []outputInfo{
23440				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23441			},
23442		},
23443	},
23444	{
23445		name:   "FABS",
23446		argLen: 1,
23447		asm:    ppc64.AFABS,
23448		reg: regInfo{
23449			inputs: []inputInfo{
23450				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23451			},
23452			outputs: []outputInfo{
23453				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23454			},
23455		},
23456	},
23457	{
23458		name:   "FNABS",
23459		argLen: 1,
23460		asm:    ppc64.AFNABS,
23461		reg: regInfo{
23462			inputs: []inputInfo{
23463				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23464			},
23465			outputs: []outputInfo{
23466				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23467			},
23468		},
23469	},
23470	{
23471		name:   "FCPSGN",
23472		argLen: 2,
23473		asm:    ppc64.AFCPSGN,
23474		reg: regInfo{
23475			inputs: []inputInfo{
23476				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23477				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23478			},
23479			outputs: []outputInfo{
23480				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23481			},
23482		},
23483	},
23484	{
23485		name:    "ORconst",
23486		auxType: auxInt64,
23487		argLen:  1,
23488		asm:     ppc64.AOR,
23489		reg: regInfo{
23490			inputs: []inputInfo{
23491				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23492			},
23493			outputs: []outputInfo{
23494				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23495			},
23496		},
23497	},
23498	{
23499		name:    "XORconst",
23500		auxType: auxInt64,
23501		argLen:  1,
23502		asm:     ppc64.AXOR,
23503		reg: regInfo{
23504			inputs: []inputInfo{
23505				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23506			},
23507			outputs: []outputInfo{
23508				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23509			},
23510		},
23511	},
23512	{
23513		name:         "ANDconst",
23514		auxType:      auxInt64,
23515		argLen:       1,
23516		clobberFlags: true,
23517		asm:          ppc64.AANDCC,
23518		reg: regInfo{
23519			inputs: []inputInfo{
23520				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23521			},
23522			outputs: []outputInfo{
23523				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23524			},
23525		},
23526	},
23527	{
23528		name:    "ANDCCconst",
23529		auxType: auxInt64,
23530		argLen:  1,
23531		asm:     ppc64.AANDCC,
23532		reg: regInfo{
23533			inputs: []inputInfo{
23534				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23535			},
23536		},
23537	},
23538	{
23539		name:   "MOVBreg",
23540		argLen: 1,
23541		asm:    ppc64.AMOVB,
23542		reg: regInfo{
23543			inputs: []inputInfo{
23544				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23545			},
23546			outputs: []outputInfo{
23547				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23548			},
23549		},
23550	},
23551	{
23552		name:   "MOVBZreg",
23553		argLen: 1,
23554		asm:    ppc64.AMOVBZ,
23555		reg: regInfo{
23556			inputs: []inputInfo{
23557				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23558			},
23559			outputs: []outputInfo{
23560				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23561			},
23562		},
23563	},
23564	{
23565		name:   "MOVHreg",
23566		argLen: 1,
23567		asm:    ppc64.AMOVH,
23568		reg: regInfo{
23569			inputs: []inputInfo{
23570				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23571			},
23572			outputs: []outputInfo{
23573				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23574			},
23575		},
23576	},
23577	{
23578		name:   "MOVHZreg",
23579		argLen: 1,
23580		asm:    ppc64.AMOVHZ,
23581		reg: regInfo{
23582			inputs: []inputInfo{
23583				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23584			},
23585			outputs: []outputInfo{
23586				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23587			},
23588		},
23589	},
23590	{
23591		name:   "MOVWreg",
23592		argLen: 1,
23593		asm:    ppc64.AMOVW,
23594		reg: regInfo{
23595			inputs: []inputInfo{
23596				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23597			},
23598			outputs: []outputInfo{
23599				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23600			},
23601		},
23602	},
23603	{
23604		name:   "MOVWZreg",
23605		argLen: 1,
23606		asm:    ppc64.AMOVWZ,
23607		reg: regInfo{
23608			inputs: []inputInfo{
23609				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23610			},
23611			outputs: []outputInfo{
23612				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23613			},
23614		},
23615	},
23616	{
23617		name:           "MOVBZload",
23618		auxType:        auxSymOff,
23619		argLen:         2,
23620		faultOnNilArg0: true,
23621		symEffect:      SymRead,
23622		asm:            ppc64.AMOVBZ,
23623		reg: regInfo{
23624			inputs: []inputInfo{
23625				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23626			},
23627			outputs: []outputInfo{
23628				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23629			},
23630		},
23631	},
23632	{
23633		name:           "MOVHload",
23634		auxType:        auxSymOff,
23635		argLen:         2,
23636		faultOnNilArg0: true,
23637		symEffect:      SymRead,
23638		asm:            ppc64.AMOVH,
23639		reg: regInfo{
23640			inputs: []inputInfo{
23641				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23642			},
23643			outputs: []outputInfo{
23644				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23645			},
23646		},
23647	},
23648	{
23649		name:           "MOVHZload",
23650		auxType:        auxSymOff,
23651		argLen:         2,
23652		faultOnNilArg0: true,
23653		symEffect:      SymRead,
23654		asm:            ppc64.AMOVHZ,
23655		reg: regInfo{
23656			inputs: []inputInfo{
23657				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23658			},
23659			outputs: []outputInfo{
23660				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23661			},
23662		},
23663	},
23664	{
23665		name:           "MOVWload",
23666		auxType:        auxSymOff,
23667		argLen:         2,
23668		faultOnNilArg0: true,
23669		symEffect:      SymRead,
23670		asm:            ppc64.AMOVW,
23671		reg: regInfo{
23672			inputs: []inputInfo{
23673				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23674			},
23675			outputs: []outputInfo{
23676				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23677			},
23678		},
23679	},
23680	{
23681		name:           "MOVWZload",
23682		auxType:        auxSymOff,
23683		argLen:         2,
23684		faultOnNilArg0: true,
23685		symEffect:      SymRead,
23686		asm:            ppc64.AMOVWZ,
23687		reg: regInfo{
23688			inputs: []inputInfo{
23689				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23690			},
23691			outputs: []outputInfo{
23692				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23693			},
23694		},
23695	},
23696	{
23697		name:           "MOVDload",
23698		auxType:        auxSymOff,
23699		argLen:         2,
23700		faultOnNilArg0: true,
23701		symEffect:      SymRead,
23702		asm:            ppc64.AMOVD,
23703		reg: regInfo{
23704			inputs: []inputInfo{
23705				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23706			},
23707			outputs: []outputInfo{
23708				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23709			},
23710		},
23711	},
23712	{
23713		name:           "MOVDBRload",
23714		auxType:        auxSymOff,
23715		argLen:         2,
23716		faultOnNilArg0: true,
23717		symEffect:      SymRead,
23718		asm:            ppc64.AMOVDBR,
23719		reg: regInfo{
23720			inputs: []inputInfo{
23721				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23722			},
23723			outputs: []outputInfo{
23724				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23725			},
23726		},
23727	},
23728	{
23729		name:           "MOVWBRload",
23730		auxType:        auxSymOff,
23731		argLen:         2,
23732		faultOnNilArg0: true,
23733		symEffect:      SymRead,
23734		asm:            ppc64.AMOVWBR,
23735		reg: regInfo{
23736			inputs: []inputInfo{
23737				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23738			},
23739			outputs: []outputInfo{
23740				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23741			},
23742		},
23743	},
23744	{
23745		name:           "MOVHBRload",
23746		auxType:        auxSymOff,
23747		argLen:         2,
23748		faultOnNilArg0: true,
23749		symEffect:      SymRead,
23750		asm:            ppc64.AMOVHBR,
23751		reg: regInfo{
23752			inputs: []inputInfo{
23753				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23754			},
23755			outputs: []outputInfo{
23756				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23757			},
23758		},
23759	},
23760	{
23761		name:           "MOVBZloadidx",
23762		auxType:        auxSymOff,
23763		argLen:         3,
23764		faultOnNilArg0: true,
23765		symEffect:      SymRead,
23766		asm:            ppc64.AMOVBZ,
23767		reg: regInfo{
23768			inputs: []inputInfo{
23769				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23770				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23771			},
23772			outputs: []outputInfo{
23773				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23774			},
23775		},
23776	},
23777	{
23778		name:           "MOVHloadidx",
23779		auxType:        auxSymOff,
23780		argLen:         3,
23781		faultOnNilArg0: true,
23782		symEffect:      SymRead,
23783		asm:            ppc64.AMOVH,
23784		reg: regInfo{
23785			inputs: []inputInfo{
23786				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23787				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23788			},
23789			outputs: []outputInfo{
23790				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23791			},
23792		},
23793	},
23794	{
23795		name:           "MOVHZloadidx",
23796		auxType:        auxSymOff,
23797		argLen:         3,
23798		faultOnNilArg0: true,
23799		symEffect:      SymRead,
23800		asm:            ppc64.AMOVHZ,
23801		reg: regInfo{
23802			inputs: []inputInfo{
23803				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23804				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23805			},
23806			outputs: []outputInfo{
23807				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23808			},
23809		},
23810	},
23811	{
23812		name:           "MOVWloadidx",
23813		auxType:        auxSymOff,
23814		argLen:         3,
23815		faultOnNilArg0: true,
23816		symEffect:      SymRead,
23817		asm:            ppc64.AMOVW,
23818		reg: regInfo{
23819			inputs: []inputInfo{
23820				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23821				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23822			},
23823			outputs: []outputInfo{
23824				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23825			},
23826		},
23827	},
23828	{
23829		name:           "MOVWZloadidx",
23830		auxType:        auxSymOff,
23831		argLen:         3,
23832		faultOnNilArg0: true,
23833		symEffect:      SymRead,
23834		asm:            ppc64.AMOVWZ,
23835		reg: regInfo{
23836			inputs: []inputInfo{
23837				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23838				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23839			},
23840			outputs: []outputInfo{
23841				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23842			},
23843		},
23844	},
23845	{
23846		name:           "MOVDloadidx",
23847		auxType:        auxSymOff,
23848		argLen:         3,
23849		faultOnNilArg0: true,
23850		symEffect:      SymRead,
23851		asm:            ppc64.AMOVD,
23852		reg: regInfo{
23853			inputs: []inputInfo{
23854				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23855				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23856			},
23857			outputs: []outputInfo{
23858				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23859			},
23860		},
23861	},
23862	{
23863		name:           "MOVHBRloadidx",
23864		auxType:        auxSymOff,
23865		argLen:         3,
23866		faultOnNilArg0: true,
23867		symEffect:      SymRead,
23868		asm:            ppc64.AMOVHBR,
23869		reg: regInfo{
23870			inputs: []inputInfo{
23871				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23872				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23873			},
23874			outputs: []outputInfo{
23875				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23876			},
23877		},
23878	},
23879	{
23880		name:           "MOVWBRloadidx",
23881		auxType:        auxSymOff,
23882		argLen:         3,
23883		faultOnNilArg0: true,
23884		symEffect:      SymRead,
23885		asm:            ppc64.AMOVWBR,
23886		reg: regInfo{
23887			inputs: []inputInfo{
23888				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23889				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23890			},
23891			outputs: []outputInfo{
23892				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23893			},
23894		},
23895	},
23896	{
23897		name:           "MOVDBRloadidx",
23898		auxType:        auxSymOff,
23899		argLen:         3,
23900		faultOnNilArg0: true,
23901		symEffect:      SymRead,
23902		asm:            ppc64.AMOVDBR,
23903		reg: regInfo{
23904			inputs: []inputInfo{
23905				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23906				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23907			},
23908			outputs: []outputInfo{
23909				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23910			},
23911		},
23912	},
23913	{
23914		name:           "FMOVDloadidx",
23915		auxType:        auxSymOff,
23916		argLen:         3,
23917		faultOnNilArg0: true,
23918		symEffect:      SymRead,
23919		asm:            ppc64.AFMOVD,
23920		reg: regInfo{
23921			inputs: []inputInfo{
23922				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23923				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23924			},
23925			outputs: []outputInfo{
23926				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23927			},
23928		},
23929	},
23930	{
23931		name:           "FMOVSloadidx",
23932		auxType:        auxSymOff,
23933		argLen:         3,
23934		faultOnNilArg0: true,
23935		symEffect:      SymRead,
23936		asm:            ppc64.AFMOVS,
23937		reg: regInfo{
23938			inputs: []inputInfo{
23939				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23940				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23941			},
23942			outputs: []outputInfo{
23943				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
23944			},
23945		},
23946	},
23947	{
23948		name:           "MOVDBRstore",
23949		auxType:        auxSymOff,
23950		argLen:         3,
23951		faultOnNilArg0: true,
23952		symEffect:      SymWrite,
23953		asm:            ppc64.AMOVDBR,
23954		reg: regInfo{
23955			inputs: []inputInfo{
23956				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23957				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23958			},
23959		},
23960	},
23961	{
23962		name:           "MOVWBRstore",
23963		auxType:        auxSymOff,
23964		argLen:         3,
23965		faultOnNilArg0: true,
23966		symEffect:      SymWrite,
23967		asm:            ppc64.AMOVWBR,
23968		reg: regInfo{
23969			inputs: []inputInfo{
23970				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23971				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23972			},
23973		},
23974	},
23975	{
23976		name:           "MOVHBRstore",
23977		auxType:        auxSymOff,
23978		argLen:         3,
23979		faultOnNilArg0: true,
23980		symEffect:      SymWrite,
23981		asm:            ppc64.AMOVHBR,
23982		reg: regInfo{
23983			inputs: []inputInfo{
23984				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23985				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23986			},
23987		},
23988	},
23989	{
23990		name:           "FMOVDload",
23991		auxType:        auxSymOff,
23992		argLen:         2,
23993		faultOnNilArg0: true,
23994		symEffect:      SymRead,
23995		asm:            ppc64.AFMOVD,
23996		reg: regInfo{
23997			inputs: []inputInfo{
23998				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
23999			},
24000			outputs: []outputInfo{
24001				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24002			},
24003		},
24004	},
24005	{
24006		name:           "FMOVSload",
24007		auxType:        auxSymOff,
24008		argLen:         2,
24009		faultOnNilArg0: true,
24010		symEffect:      SymRead,
24011		asm:            ppc64.AFMOVS,
24012		reg: regInfo{
24013			inputs: []inputInfo{
24014				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24015			},
24016			outputs: []outputInfo{
24017				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24018			},
24019		},
24020	},
24021	{
24022		name:           "MOVBstore",
24023		auxType:        auxSymOff,
24024		argLen:         3,
24025		faultOnNilArg0: true,
24026		symEffect:      SymWrite,
24027		asm:            ppc64.AMOVB,
24028		reg: regInfo{
24029			inputs: []inputInfo{
24030				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24031				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24032			},
24033		},
24034	},
24035	{
24036		name:           "MOVHstore",
24037		auxType:        auxSymOff,
24038		argLen:         3,
24039		faultOnNilArg0: true,
24040		symEffect:      SymWrite,
24041		asm:            ppc64.AMOVH,
24042		reg: regInfo{
24043			inputs: []inputInfo{
24044				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24045				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24046			},
24047		},
24048	},
24049	{
24050		name:           "MOVWstore",
24051		auxType:        auxSymOff,
24052		argLen:         3,
24053		faultOnNilArg0: true,
24054		symEffect:      SymWrite,
24055		asm:            ppc64.AMOVW,
24056		reg: regInfo{
24057			inputs: []inputInfo{
24058				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24059				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24060			},
24061		},
24062	},
24063	{
24064		name:           "MOVDstore",
24065		auxType:        auxSymOff,
24066		argLen:         3,
24067		faultOnNilArg0: true,
24068		symEffect:      SymWrite,
24069		asm:            ppc64.AMOVD,
24070		reg: regInfo{
24071			inputs: []inputInfo{
24072				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24073				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24074			},
24075		},
24076	},
24077	{
24078		name:           "FMOVDstore",
24079		auxType:        auxSymOff,
24080		argLen:         3,
24081		faultOnNilArg0: true,
24082		symEffect:      SymWrite,
24083		asm:            ppc64.AFMOVD,
24084		reg: regInfo{
24085			inputs: []inputInfo{
24086				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24087				{0, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24088			},
24089		},
24090	},
24091	{
24092		name:           "FMOVSstore",
24093		auxType:        auxSymOff,
24094		argLen:         3,
24095		faultOnNilArg0: true,
24096		symEffect:      SymWrite,
24097		asm:            ppc64.AFMOVS,
24098		reg: regInfo{
24099			inputs: []inputInfo{
24100				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24101				{0, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24102			},
24103		},
24104	},
24105	{
24106		name:           "MOVBstoreidx",
24107		auxType:        auxSymOff,
24108		argLen:         4,
24109		faultOnNilArg0: true,
24110		symEffect:      SymWrite,
24111		asm:            ppc64.AMOVB,
24112		reg: regInfo{
24113			inputs: []inputInfo{
24114				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24115				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24116				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24117			},
24118		},
24119	},
24120	{
24121		name:           "MOVHstoreidx",
24122		auxType:        auxSymOff,
24123		argLen:         4,
24124		faultOnNilArg0: true,
24125		symEffect:      SymWrite,
24126		asm:            ppc64.AMOVH,
24127		reg: regInfo{
24128			inputs: []inputInfo{
24129				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24130				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24131				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24132			},
24133		},
24134	},
24135	{
24136		name:           "MOVWstoreidx",
24137		auxType:        auxSymOff,
24138		argLen:         4,
24139		faultOnNilArg0: true,
24140		symEffect:      SymWrite,
24141		asm:            ppc64.AMOVW,
24142		reg: regInfo{
24143			inputs: []inputInfo{
24144				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24145				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24146				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24147			},
24148		},
24149	},
24150	{
24151		name:           "MOVDstoreidx",
24152		auxType:        auxSymOff,
24153		argLen:         4,
24154		faultOnNilArg0: true,
24155		symEffect:      SymWrite,
24156		asm:            ppc64.AMOVD,
24157		reg: regInfo{
24158			inputs: []inputInfo{
24159				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24160				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24161				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24162			},
24163		},
24164	},
24165	{
24166		name:           "FMOVDstoreidx",
24167		auxType:        auxSymOff,
24168		argLen:         4,
24169		faultOnNilArg0: true,
24170		symEffect:      SymWrite,
24171		asm:            ppc64.AFMOVD,
24172		reg: regInfo{
24173			inputs: []inputInfo{
24174				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24175				{0, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24176				{1, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24177			},
24178		},
24179	},
24180	{
24181		name:           "FMOVSstoreidx",
24182		auxType:        auxSymOff,
24183		argLen:         4,
24184		faultOnNilArg0: true,
24185		symEffect:      SymWrite,
24186		asm:            ppc64.AFMOVS,
24187		reg: regInfo{
24188			inputs: []inputInfo{
24189				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24190				{0, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24191				{1, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24192			},
24193		},
24194	},
24195	{
24196		name:           "MOVHBRstoreidx",
24197		auxType:        auxSymOff,
24198		argLen:         4,
24199		faultOnNilArg0: true,
24200		symEffect:      SymWrite,
24201		asm:            ppc64.AMOVHBR,
24202		reg: regInfo{
24203			inputs: []inputInfo{
24204				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24205				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24206				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24207			},
24208		},
24209	},
24210	{
24211		name:           "MOVWBRstoreidx",
24212		auxType:        auxSymOff,
24213		argLen:         4,
24214		faultOnNilArg0: true,
24215		symEffect:      SymWrite,
24216		asm:            ppc64.AMOVWBR,
24217		reg: regInfo{
24218			inputs: []inputInfo{
24219				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24220				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24221				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24222			},
24223		},
24224	},
24225	{
24226		name:           "MOVDBRstoreidx",
24227		auxType:        auxSymOff,
24228		argLen:         4,
24229		faultOnNilArg0: true,
24230		symEffect:      SymWrite,
24231		asm:            ppc64.AMOVDBR,
24232		reg: regInfo{
24233			inputs: []inputInfo{
24234				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24235				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24236				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24237			},
24238		},
24239	},
24240	{
24241		name:           "MOVBstorezero",
24242		auxType:        auxSymOff,
24243		argLen:         2,
24244		faultOnNilArg0: true,
24245		symEffect:      SymWrite,
24246		asm:            ppc64.AMOVB,
24247		reg: regInfo{
24248			inputs: []inputInfo{
24249				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24250			},
24251		},
24252	},
24253	{
24254		name:           "MOVHstorezero",
24255		auxType:        auxSymOff,
24256		argLen:         2,
24257		faultOnNilArg0: true,
24258		symEffect:      SymWrite,
24259		asm:            ppc64.AMOVH,
24260		reg: regInfo{
24261			inputs: []inputInfo{
24262				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24263			},
24264		},
24265	},
24266	{
24267		name:           "MOVWstorezero",
24268		auxType:        auxSymOff,
24269		argLen:         2,
24270		faultOnNilArg0: true,
24271		symEffect:      SymWrite,
24272		asm:            ppc64.AMOVW,
24273		reg: regInfo{
24274			inputs: []inputInfo{
24275				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24276			},
24277		},
24278	},
24279	{
24280		name:           "MOVDstorezero",
24281		auxType:        auxSymOff,
24282		argLen:         2,
24283		faultOnNilArg0: true,
24284		symEffect:      SymWrite,
24285		asm:            ppc64.AMOVD,
24286		reg: regInfo{
24287			inputs: []inputInfo{
24288				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24289			},
24290		},
24291	},
24292	{
24293		name:              "MOVDaddr",
24294		auxType:           auxSymOff,
24295		argLen:            1,
24296		rematerializeable: true,
24297		symEffect:         SymAddr,
24298		asm:               ppc64.AMOVD,
24299		reg: regInfo{
24300			inputs: []inputInfo{
24301				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24302			},
24303			outputs: []outputInfo{
24304				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24305			},
24306		},
24307	},
24308	{
24309		name:              "MOVDconst",
24310		auxType:           auxInt64,
24311		argLen:            0,
24312		rematerializeable: true,
24313		asm:               ppc64.AMOVD,
24314		reg: regInfo{
24315			outputs: []outputInfo{
24316				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24317			},
24318		},
24319	},
24320	{
24321		name:              "FMOVDconst",
24322		auxType:           auxFloat64,
24323		argLen:            0,
24324		rematerializeable: true,
24325		asm:               ppc64.AFMOVD,
24326		reg: regInfo{
24327			outputs: []outputInfo{
24328				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24329			},
24330		},
24331	},
24332	{
24333		name:              "FMOVSconst",
24334		auxType:           auxFloat32,
24335		argLen:            0,
24336		rematerializeable: true,
24337		asm:               ppc64.AFMOVS,
24338		reg: regInfo{
24339			outputs: []outputInfo{
24340				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24341			},
24342		},
24343	},
24344	{
24345		name:   "FCMPU",
24346		argLen: 2,
24347		asm:    ppc64.AFCMPU,
24348		reg: regInfo{
24349			inputs: []inputInfo{
24350				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24351				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24352			},
24353		},
24354	},
24355	{
24356		name:   "CMP",
24357		argLen: 2,
24358		asm:    ppc64.ACMP,
24359		reg: regInfo{
24360			inputs: []inputInfo{
24361				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24362				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24363			},
24364		},
24365	},
24366	{
24367		name:   "CMPU",
24368		argLen: 2,
24369		asm:    ppc64.ACMPU,
24370		reg: regInfo{
24371			inputs: []inputInfo{
24372				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24373				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24374			},
24375		},
24376	},
24377	{
24378		name:   "CMPW",
24379		argLen: 2,
24380		asm:    ppc64.ACMPW,
24381		reg: regInfo{
24382			inputs: []inputInfo{
24383				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24384				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24385			},
24386		},
24387	},
24388	{
24389		name:   "CMPWU",
24390		argLen: 2,
24391		asm:    ppc64.ACMPWU,
24392		reg: regInfo{
24393			inputs: []inputInfo{
24394				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24395				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24396			},
24397		},
24398	},
24399	{
24400		name:    "CMPconst",
24401		auxType: auxInt64,
24402		argLen:  1,
24403		asm:     ppc64.ACMP,
24404		reg: regInfo{
24405			inputs: []inputInfo{
24406				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24407			},
24408		},
24409	},
24410	{
24411		name:    "CMPUconst",
24412		auxType: auxInt64,
24413		argLen:  1,
24414		asm:     ppc64.ACMPU,
24415		reg: regInfo{
24416			inputs: []inputInfo{
24417				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24418			},
24419		},
24420	},
24421	{
24422		name:    "CMPWconst",
24423		auxType: auxInt32,
24424		argLen:  1,
24425		asm:     ppc64.ACMPW,
24426		reg: regInfo{
24427			inputs: []inputInfo{
24428				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24429			},
24430		},
24431	},
24432	{
24433		name:    "CMPWUconst",
24434		auxType: auxInt32,
24435		argLen:  1,
24436		asm:     ppc64.ACMPWU,
24437		reg: regInfo{
24438			inputs: []inputInfo{
24439				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24440			},
24441		},
24442	},
24443	{
24444		name:    "ISEL",
24445		auxType: auxInt32,
24446		argLen:  3,
24447		asm:     ppc64.AISEL,
24448		reg: regInfo{
24449			inputs: []inputInfo{
24450				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24451				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24452			},
24453			outputs: []outputInfo{
24454				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24455			},
24456		},
24457	},
24458	{
24459		name:    "ISELB",
24460		auxType: auxInt32,
24461		argLen:  2,
24462		asm:     ppc64.AISEL,
24463		reg: regInfo{
24464			inputs: []inputInfo{
24465				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24466			},
24467			outputs: []outputInfo{
24468				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24469			},
24470		},
24471	},
24472	{
24473		name:   "Equal",
24474		argLen: 1,
24475		reg: regInfo{
24476			outputs: []outputInfo{
24477				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24478			},
24479		},
24480	},
24481	{
24482		name:   "NotEqual",
24483		argLen: 1,
24484		reg: regInfo{
24485			outputs: []outputInfo{
24486				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24487			},
24488		},
24489	},
24490	{
24491		name:   "LessThan",
24492		argLen: 1,
24493		reg: regInfo{
24494			outputs: []outputInfo{
24495				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24496			},
24497		},
24498	},
24499	{
24500		name:   "FLessThan",
24501		argLen: 1,
24502		reg: regInfo{
24503			outputs: []outputInfo{
24504				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24505			},
24506		},
24507	},
24508	{
24509		name:   "LessEqual",
24510		argLen: 1,
24511		reg: regInfo{
24512			outputs: []outputInfo{
24513				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24514			},
24515		},
24516	},
24517	{
24518		name:   "FLessEqual",
24519		argLen: 1,
24520		reg: regInfo{
24521			outputs: []outputInfo{
24522				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24523			},
24524		},
24525	},
24526	{
24527		name:   "GreaterThan",
24528		argLen: 1,
24529		reg: regInfo{
24530			outputs: []outputInfo{
24531				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24532			},
24533		},
24534	},
24535	{
24536		name:   "FGreaterThan",
24537		argLen: 1,
24538		reg: regInfo{
24539			outputs: []outputInfo{
24540				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24541			},
24542		},
24543	},
24544	{
24545		name:   "GreaterEqual",
24546		argLen: 1,
24547		reg: regInfo{
24548			outputs: []outputInfo{
24549				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24550			},
24551		},
24552	},
24553	{
24554		name:   "FGreaterEqual",
24555		argLen: 1,
24556		reg: regInfo{
24557			outputs: []outputInfo{
24558				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24559			},
24560		},
24561	},
24562	{
24563		name:      "LoweredGetClosurePtr",
24564		argLen:    0,
24565		zeroWidth: true,
24566		reg: regInfo{
24567			outputs: []outputInfo{
24568				{0, 2048}, // R11
24569			},
24570		},
24571	},
24572	{
24573		name:              "LoweredGetCallerSP",
24574		argLen:            0,
24575		rematerializeable: true,
24576		reg: regInfo{
24577			outputs: []outputInfo{
24578				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24579			},
24580		},
24581	},
24582	{
24583		name:              "LoweredGetCallerPC",
24584		argLen:            0,
24585		rematerializeable: true,
24586		reg: regInfo{
24587			outputs: []outputInfo{
24588				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24589			},
24590		},
24591	},
24592	{
24593		name:           "LoweredNilCheck",
24594		argLen:         2,
24595		clobberFlags:   true,
24596		nilCheck:       true,
24597		faultOnNilArg0: true,
24598		reg: regInfo{
24599			inputs: []inputInfo{
24600				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24601			},
24602			clobbers: 2147483648, // R31
24603		},
24604	},
24605	{
24606		name:         "LoweredRound32F",
24607		argLen:       1,
24608		resultInArg0: true,
24609		zeroWidth:    true,
24610		reg: regInfo{
24611			inputs: []inputInfo{
24612				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24613			},
24614			outputs: []outputInfo{
24615				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24616			},
24617		},
24618	},
24619	{
24620		name:         "LoweredRound64F",
24621		argLen:       1,
24622		resultInArg0: true,
24623		zeroWidth:    true,
24624		reg: regInfo{
24625			inputs: []inputInfo{
24626				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24627			},
24628			outputs: []outputInfo{
24629				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24630			},
24631		},
24632	},
24633	{
24634		name:         "CALLstatic",
24635		auxType:      auxSymOff,
24636		argLen:       1,
24637		clobberFlags: true,
24638		call:         true,
24639		symEffect:    SymNone,
24640		reg: regInfo{
24641			clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24642		},
24643	},
24644	{
24645		name:         "CALLclosure",
24646		auxType:      auxInt64,
24647		argLen:       3,
24648		clobberFlags: true,
24649		call:         true,
24650		reg: regInfo{
24651			inputs: []inputInfo{
24652				{0, 4096}, // R12
24653				{1, 2048}, // R11
24654			},
24655			clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24656		},
24657	},
24658	{
24659		name:         "CALLinter",
24660		auxType:      auxInt64,
24661		argLen:       2,
24662		clobberFlags: true,
24663		call:         true,
24664		reg: regInfo{
24665			inputs: []inputInfo{
24666				{0, 4096}, // R12
24667			},
24668			clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24669		},
24670	},
24671	{
24672		name:           "LoweredZero",
24673		auxType:        auxInt64,
24674		argLen:         2,
24675		clobberFlags:   true,
24676		faultOnNilArg0: true,
24677		unsafePoint:    true,
24678		reg: regInfo{
24679			inputs: []inputInfo{
24680				{0, 8}, // R3
24681			},
24682			clobbers: 8, // R3
24683		},
24684	},
24685	{
24686		name:           "LoweredMove",
24687		auxType:        auxInt64,
24688		argLen:         3,
24689		clobberFlags:   true,
24690		faultOnNilArg0: true,
24691		faultOnNilArg1: true,
24692		unsafePoint:    true,
24693		reg: regInfo{
24694			inputs: []inputInfo{
24695				{0, 8},  // R3
24696				{1, 16}, // R4
24697			},
24698			clobbers: 16408, // R3 R4 R14
24699		},
24700	},
24701	{
24702		name:           "LoweredAtomicStore8",
24703		auxType:        auxInt64,
24704		argLen:         3,
24705		faultOnNilArg0: true,
24706		hasSideEffects: true,
24707		reg: regInfo{
24708			inputs: []inputInfo{
24709				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24710				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24711			},
24712		},
24713	},
24714	{
24715		name:           "LoweredAtomicStore32",
24716		auxType:        auxInt64,
24717		argLen:         3,
24718		faultOnNilArg0: true,
24719		hasSideEffects: true,
24720		reg: regInfo{
24721			inputs: []inputInfo{
24722				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24723				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24724			},
24725		},
24726	},
24727	{
24728		name:           "LoweredAtomicStore64",
24729		auxType:        auxInt64,
24730		argLen:         3,
24731		faultOnNilArg0: true,
24732		hasSideEffects: true,
24733		reg: regInfo{
24734			inputs: []inputInfo{
24735				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24736				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24737			},
24738		},
24739	},
24740	{
24741		name:           "LoweredAtomicLoad8",
24742		auxType:        auxInt64,
24743		argLen:         2,
24744		clobberFlags:   true,
24745		faultOnNilArg0: true,
24746		reg: regInfo{
24747			inputs: []inputInfo{
24748				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24749			},
24750			outputs: []outputInfo{
24751				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24752			},
24753		},
24754	},
24755	{
24756		name:           "LoweredAtomicLoad32",
24757		auxType:        auxInt64,
24758		argLen:         2,
24759		clobberFlags:   true,
24760		faultOnNilArg0: true,
24761		reg: regInfo{
24762			inputs: []inputInfo{
24763				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24764			},
24765			outputs: []outputInfo{
24766				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24767			},
24768		},
24769	},
24770	{
24771		name:           "LoweredAtomicLoad64",
24772		auxType:        auxInt64,
24773		argLen:         2,
24774		clobberFlags:   true,
24775		faultOnNilArg0: true,
24776		reg: regInfo{
24777			inputs: []inputInfo{
24778				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24779			},
24780			outputs: []outputInfo{
24781				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24782			},
24783		},
24784	},
24785	{
24786		name:           "LoweredAtomicLoadPtr",
24787		auxType:        auxInt64,
24788		argLen:         2,
24789		clobberFlags:   true,
24790		faultOnNilArg0: true,
24791		reg: regInfo{
24792			inputs: []inputInfo{
24793				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24794			},
24795			outputs: []outputInfo{
24796				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24797			},
24798		},
24799	},
24800	{
24801		name:            "LoweredAtomicAdd32",
24802		argLen:          3,
24803		resultNotInArgs: true,
24804		clobberFlags:    true,
24805		faultOnNilArg0:  true,
24806		hasSideEffects:  true,
24807		reg: regInfo{
24808			inputs: []inputInfo{
24809				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24810				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24811			},
24812			outputs: []outputInfo{
24813				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24814			},
24815		},
24816	},
24817	{
24818		name:            "LoweredAtomicAdd64",
24819		argLen:          3,
24820		resultNotInArgs: true,
24821		clobberFlags:    true,
24822		faultOnNilArg0:  true,
24823		hasSideEffects:  true,
24824		reg: regInfo{
24825			inputs: []inputInfo{
24826				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24827				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24828			},
24829			outputs: []outputInfo{
24830				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24831			},
24832		},
24833	},
24834	{
24835		name:            "LoweredAtomicExchange32",
24836		argLen:          3,
24837		resultNotInArgs: true,
24838		clobberFlags:    true,
24839		faultOnNilArg0:  true,
24840		hasSideEffects:  true,
24841		reg: regInfo{
24842			inputs: []inputInfo{
24843				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24844				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24845			},
24846			outputs: []outputInfo{
24847				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24848			},
24849		},
24850	},
24851	{
24852		name:            "LoweredAtomicExchange64",
24853		argLen:          3,
24854		resultNotInArgs: true,
24855		clobberFlags:    true,
24856		faultOnNilArg0:  true,
24857		hasSideEffects:  true,
24858		reg: regInfo{
24859			inputs: []inputInfo{
24860				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24861				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24862			},
24863			outputs: []outputInfo{
24864				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24865			},
24866		},
24867	},
24868	{
24869		name:            "LoweredAtomicCas64",
24870		auxType:         auxInt64,
24871		argLen:          4,
24872		resultNotInArgs: true,
24873		clobberFlags:    true,
24874		faultOnNilArg0:  true,
24875		hasSideEffects:  true,
24876		reg: regInfo{
24877			inputs: []inputInfo{
24878				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24879				{2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24880				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24881			},
24882			outputs: []outputInfo{
24883				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24884			},
24885		},
24886	},
24887	{
24888		name:            "LoweredAtomicCas32",
24889		auxType:         auxInt64,
24890		argLen:          4,
24891		resultNotInArgs: true,
24892		clobberFlags:    true,
24893		faultOnNilArg0:  true,
24894		hasSideEffects:  true,
24895		reg: regInfo{
24896			inputs: []inputInfo{
24897				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24898				{2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24899				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24900			},
24901			outputs: []outputInfo{
24902				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24903			},
24904		},
24905	},
24906	{
24907		name:           "LoweredAtomicAnd8",
24908		argLen:         3,
24909		faultOnNilArg0: true,
24910		hasSideEffects: true,
24911		asm:            ppc64.AAND,
24912		reg: regInfo{
24913			inputs: []inputInfo{
24914				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24915				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24916			},
24917		},
24918	},
24919	{
24920		name:           "LoweredAtomicOr8",
24921		argLen:         3,
24922		faultOnNilArg0: true,
24923		hasSideEffects: true,
24924		asm:            ppc64.AOR,
24925		reg: regInfo{
24926			inputs: []inputInfo{
24927				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24928				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
24929			},
24930		},
24931	},
24932	{
24933		name:         "LoweredWB",
24934		auxType:      auxSym,
24935		argLen:       3,
24936		clobberFlags: true,
24937		symEffect:    SymNone,
24938		reg: regInfo{
24939			inputs: []inputInfo{
24940				{0, 1048576}, // R20
24941				{1, 2097152}, // R21
24942			},
24943			clobbers: 576460746931503104, // R16 R17 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
24944		},
24945	},
24946	{
24947		name:    "LoweredPanicBoundsA",
24948		auxType: auxInt64,
24949		argLen:  3,
24950		reg: regInfo{
24951			inputs: []inputInfo{
24952				{0, 32}, // R5
24953				{1, 64}, // R6
24954			},
24955		},
24956	},
24957	{
24958		name:    "LoweredPanicBoundsB",
24959		auxType: auxInt64,
24960		argLen:  3,
24961		reg: regInfo{
24962			inputs: []inputInfo{
24963				{0, 16}, // R4
24964				{1, 32}, // R5
24965			},
24966		},
24967	},
24968	{
24969		name:    "LoweredPanicBoundsC",
24970		auxType: auxInt64,
24971		argLen:  3,
24972		reg: regInfo{
24973			inputs: []inputInfo{
24974				{0, 8},  // R3
24975				{1, 16}, // R4
24976			},
24977		},
24978	},
24979	{
24980		name:   "InvertFlags",
24981		argLen: 1,
24982		reg:    regInfo{},
24983	},
24984	{
24985		name:   "FlagEQ",
24986		argLen: 0,
24987		reg:    regInfo{},
24988	},
24989	{
24990		name:   "FlagLT",
24991		argLen: 0,
24992		reg:    regInfo{},
24993	},
24994	{
24995		name:   "FlagGT",
24996		argLen: 0,
24997		reg:    regInfo{},
24998	},
24999
25000	{
25001		name:        "ADD",
25002		argLen:      2,
25003		commutative: true,
25004		asm:         riscv.AADD,
25005		reg: regInfo{
25006			inputs: []inputInfo{
25007				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25008				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25009			},
25010			outputs: []outputInfo{
25011				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25012			},
25013		},
25014	},
25015	{
25016		name:    "ADDI",
25017		auxType: auxInt64,
25018		argLen:  1,
25019		asm:     riscv.AADDI,
25020		reg: regInfo{
25021			inputs: []inputInfo{
25022				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25023			},
25024			outputs: []outputInfo{
25025				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25026			},
25027		},
25028	},
25029	{
25030		name:   "SUB",
25031		argLen: 2,
25032		asm:    riscv.ASUB,
25033		reg: regInfo{
25034			inputs: []inputInfo{
25035				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25036				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25037			},
25038			outputs: []outputInfo{
25039				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25040			},
25041		},
25042	},
25043	{
25044		name:        "MUL",
25045		argLen:      2,
25046		commutative: true,
25047		asm:         riscv.AMUL,
25048		reg: regInfo{
25049			inputs: []inputInfo{
25050				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25051				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25052			},
25053			outputs: []outputInfo{
25054				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25055			},
25056		},
25057	},
25058	{
25059		name:        "MULW",
25060		argLen:      2,
25061		commutative: true,
25062		asm:         riscv.AMULW,
25063		reg: regInfo{
25064			inputs: []inputInfo{
25065				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25066				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25067			},
25068			outputs: []outputInfo{
25069				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25070			},
25071		},
25072	},
25073	{
25074		name:        "MULH",
25075		argLen:      2,
25076		commutative: true,
25077		asm:         riscv.AMULH,
25078		reg: regInfo{
25079			inputs: []inputInfo{
25080				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25081				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25082			},
25083			outputs: []outputInfo{
25084				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25085			},
25086		},
25087	},
25088	{
25089		name:        "MULHU",
25090		argLen:      2,
25091		commutative: true,
25092		asm:         riscv.AMULHU,
25093		reg: regInfo{
25094			inputs: []inputInfo{
25095				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25096				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25097			},
25098			outputs: []outputInfo{
25099				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25100			},
25101		},
25102	},
25103	{
25104		name:   "DIV",
25105		argLen: 2,
25106		asm:    riscv.ADIV,
25107		reg: regInfo{
25108			inputs: []inputInfo{
25109				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25110				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25111			},
25112			outputs: []outputInfo{
25113				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25114			},
25115		},
25116	},
25117	{
25118		name:   "DIVU",
25119		argLen: 2,
25120		asm:    riscv.ADIVU,
25121		reg: regInfo{
25122			inputs: []inputInfo{
25123				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25124				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25125			},
25126			outputs: []outputInfo{
25127				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25128			},
25129		},
25130	},
25131	{
25132		name:   "DIVW",
25133		argLen: 2,
25134		asm:    riscv.ADIVW,
25135		reg: regInfo{
25136			inputs: []inputInfo{
25137				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25138				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25139			},
25140			outputs: []outputInfo{
25141				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25142			},
25143		},
25144	},
25145	{
25146		name:   "DIVUW",
25147		argLen: 2,
25148		asm:    riscv.ADIVUW,
25149		reg: regInfo{
25150			inputs: []inputInfo{
25151				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25152				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25153			},
25154			outputs: []outputInfo{
25155				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25156			},
25157		},
25158	},
25159	{
25160		name:   "REM",
25161		argLen: 2,
25162		asm:    riscv.AREM,
25163		reg: regInfo{
25164			inputs: []inputInfo{
25165				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25166				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25167			},
25168			outputs: []outputInfo{
25169				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25170			},
25171		},
25172	},
25173	{
25174		name:   "REMU",
25175		argLen: 2,
25176		asm:    riscv.AREMU,
25177		reg: regInfo{
25178			inputs: []inputInfo{
25179				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25180				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25181			},
25182			outputs: []outputInfo{
25183				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25184			},
25185		},
25186	},
25187	{
25188		name:   "REMW",
25189		argLen: 2,
25190		asm:    riscv.AREMW,
25191		reg: regInfo{
25192			inputs: []inputInfo{
25193				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25194				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25195			},
25196			outputs: []outputInfo{
25197				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25198			},
25199		},
25200	},
25201	{
25202		name:   "REMUW",
25203		argLen: 2,
25204		asm:    riscv.AREMUW,
25205		reg: regInfo{
25206			inputs: []inputInfo{
25207				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25208				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25209			},
25210			outputs: []outputInfo{
25211				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25212			},
25213		},
25214	},
25215	{
25216		name:              "MOVaddr",
25217		auxType:           auxSymOff,
25218		argLen:            1,
25219		rematerializeable: true,
25220		symEffect:         SymRdWr,
25221		asm:               riscv.AMOV,
25222		reg: regInfo{
25223			inputs: []inputInfo{
25224				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25225			},
25226			outputs: []outputInfo{
25227				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25228			},
25229		},
25230	},
25231	{
25232		name:              "MOVBconst",
25233		auxType:           auxInt8,
25234		argLen:            0,
25235		rematerializeable: true,
25236		asm:               riscv.AMOV,
25237		reg: regInfo{
25238			outputs: []outputInfo{
25239				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25240			},
25241		},
25242	},
25243	{
25244		name:              "MOVHconst",
25245		auxType:           auxInt16,
25246		argLen:            0,
25247		rematerializeable: true,
25248		asm:               riscv.AMOV,
25249		reg: regInfo{
25250			outputs: []outputInfo{
25251				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25252			},
25253		},
25254	},
25255	{
25256		name:              "MOVWconst",
25257		auxType:           auxInt32,
25258		argLen:            0,
25259		rematerializeable: true,
25260		asm:               riscv.AMOV,
25261		reg: regInfo{
25262			outputs: []outputInfo{
25263				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25264			},
25265		},
25266	},
25267	{
25268		name:              "MOVDconst",
25269		auxType:           auxInt64,
25270		argLen:            0,
25271		rematerializeable: true,
25272		asm:               riscv.AMOV,
25273		reg: regInfo{
25274			outputs: []outputInfo{
25275				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25276			},
25277		},
25278	},
25279	{
25280		name:           "MOVBload",
25281		auxType:        auxSymOff,
25282		argLen:         2,
25283		faultOnNilArg0: true,
25284		symEffect:      SymRead,
25285		asm:            riscv.AMOVB,
25286		reg: regInfo{
25287			inputs: []inputInfo{
25288				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25289			},
25290			outputs: []outputInfo{
25291				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25292			},
25293		},
25294	},
25295	{
25296		name:           "MOVHload",
25297		auxType:        auxSymOff,
25298		argLen:         2,
25299		faultOnNilArg0: true,
25300		symEffect:      SymRead,
25301		asm:            riscv.AMOVH,
25302		reg: regInfo{
25303			inputs: []inputInfo{
25304				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25305			},
25306			outputs: []outputInfo{
25307				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25308			},
25309		},
25310	},
25311	{
25312		name:           "MOVWload",
25313		auxType:        auxSymOff,
25314		argLen:         2,
25315		faultOnNilArg0: true,
25316		symEffect:      SymRead,
25317		asm:            riscv.AMOVW,
25318		reg: regInfo{
25319			inputs: []inputInfo{
25320				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25321			},
25322			outputs: []outputInfo{
25323				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25324			},
25325		},
25326	},
25327	{
25328		name:           "MOVDload",
25329		auxType:        auxSymOff,
25330		argLen:         2,
25331		faultOnNilArg0: true,
25332		symEffect:      SymRead,
25333		asm:            riscv.AMOV,
25334		reg: regInfo{
25335			inputs: []inputInfo{
25336				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25337			},
25338			outputs: []outputInfo{
25339				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25340			},
25341		},
25342	},
25343	{
25344		name:           "MOVBUload",
25345		auxType:        auxSymOff,
25346		argLen:         2,
25347		faultOnNilArg0: true,
25348		symEffect:      SymRead,
25349		asm:            riscv.AMOVBU,
25350		reg: regInfo{
25351			inputs: []inputInfo{
25352				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25353			},
25354			outputs: []outputInfo{
25355				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25356			},
25357		},
25358	},
25359	{
25360		name:           "MOVHUload",
25361		auxType:        auxSymOff,
25362		argLen:         2,
25363		faultOnNilArg0: true,
25364		symEffect:      SymRead,
25365		asm:            riscv.AMOVHU,
25366		reg: regInfo{
25367			inputs: []inputInfo{
25368				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25369			},
25370			outputs: []outputInfo{
25371				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25372			},
25373		},
25374	},
25375	{
25376		name:           "MOVWUload",
25377		auxType:        auxSymOff,
25378		argLen:         2,
25379		faultOnNilArg0: true,
25380		symEffect:      SymRead,
25381		asm:            riscv.AMOVWU,
25382		reg: regInfo{
25383			inputs: []inputInfo{
25384				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25385			},
25386			outputs: []outputInfo{
25387				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25388			},
25389		},
25390	},
25391	{
25392		name:           "MOVBstore",
25393		auxType:        auxSymOff,
25394		argLen:         3,
25395		faultOnNilArg0: true,
25396		symEffect:      SymWrite,
25397		asm:            riscv.AMOVB,
25398		reg: regInfo{
25399			inputs: []inputInfo{
25400				{1, 1073741814},          // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25401				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25402			},
25403		},
25404	},
25405	{
25406		name:           "MOVHstore",
25407		auxType:        auxSymOff,
25408		argLen:         3,
25409		faultOnNilArg0: true,
25410		symEffect:      SymWrite,
25411		asm:            riscv.AMOVH,
25412		reg: regInfo{
25413			inputs: []inputInfo{
25414				{1, 1073741814},          // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25415				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25416			},
25417		},
25418	},
25419	{
25420		name:           "MOVWstore",
25421		auxType:        auxSymOff,
25422		argLen:         3,
25423		faultOnNilArg0: true,
25424		symEffect:      SymWrite,
25425		asm:            riscv.AMOVW,
25426		reg: regInfo{
25427			inputs: []inputInfo{
25428				{1, 1073741814},          // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25429				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25430			},
25431		},
25432	},
25433	{
25434		name:           "MOVDstore",
25435		auxType:        auxSymOff,
25436		argLen:         3,
25437		faultOnNilArg0: true,
25438		symEffect:      SymWrite,
25439		asm:            riscv.AMOV,
25440		reg: regInfo{
25441			inputs: []inputInfo{
25442				{1, 1073741814},          // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25443				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
25444			},
25445		},
25446	},
25447	{
25448		name:   "SLL",
25449		argLen: 2,
25450		asm:    riscv.ASLL,
25451		reg: regInfo{
25452			inputs: []inputInfo{
25453				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25454				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25455			},
25456			outputs: []outputInfo{
25457				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25458			},
25459		},
25460	},
25461	{
25462		name:   "SRA",
25463		argLen: 2,
25464		asm:    riscv.ASRA,
25465		reg: regInfo{
25466			inputs: []inputInfo{
25467				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25468				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25469			},
25470			outputs: []outputInfo{
25471				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25472			},
25473		},
25474	},
25475	{
25476		name:   "SRL",
25477		argLen: 2,
25478		asm:    riscv.ASRL,
25479		reg: regInfo{
25480			inputs: []inputInfo{
25481				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25482				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25483			},
25484			outputs: []outputInfo{
25485				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25486			},
25487		},
25488	},
25489	{
25490		name:    "SLLI",
25491		auxType: auxInt64,
25492		argLen:  1,
25493		asm:     riscv.ASLLI,
25494		reg: regInfo{
25495			inputs: []inputInfo{
25496				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25497			},
25498			outputs: []outputInfo{
25499				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25500			},
25501		},
25502	},
25503	{
25504		name:    "SRAI",
25505		auxType: auxInt64,
25506		argLen:  1,
25507		asm:     riscv.ASRAI,
25508		reg: regInfo{
25509			inputs: []inputInfo{
25510				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25511			},
25512			outputs: []outputInfo{
25513				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25514			},
25515		},
25516	},
25517	{
25518		name:    "SRLI",
25519		auxType: auxInt64,
25520		argLen:  1,
25521		asm:     riscv.ASRLI,
25522		reg: regInfo{
25523			inputs: []inputInfo{
25524				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25525			},
25526			outputs: []outputInfo{
25527				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25528			},
25529		},
25530	},
25531	{
25532		name:        "XOR",
25533		argLen:      2,
25534		commutative: true,
25535		asm:         riscv.AXOR,
25536		reg: regInfo{
25537			inputs: []inputInfo{
25538				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25539				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25540			},
25541			outputs: []outputInfo{
25542				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25543			},
25544		},
25545	},
25546	{
25547		name:    "XORI",
25548		auxType: auxInt64,
25549		argLen:  1,
25550		asm:     riscv.AXORI,
25551		reg: regInfo{
25552			inputs: []inputInfo{
25553				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25554			},
25555			outputs: []outputInfo{
25556				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25557			},
25558		},
25559	},
25560	{
25561		name:        "OR",
25562		argLen:      2,
25563		commutative: true,
25564		asm:         riscv.AOR,
25565		reg: regInfo{
25566			inputs: []inputInfo{
25567				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25568				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25569			},
25570			outputs: []outputInfo{
25571				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25572			},
25573		},
25574	},
25575	{
25576		name:    "ORI",
25577		auxType: auxInt64,
25578		argLen:  1,
25579		asm:     riscv.AORI,
25580		reg: regInfo{
25581			inputs: []inputInfo{
25582				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25583			},
25584			outputs: []outputInfo{
25585				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25586			},
25587		},
25588	},
25589	{
25590		name:        "AND",
25591		argLen:      2,
25592		commutative: true,
25593		asm:         riscv.AAND,
25594		reg: regInfo{
25595			inputs: []inputInfo{
25596				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25597				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25598			},
25599			outputs: []outputInfo{
25600				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25601			},
25602		},
25603	},
25604	{
25605		name:    "ANDI",
25606		auxType: auxInt64,
25607		argLen:  1,
25608		asm:     riscv.AANDI,
25609		reg: regInfo{
25610			inputs: []inputInfo{
25611				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25612			},
25613			outputs: []outputInfo{
25614				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25615			},
25616		},
25617	},
25618	{
25619		name:   "SEQZ",
25620		argLen: 1,
25621		asm:    riscv.ASEQZ,
25622		reg: regInfo{
25623			inputs: []inputInfo{
25624				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25625			},
25626			outputs: []outputInfo{
25627				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25628			},
25629		},
25630	},
25631	{
25632		name:   "SNEZ",
25633		argLen: 1,
25634		asm:    riscv.ASNEZ,
25635		reg: regInfo{
25636			inputs: []inputInfo{
25637				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25638			},
25639			outputs: []outputInfo{
25640				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25641			},
25642		},
25643	},
25644	{
25645		name:   "SLT",
25646		argLen: 2,
25647		asm:    riscv.ASLT,
25648		reg: regInfo{
25649			inputs: []inputInfo{
25650				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25651				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25652			},
25653			outputs: []outputInfo{
25654				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25655			},
25656		},
25657	},
25658	{
25659		name:    "SLTI",
25660		auxType: auxInt64,
25661		argLen:  1,
25662		asm:     riscv.ASLTI,
25663		reg: regInfo{
25664			inputs: []inputInfo{
25665				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25666			},
25667			outputs: []outputInfo{
25668				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25669			},
25670		},
25671	},
25672	{
25673		name:   "SLTU",
25674		argLen: 2,
25675		asm:    riscv.ASLTU,
25676		reg: regInfo{
25677			inputs: []inputInfo{
25678				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25679				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25680			},
25681			outputs: []outputInfo{
25682				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25683			},
25684		},
25685	},
25686	{
25687		name:    "SLTIU",
25688		auxType: auxInt64,
25689		argLen:  1,
25690		asm:     riscv.ASLTIU,
25691		reg: regInfo{
25692			inputs: []inputInfo{
25693				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25694			},
25695			outputs: []outputInfo{
25696				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25697			},
25698		},
25699	},
25700	{
25701		name:   "MOVconvert",
25702		argLen: 2,
25703		asm:    riscv.AMOV,
25704		reg: regInfo{
25705			inputs: []inputInfo{
25706				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25707			},
25708			outputs: []outputInfo{
25709				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25710			},
25711		},
25712	},
25713	{
25714		name:      "CALLstatic",
25715		auxType:   auxSymOff,
25716		argLen:    1,
25717		call:      true,
25718		symEffect: SymNone,
25719		reg: regInfo{
25720			clobbers: 9223372035781033980, // X3 g X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25721		},
25722	},
25723	{
25724		name:    "CALLclosure",
25725		auxType: auxInt64,
25726		argLen:  3,
25727		call:    true,
25728		reg: regInfo{
25729			inputs: []inputInfo{
25730				{1, 524288},     // X20
25731				{0, 1073741814}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25732			},
25733			clobbers: 9223372035781033980, // X3 g X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25734		},
25735	},
25736	{
25737		name:    "CALLinter",
25738		auxType: auxInt64,
25739		argLen:  2,
25740		call:    true,
25741		reg: regInfo{
25742			inputs: []inputInfo{
25743				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25744			},
25745			clobbers: 9223372035781033980, // X3 g X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25746		},
25747	},
25748	{
25749		name:           "LoweredZero",
25750		auxType:        auxInt64,
25751		argLen:         3,
25752		faultOnNilArg0: true,
25753		reg: regInfo{
25754			inputs: []inputInfo{
25755				{0, 16},         // X5
25756				{1, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25757			},
25758			clobbers: 16, // X5
25759		},
25760	},
25761	{
25762		name:           "LoweredMove",
25763		auxType:        auxInt64,
25764		argLen:         4,
25765		faultOnNilArg0: true,
25766		faultOnNilArg1: true,
25767		reg: regInfo{
25768			inputs: []inputInfo{
25769				{0, 16},         // X5
25770				{1, 32},         // X6
25771				{2, 1073741748}, // X3 X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25772			},
25773			clobbers: 112, // X5 X6 X7
25774		},
25775	},
25776	{
25777		name:           "LoweredNilCheck",
25778		argLen:         2,
25779		nilCheck:       true,
25780		faultOnNilArg0: true,
25781		reg: regInfo{
25782			inputs: []inputInfo{
25783				{0, 1073741814}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25784			},
25785		},
25786	},
25787	{
25788		name:   "LoweredGetClosurePtr",
25789		argLen: 0,
25790		reg: regInfo{
25791			outputs: []outputInfo{
25792				{0, 524288}, // X20
25793			},
25794		},
25795	},
25796	{
25797		name:              "LoweredGetCallerSP",
25798		argLen:            0,
25799		rematerializeable: true,
25800		reg: regInfo{
25801			outputs: []outputInfo{
25802				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25803			},
25804		},
25805	},
25806	{
25807		name:              "LoweredGetCallerPC",
25808		argLen:            0,
25809		rematerializeable: true,
25810		reg: regInfo{
25811			outputs: []outputInfo{
25812				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25813			},
25814		},
25815	},
25816	{
25817		name:         "LoweredWB",
25818		auxType:      auxSym,
25819		argLen:       3,
25820		clobberFlags: true,
25821		symEffect:    SymNone,
25822		reg: regInfo{
25823			inputs: []inputInfo{
25824				{0, 16}, // X5
25825				{1, 32}, // X6
25826			},
25827			clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25828		},
25829	},
25830	{
25831		name:    "LoweredPanicBoundsA",
25832		auxType: auxInt64,
25833		argLen:  3,
25834		reg: regInfo{
25835			inputs: []inputInfo{
25836				{0, 64},        // X7
25837				{1, 134217728}, // X28
25838			},
25839		},
25840	},
25841	{
25842		name:    "LoweredPanicBoundsB",
25843		auxType: auxInt64,
25844		argLen:  3,
25845		reg: regInfo{
25846			inputs: []inputInfo{
25847				{0, 32}, // X6
25848				{1, 64}, // X7
25849			},
25850		},
25851	},
25852	{
25853		name:    "LoweredPanicBoundsC",
25854		auxType: auxInt64,
25855		argLen:  3,
25856		reg: regInfo{
25857			inputs: []inputInfo{
25858				{0, 16}, // X5
25859				{1, 32}, // X6
25860			},
25861		},
25862	},
25863	{
25864		name:        "FADDS",
25865		argLen:      2,
25866		commutative: true,
25867		asm:         riscv.AFADDS,
25868		reg: regInfo{
25869			inputs: []inputInfo{
25870				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25871				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25872			},
25873			outputs: []outputInfo{
25874				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25875			},
25876		},
25877	},
25878	{
25879		name:   "FSUBS",
25880		argLen: 2,
25881		asm:    riscv.AFSUBS,
25882		reg: regInfo{
25883			inputs: []inputInfo{
25884				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25885				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25886			},
25887			outputs: []outputInfo{
25888				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25889			},
25890		},
25891	},
25892	{
25893		name:        "FMULS",
25894		argLen:      2,
25895		commutative: true,
25896		asm:         riscv.AFMULS,
25897		reg: regInfo{
25898			inputs: []inputInfo{
25899				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25900				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25901			},
25902			outputs: []outputInfo{
25903				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25904			},
25905		},
25906	},
25907	{
25908		name:   "FDIVS",
25909		argLen: 2,
25910		asm:    riscv.AFDIVS,
25911		reg: regInfo{
25912			inputs: []inputInfo{
25913				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25914				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25915			},
25916			outputs: []outputInfo{
25917				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25918			},
25919		},
25920	},
25921	{
25922		name:   "FSQRTS",
25923		argLen: 1,
25924		asm:    riscv.AFSQRTS,
25925		reg: regInfo{
25926			inputs: []inputInfo{
25927				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25928			},
25929			outputs: []outputInfo{
25930				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25931			},
25932		},
25933	},
25934	{
25935		name:   "FNEGS",
25936		argLen: 1,
25937		asm:    riscv.AFNEGS,
25938		reg: regInfo{
25939			inputs: []inputInfo{
25940				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25941			},
25942			outputs: []outputInfo{
25943				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25944			},
25945		},
25946	},
25947	{
25948		name:   "FMVSX",
25949		argLen: 1,
25950		asm:    riscv.AFMVSX,
25951		reg: regInfo{
25952			inputs: []inputInfo{
25953				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25954			},
25955			outputs: []outputInfo{
25956				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25957			},
25958		},
25959	},
25960	{
25961		name:   "FCVTSW",
25962		argLen: 1,
25963		asm:    riscv.AFCVTSW,
25964		reg: regInfo{
25965			inputs: []inputInfo{
25966				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25967			},
25968			outputs: []outputInfo{
25969				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25970			},
25971		},
25972	},
25973	{
25974		name:   "FCVTSL",
25975		argLen: 1,
25976		asm:    riscv.AFCVTSL,
25977		reg: regInfo{
25978			inputs: []inputInfo{
25979				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25980			},
25981			outputs: []outputInfo{
25982				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25983			},
25984		},
25985	},
25986	{
25987		name:   "FCVTWS",
25988		argLen: 1,
25989		asm:    riscv.AFCVTWS,
25990		reg: regInfo{
25991			inputs: []inputInfo{
25992				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
25993			},
25994			outputs: []outputInfo{
25995				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
25996			},
25997		},
25998	},
25999	{
26000		name:   "FCVTLS",
26001		argLen: 1,
26002		asm:    riscv.AFCVTLS,
26003		reg: regInfo{
26004			inputs: []inputInfo{
26005				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26006			},
26007			outputs: []outputInfo{
26008				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26009			},
26010		},
26011	},
26012	{
26013		name:           "FMOVWload",
26014		auxType:        auxSymOff,
26015		argLen:         2,
26016		faultOnNilArg0: true,
26017		symEffect:      SymRead,
26018		asm:            riscv.AMOVF,
26019		reg: regInfo{
26020			inputs: []inputInfo{
26021				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
26022			},
26023			outputs: []outputInfo{
26024				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26025			},
26026		},
26027	},
26028	{
26029		name:           "FMOVWstore",
26030		auxType:        auxSymOff,
26031		argLen:         3,
26032		faultOnNilArg0: true,
26033		symEffect:      SymWrite,
26034		asm:            riscv.AMOVF,
26035		reg: regInfo{
26036			inputs: []inputInfo{
26037				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
26038				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26039			},
26040		},
26041	},
26042	{
26043		name:        "FEQS",
26044		argLen:      2,
26045		commutative: true,
26046		asm:         riscv.AFEQS,
26047		reg: regInfo{
26048			inputs: []inputInfo{
26049				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26050				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26051			},
26052			outputs: []outputInfo{
26053				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26054			},
26055		},
26056	},
26057	{
26058		name:        "FNES",
26059		argLen:      2,
26060		commutative: true,
26061		asm:         riscv.AFNES,
26062		reg: regInfo{
26063			inputs: []inputInfo{
26064				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26065				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26066			},
26067			outputs: []outputInfo{
26068				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26069			},
26070		},
26071	},
26072	{
26073		name:   "FLTS",
26074		argLen: 2,
26075		asm:    riscv.AFLTS,
26076		reg: regInfo{
26077			inputs: []inputInfo{
26078				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26079				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26080			},
26081			outputs: []outputInfo{
26082				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26083			},
26084		},
26085	},
26086	{
26087		name:   "FLES",
26088		argLen: 2,
26089		asm:    riscv.AFLES,
26090		reg: regInfo{
26091			inputs: []inputInfo{
26092				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26093				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26094			},
26095			outputs: []outputInfo{
26096				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26097			},
26098		},
26099	},
26100	{
26101		name:        "FADDD",
26102		argLen:      2,
26103		commutative: true,
26104		asm:         riscv.AFADDD,
26105		reg: regInfo{
26106			inputs: []inputInfo{
26107				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26108				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26109			},
26110			outputs: []outputInfo{
26111				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26112			},
26113		},
26114	},
26115	{
26116		name:   "FSUBD",
26117		argLen: 2,
26118		asm:    riscv.AFSUBD,
26119		reg: regInfo{
26120			inputs: []inputInfo{
26121				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26122				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26123			},
26124			outputs: []outputInfo{
26125				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26126			},
26127		},
26128	},
26129	{
26130		name:        "FMULD",
26131		argLen:      2,
26132		commutative: true,
26133		asm:         riscv.AFMULD,
26134		reg: regInfo{
26135			inputs: []inputInfo{
26136				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26137				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26138			},
26139			outputs: []outputInfo{
26140				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26141			},
26142		},
26143	},
26144	{
26145		name:   "FDIVD",
26146		argLen: 2,
26147		asm:    riscv.AFDIVD,
26148		reg: regInfo{
26149			inputs: []inputInfo{
26150				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26151				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26152			},
26153			outputs: []outputInfo{
26154				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26155			},
26156		},
26157	},
26158	{
26159		name:   "FSQRTD",
26160		argLen: 1,
26161		asm:    riscv.AFSQRTD,
26162		reg: regInfo{
26163			inputs: []inputInfo{
26164				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26165			},
26166			outputs: []outputInfo{
26167				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26168			},
26169		},
26170	},
26171	{
26172		name:   "FNEGD",
26173		argLen: 1,
26174		asm:    riscv.AFNEGD,
26175		reg: regInfo{
26176			inputs: []inputInfo{
26177				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26178			},
26179			outputs: []outputInfo{
26180				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26181			},
26182		},
26183	},
26184	{
26185		name:   "FMVDX",
26186		argLen: 1,
26187		asm:    riscv.AFMVDX,
26188		reg: regInfo{
26189			inputs: []inputInfo{
26190				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26191			},
26192			outputs: []outputInfo{
26193				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26194			},
26195		},
26196	},
26197	{
26198		name:   "FCVTDW",
26199		argLen: 1,
26200		asm:    riscv.AFCVTDW,
26201		reg: regInfo{
26202			inputs: []inputInfo{
26203				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26204			},
26205			outputs: []outputInfo{
26206				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26207			},
26208		},
26209	},
26210	{
26211		name:   "FCVTDL",
26212		argLen: 1,
26213		asm:    riscv.AFCVTDL,
26214		reg: regInfo{
26215			inputs: []inputInfo{
26216				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26217			},
26218			outputs: []outputInfo{
26219				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26220			},
26221		},
26222	},
26223	{
26224		name:   "FCVTWD",
26225		argLen: 1,
26226		asm:    riscv.AFCVTWD,
26227		reg: regInfo{
26228			inputs: []inputInfo{
26229				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26230			},
26231			outputs: []outputInfo{
26232				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26233			},
26234		},
26235	},
26236	{
26237		name:   "FCVTLD",
26238		argLen: 1,
26239		asm:    riscv.AFCVTLD,
26240		reg: regInfo{
26241			inputs: []inputInfo{
26242				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26243			},
26244			outputs: []outputInfo{
26245				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26246			},
26247		},
26248	},
26249	{
26250		name:   "FCVTDS",
26251		argLen: 1,
26252		asm:    riscv.AFCVTDS,
26253		reg: regInfo{
26254			inputs: []inputInfo{
26255				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26256			},
26257			outputs: []outputInfo{
26258				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26259			},
26260		},
26261	},
26262	{
26263		name:   "FCVTSD",
26264		argLen: 1,
26265		asm:    riscv.AFCVTSD,
26266		reg: regInfo{
26267			inputs: []inputInfo{
26268				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26269			},
26270			outputs: []outputInfo{
26271				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26272			},
26273		},
26274	},
26275	{
26276		name:           "FMOVDload",
26277		auxType:        auxSymOff,
26278		argLen:         2,
26279		faultOnNilArg0: true,
26280		symEffect:      SymRead,
26281		asm:            riscv.AMOVD,
26282		reg: regInfo{
26283			inputs: []inputInfo{
26284				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
26285			},
26286			outputs: []outputInfo{
26287				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26288			},
26289		},
26290	},
26291	{
26292		name:           "FMOVDstore",
26293		auxType:        auxSymOff,
26294		argLen:         3,
26295		faultOnNilArg0: true,
26296		symEffect:      SymWrite,
26297		asm:            riscv.AMOVD,
26298		reg: regInfo{
26299			inputs: []inputInfo{
26300				{0, 9223372037928517622}, // SP X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 SB
26301				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26302			},
26303		},
26304	},
26305	{
26306		name:        "FEQD",
26307		argLen:      2,
26308		commutative: true,
26309		asm:         riscv.AFEQD,
26310		reg: regInfo{
26311			inputs: []inputInfo{
26312				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26313				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26314			},
26315			outputs: []outputInfo{
26316				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26317			},
26318		},
26319	},
26320	{
26321		name:        "FNED",
26322		argLen:      2,
26323		commutative: true,
26324		asm:         riscv.AFNED,
26325		reg: regInfo{
26326			inputs: []inputInfo{
26327				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26328				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26329			},
26330			outputs: []outputInfo{
26331				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26332			},
26333		},
26334	},
26335	{
26336		name:   "FLTD",
26337		argLen: 2,
26338		asm:    riscv.AFLTD,
26339		reg: regInfo{
26340			inputs: []inputInfo{
26341				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26342				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26343			},
26344			outputs: []outputInfo{
26345				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26346			},
26347		},
26348	},
26349	{
26350		name:   "FLED",
26351		argLen: 2,
26352		asm:    riscv.AFLED,
26353		reg: regInfo{
26354			inputs: []inputInfo{
26355				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26356				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
26357			},
26358			outputs: []outputInfo{
26359				{0, 1073741812}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30
26360			},
26361		},
26362	},
26363
26364	{
26365		name:         "FADDS",
26366		argLen:       2,
26367		commutative:  true,
26368		resultInArg0: true,
26369		clobberFlags: true,
26370		asm:          s390x.AFADDS,
26371		reg: regInfo{
26372			inputs: []inputInfo{
26373				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26374				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26375			},
26376			outputs: []outputInfo{
26377				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26378			},
26379		},
26380	},
26381	{
26382		name:         "FADD",
26383		argLen:       2,
26384		commutative:  true,
26385		resultInArg0: true,
26386		clobberFlags: true,
26387		asm:          s390x.AFADD,
26388		reg: regInfo{
26389			inputs: []inputInfo{
26390				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26391				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26392			},
26393			outputs: []outputInfo{
26394				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26395			},
26396		},
26397	},
26398	{
26399		name:         "FSUBS",
26400		argLen:       2,
26401		resultInArg0: true,
26402		clobberFlags: true,
26403		asm:          s390x.AFSUBS,
26404		reg: regInfo{
26405			inputs: []inputInfo{
26406				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26407				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26408			},
26409			outputs: []outputInfo{
26410				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26411			},
26412		},
26413	},
26414	{
26415		name:         "FSUB",
26416		argLen:       2,
26417		resultInArg0: true,
26418		clobberFlags: true,
26419		asm:          s390x.AFSUB,
26420		reg: regInfo{
26421			inputs: []inputInfo{
26422				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26423				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26424			},
26425			outputs: []outputInfo{
26426				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26427			},
26428		},
26429	},
26430	{
26431		name:         "FMULS",
26432		argLen:       2,
26433		commutative:  true,
26434		resultInArg0: true,
26435		asm:          s390x.AFMULS,
26436		reg: regInfo{
26437			inputs: []inputInfo{
26438				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26439				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26440			},
26441			outputs: []outputInfo{
26442				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26443			},
26444		},
26445	},
26446	{
26447		name:         "FMUL",
26448		argLen:       2,
26449		commutative:  true,
26450		resultInArg0: true,
26451		asm:          s390x.AFMUL,
26452		reg: regInfo{
26453			inputs: []inputInfo{
26454				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26455				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26456			},
26457			outputs: []outputInfo{
26458				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26459			},
26460		},
26461	},
26462	{
26463		name:         "FDIVS",
26464		argLen:       2,
26465		resultInArg0: true,
26466		asm:          s390x.AFDIVS,
26467		reg: regInfo{
26468			inputs: []inputInfo{
26469				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26470				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26471			},
26472			outputs: []outputInfo{
26473				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26474			},
26475		},
26476	},
26477	{
26478		name:         "FDIV",
26479		argLen:       2,
26480		resultInArg0: true,
26481		asm:          s390x.AFDIV,
26482		reg: regInfo{
26483			inputs: []inputInfo{
26484				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26485				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26486			},
26487			outputs: []outputInfo{
26488				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26489			},
26490		},
26491	},
26492	{
26493		name:         "FNEGS",
26494		argLen:       1,
26495		clobberFlags: true,
26496		asm:          s390x.AFNEGS,
26497		reg: regInfo{
26498			inputs: []inputInfo{
26499				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26500			},
26501			outputs: []outputInfo{
26502				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26503			},
26504		},
26505	},
26506	{
26507		name:         "FNEG",
26508		argLen:       1,
26509		clobberFlags: true,
26510		asm:          s390x.AFNEG,
26511		reg: regInfo{
26512			inputs: []inputInfo{
26513				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26514			},
26515			outputs: []outputInfo{
26516				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26517			},
26518		},
26519	},
26520	{
26521		name:         "FMADDS",
26522		argLen:       3,
26523		resultInArg0: true,
26524		asm:          s390x.AFMADDS,
26525		reg: regInfo{
26526			inputs: []inputInfo{
26527				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26528				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26529				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26530			},
26531			outputs: []outputInfo{
26532				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26533			},
26534		},
26535	},
26536	{
26537		name:         "FMADD",
26538		argLen:       3,
26539		resultInArg0: true,
26540		asm:          s390x.AFMADD,
26541		reg: regInfo{
26542			inputs: []inputInfo{
26543				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26544				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26545				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26546			},
26547			outputs: []outputInfo{
26548				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26549			},
26550		},
26551	},
26552	{
26553		name:         "FMSUBS",
26554		argLen:       3,
26555		resultInArg0: true,
26556		asm:          s390x.AFMSUBS,
26557		reg: regInfo{
26558			inputs: []inputInfo{
26559				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26560				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26561				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26562			},
26563			outputs: []outputInfo{
26564				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26565			},
26566		},
26567	},
26568	{
26569		name:         "FMSUB",
26570		argLen:       3,
26571		resultInArg0: true,
26572		asm:          s390x.AFMSUB,
26573		reg: regInfo{
26574			inputs: []inputInfo{
26575				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26576				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26577				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26578			},
26579			outputs: []outputInfo{
26580				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26581			},
26582		},
26583	},
26584	{
26585		name:   "LPDFR",
26586		argLen: 1,
26587		asm:    s390x.ALPDFR,
26588		reg: regInfo{
26589			inputs: []inputInfo{
26590				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26591			},
26592			outputs: []outputInfo{
26593				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26594			},
26595		},
26596	},
26597	{
26598		name:   "LNDFR",
26599		argLen: 1,
26600		asm:    s390x.ALNDFR,
26601		reg: regInfo{
26602			inputs: []inputInfo{
26603				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26604			},
26605			outputs: []outputInfo{
26606				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26607			},
26608		},
26609	},
26610	{
26611		name:   "CPSDR",
26612		argLen: 2,
26613		asm:    s390x.ACPSDR,
26614		reg: regInfo{
26615			inputs: []inputInfo{
26616				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26617				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26618			},
26619			outputs: []outputInfo{
26620				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26621			},
26622		},
26623	},
26624	{
26625		name:    "FIDBR",
26626		auxType: auxInt8,
26627		argLen:  1,
26628		asm:     s390x.AFIDBR,
26629		reg: regInfo{
26630			inputs: []inputInfo{
26631				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26632			},
26633			outputs: []outputInfo{
26634				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26635			},
26636		},
26637	},
26638	{
26639		name:           "FMOVSload",
26640		auxType:        auxSymOff,
26641		argLen:         2,
26642		faultOnNilArg0: true,
26643		symEffect:      SymRead,
26644		asm:            s390x.AFMOVS,
26645		reg: regInfo{
26646			inputs: []inputInfo{
26647				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
26648			},
26649			outputs: []outputInfo{
26650				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26651			},
26652		},
26653	},
26654	{
26655		name:           "FMOVDload",
26656		auxType:        auxSymOff,
26657		argLen:         2,
26658		faultOnNilArg0: true,
26659		symEffect:      SymRead,
26660		asm:            s390x.AFMOVD,
26661		reg: regInfo{
26662			inputs: []inputInfo{
26663				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
26664			},
26665			outputs: []outputInfo{
26666				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26667			},
26668		},
26669	},
26670	{
26671		name:              "FMOVSconst",
26672		auxType:           auxFloat32,
26673		argLen:            0,
26674		rematerializeable: true,
26675		asm:               s390x.AFMOVS,
26676		reg: regInfo{
26677			outputs: []outputInfo{
26678				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26679			},
26680		},
26681	},
26682	{
26683		name:              "FMOVDconst",
26684		auxType:           auxFloat64,
26685		argLen:            0,
26686		rematerializeable: true,
26687		asm:               s390x.AFMOVD,
26688		reg: regInfo{
26689			outputs: []outputInfo{
26690				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26691			},
26692		},
26693	},
26694	{
26695		name:      "FMOVSloadidx",
26696		auxType:   auxSymOff,
26697		argLen:    3,
26698		symEffect: SymRead,
26699		asm:       s390x.AFMOVS,
26700		reg: regInfo{
26701			inputs: []inputInfo{
26702				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26703				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26704			},
26705			outputs: []outputInfo{
26706				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26707			},
26708		},
26709	},
26710	{
26711		name:      "FMOVDloadidx",
26712		auxType:   auxSymOff,
26713		argLen:    3,
26714		symEffect: SymRead,
26715		asm:       s390x.AFMOVD,
26716		reg: regInfo{
26717			inputs: []inputInfo{
26718				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26719				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26720			},
26721			outputs: []outputInfo{
26722				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26723			},
26724		},
26725	},
26726	{
26727		name:           "FMOVSstore",
26728		auxType:        auxSymOff,
26729		argLen:         3,
26730		faultOnNilArg0: true,
26731		symEffect:      SymWrite,
26732		asm:            s390x.AFMOVS,
26733		reg: regInfo{
26734			inputs: []inputInfo{
26735				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
26736				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26737			},
26738		},
26739	},
26740	{
26741		name:           "FMOVDstore",
26742		auxType:        auxSymOff,
26743		argLen:         3,
26744		faultOnNilArg0: true,
26745		symEffect:      SymWrite,
26746		asm:            s390x.AFMOVD,
26747		reg: regInfo{
26748			inputs: []inputInfo{
26749				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
26750				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26751			},
26752		},
26753	},
26754	{
26755		name:      "FMOVSstoreidx",
26756		auxType:   auxSymOff,
26757		argLen:    4,
26758		symEffect: SymWrite,
26759		asm:       s390x.AFMOVS,
26760		reg: regInfo{
26761			inputs: []inputInfo{
26762				{0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26763				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26764				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26765			},
26766		},
26767	},
26768	{
26769		name:      "FMOVDstoreidx",
26770		auxType:   auxSymOff,
26771		argLen:    4,
26772		symEffect: SymWrite,
26773		asm:       s390x.AFMOVD,
26774		reg: regInfo{
26775			inputs: []inputInfo{
26776				{0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26777				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26778				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
26779			},
26780		},
26781	},
26782	{
26783		name:         "ADD",
26784		argLen:       2,
26785		commutative:  true,
26786		clobberFlags: true,
26787		asm:          s390x.AADD,
26788		reg: regInfo{
26789			inputs: []inputInfo{
26790				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26791				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26792			},
26793			outputs: []outputInfo{
26794				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26795			},
26796		},
26797	},
26798	{
26799		name:         "ADDW",
26800		argLen:       2,
26801		commutative:  true,
26802		clobberFlags: true,
26803		asm:          s390x.AADDW,
26804		reg: regInfo{
26805			inputs: []inputInfo{
26806				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26807				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26808			},
26809			outputs: []outputInfo{
26810				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26811			},
26812		},
26813	},
26814	{
26815		name:         "ADDconst",
26816		auxType:      auxInt32,
26817		argLen:       1,
26818		clobberFlags: true,
26819		asm:          s390x.AADD,
26820		reg: regInfo{
26821			inputs: []inputInfo{
26822				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26823			},
26824			outputs: []outputInfo{
26825				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26826			},
26827		},
26828	},
26829	{
26830		name:         "ADDWconst",
26831		auxType:      auxInt32,
26832		argLen:       1,
26833		clobberFlags: true,
26834		asm:          s390x.AADDW,
26835		reg: regInfo{
26836			inputs: []inputInfo{
26837				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26838			},
26839			outputs: []outputInfo{
26840				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26841			},
26842		},
26843	},
26844	{
26845		name:           "ADDload",
26846		auxType:        auxSymOff,
26847		argLen:         3,
26848		resultInArg0:   true,
26849		clobberFlags:   true,
26850		faultOnNilArg1: true,
26851		symEffect:      SymRead,
26852		asm:            s390x.AADD,
26853		reg: regInfo{
26854			inputs: []inputInfo{
26855				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26856				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26857			},
26858			outputs: []outputInfo{
26859				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26860			},
26861		},
26862	},
26863	{
26864		name:           "ADDWload",
26865		auxType:        auxSymOff,
26866		argLen:         3,
26867		resultInArg0:   true,
26868		clobberFlags:   true,
26869		faultOnNilArg1: true,
26870		symEffect:      SymRead,
26871		asm:            s390x.AADDW,
26872		reg: regInfo{
26873			inputs: []inputInfo{
26874				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26875				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26876			},
26877			outputs: []outputInfo{
26878				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26879			},
26880		},
26881	},
26882	{
26883		name:         "SUB",
26884		argLen:       2,
26885		clobberFlags: true,
26886		asm:          s390x.ASUB,
26887		reg: regInfo{
26888			inputs: []inputInfo{
26889				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26890				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26891			},
26892			outputs: []outputInfo{
26893				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26894			},
26895		},
26896	},
26897	{
26898		name:         "SUBW",
26899		argLen:       2,
26900		clobberFlags: true,
26901		asm:          s390x.ASUBW,
26902		reg: regInfo{
26903			inputs: []inputInfo{
26904				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26905				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26906			},
26907			outputs: []outputInfo{
26908				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26909			},
26910		},
26911	},
26912	{
26913		name:         "SUBconst",
26914		auxType:      auxInt32,
26915		argLen:       1,
26916		resultInArg0: true,
26917		clobberFlags: true,
26918		asm:          s390x.ASUB,
26919		reg: regInfo{
26920			inputs: []inputInfo{
26921				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26922			},
26923			outputs: []outputInfo{
26924				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26925			},
26926		},
26927	},
26928	{
26929		name:         "SUBWconst",
26930		auxType:      auxInt32,
26931		argLen:       1,
26932		resultInArg0: true,
26933		clobberFlags: true,
26934		asm:          s390x.ASUBW,
26935		reg: regInfo{
26936			inputs: []inputInfo{
26937				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26938			},
26939			outputs: []outputInfo{
26940				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26941			},
26942		},
26943	},
26944	{
26945		name:           "SUBload",
26946		auxType:        auxSymOff,
26947		argLen:         3,
26948		resultInArg0:   true,
26949		clobberFlags:   true,
26950		faultOnNilArg1: true,
26951		symEffect:      SymRead,
26952		asm:            s390x.ASUB,
26953		reg: regInfo{
26954			inputs: []inputInfo{
26955				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26956				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26957			},
26958			outputs: []outputInfo{
26959				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26960			},
26961		},
26962	},
26963	{
26964		name:           "SUBWload",
26965		auxType:        auxSymOff,
26966		argLen:         3,
26967		resultInArg0:   true,
26968		clobberFlags:   true,
26969		faultOnNilArg1: true,
26970		symEffect:      SymRead,
26971		asm:            s390x.ASUBW,
26972		reg: regInfo{
26973			inputs: []inputInfo{
26974				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26975				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
26976			},
26977			outputs: []outputInfo{
26978				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26979			},
26980		},
26981	},
26982	{
26983		name:         "MULLD",
26984		argLen:       2,
26985		commutative:  true,
26986		resultInArg0: true,
26987		clobberFlags: true,
26988		asm:          s390x.AMULLD,
26989		reg: regInfo{
26990			inputs: []inputInfo{
26991				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26992				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26993			},
26994			outputs: []outputInfo{
26995				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
26996			},
26997		},
26998	},
26999	{
27000		name:         "MULLW",
27001		argLen:       2,
27002		commutative:  true,
27003		resultInArg0: true,
27004		clobberFlags: true,
27005		asm:          s390x.AMULLW,
27006		reg: regInfo{
27007			inputs: []inputInfo{
27008				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27009				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27010			},
27011			outputs: []outputInfo{
27012				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27013			},
27014		},
27015	},
27016	{
27017		name:         "MULLDconst",
27018		auxType:      auxInt32,
27019		argLen:       1,
27020		resultInArg0: true,
27021		clobberFlags: true,
27022		asm:          s390x.AMULLD,
27023		reg: regInfo{
27024			inputs: []inputInfo{
27025				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27026			},
27027			outputs: []outputInfo{
27028				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27029			},
27030		},
27031	},
27032	{
27033		name:         "MULLWconst",
27034		auxType:      auxInt32,
27035		argLen:       1,
27036		resultInArg0: true,
27037		clobberFlags: true,
27038		asm:          s390x.AMULLW,
27039		reg: regInfo{
27040			inputs: []inputInfo{
27041				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27042			},
27043			outputs: []outputInfo{
27044				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27045			},
27046		},
27047	},
27048	{
27049		name:           "MULLDload",
27050		auxType:        auxSymOff,
27051		argLen:         3,
27052		resultInArg0:   true,
27053		clobberFlags:   true,
27054		faultOnNilArg1: true,
27055		symEffect:      SymRead,
27056		asm:            s390x.AMULLD,
27057		reg: regInfo{
27058			inputs: []inputInfo{
27059				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27060				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27061			},
27062			outputs: []outputInfo{
27063				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27064			},
27065		},
27066	},
27067	{
27068		name:           "MULLWload",
27069		auxType:        auxSymOff,
27070		argLen:         3,
27071		resultInArg0:   true,
27072		clobberFlags:   true,
27073		faultOnNilArg1: true,
27074		symEffect:      SymRead,
27075		asm:            s390x.AMULLW,
27076		reg: regInfo{
27077			inputs: []inputInfo{
27078				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27079				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27080			},
27081			outputs: []outputInfo{
27082				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27083			},
27084		},
27085	},
27086	{
27087		name:         "MULHD",
27088		argLen:       2,
27089		commutative:  true,
27090		resultInArg0: true,
27091		clobberFlags: true,
27092		asm:          s390x.AMULHD,
27093		reg: regInfo{
27094			inputs: []inputInfo{
27095				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27096				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27097			},
27098			clobbers: 2048, // R11
27099			outputs: []outputInfo{
27100				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27101			},
27102		},
27103	},
27104	{
27105		name:         "MULHDU",
27106		argLen:       2,
27107		commutative:  true,
27108		resultInArg0: true,
27109		clobberFlags: true,
27110		asm:          s390x.AMULHDU,
27111		reg: regInfo{
27112			inputs: []inputInfo{
27113				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27114				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27115			},
27116			clobbers: 2048, // R11
27117			outputs: []outputInfo{
27118				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27119			},
27120		},
27121	},
27122	{
27123		name:         "DIVD",
27124		argLen:       2,
27125		resultInArg0: true,
27126		clobberFlags: true,
27127		asm:          s390x.ADIVD,
27128		reg: regInfo{
27129			inputs: []inputInfo{
27130				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27131				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27132			},
27133			clobbers: 2048, // R11
27134			outputs: []outputInfo{
27135				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27136			},
27137		},
27138	},
27139	{
27140		name:         "DIVW",
27141		argLen:       2,
27142		resultInArg0: true,
27143		clobberFlags: true,
27144		asm:          s390x.ADIVW,
27145		reg: regInfo{
27146			inputs: []inputInfo{
27147				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27148				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27149			},
27150			clobbers: 2048, // R11
27151			outputs: []outputInfo{
27152				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27153			},
27154		},
27155	},
27156	{
27157		name:         "DIVDU",
27158		argLen:       2,
27159		resultInArg0: true,
27160		clobberFlags: true,
27161		asm:          s390x.ADIVDU,
27162		reg: regInfo{
27163			inputs: []inputInfo{
27164				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27165				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27166			},
27167			clobbers: 2048, // R11
27168			outputs: []outputInfo{
27169				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27170			},
27171		},
27172	},
27173	{
27174		name:         "DIVWU",
27175		argLen:       2,
27176		resultInArg0: true,
27177		clobberFlags: true,
27178		asm:          s390x.ADIVWU,
27179		reg: regInfo{
27180			inputs: []inputInfo{
27181				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27182				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27183			},
27184			clobbers: 2048, // R11
27185			outputs: []outputInfo{
27186				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27187			},
27188		},
27189	},
27190	{
27191		name:         "MODD",
27192		argLen:       2,
27193		resultInArg0: true,
27194		clobberFlags: true,
27195		asm:          s390x.AMODD,
27196		reg: regInfo{
27197			inputs: []inputInfo{
27198				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27199				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27200			},
27201			clobbers: 2048, // R11
27202			outputs: []outputInfo{
27203				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27204			},
27205		},
27206	},
27207	{
27208		name:         "MODW",
27209		argLen:       2,
27210		resultInArg0: true,
27211		clobberFlags: true,
27212		asm:          s390x.AMODW,
27213		reg: regInfo{
27214			inputs: []inputInfo{
27215				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27216				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27217			},
27218			clobbers: 2048, // R11
27219			outputs: []outputInfo{
27220				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27221			},
27222		},
27223	},
27224	{
27225		name:         "MODDU",
27226		argLen:       2,
27227		resultInArg0: true,
27228		clobberFlags: true,
27229		asm:          s390x.AMODDU,
27230		reg: regInfo{
27231			inputs: []inputInfo{
27232				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27233				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27234			},
27235			clobbers: 2048, // R11
27236			outputs: []outputInfo{
27237				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27238			},
27239		},
27240	},
27241	{
27242		name:         "MODWU",
27243		argLen:       2,
27244		resultInArg0: true,
27245		clobberFlags: true,
27246		asm:          s390x.AMODWU,
27247		reg: regInfo{
27248			inputs: []inputInfo{
27249				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27250				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27251			},
27252			clobbers: 2048, // R11
27253			outputs: []outputInfo{
27254				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
27255			},
27256		},
27257	},
27258	{
27259		name:         "AND",
27260		argLen:       2,
27261		commutative:  true,
27262		clobberFlags: true,
27263		asm:          s390x.AAND,
27264		reg: regInfo{
27265			inputs: []inputInfo{
27266				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27267				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27268			},
27269			outputs: []outputInfo{
27270				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27271			},
27272		},
27273	},
27274	{
27275		name:         "ANDW",
27276		argLen:       2,
27277		commutative:  true,
27278		clobberFlags: true,
27279		asm:          s390x.AANDW,
27280		reg: regInfo{
27281			inputs: []inputInfo{
27282				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27283				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27284			},
27285			outputs: []outputInfo{
27286				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27287			},
27288		},
27289	},
27290	{
27291		name:         "ANDconst",
27292		auxType:      auxInt64,
27293		argLen:       1,
27294		resultInArg0: true,
27295		clobberFlags: true,
27296		asm:          s390x.AAND,
27297		reg: regInfo{
27298			inputs: []inputInfo{
27299				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27300			},
27301			outputs: []outputInfo{
27302				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27303			},
27304		},
27305	},
27306	{
27307		name:         "ANDWconst",
27308		auxType:      auxInt32,
27309		argLen:       1,
27310		resultInArg0: true,
27311		clobberFlags: true,
27312		asm:          s390x.AANDW,
27313		reg: regInfo{
27314			inputs: []inputInfo{
27315				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27316			},
27317			outputs: []outputInfo{
27318				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27319			},
27320		},
27321	},
27322	{
27323		name:           "ANDload",
27324		auxType:        auxSymOff,
27325		argLen:         3,
27326		resultInArg0:   true,
27327		clobberFlags:   true,
27328		faultOnNilArg1: true,
27329		symEffect:      SymRead,
27330		asm:            s390x.AAND,
27331		reg: regInfo{
27332			inputs: []inputInfo{
27333				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27334				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27335			},
27336			outputs: []outputInfo{
27337				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27338			},
27339		},
27340	},
27341	{
27342		name:           "ANDWload",
27343		auxType:        auxSymOff,
27344		argLen:         3,
27345		resultInArg0:   true,
27346		clobberFlags:   true,
27347		faultOnNilArg1: true,
27348		symEffect:      SymRead,
27349		asm:            s390x.AANDW,
27350		reg: regInfo{
27351			inputs: []inputInfo{
27352				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27353				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27354			},
27355			outputs: []outputInfo{
27356				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27357			},
27358		},
27359	},
27360	{
27361		name:         "OR",
27362		argLen:       2,
27363		commutative:  true,
27364		clobberFlags: true,
27365		asm:          s390x.AOR,
27366		reg: regInfo{
27367			inputs: []inputInfo{
27368				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27369				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27370			},
27371			outputs: []outputInfo{
27372				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27373			},
27374		},
27375	},
27376	{
27377		name:         "ORW",
27378		argLen:       2,
27379		commutative:  true,
27380		clobberFlags: true,
27381		asm:          s390x.AORW,
27382		reg: regInfo{
27383			inputs: []inputInfo{
27384				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27385				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27386			},
27387			outputs: []outputInfo{
27388				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27389			},
27390		},
27391	},
27392	{
27393		name:         "ORconst",
27394		auxType:      auxInt64,
27395		argLen:       1,
27396		resultInArg0: true,
27397		clobberFlags: true,
27398		asm:          s390x.AOR,
27399		reg: regInfo{
27400			inputs: []inputInfo{
27401				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27402			},
27403			outputs: []outputInfo{
27404				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27405			},
27406		},
27407	},
27408	{
27409		name:         "ORWconst",
27410		auxType:      auxInt32,
27411		argLen:       1,
27412		resultInArg0: true,
27413		clobberFlags: true,
27414		asm:          s390x.AORW,
27415		reg: regInfo{
27416			inputs: []inputInfo{
27417				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27418			},
27419			outputs: []outputInfo{
27420				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27421			},
27422		},
27423	},
27424	{
27425		name:           "ORload",
27426		auxType:        auxSymOff,
27427		argLen:         3,
27428		resultInArg0:   true,
27429		clobberFlags:   true,
27430		faultOnNilArg1: true,
27431		symEffect:      SymRead,
27432		asm:            s390x.AOR,
27433		reg: regInfo{
27434			inputs: []inputInfo{
27435				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27436				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27437			},
27438			outputs: []outputInfo{
27439				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27440			},
27441		},
27442	},
27443	{
27444		name:           "ORWload",
27445		auxType:        auxSymOff,
27446		argLen:         3,
27447		resultInArg0:   true,
27448		clobberFlags:   true,
27449		faultOnNilArg1: true,
27450		symEffect:      SymRead,
27451		asm:            s390x.AORW,
27452		reg: regInfo{
27453			inputs: []inputInfo{
27454				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27455				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27456			},
27457			outputs: []outputInfo{
27458				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27459			},
27460		},
27461	},
27462	{
27463		name:         "XOR",
27464		argLen:       2,
27465		commutative:  true,
27466		clobberFlags: true,
27467		asm:          s390x.AXOR,
27468		reg: regInfo{
27469			inputs: []inputInfo{
27470				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27471				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27472			},
27473			outputs: []outputInfo{
27474				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27475			},
27476		},
27477	},
27478	{
27479		name:         "XORW",
27480		argLen:       2,
27481		commutative:  true,
27482		clobberFlags: true,
27483		asm:          s390x.AXORW,
27484		reg: regInfo{
27485			inputs: []inputInfo{
27486				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27487				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27488			},
27489			outputs: []outputInfo{
27490				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27491			},
27492		},
27493	},
27494	{
27495		name:         "XORconst",
27496		auxType:      auxInt64,
27497		argLen:       1,
27498		resultInArg0: true,
27499		clobberFlags: true,
27500		asm:          s390x.AXOR,
27501		reg: regInfo{
27502			inputs: []inputInfo{
27503				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27504			},
27505			outputs: []outputInfo{
27506				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27507			},
27508		},
27509	},
27510	{
27511		name:         "XORWconst",
27512		auxType:      auxInt32,
27513		argLen:       1,
27514		resultInArg0: true,
27515		clobberFlags: true,
27516		asm:          s390x.AXORW,
27517		reg: regInfo{
27518			inputs: []inputInfo{
27519				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27520			},
27521			outputs: []outputInfo{
27522				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27523			},
27524		},
27525	},
27526	{
27527		name:           "XORload",
27528		auxType:        auxSymOff,
27529		argLen:         3,
27530		resultInArg0:   true,
27531		clobberFlags:   true,
27532		faultOnNilArg1: true,
27533		symEffect:      SymRead,
27534		asm:            s390x.AXOR,
27535		reg: regInfo{
27536			inputs: []inputInfo{
27537				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27538				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27539			},
27540			outputs: []outputInfo{
27541				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27542			},
27543		},
27544	},
27545	{
27546		name:           "XORWload",
27547		auxType:        auxSymOff,
27548		argLen:         3,
27549		resultInArg0:   true,
27550		clobberFlags:   true,
27551		faultOnNilArg1: true,
27552		symEffect:      SymRead,
27553		asm:            s390x.AXORW,
27554		reg: regInfo{
27555			inputs: []inputInfo{
27556				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27557				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27558			},
27559			outputs: []outputInfo{
27560				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27561			},
27562		},
27563	},
27564	{
27565		name:        "ADDC",
27566		argLen:      2,
27567		commutative: true,
27568		asm:         s390x.AADDC,
27569		reg: regInfo{
27570			inputs: []inputInfo{
27571				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27572				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27573			},
27574			outputs: []outputInfo{
27575				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27576			},
27577		},
27578	},
27579	{
27580		name:    "ADDCconst",
27581		auxType: auxInt16,
27582		argLen:  1,
27583		asm:     s390x.AADDC,
27584		reg: regInfo{
27585			inputs: []inputInfo{
27586				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27587			},
27588			outputs: []outputInfo{
27589				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27590			},
27591		},
27592	},
27593	{
27594		name:         "ADDE",
27595		argLen:       3,
27596		commutative:  true,
27597		resultInArg0: true,
27598		asm:          s390x.AADDE,
27599		reg: regInfo{
27600			inputs: []inputInfo{
27601				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27602				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27603			},
27604			outputs: []outputInfo{
27605				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27606			},
27607		},
27608	},
27609	{
27610		name:   "SUBC",
27611		argLen: 2,
27612		asm:    s390x.ASUBC,
27613		reg: regInfo{
27614			inputs: []inputInfo{
27615				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27616				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27617			},
27618			outputs: []outputInfo{
27619				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27620			},
27621		},
27622	},
27623	{
27624		name:         "SUBE",
27625		argLen:       3,
27626		resultInArg0: true,
27627		asm:          s390x.ASUBE,
27628		reg: regInfo{
27629			inputs: []inputInfo{
27630				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27631				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27632			},
27633			outputs: []outputInfo{
27634				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27635			},
27636		},
27637	},
27638	{
27639		name:   "CMP",
27640		argLen: 2,
27641		asm:    s390x.ACMP,
27642		reg: regInfo{
27643			inputs: []inputInfo{
27644				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27645				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27646			},
27647		},
27648	},
27649	{
27650		name:   "CMPW",
27651		argLen: 2,
27652		asm:    s390x.ACMPW,
27653		reg: regInfo{
27654			inputs: []inputInfo{
27655				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27656				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27657			},
27658		},
27659	},
27660	{
27661		name:   "CMPU",
27662		argLen: 2,
27663		asm:    s390x.ACMPU,
27664		reg: regInfo{
27665			inputs: []inputInfo{
27666				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27667				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27668			},
27669		},
27670	},
27671	{
27672		name:   "CMPWU",
27673		argLen: 2,
27674		asm:    s390x.ACMPWU,
27675		reg: regInfo{
27676			inputs: []inputInfo{
27677				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27678				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27679			},
27680		},
27681	},
27682	{
27683		name:    "CMPconst",
27684		auxType: auxInt32,
27685		argLen:  1,
27686		asm:     s390x.ACMP,
27687		reg: regInfo{
27688			inputs: []inputInfo{
27689				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27690			},
27691		},
27692	},
27693	{
27694		name:    "CMPWconst",
27695		auxType: auxInt32,
27696		argLen:  1,
27697		asm:     s390x.ACMPW,
27698		reg: regInfo{
27699			inputs: []inputInfo{
27700				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27701			},
27702		},
27703	},
27704	{
27705		name:    "CMPUconst",
27706		auxType: auxInt32,
27707		argLen:  1,
27708		asm:     s390x.ACMPU,
27709		reg: regInfo{
27710			inputs: []inputInfo{
27711				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27712			},
27713		},
27714	},
27715	{
27716		name:    "CMPWUconst",
27717		auxType: auxInt32,
27718		argLen:  1,
27719		asm:     s390x.ACMPWU,
27720		reg: regInfo{
27721			inputs: []inputInfo{
27722				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
27723			},
27724		},
27725	},
27726	{
27727		name:   "FCMPS",
27728		argLen: 2,
27729		asm:    s390x.ACEBR,
27730		reg: regInfo{
27731			inputs: []inputInfo{
27732				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
27733				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
27734			},
27735		},
27736	},
27737	{
27738		name:   "FCMP",
27739		argLen: 2,
27740		asm:    s390x.AFCMPU,
27741		reg: regInfo{
27742			inputs: []inputInfo{
27743				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
27744				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
27745			},
27746		},
27747	},
27748	{
27749		name:   "SLD",
27750		argLen: 2,
27751		asm:    s390x.ASLD,
27752		reg: regInfo{
27753			inputs: []inputInfo{
27754				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27755				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27756			},
27757			outputs: []outputInfo{
27758				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27759			},
27760		},
27761	},
27762	{
27763		name:   "SLW",
27764		argLen: 2,
27765		asm:    s390x.ASLW,
27766		reg: regInfo{
27767			inputs: []inputInfo{
27768				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27769				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27770			},
27771			outputs: []outputInfo{
27772				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27773			},
27774		},
27775	},
27776	{
27777		name:    "SLDconst",
27778		auxType: auxInt8,
27779		argLen:  1,
27780		asm:     s390x.ASLD,
27781		reg: regInfo{
27782			inputs: []inputInfo{
27783				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27784			},
27785			outputs: []outputInfo{
27786				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27787			},
27788		},
27789	},
27790	{
27791		name:    "SLWconst",
27792		auxType: auxInt8,
27793		argLen:  1,
27794		asm:     s390x.ASLW,
27795		reg: regInfo{
27796			inputs: []inputInfo{
27797				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27798			},
27799			outputs: []outputInfo{
27800				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27801			},
27802		},
27803	},
27804	{
27805		name:   "SRD",
27806		argLen: 2,
27807		asm:    s390x.ASRD,
27808		reg: regInfo{
27809			inputs: []inputInfo{
27810				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27811				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27812			},
27813			outputs: []outputInfo{
27814				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27815			},
27816		},
27817	},
27818	{
27819		name:   "SRW",
27820		argLen: 2,
27821		asm:    s390x.ASRW,
27822		reg: regInfo{
27823			inputs: []inputInfo{
27824				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27825				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27826			},
27827			outputs: []outputInfo{
27828				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27829			},
27830		},
27831	},
27832	{
27833		name:    "SRDconst",
27834		auxType: auxInt8,
27835		argLen:  1,
27836		asm:     s390x.ASRD,
27837		reg: regInfo{
27838			inputs: []inputInfo{
27839				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27840			},
27841			outputs: []outputInfo{
27842				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27843			},
27844		},
27845	},
27846	{
27847		name:    "SRWconst",
27848		auxType: auxInt8,
27849		argLen:  1,
27850		asm:     s390x.ASRW,
27851		reg: regInfo{
27852			inputs: []inputInfo{
27853				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27854			},
27855			outputs: []outputInfo{
27856				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27857			},
27858		},
27859	},
27860	{
27861		name:         "SRAD",
27862		argLen:       2,
27863		clobberFlags: true,
27864		asm:          s390x.ASRAD,
27865		reg: regInfo{
27866			inputs: []inputInfo{
27867				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27868				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27869			},
27870			outputs: []outputInfo{
27871				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27872			},
27873		},
27874	},
27875	{
27876		name:         "SRAW",
27877		argLen:       2,
27878		clobberFlags: true,
27879		asm:          s390x.ASRAW,
27880		reg: regInfo{
27881			inputs: []inputInfo{
27882				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27883				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27884			},
27885			outputs: []outputInfo{
27886				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27887			},
27888		},
27889	},
27890	{
27891		name:         "SRADconst",
27892		auxType:      auxInt8,
27893		argLen:       1,
27894		clobberFlags: true,
27895		asm:          s390x.ASRAD,
27896		reg: regInfo{
27897			inputs: []inputInfo{
27898				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27899			},
27900			outputs: []outputInfo{
27901				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27902			},
27903		},
27904	},
27905	{
27906		name:         "SRAWconst",
27907		auxType:      auxInt8,
27908		argLen:       1,
27909		clobberFlags: true,
27910		asm:          s390x.ASRAW,
27911		reg: regInfo{
27912			inputs: []inputInfo{
27913				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27914			},
27915			outputs: []outputInfo{
27916				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27917			},
27918		},
27919	},
27920	{
27921		name:   "RLLG",
27922		argLen: 2,
27923		asm:    s390x.ARLLG,
27924		reg: regInfo{
27925			inputs: []inputInfo{
27926				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27927				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27928			},
27929			outputs: []outputInfo{
27930				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27931			},
27932		},
27933	},
27934	{
27935		name:   "RLL",
27936		argLen: 2,
27937		asm:    s390x.ARLL,
27938		reg: regInfo{
27939			inputs: []inputInfo{
27940				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27941				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27942			},
27943			outputs: []outputInfo{
27944				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27945			},
27946		},
27947	},
27948	{
27949		name:    "RLLGconst",
27950		auxType: auxInt8,
27951		argLen:  1,
27952		asm:     s390x.ARLLG,
27953		reg: regInfo{
27954			inputs: []inputInfo{
27955				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27956			},
27957			outputs: []outputInfo{
27958				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27959			},
27960		},
27961	},
27962	{
27963		name:    "RLLconst",
27964		auxType: auxInt8,
27965		argLen:  1,
27966		asm:     s390x.ARLL,
27967		reg: regInfo{
27968			inputs: []inputInfo{
27969				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27970			},
27971			outputs: []outputInfo{
27972				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27973			},
27974		},
27975	},
27976	{
27977		name:         "RXSBG",
27978		auxType:      auxArchSpecific,
27979		argLen:       2,
27980		resultInArg0: true,
27981		clobberFlags: true,
27982		asm:          s390x.ARXSBG,
27983		reg: regInfo{
27984			inputs: []inputInfo{
27985				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27986				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27987			},
27988			outputs: []outputInfo{
27989				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
27990			},
27991		},
27992	},
27993	{
27994		name:         "NEG",
27995		argLen:       1,
27996		clobberFlags: true,
27997		asm:          s390x.ANEG,
27998		reg: regInfo{
27999			inputs: []inputInfo{
28000				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28001			},
28002			outputs: []outputInfo{
28003				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28004			},
28005		},
28006	},
28007	{
28008		name:         "NEGW",
28009		argLen:       1,
28010		clobberFlags: true,
28011		asm:          s390x.ANEGW,
28012		reg: regInfo{
28013			inputs: []inputInfo{
28014				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28015			},
28016			outputs: []outputInfo{
28017				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28018			},
28019		},
28020	},
28021	{
28022		name:         "NOT",
28023		argLen:       1,
28024		resultInArg0: true,
28025		clobberFlags: true,
28026		reg: regInfo{
28027			inputs: []inputInfo{
28028				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28029			},
28030			outputs: []outputInfo{
28031				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28032			},
28033		},
28034	},
28035	{
28036		name:         "NOTW",
28037		argLen:       1,
28038		resultInArg0: true,
28039		clobberFlags: true,
28040		reg: regInfo{
28041			inputs: []inputInfo{
28042				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28043			},
28044			outputs: []outputInfo{
28045				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28046			},
28047		},
28048	},
28049	{
28050		name:   "FSQRT",
28051		argLen: 1,
28052		asm:    s390x.AFSQRT,
28053		reg: regInfo{
28054			inputs: []inputInfo{
28055				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28056			},
28057			outputs: []outputInfo{
28058				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28059			},
28060		},
28061	},
28062	{
28063		name:         "LOCGR",
28064		auxType:      auxArchSpecific,
28065		argLen:       3,
28066		resultInArg0: true,
28067		asm:          s390x.ALOCGR,
28068		reg: regInfo{
28069			inputs: []inputInfo{
28070				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28071				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28072			},
28073			outputs: []outputInfo{
28074				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28075			},
28076		},
28077	},
28078	{
28079		name:   "MOVBreg",
28080		argLen: 1,
28081		asm:    s390x.AMOVB,
28082		reg: regInfo{
28083			inputs: []inputInfo{
28084				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28085			},
28086			outputs: []outputInfo{
28087				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28088			},
28089		},
28090	},
28091	{
28092		name:   "MOVBZreg",
28093		argLen: 1,
28094		asm:    s390x.AMOVBZ,
28095		reg: regInfo{
28096			inputs: []inputInfo{
28097				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28098			},
28099			outputs: []outputInfo{
28100				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28101			},
28102		},
28103	},
28104	{
28105		name:   "MOVHreg",
28106		argLen: 1,
28107		asm:    s390x.AMOVH,
28108		reg: regInfo{
28109			inputs: []inputInfo{
28110				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28111			},
28112			outputs: []outputInfo{
28113				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28114			},
28115		},
28116	},
28117	{
28118		name:   "MOVHZreg",
28119		argLen: 1,
28120		asm:    s390x.AMOVHZ,
28121		reg: regInfo{
28122			inputs: []inputInfo{
28123				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28124			},
28125			outputs: []outputInfo{
28126				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28127			},
28128		},
28129	},
28130	{
28131		name:   "MOVWreg",
28132		argLen: 1,
28133		asm:    s390x.AMOVW,
28134		reg: regInfo{
28135			inputs: []inputInfo{
28136				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28137			},
28138			outputs: []outputInfo{
28139				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28140			},
28141		},
28142	},
28143	{
28144		name:   "MOVWZreg",
28145		argLen: 1,
28146		asm:    s390x.AMOVWZ,
28147		reg: regInfo{
28148			inputs: []inputInfo{
28149				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28150			},
28151			outputs: []outputInfo{
28152				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28153			},
28154		},
28155	},
28156	{
28157		name:              "MOVDconst",
28158		auxType:           auxInt64,
28159		argLen:            0,
28160		rematerializeable: true,
28161		asm:               s390x.AMOVD,
28162		reg: regInfo{
28163			outputs: []outputInfo{
28164				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28165			},
28166		},
28167	},
28168	{
28169		name:   "LDGR",
28170		argLen: 1,
28171		asm:    s390x.ALDGR,
28172		reg: regInfo{
28173			inputs: []inputInfo{
28174				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28175			},
28176			outputs: []outputInfo{
28177				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28178			},
28179		},
28180	},
28181	{
28182		name:   "LGDR",
28183		argLen: 1,
28184		asm:    s390x.ALGDR,
28185		reg: regInfo{
28186			inputs: []inputInfo{
28187				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28188			},
28189			outputs: []outputInfo{
28190				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28191			},
28192		},
28193	},
28194	{
28195		name:   "CFDBRA",
28196		argLen: 1,
28197		asm:    s390x.ACFDBRA,
28198		reg: regInfo{
28199			inputs: []inputInfo{
28200				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28201			},
28202			outputs: []outputInfo{
28203				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28204			},
28205		},
28206	},
28207	{
28208		name:   "CGDBRA",
28209		argLen: 1,
28210		asm:    s390x.ACGDBRA,
28211		reg: regInfo{
28212			inputs: []inputInfo{
28213				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28214			},
28215			outputs: []outputInfo{
28216				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28217			},
28218		},
28219	},
28220	{
28221		name:   "CFEBRA",
28222		argLen: 1,
28223		asm:    s390x.ACFEBRA,
28224		reg: regInfo{
28225			inputs: []inputInfo{
28226				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28227			},
28228			outputs: []outputInfo{
28229				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28230			},
28231		},
28232	},
28233	{
28234		name:   "CGEBRA",
28235		argLen: 1,
28236		asm:    s390x.ACGEBRA,
28237		reg: regInfo{
28238			inputs: []inputInfo{
28239				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28240			},
28241			outputs: []outputInfo{
28242				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28243			},
28244		},
28245	},
28246	{
28247		name:   "CEFBRA",
28248		argLen: 1,
28249		asm:    s390x.ACEFBRA,
28250		reg: regInfo{
28251			inputs: []inputInfo{
28252				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28253			},
28254			outputs: []outputInfo{
28255				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28256			},
28257		},
28258	},
28259	{
28260		name:   "CDFBRA",
28261		argLen: 1,
28262		asm:    s390x.ACDFBRA,
28263		reg: regInfo{
28264			inputs: []inputInfo{
28265				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28266			},
28267			outputs: []outputInfo{
28268				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28269			},
28270		},
28271	},
28272	{
28273		name:   "CEGBRA",
28274		argLen: 1,
28275		asm:    s390x.ACEGBRA,
28276		reg: regInfo{
28277			inputs: []inputInfo{
28278				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28279			},
28280			outputs: []outputInfo{
28281				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28282			},
28283		},
28284	},
28285	{
28286		name:   "CDGBRA",
28287		argLen: 1,
28288		asm:    s390x.ACDGBRA,
28289		reg: regInfo{
28290			inputs: []inputInfo{
28291				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28292			},
28293			outputs: []outputInfo{
28294				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28295			},
28296		},
28297	},
28298	{
28299		name:   "LEDBR",
28300		argLen: 1,
28301		asm:    s390x.ALEDBR,
28302		reg: regInfo{
28303			inputs: []inputInfo{
28304				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28305			},
28306			outputs: []outputInfo{
28307				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28308			},
28309		},
28310	},
28311	{
28312		name:   "LDEBR",
28313		argLen: 1,
28314		asm:    s390x.ALDEBR,
28315		reg: regInfo{
28316			inputs: []inputInfo{
28317				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28318			},
28319			outputs: []outputInfo{
28320				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
28321			},
28322		},
28323	},
28324	{
28325		name:              "MOVDaddr",
28326		auxType:           auxSymOff,
28327		argLen:            1,
28328		rematerializeable: true,
28329		symEffect:         SymRead,
28330		reg: regInfo{
28331			inputs: []inputInfo{
28332				{0, 4295000064}, // SP SB
28333			},
28334			outputs: []outputInfo{
28335				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28336			},
28337		},
28338	},
28339	{
28340		name:      "MOVDaddridx",
28341		auxType:   auxSymOff,
28342		argLen:    2,
28343		symEffect: SymRead,
28344		reg: regInfo{
28345			inputs: []inputInfo{
28346				{0, 4295000064}, // SP SB
28347				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28348			},
28349			outputs: []outputInfo{
28350				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28351			},
28352		},
28353	},
28354	{
28355		name:           "MOVBZload",
28356		auxType:        auxSymOff,
28357		argLen:         2,
28358		faultOnNilArg0: true,
28359		symEffect:      SymRead,
28360		asm:            s390x.AMOVBZ,
28361		reg: regInfo{
28362			inputs: []inputInfo{
28363				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28364			},
28365			outputs: []outputInfo{
28366				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28367			},
28368		},
28369	},
28370	{
28371		name:           "MOVBload",
28372		auxType:        auxSymOff,
28373		argLen:         2,
28374		faultOnNilArg0: true,
28375		symEffect:      SymRead,
28376		asm:            s390x.AMOVB,
28377		reg: regInfo{
28378			inputs: []inputInfo{
28379				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28380			},
28381			outputs: []outputInfo{
28382				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28383			},
28384		},
28385	},
28386	{
28387		name:           "MOVHZload",
28388		auxType:        auxSymOff,
28389		argLen:         2,
28390		faultOnNilArg0: true,
28391		symEffect:      SymRead,
28392		asm:            s390x.AMOVHZ,
28393		reg: regInfo{
28394			inputs: []inputInfo{
28395				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28396			},
28397			outputs: []outputInfo{
28398				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28399			},
28400		},
28401	},
28402	{
28403		name:           "MOVHload",
28404		auxType:        auxSymOff,
28405		argLen:         2,
28406		faultOnNilArg0: true,
28407		symEffect:      SymRead,
28408		asm:            s390x.AMOVH,
28409		reg: regInfo{
28410			inputs: []inputInfo{
28411				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28412			},
28413			outputs: []outputInfo{
28414				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28415			},
28416		},
28417	},
28418	{
28419		name:           "MOVWZload",
28420		auxType:        auxSymOff,
28421		argLen:         2,
28422		faultOnNilArg0: true,
28423		symEffect:      SymRead,
28424		asm:            s390x.AMOVWZ,
28425		reg: regInfo{
28426			inputs: []inputInfo{
28427				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28428			},
28429			outputs: []outputInfo{
28430				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28431			},
28432		},
28433	},
28434	{
28435		name:           "MOVWload",
28436		auxType:        auxSymOff,
28437		argLen:         2,
28438		faultOnNilArg0: true,
28439		symEffect:      SymRead,
28440		asm:            s390x.AMOVW,
28441		reg: regInfo{
28442			inputs: []inputInfo{
28443				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28444			},
28445			outputs: []outputInfo{
28446				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28447			},
28448		},
28449	},
28450	{
28451		name:           "MOVDload",
28452		auxType:        auxSymOff,
28453		argLen:         2,
28454		faultOnNilArg0: true,
28455		symEffect:      SymRead,
28456		asm:            s390x.AMOVD,
28457		reg: regInfo{
28458			inputs: []inputInfo{
28459				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28460			},
28461			outputs: []outputInfo{
28462				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28463			},
28464		},
28465	},
28466	{
28467		name:   "MOVWBR",
28468		argLen: 1,
28469		asm:    s390x.AMOVWBR,
28470		reg: regInfo{
28471			inputs: []inputInfo{
28472				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28473			},
28474			outputs: []outputInfo{
28475				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28476			},
28477		},
28478	},
28479	{
28480		name:   "MOVDBR",
28481		argLen: 1,
28482		asm:    s390x.AMOVDBR,
28483		reg: regInfo{
28484			inputs: []inputInfo{
28485				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28486			},
28487			outputs: []outputInfo{
28488				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28489			},
28490		},
28491	},
28492	{
28493		name:           "MOVHBRload",
28494		auxType:        auxSymOff,
28495		argLen:         2,
28496		faultOnNilArg0: true,
28497		symEffect:      SymRead,
28498		asm:            s390x.AMOVHBR,
28499		reg: regInfo{
28500			inputs: []inputInfo{
28501				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28502			},
28503			outputs: []outputInfo{
28504				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28505			},
28506		},
28507	},
28508	{
28509		name:           "MOVWBRload",
28510		auxType:        auxSymOff,
28511		argLen:         2,
28512		faultOnNilArg0: true,
28513		symEffect:      SymRead,
28514		asm:            s390x.AMOVWBR,
28515		reg: regInfo{
28516			inputs: []inputInfo{
28517				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28518			},
28519			outputs: []outputInfo{
28520				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28521			},
28522		},
28523	},
28524	{
28525		name:           "MOVDBRload",
28526		auxType:        auxSymOff,
28527		argLen:         2,
28528		faultOnNilArg0: true,
28529		symEffect:      SymRead,
28530		asm:            s390x.AMOVDBR,
28531		reg: regInfo{
28532			inputs: []inputInfo{
28533				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28534			},
28535			outputs: []outputInfo{
28536				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28537			},
28538		},
28539	},
28540	{
28541		name:           "MOVBstore",
28542		auxType:        auxSymOff,
28543		argLen:         3,
28544		faultOnNilArg0: true,
28545		symEffect:      SymWrite,
28546		asm:            s390x.AMOVB,
28547		reg: regInfo{
28548			inputs: []inputInfo{
28549				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28550				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28551			},
28552		},
28553	},
28554	{
28555		name:           "MOVHstore",
28556		auxType:        auxSymOff,
28557		argLen:         3,
28558		faultOnNilArg0: true,
28559		symEffect:      SymWrite,
28560		asm:            s390x.AMOVH,
28561		reg: regInfo{
28562			inputs: []inputInfo{
28563				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28564				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28565			},
28566		},
28567	},
28568	{
28569		name:           "MOVWstore",
28570		auxType:        auxSymOff,
28571		argLen:         3,
28572		faultOnNilArg0: true,
28573		symEffect:      SymWrite,
28574		asm:            s390x.AMOVW,
28575		reg: regInfo{
28576			inputs: []inputInfo{
28577				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28578				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28579			},
28580		},
28581	},
28582	{
28583		name:           "MOVDstore",
28584		auxType:        auxSymOff,
28585		argLen:         3,
28586		faultOnNilArg0: true,
28587		symEffect:      SymWrite,
28588		asm:            s390x.AMOVD,
28589		reg: regInfo{
28590			inputs: []inputInfo{
28591				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28592				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28593			},
28594		},
28595	},
28596	{
28597		name:           "MOVHBRstore",
28598		auxType:        auxSymOff,
28599		argLen:         3,
28600		faultOnNilArg0: true,
28601		symEffect:      SymWrite,
28602		asm:            s390x.AMOVHBR,
28603		reg: regInfo{
28604			inputs: []inputInfo{
28605				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28606				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28607			},
28608		},
28609	},
28610	{
28611		name:           "MOVWBRstore",
28612		auxType:        auxSymOff,
28613		argLen:         3,
28614		faultOnNilArg0: true,
28615		symEffect:      SymWrite,
28616		asm:            s390x.AMOVWBR,
28617		reg: regInfo{
28618			inputs: []inputInfo{
28619				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28620				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28621			},
28622		},
28623	},
28624	{
28625		name:           "MOVDBRstore",
28626		auxType:        auxSymOff,
28627		argLen:         3,
28628		faultOnNilArg0: true,
28629		symEffect:      SymWrite,
28630		asm:            s390x.AMOVDBR,
28631		reg: regInfo{
28632			inputs: []inputInfo{
28633				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28634				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28635			},
28636		},
28637	},
28638	{
28639		name:           "MVC",
28640		auxType:        auxSymValAndOff,
28641		argLen:         3,
28642		clobberFlags:   true,
28643		faultOnNilArg0: true,
28644		faultOnNilArg1: true,
28645		symEffect:      SymNone,
28646		asm:            s390x.AMVC,
28647		reg: regInfo{
28648			inputs: []inputInfo{
28649				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28650				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28651			},
28652		},
28653	},
28654	{
28655		name:        "MOVBZloadidx",
28656		auxType:     auxSymOff,
28657		argLen:      3,
28658		commutative: true,
28659		symEffect:   SymRead,
28660		asm:         s390x.AMOVBZ,
28661		reg: regInfo{
28662			inputs: []inputInfo{
28663				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28664				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28665			},
28666			outputs: []outputInfo{
28667				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28668			},
28669		},
28670	},
28671	{
28672		name:        "MOVBloadidx",
28673		auxType:     auxSymOff,
28674		argLen:      3,
28675		commutative: true,
28676		symEffect:   SymRead,
28677		asm:         s390x.AMOVB,
28678		reg: regInfo{
28679			inputs: []inputInfo{
28680				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28681				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28682			},
28683			outputs: []outputInfo{
28684				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28685			},
28686		},
28687	},
28688	{
28689		name:        "MOVHZloadidx",
28690		auxType:     auxSymOff,
28691		argLen:      3,
28692		commutative: true,
28693		symEffect:   SymRead,
28694		asm:         s390x.AMOVHZ,
28695		reg: regInfo{
28696			inputs: []inputInfo{
28697				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28698				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28699			},
28700			outputs: []outputInfo{
28701				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28702			},
28703		},
28704	},
28705	{
28706		name:        "MOVHloadidx",
28707		auxType:     auxSymOff,
28708		argLen:      3,
28709		commutative: true,
28710		symEffect:   SymRead,
28711		asm:         s390x.AMOVH,
28712		reg: regInfo{
28713			inputs: []inputInfo{
28714				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28715				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28716			},
28717			outputs: []outputInfo{
28718				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28719			},
28720		},
28721	},
28722	{
28723		name:        "MOVWZloadidx",
28724		auxType:     auxSymOff,
28725		argLen:      3,
28726		commutative: true,
28727		symEffect:   SymRead,
28728		asm:         s390x.AMOVWZ,
28729		reg: regInfo{
28730			inputs: []inputInfo{
28731				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28732				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28733			},
28734			outputs: []outputInfo{
28735				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28736			},
28737		},
28738	},
28739	{
28740		name:        "MOVWloadidx",
28741		auxType:     auxSymOff,
28742		argLen:      3,
28743		commutative: true,
28744		symEffect:   SymRead,
28745		asm:         s390x.AMOVW,
28746		reg: regInfo{
28747			inputs: []inputInfo{
28748				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28749				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28750			},
28751			outputs: []outputInfo{
28752				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28753			},
28754		},
28755	},
28756	{
28757		name:        "MOVDloadidx",
28758		auxType:     auxSymOff,
28759		argLen:      3,
28760		commutative: true,
28761		symEffect:   SymRead,
28762		asm:         s390x.AMOVD,
28763		reg: regInfo{
28764			inputs: []inputInfo{
28765				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28766				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28767			},
28768			outputs: []outputInfo{
28769				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28770			},
28771		},
28772	},
28773	{
28774		name:        "MOVHBRloadidx",
28775		auxType:     auxSymOff,
28776		argLen:      3,
28777		commutative: true,
28778		symEffect:   SymRead,
28779		asm:         s390x.AMOVHBR,
28780		reg: regInfo{
28781			inputs: []inputInfo{
28782				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28783				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28784			},
28785			outputs: []outputInfo{
28786				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28787			},
28788		},
28789	},
28790	{
28791		name:        "MOVWBRloadidx",
28792		auxType:     auxSymOff,
28793		argLen:      3,
28794		commutative: true,
28795		symEffect:   SymRead,
28796		asm:         s390x.AMOVWBR,
28797		reg: regInfo{
28798			inputs: []inputInfo{
28799				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28800				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28801			},
28802			outputs: []outputInfo{
28803				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28804			},
28805		},
28806	},
28807	{
28808		name:        "MOVDBRloadidx",
28809		auxType:     auxSymOff,
28810		argLen:      3,
28811		commutative: true,
28812		symEffect:   SymRead,
28813		asm:         s390x.AMOVDBR,
28814		reg: regInfo{
28815			inputs: []inputInfo{
28816				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28817				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28818			},
28819			outputs: []outputInfo{
28820				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28821			},
28822		},
28823	},
28824	{
28825		name:        "MOVBstoreidx",
28826		auxType:     auxSymOff,
28827		argLen:      4,
28828		commutative: true,
28829		symEffect:   SymWrite,
28830		asm:         s390x.AMOVB,
28831		reg: regInfo{
28832			inputs: []inputInfo{
28833				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28834				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28835				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28836			},
28837		},
28838	},
28839	{
28840		name:        "MOVHstoreidx",
28841		auxType:     auxSymOff,
28842		argLen:      4,
28843		commutative: true,
28844		symEffect:   SymWrite,
28845		asm:         s390x.AMOVH,
28846		reg: regInfo{
28847			inputs: []inputInfo{
28848				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28849				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28850				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28851			},
28852		},
28853	},
28854	{
28855		name:        "MOVWstoreidx",
28856		auxType:     auxSymOff,
28857		argLen:      4,
28858		commutative: true,
28859		symEffect:   SymWrite,
28860		asm:         s390x.AMOVW,
28861		reg: regInfo{
28862			inputs: []inputInfo{
28863				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28864				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28865				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28866			},
28867		},
28868	},
28869	{
28870		name:        "MOVDstoreidx",
28871		auxType:     auxSymOff,
28872		argLen:      4,
28873		commutative: true,
28874		symEffect:   SymWrite,
28875		asm:         s390x.AMOVD,
28876		reg: regInfo{
28877			inputs: []inputInfo{
28878				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28879				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28880				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28881			},
28882		},
28883	},
28884	{
28885		name:        "MOVHBRstoreidx",
28886		auxType:     auxSymOff,
28887		argLen:      4,
28888		commutative: true,
28889		symEffect:   SymWrite,
28890		asm:         s390x.AMOVHBR,
28891		reg: regInfo{
28892			inputs: []inputInfo{
28893				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28894				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28895				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28896			},
28897		},
28898	},
28899	{
28900		name:        "MOVWBRstoreidx",
28901		auxType:     auxSymOff,
28902		argLen:      4,
28903		commutative: true,
28904		symEffect:   SymWrite,
28905		asm:         s390x.AMOVWBR,
28906		reg: regInfo{
28907			inputs: []inputInfo{
28908				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28909				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28910				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28911			},
28912		},
28913	},
28914	{
28915		name:        "MOVDBRstoreidx",
28916		auxType:     auxSymOff,
28917		argLen:      4,
28918		commutative: true,
28919		symEffect:   SymWrite,
28920		asm:         s390x.AMOVDBR,
28921		reg: regInfo{
28922			inputs: []inputInfo{
28923				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28924				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28925				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
28926			},
28927		},
28928	},
28929	{
28930		name:           "MOVBstoreconst",
28931		auxType:        auxSymValAndOff,
28932		argLen:         2,
28933		faultOnNilArg0: true,
28934		symEffect:      SymWrite,
28935		asm:            s390x.AMOVB,
28936		reg: regInfo{
28937			inputs: []inputInfo{
28938				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28939			},
28940		},
28941	},
28942	{
28943		name:           "MOVHstoreconst",
28944		auxType:        auxSymValAndOff,
28945		argLen:         2,
28946		faultOnNilArg0: true,
28947		symEffect:      SymWrite,
28948		asm:            s390x.AMOVH,
28949		reg: regInfo{
28950			inputs: []inputInfo{
28951				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28952			},
28953		},
28954	},
28955	{
28956		name:           "MOVWstoreconst",
28957		auxType:        auxSymValAndOff,
28958		argLen:         2,
28959		faultOnNilArg0: true,
28960		symEffect:      SymWrite,
28961		asm:            s390x.AMOVW,
28962		reg: regInfo{
28963			inputs: []inputInfo{
28964				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28965			},
28966		},
28967	},
28968	{
28969		name:           "MOVDstoreconst",
28970		auxType:        auxSymValAndOff,
28971		argLen:         2,
28972		faultOnNilArg0: true,
28973		symEffect:      SymWrite,
28974		asm:            s390x.AMOVD,
28975		reg: regInfo{
28976			inputs: []inputInfo{
28977				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
28978			},
28979		},
28980	},
28981	{
28982		name:           "CLEAR",
28983		auxType:        auxSymValAndOff,
28984		argLen:         2,
28985		clobberFlags:   true,
28986		faultOnNilArg0: true,
28987		symEffect:      SymWrite,
28988		asm:            s390x.ACLEAR,
28989		reg: regInfo{
28990			inputs: []inputInfo{
28991				{0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
28992			},
28993		},
28994	},
28995	{
28996		name:         "CALLstatic",
28997		auxType:      auxSymOff,
28998		argLen:       1,
28999		clobberFlags: true,
29000		call:         true,
29001		symEffect:    SymNone,
29002		reg: regInfo{
29003			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29004		},
29005	},
29006	{
29007		name:         "CALLclosure",
29008		auxType:      auxInt64,
29009		argLen:       3,
29010		clobberFlags: true,
29011		call:         true,
29012		reg: regInfo{
29013			inputs: []inputInfo{
29014				{1, 4096},  // R12
29015				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29016			},
29017			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29018		},
29019	},
29020	{
29021		name:         "CALLinter",
29022		auxType:      auxInt64,
29023		argLen:       2,
29024		clobberFlags: true,
29025		call:         true,
29026		reg: regInfo{
29027			inputs: []inputInfo{
29028				{0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29029			},
29030			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29031		},
29032	},
29033	{
29034		name:   "InvertFlags",
29035		argLen: 1,
29036		reg:    regInfo{},
29037	},
29038	{
29039		name:   "LoweredGetG",
29040		argLen: 1,
29041		reg: regInfo{
29042			outputs: []outputInfo{
29043				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29044			},
29045		},
29046	},
29047	{
29048		name:      "LoweredGetClosurePtr",
29049		argLen:    0,
29050		zeroWidth: true,
29051		reg: regInfo{
29052			outputs: []outputInfo{
29053				{0, 4096}, // R12
29054			},
29055		},
29056	},
29057	{
29058		name:              "LoweredGetCallerSP",
29059		argLen:            0,
29060		rematerializeable: true,
29061		reg: regInfo{
29062			outputs: []outputInfo{
29063				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29064			},
29065		},
29066	},
29067	{
29068		name:              "LoweredGetCallerPC",
29069		argLen:            0,
29070		rematerializeable: true,
29071		reg: regInfo{
29072			outputs: []outputInfo{
29073				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29074			},
29075		},
29076	},
29077	{
29078		name:           "LoweredNilCheck",
29079		argLen:         2,
29080		clobberFlags:   true,
29081		nilCheck:       true,
29082		faultOnNilArg0: true,
29083		reg: regInfo{
29084			inputs: []inputInfo{
29085				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29086			},
29087		},
29088	},
29089	{
29090		name:         "LoweredRound32F",
29091		argLen:       1,
29092		resultInArg0: true,
29093		zeroWidth:    true,
29094		reg: regInfo{
29095			inputs: []inputInfo{
29096				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29097			},
29098			outputs: []outputInfo{
29099				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29100			},
29101		},
29102	},
29103	{
29104		name:         "LoweredRound64F",
29105		argLen:       1,
29106		resultInArg0: true,
29107		zeroWidth:    true,
29108		reg: regInfo{
29109			inputs: []inputInfo{
29110				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29111			},
29112			outputs: []outputInfo{
29113				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29114			},
29115		},
29116	},
29117	{
29118		name:         "LoweredWB",
29119		auxType:      auxSym,
29120		argLen:       3,
29121		clobberFlags: true,
29122		symEffect:    SymNone,
29123		reg: regInfo{
29124			inputs: []inputInfo{
29125				{0, 4}, // R2
29126				{1, 8}, // R3
29127			},
29128			clobbers: 4294918144, // R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29129		},
29130	},
29131	{
29132		name:    "LoweredPanicBoundsA",
29133		auxType: auxInt64,
29134		argLen:  3,
29135		reg: regInfo{
29136			inputs: []inputInfo{
29137				{0, 4}, // R2
29138				{1, 8}, // R3
29139			},
29140		},
29141	},
29142	{
29143		name:    "LoweredPanicBoundsB",
29144		auxType: auxInt64,
29145		argLen:  3,
29146		reg: regInfo{
29147			inputs: []inputInfo{
29148				{0, 2}, // R1
29149				{1, 4}, // R2
29150			},
29151		},
29152	},
29153	{
29154		name:    "LoweredPanicBoundsC",
29155		auxType: auxInt64,
29156		argLen:  3,
29157		reg: regInfo{
29158			inputs: []inputInfo{
29159				{0, 1}, // R0
29160				{1, 2}, // R1
29161			},
29162		},
29163	},
29164	{
29165		name:   "FlagEQ",
29166		argLen: 0,
29167		reg:    regInfo{},
29168	},
29169	{
29170		name:   "FlagLT",
29171		argLen: 0,
29172		reg:    regInfo{},
29173	},
29174	{
29175		name:   "FlagGT",
29176		argLen: 0,
29177		reg:    regInfo{},
29178	},
29179	{
29180		name:   "FlagOV",
29181		argLen: 0,
29182		reg:    regInfo{},
29183	},
29184	{
29185		name:   "SYNC",
29186		argLen: 1,
29187		asm:    s390x.ASYNC,
29188		reg:    regInfo{},
29189	},
29190	{
29191		name:           "MOVBZatomicload",
29192		auxType:        auxSymOff,
29193		argLen:         2,
29194		faultOnNilArg0: true,
29195		symEffect:      SymRead,
29196		asm:            s390x.AMOVBZ,
29197		reg: regInfo{
29198			inputs: []inputInfo{
29199				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
29200			},
29201			outputs: []outputInfo{
29202				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29203			},
29204		},
29205	},
29206	{
29207		name:           "MOVWZatomicload",
29208		auxType:        auxSymOff,
29209		argLen:         2,
29210		faultOnNilArg0: true,
29211		symEffect:      SymRead,
29212		asm:            s390x.AMOVWZ,
29213		reg: regInfo{
29214			inputs: []inputInfo{
29215				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
29216			},
29217			outputs: []outputInfo{
29218				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29219			},
29220		},
29221	},
29222	{
29223		name:           "MOVDatomicload",
29224		auxType:        auxSymOff,
29225		argLen:         2,
29226		faultOnNilArg0: true,
29227		symEffect:      SymRead,
29228		asm:            s390x.AMOVD,
29229		reg: regInfo{
29230			inputs: []inputInfo{
29231				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
29232			},
29233			outputs: []outputInfo{
29234				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29235			},
29236		},
29237	},
29238	{
29239		name:           "MOVBatomicstore",
29240		auxType:        auxSymOff,
29241		argLen:         3,
29242		clobberFlags:   true,
29243		faultOnNilArg0: true,
29244		hasSideEffects: true,
29245		symEffect:      SymWrite,
29246		asm:            s390x.AMOVB,
29247		reg: regInfo{
29248			inputs: []inputInfo{
29249				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
29250				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29251			},
29252		},
29253	},
29254	{
29255		name:           "MOVWatomicstore",
29256		auxType:        auxSymOff,
29257		argLen:         3,
29258		clobberFlags:   true,
29259		faultOnNilArg0: true,
29260		hasSideEffects: true,
29261		symEffect:      SymWrite,
29262		asm:            s390x.AMOVW,
29263		reg: regInfo{
29264			inputs: []inputInfo{
29265				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
29266				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29267			},
29268		},
29269	},
29270	{
29271		name:           "MOVDatomicstore",
29272		auxType:        auxSymOff,
29273		argLen:         3,
29274		clobberFlags:   true,
29275		faultOnNilArg0: true,
29276		hasSideEffects: true,
29277		symEffect:      SymWrite,
29278		asm:            s390x.AMOVD,
29279		reg: regInfo{
29280			inputs: []inputInfo{
29281				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
29282				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29283			},
29284		},
29285	},
29286	{
29287		name:           "LAA",
29288		auxType:        auxSymOff,
29289		argLen:         3,
29290		clobberFlags:   true,
29291		faultOnNilArg0: true,
29292		hasSideEffects: true,
29293		symEffect:      SymRdWr,
29294		asm:            s390x.ALAA,
29295		reg: regInfo{
29296			inputs: []inputInfo{
29297				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
29298				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29299			},
29300			outputs: []outputInfo{
29301				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29302			},
29303		},
29304	},
29305	{
29306		name:           "LAAG",
29307		auxType:        auxSymOff,
29308		argLen:         3,
29309		clobberFlags:   true,
29310		faultOnNilArg0: true,
29311		hasSideEffects: true,
29312		symEffect:      SymRdWr,
29313		asm:            s390x.ALAAG,
29314		reg: regInfo{
29315			inputs: []inputInfo{
29316				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
29317				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29318			},
29319			outputs: []outputInfo{
29320				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29321			},
29322		},
29323	},
29324	{
29325		name:   "AddTupleFirst32",
29326		argLen: 2,
29327		reg:    regInfo{},
29328	},
29329	{
29330		name:   "AddTupleFirst64",
29331		argLen: 2,
29332		reg:    regInfo{},
29333	},
29334	{
29335		name:           "LAOfloor",
29336		argLen:         3,
29337		clobberFlags:   true,
29338		hasSideEffects: true,
29339		asm:            s390x.ALAO,
29340		reg: regInfo{
29341			inputs: []inputInfo{
29342				{0, 2},     // R1
29343				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29344			},
29345			clobbers: 2, // R1
29346		},
29347	},
29348	{
29349		name:           "LANfloor",
29350		argLen:         3,
29351		clobberFlags:   true,
29352		hasSideEffects: true,
29353		asm:            s390x.ALAN,
29354		reg: regInfo{
29355			inputs: []inputInfo{
29356				{0, 2},     // R1
29357				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29358			},
29359			clobbers: 2, // R1
29360		},
29361	},
29362	{
29363		name:           "LoweredAtomicCas32",
29364		auxType:        auxSymOff,
29365		argLen:         4,
29366		clobberFlags:   true,
29367		faultOnNilArg0: true,
29368		hasSideEffects: true,
29369		symEffect:      SymRdWr,
29370		asm:            s390x.ACS,
29371		reg: regInfo{
29372			inputs: []inputInfo{
29373				{1, 1},     // R0
29374				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29375				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29376			},
29377			clobbers: 1, // R0
29378			outputs: []outputInfo{
29379				{1, 0},
29380				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29381			},
29382		},
29383	},
29384	{
29385		name:           "LoweredAtomicCas64",
29386		auxType:        auxSymOff,
29387		argLen:         4,
29388		clobberFlags:   true,
29389		faultOnNilArg0: true,
29390		hasSideEffects: true,
29391		symEffect:      SymRdWr,
29392		asm:            s390x.ACSG,
29393		reg: regInfo{
29394			inputs: []inputInfo{
29395				{1, 1},     // R0
29396				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29397				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29398			},
29399			clobbers: 1, // R0
29400			outputs: []outputInfo{
29401				{1, 0},
29402				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29403			},
29404		},
29405	},
29406	{
29407		name:           "LoweredAtomicExchange32",
29408		auxType:        auxSymOff,
29409		argLen:         3,
29410		clobberFlags:   true,
29411		faultOnNilArg0: true,
29412		hasSideEffects: true,
29413		symEffect:      SymRdWr,
29414		asm:            s390x.ACS,
29415		reg: regInfo{
29416			inputs: []inputInfo{
29417				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29418				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29419			},
29420			outputs: []outputInfo{
29421				{1, 0},
29422				{0, 1}, // R0
29423			},
29424		},
29425	},
29426	{
29427		name:           "LoweredAtomicExchange64",
29428		auxType:        auxSymOff,
29429		argLen:         3,
29430		clobberFlags:   true,
29431		faultOnNilArg0: true,
29432		hasSideEffects: true,
29433		symEffect:      SymRdWr,
29434		asm:            s390x.ACSG,
29435		reg: regInfo{
29436			inputs: []inputInfo{
29437				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29438				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29439			},
29440			outputs: []outputInfo{
29441				{1, 0},
29442				{0, 1}, // R0
29443			},
29444		},
29445	},
29446	{
29447		name:         "FLOGR",
29448		argLen:       1,
29449		clobberFlags: true,
29450		asm:          s390x.AFLOGR,
29451		reg: regInfo{
29452			inputs: []inputInfo{
29453				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29454			},
29455			clobbers: 2, // R1
29456			outputs: []outputInfo{
29457				{0, 1}, // R0
29458			},
29459		},
29460	},
29461	{
29462		name:         "POPCNT",
29463		argLen:       1,
29464		clobberFlags: true,
29465		asm:          s390x.APOPCNT,
29466		reg: regInfo{
29467			inputs: []inputInfo{
29468				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29469			},
29470			outputs: []outputInfo{
29471				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29472			},
29473		},
29474	},
29475	{
29476		name:   "MLGR",
29477		argLen: 2,
29478		asm:    s390x.AMLGR,
29479		reg: regInfo{
29480			inputs: []inputInfo{
29481				{1, 8},     // R3
29482				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
29483			},
29484			outputs: []outputInfo{
29485				{0, 4}, // R2
29486				{1, 8}, // R3
29487			},
29488		},
29489	},
29490	{
29491		name:   "SumBytes2",
29492		argLen: 1,
29493		reg:    regInfo{},
29494	},
29495	{
29496		name:   "SumBytes4",
29497		argLen: 1,
29498		reg:    regInfo{},
29499	},
29500	{
29501		name:   "SumBytes8",
29502		argLen: 1,
29503		reg:    regInfo{},
29504	},
29505	{
29506		name:           "STMG2",
29507		auxType:        auxSymOff,
29508		argLen:         4,
29509		faultOnNilArg0: true,
29510		symEffect:      SymWrite,
29511		asm:            s390x.ASTMG,
29512		reg: regInfo{
29513			inputs: []inputInfo{
29514				{1, 2},     // R1
29515				{2, 4},     // R2
29516				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29517			},
29518		},
29519	},
29520	{
29521		name:           "STMG3",
29522		auxType:        auxSymOff,
29523		argLen:         5,
29524		faultOnNilArg0: true,
29525		symEffect:      SymWrite,
29526		asm:            s390x.ASTMG,
29527		reg: regInfo{
29528			inputs: []inputInfo{
29529				{1, 2},     // R1
29530				{2, 4},     // R2
29531				{3, 8},     // R3
29532				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29533			},
29534		},
29535	},
29536	{
29537		name:           "STMG4",
29538		auxType:        auxSymOff,
29539		argLen:         6,
29540		faultOnNilArg0: true,
29541		symEffect:      SymWrite,
29542		asm:            s390x.ASTMG,
29543		reg: regInfo{
29544			inputs: []inputInfo{
29545				{1, 2},     // R1
29546				{2, 4},     // R2
29547				{3, 8},     // R3
29548				{4, 16},    // R4
29549				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29550			},
29551		},
29552	},
29553	{
29554		name:           "STM2",
29555		auxType:        auxSymOff,
29556		argLen:         4,
29557		faultOnNilArg0: true,
29558		symEffect:      SymWrite,
29559		asm:            s390x.ASTMY,
29560		reg: regInfo{
29561			inputs: []inputInfo{
29562				{1, 2},     // R1
29563				{2, 4},     // R2
29564				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29565			},
29566		},
29567	},
29568	{
29569		name:           "STM3",
29570		auxType:        auxSymOff,
29571		argLen:         5,
29572		faultOnNilArg0: true,
29573		symEffect:      SymWrite,
29574		asm:            s390x.ASTMY,
29575		reg: regInfo{
29576			inputs: []inputInfo{
29577				{1, 2},     // R1
29578				{2, 4},     // R2
29579				{3, 8},     // R3
29580				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29581			},
29582		},
29583	},
29584	{
29585		name:           "STM4",
29586		auxType:        auxSymOff,
29587		argLen:         6,
29588		faultOnNilArg0: true,
29589		symEffect:      SymWrite,
29590		asm:            s390x.ASTMY,
29591		reg: regInfo{
29592			inputs: []inputInfo{
29593				{1, 2},     // R1
29594				{2, 4},     // R2
29595				{3, 8},     // R3
29596				{4, 16},    // R4
29597				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29598			},
29599		},
29600	},
29601	{
29602		name:           "LoweredMove",
29603		auxType:        auxInt64,
29604		argLen:         4,
29605		clobberFlags:   true,
29606		faultOnNilArg0: true,
29607		faultOnNilArg1: true,
29608		reg: regInfo{
29609			inputs: []inputInfo{
29610				{0, 2},     // R1
29611				{1, 4},     // R2
29612				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29613			},
29614			clobbers: 6, // R1 R2
29615		},
29616	},
29617	{
29618		name:           "LoweredZero",
29619		auxType:        auxInt64,
29620		argLen:         3,
29621		clobberFlags:   true,
29622		faultOnNilArg0: true,
29623		reg: regInfo{
29624			inputs: []inputInfo{
29625				{0, 2},     // R1
29626				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
29627			},
29628			clobbers: 2, // R1
29629		},
29630	},
29631
29632	{
29633		name:      "LoweredStaticCall",
29634		auxType:   auxSymOff,
29635		argLen:    1,
29636		call:      true,
29637		symEffect: SymNone,
29638		reg: regInfo{
29639			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
29640		},
29641	},
29642	{
29643		name:    "LoweredClosureCall",
29644		auxType: auxInt64,
29645		argLen:  3,
29646		call:    true,
29647		reg: regInfo{
29648			inputs: []inputInfo{
29649				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29650				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29651			},
29652			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
29653		},
29654	},
29655	{
29656		name:    "LoweredInterCall",
29657		auxType: auxInt64,
29658		argLen:  2,
29659		call:    true,
29660		reg: regInfo{
29661			inputs: []inputInfo{
29662				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29663			},
29664			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
29665		},
29666	},
29667	{
29668		name:              "LoweredAddr",
29669		auxType:           auxSymOff,
29670		argLen:            1,
29671		rematerializeable: true,
29672		symEffect:         SymAddr,
29673		reg: regInfo{
29674			inputs: []inputInfo{
29675				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
29676			},
29677			outputs: []outputInfo{
29678				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29679			},
29680		},
29681	},
29682	{
29683		name:    "LoweredMove",
29684		auxType: auxInt64,
29685		argLen:  3,
29686		reg: regInfo{
29687			inputs: []inputInfo{
29688				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29689				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29690			},
29691		},
29692	},
29693	{
29694		name:    "LoweredZero",
29695		auxType: auxInt64,
29696		argLen:  2,
29697		reg: regInfo{
29698			inputs: []inputInfo{
29699				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29700			},
29701		},
29702	},
29703	{
29704		name:   "LoweredGetClosurePtr",
29705		argLen: 0,
29706		reg: regInfo{
29707			outputs: []outputInfo{
29708				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29709			},
29710		},
29711	},
29712	{
29713		name:              "LoweredGetCallerPC",
29714		argLen:            0,
29715		rematerializeable: true,
29716		reg: regInfo{
29717			outputs: []outputInfo{
29718				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29719			},
29720		},
29721	},
29722	{
29723		name:              "LoweredGetCallerSP",
29724		argLen:            0,
29725		rematerializeable: true,
29726		reg: regInfo{
29727			outputs: []outputInfo{
29728				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29729			},
29730		},
29731	},
29732	{
29733		name:           "LoweredNilCheck",
29734		argLen:         2,
29735		nilCheck:       true,
29736		faultOnNilArg0: true,
29737		reg: regInfo{
29738			inputs: []inputInfo{
29739				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29740			},
29741		},
29742	},
29743	{
29744		name:      "LoweredWB",
29745		auxType:   auxSym,
29746		argLen:    3,
29747		symEffect: SymNone,
29748		reg: regInfo{
29749			inputs: []inputInfo{
29750				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29751				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29752			},
29753		},
29754	},
29755	{
29756		name:   "LoweredConvert",
29757		argLen: 2,
29758		reg: regInfo{
29759			inputs: []inputInfo{
29760				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29761			},
29762			outputs: []outputInfo{
29763				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29764			},
29765		},
29766	},
29767	{
29768		name:   "Select",
29769		argLen: 3,
29770		asm:    wasm.ASelect,
29771		reg: regInfo{
29772			inputs: []inputInfo{
29773				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
29774				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
29775				{2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
29776			},
29777			outputs: []outputInfo{
29778				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29779			},
29780		},
29781	},
29782	{
29783		name:    "I64Load8U",
29784		auxType: auxInt64,
29785		argLen:  2,
29786		asm:     wasm.AI64Load8U,
29787		reg: regInfo{
29788			inputs: []inputInfo{
29789				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29790			},
29791			outputs: []outputInfo{
29792				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29793			},
29794		},
29795	},
29796	{
29797		name:    "I64Load8S",
29798		auxType: auxInt64,
29799		argLen:  2,
29800		asm:     wasm.AI64Load8S,
29801		reg: regInfo{
29802			inputs: []inputInfo{
29803				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29804			},
29805			outputs: []outputInfo{
29806				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29807			},
29808		},
29809	},
29810	{
29811		name:    "I64Load16U",
29812		auxType: auxInt64,
29813		argLen:  2,
29814		asm:     wasm.AI64Load16U,
29815		reg: regInfo{
29816			inputs: []inputInfo{
29817				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29818			},
29819			outputs: []outputInfo{
29820				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29821			},
29822		},
29823	},
29824	{
29825		name:    "I64Load16S",
29826		auxType: auxInt64,
29827		argLen:  2,
29828		asm:     wasm.AI64Load16S,
29829		reg: regInfo{
29830			inputs: []inputInfo{
29831				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29832			},
29833			outputs: []outputInfo{
29834				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29835			},
29836		},
29837	},
29838	{
29839		name:    "I64Load32U",
29840		auxType: auxInt64,
29841		argLen:  2,
29842		asm:     wasm.AI64Load32U,
29843		reg: regInfo{
29844			inputs: []inputInfo{
29845				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29846			},
29847			outputs: []outputInfo{
29848				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29849			},
29850		},
29851	},
29852	{
29853		name:    "I64Load32S",
29854		auxType: auxInt64,
29855		argLen:  2,
29856		asm:     wasm.AI64Load32S,
29857		reg: regInfo{
29858			inputs: []inputInfo{
29859				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29860			},
29861			outputs: []outputInfo{
29862				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29863			},
29864		},
29865	},
29866	{
29867		name:    "I64Load",
29868		auxType: auxInt64,
29869		argLen:  2,
29870		asm:     wasm.AI64Load,
29871		reg: regInfo{
29872			inputs: []inputInfo{
29873				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29874			},
29875			outputs: []outputInfo{
29876				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29877			},
29878		},
29879	},
29880	{
29881		name:    "I64Store8",
29882		auxType: auxInt64,
29883		argLen:  3,
29884		asm:     wasm.AI64Store8,
29885		reg: regInfo{
29886			inputs: []inputInfo{
29887				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
29888				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29889			},
29890		},
29891	},
29892	{
29893		name:    "I64Store16",
29894		auxType: auxInt64,
29895		argLen:  3,
29896		asm:     wasm.AI64Store16,
29897		reg: regInfo{
29898			inputs: []inputInfo{
29899				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
29900				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29901			},
29902		},
29903	},
29904	{
29905		name:    "I64Store32",
29906		auxType: auxInt64,
29907		argLen:  3,
29908		asm:     wasm.AI64Store32,
29909		reg: regInfo{
29910			inputs: []inputInfo{
29911				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
29912				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29913			},
29914		},
29915	},
29916	{
29917		name:    "I64Store",
29918		auxType: auxInt64,
29919		argLen:  3,
29920		asm:     wasm.AI64Store,
29921		reg: regInfo{
29922			inputs: []inputInfo{
29923				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
29924				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29925			},
29926		},
29927	},
29928	{
29929		name:    "F32Load",
29930		auxType: auxInt64,
29931		argLen:  2,
29932		asm:     wasm.AF32Load,
29933		reg: regInfo{
29934			inputs: []inputInfo{
29935				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29936			},
29937			outputs: []outputInfo{
29938				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29939			},
29940		},
29941	},
29942	{
29943		name:    "F64Load",
29944		auxType: auxInt64,
29945		argLen:  2,
29946		asm:     wasm.AF64Load,
29947		reg: regInfo{
29948			inputs: []inputInfo{
29949				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29950			},
29951			outputs: []outputInfo{
29952				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29953			},
29954		},
29955	},
29956	{
29957		name:    "F32Store",
29958		auxType: auxInt64,
29959		argLen:  3,
29960		asm:     wasm.AF32Store,
29961		reg: regInfo{
29962			inputs: []inputInfo{
29963				{1, 4294901760},       // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29964				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29965			},
29966		},
29967	},
29968	{
29969		name:    "F64Store",
29970		auxType: auxInt64,
29971		argLen:  3,
29972		asm:     wasm.AF64Store,
29973		reg: regInfo{
29974			inputs: []inputInfo{
29975				{1, 281470681743360},  // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29976				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
29977			},
29978		},
29979	},
29980	{
29981		name:              "I64Const",
29982		auxType:           auxInt64,
29983		argLen:            0,
29984		rematerializeable: true,
29985		reg: regInfo{
29986			outputs: []outputInfo{
29987				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
29988			},
29989		},
29990	},
29991	{
29992		name:              "F32Const",
29993		auxType:           auxFloat32,
29994		argLen:            0,
29995		rematerializeable: true,
29996		reg: regInfo{
29997			outputs: []outputInfo{
29998				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29999			},
30000		},
30001	},
30002	{
30003		name:              "F64Const",
30004		auxType:           auxFloat64,
30005		argLen:            0,
30006		rematerializeable: true,
30007		reg: regInfo{
30008			outputs: []outputInfo{
30009				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30010			},
30011		},
30012	},
30013	{
30014		name:   "I64Eqz",
30015		argLen: 1,
30016		asm:    wasm.AI64Eqz,
30017		reg: regInfo{
30018			inputs: []inputInfo{
30019				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30020			},
30021			outputs: []outputInfo{
30022				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30023			},
30024		},
30025	},
30026	{
30027		name:   "I64Eq",
30028		argLen: 2,
30029		asm:    wasm.AI64Eq,
30030		reg: regInfo{
30031			inputs: []inputInfo{
30032				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30033				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30034			},
30035			outputs: []outputInfo{
30036				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30037			},
30038		},
30039	},
30040	{
30041		name:   "I64Ne",
30042		argLen: 2,
30043		asm:    wasm.AI64Ne,
30044		reg: regInfo{
30045			inputs: []inputInfo{
30046				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30047				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30048			},
30049			outputs: []outputInfo{
30050				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30051			},
30052		},
30053	},
30054	{
30055		name:   "I64LtS",
30056		argLen: 2,
30057		asm:    wasm.AI64LtS,
30058		reg: regInfo{
30059			inputs: []inputInfo{
30060				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30061				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30062			},
30063			outputs: []outputInfo{
30064				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30065			},
30066		},
30067	},
30068	{
30069		name:   "I64LtU",
30070		argLen: 2,
30071		asm:    wasm.AI64LtU,
30072		reg: regInfo{
30073			inputs: []inputInfo{
30074				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30075				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30076			},
30077			outputs: []outputInfo{
30078				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30079			},
30080		},
30081	},
30082	{
30083		name:   "I64GtS",
30084		argLen: 2,
30085		asm:    wasm.AI64GtS,
30086		reg: regInfo{
30087			inputs: []inputInfo{
30088				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30089				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30090			},
30091			outputs: []outputInfo{
30092				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30093			},
30094		},
30095	},
30096	{
30097		name:   "I64GtU",
30098		argLen: 2,
30099		asm:    wasm.AI64GtU,
30100		reg: regInfo{
30101			inputs: []inputInfo{
30102				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30103				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30104			},
30105			outputs: []outputInfo{
30106				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30107			},
30108		},
30109	},
30110	{
30111		name:   "I64LeS",
30112		argLen: 2,
30113		asm:    wasm.AI64LeS,
30114		reg: regInfo{
30115			inputs: []inputInfo{
30116				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30117				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30118			},
30119			outputs: []outputInfo{
30120				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30121			},
30122		},
30123	},
30124	{
30125		name:   "I64LeU",
30126		argLen: 2,
30127		asm:    wasm.AI64LeU,
30128		reg: regInfo{
30129			inputs: []inputInfo{
30130				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30131				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30132			},
30133			outputs: []outputInfo{
30134				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30135			},
30136		},
30137	},
30138	{
30139		name:   "I64GeS",
30140		argLen: 2,
30141		asm:    wasm.AI64GeS,
30142		reg: regInfo{
30143			inputs: []inputInfo{
30144				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30145				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30146			},
30147			outputs: []outputInfo{
30148				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30149			},
30150		},
30151	},
30152	{
30153		name:   "I64GeU",
30154		argLen: 2,
30155		asm:    wasm.AI64GeU,
30156		reg: regInfo{
30157			inputs: []inputInfo{
30158				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30159				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30160			},
30161			outputs: []outputInfo{
30162				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30163			},
30164		},
30165	},
30166	{
30167		name:   "F32Eq",
30168		argLen: 2,
30169		asm:    wasm.AF32Eq,
30170		reg: regInfo{
30171			inputs: []inputInfo{
30172				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30173				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30174			},
30175			outputs: []outputInfo{
30176				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30177			},
30178		},
30179	},
30180	{
30181		name:   "F32Ne",
30182		argLen: 2,
30183		asm:    wasm.AF32Ne,
30184		reg: regInfo{
30185			inputs: []inputInfo{
30186				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30187				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30188			},
30189			outputs: []outputInfo{
30190				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30191			},
30192		},
30193	},
30194	{
30195		name:   "F32Lt",
30196		argLen: 2,
30197		asm:    wasm.AF32Lt,
30198		reg: regInfo{
30199			inputs: []inputInfo{
30200				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30201				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30202			},
30203			outputs: []outputInfo{
30204				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30205			},
30206		},
30207	},
30208	{
30209		name:   "F32Gt",
30210		argLen: 2,
30211		asm:    wasm.AF32Gt,
30212		reg: regInfo{
30213			inputs: []inputInfo{
30214				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30215				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30216			},
30217			outputs: []outputInfo{
30218				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30219			},
30220		},
30221	},
30222	{
30223		name:   "F32Le",
30224		argLen: 2,
30225		asm:    wasm.AF32Le,
30226		reg: regInfo{
30227			inputs: []inputInfo{
30228				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30229				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30230			},
30231			outputs: []outputInfo{
30232				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30233			},
30234		},
30235	},
30236	{
30237		name:   "F32Ge",
30238		argLen: 2,
30239		asm:    wasm.AF32Ge,
30240		reg: regInfo{
30241			inputs: []inputInfo{
30242				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30243				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30244			},
30245			outputs: []outputInfo{
30246				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30247			},
30248		},
30249	},
30250	{
30251		name:   "F64Eq",
30252		argLen: 2,
30253		asm:    wasm.AF64Eq,
30254		reg: regInfo{
30255			inputs: []inputInfo{
30256				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30257				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30258			},
30259			outputs: []outputInfo{
30260				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30261			},
30262		},
30263	},
30264	{
30265		name:   "F64Ne",
30266		argLen: 2,
30267		asm:    wasm.AF64Ne,
30268		reg: regInfo{
30269			inputs: []inputInfo{
30270				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30271				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30272			},
30273			outputs: []outputInfo{
30274				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30275			},
30276		},
30277	},
30278	{
30279		name:   "F64Lt",
30280		argLen: 2,
30281		asm:    wasm.AF64Lt,
30282		reg: regInfo{
30283			inputs: []inputInfo{
30284				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30285				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30286			},
30287			outputs: []outputInfo{
30288				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30289			},
30290		},
30291	},
30292	{
30293		name:   "F64Gt",
30294		argLen: 2,
30295		asm:    wasm.AF64Gt,
30296		reg: regInfo{
30297			inputs: []inputInfo{
30298				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30299				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30300			},
30301			outputs: []outputInfo{
30302				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30303			},
30304		},
30305	},
30306	{
30307		name:   "F64Le",
30308		argLen: 2,
30309		asm:    wasm.AF64Le,
30310		reg: regInfo{
30311			inputs: []inputInfo{
30312				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30313				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30314			},
30315			outputs: []outputInfo{
30316				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30317			},
30318		},
30319	},
30320	{
30321		name:   "F64Ge",
30322		argLen: 2,
30323		asm:    wasm.AF64Ge,
30324		reg: regInfo{
30325			inputs: []inputInfo{
30326				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30327				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30328			},
30329			outputs: []outputInfo{
30330				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30331			},
30332		},
30333	},
30334	{
30335		name:   "I64Add",
30336		argLen: 2,
30337		asm:    wasm.AI64Add,
30338		reg: regInfo{
30339			inputs: []inputInfo{
30340				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30341				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30342			},
30343			outputs: []outputInfo{
30344				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30345			},
30346		},
30347	},
30348	{
30349		name:    "I64AddConst",
30350		auxType: auxInt64,
30351		argLen:  1,
30352		asm:     wasm.AI64Add,
30353		reg: regInfo{
30354			inputs: []inputInfo{
30355				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30356			},
30357			outputs: []outputInfo{
30358				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30359			},
30360		},
30361	},
30362	{
30363		name:   "I64Sub",
30364		argLen: 2,
30365		asm:    wasm.AI64Sub,
30366		reg: regInfo{
30367			inputs: []inputInfo{
30368				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30369				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30370			},
30371			outputs: []outputInfo{
30372				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30373			},
30374		},
30375	},
30376	{
30377		name:   "I64Mul",
30378		argLen: 2,
30379		asm:    wasm.AI64Mul,
30380		reg: regInfo{
30381			inputs: []inputInfo{
30382				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30383				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30384			},
30385			outputs: []outputInfo{
30386				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30387			},
30388		},
30389	},
30390	{
30391		name:   "I64DivS",
30392		argLen: 2,
30393		asm:    wasm.AI64DivS,
30394		reg: regInfo{
30395			inputs: []inputInfo{
30396				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30397				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30398			},
30399			outputs: []outputInfo{
30400				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30401			},
30402		},
30403	},
30404	{
30405		name:   "I64DivU",
30406		argLen: 2,
30407		asm:    wasm.AI64DivU,
30408		reg: regInfo{
30409			inputs: []inputInfo{
30410				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30411				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30412			},
30413			outputs: []outputInfo{
30414				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30415			},
30416		},
30417	},
30418	{
30419		name:   "I64RemS",
30420		argLen: 2,
30421		asm:    wasm.AI64RemS,
30422		reg: regInfo{
30423			inputs: []inputInfo{
30424				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30425				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30426			},
30427			outputs: []outputInfo{
30428				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30429			},
30430		},
30431	},
30432	{
30433		name:   "I64RemU",
30434		argLen: 2,
30435		asm:    wasm.AI64RemU,
30436		reg: regInfo{
30437			inputs: []inputInfo{
30438				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30439				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30440			},
30441			outputs: []outputInfo{
30442				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30443			},
30444		},
30445	},
30446	{
30447		name:   "I64And",
30448		argLen: 2,
30449		asm:    wasm.AI64And,
30450		reg: regInfo{
30451			inputs: []inputInfo{
30452				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30453				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30454			},
30455			outputs: []outputInfo{
30456				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30457			},
30458		},
30459	},
30460	{
30461		name:   "I64Or",
30462		argLen: 2,
30463		asm:    wasm.AI64Or,
30464		reg: regInfo{
30465			inputs: []inputInfo{
30466				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30467				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30468			},
30469			outputs: []outputInfo{
30470				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30471			},
30472		},
30473	},
30474	{
30475		name:   "I64Xor",
30476		argLen: 2,
30477		asm:    wasm.AI64Xor,
30478		reg: regInfo{
30479			inputs: []inputInfo{
30480				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30481				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30482			},
30483			outputs: []outputInfo{
30484				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30485			},
30486		},
30487	},
30488	{
30489		name:   "I64Shl",
30490		argLen: 2,
30491		asm:    wasm.AI64Shl,
30492		reg: regInfo{
30493			inputs: []inputInfo{
30494				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30495				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30496			},
30497			outputs: []outputInfo{
30498				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30499			},
30500		},
30501	},
30502	{
30503		name:   "I64ShrS",
30504		argLen: 2,
30505		asm:    wasm.AI64ShrS,
30506		reg: regInfo{
30507			inputs: []inputInfo{
30508				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30509				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30510			},
30511			outputs: []outputInfo{
30512				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30513			},
30514		},
30515	},
30516	{
30517		name:   "I64ShrU",
30518		argLen: 2,
30519		asm:    wasm.AI64ShrU,
30520		reg: regInfo{
30521			inputs: []inputInfo{
30522				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30523				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30524			},
30525			outputs: []outputInfo{
30526				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30527			},
30528		},
30529	},
30530	{
30531		name:   "F32Neg",
30532		argLen: 1,
30533		asm:    wasm.AF32Neg,
30534		reg: regInfo{
30535			inputs: []inputInfo{
30536				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30537			},
30538			outputs: []outputInfo{
30539				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30540			},
30541		},
30542	},
30543	{
30544		name:   "F32Add",
30545		argLen: 2,
30546		asm:    wasm.AF32Add,
30547		reg: regInfo{
30548			inputs: []inputInfo{
30549				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30550				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30551			},
30552			outputs: []outputInfo{
30553				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30554			},
30555		},
30556	},
30557	{
30558		name:   "F32Sub",
30559		argLen: 2,
30560		asm:    wasm.AF32Sub,
30561		reg: regInfo{
30562			inputs: []inputInfo{
30563				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30564				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30565			},
30566			outputs: []outputInfo{
30567				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30568			},
30569		},
30570	},
30571	{
30572		name:   "F32Mul",
30573		argLen: 2,
30574		asm:    wasm.AF32Mul,
30575		reg: regInfo{
30576			inputs: []inputInfo{
30577				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30578				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30579			},
30580			outputs: []outputInfo{
30581				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30582			},
30583		},
30584	},
30585	{
30586		name:   "F32Div",
30587		argLen: 2,
30588		asm:    wasm.AF32Div,
30589		reg: regInfo{
30590			inputs: []inputInfo{
30591				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30592				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30593			},
30594			outputs: []outputInfo{
30595				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30596			},
30597		},
30598	},
30599	{
30600		name:   "F64Neg",
30601		argLen: 1,
30602		asm:    wasm.AF64Neg,
30603		reg: regInfo{
30604			inputs: []inputInfo{
30605				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30606			},
30607			outputs: []outputInfo{
30608				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30609			},
30610		},
30611	},
30612	{
30613		name:   "F64Add",
30614		argLen: 2,
30615		asm:    wasm.AF64Add,
30616		reg: regInfo{
30617			inputs: []inputInfo{
30618				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30619				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30620			},
30621			outputs: []outputInfo{
30622				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30623			},
30624		},
30625	},
30626	{
30627		name:   "F64Sub",
30628		argLen: 2,
30629		asm:    wasm.AF64Sub,
30630		reg: regInfo{
30631			inputs: []inputInfo{
30632				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30633				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30634			},
30635			outputs: []outputInfo{
30636				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30637			},
30638		},
30639	},
30640	{
30641		name:   "F64Mul",
30642		argLen: 2,
30643		asm:    wasm.AF64Mul,
30644		reg: regInfo{
30645			inputs: []inputInfo{
30646				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30647				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30648			},
30649			outputs: []outputInfo{
30650				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30651			},
30652		},
30653	},
30654	{
30655		name:   "F64Div",
30656		argLen: 2,
30657		asm:    wasm.AF64Div,
30658		reg: regInfo{
30659			inputs: []inputInfo{
30660				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30661				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30662			},
30663			outputs: []outputInfo{
30664				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30665			},
30666		},
30667	},
30668	{
30669		name:   "I64TruncSatF64S",
30670		argLen: 1,
30671		asm:    wasm.AI64TruncSatF64S,
30672		reg: regInfo{
30673			inputs: []inputInfo{
30674				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30675			},
30676			outputs: []outputInfo{
30677				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30678			},
30679		},
30680	},
30681	{
30682		name:   "I64TruncSatF64U",
30683		argLen: 1,
30684		asm:    wasm.AI64TruncSatF64U,
30685		reg: regInfo{
30686			inputs: []inputInfo{
30687				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30688			},
30689			outputs: []outputInfo{
30690				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30691			},
30692		},
30693	},
30694	{
30695		name:   "I64TruncSatF32S",
30696		argLen: 1,
30697		asm:    wasm.AI64TruncSatF32S,
30698		reg: regInfo{
30699			inputs: []inputInfo{
30700				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30701			},
30702			outputs: []outputInfo{
30703				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30704			},
30705		},
30706	},
30707	{
30708		name:   "I64TruncSatF32U",
30709		argLen: 1,
30710		asm:    wasm.AI64TruncSatF32U,
30711		reg: regInfo{
30712			inputs: []inputInfo{
30713				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30714			},
30715			outputs: []outputInfo{
30716				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30717			},
30718		},
30719	},
30720	{
30721		name:   "F32ConvertI64S",
30722		argLen: 1,
30723		asm:    wasm.AF32ConvertI64S,
30724		reg: regInfo{
30725			inputs: []inputInfo{
30726				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30727			},
30728			outputs: []outputInfo{
30729				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30730			},
30731		},
30732	},
30733	{
30734		name:   "F32ConvertI64U",
30735		argLen: 1,
30736		asm:    wasm.AF32ConvertI64U,
30737		reg: regInfo{
30738			inputs: []inputInfo{
30739				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30740			},
30741			outputs: []outputInfo{
30742				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30743			},
30744		},
30745	},
30746	{
30747		name:   "F64ConvertI64S",
30748		argLen: 1,
30749		asm:    wasm.AF64ConvertI64S,
30750		reg: regInfo{
30751			inputs: []inputInfo{
30752				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30753			},
30754			outputs: []outputInfo{
30755				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30756			},
30757		},
30758	},
30759	{
30760		name:   "F64ConvertI64U",
30761		argLen: 1,
30762		asm:    wasm.AF64ConvertI64U,
30763		reg: regInfo{
30764			inputs: []inputInfo{
30765				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30766			},
30767			outputs: []outputInfo{
30768				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30769			},
30770		},
30771	},
30772	{
30773		name:   "F32DemoteF64",
30774		argLen: 1,
30775		asm:    wasm.AF32DemoteF64,
30776		reg: regInfo{
30777			inputs: []inputInfo{
30778				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30779			},
30780			outputs: []outputInfo{
30781				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30782			},
30783		},
30784	},
30785	{
30786		name:   "F64PromoteF32",
30787		argLen: 1,
30788		asm:    wasm.AF64PromoteF32,
30789		reg: regInfo{
30790			inputs: []inputInfo{
30791				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30792			},
30793			outputs: []outputInfo{
30794				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30795			},
30796		},
30797	},
30798	{
30799		name:   "I64Extend8S",
30800		argLen: 1,
30801		asm:    wasm.AI64Extend8S,
30802		reg: regInfo{
30803			inputs: []inputInfo{
30804				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30805			},
30806			outputs: []outputInfo{
30807				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30808			},
30809		},
30810	},
30811	{
30812		name:   "I64Extend16S",
30813		argLen: 1,
30814		asm:    wasm.AI64Extend16S,
30815		reg: regInfo{
30816			inputs: []inputInfo{
30817				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30818			},
30819			outputs: []outputInfo{
30820				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30821			},
30822		},
30823	},
30824	{
30825		name:   "I64Extend32S",
30826		argLen: 1,
30827		asm:    wasm.AI64Extend32S,
30828		reg: regInfo{
30829			inputs: []inputInfo{
30830				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
30831			},
30832			outputs: []outputInfo{
30833				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
30834			},
30835		},
30836	},
30837	{
30838		name:   "F32Sqrt",
30839		argLen: 1,
30840		asm:    wasm.AF32Sqrt,
30841		reg: regInfo{
30842			inputs: []inputInfo{
30843				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30844			},
30845			outputs: []outputInfo{
30846				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30847			},
30848		},
30849	},
30850	{
30851		name:   "F32Trunc",
30852		argLen: 1,
30853		asm:    wasm.AF32Trunc,
30854		reg: regInfo{
30855			inputs: []inputInfo{
30856				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30857			},
30858			outputs: []outputInfo{
30859				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30860			},
30861		},
30862	},
30863	{
30864		name:   "F32Ceil",
30865		argLen: 1,
30866		asm:    wasm.AF32Ceil,
30867		reg: regInfo{
30868			inputs: []inputInfo{
30869				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30870			},
30871			outputs: []outputInfo{
30872				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30873			},
30874		},
30875	},
30876	{
30877		name:   "F32Floor",
30878		argLen: 1,
30879		asm:    wasm.AF32Floor,
30880		reg: regInfo{
30881			inputs: []inputInfo{
30882				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30883			},
30884			outputs: []outputInfo{
30885				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30886			},
30887		},
30888	},
30889	{
30890		name:   "F32Nearest",
30891		argLen: 1,
30892		asm:    wasm.AF32Nearest,
30893		reg: regInfo{
30894			inputs: []inputInfo{
30895				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30896			},
30897			outputs: []outputInfo{
30898				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30899			},
30900		},
30901	},
30902	{
30903		name:   "F32Abs",
30904		argLen: 1,
30905		asm:    wasm.AF32Abs,
30906		reg: regInfo{
30907			inputs: []inputInfo{
30908				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30909			},
30910			outputs: []outputInfo{
30911				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30912			},
30913		},
30914	},
30915	{
30916		name:   "F32Copysign",
30917		argLen: 2,
30918		asm:    wasm.AF32Copysign,
30919		reg: regInfo{
30920			inputs: []inputInfo{
30921				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30922				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30923			},
30924			outputs: []outputInfo{
30925				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30926			},
30927		},
30928	},
30929	{
30930		name:   "F64Sqrt",
30931		argLen: 1,
30932		asm:    wasm.AF64Sqrt,
30933		reg: regInfo{
30934			inputs: []inputInfo{
30935				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30936			},
30937			outputs: []outputInfo{
30938				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30939			},
30940		},
30941	},
30942	{
30943		name:   "F64Trunc",
30944		argLen: 1,
30945		asm:    wasm.AF64Trunc,
30946		reg: regInfo{
30947			inputs: []inputInfo{
30948				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30949			},
30950			outputs: []outputInfo{
30951				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30952			},
30953		},
30954	},
30955	{
30956		name:   "F64Ceil",
30957		argLen: 1,
30958		asm:    wasm.AF64Ceil,
30959		reg: regInfo{
30960			inputs: []inputInfo{
30961				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30962			},
30963			outputs: []outputInfo{
30964				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30965			},
30966		},
30967	},
30968	{
30969		name:   "F64Floor",
30970		argLen: 1,
30971		asm:    wasm.AF64Floor,
30972		reg: regInfo{
30973			inputs: []inputInfo{
30974				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30975			},
30976			outputs: []outputInfo{
30977				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30978			},
30979		},
30980	},
30981	{
30982		name:   "F64Nearest",
30983		argLen: 1,
30984		asm:    wasm.AF64Nearest,
30985		reg: regInfo{
30986			inputs: []inputInfo{
30987				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30988			},
30989			outputs: []outputInfo{
30990				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
30991			},
30992		},
30993	},
30994	{
30995		name:   "F64Abs",
30996		argLen: 1,
30997		asm:    wasm.AF64Abs,
30998		reg: regInfo{
30999			inputs: []inputInfo{
31000				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
31001			},
31002			outputs: []outputInfo{
31003				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
31004			},
31005		},
31006	},
31007	{
31008		name:   "F64Copysign",
31009		argLen: 2,
31010		asm:    wasm.AF64Copysign,
31011		reg: regInfo{
31012			inputs: []inputInfo{
31013				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
31014				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
31015			},
31016			outputs: []outputInfo{
31017				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
31018			},
31019		},
31020	},
31021	{
31022		name:   "I64Ctz",
31023		argLen: 1,
31024		asm:    wasm.AI64Ctz,
31025		reg: regInfo{
31026			inputs: []inputInfo{
31027				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
31028			},
31029			outputs: []outputInfo{
31030				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
31031			},
31032		},
31033	},
31034	{
31035		name:   "I64Clz",
31036		argLen: 1,
31037		asm:    wasm.AI64Clz,
31038		reg: regInfo{
31039			inputs: []inputInfo{
31040				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
31041			},
31042			outputs: []outputInfo{
31043				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
31044			},
31045		},
31046	},
31047	{
31048		name:   "I32Rotl",
31049		argLen: 2,
31050		asm:    wasm.AI32Rotl,
31051		reg: regInfo{
31052			inputs: []inputInfo{
31053				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
31054				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
31055			},
31056			outputs: []outputInfo{
31057				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
31058			},
31059		},
31060	},
31061	{
31062		name:   "I64Rotl",
31063		argLen: 2,
31064		asm:    wasm.AI64Rotl,
31065		reg: regInfo{
31066			inputs: []inputInfo{
31067				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
31068				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
31069			},
31070			outputs: []outputInfo{
31071				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
31072			},
31073		},
31074	},
31075	{
31076		name:   "I64Popcnt",
31077		argLen: 1,
31078		asm:    wasm.AI64Popcnt,
31079		reg: regInfo{
31080			inputs: []inputInfo{
31081				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
31082			},
31083			outputs: []outputInfo{
31084				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
31085			},
31086		},
31087	},
31088
31089	{
31090		name:        "Add8",
31091		argLen:      2,
31092		commutative: true,
31093		generic:     true,
31094	},
31095	{
31096		name:        "Add16",
31097		argLen:      2,
31098		commutative: true,
31099		generic:     true,
31100	},
31101	{
31102		name:        "Add32",
31103		argLen:      2,
31104		commutative: true,
31105		generic:     true,
31106	},
31107	{
31108		name:        "Add64",
31109		argLen:      2,
31110		commutative: true,
31111		generic:     true,
31112	},
31113	{
31114		name:    "AddPtr",
31115		argLen:  2,
31116		generic: true,
31117	},
31118	{
31119		name:        "Add32F",
31120		argLen:      2,
31121		commutative: true,
31122		generic:     true,
31123	},
31124	{
31125		name:        "Add64F",
31126		argLen:      2,
31127		commutative: true,
31128		generic:     true,
31129	},
31130	{
31131		name:    "Sub8",
31132		argLen:  2,
31133		generic: true,
31134	},
31135	{
31136		name:    "Sub16",
31137		argLen:  2,
31138		generic: true,
31139	},
31140	{
31141		name:    "Sub32",
31142		argLen:  2,
31143		generic: true,
31144	},
31145	{
31146		name:    "Sub64",
31147		argLen:  2,
31148		generic: true,
31149	},
31150	{
31151		name:    "SubPtr",
31152		argLen:  2,
31153		generic: true,
31154	},
31155	{
31156		name:    "Sub32F",
31157		argLen:  2,
31158		generic: true,
31159	},
31160	{
31161		name:    "Sub64F",
31162		argLen:  2,
31163		generic: true,
31164	},
31165	{
31166		name:        "Mul8",
31167		argLen:      2,
31168		commutative: true,
31169		generic:     true,
31170	},
31171	{
31172		name:        "Mul16",
31173		argLen:      2,
31174		commutative: true,
31175		generic:     true,
31176	},
31177	{
31178		name:        "Mul32",
31179		argLen:      2,
31180		commutative: true,
31181		generic:     true,
31182	},
31183	{
31184		name:        "Mul64",
31185		argLen:      2,
31186		commutative: true,
31187		generic:     true,
31188	},
31189	{
31190		name:        "Mul32F",
31191		argLen:      2,
31192		commutative: true,
31193		generic:     true,
31194	},
31195	{
31196		name:        "Mul64F",
31197		argLen:      2,
31198		commutative: true,
31199		generic:     true,
31200	},
31201	{
31202		name:    "Div32F",
31203		argLen:  2,
31204		generic: true,
31205	},
31206	{
31207		name:    "Div64F",
31208		argLen:  2,
31209		generic: true,
31210	},
31211	{
31212		name:        "Hmul32",
31213		argLen:      2,
31214		commutative: true,
31215		generic:     true,
31216	},
31217	{
31218		name:        "Hmul32u",
31219		argLen:      2,
31220		commutative: true,
31221		generic:     true,
31222	},
31223	{
31224		name:        "Hmul64",
31225		argLen:      2,
31226		commutative: true,
31227		generic:     true,
31228	},
31229	{
31230		name:        "Hmul64u",
31231		argLen:      2,
31232		commutative: true,
31233		generic:     true,
31234	},
31235	{
31236		name:        "Mul32uhilo",
31237		argLen:      2,
31238		commutative: true,
31239		generic:     true,
31240	},
31241	{
31242		name:        "Mul64uhilo",
31243		argLen:      2,
31244		commutative: true,
31245		generic:     true,
31246	},
31247	{
31248		name:        "Mul32uover",
31249		argLen:      2,
31250		commutative: true,
31251		generic:     true,
31252	},
31253	{
31254		name:        "Mul64uover",
31255		argLen:      2,
31256		commutative: true,
31257		generic:     true,
31258	},
31259	{
31260		name:    "Avg32u",
31261		argLen:  2,
31262		generic: true,
31263	},
31264	{
31265		name:    "Avg64u",
31266		argLen:  2,
31267		generic: true,
31268	},
31269	{
31270		name:    "Div8",
31271		argLen:  2,
31272		generic: true,
31273	},
31274	{
31275		name:    "Div8u",
31276		argLen:  2,
31277		generic: true,
31278	},
31279	{
31280		name:    "Div16",
31281		auxType: auxBool,
31282		argLen:  2,
31283		generic: true,
31284	},
31285	{
31286		name:    "Div16u",
31287		argLen:  2,
31288		generic: true,
31289	},
31290	{
31291		name:    "Div32",
31292		auxType: auxBool,
31293		argLen:  2,
31294		generic: true,
31295	},
31296	{
31297		name:    "Div32u",
31298		argLen:  2,
31299		generic: true,
31300	},
31301	{
31302		name:    "Div64",
31303		auxType: auxBool,
31304		argLen:  2,
31305		generic: true,
31306	},
31307	{
31308		name:    "Div64u",
31309		argLen:  2,
31310		generic: true,
31311	},
31312	{
31313		name:    "Div128u",
31314		argLen:  3,
31315		generic: true,
31316	},
31317	{
31318		name:    "Mod8",
31319		argLen:  2,
31320		generic: true,
31321	},
31322	{
31323		name:    "Mod8u",
31324		argLen:  2,
31325		generic: true,
31326	},
31327	{
31328		name:    "Mod16",
31329		auxType: auxBool,
31330		argLen:  2,
31331		generic: true,
31332	},
31333	{
31334		name:    "Mod16u",
31335		argLen:  2,
31336		generic: true,
31337	},
31338	{
31339		name:    "Mod32",
31340		auxType: auxBool,
31341		argLen:  2,
31342		generic: true,
31343	},
31344	{
31345		name:    "Mod32u",
31346		argLen:  2,
31347		generic: true,
31348	},
31349	{
31350		name:    "Mod64",
31351		auxType: auxBool,
31352		argLen:  2,
31353		generic: true,
31354	},
31355	{
31356		name:    "Mod64u",
31357		argLen:  2,
31358		generic: true,
31359	},
31360	{
31361		name:        "And8",
31362		argLen:      2,
31363		commutative: true,
31364		generic:     true,
31365	},
31366	{
31367		name:        "And16",
31368		argLen:      2,
31369		commutative: true,
31370		generic:     true,
31371	},
31372	{
31373		name:        "And32",
31374		argLen:      2,
31375		commutative: true,
31376		generic:     true,
31377	},
31378	{
31379		name:        "And64",
31380		argLen:      2,
31381		commutative: true,
31382		generic:     true,
31383	},
31384	{
31385		name:        "Or8",
31386		argLen:      2,
31387		commutative: true,
31388		generic:     true,
31389	},
31390	{
31391		name:        "Or16",
31392		argLen:      2,
31393		commutative: true,
31394		generic:     true,
31395	},
31396	{
31397		name:        "Or32",
31398		argLen:      2,
31399		commutative: true,
31400		generic:     true,
31401	},
31402	{
31403		name:        "Or64",
31404		argLen:      2,
31405		commutative: true,
31406		generic:     true,
31407	},
31408	{
31409		name:        "Xor8",
31410		argLen:      2,
31411		commutative: true,
31412		generic:     true,
31413	},
31414	{
31415		name:        "Xor16",
31416		argLen:      2,
31417		commutative: true,
31418		generic:     true,
31419	},
31420	{
31421		name:        "Xor32",
31422		argLen:      2,
31423		commutative: true,
31424		generic:     true,
31425	},
31426	{
31427		name:        "Xor64",
31428		argLen:      2,
31429		commutative: true,
31430		generic:     true,
31431	},
31432	{
31433		name:    "Lsh8x8",
31434		auxType: auxBool,
31435		argLen:  2,
31436		generic: true,
31437	},
31438	{
31439		name:    "Lsh8x16",
31440		auxType: auxBool,
31441		argLen:  2,
31442		generic: true,
31443	},
31444	{
31445		name:    "Lsh8x32",
31446		auxType: auxBool,
31447		argLen:  2,
31448		generic: true,
31449	},
31450	{
31451		name:    "Lsh8x64",
31452		auxType: auxBool,
31453		argLen:  2,
31454		generic: true,
31455	},
31456	{
31457		name:    "Lsh16x8",
31458		auxType: auxBool,
31459		argLen:  2,
31460		generic: true,
31461	},
31462	{
31463		name:    "Lsh16x16",
31464		auxType: auxBool,
31465		argLen:  2,
31466		generic: true,
31467	},
31468	{
31469		name:    "Lsh16x32",
31470		auxType: auxBool,
31471		argLen:  2,
31472		generic: true,
31473	},
31474	{
31475		name:    "Lsh16x64",
31476		auxType: auxBool,
31477		argLen:  2,
31478		generic: true,
31479	},
31480	{
31481		name:    "Lsh32x8",
31482		auxType: auxBool,
31483		argLen:  2,
31484		generic: true,
31485	},
31486	{
31487		name:    "Lsh32x16",
31488		auxType: auxBool,
31489		argLen:  2,
31490		generic: true,
31491	},
31492	{
31493		name:    "Lsh32x32",
31494		auxType: auxBool,
31495		argLen:  2,
31496		generic: true,
31497	},
31498	{
31499		name:    "Lsh32x64",
31500		auxType: auxBool,
31501		argLen:  2,
31502		generic: true,
31503	},
31504	{
31505		name:    "Lsh64x8",
31506		auxType: auxBool,
31507		argLen:  2,
31508		generic: true,
31509	},
31510	{
31511		name:    "Lsh64x16",
31512		auxType: auxBool,
31513		argLen:  2,
31514		generic: true,
31515	},
31516	{
31517		name:    "Lsh64x32",
31518		auxType: auxBool,
31519		argLen:  2,
31520		generic: true,
31521	},
31522	{
31523		name:    "Lsh64x64",
31524		auxType: auxBool,
31525		argLen:  2,
31526		generic: true,
31527	},
31528	{
31529		name:    "Rsh8x8",
31530		auxType: auxBool,
31531		argLen:  2,
31532		generic: true,
31533	},
31534	{
31535		name:    "Rsh8x16",
31536		auxType: auxBool,
31537		argLen:  2,
31538		generic: true,
31539	},
31540	{
31541		name:    "Rsh8x32",
31542		auxType: auxBool,
31543		argLen:  2,
31544		generic: true,
31545	},
31546	{
31547		name:    "Rsh8x64",
31548		auxType: auxBool,
31549		argLen:  2,
31550		generic: true,
31551	},
31552	{
31553		name:    "Rsh16x8",
31554		auxType: auxBool,
31555		argLen:  2,
31556		generic: true,
31557	},
31558	{
31559		name:    "Rsh16x16",
31560		auxType: auxBool,
31561		argLen:  2,
31562		generic: true,
31563	},
31564	{
31565		name:    "Rsh16x32",
31566		auxType: auxBool,
31567		argLen:  2,
31568		generic: true,
31569	},
31570	{
31571		name:    "Rsh16x64",
31572		auxType: auxBool,
31573		argLen:  2,
31574		generic: true,
31575	},
31576	{
31577		name:    "Rsh32x8",
31578		auxType: auxBool,
31579		argLen:  2,
31580		generic: true,
31581	},
31582	{
31583		name:    "Rsh32x16",
31584		auxType: auxBool,
31585		argLen:  2,
31586		generic: true,
31587	},
31588	{
31589		name:    "Rsh32x32",
31590		auxType: auxBool,
31591		argLen:  2,
31592		generic: true,
31593	},
31594	{
31595		name:    "Rsh32x64",
31596		auxType: auxBool,
31597		argLen:  2,
31598		generic: true,
31599	},
31600	{
31601		name:    "Rsh64x8",
31602		auxType: auxBool,
31603		argLen:  2,
31604		generic: true,
31605	},
31606	{
31607		name:    "Rsh64x16",
31608		auxType: auxBool,
31609		argLen:  2,
31610		generic: true,
31611	},
31612	{
31613		name:    "Rsh64x32",
31614		auxType: auxBool,
31615		argLen:  2,
31616		generic: true,
31617	},
31618	{
31619		name:    "Rsh64x64",
31620		auxType: auxBool,
31621		argLen:  2,
31622		generic: true,
31623	},
31624	{
31625		name:    "Rsh8Ux8",
31626		auxType: auxBool,
31627		argLen:  2,
31628		generic: true,
31629	},
31630	{
31631		name:    "Rsh8Ux16",
31632		auxType: auxBool,
31633		argLen:  2,
31634		generic: true,
31635	},
31636	{
31637		name:    "Rsh8Ux32",
31638		auxType: auxBool,
31639		argLen:  2,
31640		generic: true,
31641	},
31642	{
31643		name:    "Rsh8Ux64",
31644		auxType: auxBool,
31645		argLen:  2,
31646		generic: true,
31647	},
31648	{
31649		name:    "Rsh16Ux8",
31650		auxType: auxBool,
31651		argLen:  2,
31652		generic: true,
31653	},
31654	{
31655		name:    "Rsh16Ux16",
31656		auxType: auxBool,
31657		argLen:  2,
31658		generic: true,
31659	},
31660	{
31661		name:    "Rsh16Ux32",
31662		auxType: auxBool,
31663		argLen:  2,
31664		generic: true,
31665	},
31666	{
31667		name:    "Rsh16Ux64",
31668		auxType: auxBool,
31669		argLen:  2,
31670		generic: true,
31671	},
31672	{
31673		name:    "Rsh32Ux8",
31674		auxType: auxBool,
31675		argLen:  2,
31676		generic: true,
31677	},
31678	{
31679		name:    "Rsh32Ux16",
31680		auxType: auxBool,
31681		argLen:  2,
31682		generic: true,
31683	},
31684	{
31685		name:    "Rsh32Ux32",
31686		auxType: auxBool,
31687		argLen:  2,
31688		generic: true,
31689	},
31690	{
31691		name:    "Rsh32Ux64",
31692		auxType: auxBool,
31693		argLen:  2,
31694		generic: true,
31695	},
31696	{
31697		name:    "Rsh64Ux8",
31698		auxType: auxBool,
31699		argLen:  2,
31700		generic: true,
31701	},
31702	{
31703		name:    "Rsh64Ux16",
31704		auxType: auxBool,
31705		argLen:  2,
31706		generic: true,
31707	},
31708	{
31709		name:    "Rsh64Ux32",
31710		auxType: auxBool,
31711		argLen:  2,
31712		generic: true,
31713	},
31714	{
31715		name:    "Rsh64Ux64",
31716		auxType: auxBool,
31717		argLen:  2,
31718		generic: true,
31719	},
31720	{
31721		name:        "Eq8",
31722		argLen:      2,
31723		commutative: true,
31724		generic:     true,
31725	},
31726	{
31727		name:        "Eq16",
31728		argLen:      2,
31729		commutative: true,
31730		generic:     true,
31731	},
31732	{
31733		name:        "Eq32",
31734		argLen:      2,
31735		commutative: true,
31736		generic:     true,
31737	},
31738	{
31739		name:        "Eq64",
31740		argLen:      2,
31741		commutative: true,
31742		generic:     true,
31743	},
31744	{
31745		name:        "EqPtr",
31746		argLen:      2,
31747		commutative: true,
31748		generic:     true,
31749	},
31750	{
31751		name:    "EqInter",
31752		argLen:  2,
31753		generic: true,
31754	},
31755	{
31756		name:    "EqSlice",
31757		argLen:  2,
31758		generic: true,
31759	},
31760	{
31761		name:        "Eq32F",
31762		argLen:      2,
31763		commutative: true,
31764		generic:     true,
31765	},
31766	{
31767		name:        "Eq64F",
31768		argLen:      2,
31769		commutative: true,
31770		generic:     true,
31771	},
31772	{
31773		name:        "Neq8",
31774		argLen:      2,
31775		commutative: true,
31776		generic:     true,
31777	},
31778	{
31779		name:        "Neq16",
31780		argLen:      2,
31781		commutative: true,
31782		generic:     true,
31783	},
31784	{
31785		name:        "Neq32",
31786		argLen:      2,
31787		commutative: true,
31788		generic:     true,
31789	},
31790	{
31791		name:        "Neq64",
31792		argLen:      2,
31793		commutative: true,
31794		generic:     true,
31795	},
31796	{
31797		name:        "NeqPtr",
31798		argLen:      2,
31799		commutative: true,
31800		generic:     true,
31801	},
31802	{
31803		name:    "NeqInter",
31804		argLen:  2,
31805		generic: true,
31806	},
31807	{
31808		name:    "NeqSlice",
31809		argLen:  2,
31810		generic: true,
31811	},
31812	{
31813		name:        "Neq32F",
31814		argLen:      2,
31815		commutative: true,
31816		generic:     true,
31817	},
31818	{
31819		name:        "Neq64F",
31820		argLen:      2,
31821		commutative: true,
31822		generic:     true,
31823	},
31824	{
31825		name:    "Less8",
31826		argLen:  2,
31827		generic: true,
31828	},
31829	{
31830		name:    "Less8U",
31831		argLen:  2,
31832		generic: true,
31833	},
31834	{
31835		name:    "Less16",
31836		argLen:  2,
31837		generic: true,
31838	},
31839	{
31840		name:    "Less16U",
31841		argLen:  2,
31842		generic: true,
31843	},
31844	{
31845		name:    "Less32",
31846		argLen:  2,
31847		generic: true,
31848	},
31849	{
31850		name:    "Less32U",
31851		argLen:  2,
31852		generic: true,
31853	},
31854	{
31855		name:    "Less64",
31856		argLen:  2,
31857		generic: true,
31858	},
31859	{
31860		name:    "Less64U",
31861		argLen:  2,
31862		generic: true,
31863	},
31864	{
31865		name:    "Less32F",
31866		argLen:  2,
31867		generic: true,
31868	},
31869	{
31870		name:    "Less64F",
31871		argLen:  2,
31872		generic: true,
31873	},
31874	{
31875		name:    "Leq8",
31876		argLen:  2,
31877		generic: true,
31878	},
31879	{
31880		name:    "Leq8U",
31881		argLen:  2,
31882		generic: true,
31883	},
31884	{
31885		name:    "Leq16",
31886		argLen:  2,
31887		generic: true,
31888	},
31889	{
31890		name:    "Leq16U",
31891		argLen:  2,
31892		generic: true,
31893	},
31894	{
31895		name:    "Leq32",
31896		argLen:  2,
31897		generic: true,
31898	},
31899	{
31900		name:    "Leq32U",
31901		argLen:  2,
31902		generic: true,
31903	},
31904	{
31905		name:    "Leq64",
31906		argLen:  2,
31907		generic: true,
31908	},
31909	{
31910		name:    "Leq64U",
31911		argLen:  2,
31912		generic: true,
31913	},
31914	{
31915		name:    "Leq32F",
31916		argLen:  2,
31917		generic: true,
31918	},
31919	{
31920		name:    "Leq64F",
31921		argLen:  2,
31922		generic: true,
31923	},
31924	{
31925		name:    "Greater8",
31926		argLen:  2,
31927		generic: true,
31928	},
31929	{
31930		name:    "Greater8U",
31931		argLen:  2,
31932		generic: true,
31933	},
31934	{
31935		name:    "Greater16",
31936		argLen:  2,
31937		generic: true,
31938	},
31939	{
31940		name:    "Greater16U",
31941		argLen:  2,
31942		generic: true,
31943	},
31944	{
31945		name:    "Greater32",
31946		argLen:  2,
31947		generic: true,
31948	},
31949	{
31950		name:    "Greater32U",
31951		argLen:  2,
31952		generic: true,
31953	},
31954	{
31955		name:    "Greater64",
31956		argLen:  2,
31957		generic: true,
31958	},
31959	{
31960		name:    "Greater64U",
31961		argLen:  2,
31962		generic: true,
31963	},
31964	{
31965		name:    "Greater32F",
31966		argLen:  2,
31967		generic: true,
31968	},
31969	{
31970		name:    "Greater64F",
31971		argLen:  2,
31972		generic: true,
31973	},
31974	{
31975		name:    "Geq8",
31976		argLen:  2,
31977		generic: true,
31978	},
31979	{
31980		name:    "Geq8U",
31981		argLen:  2,
31982		generic: true,
31983	},
31984	{
31985		name:    "Geq16",
31986		argLen:  2,
31987		generic: true,
31988	},
31989	{
31990		name:    "Geq16U",
31991		argLen:  2,
31992		generic: true,
31993	},
31994	{
31995		name:    "Geq32",
31996		argLen:  2,
31997		generic: true,
31998	},
31999	{
32000		name:    "Geq32U",
32001		argLen:  2,
32002		generic: true,
32003	},
32004	{
32005		name:    "Geq64",
32006		argLen:  2,
32007		generic: true,
32008	},
32009	{
32010		name:    "Geq64U",
32011		argLen:  2,
32012		generic: true,
32013	},
32014	{
32015		name:    "Geq32F",
32016		argLen:  2,
32017		generic: true,
32018	},
32019	{
32020		name:    "Geq64F",
32021		argLen:  2,
32022		generic: true,
32023	},
32024	{
32025		name:    "CondSelect",
32026		argLen:  3,
32027		generic: true,
32028	},
32029	{
32030		name:        "AndB",
32031		argLen:      2,
32032		commutative: true,
32033		generic:     true,
32034	},
32035	{
32036		name:        "OrB",
32037		argLen:      2,
32038		commutative: true,
32039		generic:     true,
32040	},
32041	{
32042		name:        "EqB",
32043		argLen:      2,
32044		commutative: true,
32045		generic:     true,
32046	},
32047	{
32048		name:        "NeqB",
32049		argLen:      2,
32050		commutative: true,
32051		generic:     true,
32052	},
32053	{
32054		name:    "Not",
32055		argLen:  1,
32056		generic: true,
32057	},
32058	{
32059		name:    "Neg8",
32060		argLen:  1,
32061		generic: true,
32062	},
32063	{
32064		name:    "Neg16",
32065		argLen:  1,
32066		generic: true,
32067	},
32068	{
32069		name:    "Neg32",
32070		argLen:  1,
32071		generic: true,
32072	},
32073	{
32074		name:    "Neg64",
32075		argLen:  1,
32076		generic: true,
32077	},
32078	{
32079		name:    "Neg32F",
32080		argLen:  1,
32081		generic: true,
32082	},
32083	{
32084		name:    "Neg64F",
32085		argLen:  1,
32086		generic: true,
32087	},
32088	{
32089		name:    "Com8",
32090		argLen:  1,
32091		generic: true,
32092	},
32093	{
32094		name:    "Com16",
32095		argLen:  1,
32096		generic: true,
32097	},
32098	{
32099		name:    "Com32",
32100		argLen:  1,
32101		generic: true,
32102	},
32103	{
32104		name:    "Com64",
32105		argLen:  1,
32106		generic: true,
32107	},
32108	{
32109		name:    "Ctz8",
32110		argLen:  1,
32111		generic: true,
32112	},
32113	{
32114		name:    "Ctz16",
32115		argLen:  1,
32116		generic: true,
32117	},
32118	{
32119		name:    "Ctz32",
32120		argLen:  1,
32121		generic: true,
32122	},
32123	{
32124		name:    "Ctz64",
32125		argLen:  1,
32126		generic: true,
32127	},
32128	{
32129		name:    "Ctz8NonZero",
32130		argLen:  1,
32131		generic: true,
32132	},
32133	{
32134		name:    "Ctz16NonZero",
32135		argLen:  1,
32136		generic: true,
32137	},
32138	{
32139		name:    "Ctz32NonZero",
32140		argLen:  1,
32141		generic: true,
32142	},
32143	{
32144		name:    "Ctz64NonZero",
32145		argLen:  1,
32146		generic: true,
32147	},
32148	{
32149		name:    "BitLen8",
32150		argLen:  1,
32151		generic: true,
32152	},
32153	{
32154		name:    "BitLen16",
32155		argLen:  1,
32156		generic: true,
32157	},
32158	{
32159		name:    "BitLen32",
32160		argLen:  1,
32161		generic: true,
32162	},
32163	{
32164		name:    "BitLen64",
32165		argLen:  1,
32166		generic: true,
32167	},
32168	{
32169		name:    "Bswap32",
32170		argLen:  1,
32171		generic: true,
32172	},
32173	{
32174		name:    "Bswap64",
32175		argLen:  1,
32176		generic: true,
32177	},
32178	{
32179		name:    "BitRev8",
32180		argLen:  1,
32181		generic: true,
32182	},
32183	{
32184		name:    "BitRev16",
32185		argLen:  1,
32186		generic: true,
32187	},
32188	{
32189		name:    "BitRev32",
32190		argLen:  1,
32191		generic: true,
32192	},
32193	{
32194		name:    "BitRev64",
32195		argLen:  1,
32196		generic: true,
32197	},
32198	{
32199		name:    "PopCount8",
32200		argLen:  1,
32201		generic: true,
32202	},
32203	{
32204		name:    "PopCount16",
32205		argLen:  1,
32206		generic: true,
32207	},
32208	{
32209		name:    "PopCount32",
32210		argLen:  1,
32211		generic: true,
32212	},
32213	{
32214		name:    "PopCount64",
32215		argLen:  1,
32216		generic: true,
32217	},
32218	{
32219		name:    "RotateLeft8",
32220		argLen:  2,
32221		generic: true,
32222	},
32223	{
32224		name:    "RotateLeft16",
32225		argLen:  2,
32226		generic: true,
32227	},
32228	{
32229		name:    "RotateLeft32",
32230		argLen:  2,
32231		generic: true,
32232	},
32233	{
32234		name:    "RotateLeft64",
32235		argLen:  2,
32236		generic: true,
32237	},
32238	{
32239		name:    "Sqrt",
32240		argLen:  1,
32241		generic: true,
32242	},
32243	{
32244		name:    "Floor",
32245		argLen:  1,
32246		generic: true,
32247	},
32248	{
32249		name:    "Ceil",
32250		argLen:  1,
32251		generic: true,
32252	},
32253	{
32254		name:    "Trunc",
32255		argLen:  1,
32256		generic: true,
32257	},
32258	{
32259		name:    "Round",
32260		argLen:  1,
32261		generic: true,
32262	},
32263	{
32264		name:    "RoundToEven",
32265		argLen:  1,
32266		generic: true,
32267	},
32268	{
32269		name:    "Abs",
32270		argLen:  1,
32271		generic: true,
32272	},
32273	{
32274		name:    "Copysign",
32275		argLen:  2,
32276		generic: true,
32277	},
32278	{
32279		name:    "FMA",
32280		argLen:  3,
32281		generic: true,
32282	},
32283	{
32284		name:      "Phi",
32285		argLen:    -1,
32286		zeroWidth: true,
32287		generic:   true,
32288	},
32289	{
32290		name:    "Copy",
32291		argLen:  1,
32292		generic: true,
32293	},
32294	{
32295		name:         "Convert",
32296		argLen:       2,
32297		resultInArg0: true,
32298		zeroWidth:    true,
32299		generic:      true,
32300	},
32301	{
32302		name:    "ConstBool",
32303		auxType: auxBool,
32304		argLen:  0,
32305		generic: true,
32306	},
32307	{
32308		name:    "ConstString",
32309		auxType: auxString,
32310		argLen:  0,
32311		generic: true,
32312	},
32313	{
32314		name:    "ConstNil",
32315		argLen:  0,
32316		generic: true,
32317	},
32318	{
32319		name:    "Const8",
32320		auxType: auxInt8,
32321		argLen:  0,
32322		generic: true,
32323	},
32324	{
32325		name:    "Const16",
32326		auxType: auxInt16,
32327		argLen:  0,
32328		generic: true,
32329	},
32330	{
32331		name:    "Const32",
32332		auxType: auxInt32,
32333		argLen:  0,
32334		generic: true,
32335	},
32336	{
32337		name:    "Const64",
32338		auxType: auxInt64,
32339		argLen:  0,
32340		generic: true,
32341	},
32342	{
32343		name:    "Const32F",
32344		auxType: auxFloat32,
32345		argLen:  0,
32346		generic: true,
32347	},
32348	{
32349		name:    "Const64F",
32350		auxType: auxFloat64,
32351		argLen:  0,
32352		generic: true,
32353	},
32354	{
32355		name:    "ConstInterface",
32356		argLen:  0,
32357		generic: true,
32358	},
32359	{
32360		name:    "ConstSlice",
32361		argLen:  0,
32362		generic: true,
32363	},
32364	{
32365		name:      "InitMem",
32366		argLen:    0,
32367		zeroWidth: true,
32368		generic:   true,
32369	},
32370	{
32371		name:      "Arg",
32372		auxType:   auxSymOff,
32373		argLen:    0,
32374		zeroWidth: true,
32375		symEffect: SymRead,
32376		generic:   true,
32377	},
32378	{
32379		name:      "Addr",
32380		auxType:   auxSym,
32381		argLen:    1,
32382		symEffect: SymAddr,
32383		generic:   true,
32384	},
32385	{
32386		name:      "LocalAddr",
32387		auxType:   auxSym,
32388		argLen:    2,
32389		symEffect: SymAddr,
32390		generic:   true,
32391	},
32392	{
32393		name:      "SP",
32394		argLen:    0,
32395		zeroWidth: true,
32396		generic:   true,
32397	},
32398	{
32399		name:      "SB",
32400		argLen:    0,
32401		zeroWidth: true,
32402		generic:   true,
32403	},
32404	{
32405		name:    "Load",
32406		argLen:  2,
32407		generic: true,
32408	},
32409	{
32410		name:    "Store",
32411		auxType: auxTyp,
32412		argLen:  3,
32413		generic: true,
32414	},
32415	{
32416		name:    "Move",
32417		auxType: auxTypSize,
32418		argLen:  3,
32419		generic: true,
32420	},
32421	{
32422		name:    "Zero",
32423		auxType: auxTypSize,
32424		argLen:  2,
32425		generic: true,
32426	},
32427	{
32428		name:    "StoreWB",
32429		auxType: auxTyp,
32430		argLen:  3,
32431		generic: true,
32432	},
32433	{
32434		name:    "MoveWB",
32435		auxType: auxTypSize,
32436		argLen:  3,
32437		generic: true,
32438	},
32439	{
32440		name:    "ZeroWB",
32441		auxType: auxTypSize,
32442		argLen:  2,
32443		generic: true,
32444	},
32445	{
32446		name:      "WB",
32447		auxType:   auxSym,
32448		argLen:    3,
32449		symEffect: SymNone,
32450		generic:   true,
32451	},
32452	{
32453		name:    "PanicBounds",
32454		auxType: auxInt64,
32455		argLen:  3,
32456		generic: true,
32457	},
32458	{
32459		name:    "PanicExtend",
32460		auxType: auxInt64,
32461		argLen:  4,
32462		generic: true,
32463	},
32464	{
32465		name:    "ClosureCall",
32466		auxType: auxInt64,
32467		argLen:  3,
32468		call:    true,
32469		generic: true,
32470	},
32471	{
32472		name:      "StaticCall",
32473		auxType:   auxSymOff,
32474		argLen:    1,
32475		call:      true,
32476		symEffect: SymNone,
32477		generic:   true,
32478	},
32479	{
32480		name:    "InterCall",
32481		auxType: auxInt64,
32482		argLen:  2,
32483		call:    true,
32484		generic: true,
32485	},
32486	{
32487		name:    "SignExt8to16",
32488		argLen:  1,
32489		generic: true,
32490	},
32491	{
32492		name:    "SignExt8to32",
32493		argLen:  1,
32494		generic: true,
32495	},
32496	{
32497		name:    "SignExt8to64",
32498		argLen:  1,
32499		generic: true,
32500	},
32501	{
32502		name:    "SignExt16to32",
32503		argLen:  1,
32504		generic: true,
32505	},
32506	{
32507		name:    "SignExt16to64",
32508		argLen:  1,
32509		generic: true,
32510	},
32511	{
32512		name:    "SignExt32to64",
32513		argLen:  1,
32514		generic: true,
32515	},
32516	{
32517		name:    "ZeroExt8to16",
32518		argLen:  1,
32519		generic: true,
32520	},
32521	{
32522		name:    "ZeroExt8to32",
32523		argLen:  1,
32524		generic: true,
32525	},
32526	{
32527		name:    "ZeroExt8to64",
32528		argLen:  1,
32529		generic: true,
32530	},
32531	{
32532		name:    "ZeroExt16to32",
32533		argLen:  1,
32534		generic: true,
32535	},
32536	{
32537		name:    "ZeroExt16to64",
32538		argLen:  1,
32539		generic: true,
32540	},
32541	{
32542		name:    "ZeroExt32to64",
32543		argLen:  1,
32544		generic: true,
32545	},
32546	{
32547		name:    "Trunc16to8",
32548		argLen:  1,
32549		generic: true,
32550	},
32551	{
32552		name:    "Trunc32to8",
32553		argLen:  1,
32554		generic: true,
32555	},
32556	{
32557		name:    "Trunc32to16",
32558		argLen:  1,
32559		generic: true,
32560	},
32561	{
32562		name:    "Trunc64to8",
32563		argLen:  1,
32564		generic: true,
32565	},
32566	{
32567		name:    "Trunc64to16",
32568		argLen:  1,
32569		generic: true,
32570	},
32571	{
32572		name:    "Trunc64to32",
32573		argLen:  1,
32574		generic: true,
32575	},
32576	{
32577		name:    "Cvt32to32F",
32578		argLen:  1,
32579		generic: true,
32580	},
32581	{
32582		name:    "Cvt32to64F",
32583		argLen:  1,
32584		generic: true,
32585	},
32586	{
32587		name:    "Cvt64to32F",
32588		argLen:  1,
32589		generic: true,
32590	},
32591	{
32592		name:    "Cvt64to64F",
32593		argLen:  1,
32594		generic: true,
32595	},
32596	{
32597		name:    "Cvt32Fto32",
32598		argLen:  1,
32599		generic: true,
32600	},
32601	{
32602		name:    "Cvt32Fto64",
32603		argLen:  1,
32604		generic: true,
32605	},
32606	{
32607		name:    "Cvt64Fto32",
32608		argLen:  1,
32609		generic: true,
32610	},
32611	{
32612		name:    "Cvt64Fto64",
32613		argLen:  1,
32614		generic: true,
32615	},
32616	{
32617		name:    "Cvt32Fto64F",
32618		argLen:  1,
32619		generic: true,
32620	},
32621	{
32622		name:    "Cvt64Fto32F",
32623		argLen:  1,
32624		generic: true,
32625	},
32626	{
32627		name:    "Round32F",
32628		argLen:  1,
32629		generic: true,
32630	},
32631	{
32632		name:    "Round64F",
32633		argLen:  1,
32634		generic: true,
32635	},
32636	{
32637		name:    "IsNonNil",
32638		argLen:  1,
32639		generic: true,
32640	},
32641	{
32642		name:    "IsInBounds",
32643		argLen:  2,
32644		generic: true,
32645	},
32646	{
32647		name:    "IsSliceInBounds",
32648		argLen:  2,
32649		generic: true,
32650	},
32651	{
32652		name:    "NilCheck",
32653		argLen:  2,
32654		generic: true,
32655	},
32656	{
32657		name:      "GetG",
32658		argLen:    1,
32659		zeroWidth: true,
32660		generic:   true,
32661	},
32662	{
32663		name:    "GetClosurePtr",
32664		argLen:  0,
32665		generic: true,
32666	},
32667	{
32668		name:    "GetCallerPC",
32669		argLen:  0,
32670		generic: true,
32671	},
32672	{
32673		name:    "GetCallerSP",
32674		argLen:  0,
32675		generic: true,
32676	},
32677	{
32678		name:    "PtrIndex",
32679		argLen:  2,
32680		generic: true,
32681	},
32682	{
32683		name:    "OffPtr",
32684		auxType: auxInt64,
32685		argLen:  1,
32686		generic: true,
32687	},
32688	{
32689		name:    "SliceMake",
32690		argLen:  3,
32691		generic: true,
32692	},
32693	{
32694		name:    "SlicePtr",
32695		argLen:  1,
32696		generic: true,
32697	},
32698	{
32699		name:    "SliceLen",
32700		argLen:  1,
32701		generic: true,
32702	},
32703	{
32704		name:    "SliceCap",
32705		argLen:  1,
32706		generic: true,
32707	},
32708	{
32709		name:    "ComplexMake",
32710		argLen:  2,
32711		generic: true,
32712	},
32713	{
32714		name:    "ComplexReal",
32715		argLen:  1,
32716		generic: true,
32717	},
32718	{
32719		name:    "ComplexImag",
32720		argLen:  1,
32721		generic: true,
32722	},
32723	{
32724		name:    "StringMake",
32725		argLen:  2,
32726		generic: true,
32727	},
32728	{
32729		name:    "StringPtr",
32730		argLen:  1,
32731		generic: true,
32732	},
32733	{
32734		name:    "StringLen",
32735		argLen:  1,
32736		generic: true,
32737	},
32738	{
32739		name:    "IMake",
32740		argLen:  2,
32741		generic: true,
32742	},
32743	{
32744		name:    "ITab",
32745		argLen:  1,
32746		generic: true,
32747	},
32748	{
32749		name:    "IData",
32750		argLen:  1,
32751		generic: true,
32752	},
32753	{
32754		name:    "StructMake0",
32755		argLen:  0,
32756		generic: true,
32757	},
32758	{
32759		name:    "StructMake1",
32760		argLen:  1,
32761		generic: true,
32762	},
32763	{
32764		name:    "StructMake2",
32765		argLen:  2,
32766		generic: true,
32767	},
32768	{
32769		name:    "StructMake3",
32770		argLen:  3,
32771		generic: true,
32772	},
32773	{
32774		name:    "StructMake4",
32775		argLen:  4,
32776		generic: true,
32777	},
32778	{
32779		name:    "StructSelect",
32780		auxType: auxInt64,
32781		argLen:  1,
32782		generic: true,
32783	},
32784	{
32785		name:    "ArrayMake0",
32786		argLen:  0,
32787		generic: true,
32788	},
32789	{
32790		name:    "ArrayMake1",
32791		argLen:  1,
32792		generic: true,
32793	},
32794	{
32795		name:    "ArraySelect",
32796		auxType: auxInt64,
32797		argLen:  1,
32798		generic: true,
32799	},
32800	{
32801		name:    "StoreReg",
32802		argLen:  1,
32803		generic: true,
32804	},
32805	{
32806		name:    "LoadReg",
32807		argLen:  1,
32808		generic: true,
32809	},
32810	{
32811		name:      "FwdRef",
32812		auxType:   auxSym,
32813		argLen:    0,
32814		symEffect: SymNone,
32815		generic:   true,
32816	},
32817	{
32818		name:    "Unknown",
32819		argLen:  0,
32820		generic: true,
32821	},
32822	{
32823		name:      "VarDef",
32824		auxType:   auxSym,
32825		argLen:    1,
32826		zeroWidth: true,
32827		symEffect: SymNone,
32828		generic:   true,
32829	},
32830	{
32831		name:      "VarKill",
32832		auxType:   auxSym,
32833		argLen:    1,
32834		symEffect: SymNone,
32835		generic:   true,
32836	},
32837	{
32838		name:      "VarLive",
32839		auxType:   auxSym,
32840		argLen:    1,
32841		zeroWidth: true,
32842		symEffect: SymRead,
32843		generic:   true,
32844	},
32845	{
32846		name:      "KeepAlive",
32847		argLen:    2,
32848		zeroWidth: true,
32849		generic:   true,
32850	},
32851	{
32852		name:    "InlMark",
32853		auxType: auxInt32,
32854		argLen:  1,
32855		generic: true,
32856	},
32857	{
32858		name:    "Int64Make",
32859		argLen:  2,
32860		generic: true,
32861	},
32862	{
32863		name:    "Int64Hi",
32864		argLen:  1,
32865		generic: true,
32866	},
32867	{
32868		name:    "Int64Lo",
32869		argLen:  1,
32870		generic: true,
32871	},
32872	{
32873		name:        "Add32carry",
32874		argLen:      2,
32875		commutative: true,
32876		generic:     true,
32877	},
32878	{
32879		name:        "Add32withcarry",
32880		argLen:      3,
32881		commutative: true,
32882		generic:     true,
32883	},
32884	{
32885		name:    "Sub32carry",
32886		argLen:  2,
32887		generic: true,
32888	},
32889	{
32890		name:    "Sub32withcarry",
32891		argLen:  3,
32892		generic: true,
32893	},
32894	{
32895		name:        "Add64carry",
32896		argLen:      3,
32897		commutative: true,
32898		generic:     true,
32899	},
32900	{
32901		name:    "Sub64borrow",
32902		argLen:  3,
32903		generic: true,
32904	},
32905	{
32906		name:    "Signmask",
32907		argLen:  1,
32908		generic: true,
32909	},
32910	{
32911		name:    "Zeromask",
32912		argLen:  1,
32913		generic: true,
32914	},
32915	{
32916		name:    "Slicemask",
32917		argLen:  1,
32918		generic: true,
32919	},
32920	{
32921		name:    "Cvt32Uto32F",
32922		argLen:  1,
32923		generic: true,
32924	},
32925	{
32926		name:    "Cvt32Uto64F",
32927		argLen:  1,
32928		generic: true,
32929	},
32930	{
32931		name:    "Cvt32Fto32U",
32932		argLen:  1,
32933		generic: true,
32934	},
32935	{
32936		name:    "Cvt64Fto32U",
32937		argLen:  1,
32938		generic: true,
32939	},
32940	{
32941		name:    "Cvt64Uto32F",
32942		argLen:  1,
32943		generic: true,
32944	},
32945	{
32946		name:    "Cvt64Uto64F",
32947		argLen:  1,
32948		generic: true,
32949	},
32950	{
32951		name:    "Cvt32Fto64U",
32952		argLen:  1,
32953		generic: true,
32954	},
32955	{
32956		name:    "Cvt64Fto64U",
32957		argLen:  1,
32958		generic: true,
32959	},
32960	{
32961		name:      "Select0",
32962		argLen:    1,
32963		zeroWidth: true,
32964		generic:   true,
32965	},
32966	{
32967		name:      "Select1",
32968		argLen:    1,
32969		zeroWidth: true,
32970		generic:   true,
32971	},
32972	{
32973		name:    "AtomicLoad8",
32974		argLen:  2,
32975		generic: true,
32976	},
32977	{
32978		name:    "AtomicLoad32",
32979		argLen:  2,
32980		generic: true,
32981	},
32982	{
32983		name:    "AtomicLoad64",
32984		argLen:  2,
32985		generic: true,
32986	},
32987	{
32988		name:    "AtomicLoadPtr",
32989		argLen:  2,
32990		generic: true,
32991	},
32992	{
32993		name:    "AtomicLoadAcq32",
32994		argLen:  2,
32995		generic: true,
32996	},
32997	{
32998		name:           "AtomicStore8",
32999		argLen:         3,
33000		hasSideEffects: true,
33001		generic:        true,
33002	},
33003	{
33004		name:           "AtomicStore32",
33005		argLen:         3,
33006		hasSideEffects: true,
33007		generic:        true,
33008	},
33009	{
33010		name:           "AtomicStore64",
33011		argLen:         3,
33012		hasSideEffects: true,
33013		generic:        true,
33014	},
33015	{
33016		name:           "AtomicStorePtrNoWB",
33017		argLen:         3,
33018		hasSideEffects: true,
33019		generic:        true,
33020	},
33021	{
33022		name:           "AtomicStoreRel32",
33023		argLen:         3,
33024		hasSideEffects: true,
33025		generic:        true,
33026	},
33027	{
33028		name:           "AtomicExchange32",
33029		argLen:         3,
33030		hasSideEffects: true,
33031		generic:        true,
33032	},
33033	{
33034		name:           "AtomicExchange64",
33035		argLen:         3,
33036		hasSideEffects: true,
33037		generic:        true,
33038	},
33039	{
33040		name:           "AtomicAdd32",
33041		argLen:         3,
33042		hasSideEffects: true,
33043		generic:        true,
33044	},
33045	{
33046		name:           "AtomicAdd64",
33047		argLen:         3,
33048		hasSideEffects: true,
33049		generic:        true,
33050	},
33051	{
33052		name:           "AtomicCompareAndSwap32",
33053		argLen:         4,
33054		hasSideEffects: true,
33055		generic:        true,
33056	},
33057	{
33058		name:           "AtomicCompareAndSwap64",
33059		argLen:         4,
33060		hasSideEffects: true,
33061		generic:        true,
33062	},
33063	{
33064		name:           "AtomicCompareAndSwapRel32",
33065		argLen:         4,
33066		hasSideEffects: true,
33067		generic:        true,
33068	},
33069	{
33070		name:           "AtomicAnd8",
33071		argLen:         3,
33072		hasSideEffects: true,
33073		generic:        true,
33074	},
33075	{
33076		name:           "AtomicOr8",
33077		argLen:         3,
33078		hasSideEffects: true,
33079		generic:        true,
33080	},
33081	{
33082		name:           "AtomicAdd32Variant",
33083		argLen:         3,
33084		hasSideEffects: true,
33085		generic:        true,
33086	},
33087	{
33088		name:           "AtomicAdd64Variant",
33089		argLen:         3,
33090		hasSideEffects: true,
33091		generic:        true,
33092	},
33093	{
33094		name:      "Clobber",
33095		auxType:   auxSymOff,
33096		argLen:    0,
33097		symEffect: SymNone,
33098		generic:   true,
33099	},
33100}
33101
33102func (o Op) Asm() obj.As          { return opcodeTable[o].asm }
33103func (o Op) Scale() int16         { return int16(opcodeTable[o].scale) }
33104func (o Op) String() string       { return opcodeTable[o].name }
33105func (o Op) UsesScratch() bool    { return opcodeTable[o].usesScratch }
33106func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect }
33107func (o Op) IsCall() bool         { return opcodeTable[o].call }
33108func (o Op) HasSideEffects() bool { return opcodeTable[o].hasSideEffects }
33109func (o Op) UnsafePoint() bool    { return opcodeTable[o].unsafePoint }
33110
33111var registers386 = [...]Register{
33112	{0, x86.REG_AX, 0, "AX"},
33113	{1, x86.REG_CX, 1, "CX"},
33114	{2, x86.REG_DX, 2, "DX"},
33115	{3, x86.REG_BX, 3, "BX"},
33116	{4, x86.REGSP, -1, "SP"},
33117	{5, x86.REG_BP, 4, "BP"},
33118	{6, x86.REG_SI, 5, "SI"},
33119	{7, x86.REG_DI, 6, "DI"},
33120	{8, x86.REG_X0, -1, "X0"},
33121	{9, x86.REG_X1, -1, "X1"},
33122	{10, x86.REG_X2, -1, "X2"},
33123	{11, x86.REG_X3, -1, "X3"},
33124	{12, x86.REG_X4, -1, "X4"},
33125	{13, x86.REG_X5, -1, "X5"},
33126	{14, x86.REG_X6, -1, "X6"},
33127	{15, x86.REG_X7, -1, "X7"},
33128	{16, 0, -1, "SB"},
33129}
33130var gpRegMask386 = regMask(239)
33131var fpRegMask386 = regMask(65280)
33132var specialRegMask386 = regMask(0)
33133var framepointerReg386 = int8(5)
33134var linkReg386 = int8(-1)
33135var registersAMD64 = [...]Register{
33136	{0, x86.REG_AX, 0, "AX"},
33137	{1, x86.REG_CX, 1, "CX"},
33138	{2, x86.REG_DX, 2, "DX"},
33139	{3, x86.REG_BX, 3, "BX"},
33140	{4, x86.REGSP, -1, "SP"},
33141	{5, x86.REG_BP, 4, "BP"},
33142	{6, x86.REG_SI, 5, "SI"},
33143	{7, x86.REG_DI, 6, "DI"},
33144	{8, x86.REG_R8, 7, "R8"},
33145	{9, x86.REG_R9, 8, "R9"},
33146	{10, x86.REG_R10, 9, "R10"},
33147	{11, x86.REG_R11, 10, "R11"},
33148	{12, x86.REG_R12, 11, "R12"},
33149	{13, x86.REG_R13, 12, "R13"},
33150	{14, x86.REG_R14, 13, "R14"},
33151	{15, x86.REG_R15, 14, "R15"},
33152	{16, x86.REG_X0, -1, "X0"},
33153	{17, x86.REG_X1, -1, "X1"},
33154	{18, x86.REG_X2, -1, "X2"},
33155	{19, x86.REG_X3, -1, "X3"},
33156	{20, x86.REG_X4, -1, "X4"},
33157	{21, x86.REG_X5, -1, "X5"},
33158	{22, x86.REG_X6, -1, "X6"},
33159	{23, x86.REG_X7, -1, "X7"},
33160	{24, x86.REG_X8, -1, "X8"},
33161	{25, x86.REG_X9, -1, "X9"},
33162	{26, x86.REG_X10, -1, "X10"},
33163	{27, x86.REG_X11, -1, "X11"},
33164	{28, x86.REG_X12, -1, "X12"},
33165	{29, x86.REG_X13, -1, "X13"},
33166	{30, x86.REG_X14, -1, "X14"},
33167	{31, x86.REG_X15, -1, "X15"},
33168	{32, 0, -1, "SB"},
33169}
33170var gpRegMaskAMD64 = regMask(65519)
33171var fpRegMaskAMD64 = regMask(4294901760)
33172var specialRegMaskAMD64 = regMask(0)
33173var framepointerRegAMD64 = int8(5)
33174var linkRegAMD64 = int8(-1)
33175var registersARM = [...]Register{
33176	{0, arm.REG_R0, 0, "R0"},
33177	{1, arm.REG_R1, 1, "R1"},
33178	{2, arm.REG_R2, 2, "R2"},
33179	{3, arm.REG_R3, 3, "R3"},
33180	{4, arm.REG_R4, 4, "R4"},
33181	{5, arm.REG_R5, 5, "R5"},
33182	{6, arm.REG_R6, 6, "R6"},
33183	{7, arm.REG_R7, 7, "R7"},
33184	{8, arm.REG_R8, 8, "R8"},
33185	{9, arm.REG_R9, 9, "R9"},
33186	{10, arm.REGG, -1, "g"},
33187	{11, arm.REG_R11, -1, "R11"},
33188	{12, arm.REG_R12, 10, "R12"},
33189	{13, arm.REGSP, -1, "SP"},
33190	{14, arm.REG_R14, 11, "R14"},
33191	{15, arm.REG_R15, -1, "R15"},
33192	{16, arm.REG_F0, -1, "F0"},
33193	{17, arm.REG_F1, -1, "F1"},
33194	{18, arm.REG_F2, -1, "F2"},
33195	{19, arm.REG_F3, -1, "F3"},
33196	{20, arm.REG_F4, -1, "F4"},
33197	{21, arm.REG_F5, -1, "F5"},
33198	{22, arm.REG_F6, -1, "F6"},
33199	{23, arm.REG_F7, -1, "F7"},
33200	{24, arm.REG_F8, -1, "F8"},
33201	{25, arm.REG_F9, -1, "F9"},
33202	{26, arm.REG_F10, -1, "F10"},
33203	{27, arm.REG_F11, -1, "F11"},
33204	{28, arm.REG_F12, -1, "F12"},
33205	{29, arm.REG_F13, -1, "F13"},
33206	{30, arm.REG_F14, -1, "F14"},
33207	{31, arm.REG_F15, -1, "F15"},
33208	{32, 0, -1, "SB"},
33209}
33210var gpRegMaskARM = regMask(21503)
33211var fpRegMaskARM = regMask(4294901760)
33212var specialRegMaskARM = regMask(0)
33213var framepointerRegARM = int8(-1)
33214var linkRegARM = int8(14)
33215var registersARM64 = [...]Register{
33216	{0, arm64.REG_R0, 0, "R0"},
33217	{1, arm64.REG_R1, 1, "R1"},
33218	{2, arm64.REG_R2, 2, "R2"},
33219	{3, arm64.REG_R3, 3, "R3"},
33220	{4, arm64.REG_R4, 4, "R4"},
33221	{5, arm64.REG_R5, 5, "R5"},
33222	{6, arm64.REG_R6, 6, "R6"},
33223	{7, arm64.REG_R7, 7, "R7"},
33224	{8, arm64.REG_R8, 8, "R8"},
33225	{9, arm64.REG_R9, 9, "R9"},
33226	{10, arm64.REG_R10, 10, "R10"},
33227	{11, arm64.REG_R11, 11, "R11"},
33228	{12, arm64.REG_R12, 12, "R12"},
33229	{13, arm64.REG_R13, 13, "R13"},
33230	{14, arm64.REG_R14, 14, "R14"},
33231	{15, arm64.REG_R15, 15, "R15"},
33232	{16, arm64.REG_R16, 16, "R16"},
33233	{17, arm64.REG_R17, 17, "R17"},
33234	{18, arm64.REG_R18, -1, "R18"},
33235	{19, arm64.REG_R19, 18, "R19"},
33236	{20, arm64.REG_R20, 19, "R20"},
33237	{21, arm64.REG_R21, 20, "R21"},
33238	{22, arm64.REG_R22, 21, "R22"},
33239	{23, arm64.REG_R23, 22, "R23"},
33240	{24, arm64.REG_R24, 23, "R24"},
33241	{25, arm64.REG_R25, 24, "R25"},
33242	{26, arm64.REG_R26, 25, "R26"},
33243	{27, arm64.REGG, -1, "g"},
33244	{28, arm64.REG_R29, -1, "R29"},
33245	{29, arm64.REG_R30, 26, "R30"},
33246	{30, arm64.REGSP, -1, "SP"},
33247	{31, arm64.REG_F0, -1, "F0"},
33248	{32, arm64.REG_F1, -1, "F1"},
33249	{33, arm64.REG_F2, -1, "F2"},
33250	{34, arm64.REG_F3, -1, "F3"},
33251	{35, arm64.REG_F4, -1, "F4"},
33252	{36, arm64.REG_F5, -1, "F5"},
33253	{37, arm64.REG_F6, -1, "F6"},
33254	{38, arm64.REG_F7, -1, "F7"},
33255	{39, arm64.REG_F8, -1, "F8"},
33256	{40, arm64.REG_F9, -1, "F9"},
33257	{41, arm64.REG_F10, -1, "F10"},
33258	{42, arm64.REG_F11, -1, "F11"},
33259	{43, arm64.REG_F12, -1, "F12"},
33260	{44, arm64.REG_F13, -1, "F13"},
33261	{45, arm64.REG_F14, -1, "F14"},
33262	{46, arm64.REG_F15, -1, "F15"},
33263	{47, arm64.REG_F16, -1, "F16"},
33264	{48, arm64.REG_F17, -1, "F17"},
33265	{49, arm64.REG_F18, -1, "F18"},
33266	{50, arm64.REG_F19, -1, "F19"},
33267	{51, arm64.REG_F20, -1, "F20"},
33268	{52, arm64.REG_F21, -1, "F21"},
33269	{53, arm64.REG_F22, -1, "F22"},
33270	{54, arm64.REG_F23, -1, "F23"},
33271	{55, arm64.REG_F24, -1, "F24"},
33272	{56, arm64.REG_F25, -1, "F25"},
33273	{57, arm64.REG_F26, -1, "F26"},
33274	{58, arm64.REG_F27, -1, "F27"},
33275	{59, arm64.REG_F28, -1, "F28"},
33276	{60, arm64.REG_F29, -1, "F29"},
33277	{61, arm64.REG_F30, -1, "F30"},
33278	{62, arm64.REG_F31, -1, "F31"},
33279	{63, 0, -1, "SB"},
33280}
33281var gpRegMaskARM64 = regMask(670826495)
33282var fpRegMaskARM64 = regMask(9223372034707292160)
33283var specialRegMaskARM64 = regMask(0)
33284var framepointerRegARM64 = int8(-1)
33285var linkRegARM64 = int8(29)
33286var registersMIPS = [...]Register{
33287	{0, mips.REG_R0, -1, "R0"},
33288	{1, mips.REG_R1, 0, "R1"},
33289	{2, mips.REG_R2, 1, "R2"},
33290	{3, mips.REG_R3, 2, "R3"},
33291	{4, mips.REG_R4, 3, "R4"},
33292	{5, mips.REG_R5, 4, "R5"},
33293	{6, mips.REG_R6, 5, "R6"},
33294	{7, mips.REG_R7, 6, "R7"},
33295	{8, mips.REG_R8, 7, "R8"},
33296	{9, mips.REG_R9, 8, "R9"},
33297	{10, mips.REG_R10, 9, "R10"},
33298	{11, mips.REG_R11, 10, "R11"},
33299	{12, mips.REG_R12, 11, "R12"},
33300	{13, mips.REG_R13, 12, "R13"},
33301	{14, mips.REG_R14, 13, "R14"},
33302	{15, mips.REG_R15, 14, "R15"},
33303	{16, mips.REG_R16, 15, "R16"},
33304	{17, mips.REG_R17, 16, "R17"},
33305	{18, mips.REG_R18, 17, "R18"},
33306	{19, mips.REG_R19, 18, "R19"},
33307	{20, mips.REG_R20, 19, "R20"},
33308	{21, mips.REG_R21, 20, "R21"},
33309	{22, mips.REG_R22, 21, "R22"},
33310	{23, mips.REG_R24, 22, "R24"},
33311	{24, mips.REG_R25, 23, "R25"},
33312	{25, mips.REG_R28, 24, "R28"},
33313	{26, mips.REGSP, -1, "SP"},
33314	{27, mips.REGG, -1, "g"},
33315	{28, mips.REG_R31, 25, "R31"},
33316	{29, mips.REG_F0, -1, "F0"},
33317	{30, mips.REG_F2, -1, "F2"},
33318	{31, mips.REG_F4, -1, "F4"},
33319	{32, mips.REG_F6, -1, "F6"},
33320	{33, mips.REG_F8, -1, "F8"},
33321	{34, mips.REG_F10, -1, "F10"},
33322	{35, mips.REG_F12, -1, "F12"},
33323	{36, mips.REG_F14, -1, "F14"},
33324	{37, mips.REG_F16, -1, "F16"},
33325	{38, mips.REG_F18, -1, "F18"},
33326	{39, mips.REG_F20, -1, "F20"},
33327	{40, mips.REG_F22, -1, "F22"},
33328	{41, mips.REG_F24, -1, "F24"},
33329	{42, mips.REG_F26, -1, "F26"},
33330	{43, mips.REG_F28, -1, "F28"},
33331	{44, mips.REG_F30, -1, "F30"},
33332	{45, mips.REG_HI, -1, "HI"},
33333	{46, mips.REG_LO, -1, "LO"},
33334	{47, 0, -1, "SB"},
33335}
33336var gpRegMaskMIPS = regMask(335544318)
33337var fpRegMaskMIPS = regMask(35183835217920)
33338var specialRegMaskMIPS = regMask(105553116266496)
33339var framepointerRegMIPS = int8(-1)
33340var linkRegMIPS = int8(28)
33341var registersMIPS64 = [...]Register{
33342	{0, mips.REG_R0, -1, "R0"},
33343	{1, mips.REG_R1, 0, "R1"},
33344	{2, mips.REG_R2, 1, "R2"},
33345	{3, mips.REG_R3, 2, "R3"},
33346	{4, mips.REG_R4, 3, "R4"},
33347	{5, mips.REG_R5, 4, "R5"},
33348	{6, mips.REG_R6, 5, "R6"},
33349	{7, mips.REG_R7, 6, "R7"},
33350	{8, mips.REG_R8, 7, "R8"},
33351	{9, mips.REG_R9, 8, "R9"},
33352	{10, mips.REG_R10, 9, "R10"},
33353	{11, mips.REG_R11, 10, "R11"},
33354	{12, mips.REG_R12, 11, "R12"},
33355	{13, mips.REG_R13, 12, "R13"},
33356	{14, mips.REG_R14, 13, "R14"},
33357	{15, mips.REG_R15, 14, "R15"},
33358	{16, mips.REG_R16, 15, "R16"},
33359	{17, mips.REG_R17, 16, "R17"},
33360	{18, mips.REG_R18, 17, "R18"},
33361	{19, mips.REG_R19, 18, "R19"},
33362	{20, mips.REG_R20, 19, "R20"},
33363	{21, mips.REG_R21, 20, "R21"},
33364	{22, mips.REG_R22, 21, "R22"},
33365	{23, mips.REG_R24, 22, "R24"},
33366	{24, mips.REG_R25, 23, "R25"},
33367	{25, mips.REGSP, -1, "SP"},
33368	{26, mips.REGG, -1, "g"},
33369	{27, mips.REG_R31, 24, "R31"},
33370	{28, mips.REG_F0, -1, "F0"},
33371	{29, mips.REG_F1, -1, "F1"},
33372	{30, mips.REG_F2, -1, "F2"},
33373	{31, mips.REG_F3, -1, "F3"},
33374	{32, mips.REG_F4, -1, "F4"},
33375	{33, mips.REG_F5, -1, "F5"},
33376	{34, mips.REG_F6, -1, "F6"},
33377	{35, mips.REG_F7, -1, "F7"},
33378	{36, mips.REG_F8, -1, "F8"},
33379	{37, mips.REG_F9, -1, "F9"},
33380	{38, mips.REG_F10, -1, "F10"},
33381	{39, mips.REG_F11, -1, "F11"},
33382	{40, mips.REG_F12, -1, "F12"},
33383	{41, mips.REG_F13, -1, "F13"},
33384	{42, mips.REG_F14, -1, "F14"},
33385	{43, mips.REG_F15, -1, "F15"},
33386	{44, mips.REG_F16, -1, "F16"},
33387	{45, mips.REG_F17, -1, "F17"},
33388	{46, mips.REG_F18, -1, "F18"},
33389	{47, mips.REG_F19, -1, "F19"},
33390	{48, mips.REG_F20, -1, "F20"},
33391	{49, mips.REG_F21, -1, "F21"},
33392	{50, mips.REG_F22, -1, "F22"},
33393	{51, mips.REG_F23, -1, "F23"},
33394	{52, mips.REG_F24, -1, "F24"},
33395	{53, mips.REG_F25, -1, "F25"},
33396	{54, mips.REG_F26, -1, "F26"},
33397	{55, mips.REG_F27, -1, "F27"},
33398	{56, mips.REG_F28, -1, "F28"},
33399	{57, mips.REG_F29, -1, "F29"},
33400	{58, mips.REG_F30, -1, "F30"},
33401	{59, mips.REG_F31, -1, "F31"},
33402	{60, mips.REG_HI, -1, "HI"},
33403	{61, mips.REG_LO, -1, "LO"},
33404	{62, 0, -1, "SB"},
33405}
33406var gpRegMaskMIPS64 = regMask(167772158)
33407var fpRegMaskMIPS64 = regMask(1152921504338411520)
33408var specialRegMaskMIPS64 = regMask(3458764513820540928)
33409var framepointerRegMIPS64 = int8(-1)
33410var linkRegMIPS64 = int8(27)
33411var registersPPC64 = [...]Register{
33412	{0, ppc64.REG_R0, -1, "R0"},
33413	{1, ppc64.REGSP, -1, "SP"},
33414	{2, 0, -1, "SB"},
33415	{3, ppc64.REG_R3, 0, "R3"},
33416	{4, ppc64.REG_R4, 1, "R4"},
33417	{5, ppc64.REG_R5, 2, "R5"},
33418	{6, ppc64.REG_R6, 3, "R6"},
33419	{7, ppc64.REG_R7, 4, "R7"},
33420	{8, ppc64.REG_R8, 5, "R8"},
33421	{9, ppc64.REG_R9, 6, "R9"},
33422	{10, ppc64.REG_R10, 7, "R10"},
33423	{11, ppc64.REG_R11, 8, "R11"},
33424	{12, ppc64.REG_R12, 9, "R12"},
33425	{13, ppc64.REG_R13, -1, "R13"},
33426	{14, ppc64.REG_R14, 10, "R14"},
33427	{15, ppc64.REG_R15, 11, "R15"},
33428	{16, ppc64.REG_R16, 12, "R16"},
33429	{17, ppc64.REG_R17, 13, "R17"},
33430	{18, ppc64.REG_R18, 14, "R18"},
33431	{19, ppc64.REG_R19, 15, "R19"},
33432	{20, ppc64.REG_R20, 16, "R20"},
33433	{21, ppc64.REG_R21, 17, "R21"},
33434	{22, ppc64.REG_R22, 18, "R22"},
33435	{23, ppc64.REG_R23, 19, "R23"},
33436	{24, ppc64.REG_R24, 20, "R24"},
33437	{25, ppc64.REG_R25, 21, "R25"},
33438	{26, ppc64.REG_R26, 22, "R26"},
33439	{27, ppc64.REG_R27, 23, "R27"},
33440	{28, ppc64.REG_R28, 24, "R28"},
33441	{29, ppc64.REG_R29, 25, "R29"},
33442	{30, ppc64.REGG, -1, "g"},
33443	{31, ppc64.REG_R31, -1, "R31"},
33444	{32, ppc64.REG_F0, -1, "F0"},
33445	{33, ppc64.REG_F1, -1, "F1"},
33446	{34, ppc64.REG_F2, -1, "F2"},
33447	{35, ppc64.REG_F3, -1, "F3"},
33448	{36, ppc64.REG_F4, -1, "F4"},
33449	{37, ppc64.REG_F5, -1, "F5"},
33450	{38, ppc64.REG_F6, -1, "F6"},
33451	{39, ppc64.REG_F7, -1, "F7"},
33452	{40, ppc64.REG_F8, -1, "F8"},
33453	{41, ppc64.REG_F9, -1, "F9"},
33454	{42, ppc64.REG_F10, -1, "F10"},
33455	{43, ppc64.REG_F11, -1, "F11"},
33456	{44, ppc64.REG_F12, -1, "F12"},
33457	{45, ppc64.REG_F13, -1, "F13"},
33458	{46, ppc64.REG_F14, -1, "F14"},
33459	{47, ppc64.REG_F15, -1, "F15"},
33460	{48, ppc64.REG_F16, -1, "F16"},
33461	{49, ppc64.REG_F17, -1, "F17"},
33462	{50, ppc64.REG_F18, -1, "F18"},
33463	{51, ppc64.REG_F19, -1, "F19"},
33464	{52, ppc64.REG_F20, -1, "F20"},
33465	{53, ppc64.REG_F21, -1, "F21"},
33466	{54, ppc64.REG_F22, -1, "F22"},
33467	{55, ppc64.REG_F23, -1, "F23"},
33468	{56, ppc64.REG_F24, -1, "F24"},
33469	{57, ppc64.REG_F25, -1, "F25"},
33470	{58, ppc64.REG_F26, -1, "F26"},
33471	{59, ppc64.REG_F27, -1, "F27"},
33472	{60, ppc64.REG_F28, -1, "F28"},
33473	{61, ppc64.REG_F29, -1, "F29"},
33474	{62, ppc64.REG_F30, -1, "F30"},
33475	{63, ppc64.REG_F31, -1, "F31"},
33476}
33477var gpRegMaskPPC64 = regMask(1073733624)
33478var fpRegMaskPPC64 = regMask(576460743713488896)
33479var specialRegMaskPPC64 = regMask(0)
33480var framepointerRegPPC64 = int8(1)
33481var linkRegPPC64 = int8(-1)
33482var registersRISCV64 = [...]Register{
33483	{0, riscv.REG_X0, -1, "X0"},
33484	{1, riscv.REGSP, -1, "SP"},
33485	{2, riscv.REG_X3, 0, "X3"},
33486	{3, riscv.REGG, -1, "g"},
33487	{4, riscv.REG_X5, 1, "X5"},
33488	{5, riscv.REG_X6, 2, "X6"},
33489	{6, riscv.REG_X7, 3, "X7"},
33490	{7, riscv.REG_X8, 4, "X8"},
33491	{8, riscv.REG_X9, 5, "X9"},
33492	{9, riscv.REG_X10, 6, "X10"},
33493	{10, riscv.REG_X11, 7, "X11"},
33494	{11, riscv.REG_X12, 8, "X12"},
33495	{12, riscv.REG_X13, 9, "X13"},
33496	{13, riscv.REG_X14, 10, "X14"},
33497	{14, riscv.REG_X15, 11, "X15"},
33498	{15, riscv.REG_X16, 12, "X16"},
33499	{16, riscv.REG_X17, 13, "X17"},
33500	{17, riscv.REG_X18, 14, "X18"},
33501	{18, riscv.REG_X19, 15, "X19"},
33502	{19, riscv.REG_X20, 16, "X20"},
33503	{20, riscv.REG_X21, 17, "X21"},
33504	{21, riscv.REG_X22, 18, "X22"},
33505	{22, riscv.REG_X23, 19, "X23"},
33506	{23, riscv.REG_X24, 20, "X24"},
33507	{24, riscv.REG_X25, 21, "X25"},
33508	{25, riscv.REG_X26, 22, "X26"},
33509	{26, riscv.REG_X27, 23, "X27"},
33510	{27, riscv.REG_X28, 24, "X28"},
33511	{28, riscv.REG_X29, 25, "X29"},
33512	{29, riscv.REG_X30, 26, "X30"},
33513	{30, riscv.REG_X31, -1, "X31"},
33514	{31, riscv.REG_F0, -1, "F0"},
33515	{32, riscv.REG_F1, -1, "F1"},
33516	{33, riscv.REG_F2, -1, "F2"},
33517	{34, riscv.REG_F3, -1, "F3"},
33518	{35, riscv.REG_F4, -1, "F4"},
33519	{36, riscv.REG_F5, -1, "F5"},
33520	{37, riscv.REG_F6, -1, "F6"},
33521	{38, riscv.REG_F7, -1, "F7"},
33522	{39, riscv.REG_F8, -1, "F8"},
33523	{40, riscv.REG_F9, -1, "F9"},
33524	{41, riscv.REG_F10, -1, "F10"},
33525	{42, riscv.REG_F11, -1, "F11"},
33526	{43, riscv.REG_F12, -1, "F12"},
33527	{44, riscv.REG_F13, -1, "F13"},
33528	{45, riscv.REG_F14, -1, "F14"},
33529	{46, riscv.REG_F15, -1, "F15"},
33530	{47, riscv.REG_F16, -1, "F16"},
33531	{48, riscv.REG_F17, -1, "F17"},
33532	{49, riscv.REG_F18, -1, "F18"},
33533	{50, riscv.REG_F19, -1, "F19"},
33534	{51, riscv.REG_F20, -1, "F20"},
33535	{52, riscv.REG_F21, -1, "F21"},
33536	{53, riscv.REG_F22, -1, "F22"},
33537	{54, riscv.REG_F23, -1, "F23"},
33538	{55, riscv.REG_F24, -1, "F24"},
33539	{56, riscv.REG_F25, -1, "F25"},
33540	{57, riscv.REG_F26, -1, "F26"},
33541	{58, riscv.REG_F27, -1, "F27"},
33542	{59, riscv.REG_F28, -1, "F28"},
33543	{60, riscv.REG_F29, -1, "F29"},
33544	{61, riscv.REG_F30, -1, "F30"},
33545	{62, riscv.REG_F31, -1, "F31"},
33546	{63, 0, -1, "SB"},
33547}
33548var gpRegMaskRISCV64 = regMask(1073741812)
33549var fpRegMaskRISCV64 = regMask(9223372034707292160)
33550var specialRegMaskRISCV64 = regMask(0)
33551var framepointerRegRISCV64 = int8(-1)
33552var linkRegRISCV64 = int8(0)
33553var registersS390X = [...]Register{
33554	{0, s390x.REG_R0, 0, "R0"},
33555	{1, s390x.REG_R1, 1, "R1"},
33556	{2, s390x.REG_R2, 2, "R2"},
33557	{3, s390x.REG_R3, 3, "R3"},
33558	{4, s390x.REG_R4, 4, "R4"},
33559	{5, s390x.REG_R5, 5, "R5"},
33560	{6, s390x.REG_R6, 6, "R6"},
33561	{7, s390x.REG_R7, 7, "R7"},
33562	{8, s390x.REG_R8, 8, "R8"},
33563	{9, s390x.REG_R9, 9, "R9"},
33564	{10, s390x.REG_R10, -1, "R10"},
33565	{11, s390x.REG_R11, 10, "R11"},
33566	{12, s390x.REG_R12, 11, "R12"},
33567	{13, s390x.REGG, -1, "g"},
33568	{14, s390x.REG_R14, 12, "R14"},
33569	{15, s390x.REGSP, -1, "SP"},
33570	{16, s390x.REG_F0, -1, "F0"},
33571	{17, s390x.REG_F1, -1, "F1"},
33572	{18, s390x.REG_F2, -1, "F2"},
33573	{19, s390x.REG_F3, -1, "F3"},
33574	{20, s390x.REG_F4, -1, "F4"},
33575	{21, s390x.REG_F5, -1, "F5"},
33576	{22, s390x.REG_F6, -1, "F6"},
33577	{23, s390x.REG_F7, -1, "F7"},
33578	{24, s390x.REG_F8, -1, "F8"},
33579	{25, s390x.REG_F9, -1, "F9"},
33580	{26, s390x.REG_F10, -1, "F10"},
33581	{27, s390x.REG_F11, -1, "F11"},
33582	{28, s390x.REG_F12, -1, "F12"},
33583	{29, s390x.REG_F13, -1, "F13"},
33584	{30, s390x.REG_F14, -1, "F14"},
33585	{31, s390x.REG_F15, -1, "F15"},
33586	{32, 0, -1, "SB"},
33587}
33588var gpRegMaskS390X = regMask(23551)
33589var fpRegMaskS390X = regMask(4294901760)
33590var specialRegMaskS390X = regMask(0)
33591var framepointerRegS390X = int8(-1)
33592var linkRegS390X = int8(14)
33593var registersWasm = [...]Register{
33594	{0, wasm.REG_R0, 0, "R0"},
33595	{1, wasm.REG_R1, 1, "R1"},
33596	{2, wasm.REG_R2, 2, "R2"},
33597	{3, wasm.REG_R3, 3, "R3"},
33598	{4, wasm.REG_R4, 4, "R4"},
33599	{5, wasm.REG_R5, 5, "R5"},
33600	{6, wasm.REG_R6, 6, "R6"},
33601	{7, wasm.REG_R7, 7, "R7"},
33602	{8, wasm.REG_R8, 8, "R8"},
33603	{9, wasm.REG_R9, 9, "R9"},
33604	{10, wasm.REG_R10, 10, "R10"},
33605	{11, wasm.REG_R11, 11, "R11"},
33606	{12, wasm.REG_R12, 12, "R12"},
33607	{13, wasm.REG_R13, 13, "R13"},
33608	{14, wasm.REG_R14, 14, "R14"},
33609	{15, wasm.REG_R15, 15, "R15"},
33610	{16, wasm.REG_F0, -1, "F0"},
33611	{17, wasm.REG_F1, -1, "F1"},
33612	{18, wasm.REG_F2, -1, "F2"},
33613	{19, wasm.REG_F3, -1, "F3"},
33614	{20, wasm.REG_F4, -1, "F4"},
33615	{21, wasm.REG_F5, -1, "F5"},
33616	{22, wasm.REG_F6, -1, "F6"},
33617	{23, wasm.REG_F7, -1, "F7"},
33618	{24, wasm.REG_F8, -1, "F8"},
33619	{25, wasm.REG_F9, -1, "F9"},
33620	{26, wasm.REG_F10, -1, "F10"},
33621	{27, wasm.REG_F11, -1, "F11"},
33622	{28, wasm.REG_F12, -1, "F12"},
33623	{29, wasm.REG_F13, -1, "F13"},
33624	{30, wasm.REG_F14, -1, "F14"},
33625	{31, wasm.REG_F15, -1, "F15"},
33626	{32, wasm.REG_F16, -1, "F16"},
33627	{33, wasm.REG_F17, -1, "F17"},
33628	{34, wasm.REG_F18, -1, "F18"},
33629	{35, wasm.REG_F19, -1, "F19"},
33630	{36, wasm.REG_F20, -1, "F20"},
33631	{37, wasm.REG_F21, -1, "F21"},
33632	{38, wasm.REG_F22, -1, "F22"},
33633	{39, wasm.REG_F23, -1, "F23"},
33634	{40, wasm.REG_F24, -1, "F24"},
33635	{41, wasm.REG_F25, -1, "F25"},
33636	{42, wasm.REG_F26, -1, "F26"},
33637	{43, wasm.REG_F27, -1, "F27"},
33638	{44, wasm.REG_F28, -1, "F28"},
33639	{45, wasm.REG_F29, -1, "F29"},
33640	{46, wasm.REG_F30, -1, "F30"},
33641	{47, wasm.REG_F31, -1, "F31"},
33642	{48, wasm.REGSP, -1, "SP"},
33643	{49, wasm.REGG, -1, "g"},
33644	{50, 0, -1, "SB"},
33645}
33646var gpRegMaskWasm = regMask(65535)
33647var fpRegMaskWasm = regMask(281474976645120)
33648var fp32RegMaskWasm = regMask(4294901760)
33649var fp64RegMaskWasm = regMask(281470681743360)
33650var specialRegMaskWasm = regMask(0)
33651var framepointerRegWasm = int8(-1)
33652var linkRegWasm = int8(-1)
33653