1 /*
2 * This file is part of the MicroPython project, http://micropython.org/
3 *
4 * The MIT License (MIT)
5 *
6 * Copyright (c) 2020 Philipp Ebensberger
7 * Copyright (c) 2021 Robert Hammelrath
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27 #include <stdint.h>
28
29 #include "fsl_gpio.h"
30 #include "fsl_iomuxc.h"
31
32 #include "py/runtime.h"
33 #include "py/mphal.h"
34 #include "shared/runtime/mpirq.h"
35 #include "extmod/virtpin.h"
36 #include "pin.h"
37
38 // Local functions
39 STATIC mp_obj_t machine_pin_obj_init_helper(const machine_pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args);
40
41 // Class Methods
42 STATIC void machine_pin_obj_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind);
43 STATIC mp_obj_t machine_pin_obj_call(mp_obj_t self_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args);
44 mp_obj_t mp_pin_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args);
45
46 // Instance Methods
47 STATIC mp_obj_t machine_pin_off(mp_obj_t self_in);
48 STATIC mp_obj_t machine_pin_on(mp_obj_t self_in);
49 STATIC mp_obj_t machine_pin_value(size_t n_args, const mp_obj_t *args);
50 STATIC mp_obj_t machine_pin_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args);
51
52 // Local data
53 enum {
54 PIN_INIT_ARG_MODE = 0,
55 PIN_INIT_ARG_PULL,
56 PIN_INIT_ARG_VALUE,
57 PIN_INIT_ARG_DRIVE,
58 };
59
60 // Pin mapping dictionaries
61 const mp_obj_type_t machine_pin_cpu_pins_obj_type = {
62 { &mp_type_type },
63 .name = MP_QSTR_cpu,
64 .locals_dict = (mp_obj_t)&machine_pin_cpu_pins_locals_dict,
65 };
66
67 const mp_obj_type_t machine_pin_board_pins_obj_type = {
68 { &mp_type_type },
69 .name = MP_QSTR_board,
70 .locals_dict = (mp_obj_t)&machine_pin_board_pins_locals_dict,
71 };
72
73 STATIC const mp_irq_methods_t machine_pin_irq_methods;
74
75 static GPIO_Type *gpiobases[] = GPIO_BASE_PTRS;
76 STATIC const uint16_t GPIO_combined_low_irqs[] = GPIO_COMBINED_LOW_IRQS;
77 STATIC const uint16_t GPIO_combined_high_irqs[] = GPIO_COMBINED_HIGH_IRQS;
78 STATIC const uint16_t IRQ_mapping[] = {kGPIO_NoIntmode, kGPIO_IntRisingEdge, kGPIO_IntFallingEdge, kGPIO_IntRisingOrFallingEdge};
79 #define GET_PIN_IRQ_INDEX(gpio_nr, pin) ((gpio_nr - 1) * 32 + pin)
80
GPIO_get_instance(GPIO_Type * gpio)81 int GPIO_get_instance(GPIO_Type *gpio) {
82 int gpio_nr;
83 for (gpio_nr = 0; gpio_nr < ARRAY_SIZE(gpiobases); gpio_nr++) {
84 if (gpio == gpiobases[gpio_nr]) {
85 return gpio_nr;
86 }
87 }
88 return 0;
89 }
90
call_handler(GPIO_Type * gpio,int gpio_nr,int pin)91 void call_handler(GPIO_Type *gpio, int gpio_nr, int pin) {
92 uint32_t mask = 1 << pin;
93 uint32_t isr = gpio->ISR & gpio->IMR;
94 for (int i = 0; i < 16; i++, pin++, mask <<= 1) {
95 // Did the ISR fire? Consider only the bits that are enabled.
96 if (isr & mask) {
97 gpio->ISR = mask; // clear the ISR flag
98 int index = GET_PIN_IRQ_INDEX(gpio_nr, pin);
99 machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[index]);
100 if (irq != NULL) {
101 irq->flags = irq->trigger;
102 mp_irq_handler(&irq->base);
103 }
104 }
105 }
106 }
107
108 // 10 GPIO IRQ handlers, each covering 16 bits.
109
GPIO1_Combined_0_15_IRQHandler(void)110 void GPIO1_Combined_0_15_IRQHandler(void) {
111 call_handler(gpiobases[1], 1, 0);
112 }
113
GPIO1_Combined_16_31_IRQHandler(void)114 void GPIO1_Combined_16_31_IRQHandler(void) {
115 call_handler(gpiobases[1], 1, 16);
116 }
117
GPIO2_Combined_0_15_IRQHandler(void)118 void GPIO2_Combined_0_15_IRQHandler(void) {
119 call_handler(gpiobases[2], 2, 0);
120 }
121
GPIO2_Combined_16_31_IRQHandler(void)122 void GPIO2_Combined_16_31_IRQHandler(void) {
123 call_handler(gpiobases[2], 2, 16);
124 }
125
GPIO3_Combined_0_15_IRQHandler(void)126 void GPIO3_Combined_0_15_IRQHandler(void) {
127 call_handler(gpiobases[3], 3, 0);
128 }
129
GPIO3_Combined_16_31_IRQHandler(void)130 void GPIO3_Combined_16_31_IRQHandler(void) {
131 call_handler(gpiobases[3], 3, 16);
132 }
133
GPIO4_Combined_0_15_IRQHandler(void)134 void GPIO4_Combined_0_15_IRQHandler(void) {
135 call_handler(gpiobases[4], 4, 0);
136 }
137
GPIO4_Combined_16_31_IRQHandler(void)138 void GPIO4_Combined_16_31_IRQHandler(void) {
139 call_handler(gpiobases[4], 4, 16);
140 }
141
GPIO5_Combined_0_15_IRQHandler(void)142 void GPIO5_Combined_0_15_IRQHandler(void) {
143 call_handler(gpiobases[5], 5, 0);
144 }
145
GPIO5_Combined_16_31_IRQHandler(void)146 void GPIO5_Combined_16_31_IRQHandler(void) {
147 call_handler(gpiobases[5], 5, 16);
148 }
149
150 // Deinit all pin IRQ handlers.
machine_pin_irq_deinit(void)151 void machine_pin_irq_deinit(void) {
152 for (int i = 0; i < ARRAY_SIZE(MP_STATE_PORT(machine_pin_irq_objects)); ++i) {
153 machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[i]);
154 if (irq != NULL) {
155 machine_pin_obj_t *self = MP_OBJ_TO_PTR(irq->base.parent);
156 GPIO_PortDisableInterrupts(self->gpio, 1U << self->pin);
157 MP_STATE_PORT(machine_pin_irq_objects[i]) = NULL;
158 }
159 }
160 }
161
162 // Simplified mode setting used by the extmod modules
machine_pin_set_mode(const machine_pin_obj_t * self,uint8_t mode)163 void machine_pin_set_mode(const machine_pin_obj_t *self, uint8_t mode) {
164 gpio_pin_config_t pin_config = {kGPIO_DigitalInput, 1, kGPIO_NoIntmode};
165
166 pin_config.direction = (mode == PIN_MODE_IN ? kGPIO_DigitalInput : kGPIO_DigitalOutput);
167 GPIO_PinInit(self->gpio, self->pin, &pin_config);
168 if (mode == PIN_MODE_OPEN_DRAIN) {
169 uint32_t pad_config = *(uint32_t *)self->configRegister;
170 pad_config |= IOMUXC_SW_PAD_CTL_PAD_ODE(0b1) | IOMUXC_SW_PAD_CTL_PAD_DSE(0b110);
171 IOMUXC_SetPinMux(self->muxRegister, PIN_AF_MODE_ALT5, 0, 0, self->configRegister, 1U); // Software Input On Field: Input Path is determined by functionality
172 IOMUXC_SetPinConfig(self->muxRegister, PIN_AF_MODE_ALT5, 0, 0, self->configRegister, pad_config);
173 }
174 }
175
machine_pin_obj_call(mp_obj_t self_in,mp_uint_t n_args,mp_uint_t n_kw,const mp_obj_t * args)176 STATIC mp_obj_t machine_pin_obj_call(mp_obj_t self_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) {
177 mp_arg_check_num(n_args, n_kw, 0, 1, false);
178 machine_pin_obj_t *self = self_in;
179
180 if (n_args == 0) {
181 return MP_OBJ_NEW_SMALL_INT(mp_hal_pin_read(self));
182 } else {
183 mp_hal_pin_write(self, mp_obj_is_true(args[0]));
184 return mp_const_none;
185 }
186 }
187
machine_pin_obj_init_helper(const machine_pin_obj_t * self,size_t n_args,const mp_obj_t * pos_args,mp_map_t * kw_args)188 STATIC mp_obj_t machine_pin_obj_init_helper(const machine_pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
189 static const mp_arg_t allowed_args[] = {
190 [PIN_INIT_ARG_MODE] { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT },
191 [PIN_INIT_ARG_PULL] { MP_QSTR_pull, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE}},
192 [PIN_INIT_ARG_VALUE] { MP_QSTR_value, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL}},
193 [PIN_INIT_ARG_DRIVE] { MP_QSTR_drive, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = PIN_DRIVE_POWER_3}},
194 // TODO: Implement additional arguments
195 /*
196 { MP_QSTR_af, MP_ARG_INT, {.u_int = -1}}, // legacy
197 { MP_QSTR_alt, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1}},*/
198 };
199
200 // Parse args
201 mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
202 mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
203
204 // Get io mode
205 uint mode = args[PIN_INIT_ARG_MODE].u_int;
206 if (!IS_GPIO_MODE(mode)) {
207 mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid pin mode: %d"), mode);
208 }
209
210 // Handle configuration for GPIO
211 if ((mode == PIN_MODE_IN) || (mode == PIN_MODE_OUT) || (mode == PIN_MODE_OPEN_DRAIN)) {
212 gpio_pin_config_t pin_config;
213 const machine_pin_af_obj_t *af_obj;
214 uint32_t pad_config = 0UL;
215 uint8_t pull = PIN_PULL_DISABLED;
216
217 // Generate pin configuration
218 if ((args[PIN_INIT_ARG_VALUE].u_obj != MP_OBJ_NULL) && (mp_obj_is_true(args[PIN_INIT_ARG_VALUE].u_obj))) {
219 pin_config.outputLogic = 1U;
220 } else {
221 pin_config.outputLogic = 0U;
222 }
223 pin_config.direction = mode == PIN_MODE_IN ? kGPIO_DigitalInput : kGPIO_DigitalOutput;
224 pin_config.interruptMode = kGPIO_NoIntmode;
225
226 af_obj = pin_find_af(self, PIN_AF_MODE_ALT5); // GPIO is always ALT5
227 if (af_obj == NULL) {
228 mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("requested AF %d not available for pin %d"), PIN_AF_MODE_ALT5, mode);
229 }
230
231 // Generate pad configuration
232 if (args[PIN_INIT_ARG_PULL].u_obj != mp_const_none) {
233 pull = (uint8_t)mp_obj_get_int(args[PIN_INIT_ARG_PULL].u_obj);
234 }
235
236 pad_config |= IOMUXC_SW_PAD_CTL_PAD_SRE(0U); // Slow Slew Rate
237 pad_config |= IOMUXC_SW_PAD_CTL_PAD_SPEED(0b01); // medium(100MHz)
238
239 if (mode == PIN_MODE_OPEN_DRAIN) {
240 pad_config |= IOMUXC_SW_PAD_CTL_PAD_ODE(0b1); // Open Drain Enabled
241 } else {
242 pad_config |= IOMUXC_SW_PAD_CTL_PAD_ODE(0b0); // Open Drain Disabled
243 }
244
245 if (pull == PIN_PULL_DISABLED) {
246 pad_config |= IOMUXC_SW_PAD_CTL_PAD_PKE(0); // Pull/Keeper Disabled
247 } else if (pull == PIN_PULL_HOLD) {
248 pad_config |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | // Pull/Keeper Enabled
249 IOMUXC_SW_PAD_CTL_PAD_PUE(0); // Keeper selected
250 } else {
251 pad_config |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | // Pull/Keeper Enabled
252 IOMUXC_SW_PAD_CTL_PAD_PUE(1) | // Pull selected
253 IOMUXC_SW_PAD_CTL_PAD_PUS(pull);
254 }
255
256 if (mode == PIN_MODE_IN) {
257 pad_config |= IOMUXC_SW_PAD_CTL_PAD_DSE(0b000) | // output driver disabled
258 IOMUXC_SW_PAD_CTL_PAD_HYS(1U); // Hysteresis enabled
259 } else {
260 uint drive = args[PIN_INIT_ARG_DRIVE].u_int;
261 if (!IS_GPIO_DRIVE(drive)) {
262 mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid drive strength: %d"), drive);
263 }
264
265 pad_config |= IOMUXC_SW_PAD_CTL_PAD_DSE(drive) |
266 IOMUXC_SW_PAD_CTL_PAD_HYS(0U); // Hysteresis disabled
267 }
268
269 // Configure PAD as GPIO
270 IOMUXC_SetPinMux(self->muxRegister, af_obj->af_mode, 0, 0, self->configRegister, 1U); // Software Input On Field: Input Path is determined by functionality
271 IOMUXC_SetPinConfig(self->muxRegister, af_obj->af_mode, 0, 0, self->configRegister, pad_config);
272 GPIO_PinInit(self->gpio, self->pin, &pin_config);
273 }
274
275 return mp_const_none;
276 }
277
machine_pin_obj_print(const mp_print_t * print,mp_obj_t o,mp_print_kind_t kind)278 STATIC void machine_pin_obj_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) {
279 (void)kind;
280 const machine_pin_obj_t *self = MP_OBJ_TO_PTR(o);
281 mp_printf(print, "Pin(%s)", qstr_str(self->name));
282 }
283
284 // pin(id, mode, pull, ...)
mp_pin_make_new(const mp_obj_type_t * type,size_t n_args,size_t n_kw,const mp_obj_t * args)285 mp_obj_t mp_pin_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
286 mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true);
287
288 const machine_pin_obj_t *pin = pin_find(args[0]);
289
290 if (n_args > 1 || n_kw > 0) {
291 // pin mode given, so configure this GPIO
292 mp_map_t kw_args;
293 mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
294 machine_pin_obj_init_helper(pin, n_args - 1, args + 1, &kw_args);
295 }
296
297 return (mp_obj_t)pin;
298 }
299
300 // pin.off()
machine_pin_off(mp_obj_t self_in)301 STATIC mp_obj_t machine_pin_off(mp_obj_t self_in) {
302 machine_pin_obj_t *self = self_in;
303 mp_hal_pin_low(self);
304 return mp_const_none;
305 }
306 STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_off_obj, machine_pin_off);
307
308 // pin.on()
machine_pin_on(mp_obj_t self_in)309 STATIC mp_obj_t machine_pin_on(mp_obj_t self_in) {
310 machine_pin_obj_t *self = self_in;
311 mp_hal_pin_high(self);
312 return mp_const_none;
313 }
314 STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_on_obj, machine_pin_on);
315
316 // pin.value([value])
machine_pin_value(size_t n_args,const mp_obj_t * args)317 STATIC mp_obj_t machine_pin_value(size_t n_args, const mp_obj_t *args) {
318 return machine_pin_obj_call(args[0], (n_args - 1), 0, args + 1);
319 }
320 STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_pin_value_obj, 1, 2, machine_pin_value);
321
322 // pin.init(mode, pull, [kwargs])
machine_pin_init(size_t n_args,const mp_obj_t * args,mp_map_t * kw_args)323 STATIC mp_obj_t machine_pin_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
324 return machine_pin_obj_init_helper(args[0], n_args - 1, args + 1, kw_args);
325 }
326 MP_DEFINE_CONST_FUN_OBJ_KW(machine_pin_init_obj, 1, machine_pin_init);
327
328 // pin.irq(handler=None, trigger=IRQ_FALLING|IRQ_RISING, hard=False)
machine_pin_irq(size_t n_args,const mp_obj_t * pos_args,mp_map_t * kw_args)329 STATIC mp_obj_t machine_pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
330 enum { ARG_handler, ARG_trigger, ARG_hard };
331 static const mp_arg_t allowed_args[] = {
332 { MP_QSTR_handler, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
333 { MP_QSTR_trigger, MP_ARG_INT, {.u_int = 3} },
334 { MP_QSTR_hard, MP_ARG_BOOL, {.u_bool = false} },
335 };
336 machine_pin_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
337 mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
338 mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
339
340 // Get the IRQ object.
341 uint32_t gpio_nr = GPIO_get_instance(self->gpio);
342 uint32_t index = GET_PIN_IRQ_INDEX(gpio_nr, self->pin);
343 if (index >= ARRAY_SIZE(MP_STATE_PORT(machine_pin_irq_objects))) {
344 mp_raise_ValueError(MP_ERROR_TEXT("IRQ not supported on given Pin"));
345 }
346 machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[index]);
347
348 // Allocate the IRQ object if it doesn't already exist.
349 if (irq == NULL) {
350 irq = m_new_obj(machine_pin_irq_obj_t);
351 irq->base.base.type = &mp_irq_type;
352 irq->base.methods = (mp_irq_methods_t *)&machine_pin_irq_methods;
353 irq->base.parent = MP_OBJ_FROM_PTR(self);
354 irq->base.handler = mp_const_none;
355 irq->base.ishard = false;
356 MP_STATE_PORT(machine_pin_irq_objects[index]) = irq;
357 }
358
359 if (n_args > 1 || kw_args->used != 0) {
360 // Configure IRQ.
361 uint32_t irq_num = self->pin < 16 ? GPIO_combined_low_irqs[gpio_nr] : GPIO_combined_high_irqs[gpio_nr];
362
363 // Disable all IRQs from the affected source while data is updated.
364 DisableIRQ(irq_num);
365 GPIO_PortDisableInterrupts(self->gpio, 1U << self->pin);
366
367 // Update IRQ data.
368 irq->base.handler = args[ARG_handler].u_obj;
369 irq->base.ishard = args[ARG_hard].u_bool;
370 irq->flags = 0;
371 if (args[ARG_trigger].u_int >= ARRAY_SIZE(IRQ_mapping)) {
372 mp_raise_ValueError(MP_ERROR_TEXT("IRQ mode not supported"));
373 }
374 irq->trigger = IRQ_mapping[args[ARG_trigger].u_int];
375
376 // Enable IRQ if a handler is given.
377 if (args[ARG_handler].u_obj != mp_const_none) {
378 // Set the pin mode
379 GPIO_PinSetInterruptConfig(self->gpio, self->pin, irq->trigger);
380 // Enable the specific Pin interrupt
381 GPIO_PortEnableInterrupts(self->gpio, 1U << self->pin);
382 }
383 // Enable LEVEL1 interrupt again
384 EnableIRQ(irq_num);
385 }
386
387 return MP_OBJ_FROM_PTR(irq);
388 }
389 STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_pin_irq_obj, 1, machine_pin_irq);
390
391 STATIC const mp_rom_map_elem_t machine_pin_locals_dict_table[] = {
392 // instance methods
393 { MP_ROM_QSTR(MP_QSTR_off), MP_ROM_PTR(&machine_pin_off_obj) },
394 { MP_ROM_QSTR(MP_QSTR_on), MP_ROM_PTR(&machine_pin_on_obj) },
395 { MP_ROM_QSTR(MP_QSTR_low), MP_ROM_PTR(&machine_pin_off_obj) },
396 { MP_ROM_QSTR(MP_QSTR_high), MP_ROM_PTR(&machine_pin_on_obj) },
397 { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&machine_pin_value_obj) },
398 { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_pin_init_obj) },
399 { MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&machine_pin_irq_obj) },
400 // class attributes
401 { MP_ROM_QSTR(MP_QSTR_board), MP_ROM_PTR(&machine_pin_board_pins_obj_type) },
402 { MP_ROM_QSTR(MP_QSTR_cpu), MP_ROM_PTR(&machine_pin_cpu_pins_obj_type) },
403 // class constants
404 { MP_ROM_QSTR(MP_QSTR_IN), MP_ROM_INT(PIN_MODE_IN) },
405 { MP_ROM_QSTR(MP_QSTR_OUT), MP_ROM_INT(PIN_MODE_OUT) },
406 { MP_ROM_QSTR(MP_QSTR_OPEN_DRAIN), MP_ROM_INT(PIN_MODE_OPEN_DRAIN) },
407
408 { MP_ROM_QSTR(MP_QSTR_PULL_UP), MP_ROM_INT(PIN_PULL_UP_100K) },
409 { MP_ROM_QSTR(MP_QSTR_PULL_UP_47K), MP_ROM_INT(PIN_PULL_UP_47K) },
410 { MP_ROM_QSTR(MP_QSTR_PULL_UP_22K), MP_ROM_INT(PIN_PULL_UP_22K) },
411 { MP_ROM_QSTR(MP_QSTR_PULL_DOWN), MP_ROM_INT(PIN_PULL_DOWN_100K) },
412 { MP_ROM_QSTR(MP_QSTR_PULL_HOLD), MP_ROM_INT(PIN_PULL_HOLD) },
413
414 { MP_ROM_QSTR(MP_QSTR_DRIVER_OFF), MP_ROM_INT(PIN_DRIVE_OFF) },
415 { MP_ROM_QSTR(MP_QSTR_POWER_0), MP_ROM_INT(PIN_DRIVE_POWER_0) }, // R0 (150 Ohm @3.3V / 260 Ohm @ 1.8V)
416 { MP_ROM_QSTR(MP_QSTR_POWER_1), MP_ROM_INT(PIN_DRIVE_POWER_1) }, // R0/2
417 { MP_ROM_QSTR(MP_QSTR_POWER_2), MP_ROM_INT(PIN_DRIVE_POWER_2) }, // R0/3
418 { MP_ROM_QSTR(MP_QSTR_POWER_3), MP_ROM_INT(PIN_DRIVE_POWER_3) }, // R0/4
419 { MP_ROM_QSTR(MP_QSTR_POWER_4), MP_ROM_INT(PIN_DRIVE_POWER_4) }, // R0/5
420 { MP_ROM_QSTR(MP_QSTR_POWER_5), MP_ROM_INT(PIN_DRIVE_POWER_5) }, // R0/6
421 { MP_ROM_QSTR(MP_QSTR_POWER_6), MP_ROM_INT(PIN_DRIVE_POWER_6) }, // R0/7
422
423 { MP_ROM_QSTR(MP_QSTR_IRQ_RISING), MP_ROM_INT(1) },
424 { MP_ROM_QSTR(MP_QSTR_IRQ_FALLING), MP_ROM_INT(2) },
425
426 };
427 STATIC MP_DEFINE_CONST_DICT(machine_pin_locals_dict, machine_pin_locals_dict_table);
428
429
machine_pin_ioctl(mp_obj_t self_in,mp_uint_t request,uintptr_t arg,int * errcode)430 STATIC mp_uint_t machine_pin_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) {
431 (void)errcode;
432 machine_pin_obj_t *self = self_in;
433
434 switch (request) {
435 case MP_PIN_READ: {
436 return mp_hal_pin_read(self);
437 }
438 case MP_PIN_WRITE: {
439 mp_hal_pin_write(self, arg);
440 return 0;
441 }
442 }
443 return -1;
444 }
445
446 STATIC const mp_pin_p_t machine_pin_obj_protocol = {
447 .ioctl = machine_pin_ioctl,
448 };
449
450 const mp_obj_type_t machine_pin_type = {
451 {&mp_type_type},
452 .name = MP_QSTR_Pin,
453 .print = machine_pin_obj_print,
454 .call = machine_pin_obj_call,
455 .make_new = mp_pin_make_new,
456 .protocol = &machine_pin_obj_protocol,
457 .locals_dict = (mp_obj_dict_t *)&machine_pin_locals_dict,
458 };
459
460 // FIXME: Create actual pin_af type!!!
461 const mp_obj_type_t machine_pin_af_type = {
462 {&mp_type_type},
463 .name = MP_QSTR_PinAF,
464 .print = machine_pin_obj_print,
465 .make_new = mp_pin_make_new,
466 .locals_dict = (mp_obj_dict_t *)&machine_pin_locals_dict,
467 };
468
machine_pin_irq_trigger(mp_obj_t self_in,mp_uint_t new_trigger)469 STATIC mp_uint_t machine_pin_irq_trigger(mp_obj_t self_in, mp_uint_t new_trigger) {
470 machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in);
471 uint32_t gpio_nr = GPIO_get_instance(self->gpio);
472 machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[GET_PIN_IRQ_INDEX(gpio_nr, self->pin)]);
473 uint32_t irq_num = self->pin < 16 ? GPIO_combined_low_irqs[gpio_nr] : GPIO_combined_high_irqs[gpio_nr];
474 DisableIRQ(irq_num);
475 irq->flags = 0;
476 irq->trigger = new_trigger;
477 // Configure the interrupt.
478 GPIO_PinSetInterruptConfig(self->gpio, self->pin, irq->trigger);
479 // Enable LEVEL1 interrupt.
480 EnableIRQ(irq_num);
481 // Enable the specific pin interrupt.
482 GPIO_PortEnableInterrupts(self->gpio, 1U << self->pin);
483 return 0;
484 }
485
machine_pin_irq_info(mp_obj_t self_in,mp_uint_t info_type)486 STATIC mp_uint_t machine_pin_irq_info(mp_obj_t self_in, mp_uint_t info_type) {
487 machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in);
488 uint32_t gpio_nr = GPIO_get_instance(self->gpio);
489 machine_pin_irq_obj_t *irq = MP_STATE_PORT(machine_pin_irq_objects[GET_PIN_IRQ_INDEX(gpio_nr, self->pin)]);
490 if (info_type == MP_IRQ_INFO_FLAGS) {
491 return irq->flags;
492 } else if (info_type == MP_IRQ_INFO_TRIGGERS) {
493 return irq->trigger;
494 }
495 return 0;
496 }
497
498 STATIC const mp_irq_methods_t machine_pin_irq_methods = {
499 .trigger = machine_pin_irq_trigger,
500 .info = machine_pin_irq_info,
501 };
502