1 /*
2 * This file is part of the MicroPython project, http://micropython.org/
3 *
4 * The MIT License (MIT)
5 *
6 * Copyright (c) 2014 Fabian Vogt
7 * Copyright (c) 2013, 2014 Damien P. George
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27
28 #include <stdio.h>
29 #include <assert.h>
30 #include <string.h>
31
32 #include "py/mpconfig.h"
33
34 // wrapper around everything in this file
35 #if MICROPY_EMIT_ARM
36
37 #include "py/asmarm.h"
38
39 #define SIGNED_FIT24(x) (((x) & 0xff800000) == 0) || (((x) & 0xff000000) == 0xff000000)
40
41 // Insert word into instruction flow
emit(asm_arm_t * as,uint op)42 STATIC void emit(asm_arm_t *as, uint op) {
43 uint8_t *c = mp_asm_base_get_cur_to_write_bytes(&as->base, 4);
44 if (c != NULL) {
45 *(uint32_t *)c = op;
46 }
47 }
48
49 // Insert word into instruction flow, add "ALWAYS" condition code
emit_al(asm_arm_t * as,uint op)50 STATIC void emit_al(asm_arm_t *as, uint op) {
51 emit(as, op | ASM_ARM_CC_AL);
52 }
53
54 // Basic instructions without condition code
asm_arm_op_push(uint reglist)55 STATIC uint asm_arm_op_push(uint reglist) {
56 // stmfd sp!, {reglist}
57 return 0x92d0000 | (reglist & 0xFFFF);
58 }
59
asm_arm_op_pop(uint reglist)60 STATIC uint asm_arm_op_pop(uint reglist) {
61 // ldmfd sp!, {reglist}
62 return 0x8bd0000 | (reglist & 0xFFFF);
63 }
64
asm_arm_op_mov_reg(uint rd,uint rn)65 STATIC uint asm_arm_op_mov_reg(uint rd, uint rn) {
66 // mov rd, rn
67 return 0x1a00000 | (rd << 12) | rn;
68 }
69
asm_arm_op_mov_imm(uint rd,uint imm)70 STATIC uint asm_arm_op_mov_imm(uint rd, uint imm) {
71 // mov rd, #imm
72 return 0x3a00000 | (rd << 12) | imm;
73 }
74
asm_arm_op_mvn_imm(uint rd,uint imm)75 STATIC uint asm_arm_op_mvn_imm(uint rd, uint imm) {
76 // mvn rd, #imm
77 return 0x3e00000 | (rd << 12) | imm;
78 }
79
asm_arm_op_add_imm(uint rd,uint rn,uint imm)80 STATIC uint asm_arm_op_add_imm(uint rd, uint rn, uint imm) {
81 // add rd, rn, #imm
82 return 0x2800000 | (rn << 16) | (rd << 12) | (imm & 0xFF);
83 }
84
asm_arm_op_add_reg(uint rd,uint rn,uint rm)85 STATIC uint asm_arm_op_add_reg(uint rd, uint rn, uint rm) {
86 // add rd, rn, rm
87 return 0x0800000 | (rn << 16) | (rd << 12) | rm;
88 }
89
asm_arm_op_sub_imm(uint rd,uint rn,uint imm)90 STATIC uint asm_arm_op_sub_imm(uint rd, uint rn, uint imm) {
91 // sub rd, rn, #imm
92 return 0x2400000 | (rn << 16) | (rd << 12) | (imm & 0xFF);
93 }
94
asm_arm_op_sub_reg(uint rd,uint rn,uint rm)95 STATIC uint asm_arm_op_sub_reg(uint rd, uint rn, uint rm) {
96 // sub rd, rn, rm
97 return 0x0400000 | (rn << 16) | (rd << 12) | rm;
98 }
99
asm_arm_op_mul_reg(uint rd,uint rm,uint rs)100 STATIC uint asm_arm_op_mul_reg(uint rd, uint rm, uint rs) {
101 // mul rd, rm, rs
102 assert(rd != rm);
103 return 0x0000090 | (rd << 16) | (rs << 8) | rm;
104 }
105
asm_arm_op_and_reg(uint rd,uint rn,uint rm)106 STATIC uint asm_arm_op_and_reg(uint rd, uint rn, uint rm) {
107 // and rd, rn, rm
108 return 0x0000000 | (rn << 16) | (rd << 12) | rm;
109 }
110
asm_arm_op_eor_reg(uint rd,uint rn,uint rm)111 STATIC uint asm_arm_op_eor_reg(uint rd, uint rn, uint rm) {
112 // eor rd, rn, rm
113 return 0x0200000 | (rn << 16) | (rd << 12) | rm;
114 }
115
asm_arm_op_orr_reg(uint rd,uint rn,uint rm)116 STATIC uint asm_arm_op_orr_reg(uint rd, uint rn, uint rm) {
117 // orr rd, rn, rm
118 return 0x1800000 | (rn << 16) | (rd << 12) | rm;
119 }
120
asm_arm_bkpt(asm_arm_t * as)121 void asm_arm_bkpt(asm_arm_t *as) {
122 // bkpt #0
123 emit_al(as, 0x1200070);
124 }
125
126 // locals:
127 // - stored on the stack in ascending order
128 // - numbered 0 through num_locals-1
129 // - SP points to first local
130 //
131 // | SP
132 // v
133 // l0 l1 l2 ... l(n-1)
134 // ^ ^
135 // | low address | high address in RAM
136
asm_arm_entry(asm_arm_t * as,int num_locals)137 void asm_arm_entry(asm_arm_t *as, int num_locals) {
138 assert(num_locals >= 0);
139
140 as->stack_adjust = 0;
141 as->push_reglist = 1 << ASM_ARM_REG_R1
142 | 1 << ASM_ARM_REG_R2
143 | 1 << ASM_ARM_REG_R3
144 | 1 << ASM_ARM_REG_R4
145 | 1 << ASM_ARM_REG_R5
146 | 1 << ASM_ARM_REG_R6
147 | 1 << ASM_ARM_REG_R7
148 | 1 << ASM_ARM_REG_R8;
149
150 // Only adjust the stack if there are more locals than usable registers
151 if (num_locals > 3) {
152 as->stack_adjust = num_locals * 4;
153 // Align stack to 8 bytes
154 if (num_locals & 1) {
155 as->stack_adjust += 4;
156 }
157 }
158
159 emit_al(as, asm_arm_op_push(as->push_reglist | 1 << ASM_ARM_REG_LR));
160 if (as->stack_adjust > 0) {
161 emit_al(as, asm_arm_op_sub_imm(ASM_ARM_REG_SP, ASM_ARM_REG_SP, as->stack_adjust));
162 }
163 }
164
asm_arm_exit(asm_arm_t * as)165 void asm_arm_exit(asm_arm_t *as) {
166 if (as->stack_adjust > 0) {
167 emit_al(as, asm_arm_op_add_imm(ASM_ARM_REG_SP, ASM_ARM_REG_SP, as->stack_adjust));
168 }
169
170 emit_al(as, asm_arm_op_pop(as->push_reglist | (1 << ASM_ARM_REG_PC)));
171 }
172
asm_arm_push(asm_arm_t * as,uint reglist)173 void asm_arm_push(asm_arm_t *as, uint reglist) {
174 emit_al(as, asm_arm_op_push(reglist));
175 }
176
asm_arm_pop(asm_arm_t * as,uint reglist)177 void asm_arm_pop(asm_arm_t *as, uint reglist) {
178 emit_al(as, asm_arm_op_pop(reglist));
179 }
180
asm_arm_mov_reg_reg(asm_arm_t * as,uint reg_dest,uint reg_src)181 void asm_arm_mov_reg_reg(asm_arm_t *as, uint reg_dest, uint reg_src) {
182 emit_al(as, asm_arm_op_mov_reg(reg_dest, reg_src));
183 }
184
asm_arm_mov_reg_i32(asm_arm_t * as,uint rd,int imm)185 size_t asm_arm_mov_reg_i32(asm_arm_t *as, uint rd, int imm) {
186 // Insert immediate into code and jump over it
187 emit_al(as, 0x59f0000 | (rd << 12)); // ldr rd, [pc]
188 emit_al(as, 0xa000000); // b pc
189 size_t loc = mp_asm_base_get_code_pos(&as->base);
190 emit(as, imm);
191 return loc;
192 }
193
asm_arm_mov_reg_i32_optimised(asm_arm_t * as,uint rd,int imm)194 void asm_arm_mov_reg_i32_optimised(asm_arm_t *as, uint rd, int imm) {
195 // TODO: There are more variants of immediate values
196 if ((imm & 0xFF) == imm) {
197 emit_al(as, asm_arm_op_mov_imm(rd, imm));
198 } else if (imm < 0 && imm >= -256) {
199 // mvn is "move not", not "move negative"
200 emit_al(as, asm_arm_op_mvn_imm(rd, ~imm));
201 } else {
202 asm_arm_mov_reg_i32(as, rd, imm);
203 }
204 }
205
asm_arm_mov_local_reg(asm_arm_t * as,int local_num,uint rd)206 void asm_arm_mov_local_reg(asm_arm_t *as, int local_num, uint rd) {
207 // str rd, [sp, #local_num*4]
208 emit_al(as, 0x58d0000 | (rd << 12) | (local_num << 2));
209 }
210
asm_arm_mov_reg_local(asm_arm_t * as,uint rd,int local_num)211 void asm_arm_mov_reg_local(asm_arm_t *as, uint rd, int local_num) {
212 // ldr rd, [sp, #local_num*4]
213 emit_al(as, 0x59d0000 | (rd << 12) | (local_num << 2));
214 }
215
asm_arm_cmp_reg_i8(asm_arm_t * as,uint rd,int imm)216 void asm_arm_cmp_reg_i8(asm_arm_t *as, uint rd, int imm) {
217 // cmp rd, #imm
218 emit_al(as, 0x3500000 | (rd << 16) | (imm & 0xFF));
219 }
220
asm_arm_cmp_reg_reg(asm_arm_t * as,uint rd,uint rn)221 void asm_arm_cmp_reg_reg(asm_arm_t *as, uint rd, uint rn) {
222 // cmp rd, rn
223 emit_al(as, 0x1500000 | (rd << 16) | rn);
224 }
225
asm_arm_setcc_reg(asm_arm_t * as,uint rd,uint cond)226 void asm_arm_setcc_reg(asm_arm_t *as, uint rd, uint cond) {
227 emit(as, asm_arm_op_mov_imm(rd, 1) | cond); // movCOND rd, #1
228 emit(as, asm_arm_op_mov_imm(rd, 0) | (cond ^ (1 << 28))); // mov!COND rd, #0
229 }
230
asm_arm_add_reg_reg_reg(asm_arm_t * as,uint rd,uint rn,uint rm)231 void asm_arm_add_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
232 // add rd, rn, rm
233 emit_al(as, asm_arm_op_add_reg(rd, rn, rm));
234 }
235
asm_arm_sub_reg_reg_reg(asm_arm_t * as,uint rd,uint rn,uint rm)236 void asm_arm_sub_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
237 // sub rd, rn, rm
238 emit_al(as, asm_arm_op_sub_reg(rd, rn, rm));
239 }
240
asm_arm_mul_reg_reg_reg(asm_arm_t * as,uint rd,uint rs,uint rm)241 void asm_arm_mul_reg_reg_reg(asm_arm_t *as, uint rd, uint rs, uint rm) {
242 // rs and rm are swapped because of restriction rd!=rm
243 // mul rd, rm, rs
244 emit_al(as, asm_arm_op_mul_reg(rd, rm, rs));
245 }
246
asm_arm_and_reg_reg_reg(asm_arm_t * as,uint rd,uint rn,uint rm)247 void asm_arm_and_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
248 // and rd, rn, rm
249 emit_al(as, asm_arm_op_and_reg(rd, rn, rm));
250 }
251
asm_arm_eor_reg_reg_reg(asm_arm_t * as,uint rd,uint rn,uint rm)252 void asm_arm_eor_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
253 // eor rd, rn, rm
254 emit_al(as, asm_arm_op_eor_reg(rd, rn, rm));
255 }
256
asm_arm_orr_reg_reg_reg(asm_arm_t * as,uint rd,uint rn,uint rm)257 void asm_arm_orr_reg_reg_reg(asm_arm_t *as, uint rd, uint rn, uint rm) {
258 // orr rd, rn, rm
259 emit_al(as, asm_arm_op_orr_reg(rd, rn, rm));
260 }
261
asm_arm_mov_reg_local_addr(asm_arm_t * as,uint rd,int local_num)262 void asm_arm_mov_reg_local_addr(asm_arm_t *as, uint rd, int local_num) {
263 // add rd, sp, #local_num*4
264 emit_al(as, asm_arm_op_add_imm(rd, ASM_ARM_REG_SP, local_num << 2));
265 }
266
asm_arm_mov_reg_pcrel(asm_arm_t * as,uint reg_dest,uint label)267 void asm_arm_mov_reg_pcrel(asm_arm_t *as, uint reg_dest, uint label) {
268 assert(label < as->base.max_num_labels);
269 mp_uint_t dest = as->base.label_offsets[label];
270 mp_int_t rel = dest - as->base.code_offset;
271 rel -= 12 + 8; // adjust for load of rel, and then PC+8 prefetch of add_reg_reg_reg
272
273 // To load rel int reg_dest, insert immediate into code and jump over it
274 emit_al(as, 0x59f0000 | (reg_dest << 12)); // ldr rd, [pc]
275 emit_al(as, 0xa000000); // b pc
276 emit(as, rel);
277
278 // Do reg_dest += PC
279 asm_arm_add_reg_reg_reg(as, reg_dest, reg_dest, ASM_ARM_REG_PC);
280 }
281
asm_arm_lsl_reg_reg(asm_arm_t * as,uint rd,uint rs)282 void asm_arm_lsl_reg_reg(asm_arm_t *as, uint rd, uint rs) {
283 // mov rd, rd, lsl rs
284 emit_al(as, 0x1a00010 | (rd << 12) | (rs << 8) | rd);
285 }
286
asm_arm_lsr_reg_reg(asm_arm_t * as,uint rd,uint rs)287 void asm_arm_lsr_reg_reg(asm_arm_t *as, uint rd, uint rs) {
288 // mov rd, rd, lsr rs
289 emit_al(as, 0x1a00030 | (rd << 12) | (rs << 8) | rd);
290 }
291
asm_arm_asr_reg_reg(asm_arm_t * as,uint rd,uint rs)292 void asm_arm_asr_reg_reg(asm_arm_t *as, uint rd, uint rs) {
293 // mov rd, rd, asr rs
294 emit_al(as, 0x1a00050 | (rd << 12) | (rs << 8) | rd);
295 }
296
asm_arm_ldr_reg_reg(asm_arm_t * as,uint rd,uint rn,uint byte_offset)297 void asm_arm_ldr_reg_reg(asm_arm_t *as, uint rd, uint rn, uint byte_offset) {
298 // ldr rd, [rn, #off]
299 emit_al(as, 0x5900000 | (rn << 16) | (rd << 12) | byte_offset);
300 }
301
asm_arm_ldrh_reg_reg(asm_arm_t * as,uint rd,uint rn)302 void asm_arm_ldrh_reg_reg(asm_arm_t *as, uint rd, uint rn) {
303 // ldrh rd, [rn]
304 emit_al(as, 0x1d000b0 | (rn << 16) | (rd << 12));
305 }
306
asm_arm_ldrb_reg_reg(asm_arm_t * as,uint rd,uint rn)307 void asm_arm_ldrb_reg_reg(asm_arm_t *as, uint rd, uint rn) {
308 // ldrb rd, [rn]
309 emit_al(as, 0x5d00000 | (rn << 16) | (rd << 12));
310 }
311
asm_arm_str_reg_reg(asm_arm_t * as,uint rd,uint rm,uint byte_offset)312 void asm_arm_str_reg_reg(asm_arm_t *as, uint rd, uint rm, uint byte_offset) {
313 // str rd, [rm, #off]
314 emit_al(as, 0x5800000 | (rm << 16) | (rd << 12) | byte_offset);
315 }
316
asm_arm_strh_reg_reg(asm_arm_t * as,uint rd,uint rm)317 void asm_arm_strh_reg_reg(asm_arm_t *as, uint rd, uint rm) {
318 // strh rd, [rm]
319 emit_al(as, 0x1c000b0 | (rm << 16) | (rd << 12));
320 }
321
asm_arm_strb_reg_reg(asm_arm_t * as,uint rd,uint rm)322 void asm_arm_strb_reg_reg(asm_arm_t *as, uint rd, uint rm) {
323 // strb rd, [rm]
324 emit_al(as, 0x5c00000 | (rm << 16) | (rd << 12));
325 }
326
asm_arm_str_reg_reg_reg(asm_arm_t * as,uint rd,uint rm,uint rn)327 void asm_arm_str_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn) {
328 // str rd, [rm, rn, lsl #2]
329 emit_al(as, 0x7800100 | (rm << 16) | (rd << 12) | rn);
330 }
331
asm_arm_strh_reg_reg_reg(asm_arm_t * as,uint rd,uint rm,uint rn)332 void asm_arm_strh_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn) {
333 // strh doesn't support scaled register index
334 emit_al(as, 0x1a00080 | (ASM_ARM_REG_R8 << 12) | rn); // mov r8, rn, lsl #1
335 emit_al(as, 0x18000b0 | (rm << 16) | (rd << 12) | ASM_ARM_REG_R8); // strh rd, [rm, r8]
336 }
337
asm_arm_strb_reg_reg_reg(asm_arm_t * as,uint rd,uint rm,uint rn)338 void asm_arm_strb_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn) {
339 // strb rd, [rm, rn]
340 emit_al(as, 0x7c00000 | (rm << 16) | (rd << 12) | rn);
341 }
342
asm_arm_bcc_label(asm_arm_t * as,int cond,uint label)343 void asm_arm_bcc_label(asm_arm_t *as, int cond, uint label) {
344 assert(label < as->base.max_num_labels);
345 mp_uint_t dest = as->base.label_offsets[label];
346 mp_int_t rel = dest - as->base.code_offset;
347 rel -= 8; // account for instruction prefetch, PC is 8 bytes ahead of this instruction
348 rel >>= 2; // in ARM mode the branch target is 32-bit aligned, so the 2 LSB are omitted
349
350 if (SIGNED_FIT24(rel)) {
351 emit(as, cond | 0xa000000 | (rel & 0xffffff));
352 } else {
353 printf("asm_arm_bcc: branch does not fit in 24 bits\n");
354 }
355 }
356
asm_arm_b_label(asm_arm_t * as,uint label)357 void asm_arm_b_label(asm_arm_t *as, uint label) {
358 asm_arm_bcc_label(as, ASM_ARM_CC_AL, label);
359 }
360
asm_arm_bl_ind(asm_arm_t * as,uint fun_id,uint reg_temp)361 void asm_arm_bl_ind(asm_arm_t *as, uint fun_id, uint reg_temp) {
362 // The table offset should fit into the ldr instruction
363 assert(fun_id < (0x1000 / 4));
364 emit_al(as, asm_arm_op_mov_reg(ASM_ARM_REG_LR, ASM_ARM_REG_PC)); // mov lr, pc
365 emit_al(as, 0x597f000 | (fun_id << 2)); // ldr pc, [r7, #fun_id*4]
366 }
367
asm_arm_bx_reg(asm_arm_t * as,uint reg_src)368 void asm_arm_bx_reg(asm_arm_t *as, uint reg_src) {
369 emit_al(as, 0x012fff10 | reg_src);
370 }
371
372 #endif // MICROPY_EMIT_ARM
373