1# Copyright 2003-2011 Novell, Inc (http://www.novell.com) 2# Copyright 2011 Xamarin, Inc (http://www.xamarin.com) 3# Licensed under the MIT license. See LICENSE file in the project root for full license information. 4# arm cpu description file 5# this file is read by genmdesc to pruduce a table with all the relevant information 6# about the cpu instructions that may be used by the regsiter allocator, the scheduler 7# and other parts of the arch-dependent part of mini. 8# 9# An opcode name is followed by a colon and optional specifiers. 10# A specifier has a name, a colon and a value. Specifiers are separated by white space. 11# Here is a description of the specifiers valid for this file and their possible values. 12# 13# dest:register describes the destination register of an instruction 14# src1:register describes the first source register of an instruction 15# src2:register describes the second source register of an instruction 16# 17# register may have the following values: 18# i integer register 19# a r0 register (first argument/result reg) 20# b base register (used in address references) 21# f floating point register 22# g floating point register returned in r0:r1 for soft-float mode 23# 24# len:number describe the maximun length in bytes of the instruction 25# number is a positive integer 26# 27# cost:number describe how many cycles are needed to complete the instruction (unused) 28# 29# clob:spec describe if the instruction clobbers registers or has special needs 30# 31# spec can be one of the following characters: 32# c clobbers caller-save registers 33# r 'reserves' the destination register until a later instruction unreserves it 34# used mostly to set output registers in function calls 35# 36# flags:spec describe if the instruction uses or sets the flags (unused) 37# 38# spec can be one of the following chars: 39# s sets the flags 40# u uses the flags 41# m uses and modifies the flags 42# 43# res:spec describe what units are used in the processor (unused) 44# 45# delay: describe delay slots (unused) 46# 47# the required specifiers are: len, clob (if registers are clobbered), the registers 48# specifiers if the registers are actually used, flags (when scheduling is implemented). 49# 50# See the code in mini-x86.c for more details on how the specifiers are used. 51# 52nop: len:4 53relaxed_nop: len:4 54break: len:4 55br: len:16 56switch: src1:i len:12 57# See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux, 58# since the corresponding sigctx structures are not well defined. 59seq_point: len:52 clob:c 60il_seq_point: len:0 61 62throw: src1:i len:24 63rethrow: src1:i len:20 64start_handler: len:20 65endfinally: len:32 66call_handler: len:16 clob:c 67endfilter: src1:i len:16 68get_ex_obj: dest:i len:16 69 70ckfinite: dest:f src1:f len:112 71ceq: dest:i len:12 72cgt: dest:i len:12 73cgt.un: dest:i len:12 74clt: dest:i len:12 75clt.un: dest:i len:12 76localloc: dest:i src1:i len:60 77compare: src1:i src2:i len:4 78compare_imm: src1:i len:12 79fcompare: src1:f src2:f len:12 80rcompare: src1:f src2:f len:12 81oparglist: src1:i len:12 82setlret: src1:i src2:i len:12 83checkthis: src1:b len:4 84call: dest:a clob:c len:20 85call_reg: dest:a src1:i len:8 clob:c 86call_membase: dest:a src1:b len:30 clob:c 87voidcall: len:20 clob:c 88voidcall_reg: src1:i len:8 clob:c 89voidcall_membase: src1:b len:24 clob:c 90fcall: dest:g len:28 clob:c 91fcall_reg: dest:g src1:i len:16 clob:c 92fcall_membase: dest:g src1:b len:30 clob:c 93rcall: dest:g len:28 clob:c 94rcall_reg: dest:g src1:i len:16 clob:c 95rcall_membase: dest:g src1:b len:30 clob:c 96lcall: dest:l len:20 clob:c 97lcall_reg: dest:l src1:i len:8 clob:c 98lcall_membase: dest:l src1:b len:24 clob:c 99vcall: len:64 clob:c 100vcall_reg: src1:i len:64 clob:c 101vcall_membase: src1:b len:70 clob:c 102tailcall: len:160 clob:c 103iconst: dest:i len:16 104r4const: dest:f len:24 105r8const: dest:f len:20 106label: len:0 107store_membase_imm: dest:b len:20 108store_membase_reg: dest:b src1:i len:20 109storei1_membase_imm: dest:b len:20 110storei1_membase_reg: dest:b src1:i len:12 111storei2_membase_imm: dest:b len:20 112storei2_membase_reg: dest:b src1:i len:12 113storei4_membase_imm: dest:b len:20 114storei4_membase_reg: dest:b src1:i len:20 115storei8_membase_imm: dest:b 116storei8_membase_reg: dest:b src1:i 117storer4_membase_reg: dest:b src1:f len:60 118storer8_membase_reg: dest:b src1:f len:24 119store_memindex: dest:b src1:i src2:i len:4 120storei1_memindex: dest:b src1:i src2:i len:4 121storei2_memindex: dest:b src1:i src2:i len:4 122storei4_memindex: dest:b src1:i src2:i len:4 123load_membase: dest:i src1:b len:20 124loadi1_membase: dest:i src1:b len:4 125loadu1_membase: dest:i src1:b len:4 126loadi2_membase: dest:i src1:b len:4 127loadu2_membase: dest:i src1:b len:4 128loadi4_membase: dest:i src1:b len:4 129loadu4_membase: dest:i src1:b len:4 130loadi8_membase: dest:i src1:b 131loadr4_membase: dest:f src1:b len:56 132loadr8_membase: dest:f src1:b len:24 133load_memindex: dest:i src1:b src2:i len:4 134loadi1_memindex: dest:i src1:b src2:i len:4 135loadu1_memindex: dest:i src1:b src2:i len:4 136loadi2_memindex: dest:i src1:b src2:i len:4 137loadu2_memindex: dest:i src1:b src2:i len:4 138loadi4_memindex: dest:i src1:b src2:i len:4 139loadu4_memindex: dest:i src1:b src2:i len:4 140loadu4_mem: dest:i len:8 141move: dest:i src1:i len:4 142fmove: dest:f src1:f len:4 143move_f_to_i4: dest:i src1:f len:28 144move_i4_to_f: dest:f src1:i len:8 145add_imm: dest:i src1:i len:12 146sub_imm: dest:i src1:i len:12 147mul_imm: dest:i src1:i len:12 148and_imm: dest:i src1:i len:12 149or_imm: dest:i src1:i len:12 150xor_imm: dest:i src1:i len:12 151shl_imm: dest:i src1:i len:8 152shr_imm: dest:i src1:i len:8 153shr_un_imm: dest:i src1:i len:8 154cond_exc_eq: len:8 155cond_exc_ne_un: len:8 156cond_exc_lt: len:8 157cond_exc_lt_un: len:8 158cond_exc_gt: len:8 159cond_exc_gt_un: len:8 160cond_exc_ge: len:8 161cond_exc_ge_un: len:8 162cond_exc_le: len:8 163cond_exc_le_un: len:8 164cond_exc_ov: len:12 165cond_exc_no: len:8 166cond_exc_c: len:12 167cond_exc_nc: len:8 168#float_beq: src1:f src2:f len:20 169#float_bne_un: src1:f src2:f len:20 170#float_blt: src1:f src2:f len:20 171#float_blt_un: src1:f src2:f len:20 172#float_bgt: src1:f src2:f len:20 173#float_bgt_un: src1:f src2:f len:20 174#float_bge: src1:f src2:f len:20 175#float_bge_un: src1:f src2:f len:20 176#float_ble: src1:f src2:f len:20 177#float_ble_un: src1:f src2:f len:20 178float_add: dest:f src1:f src2:f len:4 179float_sub: dest:f src1:f src2:f len:4 180float_mul: dest:f src1:f src2:f len:4 181float_div: dest:f src1:f src2:f len:4 182float_div_un: dest:f src1:f src2:f len:4 183float_rem: dest:f src1:f src2:f len:16 184float_rem_un: dest:f src1:f src2:f len:16 185float_neg: dest:f src1:f len:4 186float_not: dest:f src1:f len:4 187float_conv_to_i1: dest:i src1:f len:88 188float_conv_to_i2: dest:i src1:f len:88 189float_conv_to_i4: dest:i src1:f len:88 190float_conv_to_i8: dest:l src1:f len:88 191float_conv_to_r4: dest:f src1:f len:8 192float_conv_to_u4: dest:i src1:f len:88 193float_conv_to_u8: dest:l src1:f len:88 194float_conv_to_u2: dest:i src1:f len:88 195float_conv_to_u1: dest:i src1:f len:88 196float_conv_to_i: dest:i src1:f len:40 197float_ceq: dest:i src1:f src2:f len:16 198float_cgt: dest:i src1:f src2:f len:16 199float_cgt_un: dest:i src1:f src2:f len:20 200float_clt: dest:i src1:f src2:f len:16 201float_clt_un: dest:i src1:f src2:f len:20 202float_cneq: dest:y src1:f src2:f len:20 203float_cge: dest:y src1:f src2:f len:20 204float_cle: dest:y src1:f src2:f len:20 205float_conv_to_u: dest:i src1:f len:36 206 207# R4 opcodes 208rmove: dest:f src1:f len:4 209r4_conv_to_i1: dest:i src1:f len:88 210r4_conv_to_i2: dest:i src1:f len:88 211r4_conv_to_i4: dest:i src1:f len:88 212r4_conv_to_u1: dest:i src1:f len:88 213r4_conv_to_u2: dest:i src1:f len:88 214r4_conv_to_u4: dest:i src1:f len:88 215r4_conv_to_r4: dest:f src1:f len:16 216r4_conv_to_r8: dest:f src1:f len:16 217r4_add: dest:f src1:f src2:f len:4 218r4_sub: dest:f src1:f src2:f len:4 219r4_mul: dest:f src1:f src2:f len:4 220r4_div: dest:f src1:f src2:f len:4 221r4_rem: dest:f src1:f src2:f len:16 222r4_neg: dest:f src1:f len:4 223r4_ceq: dest:i src1:f src2:f len:16 224r4_cgt: dest:i src1:f src2:f len:16 225r4_cgt_un: dest:i src1:f src2:f len:20 226r4_clt: dest:i src1:f src2:f len:16 227r4_clt_un: dest:i src1:f src2:f len:20 228r4_cneq: dest:y src1:f src2:f len:20 229r4_cge: dest:y src1:f src2:f len:20 230r4_cle: dest:y src1:f src2:f len:20 231 232setfret: src1:f len:12 233aot_const: dest:i len:16 234objc_get_selector: dest:i len:32 235sqrt: dest:f src1:f len:4 236adc: dest:i src1:i src2:i len:4 237addcc: dest:i src1:i src2:i len:4 238subcc: dest:i src1:i src2:i len:4 239adc_imm: dest:i src1:i len:12 240addcc_imm: dest:i src1:i len:12 241subcc_imm: dest:i src1:i len:12 242sbb: dest:i src1:i src2:i len:4 243sbb_imm: dest:i src1:i len:12 244br_reg: src1:i len:8 245bigmul: len:8 dest:l src1:i src2:i 246bigmul_un: len:8 dest:l src1:i src2:i 247tls_get: len:16 dest:i 248tls_set: len:16 src1:i clob:c 249 250# 32 bit opcodes 251int_add: dest:i src1:i src2:i len:4 252int_sub: dest:i src1:i src2:i len:4 253int_mul: dest:i src1:i src2:i len:4 254int_div: dest:i src1:i src2:i len:4 255int_div_un: dest:i src1:i src2:i len:4 256int_rem: dest:i src1:i src2:i len:8 257int_rem_un: dest:i src1:i src2:i len:8 258int_and: dest:i src1:i src2:i len:4 259int_or: dest:i src1:i src2:i len:4 260int_xor: dest:i src1:i src2:i len:4 261int_shl: dest:i src1:i src2:i len:4 262int_shr: dest:i src1:i src2:i len:4 263int_shr_un: dest:i src1:i src2:i len:4 264int_neg: dest:i src1:i len:4 265int_not: dest:i src1:i len:4 266int_conv_to_i1: dest:i src1:i len:8 267int_conv_to_i2: dest:i src1:i len:8 268int_conv_to_i4: dest:i src1:i len:4 269int_conv_to_r4: dest:f src1:i len:84 270int_conv_to_r8: dest:f src1:i len:84 271int_conv_to_u4: dest:i src1:i 272int_conv_to_r_un: dest:f src1:i len:56 273int_conv_to_u2: dest:i src1:i len:8 274int_conv_to_u1: dest:i src1:i len:4 275int_beq: len:16 276int_bge: len:16 277int_bgt: len:16 278int_ble: len:16 279int_blt: len:16 280int_bne_un: len:16 281int_bge_un: len:16 282int_bgt_un: len:16 283int_ble_un: len:16 284int_blt_un: len:16 285int_add_ovf: dest:i src1:i src2:i len:16 286int_add_ovf_un: dest:i src1:i src2:i len:16 287int_mul_ovf: dest:i src1:i src2:i len:16 288int_mul_ovf_un: dest:i src1:i src2:i len:16 289int_sub_ovf: dest:i src1:i src2:i len:16 290int_sub_ovf_un: dest:i src1:i src2:i len:16 291add_ovf_carry: dest:i src1:i src2:i len:16 292sub_ovf_carry: dest:i src1:i src2:i len:16 293add_ovf_un_carry: dest:i src1:i src2:i len:16 294sub_ovf_un_carry: dest:i src1:i src2:i len:16 295 296arm_rsbs_imm: dest:i src1:i len:4 297arm_rsc_imm: dest:i src1:i len:4 298 299# Linear IR opcodes 300dummy_use: src1:i len:0 301dummy_store: len:0 302dummy_iconst: dest:i len:0 303dummy_r8const: dest:f len:0 304not_reached: len:0 305not_null: src1:i len:0 306 307int_adc: dest:i src1:i src2:i len:4 308int_addcc: dest:i src1:i src2:i len:4 309int_subcc: dest:i src1:i src2:i len:4 310int_sbb: dest:i src1:i src2:i len:4 311int_adc_imm: dest:i src1:i len:12 312int_sbb_imm: dest:i src1:i len:12 313 314int_add_imm: dest:i src1:i len:12 315int_sub_imm: dest:i src1:i len:12 316int_mul_imm: dest:i src1:i len:12 317int_div_imm: dest:i src1:i len:20 318int_div_un_imm: dest:i src1:i len:12 319int_rem_imm: dest:i src1:i len:28 320int_rem_un_imm: dest:i src1:i len:16 321int_and_imm: dest:i src1:i len:12 322int_or_imm: dest:i src1:i len:12 323int_xor_imm: dest:i src1:i len:12 324int_shl_imm: dest:i src1:i len:8 325int_shr_imm: dest:i src1:i len:8 326int_shr_un_imm: dest:i src1:i len:8 327 328int_ceq: dest:i len:12 329int_cgt: dest:i len:12 330int_cgt_un: dest:i len:12 331int_clt: dest:i len:12 332int_clt_un: dest:i len:12 333 334int_cneq: dest:i len:12 335int_cge: dest:i len:12 336int_cle: dest:i len:12 337int_cge_un: dest:i len:12 338int_cle_un: dest:i len:12 339 340cond_exc_ieq: len:16 341cond_exc_ine_un: len:16 342cond_exc_ilt: len:16 343cond_exc_ilt_un: len:16 344cond_exc_igt: len:16 345cond_exc_igt_un: len:16 346cond_exc_ige: len:16 347cond_exc_ige_un: len:16 348cond_exc_ile: len:16 349cond_exc_ile_un: len:16 350cond_exc_iov: len:20 351cond_exc_ino: len:16 352cond_exc_ic: len:20 353cond_exc_inc: len:16 354 355icompare: src1:i src2:i len:4 356icompare_imm: src1:i len:12 357 358long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36 359 360vcall2: len:64 clob:c 361vcall2_reg: src1:i len:64 clob:c 362vcall2_membase: src1:b len:64 clob:c 363dyn_call: src1:i src2:i len:252 clob:c 364 365# This is different from the original JIT opcodes 366float_beq: len:32 367float_bne_un: len:32 368float_blt: len:32 369float_blt_un: len:32 370float_bgt: len:32 371float_bgt_un: len:32 372float_bge: len:32 373float_bge_un: len:32 374float_ble: len:32 375float_ble_un: len:32 376 377liverange_start: len:0 378liverange_end: len:0 379gc_liveness_def: len:0 380gc_liveness_use: len:0 381gc_spill_slot_liveness_def: len:0 382gc_param_slot_liveness_def: len:0 383gc_safe_point: clob:c src1:i len:40 384 385atomic_add_i4: dest:i src1:i src2:i len:64 386atomic_exchange_i4: dest:i src1:i src2:i len:64 387atomic_cas_i4: dest:i src1:i src2:i src3:i len:64 388memory_barrier: len:8 clob:a 389atomic_load_i1: dest:i src1:b len:28 390atomic_load_u1: dest:i src1:b len:28 391atomic_load_i2: dest:i src1:b len:28 392atomic_load_u2: dest:i src1:b len:28 393atomic_load_i4: dest:i src1:b len:28 394atomic_load_u4: dest:i src1:b len:28 395atomic_load_r4: dest:f src1:b len:80 396atomic_load_r8: dest:f src1:b len:32 397atomic_store_i1: dest:b src1:i len:28 398atomic_store_u1: dest:b src1:i len:28 399atomic_store_i2: dest:b src1:i len:28 400atomic_store_u2: dest:b src1:i len:28 401atomic_store_i4: dest:b src1:i len:28 402atomic_store_u4: dest:b src1:i len:28 403atomic_store_r4: dest:b src1:f len:80 404atomic_store_r8: dest:b src1:f len:32 405 406generic_class_init: src1:a len:44 clob:c 407 408fill_prof_call_ctx: src1:i len:128 409