1# mips cpu description file 2# this file is read by genmdesc to pruduce a table with all the relevant 3# information about the cpu instructions that may be used by the regsiter 4# allocator, the scheduler and other parts of the arch-dependent part of mini. 5# 6# An opcode name is followed by a colon and optional specifiers. 7# A specifier has a name, a colon and a value. 8# Specifiers are separated by white space. 9# Here is a description of the specifiers valid for this file and their 10# possible values. 11# 12# dest:register describes the destination register of an instruction 13# src1:register describes the first source register of an instruction 14# src2:register describes the second source register of an instruction 15# 16# register may have the following values: 17# i integer register 18# l integer register pair 19# v v0 register (output from calls) 20# V v0/v1 register pair (output from calls) 21# a at register 22# b base register (used in address references) 23# f floating point register (pair - always) 24# g floating point register return pair (f0/f1) 25# 26# len:number describe the maximun length in bytes of the instruction 27# number is a positive integer 28# 29# cost:number describe how many cycles are needed to complete the instruction (unused) 30# 31# clob:spec describe if the instruction clobbers registers or has special needs 32# 33# spec can be one of the following characters: 34# c clobbers caller-save registers 35# r 'reserves' the destination register until a later instruction unreserves it 36# used mostly to set output registers in function calls 37# 38# flags:spec describe if the instruction uses or sets the flags (unused) 39# 40# spec can be one of the following chars: 41# s sets the flags 42# u uses the flags 43# m uses and modifies the flags 44# 45# res:spec describe what units are used in the processor (unused) 46# 47# delay: describe delay slots (unused) 48# 49# the required specifiers are: len, clob (if registers are clobbered), the registers 50# specifiers if the registers are actually used, flags (when scheduling is implemented). 51# 52# See the code in mini-x86.c for more details on how the specifiers are used. 53# 54memory_barrier: len:4 55nop: len:4 56relaxed_nop: len:4 57break: len:16 58jmp: len:92 59call: dest:v clob:c len:20 60br: len:16 61switch: src1:i len:40 62seq_point: len:24 63il_seq_point: len:0 64 65int_conv_to_r_un: dest:f src1:i len:32 66throw: src1:i len:24 67rethrow: src1:i len:24 68ckfinite: dest:f src1:f len:52 69start_handler: len:16 70endfinally: len:12 71ceq: dest:i len:16 72cgt: dest:i len:16 73cgt.un: dest:i len:16 74clt: dest:i len:16 75clt.un: dest:i len:16 76localloc: dest:i src1:i len:60 77compare: src1:i src2:i len:20 78compare_imm: src1:i len:20 79fcompare: src1:f src2:f len:12 80oparglist: src1:i len:12 81setlret: src1:i src2:i len:12 82checkthis: src1:b len:4 83 84voidcall: len:20 clob:c 85voidcall_reg: src1:i len:20 clob:c 86voidcall_membase: src1:b len:20 clob:c 87 88fcall: dest:g len:20 clob:c 89fcall_reg: dest:g src1:i len:20 clob:c 90fcall_membase: dest:g src1:b len:20 clob:c 91 92lcall: dest:V len:28 clob:c 93lcall_reg: dest:V src1:i len:28 clob:c 94lcall_membase: dest:V src1:b len:28 clob:c 95 96call_reg: dest:v src1:i len:20 clob:c 97call_membase: dest:v src1:b len:20 clob:c 98 99vcall: len:16 clob:c 100vcall_reg: src1:i len:20 clob:c 101vcall_membase: src1:b len:20 clob:c 102 103vcall2: len:16 clob:c 104vcall2_reg: src1:i len:20 clob:c 105vcall2_membase: src1:b len:20 clob:c 106 107jump_table: dest:i len:8 108 109iconst: dest:i len:12 110i8const: dest:l len:24 111r4const: dest:f len:20 112r8const: dest:f len:28 113label: len:0 114store_membase_imm: dest:b len:20 115store_membase_reg: dest:b src1:i len:20 116storei1_membase_imm: dest:b len:20 117storei1_membase_reg: dest:b src1:i len:20 118storei2_membase_imm: dest:b len:20 119storei2_membase_reg: dest:b src1:i len:20 120storei4_membase_imm: dest:b len:20 121storei4_membase_reg: dest:b src1:i len:20 122storei8_membase_imm: dest:b 123storei8_membase_reg: dest:b src1:i len:20 124storer4_membase_reg: dest:b src1:f len:20 125storer8_membase_reg: dest:b src1:f len:20 126load_membase: dest:i src1:b len:20 127loadi1_membase: dest:i src1:b len:20 128loadu1_membase: dest:i src1:b len:20 129loadi2_membase: dest:i src1:b len:20 130loadu2_membase: dest:i src1:b len:20 131loadi4_membase: dest:i src1:b len:20 132loadu4_membase: dest:i src1:b len:20 133loadi8_membase: dest:i src1:b len:20 134loadr4_membase: dest:f src1:b len:20 135loadr8_membase: dest:f src1:b len:20 136load_memindex: dest:i src1:b src2:i len:4 137loadi1_memindex: dest:i src1:b src2:i len:12 138loadu1_memindex: dest:i src1:b src2:i len:12 139loadi2_memindex: dest:i src1:b src2:i len:12 140loadu2_memindex: dest:i src1:b src2:i len:12 141loadi4_memindex: dest:i src1:b src2:i len:12 142loadu4_memindex: dest:i src1:b src2:i len:12 143loadr4_memindex: dest:f src1:b src2:i len:12 144loadr8_memindex: dest:f src1:b src2:i len:12 145store_memindex: dest:b src1:i src2:i len:12 146storei1_memindex: dest:b src1:i src2:i len:12 147storei2_memindex: dest:b src1:i src2:i len:12 148storei4_memindex: dest:b src1:i src2:i len:12 149storer4_memindex: dest:b src1:f src2:i len:12 150storer8_memindex: dest:b src1:f src2:i len:12 151loadu4_mem: dest:i len:8 152move: dest:i src1:i len:4 153fmove: dest:f src1:f len:8 154move_f_to_i4: dest:i src1:f len:4 155move_i4_to_f: dest:f src1:i len:4 156add_imm: dest:i src1:i len:12 157sub_imm: dest:i src1:i len:12 158mul_imm: dest:i src1:i len:20 159# there is no actual support for division or reminder by immediate 160# we simulate them, though (but we need to change the burg rules 161# to allocate a symbolic reg for src2) 162div_imm: dest:i src1:i src2:i len:20 163div_un_imm: dest:i src1:i src2:i len:12 164rem_imm: dest:i src1:i src2:i len:28 165rem_un_imm: dest:i src1:i src2:i len:16 166and_imm: dest:i src1:i len:12 167or_imm: dest:i src1:i len:12 168xor_imm: dest:i src1:i len:12 169shl_imm: dest:i src1:i len:8 170shr_imm: dest:i src1:i len:8 171shr_un_imm: dest:i src1:i len:8 172 173# Linear IR opcodes 174dummy_use: src1:i len:0 175dummy_store: len:0 176not_reached: len:0 177not_null: src1:i len:0 178 179# 32 bit opcodes 180int_add: dest:i src1:i src2:i len:4 181int_sub: dest:i src1:i src2:i len:4 182int_mul: dest:i src1:i src2:i len:16 183int_div: dest:i src1:i src2:i len:84 184int_div_un: dest:i src1:i src2:i len:40 185int_rem: dest:i src1:i src2:i len:84 186int_rem_un: dest:i src1:i src2:i len:40 187int_and: dest:i src1:i src2:i len:4 188int_or: dest:i src1:i src2:i len:4 189int_xor: dest:i src1:i src2:i len:4 190int_shl: dest:i src1:i src2:i len:4 191int_shr: dest:i src1:i src2:i len:4 192int_shr_un: dest:i src1:i src2:i len:4 193int_neg: dest:i src1:i len:4 194int_not: dest:i src1:i len:4 195int_conv_to_i1: dest:i src1:i len:8 196int_conv_to_i2: dest:i src1:i len:8 197int_conv_to_i4: dest:i src1:i len:4 198int_conv_to_r4: dest:f src1:i len:36 199int_conv_to_r8: dest:f src1:i len:36 200int_conv_to_u4: dest:i src1:i 201int_conv_to_u2: dest:i src1:i len:8 202int_conv_to_u1: dest:i src1:i len:4 203int_beq: len:8 204int_bge: len:8 205int_bgt: len:8 206int_ble: len:8 207int_blt: len:8 208int_bne_un: len:8 209int_bge_un: len:8 210int_bgt_un: len:8 211int_ble_un: len:8 212int_blt_un: len:8 213int_add_ovf: dest:i src1:i src2:i len:16 214int_add_ovf_un: dest:i src1:i src2:i len:16 215int_mul_ovf: dest:i src1:i src2:i len:56 216int_mul_ovf_un: dest:i src1:i src2:i len:56 217int_sub_ovf: dest:i src1:i src2:i len:16 218int_sub_ovf_un: dest:i src1:i src2:i len:16 219 220int_adc: dest:i src1:i src2:i len:4 221int_addcc: dest:i src1:i src2:i len:4 222int_subcc: dest:i src1:i src2:i len:4 223int_sbb: dest:i src1:i src2:i len:4 224int_adc_imm: dest:i src1:i len:12 225int_sbb_imm: dest:i src1:i len:12 226 227int_add_imm: dest:i src1:i len:12 228int_sub_imm: dest:i src1:i len:12 229int_mul_imm: dest:i src1:i len:12 230int_div_imm: dest:i src1:i len:20 231int_div_un_imm: dest:i src1:i len:12 232int_rem_imm: dest:i src1:i len:28 233int_rem_un_imm: dest:i src1:i len:16 234int_and_imm: dest:i src1:i len:12 235int_or_imm: dest:i src1:i len:12 236int_xor_imm: dest:i src1:i len:12 237int_shl_imm: dest:i src1:i len:8 238int_shr_imm: dest:i src1:i len:8 239int_shr_un_imm: dest:i src1:i len:8 240 241int_ceq: dest:i len:16 242int_cgt: dest:i len:16 243int_cgt_un: dest:i len:16 244int_clt: dest:i len:16 245int_clt_un: dest:i len:16 246 247cond_exc_eq: len:32 248cond_exc_ne_un: len:32 249cond_exc_lt: len:32 250cond_exc_lt_un: len:32 251cond_exc_gt: len:32 252cond_exc_gt_un: len:32 253cond_exc_ge: len:32 254cond_exc_ge_un: len:32 255cond_exc_le: len:32 256cond_exc_le_un: len:32 257cond_exc_ov: len:32 258cond_exc_no: len:32 259cond_exc_c: len:32 260cond_exc_nc: len:32 261 262cond_exc_ieq: len:32 263cond_exc_ine_un: len:32 264cond_exc_ilt: len:32 265cond_exc_ilt_un: len:32 266cond_exc_igt: len:32 267cond_exc_igt_un: len:32 268cond_exc_ige: len:32 269cond_exc_ige_un: len:32 270cond_exc_ile: len:32 271cond_exc_ile_un: len:32 272cond_exc_iov: len:12 273cond_exc_ino: len:32 274cond_exc_ic: len:12 275cond_exc_inc: len:32 276 277icompare: src1:i src2:i len:4 278icompare_imm: src1:i len:12 279 280# 64 bit opcodes 281long_add: dest:i src1:i src2:i len:4 282long_sub: dest:i src1:i src2:i len:4 283long_mul: dest:i src1:i src2:i len:32 284long_mul_imm: dest:i src1:i len:4 285long_div: dest:i src1:i src2:i len:40 286long_div_un: dest:i src1:i src2:i len:16 287long_rem: dest:i src1:i src2:i len:48 288long_rem_un: dest:i src1:i src2:i len:24 289long_and: dest:i src1:i src2:i len:4 290long_or: dest:i src1:i src2:i len:4 291long_xor: dest:i src1:i src2:i len:4 292long_shl: dest:i src1:i src2:i len:4 293long_shl_imm: dest:i src1:i len:4 294long_shr: dest:i src1:i src2:i len:4 295long_shr_un: dest:i src1:i src2:i len:4 296long_shr_imm: dest:i src1:i len:4 297long_shr_un_imm: dest:i src1:i len:4 298long_neg: dest:i src1:i len:4 299long_not: dest:i src1:i len:4 300long_conv_to_i1: dest:i src1:l len:32 301long_conv_to_i2: dest:i src1:l len:32 302long_conv_to_i4: dest:i src1:l len:32 303long_conv_to_r4: dest:f src1:l len:32 304long_conv_to_r8: dest:f src1:l len:32 305long_conv_to_u4: dest:i src1:l len:32 306long_conv_to_u8: dest:l src1:l len:32 307long_conv_to_u2: dest:i src1:l len:32 308long_conv_to_u1: dest:i src1:l len:32 309long_conv_to_i: dest:i src1:l len:32 310long_conv_to_ovf_i: dest:i src1:i src2:i len:32 311long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:32 312zext_i4: dest:i src1:i len:16 313sext_i4: dest:i src1:i len:16 314 315long_beq: len:8 316long_bge: len:8 317long_bgt: len:8 318long_ble: len:8 319long_blt: len:8 320long_bne_un: len:8 321long_bge_un: len:8 322long_bgt_un: len:8 323long_ble_un: len:8 324long_blt_un: len:8 325long_add_ovf: dest:i src1:i src2:i len:16 326long_add_ovf_un: dest:i src1:i src2:i len:16 327long_mul_ovf: dest:i src1:i src2:i len:16 328long_mul_ovf_un: dest:i src1:i src2:i len:16 329long_sub_ovf: dest:i src1:i src2:i len:16 330long_sub_ovf_un: dest:i src1:i src2:i len:16 331 332long_ceq: dest:i len:12 333long_cgt: dest:i len:12 334long_cgt_un: dest:i len:12 335long_clt: dest:i len:12 336long_clt_un: dest:i len:12 337 338long_add_imm: dest:i src1:i clob:1 len:4 339long_sub_imm: dest:i src1:i clob:1 len:4 340long_and_imm: dest:i src1:i clob:1 len:4 341long_or_imm: dest:i src1:i clob:1 len:4 342long_xor_imm: dest:i src1:i clob:1 len:4 343 344lcompare: src1:i src2:i len:4 345lcompare_imm: src1:i len:12 346 347long_conv_to_r_un: dest:f src1:i src2:i len:37 348 349float_beq: len:16 350float_bne_un: len:16 351float_blt: len:16 352float_blt_un: len:16 353float_bgt: len:16 354float_bgt_un: len:16 355float_bge: len:16 356float_bge_un: len:16 357float_ble: len:16 358float_ble_un: len:16 359 360float_add: dest:f src1:f src2:f len:4 361float_sub: dest:f src1:f src2:f len:4 362float_mul: dest:f src1:f src2:f len:4 363float_div: dest:f src1:f src2:f len:4 364float_div_un: dest:f src1:f src2:f len:4 365float_rem: dest:f src1:f src2:f len:16 366float_rem_un: dest:f src1:f src2:f len:16 367float_neg: dest:f src1:f len:4 368float_not: dest:f src1:f len:4 369float_conv_to_i1: dest:i src1:f len:40 370float_conv_to_i2: dest:i src1:f len:40 371float_conv_to_i4: dest:i src1:f len:40 372float_conv_to_i8: dest:l src1:f len:40 373float_conv_to_r4: dest:f src1:f len:8 374float_conv_to_u4: dest:i src1:f len:40 375float_conv_to_u8: dest:l src1:f len:40 376float_conv_to_u2: dest:i src1:f len:40 377float_conv_to_u1: dest:i src1:f len:40 378float_conv_to_i: dest:i src1:f len:40 379float_ceq: dest:i src1:f src2:f len:20 380float_cgt: dest:i src1:f src2:f len:20 381float_cgt_un: dest:i src1:f src2:f len:20 382float_clt: dest:i src1:f src2:f len:20 383float_clt_un: dest:i src1:f src2:f len:20 384float_conv_to_u: dest:i src1:f len:36 385call_handler: len:20 clob:c 386endfilter: src1:i len:16 387aot_const: dest:i len:8 388sqrt: dest:f src1:f len:4 389adc: dest:i src1:i src2:i len:4 390addcc: dest:i src1:i src2:i len:4 391subcc: dest:i src1:i src2:i len:4 392adc_imm: dest:i src1:i len:12 393addcc_imm: dest:i src1:i len:12 394subcc_imm: dest:i src1:i len:12 395sbb: dest:i src1:i src2:i len:4 396sbb_imm: dest:i src1:i len:12 397br_reg: src1:i len:8 398#ppc_subfic: dest:i src1:i len:4 399#ppc_subfze: dest:i src1:i len:4 400bigmul: len:52 dest:l src1:i src2:i 401bigmul_un: len:52 dest:l src1:i src2:i 402mips_beq: src1:i src2:i len:24 403mips_bgez: src1:i len:24 404mips_bgtz: src1:i len:24 405mips_blez: src1:i len:24 406mips_bltz: src1:i len:24 407mips_bne: src1:i src2:i len:24 408mips_cvtsd: dest:f src1:f len:8 409mips_fbeq: src1:f src2:f len:16 410mips_fbge: src1:f src2:f len:32 411mips_fbge_un: src1:f src2:f len:16 412mips_fbgt: src1:f src2:f len:32 413mips_fbgt_un: src1:f src2:f len:16 414mips_fble: src1:f src2:f len:32 415mips_fble_un: src1:f src2:f len:16 416mips_fblt: src1:f src2:f len:32 417mips_fblt_un: src1:f src2:f len:16 418mips_fbne: src1:f src2:f len:16 419mips_lwc1: dest:f src1:b len:16 420mips_mtc1_s: dest:f src1:i len:8 421mips_mtc1_s2: dest:f src1:i src2:i len:8 422mips_mfc1_s: dest:i src1:f len:8 423mips_mtc1_d: dest:f src1:i len:8 424mips_mfc1_d: dest:i src1:f len:8 425mips_slti: dest:i src1:i len:4 426mips_slt: dest:i src1:i src2:i len:4 427mips_sltiu: dest:i src1:i len:4 428mips_sltu: dest:i src1:i src2:i len:4 429mips_cond_exc_eq: src1:i src2:i len:44 430mips_cond_exc_ge: src1:i src2:i len:44 431mips_cond_exc_gt: src1:i src2:i len:44 432mips_cond_exc_le: src1:i src2:i len:44 433mips_cond_exc_lt: src1:i src2:i len:44 434mips_cond_exc_ne_un: src1:i src2:i len:44 435mips_cond_exc_ge_un: src1:i src2:i len:44 436mips_cond_exc_gt_un: src1:i src2:i len:44 437mips_cond_exc_le_un: src1:i src2:i len:44 438mips_cond_exc_lt_un: src1:i src2:i len:44 439mips_cond_exc_ov: src1:i src2:i len:44 440mips_cond_exc_no: src1:i src2:i len:44 441mips_cond_exc_c: src1:i src2:i len:44 442mips_cond_exc_nc: src1:i src2:i len:44 443mips_cond_exc_ieq: src1:i src2:i len:44 444mips_cond_exc_ige: src1:i src2:i len:44 445mips_cond_exc_igt: src1:i src2:i len:44 446mips_cond_exc_ile: src1:i src2:i len:44 447mips_cond_exc_ilt: src1:i src2:i len:44 448mips_cond_exc_ine_un: src1:i src2:i len:44 449mips_cond_exc_ige_un: src1:i src2:i len:44 450mips_cond_exc_igt_un: src1:i src2:i len:44 451mips_cond_exc_ile_un: src1:i src2:i len:44 452mips_cond_exc_ilt_un: src1:i src2:i len:44 453mips_cond_exc_iov: src1:i src2:i len:44 454mips_cond_exc_ino: src1:i src2:i len:44 455mips_cond_exc_ic: src1:i src2:i len:44 456mips_cond_exc_inc: src1:i src2:i len:44 457 458gc_safe_point: len:0 459