1(**************************************************************************)
2(*                                                                        *)
3(*                                 OCaml                                  *)
4(*                                                                        *)
5(*            Xavier Leroy, projet Gallium, INRIA Rocquencourt            *)
6(*                          Bill O'Farrell, IBM                           *)
7(*                                                                        *)
8(*   Copyright 2015 Institut National de Recherche en Informatique et     *)
9(*     en Automatique.                                                    *)
10(*   Copyright 2015 IBM (Bill O'Farrell with help from Tristan Amini).    *)
11(*                                                                        *)
12(*   All rights reserved.  This file is distributed under the terms of    *)
13(*   the GNU Lesser General Public License version 2.1, with the          *)
14(*   special exception on linking described in the file LICENSE.          *)
15(*                                                                        *)
16(**************************************************************************)
17
18(* Instruction scheduling for the Z processor *)
19
20open Arch
21open Mach
22
23(* The z10 processor is in-order, dual-issue.  It could benefit from some
24   basic-block scheduling, although precise latency information
25   is not available.
26   The z196 and later are out-of-order processors.  Basic-block
27   scheduling probably makes no difference. *)
28
29class scheduler = object
30
31inherit Schedgen.scheduler_generic
32
33(* Latencies (in cycles). Wild guesses.  We multiply all latencies by 2
34   to favor dual-issue. *)
35
36method oper_latency = function
37    Ireload -> 4
38  | Iload(_, _) -> 4
39  | Iconst_float _ -> 4 (* turned into a load *)
40  | Iintop(Imul) -> 10
41  | Iintop_imm(Imul, _) -> 10
42  | Iaddf | Isubf | Imulf -> 8
43  | Idivf -> 40
44  | Ispecific(Imultaddf | Imultsubf) -> 8
45  | _ -> 2
46
47method! reload_retaddr_latency = 4
48
49(* Issue cycles.  Rough approximations. *)
50
51method oper_issue_cycles = function
52  | Ialloc _ -> 4
53  | Iintop(Imulh) -> 15
54  | Iintop(Idiv|Imod) -> 20
55  | Iintop(Icomp _) -> 4
56  | Iintop_imm(Icomp _, _) -> 4
57  | _ -> 1
58
59method! reload_retaddr_issue_cycles = 1
60
61end
62
63let fundecl f = (new scheduler)#schedule_fundecl f
64