1 // REQUIRES: riscv-registered-target
2 // RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +experimental-v \
3 // RUN: -O1 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
4
5 #include <riscv_vector.h>
6
7 vint32m1_t Baz();
8
9 // CHECK-LABEL: @_Z4Testv(
10 // CHECK-NEXT: entry:
11 // CHECK-NEXT: [[A:%.*]] = alloca <vscale x 2 x i32>*, align 8
12 // CHECK-NEXT: [[REF_TMP:%.*]] = alloca <vscale x 2 x i32>, align 4
13 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <vscale x 2 x i32>** [[A]] to i8*
14 // CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP0]]) #[[ATTR3:[0-9]+]]
15 // CHECK-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i32>* [[REF_TMP]] to i8*
16 // CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[TMP1]]) #[[ATTR3]]
17 // CHECK: [[TMP4:%.*]] = bitcast <vscale x 2 x i32>* [[REF_TMP]] to i8*
18 // CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[TMP4]]) #[[ATTR3]]
19 // CHECK-NEXT: [[TMP5:%.*]] = bitcast <vscale x 2 x i32>** [[A]] to i8*
20 // CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP5]]) #[[ATTR3]]
21 //
Test()22 vint32m1_t Test() {
23 const vint32m1_t &a = Baz();
24 return a;
25 }
26