1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
4 
5 #include <riscv_vector.h>
6 
7 //
8 // CHECK-RV64-LABEL: @test_vpopc_m_b1(
9 // CHECK-RV64-NEXT:  entry:
10 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
11 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
12 //
test_vpopc_m_b1(vbool1_t op1,size_t vl)13 unsigned long test_vpopc_m_b1(vbool1_t op1, size_t vl) {
14   return vpopc_m_b1(op1, vl);
15 }
16 
17 //
18 // CHECK-RV64-LABEL: @test_vpopc_m_b2(
19 // CHECK-RV64-NEXT:  entry:
20 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
21 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
22 //
test_vpopc_m_b2(vbool2_t op1,size_t vl)23 unsigned long test_vpopc_m_b2(vbool2_t op1, size_t vl) {
24   return vpopc_m_b2(op1, vl);
25 }
26 
27 //
28 // CHECK-RV64-LABEL: @test_vpopc_m_b4(
29 // CHECK-RV64-NEXT:  entry:
30 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
31 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
32 //
test_vpopc_m_b4(vbool4_t op1,size_t vl)33 unsigned long test_vpopc_m_b4(vbool4_t op1, size_t vl) {
34   return vpopc_m_b4(op1, vl);
35 }
36 
37 //
38 // CHECK-RV64-LABEL: @test_vpopc_m_b8(
39 // CHECK-RV64-NEXT:  entry:
40 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
41 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
42 //
test_vpopc_m_b8(vbool8_t op1,size_t vl)43 unsigned long test_vpopc_m_b8(vbool8_t op1, size_t vl) {
44   return vpopc_m_b8(op1, vl);
45 }
46 
47 //
48 // CHECK-RV64-LABEL: @test_vpopc_m_b16(
49 // CHECK-RV64-NEXT:  entry:
50 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
51 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
52 //
test_vpopc_m_b16(vbool16_t op1,size_t vl)53 unsigned long test_vpopc_m_b16(vbool16_t op1, size_t vl) {
54   return vpopc_m_b16(op1, vl);
55 }
56 
57 //
58 // CHECK-RV64-LABEL: @test_vpopc_m_b32(
59 // CHECK-RV64-NEXT:  entry:
60 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
61 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
62 //
test_vpopc_m_b32(vbool32_t op1,size_t vl)63 unsigned long test_vpopc_m_b32(vbool32_t op1, size_t vl) {
64   return vpopc_m_b32(op1, vl);
65 }
66 
67 //
68 // CHECK-RV64-LABEL: @test_vpopc_m_b64(
69 // CHECK-RV64-NEXT:  entry:
70 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
71 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
72 //
test_vpopc_m_b64(vbool64_t op1,size_t vl)73 unsigned long test_vpopc_m_b64(vbool64_t op1, size_t vl) {
74   return vpopc_m_b64(op1, vl);
75 }
76 
77 //
78 // CHECK-RV64-LABEL: @test_vpopc_m_b1_m(
79 // CHECK-RV64-NEXT:  entry:
80 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.mask.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
81 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
82 //
test_vpopc_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)83 unsigned long test_vpopc_m_b1_m(vbool1_t mask, vbool1_t op1, size_t vl) {
84   return vpopc_m_b1_m(mask, op1, vl);
85 }
86 
87 //
88 // CHECK-RV64-LABEL: @test_vpopc_m_b2_m(
89 // CHECK-RV64-NEXT:  entry:
90 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.mask.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
91 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
92 //
test_vpopc_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)93 unsigned long test_vpopc_m_b2_m(vbool2_t mask, vbool2_t op1, size_t vl) {
94   return vpopc_m_b2_m(mask, op1, vl);
95 }
96 
97 //
98 // CHECK-RV64-LABEL: @test_vpopc_m_b4_m(
99 // CHECK-RV64-NEXT:  entry:
100 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.mask.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
101 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
102 //
test_vpopc_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)103 unsigned long test_vpopc_m_b4_m(vbool4_t mask, vbool4_t op1, size_t vl) {
104   return vpopc_m_b4_m(mask, op1, vl);
105 }
106 
107 //
108 // CHECK-RV64-LABEL: @test_vpopc_m_b8_m(
109 // CHECK-RV64-NEXT:  entry:
110 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.mask.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
111 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
112 //
test_vpopc_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)113 unsigned long test_vpopc_m_b8_m(vbool8_t mask, vbool8_t op1, size_t vl) {
114   return vpopc_m_b8_m(mask, op1, vl);
115 }
116 
117 //
118 // CHECK-RV64-LABEL: @test_vpopc_m_b16_m(
119 // CHECK-RV64-NEXT:  entry:
120 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.mask.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
121 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
122 //
test_vpopc_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)123 unsigned long test_vpopc_m_b16_m(vbool16_t mask, vbool16_t op1, size_t vl) {
124   return vpopc_m_b16_m(mask, op1, vl);
125 }
126 
127 //
128 // CHECK-RV64-LABEL: @test_vpopc_m_b32_m(
129 // CHECK-RV64-NEXT:  entry:
130 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.mask.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
131 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
132 //
test_vpopc_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)133 unsigned long test_vpopc_m_b32_m(vbool32_t mask, vbool32_t op1, size_t vl) {
134   return vpopc_m_b32_m(mask, op1, vl);
135 }
136 
137 //
138 // CHECK-RV64-LABEL: @test_vpopc_m_b64_m(
139 // CHECK-RV64-NEXT:  entry:
140 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vpopc.mask.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
141 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
142 //
test_vpopc_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)143 unsigned long test_vpopc_m_b64_m(vbool64_t mask, vbool64_t op1, size_t vl) {
144   return vpopc_m_b64_m(mask, op1, vl);
145 }
146