1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
9 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5
11 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK6
12 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5| FileCheck %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5
14 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK8
15
16 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10
19 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
20 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12
22 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK13
23 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -DOMP5
24 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK14
25 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -DOMP5 | FileCheck %s --check-prefix=CHECK15
26 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -DOMP5
27 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK16
28
29 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region)
30 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
31 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17
32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
33 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18
34 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
35 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19
36 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
37 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20
38 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5
39 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK21
40 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5
41 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK22
42 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5
43 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK23
44 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5
45 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK24
46
47 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
48 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25
49 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
50 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26
51 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27
53 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
54 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28
55 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -DOMP5
56 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK29
57 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -DOMP5
58 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK30
59 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -DOMP5
60 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -DOMP5 | FileCheck %s --check-prefix=CHECK31
61 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -DOMP5
62 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - -DOMP5 | FileCheck %s --check-prefix=CHECK32
63
64 // expected-no-diagnostics
65 #ifndef HEADER
66 #define HEADER
67
68
without_schedule_clause(float * a,float * b,float * c,float * d)69 void without_schedule_clause(float *a, float *b, float *c, float *d) {
70 #pragma omp target
71 #pragma omp teams
72 #ifdef OMP5
73 #pragma omp distribute simd simdlen(8) aligned(a) if(true)
74 #else
75 #pragma omp distribute simd simdlen(8) aligned(a)
76 #endif // OMP5
77 for (int i = 33; i < 32000000; i += 7) {
78 a[i] = b[i] * c[i] * d[i];
79 }
80 }
81
82 // ... loop body ...
83
84
static_not_chunked(float * a,float * b,float * c,float * d)85 void static_not_chunked(float *a, float *b, float *c, float *d) {
86 #pragma omp target
87 #pragma omp teams
88 #ifdef OMP5
89 #pragma omp distribute simd dist_schedule(static) safelen(32) if(simd: true) nontemporal(a, b)
90 #else
91 #pragma omp distribute simd dist_schedule(static) safelen(32)
92 #endif // OMP5
93 for (int i = 32000000; i > 33; i += -7) {
94 a[i] = b[i] * c[i] * d[i];
95 }
96 }
97
98 // ... loop body ...
99
100
101
static_chunked(float * a,float * b,float * c,float * d)102 void static_chunked(float *a, float *b, float *c, float *d) {
103 #pragma omp target
104 #pragma omp teams
105 #pragma omp distribute simd dist_schedule(static, 5)
106 for (unsigned i = 131071; i <= 2147483647; i += 127) {
107 a[i] = b[i] * c[i] * d[i];
108 }
109 }
110
111 // ... loop body ...
112
test_precond()113 void test_precond() {
114 char a = 0; char i;
115 #pragma omp target
116 #pragma omp teams
117 #ifdef OMP5
118 #pragma omp distribute simd linear(i) if(a) nontemporal(i)
119 #else
120 #pragma omp distribute simd linear(i)
121 #endif // OMP5
122 for(i = a; i < 10; ++i);
123 }
124
125 // a is passed as a parameter to the outlined functions
126 // ..many loads of %0..
127
128 // no templates for now, as these require special handling in target regions and/or declare target
129
130
131 template <typename T>
ftemplate()132 T ftemplate() {
133 short aa = 0;
134
135 #pragma omp target
136 #pragma omp teams
137 #pragma omp distribute simd dist_schedule(static, aa)
138 for (int i = 0; i < 100; i++) {
139 }
140 return T();
141 }
142
fint(void)143 int fint(void) { return ftemplate<int>(); }
144
145 #endif
146
147 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
148 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
149 // CHECK1-NEXT: entry:
150 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
151 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
152 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
153 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
154 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
155 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
156 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
157 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
158 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
159 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
160 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
161 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
162 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
163 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
164 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
165 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
166 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
167 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
168 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
169 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
170 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
171 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
172 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
173 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
174 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
175 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
176 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
177 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
178 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
179 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
180 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
181 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
182 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
183 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
184 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
185 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
186 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
187 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
188 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
189 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
190 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
191 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
192 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
193 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
194 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
195 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
196 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
197 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
198 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
199 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
200 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424)
201 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
202 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
203 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
204 // CHECK1: omp_offload.failed:
205 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
206 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
207 // CHECK1: omp_offload.cont:
208 // CHECK1-NEXT: ret void
209 //
210 //
211 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
212 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] {
213 // CHECK1-NEXT: entry:
214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
215 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
216 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
217 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
218 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
219 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
220 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
221 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
222 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
223 // CHECK1-NEXT: ret void
224 //
225 //
226 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
227 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
228 // CHECK1-NEXT: entry:
229 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
230 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
231 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
232 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
233 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
234 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
235 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
236 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
237 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
238 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
239 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
240 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
241 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
242 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
243 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
244 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
245 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
246 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
247 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
248 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
249 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
250 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
251 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
252 // CHECK1-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
253 // CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
254 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
255 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
256 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
257 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
258 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
259 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
260 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
261 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
262 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
263 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
264 // CHECK1: cond.true:
265 // CHECK1-NEXT: br label [[COND_END:%.*]]
266 // CHECK1: cond.false:
267 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
268 // CHECK1-NEXT: br label [[COND_END]]
269 // CHECK1: cond.end:
270 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
271 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
272 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
273 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
274 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
275 // CHECK1: omp.inner.for.cond:
276 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
277 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
278 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
279 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
280 // CHECK1: omp.inner.for.body:
281 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
282 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
283 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
284 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
285 // CHECK1-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8
286 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
287 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
288 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
289 // CHECK1-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8
290 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8
291 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
292 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
293 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
294 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !8
295 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
296 // CHECK1-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8
297 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
298 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
299 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
300 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
301 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
302 // CHECK1-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8
303 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
304 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
305 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
306 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
307 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
308 // CHECK1: omp.body.continue:
309 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
310 // CHECK1: omp.inner.for.inc:
311 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
312 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
313 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
314 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
315 // CHECK1: omp.inner.for.end:
316 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
317 // CHECK1: omp.loop.exit:
318 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
319 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
320 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
321 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
322 // CHECK1: .omp.final.then:
323 // CHECK1-NEXT: store i32 32000001, i32* [[I]], align 4
324 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
325 // CHECK1: .omp.final.done:
326 // CHECK1-NEXT: ret void
327 //
328 //
329 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
330 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
331 // CHECK1-NEXT: entry:
332 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
333 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
334 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
335 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
336 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
337 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
338 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
339 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
340 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
341 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
342 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
343 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
344 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
345 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
346 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
347 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
348 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
349 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
350 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
351 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
352 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
353 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
354 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
355 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
356 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
357 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
358 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
359 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
360 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
361 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
362 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
363 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
364 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
365 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
366 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
367 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
368 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
369 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
370 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
371 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
372 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
373 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
374 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
375 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
376 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
377 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
378 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
379 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
380 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
381 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
382 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424)
383 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
384 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
385 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
386 // CHECK1: omp_offload.failed:
387 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
388 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
389 // CHECK1: omp_offload.cont:
390 // CHECK1-NEXT: ret void
391 //
392 //
393 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
394 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
395 // CHECK1-NEXT: entry:
396 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
397 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
398 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
399 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
400 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
401 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
402 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
403 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
404 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
405 // CHECK1-NEXT: ret void
406 //
407 //
408 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
409 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
410 // CHECK1-NEXT: entry:
411 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
412 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
413 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
414 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
415 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
416 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
417 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
418 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
419 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
420 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
421 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
422 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
423 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
424 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
425 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
426 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
427 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
428 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
429 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
430 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
431 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
432 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
433 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
434 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
435 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
436 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
437 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
438 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
439 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
440 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
441 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
442 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
443 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
444 // CHECK1: cond.true:
445 // CHECK1-NEXT: br label [[COND_END:%.*]]
446 // CHECK1: cond.false:
447 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
448 // CHECK1-NEXT: br label [[COND_END]]
449 // CHECK1: cond.end:
450 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
451 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
452 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
453 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
454 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
455 // CHECK1: omp.inner.for.cond:
456 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
457 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
458 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
459 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
460 // CHECK1: omp.inner.for.body:
461 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
462 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
463 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
464 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4
465 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8
466 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
467 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
468 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
469 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
470 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
471 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
472 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
473 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
474 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
475 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
476 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
477 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
478 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
479 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
480 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
481 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
482 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8
483 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
484 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
485 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
486 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
487 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
488 // CHECK1: omp.body.continue:
489 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
490 // CHECK1: omp.inner.for.inc:
491 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
492 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
493 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
494 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
495 // CHECK1: omp.inner.for.end:
496 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
497 // CHECK1: omp.loop.exit:
498 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
499 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
500 // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
501 // CHECK1-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
502 // CHECK1: .omp.final.then:
503 // CHECK1-NEXT: store i32 32, i32* [[I]], align 4
504 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
505 // CHECK1: .omp.final.done:
506 // CHECK1-NEXT: ret void
507 //
508 //
509 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
510 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
511 // CHECK1-NEXT: entry:
512 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
513 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
514 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
515 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
516 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
517 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
518 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
519 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
520 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
521 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
522 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
523 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
524 // CHECK1-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
525 // CHECK1-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
526 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
527 // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
528 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
529 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
530 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
531 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
532 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
533 // CHECK1-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
534 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
535 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
536 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
537 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
538 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
539 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
540 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
541 // CHECK1-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
542 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
543 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
544 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
545 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
546 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
547 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
548 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
549 // CHECK1-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
550 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
551 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
552 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
553 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
554 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
555 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
556 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
557 // CHECK1-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
558 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
559 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
560 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
561 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
562 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289)
563 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
564 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
565 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
566 // CHECK1: omp_offload.failed:
567 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
568 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
569 // CHECK1: omp_offload.cont:
570 // CHECK1-NEXT: ret void
571 //
572 //
573 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
574 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
575 // CHECK1-NEXT: entry:
576 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
577 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
578 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
579 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
580 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
581 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
582 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
583 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
584 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
585 // CHECK1-NEXT: ret void
586 //
587 //
588 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
589 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
590 // CHECK1-NEXT: entry:
591 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
592 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
593 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
594 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
595 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
596 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
597 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
598 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
599 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
600 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
601 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
602 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
603 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
604 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
605 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
606 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
607 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
608 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
609 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
610 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
611 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
612 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
613 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
614 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
615 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
616 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
617 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
618 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
619 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
620 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
621 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
622 // CHECK1: omp.dispatch.cond:
623 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
624 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
625 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
626 // CHECK1: cond.true:
627 // CHECK1-NEXT: br label [[COND_END:%.*]]
628 // CHECK1: cond.false:
629 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
630 // CHECK1-NEXT: br label [[COND_END]]
631 // CHECK1: cond.end:
632 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
633 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
634 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
635 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
636 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
637 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
638 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
639 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
640 // CHECK1: omp.dispatch.body:
641 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
642 // CHECK1: omp.inner.for.cond:
643 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
644 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17
645 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
646 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
647 // CHECK1: omp.inner.for.body:
648 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
649 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
650 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
651 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
652 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !17
653 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
654 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
655 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
656 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17
657 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !17
658 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
659 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
660 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
661 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !17
662 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
663 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !17
664 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
665 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
666 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
667 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !17
668 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
669 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !17
670 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
671 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
672 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
673 // CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17
674 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
675 // CHECK1: omp.body.continue:
676 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
677 // CHECK1: omp.inner.for.inc:
678 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
679 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
680 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
681 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
682 // CHECK1: omp.inner.for.end:
683 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
684 // CHECK1: omp.dispatch.inc:
685 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
686 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
687 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
688 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
689 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
690 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
691 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
692 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
693 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
694 // CHECK1: omp.dispatch.end:
695 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
696 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
697 // CHECK1-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
698 // CHECK1-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
699 // CHECK1: .omp.final.then:
700 // CHECK1-NEXT: store i32 -2147483522, i32* [[I]], align 4
701 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
702 // CHECK1: .omp.final.done:
703 // CHECK1-NEXT: ret void
704 //
705 //
706 // CHECK1-LABEL: define {{[^@]+}}@_Z12test_precondv
707 // CHECK1-SAME: () #[[ATTR0]] {
708 // CHECK1-NEXT: entry:
709 // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1
710 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1
711 // CHECK1-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8
712 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
713 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
714 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
715 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
716 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1
717 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
718 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
719 // CHECK1-NEXT: store i8 0, i8* [[A]], align 1
720 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
721 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_CASTED]] to i8*
722 // CHECK1-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
723 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[I_CASTED]], align 8
724 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
725 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8*
726 // CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
727 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
728 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
729 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
730 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
731 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
732 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
733 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
734 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
735 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
736 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
737 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
738 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
739 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
740 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
741 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
742 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
743 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
744 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
745 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
746 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
747 // CHECK1-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
748 // CHECK1-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
749 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
750 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
751 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
752 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
753 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
754 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
755 // CHECK1-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
756 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
757 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
758 // CHECK1-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
759 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]])
760 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
761 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
762 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
763 // CHECK1: omp_offload.failed:
764 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]]
765 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
766 // CHECK1: omp_offload.cont:
767 // CHECK1-NEXT: ret void
768 //
769 //
770 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
771 // CHECK1-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
772 // CHECK1-NEXT: entry:
773 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
774 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
775 // CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
776 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
777 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
778 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
779 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
780 // CHECK1-NEXT: ret void
781 //
782 //
783 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
784 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
785 // CHECK1-NEXT: entry:
786 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
787 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
788 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
789 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
790 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
791 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1
792 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
793 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
794 // CHECK1-NEXT: [[I4:%.*]] = alloca i8, align 1
795 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
796 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
797 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
798 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
799 // CHECK1-NEXT: [[I6:%.*]] = alloca i8, align 1
800 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
801 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
802 // CHECK1-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
803 // CHECK1-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
804 // CHECK1-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
805 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
806 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
807 // CHECK1-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
808 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
809 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
810 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
811 // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
812 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
813 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
814 // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
815 // CHECK1-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
816 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
817 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
818 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
819 // CHECK1-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
820 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
821 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
822 // CHECK1: omp.precond.then:
823 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
824 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
825 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
826 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
827 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
828 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
829 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
830 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
831 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
832 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
833 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
834 // CHECK1-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
835 // CHECK1: cond.true:
836 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
837 // CHECK1-NEXT: br label [[COND_END:%.*]]
838 // CHECK1: cond.false:
839 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
840 // CHECK1-NEXT: br label [[COND_END]]
841 // CHECK1: cond.end:
842 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
843 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
844 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
845 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
846 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
847 // CHECK1: omp.inner.for.cond:
848 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
849 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
850 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
851 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
852 // CHECK1: omp.inner.for.body:
853 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !20
854 // CHECK1-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
855 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
856 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
857 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
858 // CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
859 // CHECK1-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !20
860 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
861 // CHECK1: omp.body.continue:
862 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
863 // CHECK1: omp.inner.for.inc:
864 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
865 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
866 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
867 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
868 // CHECK1: omp.inner.for.end:
869 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
870 // CHECK1: omp.loop.exit:
871 // CHECK1-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
872 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
873 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
874 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
875 // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
876 // CHECK1-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
877 // CHECK1: .omp.final.then:
878 // CHECK1-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
879 // CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
880 // CHECK1-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
881 // CHECK1-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
882 // CHECK1-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
883 // CHECK1-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
884 // CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
885 // CHECK1-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
886 // CHECK1-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
887 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
888 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
889 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
890 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
891 // CHECK1: .omp.final.done:
892 // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
893 // CHECK1: omp.precond.end:
894 // CHECK1-NEXT: ret void
895 //
896 //
897 // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv
898 // CHECK1-SAME: () #[[ATTR0]] {
899 // CHECK1-NEXT: entry:
900 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
901 // CHECK1-NEXT: ret i32 [[CALL]]
902 //
903 //
904 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
905 // CHECK1-SAME: () #[[ATTR0]] comdat {
906 // CHECK1-NEXT: entry:
907 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
908 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
909 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
910 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
911 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
912 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
913 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
914 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
915 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
916 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
917 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
918 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
919 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
920 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
921 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
922 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
923 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
924 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
925 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8
926 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
927 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
928 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100)
929 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
930 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
931 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
932 // CHECK1: omp_offload.failed:
933 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]]
934 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
935 // CHECK1: omp_offload.cont:
936 // CHECK1-NEXT: ret i32 0
937 //
938 //
939 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
940 // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] {
941 // CHECK1-NEXT: entry:
942 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
943 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
944 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
945 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
946 // CHECK1-NEXT: ret void
947 //
948 //
949 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
950 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
951 // CHECK1-NEXT: entry:
952 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
953 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
954 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
955 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
956 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
957 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
958 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
959 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
960 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
961 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
962 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
963 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
964 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
965 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
966 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
967 // CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
968 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
969 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
970 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
971 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
972 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
973 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
974 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
975 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
976 // CHECK1: omp.dispatch.cond:
977 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
978 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
979 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
980 // CHECK1: cond.true:
981 // CHECK1-NEXT: br label [[COND_END:%.*]]
982 // CHECK1: cond.false:
983 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
984 // CHECK1-NEXT: br label [[COND_END]]
985 // CHECK1: cond.end:
986 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
987 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
988 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
989 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
990 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
991 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
992 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
993 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
994 // CHECK1: omp.dispatch.body:
995 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
996 // CHECK1: omp.inner.for.cond:
997 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
998 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
999 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1000 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1001 // CHECK1: omp.inner.for.body:
1002 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1003 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
1004 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1005 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23
1006 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1007 // CHECK1: omp.body.continue:
1008 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1009 // CHECK1: omp.inner.for.inc:
1010 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1011 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
1012 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1013 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
1014 // CHECK1: omp.inner.for.end:
1015 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1016 // CHECK1: omp.dispatch.inc:
1017 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1018 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1019 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
1020 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
1021 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1022 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1023 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
1024 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
1025 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
1026 // CHECK1: omp.dispatch.end:
1027 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1028 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1029 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1030 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1031 // CHECK1: .omp.final.then:
1032 // CHECK1-NEXT: store i32 100, i32* [[I]], align 4
1033 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
1034 // CHECK1: .omp.final.done:
1035 // CHECK1-NEXT: ret void
1036 //
1037 //
1038 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1039 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
1040 // CHECK1-NEXT: entry:
1041 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1042 // CHECK1-NEXT: ret void
1043 //
1044 //
1045 // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
1046 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1047 // CHECK2-NEXT: entry:
1048 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
1049 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
1050 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
1051 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
1052 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1053 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1054 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1055 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1056 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
1057 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
1058 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
1059 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
1060 // CHECK2-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
1061 // CHECK2-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
1062 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
1063 // CHECK2-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
1064 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1065 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
1066 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
1067 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1068 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
1069 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
1070 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1071 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8
1072 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1073 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
1074 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
1075 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1076 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
1077 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
1078 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1079 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8
1080 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1081 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
1082 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
1083 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1084 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
1085 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
1086 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1087 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8
1088 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1089 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
1090 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
1091 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1092 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
1093 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
1094 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1095 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8
1096 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1097 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1098 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424)
1099 // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1100 // CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
1101 // CHECK2-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1102 // CHECK2: omp_offload.failed:
1103 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
1104 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1105 // CHECK2: omp_offload.cont:
1106 // CHECK2-NEXT: ret void
1107 //
1108 //
1109 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
1110 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] {
1111 // CHECK2-NEXT: entry:
1112 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
1113 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
1114 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
1115 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
1116 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
1117 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
1118 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
1119 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
1120 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
1121 // CHECK2-NEXT: ret void
1122 //
1123 //
1124 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
1125 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
1126 // CHECK2-NEXT: entry:
1127 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1128 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1129 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
1130 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
1131 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
1132 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
1133 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1134 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1135 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1136 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1137 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1138 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1139 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1140 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1141 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1142 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
1143 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
1144 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
1145 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
1146 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
1147 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
1148 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
1149 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
1150 // CHECK2-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
1151 // CHECK2-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
1152 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1153 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
1154 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1155 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1156 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1157 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
1158 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1159 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1160 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
1161 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1162 // CHECK2: cond.true:
1163 // CHECK2-NEXT: br label [[COND_END:%.*]]
1164 // CHECK2: cond.false:
1165 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1166 // CHECK2-NEXT: br label [[COND_END]]
1167 // CHECK2: cond.end:
1168 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
1169 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1170 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1171 // CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
1172 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1173 // CHECK2: omp.inner.for.cond:
1174 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
1175 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
1176 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
1177 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1178 // CHECK2: omp.inner.for.body:
1179 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
1180 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
1181 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
1182 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
1183 // CHECK2-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8
1184 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
1185 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
1186 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
1187 // CHECK2-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8
1188 // CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8
1189 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
1190 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
1191 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
1192 // CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !8
1193 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
1194 // CHECK2-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8
1195 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
1196 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
1197 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
1198 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
1199 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
1200 // CHECK2-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8
1201 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
1202 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
1203 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
1204 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
1205 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1206 // CHECK2: omp.body.continue:
1207 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1208 // CHECK2: omp.inner.for.inc:
1209 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
1210 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
1211 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
1212 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
1213 // CHECK2: omp.inner.for.end:
1214 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1215 // CHECK2: omp.loop.exit:
1216 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
1217 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1218 // CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1219 // CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1220 // CHECK2: .omp.final.then:
1221 // CHECK2-NEXT: store i32 32000001, i32* [[I]], align 4
1222 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1223 // CHECK2: .omp.final.done:
1224 // CHECK2-NEXT: ret void
1225 //
1226 //
1227 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
1228 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
1229 // CHECK2-NEXT: entry:
1230 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
1231 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
1232 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
1233 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
1234 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1235 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1236 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1237 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1238 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
1239 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
1240 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
1241 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
1242 // CHECK2-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
1243 // CHECK2-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
1244 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
1245 // CHECK2-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
1246 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1247 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
1248 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
1249 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1250 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
1251 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
1252 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1253 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8
1254 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1255 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
1256 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
1257 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1258 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
1259 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
1260 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1261 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8
1262 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1263 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
1264 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
1265 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1266 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
1267 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
1268 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1269 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8
1270 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1271 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
1272 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
1273 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1274 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
1275 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
1276 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1277 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8
1278 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1279 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1280 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424)
1281 // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1282 // CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
1283 // CHECK2-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1284 // CHECK2: omp_offload.failed:
1285 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
1286 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1287 // CHECK2: omp_offload.cont:
1288 // CHECK2-NEXT: ret void
1289 //
1290 //
1291 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
1292 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
1293 // CHECK2-NEXT: entry:
1294 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
1295 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
1296 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
1297 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
1298 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
1299 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
1300 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
1301 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
1302 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
1303 // CHECK2-NEXT: ret void
1304 //
1305 //
1306 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
1307 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
1308 // CHECK2-NEXT: entry:
1309 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1310 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1311 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
1312 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
1313 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
1314 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
1315 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1316 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1317 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1318 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1319 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1320 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1321 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1322 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1323 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1324 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
1325 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
1326 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
1327 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
1328 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
1329 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
1330 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
1331 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
1332 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1333 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
1334 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1335 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1336 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1337 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1338 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1339 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1340 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
1341 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1342 // CHECK2: cond.true:
1343 // CHECK2-NEXT: br label [[COND_END:%.*]]
1344 // CHECK2: cond.false:
1345 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1346 // CHECK2-NEXT: br label [[COND_END]]
1347 // CHECK2: cond.end:
1348 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1349 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1350 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1351 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1352 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1353 // CHECK2: omp.inner.for.cond:
1354 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1355 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1356 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1357 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1358 // CHECK2: omp.inner.for.body:
1359 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1360 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
1361 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
1362 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4
1363 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8
1364 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
1365 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
1366 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
1367 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
1368 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
1369 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
1370 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
1371 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
1372 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
1373 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
1374 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
1375 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
1376 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
1377 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
1378 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
1379 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
1380 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8
1381 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
1382 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
1383 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
1384 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
1385 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1386 // CHECK2: omp.body.continue:
1387 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1388 // CHECK2: omp.inner.for.inc:
1389 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1390 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
1391 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1392 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
1393 // CHECK2: omp.inner.for.end:
1394 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1395 // CHECK2: omp.loop.exit:
1396 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1397 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1398 // CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
1399 // CHECK2-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1400 // CHECK2: .omp.final.then:
1401 // CHECK2-NEXT: store i32 32, i32* [[I]], align 4
1402 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1403 // CHECK2: .omp.final.done:
1404 // CHECK2-NEXT: ret void
1405 //
1406 //
1407 // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
1408 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
1409 // CHECK2-NEXT: entry:
1410 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
1411 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
1412 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
1413 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
1414 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1415 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1416 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1417 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1418 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
1419 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
1420 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
1421 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
1422 // CHECK2-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
1423 // CHECK2-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
1424 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
1425 // CHECK2-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
1426 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1427 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
1428 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
1429 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1430 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
1431 // CHECK2-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
1432 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1433 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8
1434 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1435 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
1436 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
1437 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1438 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
1439 // CHECK2-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
1440 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1441 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8
1442 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1443 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
1444 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
1445 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1446 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
1447 // CHECK2-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
1448 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1449 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8
1450 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1451 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
1452 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
1453 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1454 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
1455 // CHECK2-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
1456 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1457 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8
1458 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1459 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1460 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289)
1461 // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1462 // CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
1463 // CHECK2-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1464 // CHECK2: omp_offload.failed:
1465 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
1466 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1467 // CHECK2: omp_offload.cont:
1468 // CHECK2-NEXT: ret void
1469 //
1470 //
1471 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
1472 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
1473 // CHECK2-NEXT: entry:
1474 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
1475 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
1476 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
1477 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
1478 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
1479 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
1480 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
1481 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
1482 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
1483 // CHECK2-NEXT: ret void
1484 //
1485 //
1486 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
1487 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
1488 // CHECK2-NEXT: entry:
1489 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1490 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1491 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
1492 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
1493 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
1494 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
1495 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1496 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1497 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1498 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1499 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1500 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1501 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1502 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1503 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1504 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
1505 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
1506 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
1507 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
1508 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
1509 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
1510 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
1511 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
1512 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1513 // CHECK2-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
1514 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1515 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1516 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1517 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1518 // CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
1519 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1520 // CHECK2: omp.dispatch.cond:
1521 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1522 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
1523 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1524 // CHECK2: cond.true:
1525 // CHECK2-NEXT: br label [[COND_END:%.*]]
1526 // CHECK2: cond.false:
1527 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1528 // CHECK2-NEXT: br label [[COND_END]]
1529 // CHECK2: cond.end:
1530 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1531 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1532 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1533 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1534 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1535 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1536 // CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
1537 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1538 // CHECK2: omp.dispatch.body:
1539 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1540 // CHECK2: omp.inner.for.cond:
1541 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
1542 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17
1543 // CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
1544 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1545 // CHECK2: omp.inner.for.body:
1546 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
1547 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
1548 // CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
1549 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
1550 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !17
1551 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
1552 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
1553 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
1554 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17
1555 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !17
1556 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
1557 // CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
1558 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
1559 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !17
1560 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
1561 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !17
1562 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
1563 // CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
1564 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
1565 // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !17
1566 // CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
1567 // CHECK2-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !17
1568 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17
1569 // CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
1570 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
1571 // CHECK2-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17
1572 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1573 // CHECK2: omp.body.continue:
1574 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1575 // CHECK2: omp.inner.for.inc:
1576 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
1577 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
1578 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
1579 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
1580 // CHECK2: omp.inner.for.end:
1581 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1582 // CHECK2: omp.dispatch.inc:
1583 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1584 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1585 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
1586 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
1587 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1588 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1589 // CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
1590 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
1591 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
1592 // CHECK2: omp.dispatch.end:
1593 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1594 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1595 // CHECK2-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
1596 // CHECK2-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1597 // CHECK2: .omp.final.then:
1598 // CHECK2-NEXT: store i32 -2147483522, i32* [[I]], align 4
1599 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1600 // CHECK2: .omp.final.done:
1601 // CHECK2-NEXT: ret void
1602 //
1603 //
1604 // CHECK2-LABEL: define {{[^@]+}}@_Z12test_precondv
1605 // CHECK2-SAME: () #[[ATTR0]] {
1606 // CHECK2-NEXT: entry:
1607 // CHECK2-NEXT: [[A:%.*]] = alloca i8, align 1
1608 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1
1609 // CHECK2-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8
1610 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1611 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
1612 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
1613 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
1614 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1
1615 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1616 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1617 // CHECK2-NEXT: store i8 0, i8* [[A]], align 1
1618 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
1619 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_CASTED]] to i8*
1620 // CHECK2-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
1621 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[I_CASTED]], align 8
1622 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
1623 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8*
1624 // CHECK2-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
1625 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
1626 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1627 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
1628 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
1629 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1630 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
1631 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
1632 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1633 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8
1634 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1635 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1636 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
1637 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1638 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
1639 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
1640 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1641 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8
1642 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1643 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1644 // CHECK2-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
1645 // CHECK2-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
1646 // CHECK2-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1647 // CHECK2-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
1648 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
1649 // CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
1650 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
1651 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
1652 // CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
1653 // CHECK2-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1654 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1655 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
1656 // CHECK2-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
1657 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]])
1658 // CHECK2-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1659 // CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
1660 // CHECK2-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1661 // CHECK2: omp_offload.failed:
1662 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]]
1663 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1664 // CHECK2: omp_offload.cont:
1665 // CHECK2-NEXT: ret void
1666 //
1667 //
1668 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
1669 // CHECK2-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
1670 // CHECK2-NEXT: entry:
1671 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
1672 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1673 // CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
1674 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
1675 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
1676 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
1677 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
1678 // CHECK2-NEXT: ret void
1679 //
1680 //
1681 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
1682 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
1683 // CHECK2-NEXT: entry:
1684 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1685 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1686 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
1687 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
1688 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1689 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1
1690 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1691 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1692 // CHECK2-NEXT: [[I4:%.*]] = alloca i8, align 1
1693 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1694 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1695 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1696 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1697 // CHECK2-NEXT: [[I6:%.*]] = alloca i8, align 1
1698 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1699 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1700 // CHECK2-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
1701 // CHECK2-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
1702 // CHECK2-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
1703 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
1704 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
1705 // CHECK2-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
1706 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1707 // CHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
1708 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
1709 // CHECK2-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
1710 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
1711 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
1712 // CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
1713 // CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
1714 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1715 // CHECK2-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
1716 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1717 // CHECK2-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
1718 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
1719 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1720 // CHECK2: omp.precond.then:
1721 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1722 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1723 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
1724 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1725 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1726 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1727 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1728 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1729 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1730 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1731 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
1732 // CHECK2-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1733 // CHECK2: cond.true:
1734 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1735 // CHECK2-NEXT: br label [[COND_END:%.*]]
1736 // CHECK2: cond.false:
1737 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1738 // CHECK2-NEXT: br label [[COND_END]]
1739 // CHECK2: cond.end:
1740 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1741 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1742 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1743 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1744 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1745 // CHECK2: omp.inner.for.cond:
1746 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
1747 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
1748 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1749 // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1750 // CHECK2: omp.inner.for.body:
1751 // CHECK2-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !20
1752 // CHECK2-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
1753 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
1754 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
1755 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
1756 // CHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
1757 // CHECK2-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !20
1758 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1759 // CHECK2: omp.body.continue:
1760 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1761 // CHECK2: omp.inner.for.inc:
1762 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
1763 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
1764 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
1765 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
1766 // CHECK2: omp.inner.for.end:
1767 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1768 // CHECK2: omp.loop.exit:
1769 // CHECK2-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1770 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
1771 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
1772 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1773 // CHECK2-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
1774 // CHECK2-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1775 // CHECK2: .omp.final.then:
1776 // CHECK2-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1777 // CHECK2-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
1778 // CHECK2-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1779 // CHECK2-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
1780 // CHECK2-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
1781 // CHECK2-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
1782 // CHECK2-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
1783 // CHECK2-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
1784 // CHECK2-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
1785 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
1786 // CHECK2-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
1787 // CHECK2-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
1788 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1789 // CHECK2: .omp.final.done:
1790 // CHECK2-NEXT: br label [[OMP_PRECOND_END]]
1791 // CHECK2: omp.precond.end:
1792 // CHECK2-NEXT: ret void
1793 //
1794 //
1795 // CHECK2-LABEL: define {{[^@]+}}@_Z4fintv
1796 // CHECK2-SAME: () #[[ATTR0]] {
1797 // CHECK2-NEXT: entry:
1798 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
1799 // CHECK2-NEXT: ret i32 [[CALL]]
1800 //
1801 //
1802 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
1803 // CHECK2-SAME: () #[[ATTR0]] comdat {
1804 // CHECK2-NEXT: entry:
1805 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
1806 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1807 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
1808 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
1809 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
1810 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1811 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
1812 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
1813 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1814 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
1815 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1816 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1817 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
1818 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
1819 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1820 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
1821 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
1822 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1823 // CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8
1824 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1825 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1826 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100)
1827 // CHECK2-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1828 // CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
1829 // CHECK2-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1830 // CHECK2: omp_offload.failed:
1831 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]]
1832 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1833 // CHECK2: omp_offload.cont:
1834 // CHECK2-NEXT: ret i32 0
1835 //
1836 //
1837 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
1838 // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] {
1839 // CHECK2-NEXT: entry:
1840 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1841 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
1842 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1843 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
1844 // CHECK2-NEXT: ret void
1845 //
1846 //
1847 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10
1848 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
1849 // CHECK2-NEXT: entry:
1850 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1851 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1852 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
1853 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1854 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1855 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1856 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1857 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1858 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1859 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1860 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1861 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1862 // CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
1863 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
1864 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1865 // CHECK2-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
1866 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1867 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1868 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
1869 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
1870 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1871 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1872 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
1873 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1874 // CHECK2: omp.dispatch.cond:
1875 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1876 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
1877 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1878 // CHECK2: cond.true:
1879 // CHECK2-NEXT: br label [[COND_END:%.*]]
1880 // CHECK2: cond.false:
1881 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1882 // CHECK2-NEXT: br label [[COND_END]]
1883 // CHECK2: cond.end:
1884 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1885 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1886 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1887 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1888 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1889 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1890 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1891 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1892 // CHECK2: omp.dispatch.body:
1893 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1894 // CHECK2: omp.inner.for.cond:
1895 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1896 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
1897 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1898 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1899 // CHECK2: omp.inner.for.body:
1900 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1901 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
1902 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1903 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23
1904 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1905 // CHECK2: omp.body.continue:
1906 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1907 // CHECK2: omp.inner.for.inc:
1908 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1909 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
1910 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
1911 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
1912 // CHECK2: omp.inner.for.end:
1913 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1914 // CHECK2: omp.dispatch.inc:
1915 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1916 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1917 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
1918 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
1919 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1920 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1921 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
1922 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
1923 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
1924 // CHECK2: omp.dispatch.end:
1925 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
1926 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1927 // CHECK2-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1928 // CHECK2-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1929 // CHECK2: .omp.final.then:
1930 // CHECK2-NEXT: store i32 100, i32* [[I]], align 4
1931 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1932 // CHECK2: .omp.final.done:
1933 // CHECK2-NEXT: ret void
1934 //
1935 //
1936 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1937 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
1938 // CHECK2-NEXT: entry:
1939 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
1940 // CHECK2-NEXT: ret void
1941 //
1942 //
1943 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
1944 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1945 // CHECK3-NEXT: entry:
1946 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
1947 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
1948 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
1949 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
1950 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
1951 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
1952 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
1953 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1954 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
1955 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
1956 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
1957 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
1958 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
1959 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
1960 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
1961 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
1962 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1963 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
1964 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
1965 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1966 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
1967 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
1968 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1969 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
1970 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1971 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
1972 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
1973 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1974 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
1975 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
1976 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1977 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
1978 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1979 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
1980 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
1981 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1982 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
1983 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
1984 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1985 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
1986 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1987 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
1988 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
1989 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1990 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
1991 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
1992 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1993 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
1994 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1995 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1996 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424)
1997 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1998 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
1999 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2000 // CHECK3: omp_offload.failed:
2001 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
2002 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2003 // CHECK3: omp_offload.cont:
2004 // CHECK3-NEXT: ret void
2005 //
2006 //
2007 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
2008 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] {
2009 // CHECK3-NEXT: entry:
2010 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
2011 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
2012 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
2013 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
2014 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
2015 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
2016 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
2017 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
2018 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
2019 // CHECK3-NEXT: ret void
2020 //
2021 //
2022 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
2023 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
2024 // CHECK3-NEXT: entry:
2025 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2026 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2027 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
2028 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
2029 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
2030 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
2031 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2032 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2033 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2034 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2035 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2036 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2037 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2038 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2039 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2040 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
2041 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
2042 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
2043 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
2044 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
2045 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
2046 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
2047 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
2048 // CHECK3-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
2049 // CHECK3-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
2050 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2051 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
2052 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2053 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2054 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2055 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
2056 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2057 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2058 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
2059 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2060 // CHECK3: cond.true:
2061 // CHECK3-NEXT: br label [[COND_END:%.*]]
2062 // CHECK3: cond.false:
2063 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2064 // CHECK3-NEXT: br label [[COND_END]]
2065 // CHECK3: cond.end:
2066 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
2067 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2068 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2069 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
2070 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2071 // CHECK3: omp.inner.for.cond:
2072 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
2073 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
2074 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
2075 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2076 // CHECK3: omp.inner.for.body:
2077 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
2078 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
2079 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
2080 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
2081 // CHECK3-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !9
2082 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
2083 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
2084 // CHECK3-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
2085 // CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !9
2086 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
2087 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
2088 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
2089 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
2090 // CHECK3-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !9
2091 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
2092 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
2093 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9
2094 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
2095 // CHECK3-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !9
2096 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
2097 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
2098 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
2099 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2100 // CHECK3: omp.body.continue:
2101 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2102 // CHECK3: omp.inner.for.inc:
2103 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
2104 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
2105 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
2106 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
2107 // CHECK3: omp.inner.for.end:
2108 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2109 // CHECK3: omp.loop.exit:
2110 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
2111 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2112 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
2113 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2114 // CHECK3: .omp.final.then:
2115 // CHECK3-NEXT: store i32 32000001, i32* [[I]], align 4
2116 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2117 // CHECK3: .omp.final.done:
2118 // CHECK3-NEXT: ret void
2119 //
2120 //
2121 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
2122 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
2123 // CHECK3-NEXT: entry:
2124 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
2125 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
2126 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
2127 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
2128 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
2129 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
2130 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
2131 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2132 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
2133 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
2134 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
2135 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
2136 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
2137 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
2138 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
2139 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
2140 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2141 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
2142 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
2143 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2144 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
2145 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
2146 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2147 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
2148 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2149 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
2150 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
2151 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2152 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
2153 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
2154 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2155 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
2156 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2157 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
2158 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
2159 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2160 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
2161 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
2162 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2163 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
2164 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2165 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
2166 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
2167 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2168 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
2169 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
2170 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2171 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
2172 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2173 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2174 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424)
2175 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2176 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
2177 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2178 // CHECK3: omp_offload.failed:
2179 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
2180 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2181 // CHECK3: omp_offload.cont:
2182 // CHECK3-NEXT: ret void
2183 //
2184 //
2185 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
2186 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
2187 // CHECK3-NEXT: entry:
2188 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
2189 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
2190 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
2191 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
2192 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
2193 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
2194 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
2195 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
2196 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
2197 // CHECK3-NEXT: ret void
2198 //
2199 //
2200 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
2201 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
2202 // CHECK3-NEXT: entry:
2203 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2204 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2205 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
2206 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
2207 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
2208 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
2209 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2210 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2211 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2212 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2213 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2214 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2215 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2216 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2217 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2218 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
2219 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
2220 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
2221 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
2222 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
2223 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
2224 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
2225 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
2226 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2227 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
2228 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2229 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2230 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2231 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2232 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2233 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2234 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
2235 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2236 // CHECK3: cond.true:
2237 // CHECK3-NEXT: br label [[COND_END:%.*]]
2238 // CHECK3: cond.false:
2239 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2240 // CHECK3-NEXT: br label [[COND_END]]
2241 // CHECK3: cond.end:
2242 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2243 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2244 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2245 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
2246 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2247 // CHECK3: omp.inner.for.cond:
2248 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2249 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2250 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2251 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2252 // CHECK3: omp.inner.for.body:
2253 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2254 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
2255 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
2256 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4
2257 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4
2258 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
2259 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
2260 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
2261 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
2262 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
2263 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
2264 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
2265 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
2266 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
2267 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
2268 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
2269 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
2270 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
2271 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4
2272 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
2273 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
2274 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
2275 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2276 // CHECK3: omp.body.continue:
2277 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2278 // CHECK3: omp.inner.for.inc:
2279 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2280 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
2281 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2282 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
2283 // CHECK3: omp.inner.for.end:
2284 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2285 // CHECK3: omp.loop.exit:
2286 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
2287 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2288 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
2289 // CHECK3-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2290 // CHECK3: .omp.final.then:
2291 // CHECK3-NEXT: store i32 32, i32* [[I]], align 4
2292 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2293 // CHECK3: .omp.final.done:
2294 // CHECK3-NEXT: ret void
2295 //
2296 //
2297 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
2298 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
2299 // CHECK3-NEXT: entry:
2300 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
2301 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
2302 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
2303 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
2304 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
2305 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
2306 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
2307 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2308 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
2309 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
2310 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
2311 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
2312 // CHECK3-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
2313 // CHECK3-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
2314 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
2315 // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
2316 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2317 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
2318 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
2319 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2320 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
2321 // CHECK3-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
2322 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2323 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
2324 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2325 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
2326 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
2327 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2328 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
2329 // CHECK3-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
2330 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2331 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
2332 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2333 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
2334 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
2335 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2336 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
2337 // CHECK3-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
2338 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2339 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
2340 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2341 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
2342 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
2343 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2344 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
2345 // CHECK3-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
2346 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2347 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
2348 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2349 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2350 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289)
2351 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2352 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
2353 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2354 // CHECK3: omp_offload.failed:
2355 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
2356 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2357 // CHECK3: omp_offload.cont:
2358 // CHECK3-NEXT: ret void
2359 //
2360 //
2361 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
2362 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
2363 // CHECK3-NEXT: entry:
2364 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
2365 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
2366 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
2367 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
2368 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
2369 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
2370 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
2371 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
2372 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
2373 // CHECK3-NEXT: ret void
2374 //
2375 //
2376 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
2377 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
2378 // CHECK3-NEXT: entry:
2379 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2380 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2381 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
2382 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
2383 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
2384 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
2385 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2386 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2387 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2388 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2389 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2390 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2391 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2392 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2393 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2394 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
2395 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
2396 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
2397 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
2398 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
2399 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
2400 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
2401 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
2402 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2403 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
2404 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2405 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2406 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2407 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2408 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
2409 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
2410 // CHECK3: omp.dispatch.cond:
2411 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2412 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
2413 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2414 // CHECK3: cond.true:
2415 // CHECK3-NEXT: br label [[COND_END:%.*]]
2416 // CHECK3: cond.false:
2417 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2418 // CHECK3-NEXT: br label [[COND_END]]
2419 // CHECK3: cond.end:
2420 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2421 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2422 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2423 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
2424 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2425 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2426 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
2427 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2428 // CHECK3: omp.dispatch.body:
2429 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2430 // CHECK3: omp.inner.for.cond:
2431 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2432 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
2433 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
2434 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2435 // CHECK3: omp.inner.for.body:
2436 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2437 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
2438 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
2439 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
2440 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !18
2441 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2442 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
2443 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18
2444 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !18
2445 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2446 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
2447 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !18
2448 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
2449 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !18
2450 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2451 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
2452 // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !18
2453 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
2454 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !18
2455 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
2456 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
2457 // CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
2458 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2459 // CHECK3: omp.body.continue:
2460 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2461 // CHECK3: omp.inner.for.inc:
2462 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2463 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
2464 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
2465 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
2466 // CHECK3: omp.inner.for.end:
2467 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
2468 // CHECK3: omp.dispatch.inc:
2469 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2470 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2471 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
2472 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
2473 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2474 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2475 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
2476 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
2477 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
2478 // CHECK3: omp.dispatch.end:
2479 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
2480 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2481 // CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
2482 // CHECK3-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2483 // CHECK3: .omp.final.then:
2484 // CHECK3-NEXT: store i32 -2147483522, i32* [[I]], align 4
2485 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2486 // CHECK3: .omp.final.done:
2487 // CHECK3-NEXT: ret void
2488 //
2489 //
2490 // CHECK3-LABEL: define {{[^@]+}}@_Z12test_precondv
2491 // CHECK3-SAME: () #[[ATTR0]] {
2492 // CHECK3-NEXT: entry:
2493 // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1
2494 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1
2495 // CHECK3-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4
2496 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2497 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
2498 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
2499 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
2500 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1
2501 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2502 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2503 // CHECK3-NEXT: store i8 0, i8* [[A]], align 1
2504 // CHECK3-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
2505 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[I_CASTED]] to i8*
2506 // CHECK3-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
2507 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_CASTED]], align 4
2508 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
2509 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
2510 // CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
2511 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
2512 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2513 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
2514 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
2515 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2516 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
2517 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
2518 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2519 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
2520 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2521 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
2522 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
2523 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2524 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
2525 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
2526 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2527 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
2528 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2529 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2530 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
2531 // CHECK3-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
2532 // CHECK3-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2533 // CHECK3-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
2534 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
2535 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
2536 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
2537 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
2538 // CHECK3-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
2539 // CHECK3-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
2540 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2541 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
2542 // CHECK3-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
2543 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]])
2544 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2545 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2546 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2547 // CHECK3: omp_offload.failed:
2548 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]]
2549 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2550 // CHECK3: omp_offload.cont:
2551 // CHECK3-NEXT: ret void
2552 //
2553 //
2554 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
2555 // CHECK3-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
2556 // CHECK3-NEXT: entry:
2557 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
2558 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2559 // CHECK3-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
2560 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2561 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
2562 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
2563 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
2564 // CHECK3-NEXT: ret void
2565 //
2566 //
2567 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
2568 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
2569 // CHECK3-NEXT: entry:
2570 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2571 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2572 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
2573 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
2574 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2575 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1
2576 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2577 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2578 // CHECK3-NEXT: [[I4:%.*]] = alloca i8, align 1
2579 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2580 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2581 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2582 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2583 // CHECK3-NEXT: [[I6:%.*]] = alloca i8, align 1
2584 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2585 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2586 // CHECK3-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
2587 // CHECK3-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
2588 // CHECK3-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
2589 // CHECK3-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
2590 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
2591 // CHECK3-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
2592 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2593 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
2594 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
2595 // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
2596 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
2597 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
2598 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
2599 // CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
2600 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2601 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
2602 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2603 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
2604 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
2605 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2606 // CHECK3: omp.precond.then:
2607 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2608 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
2609 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
2610 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2611 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2612 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2613 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
2614 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2615 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2616 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
2617 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
2618 // CHECK3-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2619 // CHECK3: cond.true:
2620 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
2621 // CHECK3-NEXT: br label [[COND_END:%.*]]
2622 // CHECK3: cond.false:
2623 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2624 // CHECK3-NEXT: br label [[COND_END]]
2625 // CHECK3: cond.end:
2626 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2627 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2628 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2629 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
2630 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2631 // CHECK3: omp.inner.for.cond:
2632 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2633 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
2634 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
2635 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2636 // CHECK3: omp.inner.for.body:
2637 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
2638 // CHECK3-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
2639 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2640 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
2641 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
2642 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
2643 // CHECK3-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
2644 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2645 // CHECK3: omp.body.continue:
2646 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2647 // CHECK3: omp.inner.for.inc:
2648 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2649 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
2650 // CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2651 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
2652 // CHECK3: omp.inner.for.end:
2653 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2654 // CHECK3: omp.loop.exit:
2655 // CHECK3-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2656 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
2657 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
2658 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2659 // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
2660 // CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2661 // CHECK3: .omp.final.then:
2662 // CHECK3-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2663 // CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
2664 // CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
2665 // CHECK3-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
2666 // CHECK3-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
2667 // CHECK3-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
2668 // CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
2669 // CHECK3-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
2670 // CHECK3-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
2671 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
2672 // CHECK3-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
2673 // CHECK3-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
2674 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2675 // CHECK3: .omp.final.done:
2676 // CHECK3-NEXT: br label [[OMP_PRECOND_END]]
2677 // CHECK3: omp.precond.end:
2678 // CHECK3-NEXT: ret void
2679 //
2680 //
2681 // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv
2682 // CHECK3-SAME: () #[[ATTR0]] {
2683 // CHECK3-NEXT: entry:
2684 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
2685 // CHECK3-NEXT: ret i32 [[CALL]]
2686 //
2687 //
2688 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
2689 // CHECK3-SAME: () #[[ATTR0]] comdat {
2690 // CHECK3-NEXT: entry:
2691 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
2692 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
2693 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
2694 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
2695 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
2696 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2697 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
2698 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
2699 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2700 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
2701 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2702 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2703 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
2704 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
2705 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2706 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
2707 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
2708 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2709 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4
2710 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2711 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2712 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100)
2713 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2714 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
2715 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2716 // CHECK3: omp_offload.failed:
2717 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]]
2718 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2719 // CHECK3: omp_offload.cont:
2720 // CHECK3-NEXT: ret i32 0
2721 //
2722 //
2723 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
2724 // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] {
2725 // CHECK3-NEXT: entry:
2726 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2727 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
2728 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2729 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
2730 // CHECK3-NEXT: ret void
2731 //
2732 //
2733 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10
2734 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
2735 // CHECK3-NEXT: entry:
2736 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2737 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2738 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
2739 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2740 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2741 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2742 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2743 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2744 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2745 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2746 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2747 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2748 // CHECK3-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
2749 // CHECK3-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
2750 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2751 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
2752 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2753 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2754 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
2755 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2756 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2757 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2758 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
2759 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
2760 // CHECK3: omp.dispatch.cond:
2761 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2762 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
2763 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2764 // CHECK3: cond.true:
2765 // CHECK3-NEXT: br label [[COND_END:%.*]]
2766 // CHECK3: cond.false:
2767 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2768 // CHECK3-NEXT: br label [[COND_END]]
2769 // CHECK3: cond.end:
2770 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2771 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2772 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2773 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2774 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2775 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2776 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2777 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2778 // CHECK3: omp.dispatch.body:
2779 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2780 // CHECK3: omp.inner.for.cond:
2781 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2782 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
2783 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2784 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2785 // CHECK3: omp.inner.for.body:
2786 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2787 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
2788 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2789 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
2790 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2791 // CHECK3: omp.body.continue:
2792 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2793 // CHECK3: omp.inner.for.inc:
2794 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2795 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
2796 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
2797 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
2798 // CHECK3: omp.inner.for.end:
2799 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
2800 // CHECK3: omp.dispatch.inc:
2801 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2802 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2803 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
2804 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
2805 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2806 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2807 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
2808 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
2809 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
2810 // CHECK3: omp.dispatch.end:
2811 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
2812 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2813 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
2814 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2815 // CHECK3: .omp.final.then:
2816 // CHECK3-NEXT: store i32 100, i32* [[I]], align 4
2817 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2818 // CHECK3: .omp.final.done:
2819 // CHECK3-NEXT: ret void
2820 //
2821 //
2822 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2823 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
2824 // CHECK3-NEXT: entry:
2825 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
2826 // CHECK3-NEXT: ret void
2827 //
2828 //
2829 // CHECK4-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
2830 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
2831 // CHECK4-NEXT: entry:
2832 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
2833 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
2834 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
2835 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
2836 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
2837 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
2838 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
2839 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2840 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
2841 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
2842 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
2843 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
2844 // CHECK4-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
2845 // CHECK4-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
2846 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
2847 // CHECK4-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
2848 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2849 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
2850 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
2851 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2852 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
2853 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
2854 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2855 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4
2856 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2857 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
2858 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
2859 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2860 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
2861 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
2862 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2863 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4
2864 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2865 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
2866 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
2867 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2868 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
2869 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
2870 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2871 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4
2872 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2873 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
2874 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
2875 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2876 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
2877 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
2878 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2879 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4
2880 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2881 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2882 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424)
2883 // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2884 // CHECK4-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
2885 // CHECK4-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2886 // CHECK4: omp_offload.failed:
2887 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
2888 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
2889 // CHECK4: omp_offload.cont:
2890 // CHECK4-NEXT: ret void
2891 //
2892 //
2893 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
2894 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] {
2895 // CHECK4-NEXT: entry:
2896 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
2897 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
2898 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
2899 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
2900 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
2901 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
2902 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
2903 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
2904 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
2905 // CHECK4-NEXT: ret void
2906 //
2907 //
2908 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
2909 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
2910 // CHECK4-NEXT: entry:
2911 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2912 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2913 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
2914 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
2915 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
2916 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
2917 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2918 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2919 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2920 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2921 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2922 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2923 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2924 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2925 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2926 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
2927 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
2928 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
2929 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
2930 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
2931 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
2932 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
2933 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
2934 // CHECK4-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
2935 // CHECK4-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
2936 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2937 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
2938 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2939 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2940 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2941 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
2942 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2943 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2944 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
2945 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2946 // CHECK4: cond.true:
2947 // CHECK4-NEXT: br label [[COND_END:%.*]]
2948 // CHECK4: cond.false:
2949 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2950 // CHECK4-NEXT: br label [[COND_END]]
2951 // CHECK4: cond.end:
2952 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
2953 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2954 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2955 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
2956 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2957 // CHECK4: omp.inner.for.cond:
2958 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
2959 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
2960 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
2961 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2962 // CHECK4: omp.inner.for.body:
2963 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
2964 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
2965 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
2966 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
2967 // CHECK4-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !9
2968 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
2969 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
2970 // CHECK4-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
2971 // CHECK4-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !9
2972 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
2973 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
2974 // CHECK4-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
2975 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
2976 // CHECK4-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !9
2977 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
2978 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
2979 // CHECK4-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9
2980 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
2981 // CHECK4-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !9
2982 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
2983 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
2984 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
2985 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2986 // CHECK4: omp.body.continue:
2987 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2988 // CHECK4: omp.inner.for.inc:
2989 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
2990 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
2991 // CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
2992 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
2993 // CHECK4: omp.inner.for.end:
2994 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2995 // CHECK4: omp.loop.exit:
2996 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
2997 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2998 // CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
2999 // CHECK4-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3000 // CHECK4: .omp.final.then:
3001 // CHECK4-NEXT: store i32 32000001, i32* [[I]], align 4
3002 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
3003 // CHECK4: .omp.final.done:
3004 // CHECK4-NEXT: ret void
3005 //
3006 //
3007 // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
3008 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
3009 // CHECK4-NEXT: entry:
3010 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3011 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3012 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3013 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3014 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3015 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3016 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3017 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3018 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3019 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3020 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3021 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3022 // CHECK4-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
3023 // CHECK4-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
3024 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
3025 // CHECK4-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
3026 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3027 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
3028 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
3029 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3030 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
3031 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
3032 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3033 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4
3034 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3035 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
3036 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
3037 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3038 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
3039 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
3040 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3041 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4
3042 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3043 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
3044 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
3045 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3046 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
3047 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
3048 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3049 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4
3050 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3051 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
3052 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
3053 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3054 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
3055 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
3056 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3057 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4
3058 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3059 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3060 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424)
3061 // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3062 // CHECK4-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
3063 // CHECK4-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3064 // CHECK4: omp_offload.failed:
3065 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
3066 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3067 // CHECK4: omp_offload.cont:
3068 // CHECK4-NEXT: ret void
3069 //
3070 //
3071 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
3072 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
3073 // CHECK4-NEXT: entry:
3074 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3075 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3076 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3077 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3078 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3079 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3080 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3081 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3082 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
3083 // CHECK4-NEXT: ret void
3084 //
3085 //
3086 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
3087 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
3088 // CHECK4-NEXT: entry:
3089 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3090 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3091 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
3092 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
3093 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
3094 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
3095 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3096 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3097 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3098 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3099 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3100 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3101 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
3102 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3103 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3104 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
3105 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
3106 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
3107 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
3108 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
3109 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
3110 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
3111 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
3112 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3113 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
3114 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3115 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3116 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3117 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3118 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3119 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3120 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
3121 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3122 // CHECK4: cond.true:
3123 // CHECK4-NEXT: br label [[COND_END:%.*]]
3124 // CHECK4: cond.false:
3125 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3126 // CHECK4-NEXT: br label [[COND_END]]
3127 // CHECK4: cond.end:
3128 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3129 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3130 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3131 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
3132 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3133 // CHECK4: omp.inner.for.cond:
3134 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3135 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3136 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3137 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3138 // CHECK4: omp.inner.for.body:
3139 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3140 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
3141 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
3142 // CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4
3143 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4
3144 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
3145 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
3146 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
3147 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
3148 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
3149 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
3150 // CHECK4-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
3151 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
3152 // CHECK4-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
3153 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
3154 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
3155 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
3156 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
3157 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4
3158 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
3159 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
3160 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
3161 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3162 // CHECK4: omp.body.continue:
3163 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3164 // CHECK4: omp.inner.for.inc:
3165 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3166 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
3167 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3168 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
3169 // CHECK4: omp.inner.for.end:
3170 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3171 // CHECK4: omp.loop.exit:
3172 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3173 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3174 // CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
3175 // CHECK4-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3176 // CHECK4: .omp.final.then:
3177 // CHECK4-NEXT: store i32 32, i32* [[I]], align 4
3178 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
3179 // CHECK4: .omp.final.done:
3180 // CHECK4-NEXT: ret void
3181 //
3182 //
3183 // CHECK4-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
3184 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
3185 // CHECK4-NEXT: entry:
3186 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3187 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3188 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3189 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3190 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3191 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3192 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3193 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3194 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3195 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3196 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3197 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3198 // CHECK4-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
3199 // CHECK4-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
3200 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
3201 // CHECK4-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
3202 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3203 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
3204 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
3205 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3206 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
3207 // CHECK4-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
3208 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3209 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4
3210 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3211 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
3212 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
3213 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3214 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
3215 // CHECK4-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
3216 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3217 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4
3218 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3219 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
3220 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
3221 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3222 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
3223 // CHECK4-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
3224 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3225 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4
3226 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3227 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
3228 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
3229 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3230 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
3231 // CHECK4-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
3232 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3233 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4
3234 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3235 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3236 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289)
3237 // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3238 // CHECK4-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
3239 // CHECK4-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3240 // CHECK4: omp_offload.failed:
3241 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
3242 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3243 // CHECK4: omp_offload.cont:
3244 // CHECK4-NEXT: ret void
3245 //
3246 //
3247 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
3248 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
3249 // CHECK4-NEXT: entry:
3250 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
3251 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
3252 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
3253 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
3254 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
3255 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
3256 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
3257 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
3258 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
3259 // CHECK4-NEXT: ret void
3260 //
3261 //
3262 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
3263 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
3264 // CHECK4-NEXT: entry:
3265 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3266 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3267 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
3268 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
3269 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
3270 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
3271 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3272 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3273 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3274 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3275 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3276 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3277 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
3278 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3279 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3280 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
3281 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
3282 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
3283 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
3284 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
3285 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
3286 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
3287 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
3288 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3289 // CHECK4-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
3290 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3291 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3292 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3293 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3294 // CHECK4-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
3295 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
3296 // CHECK4: omp.dispatch.cond:
3297 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3298 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
3299 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3300 // CHECK4: cond.true:
3301 // CHECK4-NEXT: br label [[COND_END:%.*]]
3302 // CHECK4: cond.false:
3303 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3304 // CHECK4-NEXT: br label [[COND_END]]
3305 // CHECK4: cond.end:
3306 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3307 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3308 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3309 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
3310 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3311 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3312 // CHECK4-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
3313 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3314 // CHECK4: omp.dispatch.body:
3315 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3316 // CHECK4: omp.inner.for.cond:
3317 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
3318 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
3319 // CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
3320 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3321 // CHECK4: omp.inner.for.body:
3322 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
3323 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
3324 // CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
3325 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
3326 // CHECK4-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !18
3327 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
3328 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
3329 // CHECK4-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18
3330 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !18
3331 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
3332 // CHECK4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
3333 // CHECK4-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !18
3334 // CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
3335 // CHECK4-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !18
3336 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
3337 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
3338 // CHECK4-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !18
3339 // CHECK4-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
3340 // CHECK4-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !18
3341 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
3342 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
3343 // CHECK4-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
3344 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3345 // CHECK4: omp.body.continue:
3346 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3347 // CHECK4: omp.inner.for.inc:
3348 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
3349 // CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
3350 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
3351 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
3352 // CHECK4: omp.inner.for.end:
3353 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
3354 // CHECK4: omp.dispatch.inc:
3355 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3356 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3357 // CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
3358 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
3359 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3360 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3361 // CHECK4-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
3362 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
3363 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
3364 // CHECK4: omp.dispatch.end:
3365 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3366 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3367 // CHECK4-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
3368 // CHECK4-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3369 // CHECK4: .omp.final.then:
3370 // CHECK4-NEXT: store i32 -2147483522, i32* [[I]], align 4
3371 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
3372 // CHECK4: .omp.final.done:
3373 // CHECK4-NEXT: ret void
3374 //
3375 //
3376 // CHECK4-LABEL: define {{[^@]+}}@_Z12test_precondv
3377 // CHECK4-SAME: () #[[ATTR0]] {
3378 // CHECK4-NEXT: entry:
3379 // CHECK4-NEXT: [[A:%.*]] = alloca i8, align 1
3380 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1
3381 // CHECK4-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4
3382 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3383 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
3384 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
3385 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
3386 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1
3387 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3388 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3389 // CHECK4-NEXT: store i8 0, i8* [[A]], align 1
3390 // CHECK4-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
3391 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[I_CASTED]] to i8*
3392 // CHECK4-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
3393 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_CASTED]], align 4
3394 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
3395 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
3396 // CHECK4-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
3397 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
3398 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3399 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
3400 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
3401 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3402 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
3403 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
3404 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3405 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4
3406 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3407 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
3408 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
3409 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3410 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
3411 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
3412 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3413 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4
3414 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3415 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3416 // CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
3417 // CHECK4-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
3418 // CHECK4-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3419 // CHECK4-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
3420 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
3421 // CHECK4-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
3422 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
3423 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
3424 // CHECK4-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
3425 // CHECK4-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
3426 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3427 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
3428 // CHECK4-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
3429 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]])
3430 // CHECK4-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3431 // CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
3432 // CHECK4-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3433 // CHECK4: omp_offload.failed:
3434 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]]
3435 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3436 // CHECK4: omp_offload.cont:
3437 // CHECK4-NEXT: ret void
3438 //
3439 //
3440 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
3441 // CHECK4-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
3442 // CHECK4-NEXT: entry:
3443 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
3444 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3445 // CHECK4-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
3446 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3447 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
3448 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
3449 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
3450 // CHECK4-NEXT: ret void
3451 //
3452 //
3453 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7
3454 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
3455 // CHECK4-NEXT: entry:
3456 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3457 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3458 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
3459 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
3460 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3461 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1
3462 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3463 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3464 // CHECK4-NEXT: [[I4:%.*]] = alloca i8, align 1
3465 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3466 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3467 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3468 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3469 // CHECK4-NEXT: [[I6:%.*]] = alloca i8, align 1
3470 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3471 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3472 // CHECK4-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
3473 // CHECK4-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
3474 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
3475 // CHECK4-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
3476 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
3477 // CHECK4-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
3478 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3479 // CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
3480 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
3481 // CHECK4-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
3482 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
3483 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
3484 // CHECK4-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
3485 // CHECK4-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
3486 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3487 // CHECK4-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
3488 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3489 // CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
3490 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
3491 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3492 // CHECK4: omp.precond.then:
3493 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3494 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
3495 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
3496 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3497 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3498 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3499 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
3500 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3501 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3502 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
3503 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
3504 // CHECK4-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3505 // CHECK4: cond.true:
3506 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
3507 // CHECK4-NEXT: br label [[COND_END:%.*]]
3508 // CHECK4: cond.false:
3509 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3510 // CHECK4-NEXT: br label [[COND_END]]
3511 // CHECK4: cond.end:
3512 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
3513 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3514 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3515 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
3516 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3517 // CHECK4: omp.inner.for.cond:
3518 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
3519 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
3520 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
3521 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3522 // CHECK4: omp.inner.for.body:
3523 // CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
3524 // CHECK4-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
3525 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
3526 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
3527 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
3528 // CHECK4-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
3529 // CHECK4-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
3530 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3531 // CHECK4: omp.body.continue:
3532 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3533 // CHECK4: omp.inner.for.inc:
3534 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
3535 // CHECK4-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
3536 // CHECK4-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
3537 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
3538 // CHECK4: omp.inner.for.end:
3539 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3540 // CHECK4: omp.loop.exit:
3541 // CHECK4-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3542 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
3543 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
3544 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3545 // CHECK4-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
3546 // CHECK4-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3547 // CHECK4: .omp.final.then:
3548 // CHECK4-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3549 // CHECK4-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
3550 // CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
3551 // CHECK4-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
3552 // CHECK4-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
3553 // CHECK4-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
3554 // CHECK4-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
3555 // CHECK4-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
3556 // CHECK4-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
3557 // CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
3558 // CHECK4-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
3559 // CHECK4-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
3560 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
3561 // CHECK4: .omp.final.done:
3562 // CHECK4-NEXT: br label [[OMP_PRECOND_END]]
3563 // CHECK4: omp.precond.end:
3564 // CHECK4-NEXT: ret void
3565 //
3566 //
3567 // CHECK4-LABEL: define {{[^@]+}}@_Z4fintv
3568 // CHECK4-SAME: () #[[ATTR0]] {
3569 // CHECK4-NEXT: entry:
3570 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
3571 // CHECK4-NEXT: ret i32 [[CALL]]
3572 //
3573 //
3574 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
3575 // CHECK4-SAME: () #[[ATTR0]] comdat {
3576 // CHECK4-NEXT: entry:
3577 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
3578 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3579 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
3580 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
3581 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
3582 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3583 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
3584 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
3585 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3586 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
3587 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3588 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3589 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
3590 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
3591 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3592 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
3593 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
3594 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3595 // CHECK4-NEXT: store i8* null, i8** [[TMP6]], align 4
3596 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3597 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3598 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100)
3599 // CHECK4-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3600 // CHECK4-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
3601 // CHECK4-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3602 // CHECK4: omp_offload.failed:
3603 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]]
3604 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3605 // CHECK4: omp_offload.cont:
3606 // CHECK4-NEXT: ret i32 0
3607 //
3608 //
3609 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
3610 // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] {
3611 // CHECK4-NEXT: entry:
3612 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3613 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
3614 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3615 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
3616 // CHECK4-NEXT: ret void
3617 //
3618 //
3619 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10
3620 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
3621 // CHECK4-NEXT: entry:
3622 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3623 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3624 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
3625 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3626 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3627 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3628 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3629 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3630 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3631 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
3632 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3633 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3634 // CHECK4-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
3635 // CHECK4-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
3636 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3637 // CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
3638 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3639 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3640 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
3641 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
3642 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3643 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
3644 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
3645 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
3646 // CHECK4: omp.dispatch.cond:
3647 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3648 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
3649 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3650 // CHECK4: cond.true:
3651 // CHECK4-NEXT: br label [[COND_END:%.*]]
3652 // CHECK4: cond.false:
3653 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3654 // CHECK4-NEXT: br label [[COND_END]]
3655 // CHECK4: cond.end:
3656 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3657 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3658 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3659 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
3660 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3661 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3662 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
3663 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3664 // CHECK4: omp.dispatch.body:
3665 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3666 // CHECK4: omp.inner.for.cond:
3667 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
3668 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
3669 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3670 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3671 // CHECK4: omp.inner.for.body:
3672 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
3673 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
3674 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3675 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
3676 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3677 // CHECK4: omp.body.continue:
3678 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3679 // CHECK4: omp.inner.for.inc:
3680 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
3681 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
3682 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
3683 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
3684 // CHECK4: omp.inner.for.end:
3685 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
3686 // CHECK4: omp.dispatch.inc:
3687 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3688 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3689 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
3690 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
3691 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3692 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3693 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
3694 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
3695 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
3696 // CHECK4: omp.dispatch.end:
3697 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
3698 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3699 // CHECK4-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
3700 // CHECK4-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3701 // CHECK4: .omp.final.then:
3702 // CHECK4-NEXT: store i32 100, i32* [[I]], align 4
3703 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
3704 // CHECK4: .omp.final.done:
3705 // CHECK4-NEXT: ret void
3706 //
3707 //
3708 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3709 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] {
3710 // CHECK4-NEXT: entry:
3711 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
3712 // CHECK4-NEXT: ret void
3713 //
3714 //
3715 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
3716 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
3717 // CHECK5-NEXT: entry:
3718 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
3719 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
3720 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
3721 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
3722 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
3723 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
3724 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
3725 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
3726 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
3727 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
3728 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
3729 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
3730 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
3731 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
3732 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
3733 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
3734 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3735 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
3736 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
3737 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3738 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
3739 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
3740 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3741 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8
3742 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3743 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
3744 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
3745 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3746 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
3747 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
3748 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3749 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8
3750 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3751 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
3752 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
3753 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3754 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
3755 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
3756 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3757 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8
3758 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3759 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
3760 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
3761 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3762 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
3763 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
3764 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
3765 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8
3766 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3767 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3768 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424)
3769 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3770 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
3771 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3772 // CHECK5: omp_offload.failed:
3773 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
3774 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
3775 // CHECK5: omp_offload.cont:
3776 // CHECK5-NEXT: ret void
3777 //
3778 //
3779 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
3780 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] {
3781 // CHECK5-NEXT: entry:
3782 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
3783 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
3784 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
3785 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
3786 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
3787 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
3788 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
3789 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
3790 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
3791 // CHECK5-NEXT: ret void
3792 //
3793 //
3794 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
3795 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
3796 // CHECK5-NEXT: entry:
3797 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3798 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3799 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
3800 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
3801 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
3802 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
3803 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3804 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
3805 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3806 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3807 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3808 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3809 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
3810 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3811 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3812 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
3813 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
3814 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
3815 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
3816 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
3817 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
3818 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
3819 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
3820 // CHECK5-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
3821 // CHECK5-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
3822 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3823 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
3824 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3825 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3826 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3827 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
3828 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3829 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3830 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
3831 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3832 // CHECK5: cond.true:
3833 // CHECK5-NEXT: br label [[COND_END:%.*]]
3834 // CHECK5: cond.false:
3835 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3836 // CHECK5-NEXT: br label [[COND_END]]
3837 // CHECK5: cond.end:
3838 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
3839 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3840 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3841 // CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
3842 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3843 // CHECK5: omp.inner.for.cond:
3844 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
3845 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
3846 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
3847 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3848 // CHECK5: omp.inner.for.body:
3849 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
3850 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
3851 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
3852 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
3853 // CHECK5-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8
3854 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
3855 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
3856 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
3857 // CHECK5-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8
3858 // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8
3859 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
3860 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
3861 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
3862 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !8
3863 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
3864 // CHECK5-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8
3865 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
3866 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
3867 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
3868 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
3869 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
3870 // CHECK5-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8
3871 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
3872 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
3873 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
3874 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
3875 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3876 // CHECK5: omp.body.continue:
3877 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3878 // CHECK5: omp.inner.for.inc:
3879 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
3880 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
3881 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
3882 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
3883 // CHECK5: omp.inner.for.end:
3884 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3885 // CHECK5: omp.loop.exit:
3886 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
3887 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3888 // CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
3889 // CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3890 // CHECK5: .omp.final.then:
3891 // CHECK5-NEXT: store i32 32000001, i32* [[I]], align 4
3892 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
3893 // CHECK5: .omp.final.done:
3894 // CHECK5-NEXT: ret void
3895 //
3896 //
3897 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
3898 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
3899 // CHECK5-NEXT: entry:
3900 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
3901 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
3902 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
3903 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
3904 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
3905 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
3906 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
3907 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
3908 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
3909 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
3910 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
3911 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
3912 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
3913 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
3914 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
3915 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
3916 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3917 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
3918 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
3919 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3920 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
3921 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
3922 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3923 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8
3924 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3925 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
3926 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
3927 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3928 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
3929 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
3930 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3931 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8
3932 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3933 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
3934 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
3935 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3936 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
3937 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
3938 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3939 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8
3940 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3941 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
3942 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
3943 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3944 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
3945 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
3946 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
3947 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8
3948 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3949 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3950 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424)
3951 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3952 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
3953 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3954 // CHECK5: omp_offload.failed:
3955 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
3956 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
3957 // CHECK5: omp_offload.cont:
3958 // CHECK5-NEXT: ret void
3959 //
3960 //
3961 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
3962 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
3963 // CHECK5-NEXT: entry:
3964 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
3965 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
3966 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
3967 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
3968 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
3969 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
3970 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
3971 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
3972 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
3973 // CHECK5-NEXT: ret void
3974 //
3975 //
3976 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
3977 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
3978 // CHECK5-NEXT: entry:
3979 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3980 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3981 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
3982 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
3983 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
3984 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
3985 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3986 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
3987 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3988 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3989 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3990 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3991 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
3992 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3993 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3994 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
3995 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
3996 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
3997 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
3998 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
3999 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
4000 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
4001 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
4002 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4003 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
4004 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4005 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4006 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4007 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
4008 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4009 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4010 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
4011 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4012 // CHECK5: cond.true:
4013 // CHECK5-NEXT: br label [[COND_END:%.*]]
4014 // CHECK5: cond.false:
4015 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4016 // CHECK5-NEXT: br label [[COND_END]]
4017 // CHECK5: cond.end:
4018 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
4019 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4020 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4021 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
4022 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4023 // CHECK5: omp.inner.for.cond:
4024 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4025 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4026 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
4027 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4028 // CHECK5: omp.inner.for.body:
4029 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4030 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
4031 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
4032 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4
4033 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !nontemporal !15
4034 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
4035 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
4036 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
4037 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
4038 // CHECK5-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
4039 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
4040 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
4041 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
4042 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
4043 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
4044 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
4045 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
4046 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
4047 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
4048 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
4049 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
4050 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !nontemporal !15
4051 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
4052 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
4053 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
4054 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
4055 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4056 // CHECK5: omp.body.continue:
4057 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4058 // CHECK5: omp.inner.for.inc:
4059 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4060 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
4061 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4062 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
4063 // CHECK5: omp.inner.for.end:
4064 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4065 // CHECK5: omp.loop.exit:
4066 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
4067 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4068 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
4069 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4070 // CHECK5: .omp.final.then:
4071 // CHECK5-NEXT: store i32 32, i32* [[I]], align 4
4072 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
4073 // CHECK5: .omp.final.done:
4074 // CHECK5-NEXT: ret void
4075 //
4076 //
4077 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
4078 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
4079 // CHECK5-NEXT: entry:
4080 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4081 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4082 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4083 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4084 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
4085 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
4086 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
4087 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
4088 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4089 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4090 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4091 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4092 // CHECK5-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
4093 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
4094 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
4095 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
4096 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4097 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
4098 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
4099 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4100 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
4101 // CHECK5-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
4102 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4103 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8
4104 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4105 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
4106 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
4107 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4108 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
4109 // CHECK5-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
4110 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
4111 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8
4112 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4113 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
4114 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
4115 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4116 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
4117 // CHECK5-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
4118 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
4119 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8
4120 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4121 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
4122 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
4123 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4124 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
4125 // CHECK5-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
4126 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
4127 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8
4128 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4129 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4130 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289)
4131 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
4132 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
4133 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4134 // CHECK5: omp_offload.failed:
4135 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
4136 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
4137 // CHECK5: omp_offload.cont:
4138 // CHECK5-NEXT: ret void
4139 //
4140 //
4141 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
4142 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
4143 // CHECK5-NEXT: entry:
4144 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4145 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4146 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4147 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4148 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4149 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4150 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4151 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4152 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
4153 // CHECK5-NEXT: ret void
4154 //
4155 //
4156 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4
4157 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
4158 // CHECK5-NEXT: entry:
4159 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4160 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4161 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
4162 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
4163 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
4164 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
4165 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4166 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
4167 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4168 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4169 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4170 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4171 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
4172 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4173 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4174 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
4175 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
4176 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
4177 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
4178 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
4179 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
4180 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
4181 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
4182 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4183 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
4184 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4185 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4186 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4187 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
4188 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
4189 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
4190 // CHECK5: omp.dispatch.cond:
4191 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4192 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
4193 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4194 // CHECK5: cond.true:
4195 // CHECK5-NEXT: br label [[COND_END:%.*]]
4196 // CHECK5: cond.false:
4197 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4198 // CHECK5-NEXT: br label [[COND_END]]
4199 // CHECK5: cond.end:
4200 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
4201 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4202 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4203 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
4204 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4205 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4206 // CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
4207 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4208 // CHECK5: omp.dispatch.body:
4209 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4210 // CHECK5: omp.inner.for.cond:
4211 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
4212 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
4213 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
4214 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4215 // CHECK5: omp.inner.for.body:
4216 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
4217 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
4218 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
4219 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
4220 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !18
4221 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
4222 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
4223 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
4224 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18
4225 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !18
4226 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
4227 // CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
4228 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
4229 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !18
4230 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
4231 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !18
4232 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
4233 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
4234 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
4235 // CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
4236 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
4237 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !18
4238 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
4239 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
4240 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
4241 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
4242 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4243 // CHECK5: omp.body.continue:
4244 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4245 // CHECK5: omp.inner.for.inc:
4246 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
4247 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
4248 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
4249 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
4250 // CHECK5: omp.inner.for.end:
4251 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
4252 // CHECK5: omp.dispatch.inc:
4253 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4254 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4255 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
4256 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
4257 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4258 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4259 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
4260 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
4261 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
4262 // CHECK5: omp.dispatch.end:
4263 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
4264 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4265 // CHECK5-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
4266 // CHECK5-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4267 // CHECK5: .omp.final.then:
4268 // CHECK5-NEXT: store i32 -2147483522, i32* [[I]], align 4
4269 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
4270 // CHECK5: .omp.final.done:
4271 // CHECK5-NEXT: ret void
4272 //
4273 //
4274 // CHECK5-LABEL: define {{[^@]+}}@_Z12test_precondv
4275 // CHECK5-SAME: () #[[ATTR0]] {
4276 // CHECK5-NEXT: entry:
4277 // CHECK5-NEXT: [[A:%.*]] = alloca i8, align 1
4278 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1
4279 // CHECK5-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8
4280 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
4281 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
4282 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
4283 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
4284 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1
4285 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4286 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4287 // CHECK5-NEXT: store i8 0, i8* [[A]], align 1
4288 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
4289 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[I_CASTED]] to i8*
4290 // CHECK5-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
4291 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[I_CASTED]], align 8
4292 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
4293 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8*
4294 // CHECK5-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
4295 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
4296 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4297 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
4298 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
4299 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4300 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
4301 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
4302 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4303 // CHECK5-NEXT: store i8* null, i8** [[TMP8]], align 8
4304 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4305 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
4306 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
4307 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4308 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
4309 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
4310 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
4311 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8
4312 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4313 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4314 // CHECK5-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
4315 // CHECK5-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
4316 // CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4317 // CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
4318 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
4319 // CHECK5-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
4320 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
4321 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
4322 // CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
4323 // CHECK5-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
4324 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4325 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
4326 // CHECK5-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
4327 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]])
4328 // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
4329 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
4330 // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4331 // CHECK5: omp_offload.failed:
4332 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]]
4333 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
4334 // CHECK5: omp_offload.cont:
4335 // CHECK5-NEXT: ret void
4336 //
4337 //
4338 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
4339 // CHECK5-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
4340 // CHECK5-NEXT: entry:
4341 // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
4342 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4343 // CHECK5-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
4344 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
4345 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
4346 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
4347 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
4348 // CHECK5-NEXT: ret void
4349 //
4350 //
4351 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7
4352 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
4353 // CHECK5-NEXT: entry:
4354 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4355 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4356 // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
4357 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
4358 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4359 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1
4360 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4361 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4362 // CHECK5-NEXT: [[I4:%.*]] = alloca i8, align 1
4363 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4364 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4365 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4366 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4367 // CHECK5-NEXT: [[I6:%.*]] = alloca i8, align 1
4368 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4369 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4370 // CHECK5-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
4371 // CHECK5-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
4372 // CHECK5-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
4373 // CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
4374 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
4375 // CHECK5-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
4376 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4377 // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
4378 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
4379 // CHECK5-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
4380 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
4381 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
4382 // CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
4383 // CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
4384 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4385 // CHECK5-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
4386 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4387 // CHECK5-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
4388 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
4389 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
4390 // CHECK5: omp.precond.then:
4391 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4392 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
4393 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
4394 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4395 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4396 // CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4397 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
4398 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4399 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4400 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
4401 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
4402 // CHECK5-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4403 // CHECK5: cond.true:
4404 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
4405 // CHECK5-NEXT: br label [[COND_END:%.*]]
4406 // CHECK5: cond.false:
4407 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4408 // CHECK5-NEXT: br label [[COND_END]]
4409 // CHECK5: cond.end:
4410 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4411 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4412 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4413 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
4414 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
4415 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
4416 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4417 // CHECK5: omp_if.then:
4418 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4419 // CHECK5: omp.inner.for.cond:
4420 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
4421 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
4422 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
4423 // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4424 // CHECK5: omp.inner.for.body:
4425 // CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
4426 // CHECK5-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
4427 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
4428 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
4429 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
4430 // CHECK5-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
4431 // CHECK5-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21
4432 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4433 // CHECK5: omp.body.continue:
4434 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4435 // CHECK5: omp.inner.for.inc:
4436 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
4437 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
4438 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
4439 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
4440 // CHECK5: omp.inner.for.end:
4441 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
4442 // CHECK5: omp_if.else:
4443 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
4444 // CHECK5: omp.inner.for.cond13:
4445 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4446 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4447 // CHECK5-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
4448 // CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
4449 // CHECK5: omp.inner.for.body15:
4450 // CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4451 // CHECK5-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
4452 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4453 // CHECK5-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
4454 // CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
4455 // CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
4456 // CHECK5-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
4457 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
4458 // CHECK5: omp.body.continue20:
4459 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
4460 // CHECK5: omp.inner.for.inc21:
4461 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4462 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
4463 // CHECK5-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
4464 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP24:![0-9]+]]
4465 // CHECK5: omp.inner.for.end23:
4466 // CHECK5-NEXT: br label [[OMP_IF_END]]
4467 // CHECK5: omp_if.end:
4468 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4469 // CHECK5: omp.loop.exit:
4470 // CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4471 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
4472 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
4473 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4474 // CHECK5-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4475 // CHECK5-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4476 // CHECK5: .omp.final.then:
4477 // CHECK5-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4478 // CHECK5-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
4479 // CHECK5-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4480 // CHECK5-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
4481 // CHECK5-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
4482 // CHECK5-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
4483 // CHECK5-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
4484 // CHECK5-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
4485 // CHECK5-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
4486 // CHECK5-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
4487 // CHECK5-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
4488 // CHECK5-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
4489 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
4490 // CHECK5: .omp.final.done:
4491 // CHECK5-NEXT: br label [[OMP_PRECOND_END]]
4492 // CHECK5: omp.precond.end:
4493 // CHECK5-NEXT: ret void
4494 //
4495 //
4496 // CHECK5-LABEL: define {{[^@]+}}@_Z4fintv
4497 // CHECK5-SAME: () #[[ATTR0]] {
4498 // CHECK5-NEXT: entry:
4499 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
4500 // CHECK5-NEXT: ret i32 [[CALL]]
4501 //
4502 //
4503 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
4504 // CHECK5-SAME: () #[[ATTR0]] comdat {
4505 // CHECK5-NEXT: entry:
4506 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2
4507 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
4508 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
4509 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
4510 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
4511 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
4512 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2
4513 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
4514 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
4515 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
4516 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
4517 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4518 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
4519 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
4520 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4521 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
4522 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
4523 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4524 // CHECK5-NEXT: store i8* null, i8** [[TMP6]], align 8
4525 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4526 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4527 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100)
4528 // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
4529 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
4530 // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4531 // CHECK5: omp_offload.failed:
4532 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]]
4533 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
4534 // CHECK5: omp_offload.cont:
4535 // CHECK5-NEXT: ret i32 0
4536 //
4537 //
4538 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
4539 // CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] {
4540 // CHECK5-NEXT: entry:
4541 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4542 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
4543 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4544 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
4545 // CHECK5-NEXT: ret void
4546 //
4547 //
4548 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10
4549 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
4550 // CHECK5-NEXT: entry:
4551 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4552 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4553 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
4554 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4555 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
4556 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4557 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4558 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4559 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4560 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
4561 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4562 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4563 // CHECK5-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
4564 // CHECK5-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
4565 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4566 // CHECK5-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
4567 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4568 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4569 // CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
4570 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4571 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4572 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
4573 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
4574 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
4575 // CHECK5: omp.dispatch.cond:
4576 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4577 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
4578 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4579 // CHECK5: cond.true:
4580 // CHECK5-NEXT: br label [[COND_END:%.*]]
4581 // CHECK5: cond.false:
4582 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4583 // CHECK5-NEXT: br label [[COND_END]]
4584 // CHECK5: cond.end:
4585 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
4586 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4587 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4588 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
4589 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4590 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4591 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
4592 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4593 // CHECK5: omp.dispatch.body:
4594 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4595 // CHECK5: omp.inner.for.cond:
4596 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
4597 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
4598 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
4599 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4600 // CHECK5: omp.inner.for.body:
4601 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
4602 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
4603 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4604 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26
4605 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4606 // CHECK5: omp.body.continue:
4607 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4608 // CHECK5: omp.inner.for.inc:
4609 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
4610 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
4611 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
4612 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
4613 // CHECK5: omp.inner.for.end:
4614 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
4615 // CHECK5: omp.dispatch.inc:
4616 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4617 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4618 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
4619 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
4620 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4621 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4622 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
4623 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
4624 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
4625 // CHECK5: omp.dispatch.end:
4626 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
4627 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4628 // CHECK5-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
4629 // CHECK5-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4630 // CHECK5: .omp.final.then:
4631 // CHECK5-NEXT: store i32 100, i32* [[I]], align 4
4632 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]]
4633 // CHECK5: .omp.final.done:
4634 // CHECK5-NEXT: ret void
4635 //
4636 //
4637 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4638 // CHECK5-SAME: () #[[ATTR4:[0-9]+]] {
4639 // CHECK5-NEXT: entry:
4640 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
4641 // CHECK5-NEXT: ret void
4642 //
4643 //
4644 // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
4645 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
4646 // CHECK6-NEXT: entry:
4647 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4648 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4649 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4650 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4651 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
4652 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
4653 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
4654 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
4655 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4656 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4657 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4658 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4659 // CHECK6-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
4660 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
4661 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
4662 // CHECK6-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
4663 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4664 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
4665 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
4666 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4667 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
4668 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
4669 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4670 // CHECK6-NEXT: store i8* null, i8** [[TMP8]], align 8
4671 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4672 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
4673 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
4674 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4675 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
4676 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
4677 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
4678 // CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8
4679 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4680 // CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
4681 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
4682 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4683 // CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
4684 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
4685 // CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
4686 // CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8
4687 // CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4688 // CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
4689 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
4690 // CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4691 // CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
4692 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
4693 // CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
4694 // CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8
4695 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4696 // CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4697 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424)
4698 // CHECK6-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
4699 // CHECK6-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
4700 // CHECK6-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4701 // CHECK6: omp_offload.failed:
4702 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
4703 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
4704 // CHECK6: omp_offload.cont:
4705 // CHECK6-NEXT: ret void
4706 //
4707 //
4708 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
4709 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] {
4710 // CHECK6-NEXT: entry:
4711 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4712 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4713 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4714 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4715 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4716 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4717 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4718 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4719 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
4720 // CHECK6-NEXT: ret void
4721 //
4722 //
4723 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
4724 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
4725 // CHECK6-NEXT: entry:
4726 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4727 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4728 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
4729 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
4730 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
4731 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
4732 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4733 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
4734 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4735 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4736 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4737 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4738 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
4739 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4740 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4741 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
4742 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
4743 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
4744 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
4745 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
4746 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
4747 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
4748 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
4749 // CHECK6-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
4750 // CHECK6-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
4751 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4752 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
4753 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4754 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4755 // CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4756 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
4757 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4758 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4759 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
4760 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4761 // CHECK6: cond.true:
4762 // CHECK6-NEXT: br label [[COND_END:%.*]]
4763 // CHECK6: cond.false:
4764 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4765 // CHECK6-NEXT: br label [[COND_END]]
4766 // CHECK6: cond.end:
4767 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
4768 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4769 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4770 // CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
4771 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4772 // CHECK6: omp.inner.for.cond:
4773 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
4774 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8
4775 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
4776 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4777 // CHECK6: omp.inner.for.body:
4778 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
4779 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
4780 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
4781 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
4782 // CHECK6-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8
4783 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
4784 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
4785 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
4786 // CHECK6-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8
4787 // CHECK6-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8
4788 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
4789 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
4790 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
4791 // CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !8
4792 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
4793 // CHECK6-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8
4794 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
4795 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
4796 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
4797 // CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
4798 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
4799 // CHECK6-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8
4800 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8
4801 // CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
4802 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
4803 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
4804 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4805 // CHECK6: omp.body.continue:
4806 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4807 // CHECK6: omp.inner.for.inc:
4808 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
4809 // CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
4810 // CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
4811 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
4812 // CHECK6: omp.inner.for.end:
4813 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4814 // CHECK6: omp.loop.exit:
4815 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
4816 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4817 // CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
4818 // CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4819 // CHECK6: .omp.final.then:
4820 // CHECK6-NEXT: store i32 32000001, i32* [[I]], align 4
4821 // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
4822 // CHECK6: .omp.final.done:
4823 // CHECK6-NEXT: ret void
4824 //
4825 //
4826 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
4827 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
4828 // CHECK6-NEXT: entry:
4829 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4830 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4831 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4832 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4833 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
4834 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
4835 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
4836 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
4837 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4838 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4839 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4840 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4841 // CHECK6-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
4842 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
4843 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
4844 // CHECK6-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
4845 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4846 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
4847 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
4848 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4849 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
4850 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
4851 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4852 // CHECK6-NEXT: store i8* null, i8** [[TMP8]], align 8
4853 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4854 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
4855 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
4856 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4857 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
4858 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
4859 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
4860 // CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8
4861 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4862 // CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
4863 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
4864 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4865 // CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
4866 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
4867 // CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
4868 // CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8
4869 // CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4870 // CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
4871 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
4872 // CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4873 // CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
4874 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
4875 // CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
4876 // CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8
4877 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4878 // CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4879 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424)
4880 // CHECK6-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
4881 // CHECK6-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
4882 // CHECK6-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4883 // CHECK6: omp_offload.failed:
4884 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
4885 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
4886 // CHECK6: omp_offload.cont:
4887 // CHECK6-NEXT: ret void
4888 //
4889 //
4890 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
4891 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
4892 // CHECK6-NEXT: entry:
4893 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
4894 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
4895 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
4896 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
4897 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
4898 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
4899 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
4900 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
4901 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
4902 // CHECK6-NEXT: ret void
4903 //
4904 //
4905 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1
4906 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
4907 // CHECK6-NEXT: entry:
4908 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4909 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4910 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
4911 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
4912 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
4913 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
4914 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4915 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
4916 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4917 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4918 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4919 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4920 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
4921 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4922 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4923 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
4924 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
4925 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
4926 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
4927 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
4928 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
4929 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
4930 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
4931 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4932 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
4933 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4934 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4935 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4936 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
4937 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4938 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4939 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
4940 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4941 // CHECK6: cond.true:
4942 // CHECK6-NEXT: br label [[COND_END:%.*]]
4943 // CHECK6: cond.false:
4944 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4945 // CHECK6-NEXT: br label [[COND_END]]
4946 // CHECK6: cond.end:
4947 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
4948 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4949 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4950 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
4951 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4952 // CHECK6: omp.inner.for.cond:
4953 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4954 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4955 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
4956 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4957 // CHECK6: omp.inner.for.body:
4958 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4959 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
4960 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
4961 // CHECK6-NEXT: store i32 [[SUB]], i32* [[I]], align 4
4962 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !nontemporal !15
4963 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
4964 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
4965 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
4966 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
4967 // CHECK6-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
4968 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
4969 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
4970 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
4971 // CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
4972 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
4973 // CHECK6-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
4974 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
4975 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
4976 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
4977 // CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
4978 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
4979 // CHECK6-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !nontemporal !15
4980 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
4981 // CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
4982 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
4983 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
4984 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4985 // CHECK6: omp.body.continue:
4986 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4987 // CHECK6: omp.inner.for.inc:
4988 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4989 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
4990 // CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4991 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
4992 // CHECK6: omp.inner.for.end:
4993 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4994 // CHECK6: omp.loop.exit:
4995 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
4996 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4997 // CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
4998 // CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4999 // CHECK6: .omp.final.then:
5000 // CHECK6-NEXT: store i32 32, i32* [[I]], align 4
5001 // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
5002 // CHECK6: .omp.final.done:
5003 // CHECK6-NEXT: ret void
5004 //
5005 //
5006 // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
5007 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
5008 // CHECK6-NEXT: entry:
5009 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
5010 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
5011 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
5012 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
5013 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
5014 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
5015 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
5016 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
5017 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
5018 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
5019 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
5020 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
5021 // CHECK6-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 8
5022 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8
5023 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 8
5024 // CHECK6-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 8
5025 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5026 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
5027 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP5]], align 8
5028 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5029 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
5030 // CHECK6-NEXT: store float* [[TMP0]], float** [[TMP7]], align 8
5031 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5032 // CHECK6-NEXT: store i8* null, i8** [[TMP8]], align 8
5033 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5034 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
5035 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP10]], align 8
5036 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5037 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
5038 // CHECK6-NEXT: store float* [[TMP1]], float** [[TMP12]], align 8
5039 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
5040 // CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8
5041 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5042 // CHECK6-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
5043 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP15]], align 8
5044 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5045 // CHECK6-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
5046 // CHECK6-NEXT: store float* [[TMP2]], float** [[TMP17]], align 8
5047 // CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
5048 // CHECK6-NEXT: store i8* null, i8** [[TMP18]], align 8
5049 // CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
5050 // CHECK6-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
5051 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP20]], align 8
5052 // CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
5053 // CHECK6-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
5054 // CHECK6-NEXT: store float* [[TMP3]], float** [[TMP22]], align 8
5055 // CHECK6-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
5056 // CHECK6-NEXT: store i8* null, i8** [[TMP23]], align 8
5057 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5058 // CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5059 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289)
5060 // CHECK6-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
5061 // CHECK6-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
5062 // CHECK6-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5063 // CHECK6: omp_offload.failed:
5064 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
5065 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
5066 // CHECK6: omp_offload.cont:
5067 // CHECK6-NEXT: ret void
5068 //
5069 //
5070 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
5071 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
5072 // CHECK6-NEXT: entry:
5073 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
5074 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
5075 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
5076 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
5077 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
5078 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
5079 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
5080 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
5081 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
5082 // CHECK6-NEXT: ret void
5083 //
5084 //
5085 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4
5086 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
5087 // CHECK6-NEXT: entry:
5088 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5089 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5090 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
5091 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
5092 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
5093 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
5094 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5095 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
5096 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5097 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5098 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5099 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5100 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
5101 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5102 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5103 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
5104 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
5105 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
5106 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
5107 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
5108 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
5109 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
5110 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
5111 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5112 // CHECK6-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
5113 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5114 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5115 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5116 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5117 // CHECK6-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
5118 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
5119 // CHECK6: omp.dispatch.cond:
5120 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5121 // CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
5122 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5123 // CHECK6: cond.true:
5124 // CHECK6-NEXT: br label [[COND_END:%.*]]
5125 // CHECK6: cond.false:
5126 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5127 // CHECK6-NEXT: br label [[COND_END]]
5128 // CHECK6: cond.end:
5129 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5130 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5131 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5132 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
5133 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5134 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5135 // CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
5136 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5137 // CHECK6: omp.dispatch.body:
5138 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5139 // CHECK6: omp.inner.for.cond:
5140 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5141 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
5142 // CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
5143 // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5144 // CHECK6: omp.inner.for.body:
5145 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5146 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
5147 // CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
5148 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
5149 // CHECK6-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !18
5150 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
5151 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
5152 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
5153 // CHECK6-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18
5154 // CHECK6-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !18
5155 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
5156 // CHECK6-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
5157 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
5158 // CHECK6-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !18
5159 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
5160 // CHECK6-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !18
5161 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
5162 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
5163 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
5164 // CHECK6-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
5165 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
5166 // CHECK6-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !18
5167 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
5168 // CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
5169 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
5170 // CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
5171 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5172 // CHECK6: omp.body.continue:
5173 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5174 // CHECK6: omp.inner.for.inc:
5175 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5176 // CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
5177 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
5178 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
5179 // CHECK6: omp.inner.for.end:
5180 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
5181 // CHECK6: omp.dispatch.inc:
5182 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5183 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5184 // CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
5185 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
5186 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5187 // CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5188 // CHECK6-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
5189 // CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
5190 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
5191 // CHECK6: omp.dispatch.end:
5192 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
5193 // CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5194 // CHECK6-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
5195 // CHECK6-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5196 // CHECK6: .omp.final.then:
5197 // CHECK6-NEXT: store i32 -2147483522, i32* [[I]], align 4
5198 // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
5199 // CHECK6: .omp.final.done:
5200 // CHECK6-NEXT: ret void
5201 //
5202 //
5203 // CHECK6-LABEL: define {{[^@]+}}@_Z12test_precondv
5204 // CHECK6-SAME: () #[[ATTR0]] {
5205 // CHECK6-NEXT: entry:
5206 // CHECK6-NEXT: [[A:%.*]] = alloca i8, align 1
5207 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1
5208 // CHECK6-NEXT: [[I_CASTED:%.*]] = alloca i64, align 8
5209 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
5210 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
5211 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
5212 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
5213 // CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1
5214 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5215 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5216 // CHECK6-NEXT: store i8 0, i8* [[A]], align 1
5217 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
5218 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[I_CASTED]] to i8*
5219 // CHECK6-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
5220 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[I_CASTED]], align 8
5221 // CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
5222 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i8*
5223 // CHECK6-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
5224 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
5225 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5226 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
5227 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
5228 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5229 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
5230 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
5231 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5232 // CHECK6-NEXT: store i8* null, i8** [[TMP8]], align 8
5233 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5234 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
5235 // CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
5236 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5237 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
5238 // CHECK6-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
5239 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
5240 // CHECK6-NEXT: store i8* null, i8** [[TMP13]], align 8
5241 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5242 // CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5243 // CHECK6-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
5244 // CHECK6-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
5245 // CHECK6-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5246 // CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
5247 // CHECK6-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
5248 // CHECK6-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
5249 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
5250 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
5251 // CHECK6-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
5252 // CHECK6-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
5253 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5254 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
5255 // CHECK6-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
5256 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]])
5257 // CHECK6-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
5258 // CHECK6-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
5259 // CHECK6-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5260 // CHECK6: omp_offload.failed:
5261 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i64 [[TMP1]], i64 [[TMP3]]) #[[ATTR3]]
5262 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
5263 // CHECK6: omp_offload.cont:
5264 // CHECK6-NEXT: ret void
5265 //
5266 //
5267 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
5268 // CHECK6-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
5269 // CHECK6-NEXT: entry:
5270 // CHECK6-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
5271 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
5272 // CHECK6-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
5273 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
5274 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
5275 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
5276 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
5277 // CHECK6-NEXT: ret void
5278 //
5279 //
5280 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7
5281 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
5282 // CHECK6-NEXT: entry:
5283 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5284 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5285 // CHECK6-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
5286 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
5287 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5288 // CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1
5289 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5290 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
5291 // CHECK6-NEXT: [[I4:%.*]] = alloca i8, align 1
5292 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5293 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5294 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5295 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5296 // CHECK6-NEXT: [[I6:%.*]] = alloca i8, align 1
5297 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5298 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5299 // CHECK6-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
5300 // CHECK6-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
5301 // CHECK6-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
5302 // CHECK6-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
5303 // CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
5304 // CHECK6-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
5305 // CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5306 // CHECK6-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
5307 // CHECK6-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
5308 // CHECK6-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
5309 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
5310 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
5311 // CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
5312 // CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
5313 // CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5314 // CHECK6-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
5315 // CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5316 // CHECK6-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
5317 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
5318 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
5319 // CHECK6: omp.precond.then:
5320 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5321 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
5322 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
5323 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5324 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5325 // CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5326 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
5327 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5328 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5329 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
5330 // CHECK6-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
5331 // CHECK6-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5332 // CHECK6: cond.true:
5333 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
5334 // CHECK6-NEXT: br label [[COND_END:%.*]]
5335 // CHECK6: cond.false:
5336 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5337 // CHECK6-NEXT: br label [[COND_END]]
5338 // CHECK6: cond.end:
5339 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
5340 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5341 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5342 // CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
5343 // CHECK6-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
5344 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
5345 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5346 // CHECK6: omp_if.then:
5347 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5348 // CHECK6: omp.inner.for.cond:
5349 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
5350 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
5351 // CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
5352 // CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5353 // CHECK6: omp.inner.for.body:
5354 // CHECK6-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
5355 // CHECK6-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
5356 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
5357 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
5358 // CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
5359 // CHECK6-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
5360 // CHECK6-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21
5361 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5362 // CHECK6: omp.body.continue:
5363 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5364 // CHECK6: omp.inner.for.inc:
5365 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
5366 // CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
5367 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
5368 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
5369 // CHECK6: omp.inner.for.end:
5370 // CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
5371 // CHECK6: omp_if.else:
5372 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
5373 // CHECK6: omp.inner.for.cond13:
5374 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5375 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5376 // CHECK6-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
5377 // CHECK6-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
5378 // CHECK6: omp.inner.for.body15:
5379 // CHECK6-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5380 // CHECK6-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
5381 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5382 // CHECK6-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
5383 // CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
5384 // CHECK6-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
5385 // CHECK6-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
5386 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
5387 // CHECK6: omp.body.continue20:
5388 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
5389 // CHECK6: omp.inner.for.inc21:
5390 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5391 // CHECK6-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
5392 // CHECK6-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
5393 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP24:![0-9]+]]
5394 // CHECK6: omp.inner.for.end23:
5395 // CHECK6-NEXT: br label [[OMP_IF_END]]
5396 // CHECK6: omp_if.end:
5397 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5398 // CHECK6: omp.loop.exit:
5399 // CHECK6-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5400 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
5401 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
5402 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5403 // CHECK6-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
5404 // CHECK6-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5405 // CHECK6: .omp.final.then:
5406 // CHECK6-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5407 // CHECK6-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
5408 // CHECK6-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5409 // CHECK6-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
5410 // CHECK6-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
5411 // CHECK6-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
5412 // CHECK6-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
5413 // CHECK6-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
5414 // CHECK6-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
5415 // CHECK6-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
5416 // CHECK6-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
5417 // CHECK6-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
5418 // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
5419 // CHECK6: .omp.final.done:
5420 // CHECK6-NEXT: br label [[OMP_PRECOND_END]]
5421 // CHECK6: omp.precond.end:
5422 // CHECK6-NEXT: ret void
5423 //
5424 //
5425 // CHECK6-LABEL: define {{[^@]+}}@_Z4fintv
5426 // CHECK6-SAME: () #[[ATTR0]] {
5427 // CHECK6-NEXT: entry:
5428 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
5429 // CHECK6-NEXT: ret i32 [[CALL]]
5430 //
5431 //
5432 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
5433 // CHECK6-SAME: () #[[ATTR0]] comdat {
5434 // CHECK6-NEXT: entry:
5435 // CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2
5436 // CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
5437 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
5438 // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
5439 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
5440 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
5441 // CHECK6-NEXT: store i16 0, i16* [[AA]], align 2
5442 // CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
5443 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5444 // CHECK6-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
5445 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5446 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5447 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
5448 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
5449 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5450 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
5451 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
5452 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5453 // CHECK6-NEXT: store i8* null, i8** [[TMP6]], align 8
5454 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5455 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5456 // CHECK6-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100)
5457 // CHECK6-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
5458 // CHECK6-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
5459 // CHECK6-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5460 // CHECK6: omp_offload.failed:
5461 // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i64 [[TMP1]]) #[[ATTR3]]
5462 // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]]
5463 // CHECK6: omp_offload.cont:
5464 // CHECK6-NEXT: ret i32 0
5465 //
5466 //
5467 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
5468 // CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] {
5469 // CHECK6-NEXT: entry:
5470 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
5471 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
5472 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5473 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
5474 // CHECK6-NEXT: ret void
5475 //
5476 //
5477 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10
5478 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
5479 // CHECK6-NEXT: entry:
5480 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5481 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5482 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
5483 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5484 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
5485 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5486 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5487 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5488 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5489 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
5490 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5491 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5492 // CHECK6-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
5493 // CHECK6-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
5494 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5495 // CHECK6-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
5496 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5497 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5498 // CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
5499 // CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
5500 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5501 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
5502 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
5503 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
5504 // CHECK6: omp.dispatch.cond:
5505 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5506 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
5507 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5508 // CHECK6: cond.true:
5509 // CHECK6-NEXT: br label [[COND_END:%.*]]
5510 // CHECK6: cond.false:
5511 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5512 // CHECK6-NEXT: br label [[COND_END]]
5513 // CHECK6: cond.end:
5514 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
5515 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5516 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5517 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
5518 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5519 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5520 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
5521 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5522 // CHECK6: omp.dispatch.body:
5523 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5524 // CHECK6: omp.inner.for.cond:
5525 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
5526 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26
5527 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
5528 // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5529 // CHECK6: omp.inner.for.body:
5530 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
5531 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
5532 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5533 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26
5534 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5535 // CHECK6: omp.body.continue:
5536 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5537 // CHECK6: omp.inner.for.inc:
5538 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
5539 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
5540 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
5541 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
5542 // CHECK6: omp.inner.for.end:
5543 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
5544 // CHECK6: omp.dispatch.inc:
5545 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5546 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5547 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
5548 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
5549 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5550 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
5551 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
5552 // CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
5553 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
5554 // CHECK6: omp.dispatch.end:
5555 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
5556 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5557 // CHECK6-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
5558 // CHECK6-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5559 // CHECK6: .omp.final.then:
5560 // CHECK6-NEXT: store i32 100, i32* [[I]], align 4
5561 // CHECK6-NEXT: br label [[DOTOMP_FINAL_DONE]]
5562 // CHECK6: .omp.final.done:
5563 // CHECK6-NEXT: ret void
5564 //
5565 //
5566 // CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5567 // CHECK6-SAME: () #[[ATTR4:[0-9]+]] {
5568 // CHECK6-NEXT: entry:
5569 // CHECK6-NEXT: call void @__tgt_register_requires(i64 1)
5570 // CHECK6-NEXT: ret void
5571 //
5572 //
5573 // CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
5574 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
5575 // CHECK7-NEXT: entry:
5576 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
5577 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
5578 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
5579 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
5580 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
5581 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
5582 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
5583 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
5584 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
5585 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
5586 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
5587 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
5588 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
5589 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
5590 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
5591 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
5592 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5593 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
5594 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
5595 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5596 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
5597 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
5598 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5599 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4
5600 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5601 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
5602 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
5603 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5604 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
5605 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
5606 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5607 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4
5608 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5609 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
5610 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
5611 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5612 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
5613 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
5614 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5615 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4
5616 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
5617 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
5618 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
5619 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
5620 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
5621 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
5622 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
5623 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4
5624 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5625 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5626 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424)
5627 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
5628 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
5629 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5630 // CHECK7: omp_offload.failed:
5631 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
5632 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
5633 // CHECK7: omp_offload.cont:
5634 // CHECK7-NEXT: ret void
5635 //
5636 //
5637 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
5638 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] {
5639 // CHECK7-NEXT: entry:
5640 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
5641 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
5642 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
5643 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
5644 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
5645 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
5646 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
5647 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
5648 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
5649 // CHECK7-NEXT: ret void
5650 //
5651 //
5652 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
5653 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
5654 // CHECK7-NEXT: entry:
5655 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5656 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5657 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
5658 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
5659 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
5660 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
5661 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5662 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
5663 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5664 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5665 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5666 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5667 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
5668 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5669 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5670 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
5671 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
5672 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
5673 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
5674 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
5675 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
5676 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
5677 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
5678 // CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
5679 // CHECK7-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
5680 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5681 // CHECK7-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
5682 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5683 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5684 // CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5685 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
5686 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5687 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5688 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
5689 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5690 // CHECK7: cond.true:
5691 // CHECK7-NEXT: br label [[COND_END:%.*]]
5692 // CHECK7: cond.false:
5693 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5694 // CHECK7-NEXT: br label [[COND_END]]
5695 // CHECK7: cond.end:
5696 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
5697 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5698 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5699 // CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
5700 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5701 // CHECK7: omp.inner.for.cond:
5702 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5703 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
5704 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
5705 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5706 // CHECK7: omp.inner.for.body:
5707 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5708 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
5709 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
5710 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
5711 // CHECK7-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !9
5712 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
5713 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
5714 // CHECK7-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
5715 // CHECK7-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !9
5716 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
5717 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
5718 // CHECK7-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
5719 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
5720 // CHECK7-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !9
5721 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
5722 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
5723 // CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9
5724 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
5725 // CHECK7-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !9
5726 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
5727 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
5728 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
5729 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5730 // CHECK7: omp.body.continue:
5731 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5732 // CHECK7: omp.inner.for.inc:
5733 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5734 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
5735 // CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
5736 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
5737 // CHECK7: omp.inner.for.end:
5738 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5739 // CHECK7: omp.loop.exit:
5740 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
5741 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5742 // CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
5743 // CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5744 // CHECK7: .omp.final.then:
5745 // CHECK7-NEXT: store i32 32000001, i32* [[I]], align 4
5746 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
5747 // CHECK7: .omp.final.done:
5748 // CHECK7-NEXT: ret void
5749 //
5750 //
5751 // CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
5752 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
5753 // CHECK7-NEXT: entry:
5754 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
5755 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
5756 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
5757 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
5758 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
5759 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
5760 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
5761 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
5762 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
5763 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
5764 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
5765 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
5766 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
5767 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
5768 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
5769 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
5770 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5771 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
5772 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
5773 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5774 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
5775 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
5776 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5777 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4
5778 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5779 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
5780 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
5781 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5782 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
5783 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
5784 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5785 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4
5786 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5787 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
5788 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
5789 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5790 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
5791 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
5792 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5793 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4
5794 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
5795 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
5796 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
5797 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
5798 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
5799 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
5800 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
5801 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4
5802 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5803 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5804 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424)
5805 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
5806 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
5807 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5808 // CHECK7: omp_offload.failed:
5809 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
5810 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
5811 // CHECK7: omp_offload.cont:
5812 // CHECK7-NEXT: ret void
5813 //
5814 //
5815 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
5816 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
5817 // CHECK7-NEXT: entry:
5818 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
5819 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
5820 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
5821 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
5822 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
5823 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
5824 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
5825 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
5826 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
5827 // CHECK7-NEXT: ret void
5828 //
5829 //
5830 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1
5831 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
5832 // CHECK7-NEXT: entry:
5833 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5834 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5835 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
5836 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
5837 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
5838 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
5839 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5840 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
5841 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5842 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5843 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5844 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5845 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
5846 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5847 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5848 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
5849 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
5850 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
5851 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
5852 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
5853 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
5854 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
5855 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
5856 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5857 // CHECK7-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
5858 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5859 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5860 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5861 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5862 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5863 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5864 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
5865 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5866 // CHECK7: cond.true:
5867 // CHECK7-NEXT: br label [[COND_END:%.*]]
5868 // CHECK7: cond.false:
5869 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5870 // CHECK7-NEXT: br label [[COND_END]]
5871 // CHECK7: cond.end:
5872 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5873 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5874 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5875 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
5876 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5877 // CHECK7: omp.inner.for.cond:
5878 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5879 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5880 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
5881 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5882 // CHECK7: omp.inner.for.body:
5883 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5884 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
5885 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
5886 // CHECK7-NEXT: store i32 [[SUB]], i32* [[I]], align 4
5887 // CHECK7-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4, !nontemporal !16
5888 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
5889 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
5890 // CHECK7-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
5891 // CHECK7-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
5892 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
5893 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
5894 // CHECK7-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
5895 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
5896 // CHECK7-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
5897 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
5898 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
5899 // CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
5900 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
5901 // CHECK7-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4, !nontemporal !16
5902 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
5903 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
5904 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
5905 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5906 // CHECK7: omp.body.continue:
5907 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5908 // CHECK7: omp.inner.for.inc:
5909 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5910 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
5911 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
5912 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
5913 // CHECK7: omp.inner.for.end:
5914 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5915 // CHECK7: omp.loop.exit:
5916 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
5917 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5918 // CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
5919 // CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5920 // CHECK7: .omp.final.then:
5921 // CHECK7-NEXT: store i32 32, i32* [[I]], align 4
5922 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
5923 // CHECK7: .omp.final.done:
5924 // CHECK7-NEXT: ret void
5925 //
5926 //
5927 // CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
5928 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
5929 // CHECK7-NEXT: entry:
5930 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
5931 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
5932 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
5933 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
5934 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
5935 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
5936 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
5937 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
5938 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
5939 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
5940 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
5941 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
5942 // CHECK7-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
5943 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
5944 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
5945 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
5946 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5947 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
5948 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
5949 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5950 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
5951 // CHECK7-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
5952 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5953 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4
5954 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5955 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
5956 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
5957 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5958 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
5959 // CHECK7-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
5960 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5961 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4
5962 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5963 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
5964 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
5965 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5966 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
5967 // CHECK7-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
5968 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5969 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4
5970 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
5971 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
5972 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
5973 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
5974 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
5975 // CHECK7-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
5976 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
5977 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4
5978 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5979 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5980 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289)
5981 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
5982 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
5983 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5984 // CHECK7: omp_offload.failed:
5985 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
5986 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
5987 // CHECK7: omp_offload.cont:
5988 // CHECK7-NEXT: ret void
5989 //
5990 //
5991 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
5992 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
5993 // CHECK7-NEXT: entry:
5994 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
5995 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
5996 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
5997 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
5998 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
5999 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6000 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6001 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6002 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6003 // CHECK7-NEXT: ret void
6004 //
6005 //
6006 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4
6007 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
6008 // CHECK7-NEXT: entry:
6009 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6010 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6011 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
6012 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
6013 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
6014 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
6015 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6016 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
6017 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6018 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6019 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6020 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6021 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
6022 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6023 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6024 // CHECK7-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
6025 // CHECK7-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
6026 // CHECK7-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
6027 // CHECK7-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
6028 // CHECK7-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
6029 // CHECK7-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
6030 // CHECK7-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
6031 // CHECK7-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
6032 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6033 // CHECK7-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
6034 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6035 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6036 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6037 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6038 // CHECK7-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
6039 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
6040 // CHECK7: omp.dispatch.cond:
6041 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6042 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
6043 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6044 // CHECK7: cond.true:
6045 // CHECK7-NEXT: br label [[COND_END:%.*]]
6046 // CHECK7: cond.false:
6047 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6048 // CHECK7-NEXT: br label [[COND_END]]
6049 // CHECK7: cond.end:
6050 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6051 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6052 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6053 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
6054 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6055 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6056 // CHECK7-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
6057 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6058 // CHECK7: omp.dispatch.body:
6059 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6060 // CHECK7: omp.inner.for.cond:
6061 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6062 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
6063 // CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
6064 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6065 // CHECK7: omp.inner.for.body:
6066 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6067 // CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
6068 // CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
6069 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
6070 // CHECK7-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !19
6071 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6072 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
6073 // CHECK7-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19
6074 // CHECK7-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !19
6075 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6076 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
6077 // CHECK7-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !19
6078 // CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
6079 // CHECK7-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !19
6080 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6081 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
6082 // CHECK7-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !19
6083 // CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
6084 // CHECK7-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !19
6085 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6086 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
6087 // CHECK7-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
6088 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6089 // CHECK7: omp.body.continue:
6090 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6091 // CHECK7: omp.inner.for.inc:
6092 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6093 // CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
6094 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6095 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
6096 // CHECK7: omp.inner.for.end:
6097 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
6098 // CHECK7: omp.dispatch.inc:
6099 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6100 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6101 // CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
6102 // CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
6103 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6104 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6105 // CHECK7-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
6106 // CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
6107 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
6108 // CHECK7: omp.dispatch.end:
6109 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6110 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6111 // CHECK7-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
6112 // CHECK7-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6113 // CHECK7: .omp.final.then:
6114 // CHECK7-NEXT: store i32 -2147483522, i32* [[I]], align 4
6115 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
6116 // CHECK7: .omp.final.done:
6117 // CHECK7-NEXT: ret void
6118 //
6119 //
6120 // CHECK7-LABEL: define {{[^@]+}}@_Z12test_precondv
6121 // CHECK7-SAME: () #[[ATTR0]] {
6122 // CHECK7-NEXT: entry:
6123 // CHECK7-NEXT: [[A:%.*]] = alloca i8, align 1
6124 // CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1
6125 // CHECK7-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4
6126 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
6127 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
6128 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
6129 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
6130 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1
6131 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6132 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
6133 // CHECK7-NEXT: store i8 0, i8* [[A]], align 1
6134 // CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
6135 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[I_CASTED]] to i8*
6136 // CHECK7-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
6137 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_CASTED]], align 4
6138 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
6139 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
6140 // CHECK7-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
6141 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
6142 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6143 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
6144 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
6145 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6146 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
6147 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
6148 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6149 // CHECK7-NEXT: store i8* null, i8** [[TMP8]], align 4
6150 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6151 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
6152 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
6153 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6154 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
6155 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
6156 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6157 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4
6158 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6159 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6160 // CHECK7-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
6161 // CHECK7-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
6162 // CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6163 // CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
6164 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
6165 // CHECK7-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
6166 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
6167 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
6168 // CHECK7-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
6169 // CHECK7-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
6170 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
6171 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
6172 // CHECK7-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
6173 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]])
6174 // CHECK7-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
6175 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
6176 // CHECK7-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6177 // CHECK7: omp_offload.failed:
6178 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]]
6179 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
6180 // CHECK7: omp_offload.cont:
6181 // CHECK7-NEXT: ret void
6182 //
6183 //
6184 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
6185 // CHECK7-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
6186 // CHECK7-NEXT: entry:
6187 // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
6188 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
6189 // CHECK7-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
6190 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
6191 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
6192 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
6193 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
6194 // CHECK7-NEXT: ret void
6195 //
6196 //
6197 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7
6198 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
6199 // CHECK7-NEXT: entry:
6200 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6201 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6202 // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
6203 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
6204 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6205 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1
6206 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6207 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
6208 // CHECK7-NEXT: [[I4:%.*]] = alloca i8, align 1
6209 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6210 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6211 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6212 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6213 // CHECK7-NEXT: [[I6:%.*]] = alloca i8, align 1
6214 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6215 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6216 // CHECK7-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
6217 // CHECK7-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
6218 // CHECK7-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
6219 // CHECK7-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
6220 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
6221 // CHECK7-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
6222 // CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6223 // CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
6224 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
6225 // CHECK7-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
6226 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
6227 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
6228 // CHECK7-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
6229 // CHECK7-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
6230 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6231 // CHECK7-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
6232 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6233 // CHECK7-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
6234 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
6235 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
6236 // CHECK7: omp.precond.then:
6237 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6238 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
6239 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
6240 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6241 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6242 // CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6243 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
6244 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6245 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6246 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
6247 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
6248 // CHECK7-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6249 // CHECK7: cond.true:
6250 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
6251 // CHECK7-NEXT: br label [[COND_END:%.*]]
6252 // CHECK7: cond.false:
6253 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6254 // CHECK7-NEXT: br label [[COND_END]]
6255 // CHECK7: cond.end:
6256 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
6257 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6258 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6259 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
6260 // CHECK7-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
6261 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
6262 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6263 // CHECK7: omp_if.then:
6264 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6265 // CHECK7: omp.inner.for.cond:
6266 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6267 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
6268 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
6269 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6270 // CHECK7: omp.inner.for.body:
6271 // CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
6272 // CHECK7-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
6273 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6274 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
6275 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
6276 // CHECK7-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
6277 // CHECK7-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
6278 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6279 // CHECK7: omp.body.continue:
6280 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6281 // CHECK7: omp.inner.for.inc:
6282 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6283 // CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
6284 // CHECK7-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6285 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
6286 // CHECK7: omp.inner.for.end:
6287 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
6288 // CHECK7: omp_if.else:
6289 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
6290 // CHECK7: omp.inner.for.cond13:
6291 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6292 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6293 // CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
6294 // CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
6295 // CHECK7: omp.inner.for.body15:
6296 // CHECK7-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6297 // CHECK7-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
6298 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6299 // CHECK7-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
6300 // CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
6301 // CHECK7-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
6302 // CHECK7-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
6303 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
6304 // CHECK7: omp.body.continue20:
6305 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
6306 // CHECK7: omp.inner.for.inc21:
6307 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6308 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
6309 // CHECK7-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
6310 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
6311 // CHECK7: omp.inner.for.end23:
6312 // CHECK7-NEXT: br label [[OMP_IF_END]]
6313 // CHECK7: omp_if.end:
6314 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6315 // CHECK7: omp.loop.exit:
6316 // CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6317 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
6318 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
6319 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6320 // CHECK7-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
6321 // CHECK7-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6322 // CHECK7: .omp.final.then:
6323 // CHECK7-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6324 // CHECK7-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
6325 // CHECK7-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6326 // CHECK7-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
6327 // CHECK7-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
6328 // CHECK7-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
6329 // CHECK7-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
6330 // CHECK7-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
6331 // CHECK7-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
6332 // CHECK7-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
6333 // CHECK7-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
6334 // CHECK7-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
6335 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
6336 // CHECK7: .omp.final.done:
6337 // CHECK7-NEXT: br label [[OMP_PRECOND_END]]
6338 // CHECK7: omp.precond.end:
6339 // CHECK7-NEXT: ret void
6340 //
6341 //
6342 // CHECK7-LABEL: define {{[^@]+}}@_Z4fintv
6343 // CHECK7-SAME: () #[[ATTR0]] {
6344 // CHECK7-NEXT: entry:
6345 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
6346 // CHECK7-NEXT: ret i32 [[CALL]]
6347 //
6348 //
6349 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
6350 // CHECK7-SAME: () #[[ATTR0]] comdat {
6351 // CHECK7-NEXT: entry:
6352 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2
6353 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
6354 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
6355 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
6356 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
6357 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
6358 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2
6359 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
6360 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6361 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
6362 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6363 // CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6364 // CHECK7-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
6365 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
6366 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6367 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
6368 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
6369 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6370 // CHECK7-NEXT: store i8* null, i8** [[TMP6]], align 4
6371 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6372 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6373 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100)
6374 // CHECK7-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
6375 // CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
6376 // CHECK7-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6377 // CHECK7: omp_offload.failed:
6378 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]]
6379 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
6380 // CHECK7: omp_offload.cont:
6381 // CHECK7-NEXT: ret i32 0
6382 //
6383 //
6384 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
6385 // CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] {
6386 // CHECK7-NEXT: entry:
6387 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
6388 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
6389 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6390 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
6391 // CHECK7-NEXT: ret void
6392 //
6393 //
6394 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10
6395 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
6396 // CHECK7-NEXT: entry:
6397 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6398 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6399 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
6400 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6401 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
6402 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6403 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6404 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6405 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6406 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
6407 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6408 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6409 // CHECK7-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
6410 // CHECK7-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
6411 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6412 // CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
6413 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6414 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6415 // CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
6416 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
6417 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6418 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
6419 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
6420 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
6421 // CHECK7: omp.dispatch.cond:
6422 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6423 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
6424 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6425 // CHECK7: cond.true:
6426 // CHECK7-NEXT: br label [[COND_END:%.*]]
6427 // CHECK7: cond.false:
6428 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6429 // CHECK7-NEXT: br label [[COND_END]]
6430 // CHECK7: cond.end:
6431 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
6432 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6433 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6434 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
6435 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6436 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6437 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
6438 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6439 // CHECK7: omp.dispatch.body:
6440 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6441 // CHECK7: omp.inner.for.cond:
6442 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
6443 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
6444 // CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6445 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6446 // CHECK7: omp.inner.for.body:
6447 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
6448 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
6449 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6450 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
6451 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6452 // CHECK7: omp.body.continue:
6453 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6454 // CHECK7: omp.inner.for.inc:
6455 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
6456 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
6457 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
6458 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
6459 // CHECK7: omp.inner.for.end:
6460 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
6461 // CHECK7: omp.dispatch.inc:
6462 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6463 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6464 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
6465 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
6466 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6467 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6468 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
6469 // CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
6470 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
6471 // CHECK7: omp.dispatch.end:
6472 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
6473 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6474 // CHECK7-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
6475 // CHECK7-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6476 // CHECK7: .omp.final.then:
6477 // CHECK7-NEXT: store i32 100, i32* [[I]], align 4
6478 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]]
6479 // CHECK7: .omp.final.done:
6480 // CHECK7-NEXT: ret void
6481 //
6482 //
6483 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
6484 // CHECK7-SAME: () #[[ATTR4:[0-9]+]] {
6485 // CHECK7-NEXT: entry:
6486 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1)
6487 // CHECK7-NEXT: ret void
6488 //
6489 //
6490 // CHECK8-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
6491 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
6492 // CHECK8-NEXT: entry:
6493 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
6494 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
6495 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
6496 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
6497 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
6498 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
6499 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
6500 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
6501 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
6502 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6503 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6504 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6505 // CHECK8-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
6506 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
6507 // CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
6508 // CHECK8-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
6509 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6510 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
6511 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
6512 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6513 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
6514 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
6515 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6516 // CHECK8-NEXT: store i8* null, i8** [[TMP8]], align 4
6517 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6518 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
6519 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
6520 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6521 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
6522 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
6523 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6524 // CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4
6525 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6526 // CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
6527 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
6528 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6529 // CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
6530 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
6531 // CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6532 // CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4
6533 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6534 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
6535 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
6536 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6537 // CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
6538 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
6539 // CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6540 // CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4
6541 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6542 // CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6543 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 4571424)
6544 // CHECK8-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
6545 // CHECK8-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
6546 // CHECK8-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6547 // CHECK8: omp_offload.failed:
6548 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3:[0-9]+]]
6549 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
6550 // CHECK8: omp_offload.cont:
6551 // CHECK8-NEXT: ret void
6552 //
6553 //
6554 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
6555 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] {
6556 // CHECK8-NEXT: entry:
6557 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
6558 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
6559 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
6560 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
6561 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
6562 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6563 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6564 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6565 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6566 // CHECK8-NEXT: ret void
6567 //
6568 //
6569 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined.
6570 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
6571 // CHECK8-NEXT: entry:
6572 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6573 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6574 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
6575 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
6576 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
6577 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
6578 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6579 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
6580 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6581 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6582 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6583 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6584 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
6585 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6586 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6587 // CHECK8-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
6588 // CHECK8-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
6589 // CHECK8-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
6590 // CHECK8-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
6591 // CHECK8-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
6592 // CHECK8-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
6593 // CHECK8-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
6594 // CHECK8-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
6595 // CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
6596 // CHECK8-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
6597 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6598 // CHECK8-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
6599 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6600 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6601 // CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6602 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
6603 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6604 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6605 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
6606 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6607 // CHECK8: cond.true:
6608 // CHECK8-NEXT: br label [[COND_END:%.*]]
6609 // CHECK8: cond.false:
6610 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6611 // CHECK8-NEXT: br label [[COND_END]]
6612 // CHECK8: cond.end:
6613 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
6614 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6615 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6616 // CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
6617 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6618 // CHECK8: omp.inner.for.cond:
6619 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
6620 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
6621 // CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
6622 // CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6623 // CHECK8: omp.inner.for.body:
6624 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
6625 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
6626 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
6627 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
6628 // CHECK8-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !9
6629 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
6630 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
6631 // CHECK8-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
6632 // CHECK8-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !9
6633 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
6634 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
6635 // CHECK8-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
6636 // CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
6637 // CHECK8-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !9
6638 // CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
6639 // CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
6640 // CHECK8-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !9
6641 // CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
6642 // CHECK8-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !9
6643 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
6644 // CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
6645 // CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
6646 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6647 // CHECK8: omp.body.continue:
6648 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6649 // CHECK8: omp.inner.for.inc:
6650 // CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
6651 // CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
6652 // CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
6653 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
6654 // CHECK8: omp.inner.for.end:
6655 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6656 // CHECK8: omp.loop.exit:
6657 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
6658 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6659 // CHECK8-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
6660 // CHECK8-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6661 // CHECK8: .omp.final.then:
6662 // CHECK8-NEXT: store i32 32000001, i32* [[I]], align 4
6663 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
6664 // CHECK8: .omp.final.done:
6665 // CHECK8-NEXT: ret void
6666 //
6667 //
6668 // CHECK8-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
6669 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
6670 // CHECK8-NEXT: entry:
6671 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
6672 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
6673 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
6674 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
6675 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
6676 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
6677 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
6678 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
6679 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
6680 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6681 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6682 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6683 // CHECK8-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
6684 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
6685 // CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
6686 // CHECK8-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
6687 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6688 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
6689 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
6690 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6691 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
6692 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
6693 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6694 // CHECK8-NEXT: store i8* null, i8** [[TMP8]], align 4
6695 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6696 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
6697 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
6698 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6699 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
6700 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
6701 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6702 // CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4
6703 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6704 // CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
6705 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
6706 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6707 // CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
6708 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
6709 // CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6710 // CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4
6711 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6712 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
6713 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
6714 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6715 // CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
6716 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
6717 // CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6718 // CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4
6719 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6720 // CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6721 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 4571424)
6722 // CHECK8-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
6723 // CHECK8-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
6724 // CHECK8-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6725 // CHECK8: omp_offload.failed:
6726 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
6727 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
6728 // CHECK8: omp_offload.cont:
6729 // CHECK8-NEXT: ret void
6730 //
6731 //
6732 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
6733 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
6734 // CHECK8-NEXT: entry:
6735 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
6736 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
6737 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
6738 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
6739 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
6740 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6741 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6742 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6743 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6744 // CHECK8-NEXT: ret void
6745 //
6746 //
6747 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1
6748 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
6749 // CHECK8-NEXT: entry:
6750 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6751 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6752 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
6753 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
6754 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
6755 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
6756 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6757 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
6758 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6759 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6760 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6761 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6762 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
6763 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6764 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6765 // CHECK8-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
6766 // CHECK8-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
6767 // CHECK8-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
6768 // CHECK8-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
6769 // CHECK8-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
6770 // CHECK8-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
6771 // CHECK8-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
6772 // CHECK8-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
6773 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6774 // CHECK8-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
6775 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6776 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6777 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6778 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6779 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6780 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6781 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
6782 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6783 // CHECK8: cond.true:
6784 // CHECK8-NEXT: br label [[COND_END:%.*]]
6785 // CHECK8: cond.false:
6786 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6787 // CHECK8-NEXT: br label [[COND_END]]
6788 // CHECK8: cond.end:
6789 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6790 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6791 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6792 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
6793 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6794 // CHECK8: omp.inner.for.cond:
6795 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6796 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6797 // CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6798 // CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6799 // CHECK8: omp.inner.for.body:
6800 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6801 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
6802 // CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
6803 // CHECK8-NEXT: store i32 [[SUB]], i32* [[I]], align 4
6804 // CHECK8-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4, !nontemporal !16
6805 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
6806 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
6807 // CHECK8-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
6808 // CHECK8-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
6809 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
6810 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
6811 // CHECK8-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
6812 // CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
6813 // CHECK8-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
6814 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
6815 // CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
6816 // CHECK8-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
6817 // CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
6818 // CHECK8-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4, !nontemporal !16
6819 // CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
6820 // CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
6821 // CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
6822 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6823 // CHECK8: omp.body.continue:
6824 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6825 // CHECK8: omp.inner.for.inc:
6826 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6827 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
6828 // CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
6829 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
6830 // CHECK8: omp.inner.for.end:
6831 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6832 // CHECK8: omp.loop.exit:
6833 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6834 // CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6835 // CHECK8-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
6836 // CHECK8-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6837 // CHECK8: .omp.final.then:
6838 // CHECK8-NEXT: store i32 32, i32* [[I]], align 4
6839 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
6840 // CHECK8: .omp.final.done:
6841 // CHECK8-NEXT: ret void
6842 //
6843 //
6844 // CHECK8-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
6845 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
6846 // CHECK8-NEXT: entry:
6847 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
6848 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
6849 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
6850 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
6851 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
6852 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
6853 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
6854 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
6855 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
6856 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6857 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6858 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6859 // CHECK8-NEXT: [[TMP0:%.*]] = load float*, float** [[A_ADDR]], align 4
6860 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 4
6861 // CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[C_ADDR]], align 4
6862 // CHECK8-NEXT: [[TMP3:%.*]] = load float*, float** [[D_ADDR]], align 4
6863 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6864 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to float**
6865 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP5]], align 4
6866 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6867 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to float**
6868 // CHECK8-NEXT: store float* [[TMP0]], float** [[TMP7]], align 4
6869 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6870 // CHECK8-NEXT: store i8* null, i8** [[TMP8]], align 4
6871 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6872 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to float**
6873 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP10]], align 4
6874 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6875 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to float**
6876 // CHECK8-NEXT: store float* [[TMP1]], float** [[TMP12]], align 4
6877 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6878 // CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4
6879 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6880 // CHECK8-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float**
6881 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP15]], align 4
6882 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6883 // CHECK8-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float**
6884 // CHECK8-NEXT: store float* [[TMP2]], float** [[TMP17]], align 4
6885 // CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6886 // CHECK8-NEXT: store i8* null, i8** [[TMP18]], align 4
6887 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6888 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to float**
6889 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP20]], align 4
6890 // CHECK8-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6891 // CHECK8-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float**
6892 // CHECK8-NEXT: store float* [[TMP3]], float** [[TMP22]], align 4
6893 // CHECK8-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6894 // CHECK8-NEXT: store i8* null, i8** [[TMP23]], align 4
6895 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6896 // CHECK8-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6897 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 16908289)
6898 // CHECK8-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.region_id, i32 4, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
6899 // CHECK8-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
6900 // CHECK8-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6901 // CHECK8: omp_offload.failed:
6902 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103(float* [[TMP0]], float* [[TMP1]], float* [[TMP2]], float* [[TMP3]]) #[[ATTR3]]
6903 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
6904 // CHECK8: omp_offload.cont:
6905 // CHECK8-NEXT: ret void
6906 //
6907 //
6908 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
6909 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] {
6910 // CHECK8-NEXT: entry:
6911 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
6912 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
6913 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
6914 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
6915 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
6916 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
6917 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
6918 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
6919 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
6920 // CHECK8-NEXT: ret void
6921 //
6922 //
6923 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4
6924 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] {
6925 // CHECK8-NEXT: entry:
6926 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6927 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6928 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
6929 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
6930 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
6931 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
6932 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6933 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
6934 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6935 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6936 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6937 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6938 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
6939 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6940 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6941 // CHECK8-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
6942 // CHECK8-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
6943 // CHECK8-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
6944 // CHECK8-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
6945 // CHECK8-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
6946 // CHECK8-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
6947 // CHECK8-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
6948 // CHECK8-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
6949 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6950 // CHECK8-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
6951 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6952 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6953 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6954 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6955 // CHECK8-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
6956 // CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
6957 // CHECK8: omp.dispatch.cond:
6958 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6959 // CHECK8-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
6960 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6961 // CHECK8: cond.true:
6962 // CHECK8-NEXT: br label [[COND_END:%.*]]
6963 // CHECK8: cond.false:
6964 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6965 // CHECK8-NEXT: br label [[COND_END]]
6966 // CHECK8: cond.end:
6967 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6968 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6969 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6970 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
6971 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6972 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6973 // CHECK8-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
6974 // CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6975 // CHECK8: omp.dispatch.body:
6976 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6977 // CHECK8: omp.inner.for.cond:
6978 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6979 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
6980 // CHECK8-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
6981 // CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6982 // CHECK8: omp.inner.for.body:
6983 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
6984 // CHECK8-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
6985 // CHECK8-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
6986 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
6987 // CHECK8-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !19
6988 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6989 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
6990 // CHECK8-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19
6991 // CHECK8-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !19
6992 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6993 // CHECK8-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
6994 // CHECK8-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !19
6995 // CHECK8-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
6996 // CHECK8-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !19
6997 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
6998 // CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
6999 // CHECK8-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !19
7000 // CHECK8-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
7001 // CHECK8-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !19
7002 // CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
7003 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
7004 // CHECK8-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
7005 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7006 // CHECK8: omp.body.continue:
7007 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7008 // CHECK8: omp.inner.for.inc:
7009 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
7010 // CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
7011 // CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
7012 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
7013 // CHECK8: omp.inner.for.end:
7014 // CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
7015 // CHECK8: omp.dispatch.inc:
7016 // CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7017 // CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7018 // CHECK8-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
7019 // CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
7020 // CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7021 // CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7022 // CHECK8-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
7023 // CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
7024 // CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]
7025 // CHECK8: omp.dispatch.end:
7026 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
7027 // CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7028 // CHECK8-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
7029 // CHECK8-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7030 // CHECK8: .omp.final.then:
7031 // CHECK8-NEXT: store i32 -2147483522, i32* [[I]], align 4
7032 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
7033 // CHECK8: .omp.final.done:
7034 // CHECK8-NEXT: ret void
7035 //
7036 //
7037 // CHECK8-LABEL: define {{[^@]+}}@_Z12test_precondv
7038 // CHECK8-SAME: () #[[ATTR0]] {
7039 // CHECK8-NEXT: entry:
7040 // CHECK8-NEXT: [[A:%.*]] = alloca i8, align 1
7041 // CHECK8-NEXT: [[I:%.*]] = alloca i8, align 1
7042 // CHECK8-NEXT: [[I_CASTED:%.*]] = alloca i32, align 4
7043 // CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
7044 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
7045 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
7046 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
7047 // CHECK8-NEXT: [[TMP:%.*]] = alloca i8, align 1
7048 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7049 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7050 // CHECK8-NEXT: store i8 0, i8* [[A]], align 1
7051 // CHECK8-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1
7052 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[I_CASTED]] to i8*
7053 // CHECK8-NEXT: store i8 [[TMP0]], i8* [[CONV]], align 1
7054 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_CASTED]], align 4
7055 // CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[A]], align 1
7056 // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_CASTED]] to i8*
7057 // CHECK8-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
7058 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
7059 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7060 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
7061 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
7062 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7063 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
7064 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
7065 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
7066 // CHECK8-NEXT: store i8* null, i8** [[TMP8]], align 4
7067 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7068 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
7069 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
7070 // CHECK8-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7071 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
7072 // CHECK8-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
7073 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
7074 // CHECK8-NEXT: store i8* null, i8** [[TMP13]], align 4
7075 // CHECK8-NEXT: [[TMP14:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7076 // CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7077 // CHECK8-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1
7078 // CHECK8-NEXT: store i8 [[TMP16]], i8* [[DOTCAPTURE_EXPR_]], align 1
7079 // CHECK8-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7080 // CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP17]] to i32
7081 // CHECK8-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV3]]
7082 // CHECK8-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
7083 // CHECK8-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1
7084 // CHECK8-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
7085 // CHECK8-NEXT: [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
7086 // CHECK8-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
7087 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
7088 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
7089 // CHECK8-NEXT: [[TMP19:%.*]] = zext i32 [[ADD6]] to i64
7090 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP19]])
7091 // CHECK8-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.region_id, i32 2, i8** [[TMP14]], i8** [[TMP15]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
7092 // CHECK8-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
7093 // CHECK8-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7094 // CHECK8: omp_offload.failed:
7095 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115(i32 [[TMP1]], i32 [[TMP3]]) #[[ATTR3]]
7096 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
7097 // CHECK8: omp_offload.cont:
7098 // CHECK8-NEXT: ret void
7099 //
7100 //
7101 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
7102 // CHECK8-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
7103 // CHECK8-NEXT: entry:
7104 // CHECK8-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
7105 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
7106 // CHECK8-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
7107 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
7108 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
7109 // CHECK8-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
7110 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
7111 // CHECK8-NEXT: ret void
7112 //
7113 //
7114 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7
7115 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] {
7116 // CHECK8-NEXT: entry:
7117 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7118 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7119 // CHECK8-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
7120 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
7121 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7122 // CHECK8-NEXT: [[TMP:%.*]] = alloca i8, align 1
7123 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7124 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
7125 // CHECK8-NEXT: [[I4:%.*]] = alloca i8, align 1
7126 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7127 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7128 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7129 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7130 // CHECK8-NEXT: [[I6:%.*]] = alloca i8, align 1
7131 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7132 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7133 // CHECK8-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
7134 // CHECK8-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
7135 // CHECK8-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
7136 // CHECK8-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
7137 // CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
7138 // CHECK8-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
7139 // CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7140 // CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
7141 // CHECK8-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
7142 // CHECK8-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
7143 // CHECK8-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
7144 // CHECK8-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
7145 // CHECK8-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
7146 // CHECK8-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
7147 // CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7148 // CHECK8-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
7149 // CHECK8-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7150 // CHECK8-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
7151 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
7152 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
7153 // CHECK8: omp.precond.then:
7154 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7155 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7156 // CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
7157 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7158 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7159 // CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7160 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
7161 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7162 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7163 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7164 // CHECK8-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
7165 // CHECK8-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7166 // CHECK8: cond.true:
7167 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7168 // CHECK8-NEXT: br label [[COND_END:%.*]]
7169 // CHECK8: cond.false:
7170 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7171 // CHECK8-NEXT: br label [[COND_END]]
7172 // CHECK8: cond.end:
7173 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
7174 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7175 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7176 // CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
7177 // CHECK8-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
7178 // CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
7179 // CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7180 // CHECK8: omp_if.then:
7181 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7182 // CHECK8: omp.inner.for.cond:
7183 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
7184 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
7185 // CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
7186 // CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7187 // CHECK8: omp.inner.for.body:
7188 // CHECK8-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
7189 // CHECK8-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
7190 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
7191 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
7192 // CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
7193 // CHECK8-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
7194 // CHECK8-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
7195 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7196 // CHECK8: omp.body.continue:
7197 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7198 // CHECK8: omp.inner.for.inc:
7199 // CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
7200 // CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
7201 // CHECK8-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
7202 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
7203 // CHECK8: omp.inner.for.end:
7204 // CHECK8-NEXT: br label [[OMP_IF_END:%.*]]
7205 // CHECK8: omp_if.else:
7206 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
7207 // CHECK8: omp.inner.for.cond13:
7208 // CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7209 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7210 // CHECK8-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
7211 // CHECK8-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
7212 // CHECK8: omp.inner.for.body15:
7213 // CHECK8-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7214 // CHECK8-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
7215 // CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7216 // CHECK8-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
7217 // CHECK8-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
7218 // CHECK8-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
7219 // CHECK8-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
7220 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
7221 // CHECK8: omp.body.continue20:
7222 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
7223 // CHECK8: omp.inner.for.inc21:
7224 // CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7225 // CHECK8-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
7226 // CHECK8-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
7227 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
7228 // CHECK8: omp.inner.for.end23:
7229 // CHECK8-NEXT: br label [[OMP_IF_END]]
7230 // CHECK8: omp_if.end:
7231 // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
7232 // CHECK8: omp.loop.exit:
7233 // CHECK8-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7234 // CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
7235 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
7236 // CHECK8-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7237 // CHECK8-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
7238 // CHECK8-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7239 // CHECK8: .omp.final.then:
7240 // CHECK8-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7241 // CHECK8-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
7242 // CHECK8-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7243 // CHECK8-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
7244 // CHECK8-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
7245 // CHECK8-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
7246 // CHECK8-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
7247 // CHECK8-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
7248 // CHECK8-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
7249 // CHECK8-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
7250 // CHECK8-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
7251 // CHECK8-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
7252 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
7253 // CHECK8: .omp.final.done:
7254 // CHECK8-NEXT: br label [[OMP_PRECOND_END]]
7255 // CHECK8: omp.precond.end:
7256 // CHECK8-NEXT: ret void
7257 //
7258 //
7259 // CHECK8-LABEL: define {{[^@]+}}@_Z4fintv
7260 // CHECK8-SAME: () #[[ATTR0]] {
7261 // CHECK8-NEXT: entry:
7262 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
7263 // CHECK8-NEXT: ret i32 [[CALL]]
7264 //
7265 //
7266 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
7267 // CHECK8-SAME: () #[[ATTR0]] comdat {
7268 // CHECK8-NEXT: entry:
7269 // CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2
7270 // CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
7271 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
7272 // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
7273 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
7274 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
7275 // CHECK8-NEXT: store i16 0, i16* [[AA]], align 2
7276 // CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[AA]], align 2
7277 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7278 // CHECK8-NEXT: store i16 [[TMP0]], i16* [[CONV]], align 2
7279 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7280 // CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7281 // CHECK8-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
7282 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
7283 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7284 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
7285 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
7286 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
7287 // CHECK8-NEXT: store i8* null, i8** [[TMP6]], align 4
7288 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7289 // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7290 // CHECK8-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 100)
7291 // CHECK8-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
7292 // CHECK8-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
7293 // CHECK8-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7294 // CHECK8: omp_offload.failed:
7295 // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135(i32 [[TMP1]]) #[[ATTR3]]
7296 // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]]
7297 // CHECK8: omp_offload.cont:
7298 // CHECK8-NEXT: ret i32 0
7299 //
7300 //
7301 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
7302 // CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] {
7303 // CHECK8-NEXT: entry:
7304 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
7305 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
7306 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7307 // CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i16* [[CONV]])
7308 // CHECK8-NEXT: ret void
7309 //
7310 //
7311 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10
7312 // CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] {
7313 // CHECK8-NEXT: entry:
7314 // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7315 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7316 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
7317 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7318 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
7319 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7320 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7321 // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7322 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7323 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
7324 // CHECK8-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7325 // CHECK8-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7326 // CHECK8-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
7327 // CHECK8-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
7328 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7329 // CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
7330 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7331 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7332 // CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
7333 // CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7334 // CHECK8-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7335 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
7336 // CHECK8-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
7337 // CHECK8-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
7338 // CHECK8: omp.dispatch.cond:
7339 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7340 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
7341 // CHECK8-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7342 // CHECK8: cond.true:
7343 // CHECK8-NEXT: br label [[COND_END:%.*]]
7344 // CHECK8: cond.false:
7345 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7346 // CHECK8-NEXT: br label [[COND_END]]
7347 // CHECK8: cond.end:
7348 // CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
7349 // CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7350 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7351 // CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
7352 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7353 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7354 // CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
7355 // CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7356 // CHECK8: omp.dispatch.body:
7357 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7358 // CHECK8: omp.inner.for.cond:
7359 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
7360 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
7361 // CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
7362 // CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7363 // CHECK8: omp.inner.for.body:
7364 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
7365 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
7366 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7367 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
7368 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7369 // CHECK8: omp.body.continue:
7370 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7371 // CHECK8: omp.inner.for.inc:
7372 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
7373 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
7374 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
7375 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
7376 // CHECK8: omp.inner.for.end:
7377 // CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
7378 // CHECK8: omp.dispatch.inc:
7379 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7380 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7381 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
7382 // CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
7383 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7384 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
7385 // CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
7386 // CHECK8-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
7387 // CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]
7388 // CHECK8: omp.dispatch.end:
7389 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
7390 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7391 // CHECK8-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
7392 // CHECK8-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7393 // CHECK8: .omp.final.then:
7394 // CHECK8-NEXT: store i32 100, i32* [[I]], align 4
7395 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]]
7396 // CHECK8: .omp.final.done:
7397 // CHECK8-NEXT: ret void
7398 //
7399 //
7400 // CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
7401 // CHECK8-SAME: () #[[ATTR4:[0-9]+]] {
7402 // CHECK8-NEXT: entry:
7403 // CHECK8-NEXT: call void @__tgt_register_requires(i64 1)
7404 // CHECK8-NEXT: ret void
7405 //
7406 //
7407 // CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
7408 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
7409 // CHECK9-NEXT: entry:
7410 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
7411 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
7412 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
7413 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
7414 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
7415 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7416 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7417 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7418 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
7419 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
7420 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
7421 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
7422 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
7423 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7424 // CHECK9-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
7425 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7426 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
7427 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
7428 // CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
7429 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7430 // CHECK9: omp.inner.for.cond:
7431 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7432 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
7433 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
7434 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7435 // CHECK9: omp.inner.for.body:
7436 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7437 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
7438 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
7439 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
7440 // CHECK9-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
7441 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
7442 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
7443 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
7444 // CHECK9-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
7445 // CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
7446 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
7447 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
7448 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
7449 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
7450 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
7451 // CHECK9-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
7452 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
7453 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
7454 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
7455 // CHECK9-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
7456 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
7457 // CHECK9-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
7458 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
7459 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
7460 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
7461 // CHECK9-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
7462 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7463 // CHECK9: omp.body.continue:
7464 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7465 // CHECK9: omp.inner.for.inc:
7466 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7467 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
7468 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7469 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
7470 // CHECK9: omp.inner.for.end:
7471 // CHECK9-NEXT: store i32 32000001, i32* [[I]], align 4
7472 // CHECK9-NEXT: ret void
7473 //
7474 //
7475 // CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
7476 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
7477 // CHECK9-NEXT: entry:
7478 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
7479 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
7480 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
7481 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
7482 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
7483 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7484 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7485 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7486 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
7487 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
7488 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
7489 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
7490 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
7491 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7492 // CHECK9-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
7493 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7494 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
7495 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7496 // CHECK9: omp.inner.for.cond:
7497 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7498 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7499 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
7500 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7501 // CHECK9: omp.inner.for.body:
7502 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7503 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
7504 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
7505 // CHECK9-NEXT: store i32 [[SUB]], i32* [[I]], align 4
7506 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8
7507 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
7508 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
7509 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
7510 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
7511 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
7512 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
7513 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
7514 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
7515 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
7516 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
7517 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
7518 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
7519 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
7520 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
7521 // CHECK9-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
7522 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
7523 // CHECK9-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8
7524 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
7525 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
7526 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
7527 // CHECK9-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
7528 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7529 // CHECK9: omp.body.continue:
7530 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7531 // CHECK9: omp.inner.for.inc:
7532 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7533 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
7534 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
7535 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
7536 // CHECK9: omp.inner.for.end:
7537 // CHECK9-NEXT: store i32 32, i32* [[I]], align 4
7538 // CHECK9-NEXT: ret void
7539 //
7540 //
7541 // CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
7542 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
7543 // CHECK9-NEXT: entry:
7544 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
7545 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
7546 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
7547 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
7548 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
7549 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7550 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7551 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7552 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
7553 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
7554 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
7555 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
7556 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
7557 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7558 // CHECK9-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
7559 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7560 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
7561 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7562 // CHECK9: omp.inner.for.cond:
7563 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
7564 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
7565 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
7566 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7567 // CHECK9: omp.inner.for.body:
7568 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
7569 // CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
7570 // CHECK9-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
7571 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
7572 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !9
7573 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
7574 // CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
7575 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
7576 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
7577 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !9
7578 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
7579 // CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
7580 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
7581 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
7582 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
7583 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !9
7584 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
7585 // CHECK9-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
7586 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
7587 // CHECK9-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !9
7588 // CHECK9-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
7589 // CHECK9-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !9
7590 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
7591 // CHECK9-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
7592 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
7593 // CHECK9-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !9
7594 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7595 // CHECK9: omp.body.continue:
7596 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7597 // CHECK9: omp.inner.for.inc:
7598 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
7599 // CHECK9-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
7600 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
7601 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
7602 // CHECK9: omp.inner.for.end:
7603 // CHECK9-NEXT: store i32 -2147483522, i32* [[I]], align 4
7604 // CHECK9-NEXT: ret void
7605 //
7606 //
7607 // CHECK9-LABEL: define {{[^@]+}}@_Z12test_precondv
7608 // CHECK9-SAME: () #[[ATTR0]] {
7609 // CHECK9-NEXT: entry:
7610 // CHECK9-NEXT: [[A:%.*]] = alloca i8, align 1
7611 // CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1
7612 // CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1
7613 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7614 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
7615 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7616 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7617 // CHECK9-NEXT: [[I4:%.*]] = alloca i8, align 1
7618 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7619 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
7620 // CHECK9-NEXT: [[I6:%.*]] = alloca i8, align 1
7621 // CHECK9-NEXT: [[I7:%.*]] = alloca i8, align 1
7622 // CHECK9-NEXT: store i8 0, i8* [[A]], align 1
7623 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
7624 // CHECK9-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
7625 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7626 // CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
7627 // CHECK9-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
7628 // CHECK9-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
7629 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
7630 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
7631 // CHECK9-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
7632 // CHECK9-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
7633 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7634 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7635 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
7636 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7637 // CHECK9-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
7638 // CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7639 // CHECK9-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
7640 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
7641 // CHECK9-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
7642 // CHECK9: simd.if.then:
7643 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7644 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
7645 // CHECK9-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
7646 // CHECK9-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
7647 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7648 // CHECK9: omp.inner.for.cond:
7649 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
7650 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
7651 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
7652 // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7653 // CHECK9: omp.inner.for.body:
7654 // CHECK9-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !12
7655 // CHECK9-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
7656 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
7657 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
7658 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
7659 // CHECK9-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
7660 // CHECK9-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !12
7661 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7662 // CHECK9: omp.body.continue:
7663 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7664 // CHECK9: omp.inner.for.inc:
7665 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
7666 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
7667 // CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
7668 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
7669 // CHECK9: omp.inner.for.end:
7670 // CHECK9-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7671 // CHECK9-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
7672 // CHECK9-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7673 // CHECK9-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
7674 // CHECK9-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
7675 // CHECK9-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
7676 // CHECK9-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
7677 // CHECK9-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
7678 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
7679 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
7680 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
7681 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
7682 // CHECK9-NEXT: br label [[SIMD_IF_END]]
7683 // CHECK9: simd.if.end:
7684 // CHECK9-NEXT: ret void
7685 //
7686 //
7687 // CHECK9-LABEL: define {{[^@]+}}@_Z4fintv
7688 // CHECK9-SAME: () #[[ATTR0]] {
7689 // CHECK9-NEXT: entry:
7690 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
7691 // CHECK9-NEXT: ret i32 [[CALL]]
7692 //
7693 //
7694 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
7695 // CHECK9-SAME: () #[[ATTR0]] comdat {
7696 // CHECK9-NEXT: entry:
7697 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2
7698 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
7699 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7700 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7701 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7702 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
7703 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2
7704 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7705 // CHECK9-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
7706 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7707 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
7708 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7709 // CHECK9: omp.inner.for.cond:
7710 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
7711 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15
7712 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
7713 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7714 // CHECK9: omp.inner.for.body:
7715 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
7716 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
7717 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7718 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
7719 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7720 // CHECK9: omp.body.continue:
7721 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7722 // CHECK9: omp.inner.for.inc:
7723 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
7724 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
7725 // CHECK9-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
7726 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
7727 // CHECK9: omp.inner.for.end:
7728 // CHECK9-NEXT: store i32 100, i32* [[I]], align 4
7729 // CHECK9-NEXT: ret i32 0
7730 //
7731 //
7732 // CHECK10-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
7733 // CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
7734 // CHECK10-NEXT: entry:
7735 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
7736 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
7737 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
7738 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
7739 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
7740 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7741 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7742 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7743 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
7744 // CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
7745 // CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
7746 // CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
7747 // CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
7748 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7749 // CHECK10-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
7750 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7751 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
7752 // CHECK10-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
7753 // CHECK10-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
7754 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7755 // CHECK10: omp.inner.for.cond:
7756 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7757 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
7758 // CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
7759 // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7760 // CHECK10: omp.inner.for.body:
7761 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7762 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
7763 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
7764 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
7765 // CHECK10-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
7766 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
7767 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
7768 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
7769 // CHECK10-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
7770 // CHECK10-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
7771 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
7772 // CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
7773 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
7774 // CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
7775 // CHECK10-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
7776 // CHECK10-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
7777 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
7778 // CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
7779 // CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
7780 // CHECK10-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
7781 // CHECK10-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
7782 // CHECK10-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
7783 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
7784 // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
7785 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
7786 // CHECK10-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
7787 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7788 // CHECK10: omp.body.continue:
7789 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7790 // CHECK10: omp.inner.for.inc:
7791 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7792 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
7793 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7794 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
7795 // CHECK10: omp.inner.for.end:
7796 // CHECK10-NEXT: store i32 32000001, i32* [[I]], align 4
7797 // CHECK10-NEXT: ret void
7798 //
7799 //
7800 // CHECK10-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
7801 // CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
7802 // CHECK10-NEXT: entry:
7803 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
7804 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
7805 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
7806 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
7807 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
7808 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7809 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7810 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7811 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
7812 // CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
7813 // CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
7814 // CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
7815 // CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
7816 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7817 // CHECK10-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
7818 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7819 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
7820 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7821 // CHECK10: omp.inner.for.cond:
7822 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7823 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7824 // CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
7825 // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7826 // CHECK10: omp.inner.for.body:
7827 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7828 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
7829 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
7830 // CHECK10-NEXT: store i32 [[SUB]], i32* [[I]], align 4
7831 // CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8
7832 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
7833 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
7834 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
7835 // CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
7836 // CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
7837 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
7838 // CHECK10-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
7839 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
7840 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
7841 // CHECK10-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
7842 // CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
7843 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
7844 // CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
7845 // CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
7846 // CHECK10-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
7847 // CHECK10-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
7848 // CHECK10-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8
7849 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
7850 // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
7851 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
7852 // CHECK10-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
7853 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7854 // CHECK10: omp.body.continue:
7855 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7856 // CHECK10: omp.inner.for.inc:
7857 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7858 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
7859 // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
7860 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
7861 // CHECK10: omp.inner.for.end:
7862 // CHECK10-NEXT: store i32 32, i32* [[I]], align 4
7863 // CHECK10-NEXT: ret void
7864 //
7865 //
7866 // CHECK10-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
7867 // CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
7868 // CHECK10-NEXT: entry:
7869 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
7870 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
7871 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
7872 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
7873 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
7874 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7875 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7876 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7877 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
7878 // CHECK10-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
7879 // CHECK10-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
7880 // CHECK10-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
7881 // CHECK10-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
7882 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7883 // CHECK10-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
7884 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7885 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
7886 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7887 // CHECK10: omp.inner.for.cond:
7888 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
7889 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
7890 // CHECK10-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
7891 // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7892 // CHECK10: omp.inner.for.body:
7893 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
7894 // CHECK10-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
7895 // CHECK10-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
7896 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
7897 // CHECK10-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !9
7898 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
7899 // CHECK10-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
7900 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
7901 // CHECK10-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
7902 // CHECK10-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !9
7903 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
7904 // CHECK10-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
7905 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
7906 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
7907 // CHECK10-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
7908 // CHECK10-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !9
7909 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
7910 // CHECK10-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
7911 // CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
7912 // CHECK10-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !9
7913 // CHECK10-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
7914 // CHECK10-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !9
7915 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
7916 // CHECK10-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
7917 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
7918 // CHECK10-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !9
7919 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7920 // CHECK10: omp.body.continue:
7921 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7922 // CHECK10: omp.inner.for.inc:
7923 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
7924 // CHECK10-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
7925 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
7926 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
7927 // CHECK10: omp.inner.for.end:
7928 // CHECK10-NEXT: store i32 -2147483522, i32* [[I]], align 4
7929 // CHECK10-NEXT: ret void
7930 //
7931 //
7932 // CHECK10-LABEL: define {{[^@]+}}@_Z12test_precondv
7933 // CHECK10-SAME: () #[[ATTR0]] {
7934 // CHECK10-NEXT: entry:
7935 // CHECK10-NEXT: [[A:%.*]] = alloca i8, align 1
7936 // CHECK10-NEXT: [[I:%.*]] = alloca i8, align 1
7937 // CHECK10-NEXT: [[TMP:%.*]] = alloca i8, align 1
7938 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7939 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
7940 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
7941 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
7942 // CHECK10-NEXT: [[I4:%.*]] = alloca i8, align 1
7943 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
7944 // CHECK10-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
7945 // CHECK10-NEXT: [[I6:%.*]] = alloca i8, align 1
7946 // CHECK10-NEXT: [[I7:%.*]] = alloca i8, align 1
7947 // CHECK10-NEXT: store i8 0, i8* [[A]], align 1
7948 // CHECK10-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
7949 // CHECK10-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
7950 // CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7951 // CHECK10-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
7952 // CHECK10-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
7953 // CHECK10-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
7954 // CHECK10-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
7955 // CHECK10-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
7956 // CHECK10-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
7957 // CHECK10-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
7958 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
7959 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
7960 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
7961 // CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7962 // CHECK10-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
7963 // CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7964 // CHECK10-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
7965 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
7966 // CHECK10-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
7967 // CHECK10: simd.if.then:
7968 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7969 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
7970 // CHECK10-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
7971 // CHECK10-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
7972 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
7973 // CHECK10: omp.inner.for.cond:
7974 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
7975 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
7976 // CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
7977 // CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7978 // CHECK10: omp.inner.for.body:
7979 // CHECK10-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !12
7980 // CHECK10-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
7981 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
7982 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
7983 // CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
7984 // CHECK10-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
7985 // CHECK10-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !12
7986 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
7987 // CHECK10: omp.body.continue:
7988 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
7989 // CHECK10: omp.inner.for.inc:
7990 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
7991 // CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
7992 // CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
7993 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
7994 // CHECK10: omp.inner.for.end:
7995 // CHECK10-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7996 // CHECK10-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
7997 // CHECK10-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
7998 // CHECK10-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
7999 // CHECK10-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
8000 // CHECK10-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
8001 // CHECK10-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
8002 // CHECK10-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
8003 // CHECK10-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
8004 // CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
8005 // CHECK10-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
8006 // CHECK10-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
8007 // CHECK10-NEXT: br label [[SIMD_IF_END]]
8008 // CHECK10: simd.if.end:
8009 // CHECK10-NEXT: ret void
8010 //
8011 //
8012 // CHECK10-LABEL: define {{[^@]+}}@_Z4fintv
8013 // CHECK10-SAME: () #[[ATTR0]] {
8014 // CHECK10-NEXT: entry:
8015 // CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
8016 // CHECK10-NEXT: ret i32 [[CALL]]
8017 //
8018 //
8019 // CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
8020 // CHECK10-SAME: () #[[ATTR0]] comdat {
8021 // CHECK10-NEXT: entry:
8022 // CHECK10-NEXT: [[AA:%.*]] = alloca i16, align 2
8023 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
8024 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8025 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8026 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8027 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
8028 // CHECK10-NEXT: store i16 0, i16* [[AA]], align 2
8029 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8030 // CHECK10-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
8031 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8032 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8033 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8034 // CHECK10: omp.inner.for.cond:
8035 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
8036 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15
8037 // CHECK10-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
8038 // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8039 // CHECK10: omp.inner.for.body:
8040 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
8041 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
8042 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8043 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
8044 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8045 // CHECK10: omp.body.continue:
8046 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8047 // CHECK10: omp.inner.for.inc:
8048 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
8049 // CHECK10-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
8050 // CHECK10-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
8051 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
8052 // CHECK10: omp.inner.for.end:
8053 // CHECK10-NEXT: store i32 100, i32* [[I]], align 4
8054 // CHECK10-NEXT: ret i32 0
8055 //
8056 //
8057 // CHECK11-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
8058 // CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
8059 // CHECK11-NEXT: entry:
8060 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
8061 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
8062 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
8063 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
8064 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
8065 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8066 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8067 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8068 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
8069 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
8070 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
8071 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
8072 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
8073 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8074 // CHECK11-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
8075 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8076 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8077 // CHECK11-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
8078 // CHECK11-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
8079 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8080 // CHECK11: omp.inner.for.cond:
8081 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8082 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
8083 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
8084 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8085 // CHECK11: omp.inner.for.body:
8086 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8087 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
8088 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
8089 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
8090 // CHECK11-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
8091 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
8092 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
8093 // CHECK11-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
8094 // CHECK11-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
8095 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
8096 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
8097 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
8098 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
8099 // CHECK11-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
8100 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
8101 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
8102 // CHECK11-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
8103 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
8104 // CHECK11-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
8105 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
8106 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
8107 // CHECK11-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
8108 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8109 // CHECK11: omp.body.continue:
8110 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8111 // CHECK11: omp.inner.for.inc:
8112 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8113 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
8114 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8115 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
8116 // CHECK11: omp.inner.for.end:
8117 // CHECK11-NEXT: store i32 32000001, i32* [[I]], align 4
8118 // CHECK11-NEXT: ret void
8119 //
8120 //
8121 // CHECK11-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
8122 // CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
8123 // CHECK11-NEXT: entry:
8124 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
8125 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
8126 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
8127 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
8128 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
8129 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8130 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8131 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8132 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
8133 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
8134 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
8135 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
8136 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
8137 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8138 // CHECK11-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
8139 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8140 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8141 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8142 // CHECK11: omp.inner.for.cond:
8143 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8144 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8145 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
8146 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8147 // CHECK11: omp.inner.for.body:
8148 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8149 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
8150 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
8151 // CHECK11-NEXT: store i32 [[SUB]], i32* [[I]], align 4
8152 // CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4
8153 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
8154 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
8155 // CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
8156 // CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
8157 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
8158 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
8159 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
8160 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
8161 // CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
8162 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
8163 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
8164 // CHECK11-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
8165 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
8166 // CHECK11-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4
8167 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
8168 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
8169 // CHECK11-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
8170 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8171 // CHECK11: omp.body.continue:
8172 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8173 // CHECK11: omp.inner.for.inc:
8174 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8175 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
8176 // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
8177 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
8178 // CHECK11: omp.inner.for.end:
8179 // CHECK11-NEXT: store i32 32, i32* [[I]], align 4
8180 // CHECK11-NEXT: ret void
8181 //
8182 //
8183 // CHECK11-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
8184 // CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
8185 // CHECK11-NEXT: entry:
8186 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
8187 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
8188 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
8189 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
8190 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
8191 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8192 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8193 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8194 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
8195 // CHECK11-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
8196 // CHECK11-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
8197 // CHECK11-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
8198 // CHECK11-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
8199 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8200 // CHECK11-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
8201 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8202 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8203 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8204 // CHECK11: omp.inner.for.cond:
8205 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8206 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
8207 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
8208 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8209 // CHECK11: omp.inner.for.body:
8210 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8211 // CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
8212 // CHECK11-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
8213 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
8214 // CHECK11-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !10
8215 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8216 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
8217 // CHECK11-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
8218 // CHECK11-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !10
8219 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8220 // CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
8221 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !10
8222 // CHECK11-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
8223 // CHECK11-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !10
8224 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8225 // CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
8226 // CHECK11-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10
8227 // CHECK11-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
8228 // CHECK11-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !10
8229 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8230 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
8231 // CHECK11-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
8232 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8233 // CHECK11: omp.body.continue:
8234 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8235 // CHECK11: omp.inner.for.inc:
8236 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8237 // CHECK11-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
8238 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8239 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
8240 // CHECK11: omp.inner.for.end:
8241 // CHECK11-NEXT: store i32 -2147483522, i32* [[I]], align 4
8242 // CHECK11-NEXT: ret void
8243 //
8244 //
8245 // CHECK11-LABEL: define {{[^@]+}}@_Z12test_precondv
8246 // CHECK11-SAME: () #[[ATTR0]] {
8247 // CHECK11-NEXT: entry:
8248 // CHECK11-NEXT: [[A:%.*]] = alloca i8, align 1
8249 // CHECK11-NEXT: [[I:%.*]] = alloca i8, align 1
8250 // CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1
8251 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
8252 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
8253 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8254 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8255 // CHECK11-NEXT: [[I4:%.*]] = alloca i8, align 1
8256 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8257 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
8258 // CHECK11-NEXT: [[I6:%.*]] = alloca i8, align 1
8259 // CHECK11-NEXT: [[I7:%.*]] = alloca i8, align 1
8260 // CHECK11-NEXT: store i8 0, i8* [[A]], align 1
8261 // CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
8262 // CHECK11-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
8263 // CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8264 // CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
8265 // CHECK11-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
8266 // CHECK11-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
8267 // CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
8268 // CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
8269 // CHECK11-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
8270 // CHECK11-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
8271 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8272 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
8273 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
8274 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8275 // CHECK11-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
8276 // CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8277 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
8278 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
8279 // CHECK11-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
8280 // CHECK11: simd.if.then:
8281 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8282 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
8283 // CHECK11-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
8284 // CHECK11-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
8285 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8286 // CHECK11: omp.inner.for.cond:
8287 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8288 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
8289 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
8290 // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8291 // CHECK11: omp.inner.for.body:
8292 // CHECK11-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
8293 // CHECK11-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
8294 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8295 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
8296 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
8297 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
8298 // CHECK11-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !13
8299 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8300 // CHECK11: omp.body.continue:
8301 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8302 // CHECK11: omp.inner.for.inc:
8303 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8304 // CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
8305 // CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8306 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
8307 // CHECK11: omp.inner.for.end:
8308 // CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8309 // CHECK11-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
8310 // CHECK11-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8311 // CHECK11-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
8312 // CHECK11-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
8313 // CHECK11-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
8314 // CHECK11-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
8315 // CHECK11-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
8316 // CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
8317 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
8318 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
8319 // CHECK11-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
8320 // CHECK11-NEXT: br label [[SIMD_IF_END]]
8321 // CHECK11: simd.if.end:
8322 // CHECK11-NEXT: ret void
8323 //
8324 //
8325 // CHECK11-LABEL: define {{[^@]+}}@_Z4fintv
8326 // CHECK11-SAME: () #[[ATTR0]] {
8327 // CHECK11-NEXT: entry:
8328 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
8329 // CHECK11-NEXT: ret i32 [[CALL]]
8330 //
8331 //
8332 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
8333 // CHECK11-SAME: () #[[ATTR0]] comdat {
8334 // CHECK11-NEXT: entry:
8335 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2
8336 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
8337 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8338 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8339 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8340 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
8341 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2
8342 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8343 // CHECK11-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
8344 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8345 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8346 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8347 // CHECK11: omp.inner.for.cond:
8348 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
8349 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16
8350 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
8351 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8352 // CHECK11: omp.inner.for.body:
8353 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
8354 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
8355 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8356 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
8357 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8358 // CHECK11: omp.body.continue:
8359 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8360 // CHECK11: omp.inner.for.inc:
8361 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
8362 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
8363 // CHECK11-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
8364 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
8365 // CHECK11: omp.inner.for.end:
8366 // CHECK11-NEXT: store i32 100, i32* [[I]], align 4
8367 // CHECK11-NEXT: ret i32 0
8368 //
8369 //
8370 // CHECK12-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
8371 // CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
8372 // CHECK12-NEXT: entry:
8373 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
8374 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
8375 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
8376 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
8377 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
8378 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8379 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8380 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8381 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
8382 // CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
8383 // CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
8384 // CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
8385 // CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
8386 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8387 // CHECK12-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
8388 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8389 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8390 // CHECK12-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
8391 // CHECK12-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
8392 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8393 // CHECK12: omp.inner.for.cond:
8394 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8395 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
8396 // CHECK12-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
8397 // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8398 // CHECK12: omp.inner.for.body:
8399 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8400 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
8401 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
8402 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
8403 // CHECK12-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
8404 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
8405 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
8406 // CHECK12-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
8407 // CHECK12-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
8408 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
8409 // CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
8410 // CHECK12-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
8411 // CHECK12-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
8412 // CHECK12-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
8413 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
8414 // CHECK12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
8415 // CHECK12-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
8416 // CHECK12-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
8417 // CHECK12-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
8418 // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
8419 // CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
8420 // CHECK12-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
8421 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8422 // CHECK12: omp.body.continue:
8423 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8424 // CHECK12: omp.inner.for.inc:
8425 // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8426 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
8427 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8428 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
8429 // CHECK12: omp.inner.for.end:
8430 // CHECK12-NEXT: store i32 32000001, i32* [[I]], align 4
8431 // CHECK12-NEXT: ret void
8432 //
8433 //
8434 // CHECK12-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
8435 // CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
8436 // CHECK12-NEXT: entry:
8437 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
8438 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
8439 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
8440 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
8441 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
8442 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8443 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8444 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8445 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
8446 // CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
8447 // CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
8448 // CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
8449 // CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
8450 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8451 // CHECK12-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
8452 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8453 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8454 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8455 // CHECK12: omp.inner.for.cond:
8456 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8457 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8458 // CHECK12-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
8459 // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8460 // CHECK12: omp.inner.for.body:
8461 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8462 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
8463 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
8464 // CHECK12-NEXT: store i32 [[SUB]], i32* [[I]], align 4
8465 // CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4
8466 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
8467 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
8468 // CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
8469 // CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
8470 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
8471 // CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
8472 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
8473 // CHECK12-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
8474 // CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
8475 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
8476 // CHECK12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
8477 // CHECK12-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
8478 // CHECK12-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
8479 // CHECK12-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4
8480 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
8481 // CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
8482 // CHECK12-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
8483 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8484 // CHECK12: omp.body.continue:
8485 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8486 // CHECK12: omp.inner.for.inc:
8487 // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8488 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
8489 // CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
8490 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
8491 // CHECK12: omp.inner.for.end:
8492 // CHECK12-NEXT: store i32 32, i32* [[I]], align 4
8493 // CHECK12-NEXT: ret void
8494 //
8495 //
8496 // CHECK12-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
8497 // CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
8498 // CHECK12-NEXT: entry:
8499 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
8500 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
8501 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
8502 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
8503 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
8504 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8505 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8506 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8507 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
8508 // CHECK12-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
8509 // CHECK12-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
8510 // CHECK12-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
8511 // CHECK12-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
8512 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8513 // CHECK12-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
8514 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8515 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8516 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8517 // CHECK12: omp.inner.for.cond:
8518 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8519 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
8520 // CHECK12-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
8521 // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8522 // CHECK12: omp.inner.for.body:
8523 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8524 // CHECK12-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
8525 // CHECK12-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
8526 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
8527 // CHECK12-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !10
8528 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8529 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
8530 // CHECK12-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
8531 // CHECK12-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !10
8532 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8533 // CHECK12-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
8534 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !10
8535 // CHECK12-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
8536 // CHECK12-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !10
8537 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8538 // CHECK12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
8539 // CHECK12-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10
8540 // CHECK12-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
8541 // CHECK12-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !10
8542 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8543 // CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
8544 // CHECK12-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
8545 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8546 // CHECK12: omp.body.continue:
8547 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8548 // CHECK12: omp.inner.for.inc:
8549 // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8550 // CHECK12-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
8551 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8552 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
8553 // CHECK12: omp.inner.for.end:
8554 // CHECK12-NEXT: store i32 -2147483522, i32* [[I]], align 4
8555 // CHECK12-NEXT: ret void
8556 //
8557 //
8558 // CHECK12-LABEL: define {{[^@]+}}@_Z12test_precondv
8559 // CHECK12-SAME: () #[[ATTR0]] {
8560 // CHECK12-NEXT: entry:
8561 // CHECK12-NEXT: [[A:%.*]] = alloca i8, align 1
8562 // CHECK12-NEXT: [[I:%.*]] = alloca i8, align 1
8563 // CHECK12-NEXT: [[TMP:%.*]] = alloca i8, align 1
8564 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
8565 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
8566 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8567 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8568 // CHECK12-NEXT: [[I4:%.*]] = alloca i8, align 1
8569 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8570 // CHECK12-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
8571 // CHECK12-NEXT: [[I6:%.*]] = alloca i8, align 1
8572 // CHECK12-NEXT: [[I7:%.*]] = alloca i8, align 1
8573 // CHECK12-NEXT: store i8 0, i8* [[A]], align 1
8574 // CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
8575 // CHECK12-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
8576 // CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8577 // CHECK12-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
8578 // CHECK12-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
8579 // CHECK12-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
8580 // CHECK12-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
8581 // CHECK12-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
8582 // CHECK12-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
8583 // CHECK12-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
8584 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8585 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
8586 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
8587 // CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8588 // CHECK12-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
8589 // CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8590 // CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
8591 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
8592 // CHECK12-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
8593 // CHECK12: simd.if.then:
8594 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8595 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
8596 // CHECK12-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
8597 // CHECK12-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
8598 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8599 // CHECK12: omp.inner.for.cond:
8600 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8601 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
8602 // CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
8603 // CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8604 // CHECK12: omp.inner.for.body:
8605 // CHECK12-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
8606 // CHECK12-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
8607 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8608 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
8609 // CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
8610 // CHECK12-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
8611 // CHECK12-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !13
8612 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8613 // CHECK12: omp.body.continue:
8614 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8615 // CHECK12: omp.inner.for.inc:
8616 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8617 // CHECK12-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
8618 // CHECK12-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8619 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
8620 // CHECK12: omp.inner.for.end:
8621 // CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8622 // CHECK12-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
8623 // CHECK12-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8624 // CHECK12-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
8625 // CHECK12-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
8626 // CHECK12-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
8627 // CHECK12-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
8628 // CHECK12-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
8629 // CHECK12-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
8630 // CHECK12-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
8631 // CHECK12-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
8632 // CHECK12-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
8633 // CHECK12-NEXT: br label [[SIMD_IF_END]]
8634 // CHECK12: simd.if.end:
8635 // CHECK12-NEXT: ret void
8636 //
8637 //
8638 // CHECK12-LABEL: define {{[^@]+}}@_Z4fintv
8639 // CHECK12-SAME: () #[[ATTR0]] {
8640 // CHECK12-NEXT: entry:
8641 // CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
8642 // CHECK12-NEXT: ret i32 [[CALL]]
8643 //
8644 //
8645 // CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
8646 // CHECK12-SAME: () #[[ATTR0]] comdat {
8647 // CHECK12-NEXT: entry:
8648 // CHECK12-NEXT: [[AA:%.*]] = alloca i16, align 2
8649 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
8650 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8651 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8652 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8653 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
8654 // CHECK12-NEXT: store i16 0, i16* [[AA]], align 2
8655 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8656 // CHECK12-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
8657 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8658 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8659 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8660 // CHECK12: omp.inner.for.cond:
8661 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
8662 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16
8663 // CHECK12-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
8664 // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8665 // CHECK12: omp.inner.for.body:
8666 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
8667 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
8668 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8669 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
8670 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8671 // CHECK12: omp.body.continue:
8672 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8673 // CHECK12: omp.inner.for.inc:
8674 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
8675 // CHECK12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
8676 // CHECK12-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
8677 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
8678 // CHECK12: omp.inner.for.end:
8679 // CHECK12-NEXT: store i32 100, i32* [[I]], align 4
8680 // CHECK12-NEXT: ret i32 0
8681 //
8682 //
8683 // CHECK13-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
8684 // CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
8685 // CHECK13-NEXT: entry:
8686 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
8687 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
8688 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
8689 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
8690 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
8691 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8692 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8693 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8694 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
8695 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
8696 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
8697 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
8698 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
8699 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8700 // CHECK13-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
8701 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8702 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8703 // CHECK13-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
8704 // CHECK13-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
8705 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8706 // CHECK13: omp.inner.for.cond:
8707 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
8708 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
8709 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
8710 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8711 // CHECK13: omp.inner.for.body:
8712 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
8713 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
8714 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
8715 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
8716 // CHECK13-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
8717 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
8718 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
8719 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
8720 // CHECK13-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
8721 // CHECK13-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
8722 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
8723 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
8724 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
8725 // CHECK13-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
8726 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
8727 // CHECK13-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
8728 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
8729 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
8730 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
8731 // CHECK13-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
8732 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
8733 // CHECK13-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
8734 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
8735 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
8736 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
8737 // CHECK13-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
8738 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8739 // CHECK13: omp.body.continue:
8740 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8741 // CHECK13: omp.inner.for.inc:
8742 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
8743 // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
8744 // CHECK13-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
8745 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
8746 // CHECK13: omp.inner.for.end:
8747 // CHECK13-NEXT: store i32 32000001, i32* [[I]], align 4
8748 // CHECK13-NEXT: ret void
8749 //
8750 //
8751 // CHECK13-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
8752 // CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
8753 // CHECK13-NEXT: entry:
8754 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
8755 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
8756 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
8757 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
8758 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
8759 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8760 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8761 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8762 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
8763 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
8764 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
8765 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
8766 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
8767 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8768 // CHECK13-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
8769 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8770 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8771 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8772 // CHECK13: omp.inner.for.cond:
8773 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8774 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8775 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
8776 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8777 // CHECK13: omp.inner.for.body:
8778 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8779 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
8780 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
8781 // CHECK13-NEXT: store i32 [[SUB]], i32* [[I]], align 4
8782 // CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !nontemporal !7
8783 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
8784 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
8785 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
8786 // CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
8787 // CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
8788 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
8789 // CHECK13-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
8790 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
8791 // CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
8792 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
8793 // CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
8794 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
8795 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
8796 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
8797 // CHECK13-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
8798 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
8799 // CHECK13-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !nontemporal !7
8800 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
8801 // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
8802 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
8803 // CHECK13-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
8804 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8805 // CHECK13: omp.body.continue:
8806 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8807 // CHECK13: omp.inner.for.inc:
8808 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8809 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
8810 // CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
8811 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
8812 // CHECK13: omp.inner.for.end:
8813 // CHECK13-NEXT: store i32 32, i32* [[I]], align 4
8814 // CHECK13-NEXT: ret void
8815 //
8816 //
8817 // CHECK13-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
8818 // CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
8819 // CHECK13-NEXT: entry:
8820 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
8821 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
8822 // CHECK13-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
8823 // CHECK13-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
8824 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
8825 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8826 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8827 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8828 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
8829 // CHECK13-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
8830 // CHECK13-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
8831 // CHECK13-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
8832 // CHECK13-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
8833 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8834 // CHECK13-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
8835 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8836 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8837 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8838 // CHECK13: omp.inner.for.cond:
8839 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8840 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
8841 // CHECK13-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
8842 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8843 // CHECK13: omp.inner.for.body:
8844 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8845 // CHECK13-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
8846 // CHECK13-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
8847 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
8848 // CHECK13-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !10
8849 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8850 // CHECK13-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
8851 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
8852 // CHECK13-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
8853 // CHECK13-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !10
8854 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8855 // CHECK13-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
8856 // CHECK13-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
8857 // CHECK13-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
8858 // CHECK13-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
8859 // CHECK13-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !10
8860 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8861 // CHECK13-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
8862 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
8863 // CHECK13-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
8864 // CHECK13-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
8865 // CHECK13-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !10
8866 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
8867 // CHECK13-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
8868 // CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
8869 // CHECK13-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !10
8870 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8871 // CHECK13: omp.body.continue:
8872 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8873 // CHECK13: omp.inner.for.inc:
8874 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8875 // CHECK13-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
8876 // CHECK13-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
8877 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
8878 // CHECK13: omp.inner.for.end:
8879 // CHECK13-NEXT: store i32 -2147483522, i32* [[I]], align 4
8880 // CHECK13-NEXT: ret void
8881 //
8882 //
8883 // CHECK13-LABEL: define {{[^@]+}}@_Z12test_precondv
8884 // CHECK13-SAME: () #[[ATTR0]] {
8885 // CHECK13-NEXT: entry:
8886 // CHECK13-NEXT: [[A:%.*]] = alloca i8, align 1
8887 // CHECK13-NEXT: [[I:%.*]] = alloca i8, align 1
8888 // CHECK13-NEXT: [[TMP:%.*]] = alloca i8, align 1
8889 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
8890 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
8891 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
8892 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
8893 // CHECK13-NEXT: [[I4:%.*]] = alloca i8, align 1
8894 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
8895 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
8896 // CHECK13-NEXT: [[I6:%.*]] = alloca i8, align 1
8897 // CHECK13-NEXT: [[I7:%.*]] = alloca i8, align 1
8898 // CHECK13-NEXT: store i8 0, i8* [[A]], align 1
8899 // CHECK13-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
8900 // CHECK13-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
8901 // CHECK13-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8902 // CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
8903 // CHECK13-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
8904 // CHECK13-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
8905 // CHECK13-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
8906 // CHECK13-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
8907 // CHECK13-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
8908 // CHECK13-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
8909 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
8910 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
8911 // CHECK13-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
8912 // CHECK13-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8913 // CHECK13-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
8914 // CHECK13-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8915 // CHECK13-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
8916 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
8917 // CHECK13-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
8918 // CHECK13: simd.if.then:
8919 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8920 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
8921 // CHECK13-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
8922 // CHECK13-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
8923 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
8924 // CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
8925 // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8926 // CHECK13: omp_if.then:
8927 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
8928 // CHECK13: omp.inner.for.cond:
8929 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8930 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
8931 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
8932 // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8933 // CHECK13: omp.inner.for.body:
8934 // CHECK13-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
8935 // CHECK13-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
8936 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8937 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
8938 // CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
8939 // CHECK13-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
8940 // CHECK13-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !7, !llvm.access.group !13
8941 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
8942 // CHECK13: omp.body.continue:
8943 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
8944 // CHECK13: omp.inner.for.inc:
8945 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8946 // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
8947 // CHECK13-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
8948 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
8949 // CHECK13: omp.inner.for.end:
8950 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]]
8951 // CHECK13: omp_if.else:
8952 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
8953 // CHECK13: omp.inner.for.cond13:
8954 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8955 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8956 // CHECK13-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
8957 // CHECK13-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
8958 // CHECK13: omp.inner.for.body15:
8959 // CHECK13-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8960 // CHECK13-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
8961 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8962 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
8963 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
8964 // CHECK13-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
8965 // CHECK13-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
8966 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
8967 // CHECK13: omp.body.continue20:
8968 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
8969 // CHECK13: omp.inner.for.inc21:
8970 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8971 // CHECK13-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
8972 // CHECK13-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
8973 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]]
8974 // CHECK13: omp.inner.for.end23:
8975 // CHECK13-NEXT: br label [[OMP_IF_END]]
8976 // CHECK13: omp_if.end:
8977 // CHECK13-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8978 // CHECK13-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
8979 // CHECK13-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8980 // CHECK13-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
8981 // CHECK13-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
8982 // CHECK13-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
8983 // CHECK13-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
8984 // CHECK13-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
8985 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
8986 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
8987 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
8988 // CHECK13-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
8989 // CHECK13-NEXT: br label [[SIMD_IF_END]]
8990 // CHECK13: simd.if.end:
8991 // CHECK13-NEXT: ret void
8992 //
8993 //
8994 // CHECK13-LABEL: define {{[^@]+}}@_Z4fintv
8995 // CHECK13-SAME: () #[[ATTR0]] {
8996 // CHECK13-NEXT: entry:
8997 // CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
8998 // CHECK13-NEXT: ret i32 [[CALL]]
8999 //
9000 //
9001 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
9002 // CHECK13-SAME: () #[[ATTR0]] comdat {
9003 // CHECK13-NEXT: entry:
9004 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2
9005 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
9006 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9007 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9008 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9009 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
9010 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2
9011 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9012 // CHECK13-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
9013 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9014 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9015 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9016 // CHECK13: omp.inner.for.cond:
9017 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
9018 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
9019 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9020 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9021 // CHECK13: omp.inner.for.body:
9022 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
9023 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
9024 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9025 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
9026 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9027 // CHECK13: omp.body.continue:
9028 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9029 // CHECK13: omp.inner.for.inc:
9030 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
9031 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
9032 // CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
9033 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
9034 // CHECK13: omp.inner.for.end:
9035 // CHECK13-NEXT: store i32 100, i32* [[I]], align 4
9036 // CHECK13-NEXT: ret i32 0
9037 //
9038 //
9039 // CHECK14-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
9040 // CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
9041 // CHECK14-NEXT: entry:
9042 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
9043 // CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
9044 // CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
9045 // CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
9046 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
9047 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9048 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9049 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9050 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
9051 // CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
9052 // CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
9053 // CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
9054 // CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
9055 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9056 // CHECK14-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
9057 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9058 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9059 // CHECK14-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
9060 // CHECK14-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
9061 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9062 // CHECK14: omp.inner.for.cond:
9063 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
9064 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
9065 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
9066 // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9067 // CHECK14: omp.inner.for.body:
9068 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
9069 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
9070 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
9071 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
9072 // CHECK14-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
9073 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
9074 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
9075 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
9076 // CHECK14-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
9077 // CHECK14-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
9078 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
9079 // CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
9080 // CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
9081 // CHECK14-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
9082 // CHECK14-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
9083 // CHECK14-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
9084 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
9085 // CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
9086 // CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
9087 // CHECK14-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
9088 // CHECK14-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
9089 // CHECK14-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
9090 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
9091 // CHECK14-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
9092 // CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
9093 // CHECK14-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
9094 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9095 // CHECK14: omp.body.continue:
9096 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9097 // CHECK14: omp.inner.for.inc:
9098 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
9099 // CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
9100 // CHECK14-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
9101 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
9102 // CHECK14: omp.inner.for.end:
9103 // CHECK14-NEXT: store i32 32000001, i32* [[I]], align 4
9104 // CHECK14-NEXT: ret void
9105 //
9106 //
9107 // CHECK14-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
9108 // CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
9109 // CHECK14-NEXT: entry:
9110 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
9111 // CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
9112 // CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
9113 // CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
9114 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
9115 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9116 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9117 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9118 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
9119 // CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
9120 // CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
9121 // CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
9122 // CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
9123 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9124 // CHECK14-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
9125 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9126 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9127 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9128 // CHECK14: omp.inner.for.cond:
9129 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9130 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9131 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9132 // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9133 // CHECK14: omp.inner.for.body:
9134 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9135 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
9136 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
9137 // CHECK14-NEXT: store i32 [[SUB]], i32* [[I]], align 4
9138 // CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !nontemporal !7
9139 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
9140 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
9141 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
9142 // CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
9143 // CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
9144 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
9145 // CHECK14-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
9146 // CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
9147 // CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
9148 // CHECK14-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
9149 // CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
9150 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
9151 // CHECK14-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
9152 // CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
9153 // CHECK14-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
9154 // CHECK14-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
9155 // CHECK14-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !nontemporal !7
9156 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
9157 // CHECK14-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
9158 // CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
9159 // CHECK14-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
9160 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9161 // CHECK14: omp.body.continue:
9162 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9163 // CHECK14: omp.inner.for.inc:
9164 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9165 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
9166 // CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
9167 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
9168 // CHECK14: omp.inner.for.end:
9169 // CHECK14-NEXT: store i32 32, i32* [[I]], align 4
9170 // CHECK14-NEXT: ret void
9171 //
9172 //
9173 // CHECK14-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
9174 // CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
9175 // CHECK14-NEXT: entry:
9176 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
9177 // CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
9178 // CHECK14-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
9179 // CHECK14-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
9180 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
9181 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9182 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9183 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9184 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
9185 // CHECK14-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
9186 // CHECK14-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
9187 // CHECK14-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
9188 // CHECK14-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
9189 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9190 // CHECK14-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
9191 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9192 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9193 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9194 // CHECK14: omp.inner.for.cond:
9195 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
9196 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
9197 // CHECK14-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
9198 // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9199 // CHECK14: omp.inner.for.body:
9200 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
9201 // CHECK14-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
9202 // CHECK14-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
9203 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
9204 // CHECK14-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !10
9205 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
9206 // CHECK14-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
9207 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
9208 // CHECK14-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
9209 // CHECK14-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !10
9210 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
9211 // CHECK14-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
9212 // CHECK14-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
9213 // CHECK14-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
9214 // CHECK14-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
9215 // CHECK14-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !10
9216 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
9217 // CHECK14-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
9218 // CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
9219 // CHECK14-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
9220 // CHECK14-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
9221 // CHECK14-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !10
9222 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
9223 // CHECK14-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
9224 // CHECK14-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
9225 // CHECK14-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !10
9226 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9227 // CHECK14: omp.body.continue:
9228 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9229 // CHECK14: omp.inner.for.inc:
9230 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
9231 // CHECK14-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
9232 // CHECK14-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
9233 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
9234 // CHECK14: omp.inner.for.end:
9235 // CHECK14-NEXT: store i32 -2147483522, i32* [[I]], align 4
9236 // CHECK14-NEXT: ret void
9237 //
9238 //
9239 // CHECK14-LABEL: define {{[^@]+}}@_Z12test_precondv
9240 // CHECK14-SAME: () #[[ATTR0]] {
9241 // CHECK14-NEXT: entry:
9242 // CHECK14-NEXT: [[A:%.*]] = alloca i8, align 1
9243 // CHECK14-NEXT: [[I:%.*]] = alloca i8, align 1
9244 // CHECK14-NEXT: [[TMP:%.*]] = alloca i8, align 1
9245 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
9246 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
9247 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9248 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9249 // CHECK14-NEXT: [[I4:%.*]] = alloca i8, align 1
9250 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9251 // CHECK14-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
9252 // CHECK14-NEXT: [[I6:%.*]] = alloca i8, align 1
9253 // CHECK14-NEXT: [[I7:%.*]] = alloca i8, align 1
9254 // CHECK14-NEXT: store i8 0, i8* [[A]], align 1
9255 // CHECK14-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
9256 // CHECK14-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
9257 // CHECK14-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9258 // CHECK14-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
9259 // CHECK14-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
9260 // CHECK14-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
9261 // CHECK14-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
9262 // CHECK14-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
9263 // CHECK14-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
9264 // CHECK14-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
9265 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9266 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
9267 // CHECK14-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
9268 // CHECK14-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9269 // CHECK14-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
9270 // CHECK14-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9271 // CHECK14-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
9272 // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
9273 // CHECK14-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
9274 // CHECK14: simd.if.then:
9275 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9276 // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
9277 // CHECK14-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
9278 // CHECK14-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
9279 // CHECK14-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
9280 // CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
9281 // CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9282 // CHECK14: omp_if.then:
9283 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9284 // CHECK14: omp.inner.for.cond:
9285 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
9286 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
9287 // CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
9288 // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9289 // CHECK14: omp.inner.for.body:
9290 // CHECK14-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
9291 // CHECK14-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
9292 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
9293 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
9294 // CHECK14-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
9295 // CHECK14-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
9296 // CHECK14-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !7, !llvm.access.group !13
9297 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9298 // CHECK14: omp.body.continue:
9299 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9300 // CHECK14: omp.inner.for.inc:
9301 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
9302 // CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
9303 // CHECK14-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
9304 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
9305 // CHECK14: omp.inner.for.end:
9306 // CHECK14-NEXT: br label [[OMP_IF_END:%.*]]
9307 // CHECK14: omp_if.else:
9308 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
9309 // CHECK14: omp.inner.for.cond13:
9310 // CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9311 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9312 // CHECK14-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
9313 // CHECK14-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
9314 // CHECK14: omp.inner.for.body15:
9315 // CHECK14-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9316 // CHECK14-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
9317 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9318 // CHECK14-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
9319 // CHECK14-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
9320 // CHECK14-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
9321 // CHECK14-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
9322 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
9323 // CHECK14: omp.body.continue20:
9324 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
9325 // CHECK14: omp.inner.for.inc21:
9326 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9327 // CHECK14-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
9328 // CHECK14-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
9329 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]]
9330 // CHECK14: omp.inner.for.end23:
9331 // CHECK14-NEXT: br label [[OMP_IF_END]]
9332 // CHECK14: omp_if.end:
9333 // CHECK14-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9334 // CHECK14-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
9335 // CHECK14-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9336 // CHECK14-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
9337 // CHECK14-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
9338 // CHECK14-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
9339 // CHECK14-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
9340 // CHECK14-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
9341 // CHECK14-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
9342 // CHECK14-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
9343 // CHECK14-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
9344 // CHECK14-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
9345 // CHECK14-NEXT: br label [[SIMD_IF_END]]
9346 // CHECK14: simd.if.end:
9347 // CHECK14-NEXT: ret void
9348 //
9349 //
9350 // CHECK14-LABEL: define {{[^@]+}}@_Z4fintv
9351 // CHECK14-SAME: () #[[ATTR0]] {
9352 // CHECK14-NEXT: entry:
9353 // CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
9354 // CHECK14-NEXT: ret i32 [[CALL]]
9355 //
9356 //
9357 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
9358 // CHECK14-SAME: () #[[ATTR0]] comdat {
9359 // CHECK14-NEXT: entry:
9360 // CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2
9361 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4
9362 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9363 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9364 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9365 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4
9366 // CHECK14-NEXT: store i16 0, i16* [[AA]], align 2
9367 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9368 // CHECK14-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
9369 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9370 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9371 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9372 // CHECK14: omp.inner.for.cond:
9373 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
9374 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
9375 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9376 // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9377 // CHECK14: omp.inner.for.body:
9378 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
9379 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
9380 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9381 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
9382 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9383 // CHECK14: omp.body.continue:
9384 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9385 // CHECK14: omp.inner.for.inc:
9386 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
9387 // CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
9388 // CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
9389 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
9390 // CHECK14: omp.inner.for.end:
9391 // CHECK14-NEXT: store i32 100, i32* [[I]], align 4
9392 // CHECK14-NEXT: ret i32 0
9393 //
9394 //
9395 // CHECK15-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
9396 // CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
9397 // CHECK15-NEXT: entry:
9398 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
9399 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
9400 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
9401 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
9402 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
9403 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9404 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9405 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9406 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
9407 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
9408 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
9409 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
9410 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
9411 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9412 // CHECK15-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
9413 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9414 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9415 // CHECK15-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
9416 // CHECK15-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
9417 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9418 // CHECK15: omp.inner.for.cond:
9419 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9420 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
9421 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
9422 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9423 // CHECK15: omp.inner.for.body:
9424 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9425 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
9426 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
9427 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
9428 // CHECK15-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
9429 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
9430 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
9431 // CHECK15-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
9432 // CHECK15-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
9433 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
9434 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
9435 // CHECK15-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
9436 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
9437 // CHECK15-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
9438 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
9439 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
9440 // CHECK15-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
9441 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
9442 // CHECK15-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
9443 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
9444 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
9445 // CHECK15-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
9446 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9447 // CHECK15: omp.body.continue:
9448 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9449 // CHECK15: omp.inner.for.inc:
9450 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9451 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
9452 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9453 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
9454 // CHECK15: omp.inner.for.end:
9455 // CHECK15-NEXT: store i32 32000001, i32* [[I]], align 4
9456 // CHECK15-NEXT: ret void
9457 //
9458 //
9459 // CHECK15-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
9460 // CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
9461 // CHECK15-NEXT: entry:
9462 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
9463 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
9464 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
9465 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
9466 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
9467 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9468 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9469 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9470 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
9471 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
9472 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
9473 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
9474 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
9475 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9476 // CHECK15-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
9477 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9478 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9479 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9480 // CHECK15: omp.inner.for.cond:
9481 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9482 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9483 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9484 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9485 // CHECK15: omp.inner.for.body:
9486 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9487 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
9488 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
9489 // CHECK15-NEXT: store i32 [[SUB]], i32* [[I]], align 4
9490 // CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !nontemporal !8
9491 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
9492 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
9493 // CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
9494 // CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
9495 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
9496 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
9497 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
9498 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
9499 // CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
9500 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
9501 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
9502 // CHECK15-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
9503 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
9504 // CHECK15-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !nontemporal !8
9505 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
9506 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
9507 // CHECK15-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
9508 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9509 // CHECK15: omp.body.continue:
9510 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9511 // CHECK15: omp.inner.for.inc:
9512 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9513 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
9514 // CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
9515 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
9516 // CHECK15: omp.inner.for.end:
9517 // CHECK15-NEXT: store i32 32, i32* [[I]], align 4
9518 // CHECK15-NEXT: ret void
9519 //
9520 //
9521 // CHECK15-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
9522 // CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
9523 // CHECK15-NEXT: entry:
9524 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
9525 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
9526 // CHECK15-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
9527 // CHECK15-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
9528 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
9529 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9530 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9531 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9532 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
9533 // CHECK15-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
9534 // CHECK15-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
9535 // CHECK15-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
9536 // CHECK15-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
9537 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9538 // CHECK15-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
9539 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9540 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9541 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9542 // CHECK15: omp.inner.for.cond:
9543 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9544 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
9545 // CHECK15-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
9546 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9547 // CHECK15: omp.inner.for.body:
9548 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9549 // CHECK15-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
9550 // CHECK15-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
9551 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
9552 // CHECK15-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !11
9553 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
9554 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
9555 // CHECK15-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11
9556 // CHECK15-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !11
9557 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
9558 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
9559 // CHECK15-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !11
9560 // CHECK15-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
9561 // CHECK15-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !11
9562 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
9563 // CHECK15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
9564 // CHECK15-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11
9565 // CHECK15-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
9566 // CHECK15-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !11
9567 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
9568 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
9569 // CHECK15-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !11
9570 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9571 // CHECK15: omp.body.continue:
9572 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9573 // CHECK15: omp.inner.for.inc:
9574 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9575 // CHECK15-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
9576 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9577 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
9578 // CHECK15: omp.inner.for.end:
9579 // CHECK15-NEXT: store i32 -2147483522, i32* [[I]], align 4
9580 // CHECK15-NEXT: ret void
9581 //
9582 //
9583 // CHECK15-LABEL: define {{[^@]+}}@_Z12test_precondv
9584 // CHECK15-SAME: () #[[ATTR0]] {
9585 // CHECK15-NEXT: entry:
9586 // CHECK15-NEXT: [[A:%.*]] = alloca i8, align 1
9587 // CHECK15-NEXT: [[I:%.*]] = alloca i8, align 1
9588 // CHECK15-NEXT: [[TMP:%.*]] = alloca i8, align 1
9589 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
9590 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
9591 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9592 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9593 // CHECK15-NEXT: [[I4:%.*]] = alloca i8, align 1
9594 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9595 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
9596 // CHECK15-NEXT: [[I6:%.*]] = alloca i8, align 1
9597 // CHECK15-NEXT: [[I7:%.*]] = alloca i8, align 1
9598 // CHECK15-NEXT: store i8 0, i8* [[A]], align 1
9599 // CHECK15-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
9600 // CHECK15-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
9601 // CHECK15-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9602 // CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
9603 // CHECK15-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
9604 // CHECK15-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
9605 // CHECK15-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
9606 // CHECK15-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
9607 // CHECK15-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
9608 // CHECK15-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
9609 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9610 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
9611 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
9612 // CHECK15-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9613 // CHECK15-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
9614 // CHECK15-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9615 // CHECK15-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
9616 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
9617 // CHECK15-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
9618 // CHECK15: simd.if.then:
9619 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9620 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
9621 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
9622 // CHECK15-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
9623 // CHECK15-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
9624 // CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
9625 // CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9626 // CHECK15: omp_if.then:
9627 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9628 // CHECK15: omp.inner.for.cond:
9629 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
9630 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14
9631 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
9632 // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9633 // CHECK15: omp.inner.for.body:
9634 // CHECK15-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !14
9635 // CHECK15-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
9636 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
9637 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
9638 // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
9639 // CHECK15-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
9640 // CHECK15-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !8, !llvm.access.group !14
9641 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9642 // CHECK15: omp.body.continue:
9643 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9644 // CHECK15: omp.inner.for.inc:
9645 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
9646 // CHECK15-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
9647 // CHECK15-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
9648 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
9649 // CHECK15: omp.inner.for.end:
9650 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]]
9651 // CHECK15: omp_if.else:
9652 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
9653 // CHECK15: omp.inner.for.cond13:
9654 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9655 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9656 // CHECK15-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
9657 // CHECK15-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
9658 // CHECK15: omp.inner.for.body15:
9659 // CHECK15-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9660 // CHECK15-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
9661 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9662 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
9663 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
9664 // CHECK15-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
9665 // CHECK15-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
9666 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
9667 // CHECK15: omp.body.continue20:
9668 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
9669 // CHECK15: omp.inner.for.inc21:
9670 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9671 // CHECK15-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
9672 // CHECK15-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
9673 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]]
9674 // CHECK15: omp.inner.for.end23:
9675 // CHECK15-NEXT: br label [[OMP_IF_END]]
9676 // CHECK15: omp_if.end:
9677 // CHECK15-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9678 // CHECK15-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
9679 // CHECK15-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9680 // CHECK15-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
9681 // CHECK15-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
9682 // CHECK15-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
9683 // CHECK15-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
9684 // CHECK15-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
9685 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
9686 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
9687 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
9688 // CHECK15-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
9689 // CHECK15-NEXT: br label [[SIMD_IF_END]]
9690 // CHECK15: simd.if.end:
9691 // CHECK15-NEXT: ret void
9692 //
9693 //
9694 // CHECK15-LABEL: define {{[^@]+}}@_Z4fintv
9695 // CHECK15-SAME: () #[[ATTR0]] {
9696 // CHECK15-NEXT: entry:
9697 // CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
9698 // CHECK15-NEXT: ret i32 [[CALL]]
9699 //
9700 //
9701 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
9702 // CHECK15-SAME: () #[[ATTR0]] comdat {
9703 // CHECK15-NEXT: entry:
9704 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2
9705 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
9706 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9707 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9708 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9709 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
9710 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2
9711 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9712 // CHECK15-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
9713 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9714 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9715 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9716 // CHECK15: omp.inner.for.cond:
9717 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
9718 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
9719 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9720 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9721 // CHECK15: omp.inner.for.body:
9722 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
9723 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
9724 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9725 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
9726 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9727 // CHECK15: omp.body.continue:
9728 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9729 // CHECK15: omp.inner.for.inc:
9730 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
9731 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
9732 // CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
9733 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
9734 // CHECK15: omp.inner.for.end:
9735 // CHECK15-NEXT: store i32 100, i32* [[I]], align 4
9736 // CHECK15-NEXT: ret i32 0
9737 //
9738 //
9739 // CHECK16-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
9740 // CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
9741 // CHECK16-NEXT: entry:
9742 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
9743 // CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
9744 // CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
9745 // CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
9746 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
9747 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9748 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9749 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9750 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
9751 // CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
9752 // CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
9753 // CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
9754 // CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
9755 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9756 // CHECK16-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
9757 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9758 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9759 // CHECK16-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
9760 // CHECK16-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
9761 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9762 // CHECK16: omp.inner.for.cond:
9763 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9764 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
9765 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
9766 // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9767 // CHECK16: omp.inner.for.body:
9768 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9769 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
9770 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
9771 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
9772 // CHECK16-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
9773 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
9774 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
9775 // CHECK16-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
9776 // CHECK16-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
9777 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
9778 // CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
9779 // CHECK16-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
9780 // CHECK16-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
9781 // CHECK16-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
9782 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
9783 // CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
9784 // CHECK16-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
9785 // CHECK16-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
9786 // CHECK16-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
9787 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
9788 // CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
9789 // CHECK16-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
9790 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9791 // CHECK16: omp.body.continue:
9792 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9793 // CHECK16: omp.inner.for.inc:
9794 // CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9795 // CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
9796 // CHECK16-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9797 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
9798 // CHECK16: omp.inner.for.end:
9799 // CHECK16-NEXT: store i32 32000001, i32* [[I]], align 4
9800 // CHECK16-NEXT: ret void
9801 //
9802 //
9803 // CHECK16-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
9804 // CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
9805 // CHECK16-NEXT: entry:
9806 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
9807 // CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
9808 // CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
9809 // CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
9810 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
9811 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9812 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9813 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9814 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
9815 // CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
9816 // CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
9817 // CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
9818 // CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
9819 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9820 // CHECK16-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
9821 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9822 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9823 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9824 // CHECK16: omp.inner.for.cond:
9825 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9826 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9827 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9828 // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9829 // CHECK16: omp.inner.for.body:
9830 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9831 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
9832 // CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
9833 // CHECK16-NEXT: store i32 [[SUB]], i32* [[I]], align 4
9834 // CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !nontemporal !8
9835 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
9836 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
9837 // CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
9838 // CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
9839 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
9840 // CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
9841 // CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
9842 // CHECK16-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
9843 // CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
9844 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
9845 // CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
9846 // CHECK16-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
9847 // CHECK16-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
9848 // CHECK16-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !nontemporal !8
9849 // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
9850 // CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
9851 // CHECK16-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
9852 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9853 // CHECK16: omp.body.continue:
9854 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9855 // CHECK16: omp.inner.for.inc:
9856 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9857 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
9858 // CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
9859 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
9860 // CHECK16: omp.inner.for.end:
9861 // CHECK16-NEXT: store i32 32, i32* [[I]], align 4
9862 // CHECK16-NEXT: ret void
9863 //
9864 //
9865 // CHECK16-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
9866 // CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
9867 // CHECK16-NEXT: entry:
9868 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
9869 // CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
9870 // CHECK16-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
9871 // CHECK16-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
9872 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
9873 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9874 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9875 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9876 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
9877 // CHECK16-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
9878 // CHECK16-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
9879 // CHECK16-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
9880 // CHECK16-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
9881 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9882 // CHECK16-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
9883 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9884 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9885 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9886 // CHECK16: omp.inner.for.cond:
9887 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9888 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
9889 // CHECK16-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
9890 // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9891 // CHECK16: omp.inner.for.body:
9892 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9893 // CHECK16-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
9894 // CHECK16-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
9895 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
9896 // CHECK16-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !11
9897 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
9898 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
9899 // CHECK16-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11
9900 // CHECK16-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !11
9901 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
9902 // CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
9903 // CHECK16-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !11
9904 // CHECK16-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
9905 // CHECK16-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !11
9906 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
9907 // CHECK16-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
9908 // CHECK16-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11
9909 // CHECK16-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
9910 // CHECK16-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !11
9911 // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
9912 // CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
9913 // CHECK16-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !11
9914 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9915 // CHECK16: omp.body.continue:
9916 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9917 // CHECK16: omp.inner.for.inc:
9918 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9919 // CHECK16-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
9920 // CHECK16-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9921 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
9922 // CHECK16: omp.inner.for.end:
9923 // CHECK16-NEXT: store i32 -2147483522, i32* [[I]], align 4
9924 // CHECK16-NEXT: ret void
9925 //
9926 //
9927 // CHECK16-LABEL: define {{[^@]+}}@_Z12test_precondv
9928 // CHECK16-SAME: () #[[ATTR0]] {
9929 // CHECK16-NEXT: entry:
9930 // CHECK16-NEXT: [[A:%.*]] = alloca i8, align 1
9931 // CHECK16-NEXT: [[I:%.*]] = alloca i8, align 1
9932 // CHECK16-NEXT: [[TMP:%.*]] = alloca i8, align 1
9933 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
9934 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
9935 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
9936 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
9937 // CHECK16-NEXT: [[I4:%.*]] = alloca i8, align 1
9938 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
9939 // CHECK16-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
9940 // CHECK16-NEXT: [[I6:%.*]] = alloca i8, align 1
9941 // CHECK16-NEXT: [[I7:%.*]] = alloca i8, align 1
9942 // CHECK16-NEXT: store i8 0, i8* [[A]], align 1
9943 // CHECK16-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
9944 // CHECK16-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
9945 // CHECK16-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9946 // CHECK16-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
9947 // CHECK16-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
9948 // CHECK16-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
9949 // CHECK16-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
9950 // CHECK16-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
9951 // CHECK16-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
9952 // CHECK16-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
9953 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
9954 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
9955 // CHECK16-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
9956 // CHECK16-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9957 // CHECK16-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
9958 // CHECK16-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9959 // CHECK16-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
9960 // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
9961 // CHECK16-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
9962 // CHECK16: simd.if.then:
9963 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9964 // CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
9965 // CHECK16-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
9966 // CHECK16-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
9967 // CHECK16-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
9968 // CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
9969 // CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9970 // CHECK16: omp_if.then:
9971 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
9972 // CHECK16: omp.inner.for.cond:
9973 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
9974 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14
9975 // CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
9976 // CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9977 // CHECK16: omp.inner.for.body:
9978 // CHECK16-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !14
9979 // CHECK16-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
9980 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
9981 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
9982 // CHECK16-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
9983 // CHECK16-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
9984 // CHECK16-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !8, !llvm.access.group !14
9985 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
9986 // CHECK16: omp.body.continue:
9987 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
9988 // CHECK16: omp.inner.for.inc:
9989 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
9990 // CHECK16-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
9991 // CHECK16-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
9992 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
9993 // CHECK16: omp.inner.for.end:
9994 // CHECK16-NEXT: br label [[OMP_IF_END:%.*]]
9995 // CHECK16: omp_if.else:
9996 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
9997 // CHECK16: omp.inner.for.cond13:
9998 // CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9999 // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10000 // CHECK16-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
10001 // CHECK16-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
10002 // CHECK16: omp.inner.for.body15:
10003 // CHECK16-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
10004 // CHECK16-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
10005 // CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10006 // CHECK16-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
10007 // CHECK16-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
10008 // CHECK16-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
10009 // CHECK16-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
10010 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
10011 // CHECK16: omp.body.continue20:
10012 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
10013 // CHECK16: omp.inner.for.inc21:
10014 // CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10015 // CHECK16-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
10016 // CHECK16-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
10017 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]]
10018 // CHECK16: omp.inner.for.end23:
10019 // CHECK16-NEXT: br label [[OMP_IF_END]]
10020 // CHECK16: omp_if.end:
10021 // CHECK16-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
10022 // CHECK16-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
10023 // CHECK16-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
10024 // CHECK16-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
10025 // CHECK16-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
10026 // CHECK16-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
10027 // CHECK16-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
10028 // CHECK16-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
10029 // CHECK16-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
10030 // CHECK16-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
10031 // CHECK16-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
10032 // CHECK16-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
10033 // CHECK16-NEXT: br label [[SIMD_IF_END]]
10034 // CHECK16: simd.if.end:
10035 // CHECK16-NEXT: ret void
10036 //
10037 //
10038 // CHECK16-LABEL: define {{[^@]+}}@_Z4fintv
10039 // CHECK16-SAME: () #[[ATTR0]] {
10040 // CHECK16-NEXT: entry:
10041 // CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
10042 // CHECK16-NEXT: ret i32 [[CALL]]
10043 //
10044 //
10045 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
10046 // CHECK16-SAME: () #[[ATTR0]] comdat {
10047 // CHECK16-NEXT: entry:
10048 // CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2
10049 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4
10050 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
10051 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
10052 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
10053 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4
10054 // CHECK16-NEXT: store i16 0, i16* [[AA]], align 2
10055 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
10056 // CHECK16-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
10057 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10058 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
10059 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
10060 // CHECK16: omp.inner.for.cond:
10061 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
10062 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
10063 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
10064 // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10065 // CHECK16: omp.inner.for.body:
10066 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
10067 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
10068 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10069 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
10070 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
10071 // CHECK16: omp.body.continue:
10072 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
10073 // CHECK16: omp.inner.for.inc:
10074 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
10075 // CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
10076 // CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
10077 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
10078 // CHECK16: omp.inner.for.end:
10079 // CHECK16-NEXT: store i32 100, i32* [[I]], align 4
10080 // CHECK16-NEXT: ret i32 0
10081 //
10082 //
10083 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
10084 // CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
10085 // CHECK17-NEXT: entry:
10086 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
10087 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
10088 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
10089 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
10090 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
10091 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
10092 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
10093 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
10094 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
10095 // CHECK17-NEXT: ret void
10096 //
10097 //
10098 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
10099 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
10100 // CHECK17-NEXT: entry:
10101 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10102 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10103 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
10104 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
10105 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
10106 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
10107 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
10108 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
10109 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
10110 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
10111 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10112 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10113 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
10114 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10115 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10116 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
10117 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
10118 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
10119 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
10120 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
10121 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
10122 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
10123 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
10124 // CHECK17-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
10125 // CHECK17-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
10126 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
10127 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
10128 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10129 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10130 // CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10131 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
10132 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10133 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10134 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
10135 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10136 // CHECK17: cond.true:
10137 // CHECK17-NEXT: br label [[COND_END:%.*]]
10138 // CHECK17: cond.false:
10139 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10140 // CHECK17-NEXT: br label [[COND_END]]
10141 // CHECK17: cond.end:
10142 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
10143 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10144 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10145 // CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
10146 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
10147 // CHECK17: omp.inner.for.cond:
10148 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
10149 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
10150 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
10151 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10152 // CHECK17: omp.inner.for.body:
10153 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
10154 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
10155 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
10156 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
10157 // CHECK17-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9
10158 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
10159 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
10160 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
10161 // CHECK17-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
10162 // CHECK17-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9
10163 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
10164 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
10165 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
10166 // CHECK17-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9
10167 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
10168 // CHECK17-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9
10169 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
10170 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
10171 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
10172 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
10173 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
10174 // CHECK17-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9
10175 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
10176 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
10177 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
10178 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
10179 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
10180 // CHECK17: omp.body.continue:
10181 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
10182 // CHECK17: omp.inner.for.inc:
10183 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
10184 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
10185 // CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
10186 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
10187 // CHECK17: omp.inner.for.end:
10188 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
10189 // CHECK17: omp.loop.exit:
10190 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
10191 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10192 // CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
10193 // CHECK17-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10194 // CHECK17: .omp.final.then:
10195 // CHECK17-NEXT: store i32 32000001, i32* [[I]], align 4
10196 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
10197 // CHECK17: .omp.final.done:
10198 // CHECK17-NEXT: ret void
10199 //
10200 //
10201 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
10202 // CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
10203 // CHECK17-NEXT: entry:
10204 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
10205 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
10206 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
10207 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
10208 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
10209 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
10210 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
10211 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
10212 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
10213 // CHECK17-NEXT: ret void
10214 //
10215 //
10216 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
10217 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
10218 // CHECK17-NEXT: entry:
10219 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10220 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10221 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
10222 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
10223 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
10224 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
10225 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
10226 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
10227 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
10228 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
10229 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10230 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10231 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
10232 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10233 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10234 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
10235 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
10236 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
10237 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
10238 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
10239 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
10240 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
10241 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
10242 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
10243 // CHECK17-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
10244 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10245 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10246 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10247 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
10248 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10249 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10250 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
10251 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10252 // CHECK17: cond.true:
10253 // CHECK17-NEXT: br label [[COND_END:%.*]]
10254 // CHECK17: cond.false:
10255 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10256 // CHECK17-NEXT: br label [[COND_END]]
10257 // CHECK17: cond.end:
10258 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10259 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10260 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10261 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
10262 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
10263 // CHECK17: omp.inner.for.cond:
10264 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10265 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10266 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
10267 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10268 // CHECK17: omp.inner.for.body:
10269 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10270 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
10271 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
10272 // CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4
10273 // CHECK17-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8
10274 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
10275 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
10276 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
10277 // CHECK17-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
10278 // CHECK17-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
10279 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
10280 // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
10281 // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
10282 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
10283 // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
10284 // CHECK17-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
10285 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
10286 // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
10287 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
10288 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
10289 // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
10290 // CHECK17-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8
10291 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
10292 // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
10293 // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
10294 // CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
10295 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
10296 // CHECK17: omp.body.continue:
10297 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
10298 // CHECK17: omp.inner.for.inc:
10299 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10300 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
10301 // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
10302 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
10303 // CHECK17: omp.inner.for.end:
10304 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
10305 // CHECK17: omp.loop.exit:
10306 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
10307 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10308 // CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
10309 // CHECK17-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10310 // CHECK17: .omp.final.then:
10311 // CHECK17-NEXT: store i32 32, i32* [[I]], align 4
10312 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
10313 // CHECK17: .omp.final.done:
10314 // CHECK17-NEXT: ret void
10315 //
10316 //
10317 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
10318 // CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
10319 // CHECK17-NEXT: entry:
10320 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
10321 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
10322 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
10323 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
10324 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
10325 // CHECK17-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
10326 // CHECK17-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
10327 // CHECK17-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
10328 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
10329 // CHECK17-NEXT: ret void
10330 //
10331 //
10332 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
10333 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
10334 // CHECK17-NEXT: entry:
10335 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10336 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10337 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
10338 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
10339 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
10340 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
10341 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
10342 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
10343 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
10344 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
10345 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10346 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10347 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
10348 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10349 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10350 // CHECK17-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
10351 // CHECK17-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
10352 // CHECK17-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
10353 // CHECK17-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
10354 // CHECK17-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
10355 // CHECK17-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
10356 // CHECK17-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
10357 // CHECK17-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
10358 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
10359 // CHECK17-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
10360 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10361 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10362 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10363 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
10364 // CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
10365 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
10366 // CHECK17: omp.dispatch.cond:
10367 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10368 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
10369 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10370 // CHECK17: cond.true:
10371 // CHECK17-NEXT: br label [[COND_END:%.*]]
10372 // CHECK17: cond.false:
10373 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10374 // CHECK17-NEXT: br label [[COND_END]]
10375 // CHECK17: cond.end:
10376 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10377 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10378 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10379 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
10380 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10381 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10382 // CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
10383 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
10384 // CHECK17: omp.dispatch.body:
10385 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
10386 // CHECK17: omp.inner.for.cond:
10387 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10388 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
10389 // CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
10390 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10391 // CHECK17: omp.inner.for.body:
10392 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10393 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
10394 // CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
10395 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
10396 // CHECK17-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !18
10397 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
10398 // CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
10399 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
10400 // CHECK17-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18
10401 // CHECK17-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !18
10402 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
10403 // CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
10404 // CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
10405 // CHECK17-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !18
10406 // CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
10407 // CHECK17-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !18
10408 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
10409 // CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
10410 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
10411 // CHECK17-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
10412 // CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
10413 // CHECK17-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !18
10414 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
10415 // CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
10416 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
10417 // CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
10418 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
10419 // CHECK17: omp.body.continue:
10420 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
10421 // CHECK17: omp.inner.for.inc:
10422 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10423 // CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
10424 // CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10425 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
10426 // CHECK17: omp.inner.for.end:
10427 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
10428 // CHECK17: omp.dispatch.inc:
10429 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10430 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10431 // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
10432 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
10433 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10434 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10435 // CHECK17-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
10436 // CHECK17-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
10437 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
10438 // CHECK17: omp.dispatch.end:
10439 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
10440 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10441 // CHECK17-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
10442 // CHECK17-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10443 // CHECK17: .omp.final.then:
10444 // CHECK17-NEXT: store i32 -2147483522, i32* [[I]], align 4
10445 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
10446 // CHECK17: .omp.final.done:
10447 // CHECK17-NEXT: ret void
10448 //
10449 //
10450 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
10451 // CHECK17-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
10452 // CHECK17-NEXT: entry:
10453 // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
10454 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
10455 // CHECK17-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
10456 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
10457 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
10458 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
10459 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
10460 // CHECK17-NEXT: ret void
10461 //
10462 //
10463 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
10464 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
10465 // CHECK17-NEXT: entry:
10466 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10467 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10468 // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
10469 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
10470 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
10471 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1
10472 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
10473 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
10474 // CHECK17-NEXT: [[I4:%.*]] = alloca i8, align 1
10475 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
10476 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
10477 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10478 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10479 // CHECK17-NEXT: [[I6:%.*]] = alloca i8, align 1
10480 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10481 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10482 // CHECK17-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
10483 // CHECK17-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
10484 // CHECK17-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
10485 // CHECK17-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
10486 // CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
10487 // CHECK17-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
10488 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
10489 // CHECK17-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
10490 // CHECK17-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
10491 // CHECK17-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
10492 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
10493 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
10494 // CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
10495 // CHECK17-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
10496 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
10497 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
10498 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
10499 // CHECK17-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
10500 // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
10501 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
10502 // CHECK17: omp.precond.then:
10503 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
10504 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
10505 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
10506 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10507 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10508 // CHECK17-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10509 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
10510 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10511 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10512 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
10513 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
10514 // CHECK17-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10515 // CHECK17: cond.true:
10516 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
10517 // CHECK17-NEXT: br label [[COND_END:%.*]]
10518 // CHECK17: cond.false:
10519 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10520 // CHECK17-NEXT: br label [[COND_END]]
10521 // CHECK17: cond.end:
10522 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
10523 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10524 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10525 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
10526 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
10527 // CHECK17: omp.inner.for.cond:
10528 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
10529 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
10530 // CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
10531 // CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10532 // CHECK17: omp.inner.for.body:
10533 // CHECK17-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
10534 // CHECK17-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
10535 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
10536 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
10537 // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
10538 // CHECK17-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
10539 // CHECK17-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
10540 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
10541 // CHECK17: omp.body.continue:
10542 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
10543 // CHECK17: omp.inner.for.inc:
10544 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
10545 // CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
10546 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
10547 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
10548 // CHECK17: omp.inner.for.end:
10549 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
10550 // CHECK17: omp.loop.exit:
10551 // CHECK17-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10552 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
10553 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
10554 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10555 // CHECK17-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
10556 // CHECK17-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10557 // CHECK17: .omp.final.then:
10558 // CHECK17-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
10559 // CHECK17-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
10560 // CHECK17-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
10561 // CHECK17-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
10562 // CHECK17-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
10563 // CHECK17-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
10564 // CHECK17-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
10565 // CHECK17-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
10566 // CHECK17-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
10567 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
10568 // CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
10569 // CHECK17-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
10570 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
10571 // CHECK17: .omp.final.done:
10572 // CHECK17-NEXT: br label [[OMP_PRECOND_END]]
10573 // CHECK17: omp.precond.end:
10574 // CHECK17-NEXT: ret void
10575 //
10576 //
10577 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
10578 // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
10579 // CHECK17-NEXT: entry:
10580 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
10581 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
10582 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10583 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
10584 // CHECK17-NEXT: ret void
10585 //
10586 //
10587 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
10588 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
10589 // CHECK17-NEXT: entry:
10590 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10591 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10592 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
10593 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
10594 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
10595 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
10596 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
10597 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10598 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10599 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
10600 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10601 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10602 // CHECK17-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
10603 // CHECK17-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
10604 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
10605 // CHECK17-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
10606 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10607 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10608 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
10609 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
10610 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10611 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
10612 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
10613 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
10614 // CHECK17: omp.dispatch.cond:
10615 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10616 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
10617 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10618 // CHECK17: cond.true:
10619 // CHECK17-NEXT: br label [[COND_END:%.*]]
10620 // CHECK17: cond.false:
10621 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10622 // CHECK17-NEXT: br label [[COND_END]]
10623 // CHECK17: cond.end:
10624 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
10625 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10626 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10627 // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
10628 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10629 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10630 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
10631 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
10632 // CHECK17: omp.dispatch.body:
10633 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
10634 // CHECK17: omp.inner.for.cond:
10635 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
10636 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
10637 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
10638 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10639 // CHECK17: omp.inner.for.body:
10640 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
10641 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
10642 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10643 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
10644 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
10645 // CHECK17: omp.body.continue:
10646 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
10647 // CHECK17: omp.inner.for.inc:
10648 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
10649 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
10650 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
10651 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
10652 // CHECK17: omp.inner.for.end:
10653 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
10654 // CHECK17: omp.dispatch.inc:
10655 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10656 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10657 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
10658 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
10659 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10660 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10661 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
10662 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
10663 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
10664 // CHECK17: omp.dispatch.end:
10665 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
10666 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10667 // CHECK17-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
10668 // CHECK17-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10669 // CHECK17: .omp.final.then:
10670 // CHECK17-NEXT: store i32 100, i32* [[I]], align 4
10671 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]]
10672 // CHECK17: .omp.final.done:
10673 // CHECK17-NEXT: ret void
10674 //
10675 //
10676 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
10677 // CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
10678 // CHECK18-NEXT: entry:
10679 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
10680 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
10681 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
10682 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
10683 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
10684 // CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
10685 // CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
10686 // CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
10687 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
10688 // CHECK18-NEXT: ret void
10689 //
10690 //
10691 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
10692 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
10693 // CHECK18-NEXT: entry:
10694 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10695 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10696 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
10697 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
10698 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
10699 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
10700 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
10701 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4
10702 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
10703 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
10704 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10705 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10706 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4
10707 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10708 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10709 // CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
10710 // CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
10711 // CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
10712 // CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
10713 // CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
10714 // CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
10715 // CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
10716 // CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
10717 // CHECK18-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
10718 // CHECK18-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
10719 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
10720 // CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
10721 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10722 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10723 // CHECK18-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10724 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
10725 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10726 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10727 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
10728 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10729 // CHECK18: cond.true:
10730 // CHECK18-NEXT: br label [[COND_END:%.*]]
10731 // CHECK18: cond.false:
10732 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10733 // CHECK18-NEXT: br label [[COND_END]]
10734 // CHECK18: cond.end:
10735 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
10736 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10737 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10738 // CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
10739 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
10740 // CHECK18: omp.inner.for.cond:
10741 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
10742 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
10743 // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
10744 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10745 // CHECK18: omp.inner.for.body:
10746 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
10747 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
10748 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
10749 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
10750 // CHECK18-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9
10751 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
10752 // CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
10753 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
10754 // CHECK18-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
10755 // CHECK18-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9
10756 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
10757 // CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
10758 // CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
10759 // CHECK18-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9
10760 // CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
10761 // CHECK18-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9
10762 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
10763 // CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
10764 // CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
10765 // CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
10766 // CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
10767 // CHECK18-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9
10768 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
10769 // CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
10770 // CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
10771 // CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
10772 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
10773 // CHECK18: omp.body.continue:
10774 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
10775 // CHECK18: omp.inner.for.inc:
10776 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
10777 // CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
10778 // CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
10779 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
10780 // CHECK18: omp.inner.for.end:
10781 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
10782 // CHECK18: omp.loop.exit:
10783 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
10784 // CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10785 // CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
10786 // CHECK18-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10787 // CHECK18: .omp.final.then:
10788 // CHECK18-NEXT: store i32 32000001, i32* [[I]], align 4
10789 // CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
10790 // CHECK18: .omp.final.done:
10791 // CHECK18-NEXT: ret void
10792 //
10793 //
10794 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
10795 // CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
10796 // CHECK18-NEXT: entry:
10797 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
10798 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
10799 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
10800 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
10801 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
10802 // CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
10803 // CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
10804 // CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
10805 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
10806 // CHECK18-NEXT: ret void
10807 //
10808 //
10809 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
10810 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
10811 // CHECK18-NEXT: entry:
10812 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10813 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10814 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
10815 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
10816 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
10817 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
10818 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
10819 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4
10820 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
10821 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
10822 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10823 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10824 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4
10825 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10826 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10827 // CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
10828 // CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
10829 // CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
10830 // CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
10831 // CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
10832 // CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
10833 // CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
10834 // CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
10835 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
10836 // CHECK18-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
10837 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10838 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10839 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10840 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
10841 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10842 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10843 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
10844 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10845 // CHECK18: cond.true:
10846 // CHECK18-NEXT: br label [[COND_END:%.*]]
10847 // CHECK18: cond.false:
10848 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10849 // CHECK18-NEXT: br label [[COND_END]]
10850 // CHECK18: cond.end:
10851 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10852 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10853 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10854 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
10855 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
10856 // CHECK18: omp.inner.for.cond:
10857 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10858 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10859 // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
10860 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10861 // CHECK18: omp.inner.for.body:
10862 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10863 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
10864 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
10865 // CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4
10866 // CHECK18-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8
10867 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
10868 // CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
10869 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
10870 // CHECK18-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
10871 // CHECK18-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
10872 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
10873 // CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
10874 // CHECK18-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
10875 // CHECK18-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
10876 // CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
10877 // CHECK18-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
10878 // CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
10879 // CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
10880 // CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
10881 // CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
10882 // CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
10883 // CHECK18-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8
10884 // CHECK18-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
10885 // CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
10886 // CHECK18-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
10887 // CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
10888 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
10889 // CHECK18: omp.body.continue:
10890 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
10891 // CHECK18: omp.inner.for.inc:
10892 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10893 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
10894 // CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
10895 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
10896 // CHECK18: omp.inner.for.end:
10897 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
10898 // CHECK18: omp.loop.exit:
10899 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
10900 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10901 // CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
10902 // CHECK18-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10903 // CHECK18: .omp.final.then:
10904 // CHECK18-NEXT: store i32 32, i32* [[I]], align 4
10905 // CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
10906 // CHECK18: .omp.final.done:
10907 // CHECK18-NEXT: ret void
10908 //
10909 //
10910 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
10911 // CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
10912 // CHECK18-NEXT: entry:
10913 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
10914 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
10915 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
10916 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
10917 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
10918 // CHECK18-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
10919 // CHECK18-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
10920 // CHECK18-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
10921 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
10922 // CHECK18-NEXT: ret void
10923 //
10924 //
10925 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
10926 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
10927 // CHECK18-NEXT: entry:
10928 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10929 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10930 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
10931 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
10932 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
10933 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
10934 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
10935 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4
10936 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
10937 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
10938 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10939 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10940 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4
10941 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10942 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10943 // CHECK18-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
10944 // CHECK18-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
10945 // CHECK18-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
10946 // CHECK18-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
10947 // CHECK18-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
10948 // CHECK18-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
10949 // CHECK18-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
10950 // CHECK18-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
10951 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
10952 // CHECK18-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
10953 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10954 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10955 // CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10956 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
10957 // CHECK18-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
10958 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
10959 // CHECK18: omp.dispatch.cond:
10960 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10961 // CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
10962 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10963 // CHECK18: cond.true:
10964 // CHECK18-NEXT: br label [[COND_END:%.*]]
10965 // CHECK18: cond.false:
10966 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10967 // CHECK18-NEXT: br label [[COND_END]]
10968 // CHECK18: cond.end:
10969 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10970 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10971 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10972 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
10973 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10974 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10975 // CHECK18-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
10976 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
10977 // CHECK18: omp.dispatch.body:
10978 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
10979 // CHECK18: omp.inner.for.cond:
10980 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10981 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
10982 // CHECK18-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
10983 // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10984 // CHECK18: omp.inner.for.body:
10985 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10986 // CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
10987 // CHECK18-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
10988 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
10989 // CHECK18-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !18
10990 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
10991 // CHECK18-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
10992 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
10993 // CHECK18-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !18
10994 // CHECK18-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !18
10995 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
10996 // CHECK18-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
10997 // CHECK18-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
10998 // CHECK18-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !18
10999 // CHECK18-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
11000 // CHECK18-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !18
11001 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
11002 // CHECK18-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
11003 // CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
11004 // CHECK18-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
11005 // CHECK18-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
11006 // CHECK18-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !18
11007 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18
11008 // CHECK18-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
11009 // CHECK18-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
11010 // CHECK18-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
11011 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
11012 // CHECK18: omp.body.continue:
11013 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
11014 // CHECK18: omp.inner.for.inc:
11015 // CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
11016 // CHECK18-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
11017 // CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
11018 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
11019 // CHECK18: omp.inner.for.end:
11020 // CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
11021 // CHECK18: omp.dispatch.inc:
11022 // CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11023 // CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11024 // CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
11025 // CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
11026 // CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11027 // CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11028 // CHECK18-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
11029 // CHECK18-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
11030 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
11031 // CHECK18: omp.dispatch.end:
11032 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
11033 // CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11034 // CHECK18-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
11035 // CHECK18-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11036 // CHECK18: .omp.final.then:
11037 // CHECK18-NEXT: store i32 -2147483522, i32* [[I]], align 4
11038 // CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
11039 // CHECK18: .omp.final.done:
11040 // CHECK18-NEXT: ret void
11041 //
11042 //
11043 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
11044 // CHECK18-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
11045 // CHECK18-NEXT: entry:
11046 // CHECK18-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
11047 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
11048 // CHECK18-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
11049 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
11050 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
11051 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
11052 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
11053 // CHECK18-NEXT: ret void
11054 //
11055 //
11056 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
11057 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
11058 // CHECK18-NEXT: entry:
11059 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
11060 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
11061 // CHECK18-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
11062 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
11063 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
11064 // CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1
11065 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
11066 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
11067 // CHECK18-NEXT: [[I4:%.*]] = alloca i8, align 1
11068 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
11069 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
11070 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11071 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11072 // CHECK18-NEXT: [[I6:%.*]] = alloca i8, align 1
11073 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
11074 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
11075 // CHECK18-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
11076 // CHECK18-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
11077 // CHECK18-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
11078 // CHECK18-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
11079 // CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
11080 // CHECK18-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
11081 // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11082 // CHECK18-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
11083 // CHECK18-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
11084 // CHECK18-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
11085 // CHECK18-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
11086 // CHECK18-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
11087 // CHECK18-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
11088 // CHECK18-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
11089 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11090 // CHECK18-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
11091 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11092 // CHECK18-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
11093 // CHECK18-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
11094 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
11095 // CHECK18: omp.precond.then:
11096 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
11097 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
11098 // CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
11099 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11100 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11101 // CHECK18-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
11102 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
11103 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11104 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11105 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
11106 // CHECK18-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
11107 // CHECK18-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11108 // CHECK18: cond.true:
11109 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
11110 // CHECK18-NEXT: br label [[COND_END:%.*]]
11111 // CHECK18: cond.false:
11112 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11113 // CHECK18-NEXT: br label [[COND_END]]
11114 // CHECK18: cond.end:
11115 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
11116 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11117 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11118 // CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
11119 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
11120 // CHECK18: omp.inner.for.cond:
11121 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
11122 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
11123 // CHECK18-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
11124 // CHECK18-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11125 // CHECK18: omp.inner.for.body:
11126 // CHECK18-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
11127 // CHECK18-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
11128 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
11129 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
11130 // CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
11131 // CHECK18-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
11132 // CHECK18-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
11133 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
11134 // CHECK18: omp.body.continue:
11135 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
11136 // CHECK18: omp.inner.for.inc:
11137 // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
11138 // CHECK18-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
11139 // CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
11140 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
11141 // CHECK18: omp.inner.for.end:
11142 // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
11143 // CHECK18: omp.loop.exit:
11144 // CHECK18-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
11145 // CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
11146 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
11147 // CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11148 // CHECK18-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
11149 // CHECK18-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11150 // CHECK18: .omp.final.then:
11151 // CHECK18-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11152 // CHECK18-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
11153 // CHECK18-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11154 // CHECK18-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
11155 // CHECK18-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
11156 // CHECK18-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
11157 // CHECK18-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
11158 // CHECK18-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
11159 // CHECK18-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
11160 // CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
11161 // CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
11162 // CHECK18-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
11163 // CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
11164 // CHECK18: .omp.final.done:
11165 // CHECK18-NEXT: br label [[OMP_PRECOND_END]]
11166 // CHECK18: omp.precond.end:
11167 // CHECK18-NEXT: ret void
11168 //
11169 //
11170 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
11171 // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
11172 // CHECK18-NEXT: entry:
11173 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
11174 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
11175 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
11176 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
11177 // CHECK18-NEXT: ret void
11178 //
11179 //
11180 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
11181 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
11182 // CHECK18-NEXT: entry:
11183 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
11184 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
11185 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
11186 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
11187 // CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4
11188 // CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
11189 // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
11190 // CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11191 // CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11192 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4
11193 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
11194 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
11195 // CHECK18-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
11196 // CHECK18-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
11197 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
11198 // CHECK18-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
11199 // CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11200 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11201 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
11202 // CHECK18-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
11203 // CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
11204 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
11205 // CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
11206 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
11207 // CHECK18: omp.dispatch.cond:
11208 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11209 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
11210 // CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11211 // CHECK18: cond.true:
11212 // CHECK18-NEXT: br label [[COND_END:%.*]]
11213 // CHECK18: cond.false:
11214 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11215 // CHECK18-NEXT: br label [[COND_END]]
11216 // CHECK18: cond.end:
11217 // CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
11218 // CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11219 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11220 // CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
11221 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11222 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11223 // CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
11224 // CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
11225 // CHECK18: omp.dispatch.body:
11226 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
11227 // CHECK18: omp.inner.for.cond:
11228 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
11229 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
11230 // CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
11231 // CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11232 // CHECK18: omp.inner.for.body:
11233 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
11234 // CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
11235 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11236 // CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
11237 // CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
11238 // CHECK18: omp.body.continue:
11239 // CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
11240 // CHECK18: omp.inner.for.inc:
11241 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
11242 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
11243 // CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
11244 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
11245 // CHECK18: omp.inner.for.end:
11246 // CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
11247 // CHECK18: omp.dispatch.inc:
11248 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11249 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11250 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
11251 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
11252 // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11253 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11254 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
11255 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
11256 // CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
11257 // CHECK18: omp.dispatch.end:
11258 // CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
11259 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11260 // CHECK18-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
11261 // CHECK18-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11262 // CHECK18: .omp.final.then:
11263 // CHECK18-NEXT: store i32 100, i32* [[I]], align 4
11264 // CHECK18-NEXT: br label [[DOTOMP_FINAL_DONE]]
11265 // CHECK18: .omp.final.done:
11266 // CHECK18-NEXT: ret void
11267 //
11268 //
11269 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
11270 // CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
11271 // CHECK19-NEXT: entry:
11272 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
11273 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
11274 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
11275 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
11276 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
11277 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
11278 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
11279 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
11280 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
11281 // CHECK19-NEXT: ret void
11282 //
11283 //
11284 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
11285 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
11286 // CHECK19-NEXT: entry:
11287 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11288 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11289 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
11290 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
11291 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
11292 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
11293 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
11294 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
11295 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
11296 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
11297 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11298 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11299 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
11300 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11301 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11302 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
11303 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
11304 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
11305 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
11306 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
11307 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
11308 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
11309 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
11310 // CHECK19-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
11311 // CHECK19-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
11312 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
11313 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
11314 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11315 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11316 // CHECK19-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11317 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
11318 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11319 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11320 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
11321 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11322 // CHECK19: cond.true:
11323 // CHECK19-NEXT: br label [[COND_END:%.*]]
11324 // CHECK19: cond.false:
11325 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11326 // CHECK19-NEXT: br label [[COND_END]]
11327 // CHECK19: cond.end:
11328 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
11329 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11330 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11331 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
11332 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
11333 // CHECK19: omp.inner.for.cond:
11334 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
11335 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
11336 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
11337 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11338 // CHECK19: omp.inner.for.body:
11339 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
11340 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
11341 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
11342 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
11343 // CHECK19-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10
11344 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
11345 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
11346 // CHECK19-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
11347 // CHECK19-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10
11348 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
11349 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
11350 // CHECK19-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
11351 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
11352 // CHECK19-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10
11353 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
11354 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
11355 // CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10
11356 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
11357 // CHECK19-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10
11358 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
11359 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
11360 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
11361 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
11362 // CHECK19: omp.body.continue:
11363 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
11364 // CHECK19: omp.inner.for.inc:
11365 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
11366 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
11367 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
11368 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
11369 // CHECK19: omp.inner.for.end:
11370 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
11371 // CHECK19: omp.loop.exit:
11372 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
11373 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11374 // CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
11375 // CHECK19-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11376 // CHECK19: .omp.final.then:
11377 // CHECK19-NEXT: store i32 32000001, i32* [[I]], align 4
11378 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
11379 // CHECK19: .omp.final.done:
11380 // CHECK19-NEXT: ret void
11381 //
11382 //
11383 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
11384 // CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
11385 // CHECK19-NEXT: entry:
11386 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
11387 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
11388 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
11389 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
11390 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
11391 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
11392 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
11393 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
11394 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
11395 // CHECK19-NEXT: ret void
11396 //
11397 //
11398 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
11399 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
11400 // CHECK19-NEXT: entry:
11401 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11402 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11403 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
11404 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
11405 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
11406 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
11407 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
11408 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
11409 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
11410 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
11411 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11412 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11413 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
11414 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11415 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11416 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
11417 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
11418 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
11419 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
11420 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
11421 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
11422 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
11423 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
11424 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
11425 // CHECK19-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
11426 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11427 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11428 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11429 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
11430 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11431 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11432 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
11433 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11434 // CHECK19: cond.true:
11435 // CHECK19-NEXT: br label [[COND_END:%.*]]
11436 // CHECK19: cond.false:
11437 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11438 // CHECK19-NEXT: br label [[COND_END]]
11439 // CHECK19: cond.end:
11440 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
11441 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11442 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11443 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
11444 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
11445 // CHECK19: omp.inner.for.cond:
11446 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11447 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11448 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
11449 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11450 // CHECK19: omp.inner.for.body:
11451 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11452 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
11453 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
11454 // CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4
11455 // CHECK19-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4
11456 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
11457 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
11458 // CHECK19-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
11459 // CHECK19-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
11460 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
11461 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
11462 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
11463 // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
11464 // CHECK19-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
11465 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
11466 // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
11467 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
11468 // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
11469 // CHECK19-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4
11470 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
11471 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
11472 // CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
11473 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
11474 // CHECK19: omp.body.continue:
11475 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
11476 // CHECK19: omp.inner.for.inc:
11477 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11478 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
11479 // CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
11480 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
11481 // CHECK19: omp.inner.for.end:
11482 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
11483 // CHECK19: omp.loop.exit:
11484 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
11485 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11486 // CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
11487 // CHECK19-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11488 // CHECK19: .omp.final.then:
11489 // CHECK19-NEXT: store i32 32, i32* [[I]], align 4
11490 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
11491 // CHECK19: .omp.final.done:
11492 // CHECK19-NEXT: ret void
11493 //
11494 //
11495 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
11496 // CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
11497 // CHECK19-NEXT: entry:
11498 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
11499 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
11500 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
11501 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
11502 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
11503 // CHECK19-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
11504 // CHECK19-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
11505 // CHECK19-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
11506 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
11507 // CHECK19-NEXT: ret void
11508 //
11509 //
11510 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
11511 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
11512 // CHECK19-NEXT: entry:
11513 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11514 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11515 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
11516 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
11517 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
11518 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
11519 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
11520 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
11521 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
11522 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
11523 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11524 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11525 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
11526 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11527 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11528 // CHECK19-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
11529 // CHECK19-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
11530 // CHECK19-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
11531 // CHECK19-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
11532 // CHECK19-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
11533 // CHECK19-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
11534 // CHECK19-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
11535 // CHECK19-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
11536 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
11537 // CHECK19-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
11538 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11539 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11540 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11541 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
11542 // CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
11543 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
11544 // CHECK19: omp.dispatch.cond:
11545 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11546 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
11547 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11548 // CHECK19: cond.true:
11549 // CHECK19-NEXT: br label [[COND_END:%.*]]
11550 // CHECK19: cond.false:
11551 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11552 // CHECK19-NEXT: br label [[COND_END]]
11553 // CHECK19: cond.end:
11554 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
11555 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11556 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11557 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
11558 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11559 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11560 // CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
11561 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
11562 // CHECK19: omp.dispatch.body:
11563 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
11564 // CHECK19: omp.inner.for.cond:
11565 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
11566 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
11567 // CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
11568 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11569 // CHECK19: omp.inner.for.body:
11570 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
11571 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
11572 // CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
11573 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
11574 // CHECK19-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !19
11575 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
11576 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
11577 // CHECK19-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19
11578 // CHECK19-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !19
11579 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
11580 // CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
11581 // CHECK19-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !19
11582 // CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
11583 // CHECK19-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !19
11584 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
11585 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
11586 // CHECK19-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !19
11587 // CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
11588 // CHECK19-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !19
11589 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
11590 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
11591 // CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
11592 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
11593 // CHECK19: omp.body.continue:
11594 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
11595 // CHECK19: omp.inner.for.inc:
11596 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
11597 // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
11598 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
11599 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
11600 // CHECK19: omp.inner.for.end:
11601 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
11602 // CHECK19: omp.dispatch.inc:
11603 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11604 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11605 // CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
11606 // CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
11607 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11608 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11609 // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
11610 // CHECK19-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
11611 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
11612 // CHECK19: omp.dispatch.end:
11613 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
11614 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11615 // CHECK19-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
11616 // CHECK19-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11617 // CHECK19: .omp.final.then:
11618 // CHECK19-NEXT: store i32 -2147483522, i32* [[I]], align 4
11619 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
11620 // CHECK19: .omp.final.done:
11621 // CHECK19-NEXT: ret void
11622 //
11623 //
11624 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
11625 // CHECK19-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
11626 // CHECK19-NEXT: entry:
11627 // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
11628 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
11629 // CHECK19-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
11630 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
11631 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
11632 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
11633 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
11634 // CHECK19-NEXT: ret void
11635 //
11636 //
11637 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
11638 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
11639 // CHECK19-NEXT: entry:
11640 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11641 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11642 // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
11643 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
11644 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
11645 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1
11646 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
11647 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
11648 // CHECK19-NEXT: [[I4:%.*]] = alloca i8, align 1
11649 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
11650 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
11651 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11652 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11653 // CHECK19-NEXT: [[I6:%.*]] = alloca i8, align 1
11654 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11655 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11656 // CHECK19-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
11657 // CHECK19-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
11658 // CHECK19-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
11659 // CHECK19-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
11660 // CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
11661 // CHECK19-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
11662 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11663 // CHECK19-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
11664 // CHECK19-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
11665 // CHECK19-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
11666 // CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
11667 // CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
11668 // CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
11669 // CHECK19-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
11670 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11671 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
11672 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11673 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
11674 // CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
11675 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
11676 // CHECK19: omp.precond.then:
11677 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
11678 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
11679 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
11680 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11681 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11682 // CHECK19-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11683 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
11684 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11685 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11686 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
11687 // CHECK19-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
11688 // CHECK19-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11689 // CHECK19: cond.true:
11690 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
11691 // CHECK19-NEXT: br label [[COND_END:%.*]]
11692 // CHECK19: cond.false:
11693 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11694 // CHECK19-NEXT: br label [[COND_END]]
11695 // CHECK19: cond.end:
11696 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
11697 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11698 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11699 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
11700 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
11701 // CHECK19: omp.inner.for.cond:
11702 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
11703 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
11704 // CHECK19-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
11705 // CHECK19-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11706 // CHECK19: omp.inner.for.body:
11707 // CHECK19-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
11708 // CHECK19-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
11709 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
11710 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
11711 // CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
11712 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
11713 // CHECK19-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !22
11714 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
11715 // CHECK19: omp.body.continue:
11716 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
11717 // CHECK19: omp.inner.for.inc:
11718 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
11719 // CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
11720 // CHECK19-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
11721 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
11722 // CHECK19: omp.inner.for.end:
11723 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
11724 // CHECK19: omp.loop.exit:
11725 // CHECK19-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11726 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
11727 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
11728 // CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11729 // CHECK19-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
11730 // CHECK19-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11731 // CHECK19: .omp.final.then:
11732 // CHECK19-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11733 // CHECK19-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
11734 // CHECK19-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11735 // CHECK19-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
11736 // CHECK19-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
11737 // CHECK19-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
11738 // CHECK19-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
11739 // CHECK19-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
11740 // CHECK19-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
11741 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
11742 // CHECK19-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
11743 // CHECK19-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
11744 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
11745 // CHECK19: .omp.final.done:
11746 // CHECK19-NEXT: br label [[OMP_PRECOND_END]]
11747 // CHECK19: omp.precond.end:
11748 // CHECK19-NEXT: ret void
11749 //
11750 //
11751 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
11752 // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
11753 // CHECK19-NEXT: entry:
11754 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
11755 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
11756 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11757 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
11758 // CHECK19-NEXT: ret void
11759 //
11760 //
11761 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
11762 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
11763 // CHECK19-NEXT: entry:
11764 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11765 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11766 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
11767 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
11768 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
11769 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
11770 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
11771 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11772 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11773 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
11774 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11775 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11776 // CHECK19-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
11777 // CHECK19-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
11778 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
11779 // CHECK19-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
11780 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11781 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11782 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
11783 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
11784 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11785 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
11786 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
11787 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
11788 // CHECK19: omp.dispatch.cond:
11789 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11790 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
11791 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11792 // CHECK19: cond.true:
11793 // CHECK19-NEXT: br label [[COND_END:%.*]]
11794 // CHECK19: cond.false:
11795 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11796 // CHECK19-NEXT: br label [[COND_END]]
11797 // CHECK19: cond.end:
11798 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
11799 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11800 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11801 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
11802 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11803 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11804 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
11805 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
11806 // CHECK19: omp.dispatch.body:
11807 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
11808 // CHECK19: omp.inner.for.cond:
11809 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
11810 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
11811 // CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
11812 // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11813 // CHECK19: omp.inner.for.body:
11814 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
11815 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
11816 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11817 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
11818 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
11819 // CHECK19: omp.body.continue:
11820 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
11821 // CHECK19: omp.inner.for.inc:
11822 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
11823 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
11824 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
11825 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
11826 // CHECK19: omp.inner.for.end:
11827 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
11828 // CHECK19: omp.dispatch.inc:
11829 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11830 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11831 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
11832 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
11833 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11834 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11835 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
11836 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
11837 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
11838 // CHECK19: omp.dispatch.end:
11839 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
11840 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11841 // CHECK19-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
11842 // CHECK19-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11843 // CHECK19: .omp.final.then:
11844 // CHECK19-NEXT: store i32 100, i32* [[I]], align 4
11845 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]]
11846 // CHECK19: .omp.final.done:
11847 // CHECK19-NEXT: ret void
11848 //
11849 //
11850 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
11851 // CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
11852 // CHECK20-NEXT: entry:
11853 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
11854 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
11855 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
11856 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
11857 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
11858 // CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
11859 // CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
11860 // CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
11861 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
11862 // CHECK20-NEXT: ret void
11863 //
11864 //
11865 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
11866 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
11867 // CHECK20-NEXT: entry:
11868 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11869 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11870 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
11871 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
11872 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
11873 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
11874 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
11875 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4
11876 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
11877 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
11878 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11879 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11880 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4
11881 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11882 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11883 // CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
11884 // CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
11885 // CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
11886 // CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
11887 // CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
11888 // CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
11889 // CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
11890 // CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
11891 // CHECK20-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
11892 // CHECK20-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
11893 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
11894 // CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
11895 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11896 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11897 // CHECK20-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11898 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
11899 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11900 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11901 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
11902 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11903 // CHECK20: cond.true:
11904 // CHECK20-NEXT: br label [[COND_END:%.*]]
11905 // CHECK20: cond.false:
11906 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11907 // CHECK20-NEXT: br label [[COND_END]]
11908 // CHECK20: cond.end:
11909 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
11910 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11911 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11912 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
11913 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
11914 // CHECK20: omp.inner.for.cond:
11915 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
11916 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
11917 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
11918 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11919 // CHECK20: omp.inner.for.body:
11920 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
11921 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
11922 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
11923 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
11924 // CHECK20-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10
11925 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
11926 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
11927 // CHECK20-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
11928 // CHECK20-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10
11929 // CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
11930 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
11931 // CHECK20-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
11932 // CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
11933 // CHECK20-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10
11934 // CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
11935 // CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
11936 // CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10
11937 // CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
11938 // CHECK20-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10
11939 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
11940 // CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
11941 // CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
11942 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
11943 // CHECK20: omp.body.continue:
11944 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
11945 // CHECK20: omp.inner.for.inc:
11946 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
11947 // CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
11948 // CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
11949 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
11950 // CHECK20: omp.inner.for.end:
11951 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
11952 // CHECK20: omp.loop.exit:
11953 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
11954 // CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11955 // CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
11956 // CHECK20-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11957 // CHECK20: .omp.final.then:
11958 // CHECK20-NEXT: store i32 32000001, i32* [[I]], align 4
11959 // CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
11960 // CHECK20: .omp.final.done:
11961 // CHECK20-NEXT: ret void
11962 //
11963 //
11964 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
11965 // CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
11966 // CHECK20-NEXT: entry:
11967 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
11968 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
11969 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
11970 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
11971 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
11972 // CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
11973 // CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
11974 // CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
11975 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
11976 // CHECK20-NEXT: ret void
11977 //
11978 //
11979 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
11980 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
11981 // CHECK20-NEXT: entry:
11982 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11983 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11984 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
11985 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
11986 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
11987 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
11988 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
11989 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4
11990 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
11991 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
11992 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11993 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11994 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4
11995 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11996 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11997 // CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
11998 // CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
11999 // CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
12000 // CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
12001 // CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
12002 // CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
12003 // CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
12004 // CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
12005 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
12006 // CHECK20-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
12007 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12008 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12009 // CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12010 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
12011 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12012 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12013 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
12014 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12015 // CHECK20: cond.true:
12016 // CHECK20-NEXT: br label [[COND_END:%.*]]
12017 // CHECK20: cond.false:
12018 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12019 // CHECK20-NEXT: br label [[COND_END]]
12020 // CHECK20: cond.end:
12021 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
12022 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12023 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12024 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
12025 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
12026 // CHECK20: omp.inner.for.cond:
12027 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12028 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12029 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
12030 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12031 // CHECK20: omp.inner.for.body:
12032 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12033 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
12034 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
12035 // CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4
12036 // CHECK20-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4
12037 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
12038 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
12039 // CHECK20-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
12040 // CHECK20-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
12041 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
12042 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
12043 // CHECK20-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
12044 // CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
12045 // CHECK20-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
12046 // CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
12047 // CHECK20-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
12048 // CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
12049 // CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
12050 // CHECK20-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4
12051 // CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
12052 // CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
12053 // CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
12054 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
12055 // CHECK20: omp.body.continue:
12056 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
12057 // CHECK20: omp.inner.for.inc:
12058 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12059 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
12060 // CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
12061 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
12062 // CHECK20: omp.inner.for.end:
12063 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
12064 // CHECK20: omp.loop.exit:
12065 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
12066 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12067 // CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
12068 // CHECK20-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12069 // CHECK20: .omp.final.then:
12070 // CHECK20-NEXT: store i32 32, i32* [[I]], align 4
12071 // CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
12072 // CHECK20: .omp.final.done:
12073 // CHECK20-NEXT: ret void
12074 //
12075 //
12076 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
12077 // CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
12078 // CHECK20-NEXT: entry:
12079 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
12080 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
12081 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
12082 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
12083 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
12084 // CHECK20-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
12085 // CHECK20-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
12086 // CHECK20-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
12087 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
12088 // CHECK20-NEXT: ret void
12089 //
12090 //
12091 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
12092 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
12093 // CHECK20-NEXT: entry:
12094 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12095 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12096 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
12097 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
12098 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
12099 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
12100 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
12101 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4
12102 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
12103 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
12104 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12105 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12106 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4
12107 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12108 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12109 // CHECK20-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
12110 // CHECK20-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
12111 // CHECK20-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
12112 // CHECK20-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
12113 // CHECK20-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
12114 // CHECK20-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
12115 // CHECK20-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
12116 // CHECK20-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
12117 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
12118 // CHECK20-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
12119 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12120 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12121 // CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12122 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
12123 // CHECK20-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
12124 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
12125 // CHECK20: omp.dispatch.cond:
12126 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12127 // CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
12128 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12129 // CHECK20: cond.true:
12130 // CHECK20-NEXT: br label [[COND_END:%.*]]
12131 // CHECK20: cond.false:
12132 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12133 // CHECK20-NEXT: br label [[COND_END]]
12134 // CHECK20: cond.end:
12135 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
12136 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12137 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12138 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
12139 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12140 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12141 // CHECK20-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
12142 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
12143 // CHECK20: omp.dispatch.body:
12144 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
12145 // CHECK20: omp.inner.for.cond:
12146 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12147 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
12148 // CHECK20-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
12149 // CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12150 // CHECK20: omp.inner.for.body:
12151 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12152 // CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
12153 // CHECK20-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
12154 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
12155 // CHECK20-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !19
12156 // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
12157 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
12158 // CHECK20-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19
12159 // CHECK20-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !19
12160 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
12161 // CHECK20-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
12162 // CHECK20-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !19
12163 // CHECK20-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
12164 // CHECK20-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !19
12165 // CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
12166 // CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
12167 // CHECK20-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !19
12168 // CHECK20-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
12169 // CHECK20-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !19
12170 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
12171 // CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
12172 // CHECK20-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
12173 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
12174 // CHECK20: omp.body.continue:
12175 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
12176 // CHECK20: omp.inner.for.inc:
12177 // CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12178 // CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
12179 // CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12180 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
12181 // CHECK20: omp.inner.for.end:
12182 // CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
12183 // CHECK20: omp.dispatch.inc:
12184 // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12185 // CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
12186 // CHECK20-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
12187 // CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
12188 // CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12189 // CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
12190 // CHECK20-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
12191 // CHECK20-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
12192 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
12193 // CHECK20: omp.dispatch.end:
12194 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
12195 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12196 // CHECK20-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
12197 // CHECK20-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12198 // CHECK20: .omp.final.then:
12199 // CHECK20-NEXT: store i32 -2147483522, i32* [[I]], align 4
12200 // CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
12201 // CHECK20: .omp.final.done:
12202 // CHECK20-NEXT: ret void
12203 //
12204 //
12205 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
12206 // CHECK20-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
12207 // CHECK20-NEXT: entry:
12208 // CHECK20-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
12209 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
12210 // CHECK20-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
12211 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
12212 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
12213 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
12214 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
12215 // CHECK20-NEXT: ret void
12216 //
12217 //
12218 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
12219 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
12220 // CHECK20-NEXT: entry:
12221 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12222 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12223 // CHECK20-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
12224 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
12225 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
12226 // CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1
12227 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
12228 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
12229 // CHECK20-NEXT: [[I4:%.*]] = alloca i8, align 1
12230 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
12231 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
12232 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12233 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12234 // CHECK20-NEXT: [[I6:%.*]] = alloca i8, align 1
12235 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12236 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12237 // CHECK20-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
12238 // CHECK20-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
12239 // CHECK20-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
12240 // CHECK20-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
12241 // CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
12242 // CHECK20-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
12243 // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12244 // CHECK20-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
12245 // CHECK20-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
12246 // CHECK20-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
12247 // CHECK20-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
12248 // CHECK20-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
12249 // CHECK20-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
12250 // CHECK20-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
12251 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12252 // CHECK20-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
12253 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12254 // CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
12255 // CHECK20-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
12256 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
12257 // CHECK20: omp.precond.then:
12258 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
12259 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
12260 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
12261 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12262 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12263 // CHECK20-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12264 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
12265 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12266 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12267 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
12268 // CHECK20-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
12269 // CHECK20-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12270 // CHECK20: cond.true:
12271 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
12272 // CHECK20-NEXT: br label [[COND_END:%.*]]
12273 // CHECK20: cond.false:
12274 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12275 // CHECK20-NEXT: br label [[COND_END]]
12276 // CHECK20: cond.end:
12277 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
12278 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12279 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12280 // CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
12281 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
12282 // CHECK20: omp.inner.for.cond:
12283 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12284 // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
12285 // CHECK20-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
12286 // CHECK20-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12287 // CHECK20: omp.inner.for.body:
12288 // CHECK20-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
12289 // CHECK20-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
12290 // CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12291 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
12292 // CHECK20-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
12293 // CHECK20-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
12294 // CHECK20-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !22
12295 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
12296 // CHECK20: omp.body.continue:
12297 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
12298 // CHECK20: omp.inner.for.inc:
12299 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12300 // CHECK20-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
12301 // CHECK20-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12302 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
12303 // CHECK20: omp.inner.for.end:
12304 // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
12305 // CHECK20: omp.loop.exit:
12306 // CHECK20-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12307 // CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4
12308 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
12309 // CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12310 // CHECK20-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
12311 // CHECK20-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12312 // CHECK20: .omp.final.then:
12313 // CHECK20-NEXT: [[TMP23:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12314 // CHECK20-NEXT: [[CONV13:%.*]] = sext i8 [[TMP23]] to i32
12315 // CHECK20-NEXT: [[TMP24:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12316 // CHECK20-NEXT: [[CONV14:%.*]] = sext i8 [[TMP24]] to i32
12317 // CHECK20-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
12318 // CHECK20-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
12319 // CHECK20-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
12320 // CHECK20-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
12321 // CHECK20-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
12322 // CHECK20-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
12323 // CHECK20-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
12324 // CHECK20-NEXT: store i8 [[CONV21]], i8* [[TMP0]], align 1
12325 // CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
12326 // CHECK20: .omp.final.done:
12327 // CHECK20-NEXT: br label [[OMP_PRECOND_END]]
12328 // CHECK20: omp.precond.end:
12329 // CHECK20-NEXT: ret void
12330 //
12331 //
12332 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
12333 // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
12334 // CHECK20-NEXT: entry:
12335 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
12336 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
12337 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12338 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
12339 // CHECK20-NEXT: ret void
12340 //
12341 //
12342 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
12343 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
12344 // CHECK20-NEXT: entry:
12345 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12346 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12347 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
12348 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
12349 // CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4
12350 // CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
12351 // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
12352 // CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12353 // CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12354 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4
12355 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12356 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12357 // CHECK20-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
12358 // CHECK20-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
12359 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
12360 // CHECK20-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
12361 // CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12362 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12363 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
12364 // CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
12365 // CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12366 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
12367 // CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
12368 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
12369 // CHECK20: omp.dispatch.cond:
12370 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12371 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
12372 // CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12373 // CHECK20: cond.true:
12374 // CHECK20-NEXT: br label [[COND_END:%.*]]
12375 // CHECK20: cond.false:
12376 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12377 // CHECK20-NEXT: br label [[COND_END]]
12378 // CHECK20: cond.end:
12379 // CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
12380 // CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12381 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12382 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
12383 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12384 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12385 // CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
12386 // CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
12387 // CHECK20: omp.dispatch.body:
12388 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
12389 // CHECK20: omp.inner.for.cond:
12390 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
12391 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
12392 // CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
12393 // CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12394 // CHECK20: omp.inner.for.body:
12395 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
12396 // CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
12397 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12398 // CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
12399 // CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
12400 // CHECK20: omp.body.continue:
12401 // CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
12402 // CHECK20: omp.inner.for.inc:
12403 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
12404 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
12405 // CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
12406 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
12407 // CHECK20: omp.inner.for.end:
12408 // CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
12409 // CHECK20: omp.dispatch.inc:
12410 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12411 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
12412 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
12413 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
12414 // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12415 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
12416 // CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
12417 // CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
12418 // CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
12419 // CHECK20: omp.dispatch.end:
12420 // CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
12421 // CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12422 // CHECK20-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
12423 // CHECK20-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12424 // CHECK20: .omp.final.then:
12425 // CHECK20-NEXT: store i32 100, i32* [[I]], align 4
12426 // CHECK20-NEXT: br label [[DOTOMP_FINAL_DONE]]
12427 // CHECK20: .omp.final.done:
12428 // CHECK20-NEXT: ret void
12429 //
12430 //
12431 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
12432 // CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
12433 // CHECK21-NEXT: entry:
12434 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
12435 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
12436 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
12437 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
12438 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
12439 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
12440 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
12441 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
12442 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
12443 // CHECK21-NEXT: ret void
12444 //
12445 //
12446 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined.
12447 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
12448 // CHECK21-NEXT: entry:
12449 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12450 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12451 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
12452 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
12453 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
12454 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
12455 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
12456 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
12457 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
12458 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
12459 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12460 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12461 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
12462 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12463 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12464 // CHECK21-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
12465 // CHECK21-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
12466 // CHECK21-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
12467 // CHECK21-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
12468 // CHECK21-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
12469 // CHECK21-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
12470 // CHECK21-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
12471 // CHECK21-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
12472 // CHECK21-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
12473 // CHECK21-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
12474 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
12475 // CHECK21-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
12476 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12477 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12478 // CHECK21-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12479 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
12480 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12481 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12482 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
12483 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12484 // CHECK21: cond.true:
12485 // CHECK21-NEXT: br label [[COND_END:%.*]]
12486 // CHECK21: cond.false:
12487 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12488 // CHECK21-NEXT: br label [[COND_END]]
12489 // CHECK21: cond.end:
12490 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
12491 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12492 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12493 // CHECK21-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
12494 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
12495 // CHECK21: omp.inner.for.cond:
12496 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
12497 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
12498 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
12499 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12500 // CHECK21: omp.inner.for.body:
12501 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
12502 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
12503 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
12504 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
12505 // CHECK21-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9
12506 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
12507 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
12508 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
12509 // CHECK21-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
12510 // CHECK21-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9
12511 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
12512 // CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
12513 // CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
12514 // CHECK21-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9
12515 // CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
12516 // CHECK21-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9
12517 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
12518 // CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
12519 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
12520 // CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
12521 // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
12522 // CHECK21-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9
12523 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
12524 // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
12525 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
12526 // CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
12527 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
12528 // CHECK21: omp.body.continue:
12529 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
12530 // CHECK21: omp.inner.for.inc:
12531 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
12532 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
12533 // CHECK21-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
12534 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
12535 // CHECK21: omp.inner.for.end:
12536 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
12537 // CHECK21: omp.loop.exit:
12538 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
12539 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12540 // CHECK21-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
12541 // CHECK21-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12542 // CHECK21: .omp.final.then:
12543 // CHECK21-NEXT: store i32 32000001, i32* [[I]], align 4
12544 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
12545 // CHECK21: .omp.final.done:
12546 // CHECK21-NEXT: ret void
12547 //
12548 //
12549 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
12550 // CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
12551 // CHECK21-NEXT: entry:
12552 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
12553 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
12554 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
12555 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
12556 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
12557 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
12558 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
12559 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
12560 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
12561 // CHECK21-NEXT: ret void
12562 //
12563 //
12564 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1
12565 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
12566 // CHECK21-NEXT: entry:
12567 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12568 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12569 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
12570 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
12571 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
12572 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
12573 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
12574 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
12575 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
12576 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
12577 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12578 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12579 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
12580 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12581 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12582 // CHECK21-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
12583 // CHECK21-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
12584 // CHECK21-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
12585 // CHECK21-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
12586 // CHECK21-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
12587 // CHECK21-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
12588 // CHECK21-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
12589 // CHECK21-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
12590 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
12591 // CHECK21-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
12592 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12593 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12594 // CHECK21-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12595 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
12596 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12597 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12598 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
12599 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12600 // CHECK21: cond.true:
12601 // CHECK21-NEXT: br label [[COND_END:%.*]]
12602 // CHECK21: cond.false:
12603 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12604 // CHECK21-NEXT: br label [[COND_END]]
12605 // CHECK21: cond.end:
12606 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
12607 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12608 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12609 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
12610 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
12611 // CHECK21: omp.inner.for.cond:
12612 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12613 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12614 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
12615 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12616 // CHECK21: omp.inner.for.body:
12617 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12618 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
12619 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
12620 // CHECK21-NEXT: store i32 [[SUB]], i32* [[I]], align 4
12621 // CHECK21-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !nontemporal !16
12622 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
12623 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
12624 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
12625 // CHECK21-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
12626 // CHECK21-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
12627 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
12628 // CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
12629 // CHECK21-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
12630 // CHECK21-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
12631 // CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
12632 // CHECK21-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
12633 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
12634 // CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
12635 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
12636 // CHECK21-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
12637 // CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
12638 // CHECK21-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !nontemporal !16
12639 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
12640 // CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
12641 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
12642 // CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
12643 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
12644 // CHECK21: omp.body.continue:
12645 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
12646 // CHECK21: omp.inner.for.inc:
12647 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12648 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
12649 // CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
12650 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
12651 // CHECK21: omp.inner.for.end:
12652 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
12653 // CHECK21: omp.loop.exit:
12654 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
12655 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12656 // CHECK21-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
12657 // CHECK21-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12658 // CHECK21: .omp.final.then:
12659 // CHECK21-NEXT: store i32 32, i32* [[I]], align 4
12660 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
12661 // CHECK21: .omp.final.done:
12662 // CHECK21-NEXT: ret void
12663 //
12664 //
12665 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
12666 // CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
12667 // CHECK21-NEXT: entry:
12668 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
12669 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
12670 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
12671 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
12672 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
12673 // CHECK21-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
12674 // CHECK21-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
12675 // CHECK21-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
12676 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
12677 // CHECK21-NEXT: ret void
12678 //
12679 //
12680 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2
12681 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
12682 // CHECK21-NEXT: entry:
12683 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12684 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12685 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
12686 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
12687 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
12688 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
12689 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
12690 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
12691 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
12692 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
12693 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12694 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12695 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
12696 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12697 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12698 // CHECK21-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
12699 // CHECK21-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
12700 // CHECK21-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
12701 // CHECK21-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
12702 // CHECK21-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
12703 // CHECK21-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
12704 // CHECK21-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
12705 // CHECK21-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
12706 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
12707 // CHECK21-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
12708 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12709 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12710 // CHECK21-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12711 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
12712 // CHECK21-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
12713 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
12714 // CHECK21: omp.dispatch.cond:
12715 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12716 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
12717 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12718 // CHECK21: cond.true:
12719 // CHECK21-NEXT: br label [[COND_END:%.*]]
12720 // CHECK21: cond.false:
12721 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12722 // CHECK21-NEXT: br label [[COND_END]]
12723 // CHECK21: cond.end:
12724 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
12725 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12726 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12727 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
12728 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12729 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12730 // CHECK21-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
12731 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
12732 // CHECK21: omp.dispatch.body:
12733 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
12734 // CHECK21: omp.inner.for.cond:
12735 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12736 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
12737 // CHECK21-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
12738 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12739 // CHECK21: omp.inner.for.body:
12740 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12741 // CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
12742 // CHECK21-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
12743 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
12744 // CHECK21-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !19
12745 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
12746 // CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
12747 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
12748 // CHECK21-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19
12749 // CHECK21-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !19
12750 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
12751 // CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
12752 // CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
12753 // CHECK21-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !19
12754 // CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
12755 // CHECK21-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !19
12756 // CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
12757 // CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
12758 // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
12759 // CHECK21-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
12760 // CHECK21-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
12761 // CHECK21-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !19
12762 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
12763 // CHECK21-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
12764 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
12765 // CHECK21-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !19
12766 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
12767 // CHECK21: omp.body.continue:
12768 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
12769 // CHECK21: omp.inner.for.inc:
12770 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12771 // CHECK21-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
12772 // CHECK21-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12773 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
12774 // CHECK21: omp.inner.for.end:
12775 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
12776 // CHECK21: omp.dispatch.inc:
12777 // CHECK21-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12778 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
12779 // CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
12780 // CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
12781 // CHECK21-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12782 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
12783 // CHECK21-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
12784 // CHECK21-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
12785 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]]
12786 // CHECK21: omp.dispatch.end:
12787 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
12788 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12789 // CHECK21-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
12790 // CHECK21-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12791 // CHECK21: .omp.final.then:
12792 // CHECK21-NEXT: store i32 -2147483522, i32* [[I]], align 4
12793 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
12794 // CHECK21: .omp.final.done:
12795 // CHECK21-NEXT: ret void
12796 //
12797 //
12798 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
12799 // CHECK21-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
12800 // CHECK21-NEXT: entry:
12801 // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
12802 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
12803 // CHECK21-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
12804 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
12805 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
12806 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
12807 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
12808 // CHECK21-NEXT: ret void
12809 //
12810 //
12811 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3
12812 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
12813 // CHECK21-NEXT: entry:
12814 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12815 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12816 // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
12817 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
12818 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
12819 // CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1
12820 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
12821 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
12822 // CHECK21-NEXT: [[I4:%.*]] = alloca i8, align 1
12823 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
12824 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
12825 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12826 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12827 // CHECK21-NEXT: [[I6:%.*]] = alloca i8, align 1
12828 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12829 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12830 // CHECK21-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
12831 // CHECK21-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
12832 // CHECK21-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
12833 // CHECK21-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
12834 // CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
12835 // CHECK21-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
12836 // CHECK21-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12837 // CHECK21-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
12838 // CHECK21-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
12839 // CHECK21-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
12840 // CHECK21-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
12841 // CHECK21-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
12842 // CHECK21-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
12843 // CHECK21-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
12844 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12845 // CHECK21-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
12846 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12847 // CHECK21-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
12848 // CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
12849 // CHECK21-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
12850 // CHECK21: omp.precond.then:
12851 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
12852 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
12853 // CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
12854 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12855 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12856 // CHECK21-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12857 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
12858 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12859 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12860 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
12861 // CHECK21-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
12862 // CHECK21-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12863 // CHECK21: cond.true:
12864 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
12865 // CHECK21-NEXT: br label [[COND_END:%.*]]
12866 // CHECK21: cond.false:
12867 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12868 // CHECK21-NEXT: br label [[COND_END]]
12869 // CHECK21: cond.end:
12870 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
12871 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12872 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12873 // CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
12874 // CHECK21-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
12875 // CHECK21-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
12876 // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12877 // CHECK21: omp_if.then:
12878 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
12879 // CHECK21: omp.inner.for.cond:
12880 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12881 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
12882 // CHECK21-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
12883 // CHECK21-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12884 // CHECK21: omp.inner.for.body:
12885 // CHECK21-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
12886 // CHECK21-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
12887 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12888 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
12889 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
12890 // CHECK21-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
12891 // CHECK21-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
12892 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
12893 // CHECK21: omp.body.continue:
12894 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
12895 // CHECK21: omp.inner.for.inc:
12896 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12897 // CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
12898 // CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12899 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
12900 // CHECK21: omp.inner.for.end:
12901 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]]
12902 // CHECK21: omp_if.else:
12903 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
12904 // CHECK21: omp.inner.for.cond13:
12905 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12906 // CHECK21-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12907 // CHECK21-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
12908 // CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
12909 // CHECK21: omp.inner.for.body15:
12910 // CHECK21-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12911 // CHECK21-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
12912 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12913 // CHECK21-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
12914 // CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
12915 // CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
12916 // CHECK21-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
12917 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
12918 // CHECK21: omp.body.continue20:
12919 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
12920 // CHECK21: omp.inner.for.inc21:
12921 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12922 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
12923 // CHECK21-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
12924 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
12925 // CHECK21: omp.inner.for.end23:
12926 // CHECK21-NEXT: br label [[OMP_IF_END]]
12927 // CHECK21: omp_if.end:
12928 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
12929 // CHECK21: omp.loop.exit:
12930 // CHECK21-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12931 // CHECK21-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
12932 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
12933 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12934 // CHECK21-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
12935 // CHECK21-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12936 // CHECK21: .omp.final.then:
12937 // CHECK21-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12938 // CHECK21-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
12939 // CHECK21-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
12940 // CHECK21-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
12941 // CHECK21-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
12942 // CHECK21-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
12943 // CHECK21-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
12944 // CHECK21-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
12945 // CHECK21-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
12946 // CHECK21-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
12947 // CHECK21-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
12948 // CHECK21-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
12949 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
12950 // CHECK21: .omp.final.done:
12951 // CHECK21-NEXT: br label [[OMP_PRECOND_END]]
12952 // CHECK21: omp.precond.end:
12953 // CHECK21-NEXT: ret void
12954 //
12955 //
12956 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
12957 // CHECK21-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
12958 // CHECK21-NEXT: entry:
12959 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
12960 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
12961 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12962 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
12963 // CHECK21-NEXT: ret void
12964 //
12965 //
12966 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4
12967 // CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
12968 // CHECK21-NEXT: entry:
12969 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12970 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12971 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
12972 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
12973 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4
12974 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
12975 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
12976 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12977 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12978 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4
12979 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12980 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12981 // CHECK21-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
12982 // CHECK21-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
12983 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
12984 // CHECK21-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
12985 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12986 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12987 // CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
12988 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
12989 // CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12990 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
12991 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
12992 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
12993 // CHECK21: omp.dispatch.cond:
12994 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12995 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
12996 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12997 // CHECK21: cond.true:
12998 // CHECK21-NEXT: br label [[COND_END:%.*]]
12999 // CHECK21: cond.false:
13000 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13001 // CHECK21-NEXT: br label [[COND_END]]
13002 // CHECK21: cond.end:
13003 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
13004 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13005 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13006 // CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
13007 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13008 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13009 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
13010 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
13011 // CHECK21: omp.dispatch.body:
13012 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
13013 // CHECK21: omp.inner.for.cond:
13014 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
13015 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
13016 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
13017 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13018 // CHECK21: omp.inner.for.body:
13019 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
13020 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
13021 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13022 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
13023 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
13024 // CHECK21: omp.body.continue:
13025 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
13026 // CHECK21: omp.inner.for.inc:
13027 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
13028 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
13029 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
13030 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
13031 // CHECK21: omp.inner.for.end:
13032 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
13033 // CHECK21: omp.dispatch.inc:
13034 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13035 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
13036 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
13037 // CHECK21-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
13038 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13039 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
13040 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
13041 // CHECK21-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
13042 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]]
13043 // CHECK21: omp.dispatch.end:
13044 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
13045 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13046 // CHECK21-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
13047 // CHECK21-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13048 // CHECK21: .omp.final.then:
13049 // CHECK21-NEXT: store i32 100, i32* [[I]], align 4
13050 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]]
13051 // CHECK21: .omp.final.done:
13052 // CHECK21-NEXT: ret void
13053 //
13054 //
13055 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
13056 // CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
13057 // CHECK22-NEXT: entry:
13058 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
13059 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
13060 // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
13061 // CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
13062 // CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
13063 // CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
13064 // CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
13065 // CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
13066 // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
13067 // CHECK22-NEXT: ret void
13068 //
13069 //
13070 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined.
13071 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
13072 // CHECK22-NEXT: entry:
13073 // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13074 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13075 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
13076 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
13077 // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
13078 // CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
13079 // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
13080 // CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4
13081 // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
13082 // CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
13083 // CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13084 // CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13085 // CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4
13086 // CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13087 // CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13088 // CHECK22-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
13089 // CHECK22-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
13090 // CHECK22-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
13091 // CHECK22-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
13092 // CHECK22-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
13093 // CHECK22-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
13094 // CHECK22-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
13095 // CHECK22-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
13096 // CHECK22-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 8
13097 // CHECK22-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i64 16) ]
13098 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
13099 // CHECK22-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
13100 // CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13101 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13102 // CHECK22-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13103 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
13104 // CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13105 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13106 // CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
13107 // CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13108 // CHECK22: cond.true:
13109 // CHECK22-NEXT: br label [[COND_END:%.*]]
13110 // CHECK22: cond.false:
13111 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13112 // CHECK22-NEXT: br label [[COND_END]]
13113 // CHECK22: cond.end:
13114 // CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
13115 // CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13116 // CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13117 // CHECK22-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
13118 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
13119 // CHECK22: omp.inner.for.cond:
13120 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
13121 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
13122 // CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
13123 // CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13124 // CHECK22: omp.inner.for.body:
13125 // CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
13126 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
13127 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
13128 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
13129 // CHECK22-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !9
13130 // CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
13131 // CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
13132 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]]
13133 // CHECK22-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
13134 // CHECK22-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !9
13135 // CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
13136 // CHECK22-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
13137 // CHECK22-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM2]]
13138 // CHECK22-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !9
13139 // CHECK22-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
13140 // CHECK22-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !9
13141 // CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
13142 // CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
13143 // CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM5]]
13144 // CHECK22-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
13145 // CHECK22-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
13146 // CHECK22-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !9
13147 // CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
13148 // CHECK22-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
13149 // CHECK22-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM8]]
13150 // CHECK22-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
13151 // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
13152 // CHECK22: omp.body.continue:
13153 // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
13154 // CHECK22: omp.inner.for.inc:
13155 // CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
13156 // CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
13157 // CHECK22-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
13158 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
13159 // CHECK22: omp.inner.for.end:
13160 // CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
13161 // CHECK22: omp.loop.exit:
13162 // CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
13163 // CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13164 // CHECK22-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
13165 // CHECK22-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13166 // CHECK22: .omp.final.then:
13167 // CHECK22-NEXT: store i32 32000001, i32* [[I]], align 4
13168 // CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
13169 // CHECK22: .omp.final.done:
13170 // CHECK22-NEXT: ret void
13171 //
13172 //
13173 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
13174 // CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
13175 // CHECK22-NEXT: entry:
13176 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
13177 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
13178 // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
13179 // CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
13180 // CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
13181 // CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
13182 // CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
13183 // CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
13184 // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
13185 // CHECK22-NEXT: ret void
13186 //
13187 //
13188 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1
13189 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
13190 // CHECK22-NEXT: entry:
13191 // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13192 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13193 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
13194 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
13195 // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
13196 // CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
13197 // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
13198 // CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4
13199 // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
13200 // CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
13201 // CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13202 // CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13203 // CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4
13204 // CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13205 // CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13206 // CHECK22-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
13207 // CHECK22-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
13208 // CHECK22-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
13209 // CHECK22-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
13210 // CHECK22-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
13211 // CHECK22-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
13212 // CHECK22-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
13213 // CHECK22-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
13214 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
13215 // CHECK22-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
13216 // CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13217 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13218 // CHECK22-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13219 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
13220 // CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13221 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13222 // CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
13223 // CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13224 // CHECK22: cond.true:
13225 // CHECK22-NEXT: br label [[COND_END:%.*]]
13226 // CHECK22: cond.false:
13227 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13228 // CHECK22-NEXT: br label [[COND_END]]
13229 // CHECK22: cond.end:
13230 // CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
13231 // CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13232 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13233 // CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
13234 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
13235 // CHECK22: omp.inner.for.cond:
13236 // CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13237 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13238 // CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
13239 // CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13240 // CHECK22: omp.inner.for.body:
13241 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13242 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
13243 // CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
13244 // CHECK22-NEXT: store i32 [[SUB]], i32* [[I]], align 4
13245 // CHECK22-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !nontemporal !16
13246 // CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
13247 // CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
13248 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]]
13249 // CHECK22-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
13250 // CHECK22-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8
13251 // CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
13252 // CHECK22-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
13253 // CHECK22-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]]
13254 // CHECK22-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4
13255 // CHECK22-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
13256 // CHECK22-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8
13257 // CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
13258 // CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
13259 // CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]]
13260 // CHECK22-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4
13261 // CHECK22-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
13262 // CHECK22-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !nontemporal !16
13263 // CHECK22-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
13264 // CHECK22-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
13265 // CHECK22-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]]
13266 // CHECK22-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
13267 // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
13268 // CHECK22: omp.body.continue:
13269 // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
13270 // CHECK22: omp.inner.for.inc:
13271 // CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13272 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
13273 // CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
13274 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
13275 // CHECK22: omp.inner.for.end:
13276 // CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
13277 // CHECK22: omp.loop.exit:
13278 // CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
13279 // CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13280 // CHECK22-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
13281 // CHECK22-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13282 // CHECK22: .omp.final.then:
13283 // CHECK22-NEXT: store i32 32, i32* [[I]], align 4
13284 // CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
13285 // CHECK22: .omp.final.done:
13286 // CHECK22-NEXT: ret void
13287 //
13288 //
13289 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
13290 // CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
13291 // CHECK22-NEXT: entry:
13292 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
13293 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
13294 // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
13295 // CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
13296 // CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
13297 // CHECK22-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
13298 // CHECK22-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
13299 // CHECK22-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
13300 // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
13301 // CHECK22-NEXT: ret void
13302 //
13303 //
13304 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2
13305 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] {
13306 // CHECK22-NEXT: entry:
13307 // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13308 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13309 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8
13310 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8
13311 // CHECK22-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8
13312 // CHECK22-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8
13313 // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
13314 // CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4
13315 // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
13316 // CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
13317 // CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13318 // CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13319 // CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4
13320 // CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13321 // CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13322 // CHECK22-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8
13323 // CHECK22-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8
13324 // CHECK22-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8
13325 // CHECK22-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8
13326 // CHECK22-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8
13327 // CHECK22-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8
13328 // CHECK22-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8
13329 // CHECK22-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8
13330 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
13331 // CHECK22-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
13332 // CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13333 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13334 // CHECK22-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13335 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
13336 // CHECK22-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
13337 // CHECK22-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
13338 // CHECK22: omp.dispatch.cond:
13339 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13340 // CHECK22-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
13341 // CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13342 // CHECK22: cond.true:
13343 // CHECK22-NEXT: br label [[COND_END:%.*]]
13344 // CHECK22: cond.false:
13345 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13346 // CHECK22-NEXT: br label [[COND_END]]
13347 // CHECK22: cond.end:
13348 // CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
13349 // CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13350 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13351 // CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
13352 // CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13353 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13354 // CHECK22-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
13355 // CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
13356 // CHECK22: omp.dispatch.body:
13357 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
13358 // CHECK22: omp.inner.for.cond:
13359 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
13360 // CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
13361 // CHECK22-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
13362 // CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13363 // CHECK22: omp.inner.for.body:
13364 // CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
13365 // CHECK22-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
13366 // CHECK22-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
13367 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
13368 // CHECK22-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !19
13369 // CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
13370 // CHECK22-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
13371 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]]
13372 // CHECK22-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !19
13373 // CHECK22-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !19
13374 // CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
13375 // CHECK22-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
13376 // CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]]
13377 // CHECK22-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !19
13378 // CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
13379 // CHECK22-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !19
13380 // CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
13381 // CHECK22-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
13382 // CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]]
13383 // CHECK22-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
13384 // CHECK22-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
13385 // CHECK22-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !19
13386 // CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19
13387 // CHECK22-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
13388 // CHECK22-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]]
13389 // CHECK22-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !19
13390 // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
13391 // CHECK22: omp.body.continue:
13392 // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
13393 // CHECK22: omp.inner.for.inc:
13394 // CHECK22-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
13395 // CHECK22-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
13396 // CHECK22-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
13397 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
13398 // CHECK22: omp.inner.for.end:
13399 // CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
13400 // CHECK22: omp.dispatch.inc:
13401 // CHECK22-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13402 // CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
13403 // CHECK22-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
13404 // CHECK22-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
13405 // CHECK22-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13406 // CHECK22-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
13407 // CHECK22-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
13408 // CHECK22-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4
13409 // CHECK22-NEXT: br label [[OMP_DISPATCH_COND]]
13410 // CHECK22: omp.dispatch.end:
13411 // CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
13412 // CHECK22-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13413 // CHECK22-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
13414 // CHECK22-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13415 // CHECK22: .omp.final.then:
13416 // CHECK22-NEXT: store i32 -2147483522, i32* [[I]], align 4
13417 // CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
13418 // CHECK22: .omp.final.done:
13419 // CHECK22-NEXT: ret void
13420 //
13421 //
13422 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
13423 // CHECK22-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
13424 // CHECK22-NEXT: entry:
13425 // CHECK22-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8
13426 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
13427 // CHECK22-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8
13428 // CHECK22-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
13429 // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[I_ADDR]] to i8*
13430 // CHECK22-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i8*
13431 // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
13432 // CHECK22-NEXT: ret void
13433 //
13434 //
13435 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3
13436 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
13437 // CHECK22-NEXT: entry:
13438 // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13439 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13440 // CHECK22-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 8
13441 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 8
13442 // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
13443 // CHECK22-NEXT: [[TMP:%.*]] = alloca i8, align 1
13444 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
13445 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
13446 // CHECK22-NEXT: [[I4:%.*]] = alloca i8, align 1
13447 // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
13448 // CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
13449 // CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13450 // CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13451 // CHECK22-NEXT: [[I6:%.*]] = alloca i8, align 1
13452 // CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13453 // CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13454 // CHECK22-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 8
13455 // CHECK22-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 8
13456 // CHECK22-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 8
13457 // CHECK22-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 8
13458 // CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
13459 // CHECK22-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
13460 // CHECK22-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
13461 // CHECK22-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
13462 // CHECK22-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
13463 // CHECK22-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
13464 // CHECK22-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
13465 // CHECK22-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
13466 // CHECK22-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
13467 // CHECK22-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
13468 // CHECK22-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
13469 // CHECK22-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
13470 // CHECK22-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
13471 // CHECK22-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
13472 // CHECK22-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
13473 // CHECK22-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
13474 // CHECK22: omp.precond.then:
13475 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
13476 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
13477 // CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
13478 // CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13479 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13480 // CHECK22-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13481 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
13482 // CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13483 // CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13484 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
13485 // CHECK22-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
13486 // CHECK22-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13487 // CHECK22: cond.true:
13488 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
13489 // CHECK22-NEXT: br label [[COND_END:%.*]]
13490 // CHECK22: cond.false:
13491 // CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13492 // CHECK22-NEXT: br label [[COND_END]]
13493 // CHECK22: cond.end:
13494 // CHECK22-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
13495 // CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13496 // CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13497 // CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
13498 // CHECK22-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
13499 // CHECK22-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
13500 // CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13501 // CHECK22: omp_if.then:
13502 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
13503 // CHECK22: omp.inner.for.cond:
13504 // CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
13505 // CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
13506 // CHECK22-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
13507 // CHECK22-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13508 // CHECK22: omp.inner.for.body:
13509 // CHECK22-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
13510 // CHECK22-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
13511 // CHECK22-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
13512 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
13513 // CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
13514 // CHECK22-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
13515 // CHECK22-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
13516 // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
13517 // CHECK22: omp.body.continue:
13518 // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
13519 // CHECK22: omp.inner.for.inc:
13520 // CHECK22-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
13521 // CHECK22-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
13522 // CHECK22-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
13523 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
13524 // CHECK22: omp.inner.for.end:
13525 // CHECK22-NEXT: br label [[OMP_IF_END:%.*]]
13526 // CHECK22: omp_if.else:
13527 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
13528 // CHECK22: omp.inner.for.cond13:
13529 // CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13530 // CHECK22-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13531 // CHECK22-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
13532 // CHECK22-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
13533 // CHECK22: omp.inner.for.body15:
13534 // CHECK22-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
13535 // CHECK22-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
13536 // CHECK22-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13537 // CHECK22-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
13538 // CHECK22-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
13539 // CHECK22-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
13540 // CHECK22-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
13541 // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
13542 // CHECK22: omp.body.continue20:
13543 // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
13544 // CHECK22: omp.inner.for.inc21:
13545 // CHECK22-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13546 // CHECK22-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
13547 // CHECK22-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
13548 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
13549 // CHECK22: omp.inner.for.end23:
13550 // CHECK22-NEXT: br label [[OMP_IF_END]]
13551 // CHECK22: omp_if.end:
13552 // CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
13553 // CHECK22: omp.loop.exit:
13554 // CHECK22-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13555 // CHECK22-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
13556 // CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
13557 // CHECK22-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13558 // CHECK22-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
13559 // CHECK22-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13560 // CHECK22: .omp.final.then:
13561 // CHECK22-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
13562 // CHECK22-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
13563 // CHECK22-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
13564 // CHECK22-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
13565 // CHECK22-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
13566 // CHECK22-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
13567 // CHECK22-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
13568 // CHECK22-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
13569 // CHECK22-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
13570 // CHECK22-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
13571 // CHECK22-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
13572 // CHECK22-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
13573 // CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
13574 // CHECK22: .omp.final.done:
13575 // CHECK22-NEXT: br label [[OMP_PRECOND_END]]
13576 // CHECK22: omp.precond.end:
13577 // CHECK22-NEXT: ret void
13578 //
13579 //
13580 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
13581 // CHECK22-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
13582 // CHECK22-NEXT: entry:
13583 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
13584 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
13585 // CHECK22-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13586 // CHECK22-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
13587 // CHECK22-NEXT: ret void
13588 //
13589 //
13590 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4
13591 // CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
13592 // CHECK22-NEXT: entry:
13593 // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13594 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13595 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8
13596 // CHECK22-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
13597 // CHECK22-NEXT: [[TMP:%.*]] = alloca i32, align 4
13598 // CHECK22-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
13599 // CHECK22-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
13600 // CHECK22-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13601 // CHECK22-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13602 // CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4
13603 // CHECK22-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13604 // CHECK22-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13605 // CHECK22-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8
13606 // CHECK22-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8
13607 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
13608 // CHECK22-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
13609 // CHECK22-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13610 // CHECK22-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13611 // CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
13612 // CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
13613 // CHECK22-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13614 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
13615 // CHECK22-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
13616 // CHECK22-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
13617 // CHECK22: omp.dispatch.cond:
13618 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13619 // CHECK22-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
13620 // CHECK22-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13621 // CHECK22: cond.true:
13622 // CHECK22-NEXT: br label [[COND_END:%.*]]
13623 // CHECK22: cond.false:
13624 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13625 // CHECK22-NEXT: br label [[COND_END]]
13626 // CHECK22: cond.end:
13627 // CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
13628 // CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13629 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13630 // CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
13631 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13632 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13633 // CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
13634 // CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
13635 // CHECK22: omp.dispatch.body:
13636 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
13637 // CHECK22: omp.inner.for.cond:
13638 // CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
13639 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
13640 // CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
13641 // CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13642 // CHECK22: omp.inner.for.body:
13643 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
13644 // CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
13645 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13646 // CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
13647 // CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
13648 // CHECK22: omp.body.continue:
13649 // CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
13650 // CHECK22: omp.inner.for.inc:
13651 // CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
13652 // CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
13653 // CHECK22-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
13654 // CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
13655 // CHECK22: omp.inner.for.end:
13656 // CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
13657 // CHECK22: omp.dispatch.inc:
13658 // CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13659 // CHECK22-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
13660 // CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
13661 // CHECK22-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
13662 // CHECK22-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13663 // CHECK22-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
13664 // CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
13665 // CHECK22-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
13666 // CHECK22-NEXT: br label [[OMP_DISPATCH_COND]]
13667 // CHECK22: omp.dispatch.end:
13668 // CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
13669 // CHECK22-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13670 // CHECK22-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
13671 // CHECK22-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13672 // CHECK22: .omp.final.then:
13673 // CHECK22-NEXT: store i32 100, i32* [[I]], align 4
13674 // CHECK22-NEXT: br label [[DOTOMP_FINAL_DONE]]
13675 // CHECK22: .omp.final.done:
13676 // CHECK22-NEXT: ret void
13677 //
13678 //
13679 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
13680 // CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
13681 // CHECK23-NEXT: entry:
13682 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
13683 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
13684 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
13685 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
13686 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
13687 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
13688 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
13689 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
13690 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
13691 // CHECK23-NEXT: ret void
13692 //
13693 //
13694 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined.
13695 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
13696 // CHECK23-NEXT: entry:
13697 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13698 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13699 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
13700 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
13701 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
13702 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
13703 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
13704 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
13705 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
13706 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
13707 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13708 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13709 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4
13710 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13711 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13712 // CHECK23-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
13713 // CHECK23-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
13714 // CHECK23-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
13715 // CHECK23-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
13716 // CHECK23-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
13717 // CHECK23-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
13718 // CHECK23-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
13719 // CHECK23-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
13720 // CHECK23-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
13721 // CHECK23-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
13722 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
13723 // CHECK23-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
13724 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13725 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13726 // CHECK23-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13727 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
13728 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13729 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13730 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
13731 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13732 // CHECK23: cond.true:
13733 // CHECK23-NEXT: br label [[COND_END:%.*]]
13734 // CHECK23: cond.false:
13735 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13736 // CHECK23-NEXT: br label [[COND_END]]
13737 // CHECK23: cond.end:
13738 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
13739 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13740 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13741 // CHECK23-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
13742 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
13743 // CHECK23: omp.inner.for.cond:
13744 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
13745 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
13746 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
13747 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13748 // CHECK23: omp.inner.for.body:
13749 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
13750 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
13751 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
13752 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
13753 // CHECK23-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10
13754 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
13755 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
13756 // CHECK23-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
13757 // CHECK23-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10
13758 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
13759 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
13760 // CHECK23-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
13761 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
13762 // CHECK23-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10
13763 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
13764 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
13765 // CHECK23-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10
13766 // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
13767 // CHECK23-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10
13768 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
13769 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
13770 // CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
13771 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
13772 // CHECK23: omp.body.continue:
13773 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
13774 // CHECK23: omp.inner.for.inc:
13775 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
13776 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
13777 // CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
13778 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
13779 // CHECK23: omp.inner.for.end:
13780 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
13781 // CHECK23: omp.loop.exit:
13782 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
13783 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13784 // CHECK23-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
13785 // CHECK23-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13786 // CHECK23: .omp.final.then:
13787 // CHECK23-NEXT: store i32 32000001, i32* [[I]], align 4
13788 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
13789 // CHECK23: .omp.final.done:
13790 // CHECK23-NEXT: ret void
13791 //
13792 //
13793 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
13794 // CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
13795 // CHECK23-NEXT: entry:
13796 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
13797 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
13798 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
13799 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
13800 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
13801 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
13802 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
13803 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
13804 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
13805 // CHECK23-NEXT: ret void
13806 //
13807 //
13808 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1
13809 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
13810 // CHECK23-NEXT: entry:
13811 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13812 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13813 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
13814 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
13815 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
13816 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
13817 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
13818 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
13819 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
13820 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
13821 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13822 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13823 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4
13824 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13825 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13826 // CHECK23-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
13827 // CHECK23-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
13828 // CHECK23-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
13829 // CHECK23-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
13830 // CHECK23-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
13831 // CHECK23-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
13832 // CHECK23-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
13833 // CHECK23-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
13834 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
13835 // CHECK23-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
13836 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13837 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13838 // CHECK23-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13839 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
13840 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13841 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13842 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
13843 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13844 // CHECK23: cond.true:
13845 // CHECK23-NEXT: br label [[COND_END:%.*]]
13846 // CHECK23: cond.false:
13847 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13848 // CHECK23-NEXT: br label [[COND_END]]
13849 // CHECK23: cond.end:
13850 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
13851 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13852 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13853 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
13854 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
13855 // CHECK23: omp.inner.for.cond:
13856 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13857 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13858 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
13859 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13860 // CHECK23: omp.inner.for.body:
13861 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13862 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
13863 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
13864 // CHECK23-NEXT: store i32 [[SUB]], i32* [[I]], align 4
13865 // CHECK23-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4, !nontemporal !17
13866 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
13867 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
13868 // CHECK23-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
13869 // CHECK23-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
13870 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
13871 // CHECK23-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
13872 // CHECK23-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
13873 // CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
13874 // CHECK23-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
13875 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
13876 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
13877 // CHECK23-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
13878 // CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
13879 // CHECK23-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4, !nontemporal !17
13880 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
13881 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
13882 // CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
13883 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
13884 // CHECK23: omp.body.continue:
13885 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
13886 // CHECK23: omp.inner.for.inc:
13887 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13888 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
13889 // CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
13890 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
13891 // CHECK23: omp.inner.for.end:
13892 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
13893 // CHECK23: omp.loop.exit:
13894 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
13895 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13896 // CHECK23-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
13897 // CHECK23-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13898 // CHECK23: .omp.final.then:
13899 // CHECK23-NEXT: store i32 32, i32* [[I]], align 4
13900 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
13901 // CHECK23: .omp.final.done:
13902 // CHECK23-NEXT: ret void
13903 //
13904 //
13905 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
13906 // CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
13907 // CHECK23-NEXT: entry:
13908 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
13909 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
13910 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
13911 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
13912 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
13913 // CHECK23-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
13914 // CHECK23-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
13915 // CHECK23-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
13916 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
13917 // CHECK23-NEXT: ret void
13918 //
13919 //
13920 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2
13921 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
13922 // CHECK23-NEXT: entry:
13923 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13924 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13925 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
13926 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
13927 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
13928 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
13929 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
13930 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
13931 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
13932 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
13933 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13934 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13935 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4
13936 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13937 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13938 // CHECK23-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
13939 // CHECK23-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
13940 // CHECK23-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
13941 // CHECK23-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
13942 // CHECK23-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
13943 // CHECK23-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
13944 // CHECK23-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
13945 // CHECK23-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
13946 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
13947 // CHECK23-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
13948 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13949 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13950 // CHECK23-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13951 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
13952 // CHECK23-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
13953 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
13954 // CHECK23: omp.dispatch.cond:
13955 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13956 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
13957 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13958 // CHECK23: cond.true:
13959 // CHECK23-NEXT: br label [[COND_END:%.*]]
13960 // CHECK23: cond.false:
13961 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13962 // CHECK23-NEXT: br label [[COND_END]]
13963 // CHECK23: cond.end:
13964 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
13965 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13966 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13967 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
13968 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13969 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13970 // CHECK23-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
13971 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
13972 // CHECK23: omp.dispatch.body:
13973 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
13974 // CHECK23: omp.inner.for.cond:
13975 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
13976 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
13977 // CHECK23-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
13978 // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13979 // CHECK23: omp.inner.for.body:
13980 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
13981 // CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
13982 // CHECK23-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
13983 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20
13984 // CHECK23-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !20
13985 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
13986 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
13987 // CHECK23-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !20
13988 // CHECK23-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !20
13989 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
13990 // CHECK23-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
13991 // CHECK23-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !20
13992 // CHECK23-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
13993 // CHECK23-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !20
13994 // CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
13995 // CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
13996 // CHECK23-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !20
13997 // CHECK23-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
13998 // CHECK23-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !20
13999 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
14000 // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
14001 // CHECK23-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !20
14002 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
14003 // CHECK23: omp.body.continue:
14004 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
14005 // CHECK23: omp.inner.for.inc:
14006 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
14007 // CHECK23-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
14008 // CHECK23-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
14009 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
14010 // CHECK23: omp.inner.for.end:
14011 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
14012 // CHECK23: omp.dispatch.inc:
14013 // CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14014 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14015 // CHECK23-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
14016 // CHECK23-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
14017 // CHECK23-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14018 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14019 // CHECK23-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
14020 // CHECK23-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
14021 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]]
14022 // CHECK23: omp.dispatch.end:
14023 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
14024 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14025 // CHECK23-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
14026 // CHECK23-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14027 // CHECK23: .omp.final.then:
14028 // CHECK23-NEXT: store i32 -2147483522, i32* [[I]], align 4
14029 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
14030 // CHECK23: .omp.final.done:
14031 // CHECK23-NEXT: ret void
14032 //
14033 //
14034 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
14035 // CHECK23-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
14036 // CHECK23-NEXT: entry:
14037 // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
14038 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14039 // CHECK23-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
14040 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14041 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
14042 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
14043 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
14044 // CHECK23-NEXT: ret void
14045 //
14046 //
14047 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3
14048 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
14049 // CHECK23-NEXT: entry:
14050 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14051 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14052 // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
14053 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
14054 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
14055 // CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1
14056 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
14057 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
14058 // CHECK23-NEXT: [[I4:%.*]] = alloca i8, align 1
14059 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
14060 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
14061 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14062 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14063 // CHECK23-NEXT: [[I6:%.*]] = alloca i8, align 1
14064 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14065 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14066 // CHECK23-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
14067 // CHECK23-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
14068 // CHECK23-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
14069 // CHECK23-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
14070 // CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
14071 // CHECK23-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
14072 // CHECK23-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14073 // CHECK23-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
14074 // CHECK23-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
14075 // CHECK23-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
14076 // CHECK23-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
14077 // CHECK23-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
14078 // CHECK23-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
14079 // CHECK23-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
14080 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14081 // CHECK23-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
14082 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14083 // CHECK23-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
14084 // CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
14085 // CHECK23-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
14086 // CHECK23: omp.precond.then:
14087 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
14088 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
14089 // CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
14090 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14091 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14092 // CHECK23-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14093 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
14094 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14095 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14096 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
14097 // CHECK23-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
14098 // CHECK23-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14099 // CHECK23: cond.true:
14100 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
14101 // CHECK23-NEXT: br label [[COND_END:%.*]]
14102 // CHECK23: cond.false:
14103 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14104 // CHECK23-NEXT: br label [[COND_END]]
14105 // CHECK23: cond.end:
14106 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
14107 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14108 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14109 // CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
14110 // CHECK23-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
14111 // CHECK23-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
14112 // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
14113 // CHECK23: omp_if.then:
14114 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
14115 // CHECK23: omp.inner.for.cond:
14116 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
14117 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
14118 // CHECK23-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
14119 // CHECK23-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14120 // CHECK23: omp.inner.for.body:
14121 // CHECK23-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !23
14122 // CHECK23-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
14123 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
14124 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
14125 // CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
14126 // CHECK23-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
14127 // CHECK23-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !17, !llvm.access.group !23
14128 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
14129 // CHECK23: omp.body.continue:
14130 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
14131 // CHECK23: omp.inner.for.inc:
14132 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
14133 // CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
14134 // CHECK23-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
14135 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
14136 // CHECK23: omp.inner.for.end:
14137 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]]
14138 // CHECK23: omp_if.else:
14139 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
14140 // CHECK23: omp.inner.for.cond13:
14141 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14142 // CHECK23-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14143 // CHECK23-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
14144 // CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
14145 // CHECK23: omp.inner.for.body15:
14146 // CHECK23-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14147 // CHECK23-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
14148 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14149 // CHECK23-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
14150 // CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
14151 // CHECK23-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
14152 // CHECK23-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
14153 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
14154 // CHECK23: omp.body.continue20:
14155 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
14156 // CHECK23: omp.inner.for.inc21:
14157 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14158 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
14159 // CHECK23-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
14160 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]]
14161 // CHECK23: omp.inner.for.end23:
14162 // CHECK23-NEXT: br label [[OMP_IF_END]]
14163 // CHECK23: omp_if.end:
14164 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
14165 // CHECK23: omp.loop.exit:
14166 // CHECK23-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14167 // CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
14168 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
14169 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14170 // CHECK23-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
14171 // CHECK23-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14172 // CHECK23: .omp.final.then:
14173 // CHECK23-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14174 // CHECK23-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
14175 // CHECK23-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14176 // CHECK23-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
14177 // CHECK23-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
14178 // CHECK23-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
14179 // CHECK23-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
14180 // CHECK23-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
14181 // CHECK23-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
14182 // CHECK23-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
14183 // CHECK23-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
14184 // CHECK23-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
14185 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
14186 // CHECK23: .omp.final.done:
14187 // CHECK23-NEXT: br label [[OMP_PRECOND_END]]
14188 // CHECK23: omp.precond.end:
14189 // CHECK23-NEXT: ret void
14190 //
14191 //
14192 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
14193 // CHECK23-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
14194 // CHECK23-NEXT: entry:
14195 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14196 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14197 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14198 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
14199 // CHECK23-NEXT: ret void
14200 //
14201 //
14202 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4
14203 // CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
14204 // CHECK23-NEXT: entry:
14205 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14206 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14207 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
14208 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
14209 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4
14210 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
14211 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
14212 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14213 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14214 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4
14215 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14216 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14217 // CHECK23-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
14218 // CHECK23-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
14219 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
14220 // CHECK23-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
14221 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14222 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14223 // CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
14224 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
14225 // CHECK23-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14226 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
14227 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
14228 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
14229 // CHECK23: omp.dispatch.cond:
14230 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14231 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
14232 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14233 // CHECK23: cond.true:
14234 // CHECK23-NEXT: br label [[COND_END:%.*]]
14235 // CHECK23: cond.false:
14236 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14237 // CHECK23-NEXT: br label [[COND_END]]
14238 // CHECK23: cond.end:
14239 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
14240 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14241 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14242 // CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
14243 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14244 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14245 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
14246 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
14247 // CHECK23: omp.dispatch.body:
14248 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
14249 // CHECK23: omp.inner.for.cond:
14250 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
14251 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
14252 // CHECK23-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
14253 // CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14254 // CHECK23: omp.inner.for.body:
14255 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
14256 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
14257 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14258 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
14259 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
14260 // CHECK23: omp.body.continue:
14261 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
14262 // CHECK23: omp.inner.for.inc:
14263 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
14264 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
14265 // CHECK23-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
14266 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
14267 // CHECK23: omp.inner.for.end:
14268 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
14269 // CHECK23: omp.dispatch.inc:
14270 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14271 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14272 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
14273 // CHECK23-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
14274 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14275 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14276 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
14277 // CHECK23-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
14278 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]]
14279 // CHECK23: omp.dispatch.end:
14280 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
14281 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14282 // CHECK23-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
14283 // CHECK23-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14284 // CHECK23: .omp.final.then:
14285 // CHECK23-NEXT: store i32 100, i32* [[I]], align 4
14286 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]]
14287 // CHECK23: .omp.final.done:
14288 // CHECK23-NEXT: ret void
14289 //
14290 //
14291 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70
14292 // CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
14293 // CHECK24-NEXT: entry:
14294 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
14295 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
14296 // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
14297 // CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
14298 // CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
14299 // CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
14300 // CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
14301 // CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
14302 // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
14303 // CHECK24-NEXT: ret void
14304 //
14305 //
14306 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined.
14307 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
14308 // CHECK24-NEXT: entry:
14309 // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14310 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14311 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
14312 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
14313 // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
14314 // CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
14315 // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
14316 // CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4
14317 // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
14318 // CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
14319 // CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14320 // CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14321 // CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4
14322 // CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14323 // CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14324 // CHECK24-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
14325 // CHECK24-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
14326 // CHECK24-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
14327 // CHECK24-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
14328 // CHECK24-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
14329 // CHECK24-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
14330 // CHECK24-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
14331 // CHECK24-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
14332 // CHECK24-NEXT: [[TMP4:%.*]] = load float*, float** [[TMP0]], align 4
14333 // CHECK24-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP4]], i32 16) ]
14334 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
14335 // CHECK24-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
14336 // CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14337 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14338 // CHECK24-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14339 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
14340 // CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14341 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14342 // CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 4571423
14343 // CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14344 // CHECK24: cond.true:
14345 // CHECK24-NEXT: br label [[COND_END:%.*]]
14346 // CHECK24: cond.false:
14347 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14348 // CHECK24-NEXT: br label [[COND_END]]
14349 // CHECK24: cond.end:
14350 // CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
14351 // CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14352 // CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14353 // CHECK24-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
14354 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
14355 // CHECK24: omp.inner.for.cond:
14356 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
14357 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
14358 // CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
14359 // CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14360 // CHECK24: omp.inner.for.body:
14361 // CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
14362 // CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
14363 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
14364 // CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
14365 // CHECK24-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !10
14366 // CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
14367 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
14368 // CHECK24-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
14369 // CHECK24-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !10
14370 // CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
14371 // CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP16]], i32 [[TMP17]]
14372 // CHECK24-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
14373 // CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
14374 // CHECK24-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !10
14375 // CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
14376 // CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP19]], i32 [[TMP20]]
14377 // CHECK24-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !10
14378 // CHECK24-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
14379 // CHECK24-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !10
14380 // CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
14381 // CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP22]], i32 [[TMP23]]
14382 // CHECK24-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
14383 // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
14384 // CHECK24: omp.body.continue:
14385 // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
14386 // CHECK24: omp.inner.for.inc:
14387 // CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
14388 // CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
14389 // CHECK24-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
14390 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
14391 // CHECK24: omp.inner.for.end:
14392 // CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
14393 // CHECK24: omp.loop.exit:
14394 // CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
14395 // CHECK24-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14396 // CHECK24-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
14397 // CHECK24-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14398 // CHECK24: .omp.final.then:
14399 // CHECK24-NEXT: store i32 32000001, i32* [[I]], align 4
14400 // CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
14401 // CHECK24: .omp.final.done:
14402 // CHECK24-NEXT: ret void
14403 //
14404 //
14405 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86
14406 // CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
14407 // CHECK24-NEXT: entry:
14408 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
14409 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
14410 // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
14411 // CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
14412 // CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
14413 // CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
14414 // CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
14415 // CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
14416 // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
14417 // CHECK24-NEXT: ret void
14418 //
14419 //
14420 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1
14421 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
14422 // CHECK24-NEXT: entry:
14423 // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14424 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14425 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
14426 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
14427 // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
14428 // CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
14429 // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
14430 // CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4
14431 // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
14432 // CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
14433 // CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14434 // CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14435 // CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4
14436 // CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14437 // CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14438 // CHECK24-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
14439 // CHECK24-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
14440 // CHECK24-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
14441 // CHECK24-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
14442 // CHECK24-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
14443 // CHECK24-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
14444 // CHECK24-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
14445 // CHECK24-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
14446 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
14447 // CHECK24-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
14448 // CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14449 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14450 // CHECK24-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14451 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
14452 // CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14453 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14454 // CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
14455 // CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14456 // CHECK24: cond.true:
14457 // CHECK24-NEXT: br label [[COND_END:%.*]]
14458 // CHECK24: cond.false:
14459 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14460 // CHECK24-NEXT: br label [[COND_END]]
14461 // CHECK24: cond.end:
14462 // CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
14463 // CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14464 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14465 // CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
14466 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
14467 // CHECK24: omp.inner.for.cond:
14468 // CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14469 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14470 // CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
14471 // CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14472 // CHECK24: omp.inner.for.body:
14473 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14474 // CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
14475 // CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
14476 // CHECK24-NEXT: store i32 [[SUB]], i32* [[I]], align 4
14477 // CHECK24-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 4, !nontemporal !17
14478 // CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
14479 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i32 [[TMP13]]
14480 // CHECK24-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4
14481 // CHECK24-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 4
14482 // CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4
14483 // CHECK24-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP15]], i32 [[TMP16]]
14484 // CHECK24-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX2]], align 4
14485 // CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
14486 // CHECK24-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 4
14487 // CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
14488 // CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP18]], i32 [[TMP19]]
14489 // CHECK24-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX4]], align 4
14490 // CHECK24-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
14491 // CHECK24-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 4, !nontemporal !17
14492 // CHECK24-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
14493 // CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 [[TMP22]]
14494 // CHECK24-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
14495 // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
14496 // CHECK24: omp.body.continue:
14497 // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
14498 // CHECK24: omp.inner.for.inc:
14499 // CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14500 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
14501 // CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
14502 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
14503 // CHECK24: omp.inner.for.end:
14504 // CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
14505 // CHECK24: omp.loop.exit:
14506 // CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
14507 // CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14508 // CHECK24-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
14509 // CHECK24-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14510 // CHECK24: .omp.final.then:
14511 // CHECK24-NEXT: store i32 32, i32* [[I]], align 4
14512 // CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
14513 // CHECK24: .omp.final.done:
14514 // CHECK24-NEXT: ret void
14515 //
14516 //
14517 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103
14518 // CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
14519 // CHECK24-NEXT: entry:
14520 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
14521 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
14522 // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
14523 // CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
14524 // CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
14525 // CHECK24-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
14526 // CHECK24-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
14527 // CHECK24-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
14528 // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]])
14529 // CHECK24-NEXT: ret void
14530 //
14531 //
14532 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2
14533 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] {
14534 // CHECK24-NEXT: entry:
14535 // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14536 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14537 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float**, align 4
14538 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float**, align 4
14539 // CHECK24-NEXT: [[C_ADDR:%.*]] = alloca float**, align 4
14540 // CHECK24-NEXT: [[D_ADDR:%.*]] = alloca float**, align 4
14541 // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
14542 // CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4
14543 // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
14544 // CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
14545 // CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14546 // CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14547 // CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4
14548 // CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14549 // CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14550 // CHECK24-NEXT: store float** [[A]], float*** [[A_ADDR]], align 4
14551 // CHECK24-NEXT: store float** [[B]], float*** [[B_ADDR]], align 4
14552 // CHECK24-NEXT: store float** [[C]], float*** [[C_ADDR]], align 4
14553 // CHECK24-NEXT: store float** [[D]], float*** [[D_ADDR]], align 4
14554 // CHECK24-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 4
14555 // CHECK24-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 4
14556 // CHECK24-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 4
14557 // CHECK24-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 4
14558 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
14559 // CHECK24-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
14560 // CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14561 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14562 // CHECK24-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14563 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
14564 // CHECK24-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5)
14565 // CHECK24-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
14566 // CHECK24: omp.dispatch.cond:
14567 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14568 // CHECK24-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
14569 // CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14570 // CHECK24: cond.true:
14571 // CHECK24-NEXT: br label [[COND_END:%.*]]
14572 // CHECK24: cond.false:
14573 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14574 // CHECK24-NEXT: br label [[COND_END]]
14575 // CHECK24: cond.end:
14576 // CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
14577 // CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14578 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14579 // CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
14580 // CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14581 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14582 // CHECK24-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
14583 // CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
14584 // CHECK24: omp.dispatch.body:
14585 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
14586 // CHECK24: omp.inner.for.cond:
14587 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
14588 // CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
14589 // CHECK24-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
14590 // CHECK24-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14591 // CHECK24: omp.inner.for.body:
14592 // CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
14593 // CHECK24-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
14594 // CHECK24-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
14595 // CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20
14596 // CHECK24-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 4, !llvm.access.group !20
14597 // CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
14598 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
14599 // CHECK24-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !20
14600 // CHECK24-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 4, !llvm.access.group !20
14601 // CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
14602 // CHECK24-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP17]], i32 [[TMP18]]
14603 // CHECK24-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !20
14604 // CHECK24-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
14605 // CHECK24-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 4, !llvm.access.group !20
14606 // CHECK24-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
14607 // CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 [[TMP21]]
14608 // CHECK24-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !20
14609 // CHECK24-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
14610 // CHECK24-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 4, !llvm.access.group !20
14611 // CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !20
14612 // CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP23]], i32 [[TMP24]]
14613 // CHECK24-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !20
14614 // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
14615 // CHECK24: omp.body.continue:
14616 // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
14617 // CHECK24: omp.inner.for.inc:
14618 // CHECK24-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
14619 // CHECK24-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
14620 // CHECK24-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
14621 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
14622 // CHECK24: omp.inner.for.end:
14623 // CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
14624 // CHECK24: omp.dispatch.inc:
14625 // CHECK24-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14626 // CHECK24-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14627 // CHECK24-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
14628 // CHECK24-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
14629 // CHECK24-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14630 // CHECK24-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14631 // CHECK24-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]]
14632 // CHECK24-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_UB]], align 4
14633 // CHECK24-NEXT: br label [[OMP_DISPATCH_COND]]
14634 // CHECK24: omp.dispatch.end:
14635 // CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
14636 // CHECK24-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14637 // CHECK24-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
14638 // CHECK24-NEXT: br i1 [[TMP31]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14639 // CHECK24: .omp.final.then:
14640 // CHECK24-NEXT: store i32 -2147483522, i32* [[I]], align 4
14641 // CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
14642 // CHECK24: .omp.final.done:
14643 // CHECK24-NEXT: ret void
14644 //
14645 //
14646 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115
14647 // CHECK24-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
14648 // CHECK24-NEXT: entry:
14649 // CHECK24-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
14650 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
14651 // CHECK24-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
14652 // CHECK24-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
14653 // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[I_ADDR]] to i8*
14654 // CHECK24-NEXT: [[CONV1:%.*]] = bitcast i32* [[A_ADDR]] to i8*
14655 // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8*, i8*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i8* [[CONV]], i8* [[CONV1]])
14656 // CHECK24-NEXT: ret void
14657 //
14658 //
14659 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3
14660 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] {
14661 // CHECK24-NEXT: entry:
14662 // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14663 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14664 // CHECK24-NEXT: [[I_ADDR:%.*]] = alloca i8*, align 4
14665 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i8*, align 4
14666 // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
14667 // CHECK24-NEXT: [[TMP:%.*]] = alloca i8, align 1
14668 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
14669 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
14670 // CHECK24-NEXT: [[I4:%.*]] = alloca i8, align 1
14671 // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
14672 // CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
14673 // CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14674 // CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14675 // CHECK24-NEXT: [[I6:%.*]] = alloca i8, align 1
14676 // CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14677 // CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14678 // CHECK24-NEXT: store i8* [[I]], i8** [[I_ADDR]], align 4
14679 // CHECK24-NEXT: store i8* [[A]], i8** [[A_ADDR]], align 4
14680 // CHECK24-NEXT: [[TMP0:%.*]] = load i8*, i8** [[I_ADDR]], align 4
14681 // CHECK24-NEXT: [[TMP1:%.*]] = load i8*, i8** [[A_ADDR]], align 4
14682 // CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
14683 // CHECK24-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1
14684 // CHECK24-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14685 // CHECK24-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32
14686 // CHECK24-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
14687 // CHECK24-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
14688 // CHECK24-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
14689 // CHECK24-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
14690 // CHECK24-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
14691 // CHECK24-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
14692 // CHECK24-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14693 // CHECK24-NEXT: store i8 [[TMP4]], i8* [[I4]], align 1
14694 // CHECK24-NEXT: [[TMP5:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14695 // CHECK24-NEXT: [[CONV5:%.*]] = sext i8 [[TMP5]] to i32
14696 // CHECK24-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
14697 // CHECK24-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
14698 // CHECK24: omp.precond.then:
14699 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
14700 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
14701 // CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
14702 // CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14703 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14704 // CHECK24-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14705 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
14706 // CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14707 // CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14708 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
14709 // CHECK24-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
14710 // CHECK24-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14711 // CHECK24: cond.true:
14712 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
14713 // CHECK24-NEXT: br label [[COND_END:%.*]]
14714 // CHECK24: cond.false:
14715 // CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14716 // CHECK24-NEXT: br label [[COND_END]]
14717 // CHECK24: cond.end:
14718 // CHECK24-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
14719 // CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14720 // CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14721 // CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
14722 // CHECK24-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP1]], align 1
14723 // CHECK24-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
14724 // CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
14725 // CHECK24: omp_if.then:
14726 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
14727 // CHECK24: omp.inner.for.cond:
14728 // CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
14729 // CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23
14730 // CHECK24-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
14731 // CHECK24-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14732 // CHECK24: omp.inner.for.body:
14733 // CHECK24-NEXT: [[TMP17:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !23
14734 // CHECK24-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
14735 // CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
14736 // CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
14737 // CHECK24-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
14738 // CHECK24-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
14739 // CHECK24-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !17, !llvm.access.group !23
14740 // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
14741 // CHECK24: omp.body.continue:
14742 // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
14743 // CHECK24: omp.inner.for.inc:
14744 // CHECK24-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
14745 // CHECK24-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
14746 // CHECK24-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
14747 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
14748 // CHECK24: omp.inner.for.end:
14749 // CHECK24-NEXT: br label [[OMP_IF_END:%.*]]
14750 // CHECK24: omp_if.else:
14751 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
14752 // CHECK24: omp.inner.for.cond13:
14753 // CHECK24-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14754 // CHECK24-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14755 // CHECK24-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
14756 // CHECK24-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
14757 // CHECK24: omp.inner.for.body15:
14758 // CHECK24-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14759 // CHECK24-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
14760 // CHECK24-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14761 // CHECK24-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
14762 // CHECK24-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
14763 // CHECK24-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
14764 // CHECK24-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
14765 // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
14766 // CHECK24: omp.body.continue20:
14767 // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
14768 // CHECK24: omp.inner.for.inc21:
14769 // CHECK24-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14770 // CHECK24-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
14771 // CHECK24-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
14772 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]]
14773 // CHECK24: omp.inner.for.end23:
14774 // CHECK24-NEXT: br label [[OMP_IF_END]]
14775 // CHECK24: omp_if.end:
14776 // CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
14777 // CHECK24: omp.loop.exit:
14778 // CHECK24-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14779 // CHECK24-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
14780 // CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
14781 // CHECK24-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14782 // CHECK24-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
14783 // CHECK24-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14784 // CHECK24: .omp.final.then:
14785 // CHECK24-NEXT: [[TMP29:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14786 // CHECK24-NEXT: [[CONV24:%.*]] = sext i8 [[TMP29]] to i32
14787 // CHECK24-NEXT: [[TMP30:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
14788 // CHECK24-NEXT: [[CONV25:%.*]] = sext i8 [[TMP30]] to i32
14789 // CHECK24-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
14790 // CHECK24-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
14791 // CHECK24-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
14792 // CHECK24-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
14793 // CHECK24-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
14794 // CHECK24-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
14795 // CHECK24-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
14796 // CHECK24-NEXT: store i8 [[CONV32]], i8* [[TMP0]], align 1
14797 // CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
14798 // CHECK24: .omp.final.done:
14799 // CHECK24-NEXT: br label [[OMP_PRECOND_END]]
14800 // CHECK24: omp.precond.end:
14801 // CHECK24-NEXT: ret void
14802 //
14803 //
14804 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135
14805 // CHECK24-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
14806 // CHECK24-NEXT: entry:
14807 // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
14808 // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
14809 // CHECK24-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14810 // CHECK24-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i16*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i16* [[CONV]])
14811 // CHECK24-NEXT: ret void
14812 //
14813 //
14814 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4
14815 // CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] {
14816 // CHECK24-NEXT: entry:
14817 // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14818 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14819 // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4
14820 // CHECK24-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
14821 // CHECK24-NEXT: [[TMP:%.*]] = alloca i32, align 4
14822 // CHECK24-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
14823 // CHECK24-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
14824 // CHECK24-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14825 // CHECK24-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14826 // CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4
14827 // CHECK24-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14828 // CHECK24-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14829 // CHECK24-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4
14830 // CHECK24-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4
14831 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
14832 // CHECK24-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
14833 // CHECK24-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14834 // CHECK24-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14835 // CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
14836 // CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
14837 // CHECK24-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14838 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
14839 // CHECK24-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]])
14840 // CHECK24-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
14841 // CHECK24: omp.dispatch.cond:
14842 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14843 // CHECK24-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99
14844 // CHECK24-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14845 // CHECK24: cond.true:
14846 // CHECK24-NEXT: br label [[COND_END:%.*]]
14847 // CHECK24: cond.false:
14848 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14849 // CHECK24-NEXT: br label [[COND_END]]
14850 // CHECK24: cond.end:
14851 // CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
14852 // CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14853 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14854 // CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
14855 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14856 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14857 // CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
14858 // CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
14859 // CHECK24: omp.dispatch.body:
14860 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
14861 // CHECK24: omp.inner.for.cond:
14862 // CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
14863 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
14864 // CHECK24-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
14865 // CHECK24-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14866 // CHECK24: omp.inner.for.body:
14867 // CHECK24-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
14868 // CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
14869 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14870 // CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
14871 // CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
14872 // CHECK24: omp.body.continue:
14873 // CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
14874 // CHECK24: omp.inner.for.inc:
14875 // CHECK24-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
14876 // CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
14877 // CHECK24-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
14878 // CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
14879 // CHECK24: omp.inner.for.end:
14880 // CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
14881 // CHECK24: omp.dispatch.inc:
14882 // CHECK24-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14883 // CHECK24-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14884 // CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
14885 // CHECK24-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
14886 // CHECK24-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14887 // CHECK24-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14888 // CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
14889 // CHECK24-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
14890 // CHECK24-NEXT: br label [[OMP_DISPATCH_COND]]
14891 // CHECK24: omp.dispatch.end:
14892 // CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
14893 // CHECK24-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14894 // CHECK24-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
14895 // CHECK24-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14896 // CHECK24: .omp.final.then:
14897 // CHECK24-NEXT: store i32 100, i32* [[I]], align 4
14898 // CHECK24-NEXT: br label [[DOTOMP_FINAL_DONE]]
14899 // CHECK24: .omp.final.done:
14900 // CHECK24-NEXT: ret void
14901 //
14902 //
14903 // CHECK25-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
14904 // CHECK25-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
14905 // CHECK25-NEXT: entry:
14906 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
14907 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
14908 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
14909 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
14910 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4
14911 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
14912 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
14913 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
14914 // CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4
14915 // CHECK25-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
14916 // CHECK25-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
14917 // CHECK25-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
14918 // CHECK25-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
14919 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
14920 // CHECK25-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
14921 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14922 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
14923 // CHECK25-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
14924 // CHECK25-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
14925 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
14926 // CHECK25: omp.inner.for.cond:
14927 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14928 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
14929 // CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
14930 // CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14931 // CHECK25: omp.inner.for.body:
14932 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14933 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
14934 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
14935 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
14936 // CHECK25-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
14937 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
14938 // CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
14939 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
14940 // CHECK25-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
14941 // CHECK25-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
14942 // CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
14943 // CHECK25-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
14944 // CHECK25-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
14945 // CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
14946 // CHECK25-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
14947 // CHECK25-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
14948 // CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
14949 // CHECK25-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
14950 // CHECK25-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
14951 // CHECK25-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
14952 // CHECK25-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
14953 // CHECK25-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
14954 // CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
14955 // CHECK25-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
14956 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
14957 // CHECK25-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
14958 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
14959 // CHECK25: omp.body.continue:
14960 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
14961 // CHECK25: omp.inner.for.inc:
14962 // CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14963 // CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
14964 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14965 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
14966 // CHECK25: omp.inner.for.end:
14967 // CHECK25-NEXT: store i32 32000001, i32* [[I]], align 4
14968 // CHECK25-NEXT: ret void
14969 //
14970 //
14971 // CHECK25-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
14972 // CHECK25-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
14973 // CHECK25-NEXT: entry:
14974 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
14975 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
14976 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
14977 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
14978 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4
14979 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
14980 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
14981 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
14982 // CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4
14983 // CHECK25-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
14984 // CHECK25-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
14985 // CHECK25-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
14986 // CHECK25-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
14987 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
14988 // CHECK25-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
14989 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14990 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
14991 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
14992 // CHECK25: omp.inner.for.cond:
14993 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14994 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14995 // CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
14996 // CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14997 // CHECK25: omp.inner.for.body:
14998 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14999 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
15000 // CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
15001 // CHECK25-NEXT: store i32 [[SUB]], i32* [[I]], align 4
15002 // CHECK25-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8
15003 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
15004 // CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
15005 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
15006 // CHECK25-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
15007 // CHECK25-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
15008 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
15009 // CHECK25-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
15010 // CHECK25-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
15011 // CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
15012 // CHECK25-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
15013 // CHECK25-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
15014 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
15015 // CHECK25-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
15016 // CHECK25-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
15017 // CHECK25-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
15018 // CHECK25-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
15019 // CHECK25-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8
15020 // CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
15021 // CHECK25-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
15022 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
15023 // CHECK25-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
15024 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15025 // CHECK25: omp.body.continue:
15026 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15027 // CHECK25: omp.inner.for.inc:
15028 // CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15029 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
15030 // CHECK25-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
15031 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
15032 // CHECK25: omp.inner.for.end:
15033 // CHECK25-NEXT: store i32 32, i32* [[I]], align 4
15034 // CHECK25-NEXT: ret void
15035 //
15036 //
15037 // CHECK25-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
15038 // CHECK25-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
15039 // CHECK25-NEXT: entry:
15040 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
15041 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
15042 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
15043 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
15044 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4
15045 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15046 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15047 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15048 // CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4
15049 // CHECK25-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
15050 // CHECK25-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
15051 // CHECK25-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
15052 // CHECK25-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
15053 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15054 // CHECK25-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
15055 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15056 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15057 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15058 // CHECK25: omp.inner.for.cond:
15059 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
15060 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
15061 // CHECK25-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
15062 // CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15063 // CHECK25: omp.inner.for.body:
15064 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
15065 // CHECK25-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
15066 // CHECK25-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
15067 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
15068 // CHECK25-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !9
15069 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
15070 // CHECK25-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
15071 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
15072 // CHECK25-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
15073 // CHECK25-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !9
15074 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
15075 // CHECK25-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
15076 // CHECK25-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
15077 // CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
15078 // CHECK25-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
15079 // CHECK25-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !9
15080 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
15081 // CHECK25-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
15082 // CHECK25-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
15083 // CHECK25-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !9
15084 // CHECK25-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
15085 // CHECK25-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !9
15086 // CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
15087 // CHECK25-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
15088 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
15089 // CHECK25-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !9
15090 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15091 // CHECK25: omp.body.continue:
15092 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15093 // CHECK25: omp.inner.for.inc:
15094 // CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
15095 // CHECK25-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
15096 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
15097 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
15098 // CHECK25: omp.inner.for.end:
15099 // CHECK25-NEXT: store i32 -2147483522, i32* [[I]], align 4
15100 // CHECK25-NEXT: ret void
15101 //
15102 //
15103 // CHECK25-LABEL: define {{[^@]+}}@_Z12test_precondv
15104 // CHECK25-SAME: () #[[ATTR0]] {
15105 // CHECK25-NEXT: entry:
15106 // CHECK25-NEXT: [[A:%.*]] = alloca i8, align 1
15107 // CHECK25-NEXT: [[I:%.*]] = alloca i8, align 1
15108 // CHECK25-NEXT: [[TMP:%.*]] = alloca i8, align 1
15109 // CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
15110 // CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
15111 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15112 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15113 // CHECK25-NEXT: [[I4:%.*]] = alloca i8, align 1
15114 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15115 // CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
15116 // CHECK25-NEXT: [[I6:%.*]] = alloca i8, align 1
15117 // CHECK25-NEXT: [[I7:%.*]] = alloca i8, align 1
15118 // CHECK25-NEXT: store i8 0, i8* [[A]], align 1
15119 // CHECK25-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
15120 // CHECK25-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
15121 // CHECK25-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15122 // CHECK25-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
15123 // CHECK25-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
15124 // CHECK25-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
15125 // CHECK25-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
15126 // CHECK25-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
15127 // CHECK25-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
15128 // CHECK25-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
15129 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15130 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
15131 // CHECK25-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
15132 // CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15133 // CHECK25-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
15134 // CHECK25-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15135 // CHECK25-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
15136 // CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
15137 // CHECK25-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
15138 // CHECK25: simd.if.then:
15139 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15140 // CHECK25-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
15141 // CHECK25-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
15142 // CHECK25-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
15143 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15144 // CHECK25: omp.inner.for.cond:
15145 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
15146 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
15147 // CHECK25-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
15148 // CHECK25-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15149 // CHECK25: omp.inner.for.body:
15150 // CHECK25-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !12
15151 // CHECK25-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
15152 // CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
15153 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
15154 // CHECK25-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
15155 // CHECK25-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
15156 // CHECK25-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !12
15157 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15158 // CHECK25: omp.body.continue:
15159 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15160 // CHECK25: omp.inner.for.inc:
15161 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
15162 // CHECK25-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
15163 // CHECK25-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
15164 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
15165 // CHECK25: omp.inner.for.end:
15166 // CHECK25-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15167 // CHECK25-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
15168 // CHECK25-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15169 // CHECK25-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
15170 // CHECK25-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
15171 // CHECK25-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
15172 // CHECK25-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
15173 // CHECK25-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
15174 // CHECK25-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
15175 // CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
15176 // CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
15177 // CHECK25-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
15178 // CHECK25-NEXT: br label [[SIMD_IF_END]]
15179 // CHECK25: simd.if.end:
15180 // CHECK25-NEXT: ret void
15181 //
15182 //
15183 // CHECK25-LABEL: define {{[^@]+}}@_Z4fintv
15184 // CHECK25-SAME: () #[[ATTR0]] {
15185 // CHECK25-NEXT: entry:
15186 // CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
15187 // CHECK25-NEXT: ret i32 [[CALL]]
15188 //
15189 //
15190 // CHECK25-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
15191 // CHECK25-SAME: () #[[ATTR0]] comdat {
15192 // CHECK25-NEXT: entry:
15193 // CHECK25-NEXT: [[AA:%.*]] = alloca i16, align 2
15194 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4
15195 // CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15196 // CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15197 // CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15198 // CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4
15199 // CHECK25-NEXT: store i16 0, i16* [[AA]], align 2
15200 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15201 // CHECK25-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
15202 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15203 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15204 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15205 // CHECK25: omp.inner.for.cond:
15206 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
15207 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15
15208 // CHECK25-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
15209 // CHECK25-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15210 // CHECK25: omp.inner.for.body:
15211 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
15212 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
15213 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15214 // CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
15215 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15216 // CHECK25: omp.body.continue:
15217 // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15218 // CHECK25: omp.inner.for.inc:
15219 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
15220 // CHECK25-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
15221 // CHECK25-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
15222 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
15223 // CHECK25: omp.inner.for.end:
15224 // CHECK25-NEXT: store i32 100, i32* [[I]], align 4
15225 // CHECK25-NEXT: ret i32 0
15226 //
15227 //
15228 // CHECK26-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
15229 // CHECK26-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
15230 // CHECK26-NEXT: entry:
15231 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
15232 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
15233 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
15234 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
15235 // CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4
15236 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15237 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15238 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15239 // CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4
15240 // CHECK26-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
15241 // CHECK26-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
15242 // CHECK26-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
15243 // CHECK26-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
15244 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15245 // CHECK26-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
15246 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15247 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15248 // CHECK26-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
15249 // CHECK26-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
15250 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15251 // CHECK26: omp.inner.for.cond:
15252 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15253 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
15254 // CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
15255 // CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15256 // CHECK26: omp.inner.for.body:
15257 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15258 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
15259 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
15260 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
15261 // CHECK26-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
15262 // CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
15263 // CHECK26-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
15264 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
15265 // CHECK26-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
15266 // CHECK26-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
15267 // CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
15268 // CHECK26-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
15269 // CHECK26-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
15270 // CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
15271 // CHECK26-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
15272 // CHECK26-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
15273 // CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
15274 // CHECK26-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
15275 // CHECK26-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
15276 // CHECK26-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
15277 // CHECK26-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
15278 // CHECK26-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
15279 // CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
15280 // CHECK26-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
15281 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
15282 // CHECK26-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
15283 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15284 // CHECK26: omp.body.continue:
15285 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15286 // CHECK26: omp.inner.for.inc:
15287 // CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15288 // CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
15289 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
15290 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
15291 // CHECK26: omp.inner.for.end:
15292 // CHECK26-NEXT: store i32 32000001, i32* [[I]], align 4
15293 // CHECK26-NEXT: ret void
15294 //
15295 //
15296 // CHECK26-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
15297 // CHECK26-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
15298 // CHECK26-NEXT: entry:
15299 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
15300 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
15301 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
15302 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
15303 // CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4
15304 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15305 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15306 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15307 // CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4
15308 // CHECK26-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
15309 // CHECK26-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
15310 // CHECK26-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
15311 // CHECK26-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
15312 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15313 // CHECK26-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
15314 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15315 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15316 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15317 // CHECK26: omp.inner.for.cond:
15318 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15319 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15320 // CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
15321 // CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15322 // CHECK26: omp.inner.for.body:
15323 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15324 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
15325 // CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
15326 // CHECK26-NEXT: store i32 [[SUB]], i32* [[I]], align 4
15327 // CHECK26-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8
15328 // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
15329 // CHECK26-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
15330 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
15331 // CHECK26-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
15332 // CHECK26-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
15333 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
15334 // CHECK26-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
15335 // CHECK26-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
15336 // CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
15337 // CHECK26-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
15338 // CHECK26-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
15339 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
15340 // CHECK26-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
15341 // CHECK26-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
15342 // CHECK26-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
15343 // CHECK26-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
15344 // CHECK26-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8
15345 // CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
15346 // CHECK26-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
15347 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
15348 // CHECK26-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
15349 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15350 // CHECK26: omp.body.continue:
15351 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15352 // CHECK26: omp.inner.for.inc:
15353 // CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15354 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
15355 // CHECK26-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
15356 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
15357 // CHECK26: omp.inner.for.end:
15358 // CHECK26-NEXT: store i32 32, i32* [[I]], align 4
15359 // CHECK26-NEXT: ret void
15360 //
15361 //
15362 // CHECK26-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
15363 // CHECK26-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
15364 // CHECK26-NEXT: entry:
15365 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
15366 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
15367 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
15368 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
15369 // CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4
15370 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15371 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15372 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15373 // CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4
15374 // CHECK26-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
15375 // CHECK26-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
15376 // CHECK26-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
15377 // CHECK26-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
15378 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15379 // CHECK26-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
15380 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15381 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15382 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15383 // CHECK26: omp.inner.for.cond:
15384 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
15385 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9
15386 // CHECK26-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
15387 // CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15388 // CHECK26: omp.inner.for.body:
15389 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
15390 // CHECK26-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
15391 // CHECK26-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
15392 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
15393 // CHECK26-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !9
15394 // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
15395 // CHECK26-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
15396 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
15397 // CHECK26-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !9
15398 // CHECK26-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !9
15399 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
15400 // CHECK26-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
15401 // CHECK26-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
15402 // CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !9
15403 // CHECK26-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
15404 // CHECK26-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !9
15405 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
15406 // CHECK26-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
15407 // CHECK26-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
15408 // CHECK26-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !9
15409 // CHECK26-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
15410 // CHECK26-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !9
15411 // CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9
15412 // CHECK26-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
15413 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
15414 // CHECK26-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !9
15415 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15416 // CHECK26: omp.body.continue:
15417 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15418 // CHECK26: omp.inner.for.inc:
15419 // CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
15420 // CHECK26-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
15421 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
15422 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
15423 // CHECK26: omp.inner.for.end:
15424 // CHECK26-NEXT: store i32 -2147483522, i32* [[I]], align 4
15425 // CHECK26-NEXT: ret void
15426 //
15427 //
15428 // CHECK26-LABEL: define {{[^@]+}}@_Z12test_precondv
15429 // CHECK26-SAME: () #[[ATTR0]] {
15430 // CHECK26-NEXT: entry:
15431 // CHECK26-NEXT: [[A:%.*]] = alloca i8, align 1
15432 // CHECK26-NEXT: [[I:%.*]] = alloca i8, align 1
15433 // CHECK26-NEXT: [[TMP:%.*]] = alloca i8, align 1
15434 // CHECK26-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
15435 // CHECK26-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
15436 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15437 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15438 // CHECK26-NEXT: [[I4:%.*]] = alloca i8, align 1
15439 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15440 // CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
15441 // CHECK26-NEXT: [[I6:%.*]] = alloca i8, align 1
15442 // CHECK26-NEXT: [[I7:%.*]] = alloca i8, align 1
15443 // CHECK26-NEXT: store i8 0, i8* [[A]], align 1
15444 // CHECK26-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
15445 // CHECK26-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
15446 // CHECK26-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15447 // CHECK26-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
15448 // CHECK26-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
15449 // CHECK26-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
15450 // CHECK26-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
15451 // CHECK26-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
15452 // CHECK26-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
15453 // CHECK26-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
15454 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15455 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
15456 // CHECK26-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
15457 // CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15458 // CHECK26-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
15459 // CHECK26-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15460 // CHECK26-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
15461 // CHECK26-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
15462 // CHECK26-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
15463 // CHECK26: simd.if.then:
15464 // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15465 // CHECK26-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
15466 // CHECK26-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
15467 // CHECK26-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
15468 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15469 // CHECK26: omp.inner.for.cond:
15470 // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
15471 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
15472 // CHECK26-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
15473 // CHECK26-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15474 // CHECK26: omp.inner.for.body:
15475 // CHECK26-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !12
15476 // CHECK26-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
15477 // CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
15478 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
15479 // CHECK26-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
15480 // CHECK26-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
15481 // CHECK26-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !12
15482 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15483 // CHECK26: omp.body.continue:
15484 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15485 // CHECK26: omp.inner.for.inc:
15486 // CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
15487 // CHECK26-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
15488 // CHECK26-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
15489 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
15490 // CHECK26: omp.inner.for.end:
15491 // CHECK26-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15492 // CHECK26-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
15493 // CHECK26-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15494 // CHECK26-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
15495 // CHECK26-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
15496 // CHECK26-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
15497 // CHECK26-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
15498 // CHECK26-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
15499 // CHECK26-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
15500 // CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
15501 // CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
15502 // CHECK26-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
15503 // CHECK26-NEXT: br label [[SIMD_IF_END]]
15504 // CHECK26: simd.if.end:
15505 // CHECK26-NEXT: ret void
15506 //
15507 //
15508 // CHECK26-LABEL: define {{[^@]+}}@_Z4fintv
15509 // CHECK26-SAME: () #[[ATTR0]] {
15510 // CHECK26-NEXT: entry:
15511 // CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
15512 // CHECK26-NEXT: ret i32 [[CALL]]
15513 //
15514 //
15515 // CHECK26-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
15516 // CHECK26-SAME: () #[[ATTR0]] comdat {
15517 // CHECK26-NEXT: entry:
15518 // CHECK26-NEXT: [[AA:%.*]] = alloca i16, align 2
15519 // CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4
15520 // CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15521 // CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15522 // CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15523 // CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4
15524 // CHECK26-NEXT: store i16 0, i16* [[AA]], align 2
15525 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15526 // CHECK26-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
15527 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15528 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15529 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15530 // CHECK26: omp.inner.for.cond:
15531 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
15532 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15
15533 // CHECK26-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
15534 // CHECK26-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15535 // CHECK26: omp.inner.for.body:
15536 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
15537 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
15538 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15539 // CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
15540 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15541 // CHECK26: omp.body.continue:
15542 // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15543 // CHECK26: omp.inner.for.inc:
15544 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
15545 // CHECK26-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
15546 // CHECK26-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
15547 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
15548 // CHECK26: omp.inner.for.end:
15549 // CHECK26-NEXT: store i32 100, i32* [[I]], align 4
15550 // CHECK26-NEXT: ret i32 0
15551 //
15552 //
15553 // CHECK27-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
15554 // CHECK27-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
15555 // CHECK27-NEXT: entry:
15556 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
15557 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
15558 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
15559 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
15560 // CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4
15561 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15562 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15563 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15564 // CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4
15565 // CHECK27-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
15566 // CHECK27-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
15567 // CHECK27-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
15568 // CHECK27-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
15569 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15570 // CHECK27-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
15571 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15572 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15573 // CHECK27-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
15574 // CHECK27-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
15575 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15576 // CHECK27: omp.inner.for.cond:
15577 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15578 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
15579 // CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
15580 // CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15581 // CHECK27: omp.inner.for.body:
15582 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15583 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
15584 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
15585 // CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
15586 // CHECK27-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
15587 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
15588 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
15589 // CHECK27-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
15590 // CHECK27-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
15591 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
15592 // CHECK27-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
15593 // CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
15594 // CHECK27-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
15595 // CHECK27-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
15596 // CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
15597 // CHECK27-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
15598 // CHECK27-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
15599 // CHECK27-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
15600 // CHECK27-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
15601 // CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
15602 // CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
15603 // CHECK27-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
15604 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15605 // CHECK27: omp.body.continue:
15606 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15607 // CHECK27: omp.inner.for.inc:
15608 // CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15609 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
15610 // CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15611 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
15612 // CHECK27: omp.inner.for.end:
15613 // CHECK27-NEXT: store i32 32000001, i32* [[I]], align 4
15614 // CHECK27-NEXT: ret void
15615 //
15616 //
15617 // CHECK27-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
15618 // CHECK27-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
15619 // CHECK27-NEXT: entry:
15620 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
15621 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
15622 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
15623 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
15624 // CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4
15625 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15626 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15627 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15628 // CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4
15629 // CHECK27-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
15630 // CHECK27-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
15631 // CHECK27-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
15632 // CHECK27-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
15633 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15634 // CHECK27-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
15635 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15636 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15637 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15638 // CHECK27: omp.inner.for.cond:
15639 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15640 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15641 // CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
15642 // CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15643 // CHECK27: omp.inner.for.body:
15644 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15645 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
15646 // CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
15647 // CHECK27-NEXT: store i32 [[SUB]], i32* [[I]], align 4
15648 // CHECK27-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4
15649 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
15650 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
15651 // CHECK27-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
15652 // CHECK27-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
15653 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
15654 // CHECK27-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
15655 // CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
15656 // CHECK27-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
15657 // CHECK27-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
15658 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
15659 // CHECK27-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
15660 // CHECK27-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
15661 // CHECK27-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
15662 // CHECK27-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4
15663 // CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
15664 // CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
15665 // CHECK27-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
15666 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15667 // CHECK27: omp.body.continue:
15668 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15669 // CHECK27: omp.inner.for.inc:
15670 // CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15671 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
15672 // CHECK27-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
15673 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
15674 // CHECK27: omp.inner.for.end:
15675 // CHECK27-NEXT: store i32 32, i32* [[I]], align 4
15676 // CHECK27-NEXT: ret void
15677 //
15678 //
15679 // CHECK27-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
15680 // CHECK27-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
15681 // CHECK27-NEXT: entry:
15682 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
15683 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
15684 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
15685 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
15686 // CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4
15687 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15688 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15689 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15690 // CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4
15691 // CHECK27-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
15692 // CHECK27-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
15693 // CHECK27-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
15694 // CHECK27-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
15695 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15696 // CHECK27-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
15697 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15698 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15699 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15700 // CHECK27: omp.inner.for.cond:
15701 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
15702 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
15703 // CHECK27-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
15704 // CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15705 // CHECK27: omp.inner.for.body:
15706 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
15707 // CHECK27-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
15708 // CHECK27-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
15709 // CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
15710 // CHECK27-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !10
15711 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
15712 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
15713 // CHECK27-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
15714 // CHECK27-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !10
15715 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
15716 // CHECK27-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
15717 // CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !10
15718 // CHECK27-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
15719 // CHECK27-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !10
15720 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
15721 // CHECK27-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
15722 // CHECK27-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10
15723 // CHECK27-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
15724 // CHECK27-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !10
15725 // CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
15726 // CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
15727 // CHECK27-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
15728 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15729 // CHECK27: omp.body.continue:
15730 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15731 // CHECK27: omp.inner.for.inc:
15732 // CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
15733 // CHECK27-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
15734 // CHECK27-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
15735 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
15736 // CHECK27: omp.inner.for.end:
15737 // CHECK27-NEXT: store i32 -2147483522, i32* [[I]], align 4
15738 // CHECK27-NEXT: ret void
15739 //
15740 //
15741 // CHECK27-LABEL: define {{[^@]+}}@_Z12test_precondv
15742 // CHECK27-SAME: () #[[ATTR0]] {
15743 // CHECK27-NEXT: entry:
15744 // CHECK27-NEXT: [[A:%.*]] = alloca i8, align 1
15745 // CHECK27-NEXT: [[I:%.*]] = alloca i8, align 1
15746 // CHECK27-NEXT: [[TMP:%.*]] = alloca i8, align 1
15747 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
15748 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
15749 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15750 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15751 // CHECK27-NEXT: [[I4:%.*]] = alloca i8, align 1
15752 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15753 // CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
15754 // CHECK27-NEXT: [[I6:%.*]] = alloca i8, align 1
15755 // CHECK27-NEXT: [[I7:%.*]] = alloca i8, align 1
15756 // CHECK27-NEXT: store i8 0, i8* [[A]], align 1
15757 // CHECK27-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
15758 // CHECK27-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
15759 // CHECK27-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15760 // CHECK27-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
15761 // CHECK27-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
15762 // CHECK27-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
15763 // CHECK27-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
15764 // CHECK27-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
15765 // CHECK27-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
15766 // CHECK27-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
15767 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15768 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
15769 // CHECK27-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
15770 // CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15771 // CHECK27-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
15772 // CHECK27-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15773 // CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
15774 // CHECK27-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
15775 // CHECK27-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
15776 // CHECK27: simd.if.then:
15777 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15778 // CHECK27-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
15779 // CHECK27-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
15780 // CHECK27-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
15781 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15782 // CHECK27: omp.inner.for.cond:
15783 // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
15784 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
15785 // CHECK27-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
15786 // CHECK27-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15787 // CHECK27: omp.inner.for.body:
15788 // CHECK27-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
15789 // CHECK27-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
15790 // CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
15791 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
15792 // CHECK27-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
15793 // CHECK27-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
15794 // CHECK27-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !13
15795 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15796 // CHECK27: omp.body.continue:
15797 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15798 // CHECK27: omp.inner.for.inc:
15799 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
15800 // CHECK27-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
15801 // CHECK27-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
15802 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
15803 // CHECK27: omp.inner.for.end:
15804 // CHECK27-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15805 // CHECK27-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
15806 // CHECK27-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
15807 // CHECK27-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
15808 // CHECK27-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
15809 // CHECK27-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
15810 // CHECK27-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
15811 // CHECK27-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
15812 // CHECK27-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
15813 // CHECK27-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
15814 // CHECK27-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
15815 // CHECK27-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
15816 // CHECK27-NEXT: br label [[SIMD_IF_END]]
15817 // CHECK27: simd.if.end:
15818 // CHECK27-NEXT: ret void
15819 //
15820 //
15821 // CHECK27-LABEL: define {{[^@]+}}@_Z4fintv
15822 // CHECK27-SAME: () #[[ATTR0]] {
15823 // CHECK27-NEXT: entry:
15824 // CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
15825 // CHECK27-NEXT: ret i32 [[CALL]]
15826 //
15827 //
15828 // CHECK27-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
15829 // CHECK27-SAME: () #[[ATTR0]] comdat {
15830 // CHECK27-NEXT: entry:
15831 // CHECK27-NEXT: [[AA:%.*]] = alloca i16, align 2
15832 // CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4
15833 // CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15834 // CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15835 // CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15836 // CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4
15837 // CHECK27-NEXT: store i16 0, i16* [[AA]], align 2
15838 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15839 // CHECK27-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
15840 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15841 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15842 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15843 // CHECK27: omp.inner.for.cond:
15844 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
15845 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16
15846 // CHECK27-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
15847 // CHECK27-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15848 // CHECK27: omp.inner.for.body:
15849 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
15850 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
15851 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15852 // CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
15853 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15854 // CHECK27: omp.body.continue:
15855 // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15856 // CHECK27: omp.inner.for.inc:
15857 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
15858 // CHECK27-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
15859 // CHECK27-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
15860 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
15861 // CHECK27: omp.inner.for.end:
15862 // CHECK27-NEXT: store i32 100, i32* [[I]], align 4
15863 // CHECK27-NEXT: ret i32 0
15864 //
15865 //
15866 // CHECK28-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
15867 // CHECK28-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
15868 // CHECK28-NEXT: entry:
15869 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
15870 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
15871 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
15872 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
15873 // CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4
15874 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15875 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15876 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15877 // CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4
15878 // CHECK28-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
15879 // CHECK28-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
15880 // CHECK28-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
15881 // CHECK28-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
15882 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15883 // CHECK28-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
15884 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15885 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15886 // CHECK28-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
15887 // CHECK28-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
15888 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15889 // CHECK28: omp.inner.for.cond:
15890 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15891 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
15892 // CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
15893 // CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15894 // CHECK28: omp.inner.for.body:
15895 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15896 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
15897 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
15898 // CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
15899 // CHECK28-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
15900 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
15901 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
15902 // CHECK28-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
15903 // CHECK28-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
15904 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
15905 // CHECK28-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
15906 // CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
15907 // CHECK28-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
15908 // CHECK28-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
15909 // CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
15910 // CHECK28-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
15911 // CHECK28-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
15912 // CHECK28-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
15913 // CHECK28-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
15914 // CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
15915 // CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
15916 // CHECK28-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
15917 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15918 // CHECK28: omp.body.continue:
15919 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15920 // CHECK28: omp.inner.for.inc:
15921 // CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15922 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
15923 // CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15924 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
15925 // CHECK28: omp.inner.for.end:
15926 // CHECK28-NEXT: store i32 32000001, i32* [[I]], align 4
15927 // CHECK28-NEXT: ret void
15928 //
15929 //
15930 // CHECK28-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
15931 // CHECK28-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
15932 // CHECK28-NEXT: entry:
15933 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
15934 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
15935 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
15936 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
15937 // CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4
15938 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
15939 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
15940 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
15941 // CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4
15942 // CHECK28-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
15943 // CHECK28-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
15944 // CHECK28-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
15945 // CHECK28-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
15946 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
15947 // CHECK28-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
15948 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15949 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15950 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
15951 // CHECK28: omp.inner.for.cond:
15952 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15953 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15954 // CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
15955 // CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15956 // CHECK28: omp.inner.for.body:
15957 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15958 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
15959 // CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
15960 // CHECK28-NEXT: store i32 [[SUB]], i32* [[I]], align 4
15961 // CHECK28-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4
15962 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
15963 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
15964 // CHECK28-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
15965 // CHECK28-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
15966 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
15967 // CHECK28-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
15968 // CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
15969 // CHECK28-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
15970 // CHECK28-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
15971 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
15972 // CHECK28-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
15973 // CHECK28-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
15974 // CHECK28-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
15975 // CHECK28-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4
15976 // CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
15977 // CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
15978 // CHECK28-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
15979 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
15980 // CHECK28: omp.body.continue:
15981 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
15982 // CHECK28: omp.inner.for.inc:
15983 // CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15984 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
15985 // CHECK28-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
15986 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
15987 // CHECK28: omp.inner.for.end:
15988 // CHECK28-NEXT: store i32 32, i32* [[I]], align 4
15989 // CHECK28-NEXT: ret void
15990 //
15991 //
15992 // CHECK28-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
15993 // CHECK28-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
15994 // CHECK28-NEXT: entry:
15995 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
15996 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
15997 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
15998 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
15999 // CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4
16000 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16001 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16002 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16003 // CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4
16004 // CHECK28-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
16005 // CHECK28-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
16006 // CHECK28-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
16007 // CHECK28-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
16008 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16009 // CHECK28-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
16010 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16011 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16012 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16013 // CHECK28: omp.inner.for.cond:
16014 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16015 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
16016 // CHECK28-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
16017 // CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16018 // CHECK28: omp.inner.for.body:
16019 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16020 // CHECK28-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
16021 // CHECK28-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
16022 // CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
16023 // CHECK28-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !10
16024 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16025 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
16026 // CHECK28-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
16027 // CHECK28-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !10
16028 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16029 // CHECK28-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
16030 // CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !10
16031 // CHECK28-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
16032 // CHECK28-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !10
16033 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16034 // CHECK28-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
16035 // CHECK28-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !10
16036 // CHECK28-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
16037 // CHECK28-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !10
16038 // CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16039 // CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
16040 // CHECK28-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
16041 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16042 // CHECK28: omp.body.continue:
16043 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16044 // CHECK28: omp.inner.for.inc:
16045 // CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16046 // CHECK28-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
16047 // CHECK28-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16048 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
16049 // CHECK28: omp.inner.for.end:
16050 // CHECK28-NEXT: store i32 -2147483522, i32* [[I]], align 4
16051 // CHECK28-NEXT: ret void
16052 //
16053 //
16054 // CHECK28-LABEL: define {{[^@]+}}@_Z12test_precondv
16055 // CHECK28-SAME: () #[[ATTR0]] {
16056 // CHECK28-NEXT: entry:
16057 // CHECK28-NEXT: [[A:%.*]] = alloca i8, align 1
16058 // CHECK28-NEXT: [[I:%.*]] = alloca i8, align 1
16059 // CHECK28-NEXT: [[TMP:%.*]] = alloca i8, align 1
16060 // CHECK28-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
16061 // CHECK28-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
16062 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16063 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16064 // CHECK28-NEXT: [[I4:%.*]] = alloca i8, align 1
16065 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16066 // CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
16067 // CHECK28-NEXT: [[I6:%.*]] = alloca i8, align 1
16068 // CHECK28-NEXT: [[I7:%.*]] = alloca i8, align 1
16069 // CHECK28-NEXT: store i8 0, i8* [[A]], align 1
16070 // CHECK28-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
16071 // CHECK28-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
16072 // CHECK28-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16073 // CHECK28-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
16074 // CHECK28-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
16075 // CHECK28-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
16076 // CHECK28-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
16077 // CHECK28-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
16078 // CHECK28-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
16079 // CHECK28-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
16080 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16081 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
16082 // CHECK28-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
16083 // CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16084 // CHECK28-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
16085 // CHECK28-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16086 // CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
16087 // CHECK28-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
16088 // CHECK28-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
16089 // CHECK28: simd.if.then:
16090 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16091 // CHECK28-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
16092 // CHECK28-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
16093 // CHECK28-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
16094 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16095 // CHECK28: omp.inner.for.cond:
16096 // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16097 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
16098 // CHECK28-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
16099 // CHECK28-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16100 // CHECK28: omp.inner.for.body:
16101 // CHECK28-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
16102 // CHECK28-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
16103 // CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16104 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
16105 // CHECK28-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
16106 // CHECK28-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
16107 // CHECK28-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !13
16108 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16109 // CHECK28: omp.body.continue:
16110 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16111 // CHECK28: omp.inner.for.inc:
16112 // CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16113 // CHECK28-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
16114 // CHECK28-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16115 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
16116 // CHECK28: omp.inner.for.end:
16117 // CHECK28-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16118 // CHECK28-NEXT: [[CONV13:%.*]] = sext i8 [[TMP12]] to i32
16119 // CHECK28-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16120 // CHECK28-NEXT: [[CONV14:%.*]] = sext i8 [[TMP13]] to i32
16121 // CHECK28-NEXT: [[SUB15:%.*]] = sub i32 10, [[CONV14]]
16122 // CHECK28-NEXT: [[SUB16:%.*]] = sub i32 [[SUB15]], 1
16123 // CHECK28-NEXT: [[ADD17:%.*]] = add i32 [[SUB16]], 1
16124 // CHECK28-NEXT: [[DIV18:%.*]] = udiv i32 [[ADD17]], 1
16125 // CHECK28-NEXT: [[MUL19:%.*]] = mul nsw i32 [[DIV18]], 1
16126 // CHECK28-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV13]], [[MUL19]]
16127 // CHECK28-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
16128 // CHECK28-NEXT: store i8 [[CONV21]], i8* [[I]], align 1
16129 // CHECK28-NEXT: br label [[SIMD_IF_END]]
16130 // CHECK28: simd.if.end:
16131 // CHECK28-NEXT: ret void
16132 //
16133 //
16134 // CHECK28-LABEL: define {{[^@]+}}@_Z4fintv
16135 // CHECK28-SAME: () #[[ATTR0]] {
16136 // CHECK28-NEXT: entry:
16137 // CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
16138 // CHECK28-NEXT: ret i32 [[CALL]]
16139 //
16140 //
16141 // CHECK28-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
16142 // CHECK28-SAME: () #[[ATTR0]] comdat {
16143 // CHECK28-NEXT: entry:
16144 // CHECK28-NEXT: [[AA:%.*]] = alloca i16, align 2
16145 // CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4
16146 // CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16147 // CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16148 // CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16149 // CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4
16150 // CHECK28-NEXT: store i16 0, i16* [[AA]], align 2
16151 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16152 // CHECK28-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
16153 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16154 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16155 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16156 // CHECK28: omp.inner.for.cond:
16157 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
16158 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16
16159 // CHECK28-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
16160 // CHECK28-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16161 // CHECK28: omp.inner.for.body:
16162 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
16163 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
16164 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
16165 // CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
16166 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16167 // CHECK28: omp.body.continue:
16168 // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16169 // CHECK28: omp.inner.for.inc:
16170 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
16171 // CHECK28-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
16172 // CHECK28-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
16173 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
16174 // CHECK28: omp.inner.for.end:
16175 // CHECK28-NEXT: store i32 100, i32* [[I]], align 4
16176 // CHECK28-NEXT: ret i32 0
16177 //
16178 //
16179 // CHECK29-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
16180 // CHECK29-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
16181 // CHECK29-NEXT: entry:
16182 // CHECK29-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
16183 // CHECK29-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
16184 // CHECK29-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
16185 // CHECK29-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
16186 // CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4
16187 // CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16188 // CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16189 // CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16190 // CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4
16191 // CHECK29-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
16192 // CHECK29-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
16193 // CHECK29-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
16194 // CHECK29-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
16195 // CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16196 // CHECK29-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
16197 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16198 // CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16199 // CHECK29-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
16200 // CHECK29-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
16201 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16202 // CHECK29: omp.inner.for.cond:
16203 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16204 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
16205 // CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
16206 // CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16207 // CHECK29: omp.inner.for.body:
16208 // CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16209 // CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
16210 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
16211 // CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
16212 // CHECK29-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
16213 // CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
16214 // CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
16215 // CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
16216 // CHECK29-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
16217 // CHECK29-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
16218 // CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
16219 // CHECK29-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
16220 // CHECK29-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
16221 // CHECK29-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
16222 // CHECK29-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
16223 // CHECK29-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
16224 // CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
16225 // CHECK29-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
16226 // CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
16227 // CHECK29-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
16228 // CHECK29-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
16229 // CHECK29-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
16230 // CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
16231 // CHECK29-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
16232 // CHECK29-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
16233 // CHECK29-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
16234 // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16235 // CHECK29: omp.body.continue:
16236 // CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16237 // CHECK29: omp.inner.for.inc:
16238 // CHECK29-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16239 // CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
16240 // CHECK29-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16241 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
16242 // CHECK29: omp.inner.for.end:
16243 // CHECK29-NEXT: store i32 32000001, i32* [[I]], align 4
16244 // CHECK29-NEXT: ret void
16245 //
16246 //
16247 // CHECK29-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
16248 // CHECK29-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
16249 // CHECK29-NEXT: entry:
16250 // CHECK29-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
16251 // CHECK29-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
16252 // CHECK29-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
16253 // CHECK29-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
16254 // CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4
16255 // CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16256 // CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16257 // CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16258 // CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4
16259 // CHECK29-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
16260 // CHECK29-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
16261 // CHECK29-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
16262 // CHECK29-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
16263 // CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16264 // CHECK29-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
16265 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16266 // CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16267 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16268 // CHECK29: omp.inner.for.cond:
16269 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16270 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16271 // CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
16272 // CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16273 // CHECK29: omp.inner.for.body:
16274 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16275 // CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
16276 // CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
16277 // CHECK29-NEXT: store i32 [[SUB]], i32* [[I]], align 4
16278 // CHECK29-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !nontemporal !7
16279 // CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
16280 // CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
16281 // CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
16282 // CHECK29-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
16283 // CHECK29-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
16284 // CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
16285 // CHECK29-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
16286 // CHECK29-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
16287 // CHECK29-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
16288 // CHECK29-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
16289 // CHECK29-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
16290 // CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
16291 // CHECK29-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
16292 // CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
16293 // CHECK29-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
16294 // CHECK29-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
16295 // CHECK29-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !nontemporal !7
16296 // CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
16297 // CHECK29-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
16298 // CHECK29-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
16299 // CHECK29-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
16300 // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16301 // CHECK29: omp.body.continue:
16302 // CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16303 // CHECK29: omp.inner.for.inc:
16304 // CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16305 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
16306 // CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
16307 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
16308 // CHECK29: omp.inner.for.end:
16309 // CHECK29-NEXT: store i32 32, i32* [[I]], align 4
16310 // CHECK29-NEXT: ret void
16311 //
16312 //
16313 // CHECK29-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
16314 // CHECK29-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
16315 // CHECK29-NEXT: entry:
16316 // CHECK29-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
16317 // CHECK29-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
16318 // CHECK29-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
16319 // CHECK29-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
16320 // CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4
16321 // CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16322 // CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16323 // CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16324 // CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4
16325 // CHECK29-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
16326 // CHECK29-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
16327 // CHECK29-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
16328 // CHECK29-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
16329 // CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16330 // CHECK29-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
16331 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16332 // CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16333 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16334 // CHECK29: omp.inner.for.cond:
16335 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16336 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
16337 // CHECK29-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
16338 // CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16339 // CHECK29: omp.inner.for.body:
16340 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16341 // CHECK29-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
16342 // CHECK29-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
16343 // CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
16344 // CHECK29-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !10
16345 // CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16346 // CHECK29-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
16347 // CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
16348 // CHECK29-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
16349 // CHECK29-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !10
16350 // CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16351 // CHECK29-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
16352 // CHECK29-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
16353 // CHECK29-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
16354 // CHECK29-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
16355 // CHECK29-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !10
16356 // CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16357 // CHECK29-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
16358 // CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
16359 // CHECK29-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
16360 // CHECK29-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
16361 // CHECK29-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !10
16362 // CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16363 // CHECK29-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
16364 // CHECK29-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
16365 // CHECK29-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !10
16366 // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16367 // CHECK29: omp.body.continue:
16368 // CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16369 // CHECK29: omp.inner.for.inc:
16370 // CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16371 // CHECK29-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
16372 // CHECK29-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16373 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
16374 // CHECK29: omp.inner.for.end:
16375 // CHECK29-NEXT: store i32 -2147483522, i32* [[I]], align 4
16376 // CHECK29-NEXT: ret void
16377 //
16378 //
16379 // CHECK29-LABEL: define {{[^@]+}}@_Z12test_precondv
16380 // CHECK29-SAME: () #[[ATTR0]] {
16381 // CHECK29-NEXT: entry:
16382 // CHECK29-NEXT: [[A:%.*]] = alloca i8, align 1
16383 // CHECK29-NEXT: [[I:%.*]] = alloca i8, align 1
16384 // CHECK29-NEXT: [[TMP:%.*]] = alloca i8, align 1
16385 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
16386 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
16387 // CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16388 // CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16389 // CHECK29-NEXT: [[I4:%.*]] = alloca i8, align 1
16390 // CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16391 // CHECK29-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
16392 // CHECK29-NEXT: [[I6:%.*]] = alloca i8, align 1
16393 // CHECK29-NEXT: [[I7:%.*]] = alloca i8, align 1
16394 // CHECK29-NEXT: store i8 0, i8* [[A]], align 1
16395 // CHECK29-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
16396 // CHECK29-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
16397 // CHECK29-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16398 // CHECK29-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
16399 // CHECK29-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
16400 // CHECK29-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
16401 // CHECK29-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
16402 // CHECK29-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
16403 // CHECK29-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
16404 // CHECK29-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
16405 // CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16406 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
16407 // CHECK29-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
16408 // CHECK29-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16409 // CHECK29-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
16410 // CHECK29-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16411 // CHECK29-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
16412 // CHECK29-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
16413 // CHECK29-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
16414 // CHECK29: simd.if.then:
16415 // CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16416 // CHECK29-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
16417 // CHECK29-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
16418 // CHECK29-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
16419 // CHECK29-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
16420 // CHECK29-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
16421 // CHECK29-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16422 // CHECK29: omp_if.then:
16423 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16424 // CHECK29: omp.inner.for.cond:
16425 // CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16426 // CHECK29-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
16427 // CHECK29-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
16428 // CHECK29-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16429 // CHECK29: omp.inner.for.body:
16430 // CHECK29-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
16431 // CHECK29-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
16432 // CHECK29-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16433 // CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
16434 // CHECK29-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
16435 // CHECK29-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
16436 // CHECK29-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !7, !llvm.access.group !13
16437 // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16438 // CHECK29: omp.body.continue:
16439 // CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16440 // CHECK29: omp.inner.for.inc:
16441 // CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16442 // CHECK29-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
16443 // CHECK29-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16444 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
16445 // CHECK29: omp.inner.for.end:
16446 // CHECK29-NEXT: br label [[OMP_IF_END:%.*]]
16447 // CHECK29: omp_if.else:
16448 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
16449 // CHECK29: omp.inner.for.cond13:
16450 // CHECK29-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16451 // CHECK29-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16452 // CHECK29-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
16453 // CHECK29-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
16454 // CHECK29: omp.inner.for.body15:
16455 // CHECK29-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16456 // CHECK29-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
16457 // CHECK29-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16458 // CHECK29-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
16459 // CHECK29-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
16460 // CHECK29-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
16461 // CHECK29-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
16462 // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
16463 // CHECK29: omp.body.continue20:
16464 // CHECK29-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
16465 // CHECK29: omp.inner.for.inc21:
16466 // CHECK29-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16467 // CHECK29-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
16468 // CHECK29-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
16469 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]]
16470 // CHECK29: omp.inner.for.end23:
16471 // CHECK29-NEXT: br label [[OMP_IF_END]]
16472 // CHECK29: omp_if.end:
16473 // CHECK29-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16474 // CHECK29-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
16475 // CHECK29-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16476 // CHECK29-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
16477 // CHECK29-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
16478 // CHECK29-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
16479 // CHECK29-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
16480 // CHECK29-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
16481 // CHECK29-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
16482 // CHECK29-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
16483 // CHECK29-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
16484 // CHECK29-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
16485 // CHECK29-NEXT: br label [[SIMD_IF_END]]
16486 // CHECK29: simd.if.end:
16487 // CHECK29-NEXT: ret void
16488 //
16489 //
16490 // CHECK29-LABEL: define {{[^@]+}}@_Z4fintv
16491 // CHECK29-SAME: () #[[ATTR0]] {
16492 // CHECK29-NEXT: entry:
16493 // CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
16494 // CHECK29-NEXT: ret i32 [[CALL]]
16495 //
16496 //
16497 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
16498 // CHECK29-SAME: () #[[ATTR0]] comdat {
16499 // CHECK29-NEXT: entry:
16500 // CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2
16501 // CHECK29-NEXT: [[TMP:%.*]] = alloca i32, align 4
16502 // CHECK29-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16503 // CHECK29-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16504 // CHECK29-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16505 // CHECK29-NEXT: [[I:%.*]] = alloca i32, align 4
16506 // CHECK29-NEXT: store i16 0, i16* [[AA]], align 2
16507 // CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16508 // CHECK29-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
16509 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16510 // CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16511 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16512 // CHECK29: omp.inner.for.cond:
16513 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
16514 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
16515 // CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
16516 // CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16517 // CHECK29: omp.inner.for.body:
16518 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
16519 // CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
16520 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
16521 // CHECK29-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
16522 // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16523 // CHECK29: omp.body.continue:
16524 // CHECK29-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16525 // CHECK29: omp.inner.for.inc:
16526 // CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
16527 // CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
16528 // CHECK29-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
16529 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
16530 // CHECK29: omp.inner.for.end:
16531 // CHECK29-NEXT: store i32 100, i32* [[I]], align 4
16532 // CHECK29-NEXT: ret i32 0
16533 //
16534 //
16535 // CHECK30-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
16536 // CHECK30-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
16537 // CHECK30-NEXT: entry:
16538 // CHECK30-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
16539 // CHECK30-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
16540 // CHECK30-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
16541 // CHECK30-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
16542 // CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4
16543 // CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16544 // CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16545 // CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16546 // CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4
16547 // CHECK30-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
16548 // CHECK30-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
16549 // CHECK30-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
16550 // CHECK30-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
16551 // CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16552 // CHECK30-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
16553 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16554 // CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16555 // CHECK30-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 8
16556 // CHECK30-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i64 16) ]
16557 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16558 // CHECK30: omp.inner.for.cond:
16559 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16560 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
16561 // CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
16562 // CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16563 // CHECK30: omp.inner.for.body:
16564 // CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16565 // CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
16566 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
16567 // CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
16568 // CHECK30-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !2
16569 // CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
16570 // CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
16571 // CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM]]
16572 // CHECK30-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !2
16573 // CHECK30-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !2
16574 // CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
16575 // CHECK30-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP9]] to i64
16576 // CHECK30-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM1]]
16577 // CHECK30-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !2
16578 // CHECK30-NEXT: [[MUL3:%.*]] = fmul float [[TMP7]], [[TMP10]]
16579 // CHECK30-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !2
16580 // CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
16581 // CHECK30-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
16582 // CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM4]]
16583 // CHECK30-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !2
16584 // CHECK30-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP13]]
16585 // CHECK30-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !2
16586 // CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
16587 // CHECK30-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64
16588 // CHECK30-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM7]]
16589 // CHECK30-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !2
16590 // CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16591 // CHECK30: omp.body.continue:
16592 // CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16593 // CHECK30: omp.inner.for.inc:
16594 // CHECK30-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16595 // CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
16596 // CHECK30-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16597 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
16598 // CHECK30: omp.inner.for.end:
16599 // CHECK30-NEXT: store i32 32000001, i32* [[I]], align 4
16600 // CHECK30-NEXT: ret void
16601 //
16602 //
16603 // CHECK30-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
16604 // CHECK30-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
16605 // CHECK30-NEXT: entry:
16606 // CHECK30-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
16607 // CHECK30-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
16608 // CHECK30-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
16609 // CHECK30-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
16610 // CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4
16611 // CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16612 // CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16613 // CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16614 // CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4
16615 // CHECK30-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
16616 // CHECK30-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
16617 // CHECK30-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
16618 // CHECK30-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
16619 // CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16620 // CHECK30-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
16621 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16622 // CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16623 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16624 // CHECK30: omp.inner.for.cond:
16625 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16626 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16627 // CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
16628 // CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16629 // CHECK30: omp.inner.for.body:
16630 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16631 // CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
16632 // CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
16633 // CHECK30-NEXT: store i32 [[SUB]], i32* [[I]], align 4
16634 // CHECK30-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !nontemporal !7
16635 // CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
16636 // CHECK30-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
16637 // CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
16638 // CHECK30-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
16639 // CHECK30-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8
16640 // CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
16641 // CHECK30-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64
16642 // CHECK30-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
16643 // CHECK30-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4
16644 // CHECK30-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
16645 // CHECK30-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8
16646 // CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
16647 // CHECK30-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
16648 // CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
16649 // CHECK30-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4
16650 // CHECK30-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
16651 // CHECK30-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !nontemporal !7
16652 // CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
16653 // CHECK30-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64
16654 // CHECK30-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
16655 // CHECK30-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4
16656 // CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16657 // CHECK30: omp.body.continue:
16658 // CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16659 // CHECK30: omp.inner.for.inc:
16660 // CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16661 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
16662 // CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
16663 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
16664 // CHECK30: omp.inner.for.end:
16665 // CHECK30-NEXT: store i32 32, i32* [[I]], align 4
16666 // CHECK30-NEXT: ret void
16667 //
16668 //
16669 // CHECK30-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
16670 // CHECK30-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
16671 // CHECK30-NEXT: entry:
16672 // CHECK30-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
16673 // CHECK30-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
16674 // CHECK30-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8
16675 // CHECK30-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8
16676 // CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4
16677 // CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16678 // CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16679 // CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16680 // CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4
16681 // CHECK30-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
16682 // CHECK30-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
16683 // CHECK30-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
16684 // CHECK30-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
16685 // CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16686 // CHECK30-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
16687 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16688 // CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16689 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16690 // CHECK30: omp.inner.for.cond:
16691 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16692 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
16693 // CHECK30-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
16694 // CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16695 // CHECK30: omp.inner.for.body:
16696 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16697 // CHECK30-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
16698 // CHECK30-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
16699 // CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
16700 // CHECK30-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group !10
16701 // CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16702 // CHECK30-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64
16703 // CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM]]
16704 // CHECK30-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10
16705 // CHECK30-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 8, !llvm.access.group !10
16706 // CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16707 // CHECK30-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP8]] to i64
16708 // CHECK30-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM1]]
16709 // CHECK30-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !10
16710 // CHECK30-NEXT: [[MUL3:%.*]] = fmul float [[TMP6]], [[TMP9]]
16711 // CHECK30-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 8, !llvm.access.group !10
16712 // CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16713 // CHECK30-NEXT: [[IDXPROM4:%.*]] = zext i32 [[TMP11]] to i64
16714 // CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM4]]
16715 // CHECK30-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !llvm.access.group !10
16716 // CHECK30-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP12]]
16717 // CHECK30-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group !10
16718 // CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10
16719 // CHECK30-NEXT: [[IDXPROM7:%.*]] = zext i32 [[TMP14]] to i64
16720 // CHECK30-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM7]]
16721 // CHECK30-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4, !llvm.access.group !10
16722 // CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16723 // CHECK30: omp.body.continue:
16724 // CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16725 // CHECK30: omp.inner.for.inc:
16726 // CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16727 // CHECK30-NEXT: [[ADD9:%.*]] = add i32 [[TMP15]], 1
16728 // CHECK30-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
16729 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
16730 // CHECK30: omp.inner.for.end:
16731 // CHECK30-NEXT: store i32 -2147483522, i32* [[I]], align 4
16732 // CHECK30-NEXT: ret void
16733 //
16734 //
16735 // CHECK30-LABEL: define {{[^@]+}}@_Z12test_precondv
16736 // CHECK30-SAME: () #[[ATTR0]] {
16737 // CHECK30-NEXT: entry:
16738 // CHECK30-NEXT: [[A:%.*]] = alloca i8, align 1
16739 // CHECK30-NEXT: [[I:%.*]] = alloca i8, align 1
16740 // CHECK30-NEXT: [[TMP:%.*]] = alloca i8, align 1
16741 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
16742 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
16743 // CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16744 // CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16745 // CHECK30-NEXT: [[I4:%.*]] = alloca i8, align 1
16746 // CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16747 // CHECK30-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
16748 // CHECK30-NEXT: [[I6:%.*]] = alloca i8, align 1
16749 // CHECK30-NEXT: [[I7:%.*]] = alloca i8, align 1
16750 // CHECK30-NEXT: store i8 0, i8* [[A]], align 1
16751 // CHECK30-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
16752 // CHECK30-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
16753 // CHECK30-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16754 // CHECK30-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
16755 // CHECK30-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
16756 // CHECK30-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
16757 // CHECK30-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
16758 // CHECK30-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
16759 // CHECK30-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
16760 // CHECK30-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
16761 // CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16762 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
16763 // CHECK30-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
16764 // CHECK30-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16765 // CHECK30-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
16766 // CHECK30-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16767 // CHECK30-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
16768 // CHECK30-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
16769 // CHECK30-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
16770 // CHECK30: simd.if.then:
16771 // CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16772 // CHECK30-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
16773 // CHECK30-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
16774 // CHECK30-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
16775 // CHECK30-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
16776 // CHECK30-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
16777 // CHECK30-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16778 // CHECK30: omp_if.then:
16779 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16780 // CHECK30: omp.inner.for.cond:
16781 // CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16782 // CHECK30-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
16783 // CHECK30-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
16784 // CHECK30-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16785 // CHECK30: omp.inner.for.body:
16786 // CHECK30-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !13
16787 // CHECK30-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
16788 // CHECK30-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16789 // CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
16790 // CHECK30-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
16791 // CHECK30-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
16792 // CHECK30-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !7, !llvm.access.group !13
16793 // CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16794 // CHECK30: omp.body.continue:
16795 // CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16796 // CHECK30: omp.inner.for.inc:
16797 // CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16798 // CHECK30-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
16799 // CHECK30-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
16800 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
16801 // CHECK30: omp.inner.for.end:
16802 // CHECK30-NEXT: br label [[OMP_IF_END:%.*]]
16803 // CHECK30: omp_if.else:
16804 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
16805 // CHECK30: omp.inner.for.cond13:
16806 // CHECK30-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16807 // CHECK30-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16808 // CHECK30-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
16809 // CHECK30-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
16810 // CHECK30: omp.inner.for.body15:
16811 // CHECK30-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16812 // CHECK30-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
16813 // CHECK30-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16814 // CHECK30-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
16815 // CHECK30-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
16816 // CHECK30-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
16817 // CHECK30-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
16818 // CHECK30-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
16819 // CHECK30: omp.body.continue20:
16820 // CHECK30-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
16821 // CHECK30: omp.inner.for.inc21:
16822 // CHECK30-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16823 // CHECK30-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
16824 // CHECK30-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
16825 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP16:![0-9]+]]
16826 // CHECK30: omp.inner.for.end23:
16827 // CHECK30-NEXT: br label [[OMP_IF_END]]
16828 // CHECK30: omp_if.end:
16829 // CHECK30-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16830 // CHECK30-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
16831 // CHECK30-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16832 // CHECK30-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
16833 // CHECK30-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
16834 // CHECK30-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
16835 // CHECK30-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
16836 // CHECK30-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
16837 // CHECK30-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
16838 // CHECK30-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
16839 // CHECK30-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
16840 // CHECK30-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
16841 // CHECK30-NEXT: br label [[SIMD_IF_END]]
16842 // CHECK30: simd.if.end:
16843 // CHECK30-NEXT: ret void
16844 //
16845 //
16846 // CHECK30-LABEL: define {{[^@]+}}@_Z4fintv
16847 // CHECK30-SAME: () #[[ATTR0]] {
16848 // CHECK30-NEXT: entry:
16849 // CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v()
16850 // CHECK30-NEXT: ret i32 [[CALL]]
16851 //
16852 //
16853 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
16854 // CHECK30-SAME: () #[[ATTR0]] comdat {
16855 // CHECK30-NEXT: entry:
16856 // CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2
16857 // CHECK30-NEXT: [[TMP:%.*]] = alloca i32, align 4
16858 // CHECK30-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16859 // CHECK30-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16860 // CHECK30-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16861 // CHECK30-NEXT: [[I:%.*]] = alloca i32, align 4
16862 // CHECK30-NEXT: store i16 0, i16* [[AA]], align 2
16863 // CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16864 // CHECK30-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
16865 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16866 // CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16867 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16868 // CHECK30: omp.inner.for.cond:
16869 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
16870 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
16871 // CHECK30-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
16872 // CHECK30-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16873 // CHECK30: omp.inner.for.body:
16874 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
16875 // CHECK30-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
16876 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
16877 // CHECK30-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
16878 // CHECK30-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16879 // CHECK30: omp.body.continue:
16880 // CHECK30-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16881 // CHECK30: omp.inner.for.inc:
16882 // CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
16883 // CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
16884 // CHECK30-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
16885 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
16886 // CHECK30: omp.inner.for.end:
16887 // CHECK30-NEXT: store i32 100, i32* [[I]], align 4
16888 // CHECK30-NEXT: ret i32 0
16889 //
16890 //
16891 // CHECK31-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
16892 // CHECK31-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
16893 // CHECK31-NEXT: entry:
16894 // CHECK31-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
16895 // CHECK31-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
16896 // CHECK31-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
16897 // CHECK31-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
16898 // CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4
16899 // CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16900 // CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16901 // CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16902 // CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4
16903 // CHECK31-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
16904 // CHECK31-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
16905 // CHECK31-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
16906 // CHECK31-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
16907 // CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16908 // CHECK31-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
16909 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16910 // CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16911 // CHECK31-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
16912 // CHECK31-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
16913 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16914 // CHECK31: omp.inner.for.cond:
16915 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16916 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
16917 // CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
16918 // CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16919 // CHECK31: omp.inner.for.body:
16920 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16921 // CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
16922 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
16923 // CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
16924 // CHECK31-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
16925 // CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
16926 // CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
16927 // CHECK31-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
16928 // CHECK31-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
16929 // CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
16930 // CHECK31-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
16931 // CHECK31-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
16932 // CHECK31-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
16933 // CHECK31-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
16934 // CHECK31-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
16935 // CHECK31-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
16936 // CHECK31-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
16937 // CHECK31-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
16938 // CHECK31-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
16939 // CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
16940 // CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
16941 // CHECK31-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
16942 // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
16943 // CHECK31: omp.body.continue:
16944 // CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
16945 // CHECK31: omp.inner.for.inc:
16946 // CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16947 // CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
16948 // CHECK31-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
16949 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
16950 // CHECK31: omp.inner.for.end:
16951 // CHECK31-NEXT: store i32 32000001, i32* [[I]], align 4
16952 // CHECK31-NEXT: ret void
16953 //
16954 //
16955 // CHECK31-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
16956 // CHECK31-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
16957 // CHECK31-NEXT: entry:
16958 // CHECK31-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
16959 // CHECK31-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
16960 // CHECK31-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
16961 // CHECK31-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
16962 // CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4
16963 // CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
16964 // CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
16965 // CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
16966 // CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4
16967 // CHECK31-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
16968 // CHECK31-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
16969 // CHECK31-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
16970 // CHECK31-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
16971 // CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
16972 // CHECK31-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
16973 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16974 // CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16975 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
16976 // CHECK31: omp.inner.for.cond:
16977 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16978 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16979 // CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
16980 // CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16981 // CHECK31: omp.inner.for.body:
16982 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16983 // CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
16984 // CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
16985 // CHECK31-NEXT: store i32 [[SUB]], i32* [[I]], align 4
16986 // CHECK31-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !nontemporal !8
16987 // CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
16988 // CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
16989 // CHECK31-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
16990 // CHECK31-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
16991 // CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
16992 // CHECK31-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
16993 // CHECK31-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
16994 // CHECK31-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
16995 // CHECK31-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
16996 // CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
16997 // CHECK31-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
16998 // CHECK31-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
16999 // CHECK31-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
17000 // CHECK31-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !nontemporal !8
17001 // CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
17002 // CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
17003 // CHECK31-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
17004 // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
17005 // CHECK31: omp.body.continue:
17006 // CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
17007 // CHECK31: omp.inner.for.inc:
17008 // CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17009 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
17010 // CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
17011 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
17012 // CHECK31: omp.inner.for.end:
17013 // CHECK31-NEXT: store i32 32, i32* [[I]], align 4
17014 // CHECK31-NEXT: ret void
17015 //
17016 //
17017 // CHECK31-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
17018 // CHECK31-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
17019 // CHECK31-NEXT: entry:
17020 // CHECK31-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
17021 // CHECK31-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
17022 // CHECK31-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
17023 // CHECK31-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
17024 // CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4
17025 // CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
17026 // CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
17027 // CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
17028 // CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4
17029 // CHECK31-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
17030 // CHECK31-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
17031 // CHECK31-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
17032 // CHECK31-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
17033 // CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
17034 // CHECK31-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
17035 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17036 // CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
17037 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
17038 // CHECK31: omp.inner.for.cond:
17039 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17040 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
17041 // CHECK31-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
17042 // CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17043 // CHECK31: omp.inner.for.body:
17044 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17045 // CHECK31-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
17046 // CHECK31-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
17047 // CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
17048 // CHECK31-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !11
17049 // CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
17050 // CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
17051 // CHECK31-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11
17052 // CHECK31-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !11
17053 // CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
17054 // CHECK31-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
17055 // CHECK31-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !11
17056 // CHECK31-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
17057 // CHECK31-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !11
17058 // CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
17059 // CHECK31-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
17060 // CHECK31-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11
17061 // CHECK31-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
17062 // CHECK31-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !11
17063 // CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
17064 // CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
17065 // CHECK31-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !11
17066 // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
17067 // CHECK31: omp.body.continue:
17068 // CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
17069 // CHECK31: omp.inner.for.inc:
17070 // CHECK31-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17071 // CHECK31-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
17072 // CHECK31-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17073 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
17074 // CHECK31: omp.inner.for.end:
17075 // CHECK31-NEXT: store i32 -2147483522, i32* [[I]], align 4
17076 // CHECK31-NEXT: ret void
17077 //
17078 //
17079 // CHECK31-LABEL: define {{[^@]+}}@_Z12test_precondv
17080 // CHECK31-SAME: () #[[ATTR0]] {
17081 // CHECK31-NEXT: entry:
17082 // CHECK31-NEXT: [[A:%.*]] = alloca i8, align 1
17083 // CHECK31-NEXT: [[I:%.*]] = alloca i8, align 1
17084 // CHECK31-NEXT: [[TMP:%.*]] = alloca i8, align 1
17085 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
17086 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
17087 // CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
17088 // CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
17089 // CHECK31-NEXT: [[I4:%.*]] = alloca i8, align 1
17090 // CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
17091 // CHECK31-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
17092 // CHECK31-NEXT: [[I6:%.*]] = alloca i8, align 1
17093 // CHECK31-NEXT: [[I7:%.*]] = alloca i8, align 1
17094 // CHECK31-NEXT: store i8 0, i8* [[A]], align 1
17095 // CHECK31-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
17096 // CHECK31-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
17097 // CHECK31-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17098 // CHECK31-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
17099 // CHECK31-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
17100 // CHECK31-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
17101 // CHECK31-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
17102 // CHECK31-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
17103 // CHECK31-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
17104 // CHECK31-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
17105 // CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
17106 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
17107 // CHECK31-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
17108 // CHECK31-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17109 // CHECK31-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
17110 // CHECK31-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17111 // CHECK31-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
17112 // CHECK31-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
17113 // CHECK31-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
17114 // CHECK31: simd.if.then:
17115 // CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17116 // CHECK31-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
17117 // CHECK31-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
17118 // CHECK31-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
17119 // CHECK31-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
17120 // CHECK31-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
17121 // CHECK31-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17122 // CHECK31: omp_if.then:
17123 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
17124 // CHECK31: omp.inner.for.cond:
17125 // CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
17126 // CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14
17127 // CHECK31-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
17128 // CHECK31-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17129 // CHECK31: omp.inner.for.body:
17130 // CHECK31-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !14
17131 // CHECK31-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
17132 // CHECK31-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
17133 // CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
17134 // CHECK31-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
17135 // CHECK31-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
17136 // CHECK31-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !8, !llvm.access.group !14
17137 // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
17138 // CHECK31: omp.body.continue:
17139 // CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
17140 // CHECK31: omp.inner.for.inc:
17141 // CHECK31-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
17142 // CHECK31-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
17143 // CHECK31-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
17144 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
17145 // CHECK31: omp.inner.for.end:
17146 // CHECK31-NEXT: br label [[OMP_IF_END:%.*]]
17147 // CHECK31: omp_if.else:
17148 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
17149 // CHECK31: omp.inner.for.cond13:
17150 // CHECK31-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17151 // CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17152 // CHECK31-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
17153 // CHECK31-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
17154 // CHECK31: omp.inner.for.body15:
17155 // CHECK31-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17156 // CHECK31-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
17157 // CHECK31-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17158 // CHECK31-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
17159 // CHECK31-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
17160 // CHECK31-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
17161 // CHECK31-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
17162 // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
17163 // CHECK31: omp.body.continue20:
17164 // CHECK31-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
17165 // CHECK31: omp.inner.for.inc21:
17166 // CHECK31-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17167 // CHECK31-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
17168 // CHECK31-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
17169 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]]
17170 // CHECK31: omp.inner.for.end23:
17171 // CHECK31-NEXT: br label [[OMP_IF_END]]
17172 // CHECK31: omp_if.end:
17173 // CHECK31-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17174 // CHECK31-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
17175 // CHECK31-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17176 // CHECK31-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
17177 // CHECK31-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
17178 // CHECK31-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
17179 // CHECK31-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
17180 // CHECK31-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
17181 // CHECK31-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
17182 // CHECK31-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
17183 // CHECK31-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
17184 // CHECK31-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
17185 // CHECK31-NEXT: br label [[SIMD_IF_END]]
17186 // CHECK31: simd.if.end:
17187 // CHECK31-NEXT: ret void
17188 //
17189 //
17190 // CHECK31-LABEL: define {{[^@]+}}@_Z4fintv
17191 // CHECK31-SAME: () #[[ATTR0]] {
17192 // CHECK31-NEXT: entry:
17193 // CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
17194 // CHECK31-NEXT: ret i32 [[CALL]]
17195 //
17196 //
17197 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
17198 // CHECK31-SAME: () #[[ATTR0]] comdat {
17199 // CHECK31-NEXT: entry:
17200 // CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2
17201 // CHECK31-NEXT: [[TMP:%.*]] = alloca i32, align 4
17202 // CHECK31-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
17203 // CHECK31-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
17204 // CHECK31-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
17205 // CHECK31-NEXT: [[I:%.*]] = alloca i32, align 4
17206 // CHECK31-NEXT: store i16 0, i16* [[AA]], align 2
17207 // CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
17208 // CHECK31-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
17209 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17210 // CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
17211 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
17212 // CHECK31: omp.inner.for.cond:
17213 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17214 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
17215 // CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
17216 // CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17217 // CHECK31: omp.inner.for.body:
17218 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17219 // CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
17220 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17221 // CHECK31-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
17222 // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
17223 // CHECK31: omp.body.continue:
17224 // CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
17225 // CHECK31: omp.inner.for.inc:
17226 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17227 // CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
17228 // CHECK31-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17229 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
17230 // CHECK31: omp.inner.for.end:
17231 // CHECK31-NEXT: store i32 100, i32* [[I]], align 4
17232 // CHECK31-NEXT: ret i32 0
17233 //
17234 //
17235 // CHECK32-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
17236 // CHECK32-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] {
17237 // CHECK32-NEXT: entry:
17238 // CHECK32-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
17239 // CHECK32-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
17240 // CHECK32-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
17241 // CHECK32-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
17242 // CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4
17243 // CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
17244 // CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
17245 // CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
17246 // CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4
17247 // CHECK32-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
17248 // CHECK32-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
17249 // CHECK32-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
17250 // CHECK32-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
17251 // CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
17252 // CHECK32-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
17253 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17254 // CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
17255 // CHECK32-NEXT: [[TMP1:%.*]] = load float*, float** [[A_ADDR]], align 4
17256 // CHECK32-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[TMP1]], i32 16) ]
17257 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
17258 // CHECK32: omp.inner.for.cond:
17259 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
17260 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
17261 // CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
17262 // CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17263 // CHECK32: omp.inner.for.body:
17264 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
17265 // CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
17266 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
17267 // CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
17268 // CHECK32-NEXT: [[TMP5:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !3
17269 // CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
17270 // CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP5]], i32 [[TMP6]]
17271 // CHECK32-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
17272 // CHECK32-NEXT: [[TMP8:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !3
17273 // CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
17274 // CHECK32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP8]], i32 [[TMP9]]
17275 // CHECK32-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !3
17276 // CHECK32-NEXT: [[MUL2:%.*]] = fmul float [[TMP7]], [[TMP10]]
17277 // CHECK32-NEXT: [[TMP11:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !3
17278 // CHECK32-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
17279 // CHECK32-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP11]], i32 [[TMP12]]
17280 // CHECK32-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !3
17281 // CHECK32-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP13]]
17282 // CHECK32-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !3
17283 // CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
17284 // CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP14]], i32 [[TMP15]]
17285 // CHECK32-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !3
17286 // CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
17287 // CHECK32: omp.body.continue:
17288 // CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
17289 // CHECK32: omp.inner.for.inc:
17290 // CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
17291 // CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
17292 // CHECK32-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
17293 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
17294 // CHECK32: omp.inner.for.end:
17295 // CHECK32-NEXT: store i32 32000001, i32* [[I]], align 4
17296 // CHECK32-NEXT: ret void
17297 //
17298 //
17299 // CHECK32-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
17300 // CHECK32-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
17301 // CHECK32-NEXT: entry:
17302 // CHECK32-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
17303 // CHECK32-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
17304 // CHECK32-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
17305 // CHECK32-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
17306 // CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4
17307 // CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
17308 // CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
17309 // CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
17310 // CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4
17311 // CHECK32-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
17312 // CHECK32-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
17313 // CHECK32-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
17314 // CHECK32-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
17315 // CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
17316 // CHECK32-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4
17317 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17318 // CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
17319 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
17320 // CHECK32: omp.inner.for.cond:
17321 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17322 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17323 // CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
17324 // CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17325 // CHECK32: omp.inner.for.body:
17326 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17327 // CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 7
17328 // CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
17329 // CHECK32-NEXT: store i32 [[SUB]], i32* [[I]], align 4
17330 // CHECK32-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !nontemporal !8
17331 // CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
17332 // CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
17333 // CHECK32-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4
17334 // CHECK32-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4
17335 // CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
17336 // CHECK32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
17337 // CHECK32-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4
17338 // CHECK32-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
17339 // CHECK32-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4
17340 // CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
17341 // CHECK32-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
17342 // CHECK32-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4
17343 // CHECK32-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
17344 // CHECK32-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !nontemporal !8
17345 // CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4
17346 // CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
17347 // CHECK32-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4
17348 // CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
17349 // CHECK32: omp.body.continue:
17350 // CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
17351 // CHECK32: omp.inner.for.inc:
17352 // CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17353 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1
17354 // CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
17355 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
17356 // CHECK32: omp.inner.for.end:
17357 // CHECK32-NEXT: store i32 32, i32* [[I]], align 4
17358 // CHECK32-NEXT: ret void
17359 //
17360 //
17361 // CHECK32-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
17362 // CHECK32-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] {
17363 // CHECK32-NEXT: entry:
17364 // CHECK32-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4
17365 // CHECK32-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4
17366 // CHECK32-NEXT: [[C_ADDR:%.*]] = alloca float*, align 4
17367 // CHECK32-NEXT: [[D_ADDR:%.*]] = alloca float*, align 4
17368 // CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4
17369 // CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
17370 // CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
17371 // CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
17372 // CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4
17373 // CHECK32-NEXT: store float* [[A]], float** [[A_ADDR]], align 4
17374 // CHECK32-NEXT: store float* [[B]], float** [[B_ADDR]], align 4
17375 // CHECK32-NEXT: store float* [[C]], float** [[C_ADDR]], align 4
17376 // CHECK32-NEXT: store float* [[D]], float** [[D_ADDR]], align 4
17377 // CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
17378 // CHECK32-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4
17379 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17380 // CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
17381 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
17382 // CHECK32: omp.inner.for.cond:
17383 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17384 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
17385 // CHECK32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP1]], [[TMP2]]
17386 // CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17387 // CHECK32: omp.inner.for.body:
17388 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17389 // CHECK32-NEXT: [[MUL:%.*]] = mul i32 [[TMP3]], 127
17390 // CHECK32-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
17391 // CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
17392 // CHECK32-NEXT: [[TMP4:%.*]] = load float*, float** [[B_ADDR]], align 4, !llvm.access.group !11
17393 // CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
17394 // CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP4]], i32 [[TMP5]]
17395 // CHECK32-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11
17396 // CHECK32-NEXT: [[TMP7:%.*]] = load float*, float** [[C_ADDR]], align 4, !llvm.access.group !11
17397 // CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
17398 // CHECK32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP7]], i32 [[TMP8]]
17399 // CHECK32-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !llvm.access.group !11
17400 // CHECK32-NEXT: [[MUL2:%.*]] = fmul float [[TMP6]], [[TMP9]]
17401 // CHECK32-NEXT: [[TMP10:%.*]] = load float*, float** [[D_ADDR]], align 4, !llvm.access.group !11
17402 // CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
17403 // CHECK32-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP10]], i32 [[TMP11]]
17404 // CHECK32-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !llvm.access.group !11
17405 // CHECK32-NEXT: [[MUL4:%.*]] = fmul float [[MUL2]], [[TMP12]]
17406 // CHECK32-NEXT: [[TMP13:%.*]] = load float*, float** [[A_ADDR]], align 4, !llvm.access.group !11
17407 // CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11
17408 // CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP13]], i32 [[TMP14]]
17409 // CHECK32-NEXT: store float [[MUL4]], float* [[ARRAYIDX5]], align 4, !llvm.access.group !11
17410 // CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
17411 // CHECK32: omp.body.continue:
17412 // CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
17413 // CHECK32: omp.inner.for.inc:
17414 // CHECK32-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17415 // CHECK32-NEXT: [[ADD6:%.*]] = add i32 [[TMP15]], 1
17416 // CHECK32-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
17417 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
17418 // CHECK32: omp.inner.for.end:
17419 // CHECK32-NEXT: store i32 -2147483522, i32* [[I]], align 4
17420 // CHECK32-NEXT: ret void
17421 //
17422 //
17423 // CHECK32-LABEL: define {{[^@]+}}@_Z12test_precondv
17424 // CHECK32-SAME: () #[[ATTR0]] {
17425 // CHECK32-NEXT: entry:
17426 // CHECK32-NEXT: [[A:%.*]] = alloca i8, align 1
17427 // CHECK32-NEXT: [[I:%.*]] = alloca i8, align 1
17428 // CHECK32-NEXT: [[TMP:%.*]] = alloca i8, align 1
17429 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
17430 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
17431 // CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
17432 // CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
17433 // CHECK32-NEXT: [[I4:%.*]] = alloca i8, align 1
17434 // CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
17435 // CHECK32-NEXT: [[DOTLINEAR_START:%.*]] = alloca i8, align 1
17436 // CHECK32-NEXT: [[I6:%.*]] = alloca i8, align 1
17437 // CHECK32-NEXT: [[I7:%.*]] = alloca i8, align 1
17438 // CHECK32-NEXT: store i8 0, i8* [[A]], align 1
17439 // CHECK32-NEXT: [[TMP0:%.*]] = load i8, i8* [[A]], align 1
17440 // CHECK32-NEXT: store i8 [[TMP0]], i8* [[DOTCAPTURE_EXPR_]], align 1
17441 // CHECK32-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17442 // CHECK32-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
17443 // CHECK32-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]]
17444 // CHECK32-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1
17445 // CHECK32-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1
17446 // CHECK32-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
17447 // CHECK32-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
17448 // CHECK32-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_1]], align 4
17449 // CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
17450 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
17451 // CHECK32-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_UB]], align 4
17452 // CHECK32-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17453 // CHECK32-NEXT: store i8 [[TMP3]], i8* [[I4]], align 1
17454 // CHECK32-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17455 // CHECK32-NEXT: [[CONV5:%.*]] = sext i8 [[TMP4]] to i32
17456 // CHECK32-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV5]], 10
17457 // CHECK32-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
17458 // CHECK32: simd.if.then:
17459 // CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17460 // CHECK32-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
17461 // CHECK32-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1
17462 // CHECK32-NEXT: store i8 [[TMP6]], i8* [[DOTLINEAR_START]], align 1
17463 // CHECK32-NEXT: [[TMP7:%.*]] = load i8, i8* [[A]], align 1
17464 // CHECK32-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP7]], 0
17465 // CHECK32-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17466 // CHECK32: omp_if.then:
17467 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
17468 // CHECK32: omp.inner.for.cond:
17469 // CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
17470 // CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14
17471 // CHECK32-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
17472 // CHECK32-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17473 // CHECK32: omp.inner.for.body:
17474 // CHECK32-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !14
17475 // CHECK32-NEXT: [[CONV9:%.*]] = sext i8 [[TMP10]] to i32
17476 // CHECK32-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
17477 // CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
17478 // CHECK32-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
17479 // CHECK32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
17480 // CHECK32-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !8, !llvm.access.group !14
17481 // CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
17482 // CHECK32: omp.body.continue:
17483 // CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
17484 // CHECK32: omp.inner.for.inc:
17485 // CHECK32-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
17486 // CHECK32-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP12]], 1
17487 // CHECK32-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
17488 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
17489 // CHECK32: omp.inner.for.end:
17490 // CHECK32-NEXT: br label [[OMP_IF_END:%.*]]
17491 // CHECK32: omp_if.else:
17492 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
17493 // CHECK32: omp.inner.for.cond13:
17494 // CHECK32-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17495 // CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17496 // CHECK32-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
17497 // CHECK32-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.*]], label [[OMP_INNER_FOR_END23:%.*]]
17498 // CHECK32: omp.inner.for.body15:
17499 // CHECK32-NEXT: [[TMP15:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17500 // CHECK32-NEXT: [[CONV16:%.*]] = sext i8 [[TMP15]] to i32
17501 // CHECK32-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17502 // CHECK32-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP16]], 1
17503 // CHECK32-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
17504 // CHECK32-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
17505 // CHECK32-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
17506 // CHECK32-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
17507 // CHECK32: omp.body.continue20:
17508 // CHECK32-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
17509 // CHECK32: omp.inner.for.inc21:
17510 // CHECK32-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17511 // CHECK32-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP17]], 1
17512 // CHECK32-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
17513 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP17:![0-9]+]]
17514 // CHECK32: omp.inner.for.end23:
17515 // CHECK32-NEXT: br label [[OMP_IF_END]]
17516 // CHECK32: omp_if.end:
17517 // CHECK32-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17518 // CHECK32-NEXT: [[CONV24:%.*]] = sext i8 [[TMP18]] to i32
17519 // CHECK32-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17520 // CHECK32-NEXT: [[CONV25:%.*]] = sext i8 [[TMP19]] to i32
17521 // CHECK32-NEXT: [[SUB26:%.*]] = sub i32 10, [[CONV25]]
17522 // CHECK32-NEXT: [[SUB27:%.*]] = sub i32 [[SUB26]], 1
17523 // CHECK32-NEXT: [[ADD28:%.*]] = add i32 [[SUB27]], 1
17524 // CHECK32-NEXT: [[DIV29:%.*]] = udiv i32 [[ADD28]], 1
17525 // CHECK32-NEXT: [[MUL30:%.*]] = mul nsw i32 [[DIV29]], 1
17526 // CHECK32-NEXT: [[ADD31:%.*]] = add nsw i32 [[CONV24]], [[MUL30]]
17527 // CHECK32-NEXT: [[CONV32:%.*]] = trunc i32 [[ADD31]] to i8
17528 // CHECK32-NEXT: store i8 [[CONV32]], i8* [[I]], align 1
17529 // CHECK32-NEXT: br label [[SIMD_IF_END]]
17530 // CHECK32: simd.if.end:
17531 // CHECK32-NEXT: ret void
17532 //
17533 //
17534 // CHECK32-LABEL: define {{[^@]+}}@_Z4fintv
17535 // CHECK32-SAME: () #[[ATTR0]] {
17536 // CHECK32-NEXT: entry:
17537 // CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v()
17538 // CHECK32-NEXT: ret i32 [[CALL]]
17539 //
17540 //
17541 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v
17542 // CHECK32-SAME: () #[[ATTR0]] comdat {
17543 // CHECK32-NEXT: entry:
17544 // CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2
17545 // CHECK32-NEXT: [[TMP:%.*]] = alloca i32, align 4
17546 // CHECK32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
17547 // CHECK32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
17548 // CHECK32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
17549 // CHECK32-NEXT: [[I:%.*]] = alloca i32, align 4
17550 // CHECK32-NEXT: store i16 0, i16* [[AA]], align 2
17551 // CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
17552 // CHECK32-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4
17553 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17554 // CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
17555 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
17556 // CHECK32: omp.inner.for.cond:
17557 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17558 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
17559 // CHECK32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
17560 // CHECK32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17561 // CHECK32: omp.inner.for.body:
17562 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17563 // CHECK32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
17564 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17565 // CHECK32-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
17566 // CHECK32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
17567 // CHECK32: omp.body.continue:
17568 // CHECK32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
17569 // CHECK32: omp.inner.for.inc:
17570 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17571 // CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
17572 // CHECK32-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17573 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
17574 // CHECK32: omp.inner.for.end:
17575 // CHECK32-NEXT: store i32 100, i32* [[I]], align 4
17576 // CHECK32-NEXT: ret i32 0
17577 //
17578