1//=- AArch64SMEInstrInfo.td - AArch64 SME Instructions -*- tablegen -*-----=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// AArch64 Scalable Matrix Extension (SME) Instruction definitions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Add vector elements horizontally or vertically to ZA tile. 15//===----------------------------------------------------------------------===// 16 17let Predicates = [HasSME] in { 18def ADDHA_MPPZ_S : sme_add_vector_to_tile_u32<0b0, "addha">; 19def ADDVA_MPPZ_S : sme_add_vector_to_tile_u32<0b1, "addva">; 20} 21 22let Predicates = [HasSMEI64] in { 23def ADDHA_MPPZ_D : sme_add_vector_to_tile_u64<0b0, "addha">; 24def ADDVA_MPPZ_D : sme_add_vector_to_tile_u64<0b1, "addva">; 25} 26 27let Predicates = [HasSME] in { 28//===----------------------------------------------------------------------===// 29// Outer products 30//===----------------------------------------------------------------------===// 31 32defm BFMOPA_MPPZZ : sme_bf16_outer_product<0b0, "bfmopa">; 33defm BFMOPS_MPPZZ : sme_bf16_outer_product<0b1, "bfmops">; 34 35def FMOPA_MPPZZ_S : sme_outer_product_fp32<0b0, "fmopa">; 36def FMOPS_MPPZZ_S : sme_outer_product_fp32<0b1, "fmops">; 37} 38 39let Predicates = [HasSMEF64] in { 40def FMOPA_MPPZZ_D : sme_outer_product_fp64<0b0, "fmopa">; 41def FMOPS_MPPZZ_D : sme_outer_product_fp64<0b1, "fmops">; 42} 43 44let Predicates = [HasSME] in { 45defm FMOPAL_MPPZZ : sme_f16_outer_product<0b0, "fmopa">; 46defm FMOPSL_MPPZZ : sme_f16_outer_product<0b1, "fmops">; 47 48def SMOPA_MPPZZ_S : sme_int_outer_product_i32<0b000, "smopa">; 49def SMOPS_MPPZZ_S : sme_int_outer_product_i32<0b001, "smops">; 50def UMOPA_MPPZZ_S : sme_int_outer_product_i32<0b110, "umopa">; 51def UMOPS_MPPZZ_S : sme_int_outer_product_i32<0b111, "umops">; 52def SUMOPA_MPPZZ_S : sme_int_outer_product_i32<0b010, "sumopa">; 53def SUMOPS_MPPZZ_S : sme_int_outer_product_i32<0b011, "sumops">; 54def USMOPA_MPPZZ_S : sme_int_outer_product_i32<0b100, "usmopa">; 55def USMOPS_MPPZZ_S : sme_int_outer_product_i32<0b101, "usmops">; 56} 57 58let Predicates = [HasSMEI64] in { 59def SMOPA_MPPZZ_D : sme_int_outer_product_i64<0b000, "smopa">; 60def SMOPS_MPPZZ_D : sme_int_outer_product_i64<0b001, "smops">; 61def UMOPA_MPPZZ_D : sme_int_outer_product_i64<0b110, "umopa">; 62def UMOPS_MPPZZ_D : sme_int_outer_product_i64<0b111, "umops">; 63def SUMOPA_MPPZZ_D : sme_int_outer_product_i64<0b010, "sumopa">; 64def SUMOPS_MPPZZ_D : sme_int_outer_product_i64<0b011, "sumops">; 65def USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa">; 66def USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops">; 67} 68 69let Predicates = [HasSME] in { 70//===----------------------------------------------------------------------===// 71// Loads and stores 72//===----------------------------------------------------------------------===// 73 74defm LD1_MXIPXX : sme_mem_ld_ss<"ld1">; 75defm ST1_MXIPXX : sme_mem_st_ss<"st1">; 76 77//===----------------------------------------------------------------------===// 78// Spill + fill 79//===----------------------------------------------------------------------===// 80 81defm LDR_ZA : sme_fill<"ldr">; 82defm STR_ZA : sme_spill<"str">; 83 84//===----------------------------------------------------------------------===// 85// Move instructions 86//===----------------------------------------------------------------------===// 87 88defm INSERT_MXIPZ : sme_vector_to_tile<"mova">; 89defm EXTRACT_ZPMXI : sme_tile_to_vector<"mova">; 90 91//===----------------------------------------------------------------------===// 92// Zero instruction 93//===----------------------------------------------------------------------===// 94 95defm ZERO_M : sme_zero<"zero">; 96 97//===----------------------------------------------------------------------===// 98// Mode selection and state access instructions 99//===----------------------------------------------------------------------===// 100 101// SME defines three pstate fields to set or clear PSTATE.SM, PSTATE.ZA, or 102// both fields: 103// 104// MSR SVCRSM, #<imm1> 105// MSR SVCRZA, #<imm1> 106// MSR SVCRSMZA, #<imm1> 107// 108// It's tricky to using the existing pstate operand defined in 109// AArch64SystemOperands.td since it only encodes 5 bits including op1;op2, 110// when these fields are also encoded in CRm[3:1]. 111class MSRpstatesvcrImm0_1 112 : PstateWriteSimple<(ins svcr_op:$pstatefield, imm0_1:$imm), "msr", 113 "\t$pstatefield, $imm">, 114 Sched<[WriteSys]> { 115 bits<3> pstatefield; 116 bit imm; 117 let Inst{18-16} = 0b011; // op1 118 let Inst{11-9} = pstatefield; 119 let Inst{8} = imm; 120 let Inst{7-5} = 0b011; // op2 121} 122 123def MSRpstatesvcrImm1 : MSRpstatesvcrImm0_1; 124def : InstAlias<"smstart", (MSRpstatesvcrImm1 0b011, 0b1)>; 125def : InstAlias<"smstart sm", (MSRpstatesvcrImm1 0b001, 0b1)>; 126def : InstAlias<"smstart za", (MSRpstatesvcrImm1 0b010, 0b1)>; 127 128def : InstAlias<"smstop", (MSRpstatesvcrImm1 0b011, 0b0)>; 129def : InstAlias<"smstop sm", (MSRpstatesvcrImm1 0b001, 0b0)>; 130def : InstAlias<"smstop za", (MSRpstatesvcrImm1 0b010, 0b0)>; 131 132//===----------------------------------------------------------------------===// 133// SVE2 instructions 134//===----------------------------------------------------------------------===// 135 136def REVD_ZPmZ : sve2_int_perm_revd<"revd">; 137 138defm SCLAMP_ZZZ : sve2_clamp<"sclamp", 0b0>; 139defm UCLAMP_ZZZ : sve2_clamp<"uclamp", 0b1>; 140 141defm DUP_PPzPRI : sve2_int_perm_dup_p<"dup">; 142 143} // End let Predicates = [HasSME] 144