1//=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M4 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM4Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 48; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F, 28 PAUnsupported.F, 29 SMEUnsupported.F); 30} 31 32//===----------------------------------------------------------------------===// 33// Define each kind of processor resource and number available on the Exynos-M4. 34 35let SchedModel = ExynosM4Model in { 36 37def M4UnitA : ProcResource<2>; // Simple integer 38def M4UnitC : ProcResource<2>; // Simple and complex integer 39let Super = M4UnitC, BufferSize = 1 in 40def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 41let Super = M4UnitC in 42def M4UnitE : ProcResource<1>; // CRC (inside C0) 43def M4UnitB : ProcResource<2>; // Branch 44def M4UnitL0 : ProcResource<1>; // Load 45def M4UnitS0 : ProcResource<1>; // Store 46def M4PipeLS : ProcResource<1>; // Load/Store 47let Super = M4PipeLS in { 48 def M4UnitL1 : ProcResource<1>; 49 def M4UnitS1 : ProcResource<1>; 50} 51def M4PipeF0 : ProcResource<1>; // FP #0 52let Super = M4PipeF0 in { 53 def M4UnitFMAC0 : ProcResource<1>; // FP multiplication 54 def M4UnitFADD0 : ProcResource<1>; // Simple FP 55 def M4UnitFCVT0 : ProcResource<1>; // FP conversion 56 def M4UnitNALU0 : ProcResource<1>; // Simple vector 57 def M4UnitNHAD : ProcResource<1>; // Horizontal vector 58 def M4UnitNMSC : ProcResource<1>; // FP and vector miscellanea 59 def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication 60 def M4UnitNSHT0 : ProcResource<1>; // Vector shifting 61 def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling 62 def M4UnitNCRY0 : ProcResource<1>; // Cryptographic 63} 64def M4PipeF1 : ProcResource<1>; // FP #1 65let Super = M4PipeF1 in { 66 def M4UnitFMAC1 : ProcResource<1>; // FP multiplication 67 def M4UnitFADD1 : ProcResource<1>; // Simple FP 68 def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized) 69 def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized) 70 def M4UnitFST0 : ProcResource<1>; // FP store 71 def M4UnitNALU1 : ProcResource<1>; // Simple vector 72 def M4UnitNSHT1 : ProcResource<1>; // Vector shifting 73 def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling 74} 75def M4PipeF2 : ProcResource<1>; // FP #2 76let Super = M4PipeF2 in { 77 def M4UnitFMAC2 : ProcResource<1>; // FP multiplication 78 def M4UnitFADD2 : ProcResource<1>; // Simple FP 79 def M4UnitFCVT1 : ProcResource<1>; // FP conversion 80 def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized) 81 def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized) 82 def M4UnitFST1 : ProcResource<1>; // FP store 83 def M4UnitNALU2 : ProcResource<1>; // Simple vector 84 def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication 85 def M4UnitNSHT2 : ProcResource<1>; // Vector shifting 86 def M4UnitNCRY1 : ProcResource<1>; // Cryptographic 87} 88 89def M4UnitALU : ProcResGroup<[M4UnitA, 90 M4UnitC]>; 91def M4UnitL : ProcResGroup<[M4UnitL0, 92 M4UnitL1]>; 93def M4UnitS : ProcResGroup<[M4UnitS0, 94 M4UnitS1]>; 95def M4UnitFMAC : ProcResGroup<[M4UnitFMAC0, 96 M4UnitFMAC1, 97 M4UnitFMAC2]>; 98def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0, 99 M4UnitFMAC1]>; 100def M4UnitFADD : ProcResGroup<[M4UnitFADD0, 101 M4UnitFADD1, 102 M4UnitFADD2]>; 103def M4UnitFADDH : ProcResGroup<[M4UnitFADD0, 104 M4UnitFADD1]>; 105def M4UnitFCVT : ProcResGroup<[M4UnitFCVT0, 106 M4UnitFCVT1]>; 107def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>; 108def M4UnitFDIV : ProcResGroup<[M4UnitFDIV0, 109 M4UnitFDIV1]>; 110def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>; 111def M4UnitFSQR : ProcResGroup<[M4UnitFSQR0, 112 M4UnitFSQR1]>; 113def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>; 114def M4UnitFST : ProcResGroup<[M4UnitFST0, 115 M4UnitFST1]>; 116def M4UnitNALU : ProcResGroup<[M4UnitNALU0, 117 M4UnitNALU1, 118 M4UnitNALU2]>; 119def M4UnitNALUH : ProcResGroup<[M4UnitNALU0, 120 M4UnitNALU1]>; 121def M4UnitNMUL : ProcResGroup<[M4UnitNMUL0, 122 M4UnitNMUL1]>; 123def M4UnitNSHT : ProcResGroup<[M4UnitNSHT0, 124 M4UnitNSHT1, 125 M4UnitNSHT2]>; 126def M4UnitNSHF : ProcResGroup<[M4UnitNSHF0, 127 M4UnitNSHF1]>; 128def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>; 129def M4UnitNCRY : ProcResGroup<[M4UnitNCRY0, 130 M4UnitNCRY1]>; 131 132//===----------------------------------------------------------------------===// 133// Resources details. 134 135def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; } 136def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 137 let NumMicroOps = 0; } 138def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4; 139 let NumMicroOps = 0; } 140 141def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; } 142def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; } 143def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 144 let ResourceCycles = [2]; } 145def M4WriteAB : SchedWriteRes<[M4UnitALU, 146 M4UnitC]> { let Latency = 2; 147 let NumMicroOps = 2; } 148def M4WriteAC : SchedWriteRes<[M4UnitALU, 149 M4UnitALU, 150 M4UnitC]> { let Latency = 3; 151 let NumMicroOps = 3; } 152def M4WriteAD : SchedWriteRes<[M4UnitALU, 153 M4UnitC]> { let Latency = 2; 154 let NumMicroOps = 2; } 155def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2; 156 let NumMicroOps = 2; } 157def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M4WriteZ0]>, 158 SchedVar<ExynosArithPred, [M4WriteA1]>, 159 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 160 SchedVar<NoSchedPred, [M4WriteAA]>]>; 161def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred, [M4WriteZ0]>, 162 SchedVar<ExynosArithPred, [M4WriteA1]>, 163 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 164 SchedVar<NoSchedPred, [M4WriteAA]>]>; 165def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M4WriteA1]>, 166 SchedVar<ExynosLogicExPred, [M4WriteA1]>, 167 SchedVar<NoSchedPred, [M4WriteAA]>]>; 168def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>, 169 SchedVar<NoSchedPred, [M4WriteAF]>]>; 170 171def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; } 172def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>, 173 SchedVar<NoSchedPred, [M4WriteAB]>]>; 174 175def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; } 176def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; } 177def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4; 178 let ResourceCycles = [2]; } 179 180def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; 181 let ResourceCycles = [12]; } 182def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; 183 let ResourceCycles = [21]; } 184 185def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; } 186 187def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; } 188def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; } 189def M4WriteLA : SchedWriteRes<[M4UnitL, 190 M4UnitL]> { let Latency = 5; 191 let NumMicroOps = 1; } 192def M4WriteLB : SchedWriteRes<[M4UnitA, 193 M4UnitL]> { let Latency = 5; 194 let NumMicroOps = 2; } 195def M4WriteLC : SchedWriteRes<[M4UnitA, 196 M4UnitL, 197 M4UnitL]> { let Latency = 5; 198 let NumMicroOps = 2; } 199def M4WriteLD : SchedWriteRes<[M4UnitA, 200 M4UnitL]> { let Latency = 4; 201 let NumMicroOps = 2; } 202def M4WriteLE : SchedWriteRes<[M4UnitA, 203 M4UnitL]> { let Latency = 6; 204 let NumMicroOps = 2; } 205def M4WriteLH : SchedWriteRes<[]> { let Latency = 5; 206 let NumMicroOps = 0; } 207def M4WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteL5]>, 208 SchedVar<NoSchedPred, [M4WriteL4]>]>; 209def M4WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteLE]>, 210 SchedVar<NoSchedPred, [M4WriteL5]>]>; 211 212def M4WriteS1 : SchedWriteRes<[M4UnitS]> { let Latency = 1; } 213def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; } 214def M4WriteSB : SchedWriteRes<[M4UnitA, 215 M4UnitS]> { let Latency = 2; 216 let NumMicroOps = 1; } 217def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>, 218 SchedVar<NoSchedPred, [M4WriteS1]>]>; 219 220def M4ReadAdrBase : SchedReadVariant<[SchedVar< 221 MCSchedPredicate< 222 CheckAny< 223 [ScaledIdxFn, 224 ExynosScaledIdxFn]>>, [ReadDefault]>, 225 SchedVar<NoSchedPred, [ReadDefault]>]>; 226 227def M4WriteNEONA : SchedWriteRes<[M4UnitNSHF, 228 M4UnitFADD]> { let Latency = 3; 229 let NumMicroOps = 2; } 230def M4WriteNEONB : SchedWriteRes<[M4UnitNALU, 231 M4UnitS0]> { let Latency = 5; 232 let NumMicroOps = 2; } 233def M4WriteNEOND : SchedWriteRes<[M4UnitNSHF, 234 M4UnitFST]> { let Latency = 6; 235 let NumMicroOps = 2; } 236def M4WriteNEONH : SchedWriteRes<[M4UnitNALU, 237 M4UnitS0]> { let Latency = 5; 238 let NumMicroOps = 2; } 239def M4WriteNEONI : SchedWriteRes<[M4UnitNSHF, 240 M4UnitS0]> { let Latency = 2; 241 let NumMicroOps = 2; } 242def M4WriteNEONJ : SchedWriteRes<[M4UnitNMSC, 243 M4UnitS0]> { let Latency = 4; } 244def M4WriteNEONK : SchedWriteRes<[M4UnitNSHF, 245 M4UnitNMSC, 246 M4UnitS0]> { let Latency = 5; 247 let NumMicroOps = 2; } 248def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 249def M4WriteNEONN : SchedWriteRes<[M4UnitNMSC, 250 M4UnitNMSC]> { let Latency = 5; 251 let NumMicroOps = 2; } 252def M4WriteNEONO : SchedWriteRes<[M4UnitNMSC, 253 M4UnitNMSC, 254 M4UnitNMSC]> { let Latency = 8; 255 let NumMicroOps = 3; } 256def M4WriteNEONP : SchedWriteRes<[M4UnitNSHF, 257 M4UnitNMSC]> { let Latency = 4; 258 let NumMicroOps = 2; } 259def M4WriteNEONQ : SchedWriteRes<[M4UnitNMSC, 260 M4UnitC]> { let Latency = 3; 261 let NumMicroOps = 1; } 262def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0, 263 M4UnitS0]> { let Latency = 4; 264 let NumMicroOps = 1; } 265def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV, 266 M4UnitFDIV]> { let Latency = 7; 267 let ResourceCycles = [6, 6]; } 268def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH, 269 M4UnitFDIVH]> { let Latency = 7; 270 let ResourceCycles = [6, 6]; } 271def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV, 272 M4UnitFDIV]> { let Latency = 12; 273 let ResourceCycles = [9, 9]; } 274def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR, 275 M4UnitFSQR]> { let Latency = 8; 276 let ResourceCycles = [7, 7]; } 277def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH, 278 M4UnitFSQRH]> { let Latency = 7; 279 let ResourceCycles = [6, 6]; } 280def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR, 281 M4UnitFSQR]> { let Latency = 12; 282 let ResourceCycles = [9, 9]; } 283def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>, 284 SchedVar<NoSchedPred, [M4WriteNEONN]>]>; 285 286def M4WriteFADD2 : SchedWriteRes<[M4UnitFADD]> { let Latency = 2; } 287def M4WriteFADD2H : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; } 288 289def M4WriteFCVT2 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 2; } 290def M4WriteFCVT2A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; } 291def M4WriteFCVT2H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; } 292def M4WriteFCVT3 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 3; } 293def M4WriteFCVT3A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; } 294def M4WriteFCVT3H : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; } 295def M4WriteFCVT4 : SchedWriteRes<[M4UnitFCVT]> { let Latency = 4; } 296def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; } 297def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; } 298 299def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7; 300 let ResourceCycles = [6]; } 301def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7; 302 let ResourceCycles = [6]; } 303def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12; 304 let ResourceCycles = [9]; } 305 306def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; } 307def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; } 308def M4WriteFMAC3 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 3; } 309def M4WriteFMAC4 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 4; } 310def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; } 311def M4WriteFMAC5 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 5; } 312 313def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7; 314 let ResourceCycles = [6]; } 315def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8; 316 let ResourceCycles = [7]; } 317def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12; 318 let ResourceCycles = [9]; } 319 320def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; } 321def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; } 322 323def M4WriteNCRY1 : SchedWriteRes<[M4UnitNCRY]> { let Latency = 1; } 324def M4WriteNCRY1A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; } 325def M4WriteNCRY3A : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; } 326def M4WriteNCRY5A : SchedWriteRes<[M4UnitNCRY]> { let Latency = 5; } 327 328def M4WriteNHAD1 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 1; } 329def M4WriteNHAD3 : SchedWriteRes<[M4UnitNHAD]> { let Latency = 3; } 330 331def M4WriteNMSC1 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 1; } 332def M4WriteNMSC2 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 2; } 333def M4WriteNMSC3 : SchedWriteRes<[M4UnitNMSC]> { let Latency = 3; } 334 335def M4WriteNMUL3 : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; } 336 337def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; } 338def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; } 339def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; } 340def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; 341 let ResourceCycles = [2]; } 342def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2; 343 let NumMicroOps = 2; 344 let ResourceCycles = [2]; } 345def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; 346 let NumMicroOps = 3; 347 let ResourceCycles = [4]; } 348def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4; 349 let NumMicroOps = 4; 350 let ResourceCycles = [4]; } 351 352def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; } 353def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; } 354def M4WriteNSHT3 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 3; } 355def M4WriteNSHT4A : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; } 356 357def M4WriteVLDA : SchedWriteRes<[M4UnitL, 358 M4UnitL]> { let Latency = 5; 359 let NumMicroOps = 2; } 360def M4WriteVLDB : SchedWriteRes<[M4UnitL, 361 M4UnitL, 362 M4UnitL]> { let Latency = 6; 363 let NumMicroOps = 3; } 364def M4WriteVLDC : SchedWriteRes<[M4UnitL, 365 M4UnitL, 366 M4UnitL, 367 M4UnitL]> { let Latency = 6; 368 let NumMicroOps = 4; } 369def M4WriteVLDD : SchedWriteRes<[M4UnitL, 370 M4UnitNSHF]> { let Latency = 6; 371 let NumMicroOps = 2; 372 let ResourceCycles = [2, 1]; } 373def M4WriteVLDF : SchedWriteRes<[M4UnitL, 374 M4UnitL]> { let Latency = 10; 375 let NumMicroOps = 2; 376 let ResourceCycles = [3, 3]; } 377def M4WriteVLDG : SchedWriteRes<[M4UnitL, 378 M4UnitNSHF, 379 M4UnitNSHF]> { let Latency = 6; 380 let NumMicroOps = 3; 381 let ResourceCycles = [2, 1, 1]; } 382def M4WriteVLDI : SchedWriteRes<[M4UnitL, 383 M4UnitL, 384 M4UnitL]> { let Latency = 12; 385 let NumMicroOps = 3; 386 let ResourceCycles = [3, 3, 3]; } 387def M4WriteVLDJ : SchedWriteRes<[M4UnitL, 388 M4UnitNSHF, 389 M4UnitNSHF, 390 M4UnitNSHF]> { let Latency = 7; 391 let NumMicroOps = 4; 392 let ResourceCycles = [3, 1, 1, 1]; } 393def M4WriteVLDK : SchedWriteRes<[M4UnitL, 394 M4UnitNSHF, 395 M4UnitNSHF, 396 M4UnitNSHF, 397 M4UnitNSHF]> { let Latency = 7; 398 let NumMicroOps = 5; 399 let ResourceCycles = [3, 1, 1, 1, 1]; } 400def M4WriteVLDL : SchedWriteRes<[M4UnitL, 401 M4UnitNSHF, 402 M4UnitNSHF, 403 M4UnitL, 404 M4UnitNSHF]> { let Latency = 7; 405 let NumMicroOps = 5; 406 let ResourceCycles = [3, 1, 1, 6, 1]; } 407def M4WriteVLDM : SchedWriteRes<[M4UnitL, 408 M4UnitNSHF, 409 M4UnitNSHF, 410 M4UnitL, 411 M4UnitNSHF, 412 M4UnitNSHF]> { let Latency = 7; 413 let NumMicroOps = 6; 414 let ResourceCycles = [3, 1, 1, 3, 1, 1]; } 415def M4WriteVLDN : SchedWriteRes<[M4UnitL, 416 M4UnitL, 417 M4UnitL, 418 M4UnitL]> { let Latency = 14; 419 let NumMicroOps = 4; 420 let ResourceCycles = [3, 3, 3, 3]; } 421 422def M4WriteVST1 : SchedWriteRes<[M4UnitS, 423 M4UnitFST]> { let Latency = 1; 424 let NumMicroOps = 1; } 425def M4WriteVSTA : WriteSequence<[WriteVST], 2>; 426def M4WriteVSTB : WriteSequence<[WriteVST], 3>; 427def M4WriteVSTC : WriteSequence<[WriteVST], 4>; 428def M4WriteVSTD : SchedWriteRes<[M4UnitS, 429 M4UnitFST]> { let Latency = 2; } 430def M4WriteVSTE : SchedWriteRes<[M4UnitS, 431 M4UnitFST, 432 M4UnitS, 433 M4UnitFST]> { let Latency = 2; 434 let NumMicroOps = 2; } 435def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF, 436 M4UnitS, 437 M4UnitFST, 438 M4UnitS, 439 M4UnitFST]> { let Latency = 4; 440 let NumMicroOps = 4; 441 let ResourceCycles = [1, 2, 1, 2, 1]; } 442def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF, 443 M4UnitNSHF, 444 M4UnitNSHF, 445 M4UnitS, 446 M4UnitFST, 447 M4UnitS, 448 M4UnitFST, 449 M4UnitS, 450 M4UnitFST]> { let Latency = 5; 451 let NumMicroOps = 6; 452 let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; } 453def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF, 454 M4UnitNSHF, 455 M4UnitNSHF, 456 M4UnitNSHF, 457 M4UnitS, 458 M4UnitFST, 459 M4UnitS, 460 M4UnitFST, 461 M4UnitS, 462 M4UnitFST, 463 M4UnitS, 464 M4UnitFST]> { let Latency = 8; 465 let NumMicroOps = 5; 466 let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; } 467def M4WriteVSTJ : SchedWriteRes<[M4UnitA, 468 M4UnitS, 469 M4UnitFST, 470 M4UnitS, 471 M4UnitFST]> { let Latency = 1; 472 let NumMicroOps = 2; } 473def M4WriteVSTK : SchedWriteRes<[M4UnitA, 474 M4UnitS, 475 M4UnitFST]> { let Latency = 3; 476 let NumMicroOps = 2; } 477def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF, 478 M4UnitNSHF, 479 M4UnitS, 480 M4UnitFST, 481 M4UnitS, 482 M4UnitFST]> { let Latency = 4; 483 let NumMicroOps = 4; 484 let ResourceCycles = [1, 1, 2, 1, 2, 1]; } 485def M4WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>, 486 SchedVar<NoSchedPred, [WriteVST]>]>; 487 488// Special cases. 489def M4WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>, 490 SchedVar<NoSchedPred, [M4WriteZ0]>]>; 491def M4WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>, 492 SchedVar<NoSchedPred, [M4WriteNALU1]>]>; 493 494// Fast forwarding. 495def M4ReadAESM1 : SchedReadAdvance<+1, [M4WriteNCRY1]>; 496def M4ReadFMACM1 : SchedReadAdvance<+1, [M4WriteFMAC4, 497 M4WriteFMAC4H, 498 M4WriteFMAC5]>; 499def M4ReadNMULM1 : SchedReadAdvance<+1, [M4WriteNMUL3]>; 500def M4ReadNMULP2 : SchedReadAdvance<-2, [M4WriteNMUL3]>; 501 502 503//===----------------------------------------------------------------------===// 504// Coarse scheduling model. 505 506// Branch instructions. 507def : SchedAlias<WriteBr, M4WriteZ0>; 508def : SchedAlias<WriteBrReg, M4WriteC1>; 509 510// Arithmetic and logical integer instructions. 511def : SchedAlias<WriteI, M4WriteA1>; 512def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 513def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen. 514def : SchedAlias<WriteIS, M4WriteA1>; 515 516// Move instructions. 517def : SchedAlias<WriteImm, M4WriteA1>; 518 519// Divide and multiply instructions. 520def : SchedAlias<WriteID32, M4WriteD12>; 521def : SchedAlias<WriteID64, M4WriteD21>; 522def : SchedAlias<WriteIM32, M4WriteC3>; 523def : SchedAlias<WriteIM64, M4WriteCA>; 524 525// Miscellaneous instructions. 526def : SchedAlias<WriteExtr, M4WriteAY>; 527 528// Addressing modes. 529def : SchedAlias<WriteAdr, M4WriteZ1>; 530def : SchedAlias<ReadAdrBase, M4ReadAdrBase>; 531 532// Load instructions. 533def : SchedAlias<WriteLD, M4WriteL4>; 534def : SchedAlias<WriteLDHi, M4WriteZ4>; 535def : SchedAlias<WriteLDIdx, M4WriteLX>; 536 537// Store instructions. 538def : SchedAlias<WriteST, M4WriteS1>; 539def : SchedAlias<WriteSTP, M4WriteS1>; 540def : SchedAlias<WriteSTX, M4WriteS1>; 541def : SchedAlias<WriteSTIdx, M4WriteSX>; 542 543// FP data instructions. 544def : SchedAlias<WriteF, M4WriteFADD2>; 545def : SchedAlias<WriteFCmp, M4WriteNMSC2>; 546def : SchedAlias<WriteFDiv, M4WriteFDIV12>; 547def : SchedAlias<WriteFMul, M4WriteFMAC3>; 548 549// FP miscellaneous instructions. 550def : SchedAlias<WriteFCvt, M4WriteFCVT2>; 551def : SchedAlias<WriteFImm, M4WriteNALU1>; 552def : SchedAlias<WriteFCopy, M4WriteNALU1>; 553 554// FP load instructions. 555def : SchedAlias<WriteVLD, M4WriteL5>; 556 557// FP store instructions. 558def : SchedAlias<WriteVST, M4WriteVST1>; 559 560// ASIMD FP instructions. 561def : SchedAlias<WriteV, M4WriteNALU1>; 562 563// Other miscellaneous instructions. 564def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 565def : WriteRes<WriteBarrier, []> { let Latency = 1; } 566def : WriteRes<WriteHint, []> { let Latency = 1; } 567def : WriteRes<WriteSys, []> { let Latency = 1; } 568 569//===----------------------------------------------------------------------===// 570// Generic fast forwarding. 571 572// TODO: Add FP register forwarding rules. 573 574def : ReadAdvance<ReadI, 0>; 575def : ReadAdvance<ReadISReg, 0>; 576def : ReadAdvance<ReadIEReg, 0>; 577def : ReadAdvance<ReadIM, 0>; 578// TODO: The forwarding for 32 bits actually saves 2 cycles. 579def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 580def : ReadAdvance<ReadID, 0>; 581def : ReadAdvance<ReadExtrHi, 0>; 582def : ReadAdvance<ReadAdrBase, 0>; 583def : ReadAdvance<ReadVLD, 0>; 584 585//===----------------------------------------------------------------------===// 586// Finer scheduling model. 587 588// Branch instructions 589def : InstRW<[M4WriteB1], (instrs Bcc)>; 590def : InstRW<[M4WriteAF], (instrs BL)>; 591def : InstRW<[M4WriteBX], (instrs BLR)>; 592def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>; 593def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>; 594 595// Arithmetic and logical integer instructions. 596def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 597def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>; 598def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 599def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 600def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>; 601 602// Move instructions. 603def : InstRW<[M4WriteCOPY], (instrs COPY)>; 604def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>; 605def : InstRW<[M4WriteZ0], (instregex "^MOV[NZ][WX]i")>; 606 607// Divide and multiply instructions. 608 609// Miscellaneous instructions. 610 611// Load instructions. 612def : InstRW<[M4WriteLD, 613 WriteLDHi, 614 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 615def : InstRW<[M4WriteL5, 616 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 617def : InstRW<[WriteLDIdx, 618 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 619def : InstRW<[M4WriteL5, 620 ReadAdrBase], (instrs PRFMroW)>; 621def : InstRW<[WriteLDIdx, 622 ReadAdrBase], (instrs PRFMroX)>; 623 624// Store instructions. 625def : InstRW<[M4WriteSB, 626 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 627def : InstRW<[WriteST, 628 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 629 630// FP data instructions. 631def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>; 632def : InstRW<[M4WriteNSHF1], (instregex "^FABS[SD]r")>; 633def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>; 634def : InstRW<[M4WriteFADD2], (instregex "^F(ADD|SUB)[SD]rr")>; 635def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>; 636def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.i(32|64)")>; 637def : InstRW<[M4WriteNEONQ], (instregex "^FCCMPE?[HSD]rr")>; 638def : InstRW<[M4WriteNMSC2], (instregex "^FCMPE?[HSD]r[ir]")>; 639def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>; 640def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>; 641def : InstRW<[M4WriteFDIV7], (instrs FDIVSrr)>; 642def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>; 643def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>; 644def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>; 645def : InstRW<[M4WriteFMAC3], (instregex "^FN?MUL[SD]rr")>; 646def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>; 647def : InstRW<[M4WriteFMAC3], (instregex "^FMULX(32|64)")>; 648def : InstRW<[M4WriteFMAC4H, 649 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)Hrrr")>; 650def : InstRW<[M4WriteFMAC4, 651 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)[SD]rrr")>; 652def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>; 653def : InstRW<[M4WriteNALU1], (instregex "^FNEG[SD]r")>; 654def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>; 655def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>; 656def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>; 657def : InstRW<[M4WriteFSQR8], (instrs FSQRTSr)>; 658def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>; 659 660// FP miscellaneous instructions. 661def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>; 662def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>; 663def : InstRW<[M4WriteFCVT2], (instregex "^FCVT[SD][SD]r")>; 664def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>; 665def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>; 666def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>; 667def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>; 668def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>; 669def : InstRW<[M4WriteNEONI], (instregex "^FMOVXDHighr")>; 670def : InstRW<[M4WriteNEONK], (instregex "^FMOVDXHighr")>; 671def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>; 672def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>; 673def : InstRW<[M4WriteNMSC1], (instregex "^FRECPXv1")>; 674def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>; 675def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)S(32|64)")>; 676 677// FP load instructions. 678def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>; 679def : InstRW<[WriteVLD], (instregex "^LDUR[BHSDQ]i")>; 680def : InstRW<[WriteVLD, 681 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>; 682def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>; 683def : InstRW<[M4WriteLE, 684 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>; 685def : InstRW<[WriteVLD, 686 ReadAdrBase], (instregex "^LDR[BHSD]roX")>; 687def : InstRW<[M4WriteLY, 688 ReadAdrBase], (instrs LDRQroX)>; 689def : InstRW<[WriteVLD, 690 M4WriteLH], (instregex "^LDN?P[SD]i")>; 691def : InstRW<[M4WriteLA, 692 M4WriteLH], (instregex "^LDN?PQi")>; 693def : InstRW<[M4WriteL5, 694 M4WriteLH, 695 WriteAdr], (instregex "^LDP[SD]post")>; 696def : InstRW<[M4WriteLB, 697 M4WriteLH, 698 WriteAdr], (instrs LDPQpost)>; 699def : InstRW<[M4WriteLB, 700 M4WriteLH, 701 WriteAdr], (instregex "^LDP[SD]pre")>; 702def : InstRW<[M4WriteLC, 703 M4WriteLH, 704 WriteAdr], (instrs LDPQpre)>; 705 706// FP store instructions. 707def : InstRW<[WriteVST], (instregex "^STUR[BHSDQ]i")>; 708def : InstRW<[WriteVST, 709 WriteAdr], (instregex "^STR[BHSDQ](post|pre)")>; 710def : InstRW<[WriteVST], (instregex "^STR[BHSDQ]ui")>; 711def : InstRW<[M4WriteVSTK, 712 ReadAdrBase], (instregex "^STR[BHSD]roW")>; 713def : InstRW<[M4WriteVSTK, 714 ReadAdrBase], (instrs STRQroW)>; 715def : InstRW<[WriteVST, 716 ReadAdrBase], (instregex "^STR[BHSD]roX")>; 717def : InstRW<[M4WriteVSTY, 718 ReadAdrBase], (instrs STRQroX)>; 719def : InstRW<[WriteVST], (instregex "^STN?P[SD]i")>; 720def : InstRW<[M4WriteVSTJ], (instregex "^STN?PQi")>; 721def : InstRW<[WriteVST, 722 WriteAdr], (instregex "^STP[SD](post|pre)")>; 723def : InstRW<[M4WriteVSTJ, 724 WriteAdr], (instregex "^STPQ(post|pre)")>; 725 726// ASIMD instructions. 727def : InstRW<[M4WriteNHAD1], (instregex "^[SU]ABDL?v")>; 728def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ABAL?v")>; 729def : InstRW<[M4WriteNMSC1], (instregex "^ABSv")>; 730def : InstRW<[M4WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 731def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>; 732def : InstRW<[M4WriteNHAD3], (instregex "^[SU]H(ADD|SUB)v")>; 733def : InstRW<[M4WriteNHAD3], (instregex "^[SU](ADD|SUB)[LW]v")>; 734def : InstRW<[M4WriteNHAD3], (instregex "^R?(ADD|SUB)HN2?v")>; 735def : InstRW<[M4WriteNHAD3], (instregex "^[SU]Q(ADD|SUB)v")>; 736def : InstRW<[M4WriteNHAD3], (instregex "^(SU|US)QADDv")>; 737def : InstRW<[M4WriteNHAD3], (instregex "^[SU]RHADDv")>; 738def : InstRW<[M4WriteNMSC1], (instregex "^SQ(ABS|NEG)v")>; 739def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>; 740def : InstRW<[M4WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 741def : InstRW<[M4WriteNALU1], (instregex "^CMTSTv")>; 742def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>; 743def : InstRW<[M4WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 744def : InstRW<[M4WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 745def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>; 746def : InstRW<[M4WriteNMUL3, 747 M4ReadNMULM1], (instregex "^ML[AS]v")>; 748def : InstRW<[M4WriteNMUL3, 749 M4ReadNMULM1], (instregex "^(SQR?D)?MULH?v")>; 750def : InstRW<[M4WriteNMUL3, 751 M4ReadNMULM1], (instregex "^SQRDML[AS]H")>; 752def : InstRW<[M4WriteNMUL3, 753 M4ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 754def : InstRW<[M4WriteNMUL3, 755 M4ReadNMULP2], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>; 756def : InstRW<[M4WriteNMUL3, 757 M4ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>; 758def : InstRW<[M4WriteNMUL3, 759 M4ReadNMULP2], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>; 760def : InstRW<[M4WriteNMUL3], (instregex "^[SU]DOT(lane)?v")>; 761def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ADALPv")>; 762def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>; 763def : InstRW<[M4WriteNSHT1], (instregex "^SHL[dv]")>; 764def : InstRW<[M4WriteNSHT1], (instregex "^S[LR]I[dv]")>; 765def : InstRW<[M4WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 766def : InstRW<[M4WriteNSHT2], (instregex "^[SU]?SHLLv")>; 767def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>; 768def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>; 769def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>; 770 771// ASIMD FP instructions. 772def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>; 773def : InstRW<[M4WriteNSHF1], (instregex "^FABSv.f(32|64)")>; 774def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>; 775def : InstRW<[M4WriteFADD2], (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>; 776def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>; 777def : InstRW<[M4WriteFADD2], (instregex "^FADDPv.f(32|64)")>; 778def : InstRW<[M4WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 779def : InstRW<[M4WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>; 780def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>; 781def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>; 782def : InstRW<[M4WriteFCVT2], (instregex "^[SU]CVTFv.[fi](32|64)")>; 783def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>; 784def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>; 785def : InstRW<[M4WriteFDIV7], (instrs FDIVv2f32)>; 786def : InstRW<[M4WriteNEONV], (instrs FDIVv4f32)>; 787def : InstRW<[M4WriteNEONW], (instrs FDIVv2f64)>; 788def : InstRW<[M4WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 789def : InstRW<[M4WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 790def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 791def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>; 792def : InstRW<[M4WriteFMAC3], (instregex "^FMULX?v.[fi](32|64)")>; 793def : InstRW<[M4WriteFMAC4H, 794 M4ReadFMACM1], (instregex "^FML[AS]v.[fi]16")>; 795def : InstRW<[M4WriteFMAC4, 796 M4ReadFMACM1], (instregex "^FML[AS]v.[fi](32|64)")>; 797def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>; 798def : InstRW<[M4WriteNALU1], (instregex "^FNEGv.f(32|64)")>; 799def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 800def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>; 801def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>; 802def : InstRW<[M4WriteFSQR8], (instrs FSQRTv2f32)>; 803def : InstRW<[M4WriteNEONX], (instrs FSQRTv4f32)>; 804def : InstRW<[M4WriteNEONY], (instrs FSQRTv2f64)>; 805 806// ASIMD miscellaneous instructions. 807def : InstRW<[M4WriteNALU1], (instregex "^RBITv")>; 808def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>; 809def : InstRW<[M4WriteNALU1], (instregex "^CL[STZ]v")>; 810def : InstRW<[M4WriteNEONB], (instregex "^DUPv.+gpr")>; 811def : InstRW<[M4WriteNSHF1], (instregex "^CPY")>; 812def : InstRW<[M4WriteNSHF1], (instregex "^DUPv.+lane")>; 813def : InstRW<[M4WriteNSHF1], (instregex "^EXTv")>; 814def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>; 815def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>; 816def : InstRW<[M4WriteNEONB], (instregex "^INSv.+gpr")>; 817def : InstRW<[M4WriteNSHF1], (instregex "^INSv.+lane")>; 818def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>; 819def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>; 820def : InstRW<[M4WriteNALU1], (instregex "^FMOVv.f(32|64)")>; 821def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>; 822def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>; 823def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>; 824def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>; 825def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>; 826def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>; 827def : InstRW<[M4WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>; 828def : InstRW<[M4WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>; 829def : InstRW<[M4WriteNSHFC], (instregex "^TB[LX]v(8|16)i8Three")>; 830def : InstRW<[M4WriteNSHFD], (instregex "^TB[LX]v(8|16)i8Four")>; 831def : InstRW<[M4WriteNEONP], (instregex "^[SU]MOVv")>; 832def : InstRW<[M4WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 833 834// ASIMD load instructions. 835def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 836def : InstRW<[WriteVLD, 837 M4WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 838def : InstRW<[WriteVLD], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 839def : InstRW<[WriteVLD, 840 M4WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 841 842def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 843def : InstRW<[M4WriteVLDA, 844 M4WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 845def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 846def : InstRW<[M4WriteVLDA, 847 M4WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 848 849def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 850def : InstRW<[M4WriteVLDB, 851 M4WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 852def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 853def : InstRW<[M4WriteVLDB, 854 M4WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 855 856def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 857def : InstRW<[M4WriteVLDC, 858 M4WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 859def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 860def : InstRW<[M4WriteVLDC, 861 M4WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 862 863def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>; 864def : InstRW<[M4WriteVLDD, 865 M4WriteA1], (instregex "LD1i(8|16|32|64)_POST$")>; 866 867def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 868def : InstRW<[WriteVLD, 869 M4WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>; 870def : InstRW<[WriteVLD], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 871def : InstRW<[WriteVLD, 872 M4WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 873 874def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 875def : InstRW<[M4WriteVLDF, 876 M4WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 877def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 878def : InstRW<[M4WriteVLDF, 879 M4WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; 880 881def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>; 882def : InstRW<[M4WriteVLDG, 883 M4WriteA1], (instregex "LD2i(8|16|32|64)_POST$")>; 884 885def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 886def : InstRW<[M4WriteVLDA, 887 M4WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>; 888def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 889def : InstRW<[M4WriteVLDA, 890 M4WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 891 892def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 893def : InstRW<[M4WriteVLDI, 894 M4WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 895def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 896def : InstRW<[M4WriteVLDI, 897 M4WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>; 898 899def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 900def : InstRW<[M4WriteVLDJ, 901 M4WriteA1], (instregex "LD3i(8|16|32)_POST$")>; 902def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>; 903def : InstRW<[M4WriteVLDL, 904 M4WriteA1], (instregex "LD3i64_POST$")>; 905 906def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 907def : InstRW<[M4WriteVLDB, 908 M4WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>; 909def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 910def : InstRW<[M4WriteVLDB, 911 M4WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>; 912 913def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 914def : InstRW<[M4WriteVLDN, 915 M4WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 916def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 917def : InstRW<[M4WriteVLDN, 918 M4WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; 919 920def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>; 921def : InstRW<[M4WriteVLDK, 922 M4WriteA1], (instregex "LD4i(8|16|32)_POST$")>; 923def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>; 924def : InstRW<[M4WriteVLDM, 925 M4WriteA1], (instregex "LD4i64_POST$")>; 926 927def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 928def : InstRW<[M4WriteVLDC, 929 M4WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>; 930def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 931def : InstRW<[M4WriteVLDC, 932 M4WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>; 933 934// ASIMD store instructions. 935def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 936def : InstRW<[WriteVST, 937 M4WriteA1], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 938def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 939def : InstRW<[WriteVST, 940 M4WriteA1], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 941 942def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 943def : InstRW<[M4WriteVSTA, 944 M4WriteA1], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 945def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 946def : InstRW<[M4WriteVSTA, 947 M4WriteA1], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 948 949def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 950def : InstRW<[M4WriteVSTB, 951 M4WriteA1], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 952def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 953def : InstRW<[M4WriteVSTB, 954 M4WriteA1], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 955 956def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 957def : InstRW<[M4WriteVSTC, 958 M4WriteA1], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 959def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 960def : InstRW<[M4WriteVSTC, 961 M4WriteA1], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 962 963def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>; 964def : InstRW<[WriteVST, 965 M4WriteA1], (instregex "ST1i(8|16|32|64)_POST$")>; 966 967def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 968def : InstRW<[M4WriteVSTD, 969 M4WriteA1], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 970def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 971def : InstRW<[M4WriteVSTE, 972 M4WriteA1], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 973 974def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>; 975def : InstRW<[M4WriteVSTD, 976 M4WriteA1], (instregex "ST2i(8|16|32|64)_POST$")>; 977 978def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 979def : InstRW<[M4WriteVSTF, 980 M4WriteA1], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 981def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 982def : InstRW<[M4WriteVSTG, 983 M4WriteA1], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>; 984 985def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>; 986def : InstRW<[M4WriteVSTE, 987 M4WriteA1], (instregex "ST3i(8|16|32|64)_POST$")>; 988 989def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>; 990def : InstRW<[M4WriteVSTL, 991 M4WriteA1], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 992def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 993def : InstRW<[M4WriteVSTI, 994 M4WriteA1], (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>; 995 996def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>; 997def : InstRW<[M4WriteVSTE, 998 M4WriteA1], (instregex "ST4i(8|16|32|64)_POST$")>; 999 1000// Cryptography instructions. 1001def : InstRW<[M4WriteNCRY1], (instregex "^AES[DE]")>; 1002def : InstRW<[M4WriteNCRY1, 1003 M4ReadAESM1], (instregex "^AESI?MC")>; 1004def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>; 1005def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>; 1006def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>; 1007def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 1008def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>; 1009def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>; 1010def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>; 1011 1012// CRC instructions. 1013def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>; 1014 1015} // SchedModel = ExynosM4Model 1016