1 //===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the VE Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/VEMCTargetDesc.h"
14 #include "TargetInfo/VETargetInfo.h"
15 #include "VE.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/TargetRegistry.h"
22
23 using namespace llvm;
24
25 #define DEBUG_TYPE "ve-disassembler"
26
27 typedef MCDisassembler::DecodeStatus DecodeStatus;
28
29 namespace {
30
31 /// A disassembler class for VE.
32 class VEDisassembler : public MCDisassembler {
33 public:
VEDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)34 VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
35 : MCDisassembler(STI, Ctx) {}
~VEDisassembler()36 virtual ~VEDisassembler() {}
37
38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39 ArrayRef<uint8_t> Bytes, uint64_t Address,
40 raw_ostream &CStream) const override;
41 };
42 } // namespace
43
createVEDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)44 static MCDisassembler *createVEDisassembler(const Target &T,
45 const MCSubtargetInfo &STI,
46 MCContext &Ctx) {
47 return new VEDisassembler(STI, Ctx);
48 }
49
LLVMInitializeVEDisassembler()50 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEDisassembler() {
51 // Register the disassembler.
52 TargetRegistry::RegisterMCDisassembler(getTheVETarget(),
53 createVEDisassembler);
54 }
55
56 static const unsigned I32RegDecoderTable[] = {
57 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
58 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
59 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
60 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
61 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
62 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
63 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
64 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
65 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
66 VE::SW63};
67
68 static const unsigned I64RegDecoderTable[] = {
69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
70 VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13,
71 VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20,
72 VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27,
73 VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34,
74 VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41,
75 VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48,
76 VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55,
77 VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62,
78 VE::SX63};
79
80 static const unsigned F32RegDecoderTable[] = {
81 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
82 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,
83 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
84 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
85 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
86 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
87 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
88 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
89 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
90 VE::SF63};
91
92 static const unsigned F128RegDecoderTable[] = {
93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
94 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
95 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
96 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
97
98 static const unsigned V64RegDecoderTable[] = {
99 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7,
100 VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15,
101 VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23,
102 VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31,
103 VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39,
104 VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47,
105 VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55,
106 VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63};
107
108 static const unsigned VMRegDecoderTable[] = {
109 VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5,
110 VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11,
111 VE::VM12, VE::VM13, VE::VM14, VE::VM15};
112
113 static const unsigned VM512RegDecoderTable[] = {VE::VMP0, VE::VMP1, VE::VMP2,
114 VE::VMP3, VE::VMP4, VE::VMP5,
115 VE::VMP6, VE::VMP7};
116
117 static const unsigned MiscRegDecoderTable[] = {
118 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
119 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
120 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,
121 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
122 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,
123 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,
124 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,
125 VE::PMC12, VE::PMC13, VE::PMC14};
126
DecodeI32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)127 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo,
128 uint64_t Address,
129 const void *Decoder) {
130 if (RegNo > 63)
131 return MCDisassembler::Fail;
132 unsigned Reg = I32RegDecoderTable[RegNo];
133 Inst.addOperand(MCOperand::createReg(Reg));
134 return MCDisassembler::Success;
135 }
136
DecodeI64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)137 static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo,
138 uint64_t Address,
139 const void *Decoder) {
140 if (RegNo > 63)
141 return MCDisassembler::Fail;
142 unsigned Reg = I64RegDecoderTable[RegNo];
143 Inst.addOperand(MCOperand::createReg(Reg));
144 return MCDisassembler::Success;
145 }
146
DecodeF32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)147 static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo,
148 uint64_t Address,
149 const void *Decoder) {
150 if (RegNo > 63)
151 return MCDisassembler::Fail;
152 unsigned Reg = F32RegDecoderTable[RegNo];
153 Inst.addOperand(MCOperand::createReg(Reg));
154 return MCDisassembler::Success;
155 }
156
DecodeF128RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)157 static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address,
159 const void *Decoder) {
160 if (RegNo % 2 || RegNo > 63)
161 return MCDisassembler::Fail;
162 unsigned Reg = F128RegDecoderTable[RegNo / 2];
163 Inst.addOperand(MCOperand::createReg(Reg));
164 return MCDisassembler::Success;
165 }
166
DecodeV64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)167 static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo,
168 uint64_t Address,
169 const void *Decoder) {
170 unsigned Reg = VE::NoRegister;
171 if (RegNo == 255)
172 Reg = VE::VIX;
173 else if (RegNo > 63)
174 return MCDisassembler::Fail;
175 else
176 Reg = V64RegDecoderTable[RegNo];
177 Inst.addOperand(MCOperand::createReg(Reg));
178 return MCDisassembler::Success;
179 }
180
DecodeVMRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)181 static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo,
182 uint64_t Address,
183 const void *Decoder) {
184 if (RegNo > 15)
185 return MCDisassembler::Fail;
186 unsigned Reg = VMRegDecoderTable[RegNo];
187 Inst.addOperand(MCOperand::createReg(Reg));
188 return MCDisassembler::Success;
189 }
190
DecodeVM512RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)191 static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo,
192 uint64_t Address,
193 const void *Decoder) {
194 if (RegNo % 2 || RegNo > 15)
195 return MCDisassembler::Fail;
196 unsigned Reg = VM512RegDecoderTable[RegNo / 2];
197 Inst.addOperand(MCOperand::createReg(Reg));
198 return MCDisassembler::Success;
199 }
200
DecodeMISCRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)201 static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,
202 uint64_t Address,
203 const void *Decoder) {
204 if (RegNo > 30)
205 return MCDisassembler::Fail;
206 unsigned Reg = MiscRegDecoderTable[RegNo];
207 if (Reg == VE::NoRegister)
208 return MCDisassembler::Fail;
209 Inst.addOperand(MCOperand::createReg(Reg));
210 return MCDisassembler::Success;
211 }
212
213 static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address,
214 const void *Decoder);
215 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
216 const void *Decoder);
217 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
220 const void *Decoder);
221 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
224 const void *Decoder);
225 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address,
236 const void *Decoder);
237 static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address,
238 const void *Decoder);
239 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
240 const void *Decoder);
241 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address,
242 const void *Decoder);
243 static DecodeStatus DecodeSIMM32(MCInst &Inst, uint64_t insn, uint64_t Address,
244 const void *Decoder);
245 static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeRDOperand(MCInst &Inst, uint64_t insn,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn,
250 uint64_t Address,
251 const void *Decoder);
252 static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn,
253 uint64_t Address,
254 const void *Decoder);
255
256 #include "VEGenDisassemblerTables.inc"
257
258 /// Read four bytes from the ArrayRef and return 32 bit word.
readInstruction64(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint64_t & Insn,bool IsLittleEndian)259 static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,
260 uint64_t &Size, uint64_t &Insn,
261 bool IsLittleEndian) {
262 // We want to read exactly 8 Bytes of data.
263 if (Bytes.size() < 8) {
264 Size = 0;
265 return MCDisassembler::Fail;
266 }
267
268 Insn = IsLittleEndian
269 ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
270 ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) |
271 ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) |
272 ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56)
273 : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) |
274 ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) |
275 ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) |
276 ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56);
277
278 return MCDisassembler::Success;
279 }
280
getInstruction(MCInst & Instr,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CStream) const281 DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
282 ArrayRef<uint8_t> Bytes,
283 uint64_t Address,
284 raw_ostream &CStream) const {
285 uint64_t Insn;
286 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
287 DecodeStatus Result =
288 readInstruction64(Bytes, Address, Size, Insn, isLittleEndian);
289 if (Result == MCDisassembler::Fail)
290 return MCDisassembler::Fail;
291
292 // Calling the auto-generated decoder function.
293
294 Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI);
295
296 if (Result != MCDisassembler::Fail) {
297 Size = 8;
298 return Result;
299 }
300
301 return MCDisassembler::Fail;
302 }
303
304 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address,
305 const void *Decoder);
306
DecodeASX(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)307 static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address,
308 const void *Decoder) {
309 unsigned sy = fieldFromInstruction(insn, 40, 7);
310 bool cy = fieldFromInstruction(insn, 47, 1);
311 unsigned sz = fieldFromInstruction(insn, 32, 7);
312 bool cz = fieldFromInstruction(insn, 39, 1);
313 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
314 DecodeStatus status;
315
316 // Decode sz.
317 if (cz) {
318 status = DecodeI64RegisterClass(MI, sz, Address, Decoder);
319 if (status != MCDisassembler::Success)
320 return status;
321 } else {
322 MI.addOperand(MCOperand::createImm(0));
323 }
324
325 // Decode sy.
326 if (cy) {
327 status = DecodeI64RegisterClass(MI, sy, Address, Decoder);
328 if (status != MCDisassembler::Success)
329 return status;
330 } else {
331 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
332 }
333
334 // Decode simm32.
335 MI.addOperand(MCOperand::createImm(simm32));
336
337 return MCDisassembler::Success;
338 }
339
DecodeAS(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)340 static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address,
341 const void *Decoder) {
342 unsigned sz = fieldFromInstruction(insn, 32, 7);
343 bool cz = fieldFromInstruction(insn, 39, 1);
344 uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
345 DecodeStatus status;
346
347 // Decode sz.
348 if (cz) {
349 status = DecodeI64RegisterClass(MI, sz, Address, Decoder);
350 if (status != MCDisassembler::Success)
351 return status;
352 } else {
353 MI.addOperand(MCOperand::createImm(0));
354 }
355
356 // Decode simm32.
357 MI.addOperand(MCOperand::createImm(simm32));
358
359 return MCDisassembler::Success;
360 }
361
DecodeMem(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder,bool isLoad,DecodeFunc DecodeSX)362 static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address,
363 const void *Decoder, bool isLoad,
364 DecodeFunc DecodeSX) {
365 unsigned sx = fieldFromInstruction(insn, 48, 7);
366
367 DecodeStatus status;
368 if (isLoad) {
369 status = DecodeSX(MI, sx, Address, Decoder);
370 if (status != MCDisassembler::Success)
371 return status;
372 }
373
374 status = DecodeASX(MI, insn, Address, Decoder);
375 if (status != MCDisassembler::Success)
376 return status;
377
378 if (!isLoad) {
379 status = DecodeSX(MI, sx, Address, Decoder);
380 if (status != MCDisassembler::Success)
381 return status;
382 }
383 return MCDisassembler::Success;
384 }
385
DecodeMemAS(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder,bool isLoad,DecodeFunc DecodeSX)386 static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address,
387 const void *Decoder, bool isLoad,
388 DecodeFunc DecodeSX) {
389 unsigned sx = fieldFromInstruction(insn, 48, 7);
390
391 DecodeStatus status;
392 if (isLoad) {
393 status = DecodeSX(MI, sx, Address, Decoder);
394 if (status != MCDisassembler::Success)
395 return status;
396 }
397
398 status = DecodeAS(MI, insn, Address, Decoder);
399 if (status != MCDisassembler::Success)
400 return status;
401
402 if (!isLoad) {
403 status = DecodeSX(MI, sx, Address, Decoder);
404 if (status != MCDisassembler::Success)
405 return status;
406 }
407 return MCDisassembler::Success;
408 }
409
DecodeLoadI32(MCInst & Inst,uint64_t insn,uint64_t Address,const void * Decoder)410 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
411 const void *Decoder) {
412 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass);
413 }
414
DecodeStoreI32(MCInst & Inst,uint64_t insn,uint64_t Address,const void * Decoder)415 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
416 uint64_t Address, const void *Decoder) {
417 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass);
418 }
419
DecodeLoadI64(MCInst & Inst,uint64_t insn,uint64_t Address,const void * Decoder)420 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
421 const void *Decoder) {
422 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);
423 }
424
DecodeStoreI64(MCInst & Inst,uint64_t insn,uint64_t Address,const void * Decoder)425 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
426 uint64_t Address, const void *Decoder) {
427 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass);
428 }
429
DecodeLoadF32(MCInst & Inst,uint64_t insn,uint64_t Address,const void * Decoder)430 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
431 const void *Decoder) {
432 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass);
433 }
434
DecodeStoreF32(MCInst & Inst,uint64_t insn,uint64_t Address,const void * Decoder)435 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
436 uint64_t Address, const void *Decoder) {
437 return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);
438 }
439
DecodeLoadASI64(MCInst & Inst,uint64_t insn,uint64_t Address,const void * Decoder)440 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
441 uint64_t Address, const void *Decoder) {
442 return DecodeMemAS(Inst, insn, Address, Decoder, true,
443 DecodeI64RegisterClass);
444 }
445
DecodeStoreASI64(MCInst & Inst,uint64_t insn,uint64_t Address,const void * Decoder)446 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
447 uint64_t Address, const void *Decoder) {
448 return DecodeMemAS(Inst, insn, Address, Decoder, false,
449 DecodeI64RegisterClass);
450 }
451
DecodeCAS(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder,bool isImmOnly,bool isUImm,DecodeFunc DecodeSX)452 static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,
453 const void *Decoder, bool isImmOnly, bool isUImm,
454 DecodeFunc DecodeSX) {
455 unsigned sx = fieldFromInstruction(insn, 48, 7);
456 bool cy = fieldFromInstruction(insn, 47, 1);
457 unsigned sy = fieldFromInstruction(insn, 40, 7);
458
459 // Add $sx.
460 DecodeStatus status;
461 status = DecodeSX(MI, sx, Address, Decoder);
462 if (status != MCDisassembler::Success)
463 return status;
464
465 // Add $disp($sz).
466 status = DecodeAS(MI, insn, Address, Decoder);
467 if (status != MCDisassembler::Success)
468 return status;
469
470 // Add $sy.
471 if (cy && !isImmOnly) {
472 status = DecodeSX(MI, sy, Address, Decoder);
473 if (status != MCDisassembler::Success)
474 return status;
475 } else {
476 if (isUImm)
477 MI.addOperand(MCOperand::createImm(sy));
478 else
479 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
480 }
481
482 // Add $sd.
483 status = DecodeSX(MI, sx, Address, Decoder);
484 if (status != MCDisassembler::Success)
485 return status;
486
487 return MCDisassembler::Success;
488 }
489
DecodeTS1AMI64(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)490 static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address,
491 const void *Decoder) {
492 return DecodeCAS(MI, insn, Address, Decoder, false, true,
493 DecodeI64RegisterClass);
494 }
495
DecodeTS1AMI32(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)496 static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address,
497 const void *Decoder) {
498 return DecodeCAS(MI, insn, Address, Decoder, false, true,
499 DecodeI32RegisterClass);
500 }
501
DecodeCASI64(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)502 static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address,
503 const void *Decoder) {
504 return DecodeCAS(MI, insn, Address, Decoder, false, false,
505 DecodeI64RegisterClass);
506 }
507
DecodeCASI32(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)508 static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address,
509 const void *Decoder) {
510 return DecodeCAS(MI, insn, Address, Decoder, false, false,
511 DecodeI32RegisterClass);
512 }
513
DecodeCall(MCInst & Inst,uint64_t insn,uint64_t Address,const void * Decoder)514 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
515 const void *Decoder) {
516 return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);
517 }
518
DecodeSIMM7(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)519 static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address,
520 const void *Decoder) {
521 uint64_t tgt = SignExtend64<7>(insn);
522 MI.addOperand(MCOperand::createImm(tgt));
523 return MCDisassembler::Success;
524 }
525
DecodeSIMM32(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)526 static DecodeStatus DecodeSIMM32(MCInst &MI, uint64_t insn, uint64_t Address,
527 const void *Decoder) {
528 uint64_t tgt = SignExtend64<32>(insn);
529 MI.addOperand(MCOperand::createImm(tgt));
530 return MCDisassembler::Success;
531 }
532
isIntegerBCKind(MCInst & MI)533 static bool isIntegerBCKind(MCInst &MI) {
534
535 #define BCm_kind(NAME) \
536 case NAME##rri: \
537 case NAME##rzi: \
538 case NAME##iri: \
539 case NAME##izi: \
540 case NAME##rri_nt: \
541 case NAME##rzi_nt: \
542 case NAME##iri_nt: \
543 case NAME##izi_nt: \
544 case NAME##rri_t: \
545 case NAME##rzi_t: \
546 case NAME##iri_t: \
547 case NAME##izi_t:
548
549 #define BCRm_kind(NAME) \
550 case NAME##rr: \
551 case NAME##ir: \
552 case NAME##rr_nt: \
553 case NAME##ir_nt: \
554 case NAME##rr_t: \
555 case NAME##ir_t:
556
557 {
558 using namespace llvm::VE;
559 switch (MI.getOpcode()) {
560 BCm_kind(BCFL) BCm_kind(BCFW) BCRm_kind(BRCFL)
561 BCRm_kind(BRCFW) return true;
562 }
563 }
564 #undef BCm_kind
565
566 return false;
567 }
568
569 // Decode CC Operand field.
DecodeCCOperand(MCInst & MI,uint64_t cf,uint64_t Address,const void * Decoder)570 static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address,
571 const void *Decoder) {
572 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));
573 return MCDisassembler::Success;
574 }
575
576 // Decode RD Operand field.
DecodeRDOperand(MCInst & MI,uint64_t cf,uint64_t Address,const void * Decoder)577 static DecodeStatus DecodeRDOperand(MCInst &MI, uint64_t cf, uint64_t Address,
578 const void *Decoder) {
579 MI.addOperand(MCOperand::createImm(VEValToRD(cf)));
580 return MCDisassembler::Success;
581 }
582
583 // Decode branch condition instruction and CCOperand field in it.
DecodeBranchCondition(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)584 static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn,
585 uint64_t Address,
586 const void *Decoder) {
587 unsigned cf = fieldFromInstruction(insn, 48, 4);
588 bool cy = fieldFromInstruction(insn, 47, 1);
589 unsigned sy = fieldFromInstruction(insn, 40, 7);
590
591 // Decode cf.
592 MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));
593
594 // Decode sy.
595 DecodeStatus status;
596 if (cy) {
597 status = DecodeI64RegisterClass(MI, sy, Address, Decoder);
598 if (status != MCDisassembler::Success)
599 return status;
600 } else {
601 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
602 }
603
604 // Decode MEMri.
605 return DecodeAS(MI, insn, Address, Decoder);
606 }
607
DecodeBranchConditionAlways(MCInst & MI,uint64_t insn,uint64_t Address,const void * Decoder)608 static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn,
609 uint64_t Address,
610 const void *Decoder) {
611 // Decode MEMri.
612 return DecodeAS(MI, insn, Address, Decoder);
613 }
614