1 /*
2 * Simulator of microcontrollers (uc320.cc)
3 *
4 * Copyright (C) 2018,18 whitequark
5 *
6 * To contact author send email to whitequark@whitequark.org
7 */
8
9 /* This file is part of microcontroller simulator: ucsim.
10
11 UCSIM is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 UCSIM is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with UCSIM; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 02111-1307, USA. */
25 /*@1@*/
26
27 #include "ddconfig.h"
28
29 #include <stdio.h>
30 #include <stdlib.h>
31 #include <ctype.h>
32 #include "i_string.h"
33
34 #include "glob.h"
35 #include "uc320cl.h"
36 #include "regs51.h"
37
38 struct timing_desc
39 {
40 u8_t opc_a;
41 u8_t opc_b;
42 bool mask;
43 int cycles;
44 };
45
46 static struct timing_desc uc320_timing_desc[] = {
47 { 0x00, 0x00, false, 1 }, /*inst_nop*/
48 { 0x1f, 0x01, true, 3 }, /*inst_ajmp_addr*/
49 { 0x02, 0x02, false, 4 }, /*inst_ljmp*/
50 { 0x03, 0x03, false, 1 }, /*inst_rr*/
51 { 0x04, 0x04, false, 1 }, /*inst_inc_a*/
52 { 0x05, 0x05, false, 2 }, /*inst_inc_addr*/
53 { 0x06, 0x07, false, 1 }, /*inst_inc_Sri*/
54 { 0x08, 0x0f, false, 1 }, /*inst_inc_rn*/
55 { 0x10, 0x10, false, 4 }, /*inst_jbc_bit_addr*/
56 { 0x1f, 0x11, true, 3 }, /*inst_acall_addr*/
57 { 0x12, 0x12, false, 4 }, /*inst_lcall*/
58 { 0x13, 0x13, false, 1 }, /*inst_rrc*/
59 { 0x14, 0x14, false, 1 }, /*inst_dec_a*/
60 { 0x15, 0x15, false, 2 }, /*inst_dec_addr*/
61 { 0x16, 0x17, false, 1 }, /*inst_dec_Sri*/
62 { 0x18, 0x1f, false, 1 }, /*inst_dec_rn*/
63 { 0x20, 0x20, false, 4 }, /*inst_jb_bit_addr*/
64 { 0x22, 0x22, false, 4 }, /*inst_ret*/
65 { 0x23, 0x23, false, 1 }, /*inst_rl*/
66 { 0x24, 0x24, false, 2 }, /*inst_add_a_Sdata*/
67 { 0x25, 0x25, false, 2 }, /*inst_add_a_addr*/
68 { 0x26, 0x27, false, 1 }, /*inst_add_a_Sri*/
69 { 0x28, 0x2f, false, 1 }, /*inst_add_a_rn*/
70 { 0x30, 0x30, false, 4 }, /*inst_jnb_bit_addr*/
71 { 0x32, 0x32, false, 4 }, /*inst_reti*/
72 { 0x33, 0x33, false, 1 }, /*inst_rlc*/
73 { 0x34, 0x34, false, 2 }, /*inst_addc_a_Sdata*/
74 { 0x35, 0x35, false, 2 }, /*inst_addc_a_addr*/
75 { 0x36, 0x37, false, 1 }, /*inst_addc_a_Sri*/
76 { 0x38, 0x3f, false, 1 }, /*inst_addc_a_rn*/
77 { 0x40, 0x40, false, 3 }, /*inst_jc_addr*/
78 { 0x42, 0x42, false, 2 }, /*inst_orl_addr_a*/
79 { 0x43, 0x43, false, 3 }, /*inst_orl_addr_Sdata*/
80 { 0x44, 0x44, false, 2 }, /*inst_orl_a_Sdata*/
81 { 0x45, 0x45, false, 2 }, /*inst_orl_a_addr*/
82 { 0x46, 0x47, false, 1 }, /*inst_orl_a_Sri*/
83 { 0x48, 0x4f, false, 1 }, /*inst_orl_a_rn*/
84 { 0x50, 0x50, false, 3 }, /*inst_jnc_addr*/
85 { 0x52, 0x52, false, 2 }, /*inst_anl_addr_a*/
86 { 0x53, 0x53, false, 3 }, /*inst_anl_addr_Sdata*/
87 { 0x54, 0x54, false, 2 }, /*inst_anl_a_Sdata*/
88 { 0x55, 0x55, false, 2 }, /*inst_anl_a_addr*/
89 { 0x56, 0x57, false, 1 }, /*inst_anl_a_Sri*/
90 { 0x58, 0x5f, false, 1 }, /*inst_anl_a_rn*/
91 { 0x60, 0x60, false, 3 }, /*inst_jz_addr*/
92 { 0x62, 0x62, false, 2 }, /*inst_xrl_addr_a*/
93 { 0x63, 0x63, false, 3 }, /*inst_xrl_addr_Sdata*/
94 { 0x64, 0x64, false, 2 }, /*inst_xrl_a_Sdata*/
95 { 0x65, 0x65, false, 2 }, /*inst_xrl_a_addr*/
96 { 0x66, 0x67, false, 1 }, /*inst_xrl_a_Sri*/
97 { 0x68, 0x6f, false, 1 }, /*inst_xrl_a_rn*/
98 { 0x70, 0x70, false, 3 }, /*inst_jnz_addr*/
99 { 0x72, 0x72, false, 2 }, /*inst_orl_c_bit*/
100 { 0x73, 0x73, false, 3 }, /*inst_jmp_Sa_dptr*/
101 { 0x74, 0x74, false, 2 }, /*inst_mov_a_Sdata*/
102 { 0x75, 0x75, false, 3 }, /*inst_mov_addr_Sdata*/
103 { 0x76, 0x77, false, 2 }, /*inst_mov_Sri_Sdata*/
104 { 0x78, 0x7f, false, 2 }, /*inst_mov_rn_Sdata*/
105 { 0x80, 0x80, false, 3 }, /*inst_sjmp*/
106 { 0x82, 0x82, false, 2 }, /*inst_anl_c_bit*/
107 { 0x83, 0x83, false, 3 }, /*inst_movc_a_Sa_pc*/
108 { 0x84, 0x84, false, 5 }, /*inst_div_ab*/
109 { 0x85, 0x85, false, 3 }, /*inst_mov_addr_addr*/
110 { 0x86, 0x87, false, 2 }, /*inst_mov_addr_Sri*/
111 { 0x88, 0x8f, false, 2 }, /*inst_mov_addr_rn*/
112 { 0x90, 0x90, false, 3 }, /*inst_mov_dptr_Sdata*/
113 { 0x92, 0x92, false, 2 }, /*inst_mov_bit_c*/
114 { 0x93, 0x93, false, 3 }, /*inst_movc_a_Sa_dptr*/
115 { 0x94, 0x94, false, 2 }, /*inst_subb_a_Sdata*/
116 { 0x95, 0x95, false, 2 }, /*inst_subb_a_addr*/
117 { 0x96, 0x97, false, 1 }, /*inst_subb_a_Sri*/
118 { 0x98, 0x9f, false, 1 }, /*inst_subb_a_rn*/
119 { 0xa0, 0xa0, false, 2 }, /*inst_orl_c_Sbit*/
120 { 0xa2, 0xa2, false, 2 }, /*inst_mov_c_bit*/
121 { 0xa3, 0xa3, false, 3 }, /*inst_inc_dptr*/
122 { 0xa4, 0xa4, false, 5 }, /*inst_mul_ab*/
123 { 0xa6, 0xa7, false, 2 }, /*inst_mov_Sri_addr*/
124 { 0xa8, 0xaf, false, 2 }, /*inst_mov_rn_addr*/
125 { 0xb0, 0xb0, false, 2 }, /*inst_anl_c_Sbit*/
126 { 0xb2, 0xb2, false, 2 }, /*inst_cpl_bit*/
127 { 0xb3, 0xb3, false, 1 }, /*inst_cpl_c*/
128 { 0xb4, 0xb4, false, 4 }, /*inst_cjne_a_Sdata_addr*/
129 { 0xb5, 0xb5, false, 4 }, /*inst_cjne_a_addr_addr*/
130 { 0xb6, 0xb7, false, 4 }, /*inst_cjne_Sri_Sdata_addr*/
131 { 0xb8, 0xbf, false, 4 }, /*inst_cjne_rn_Sdata_addr*/
132 { 0xc0, 0xc0, false, 2 }, /*inst_push*/
133 { 0xc2, 0xc2, false, 2 }, /*inst_clr_bit*/
134 { 0xc3, 0xc3, false, 1 }, /*inst_clr_c*/
135 { 0xc4, 0xc4, false, 1 }, /*inst_swap*/
136 { 0xc5, 0xc5, false, 2 }, /*inst_xch_a_addr*/
137 { 0xc6, 0xc7, false, 1 }, /*inst_xch_a_Sri*/
138 { 0xc8, 0xcf, false, 1 }, /*inst_xch_a_rn*/
139 { 0xd0, 0xd0, false, 2 }, /*inst_pop*/
140 { 0xd2, 0xd2, false, 2 }, /*inst_setb_bit*/
141 { 0xd3, 0xd3, false, 1 }, /*inst_setb_c*/
142 { 0xd4, 0xd4, false, 1 }, /*inst_da_a*/
143 { 0xd5, 0xd5, false, 4 }, /*inst_djnz_addr_addr*/
144 { 0xd6, 0xd7, false, 1 }, /*inst_xchd_a_Sri*/
145 { 0xd8, 0xdf, false, 3 }, /*inst_djnz_rn_addr*/
146 { 0xe0, 0xe0, false, 2 }, /*inst_movx_a_Sdptr*/
147 { 0xe2, 0xe3, false, 2 }, /*inst_movx_a_Sri*/
148 { 0xe4, 0xe4, false, 1 }, /*inst_clr_a*/
149 { 0xe5, 0xe5, false, 2 }, /*inst_mov_a_addr*/
150 { 0xe6, 0xe7, false, 1 }, /*inst_mov_a_Sri*/
151 { 0xe8, 0xef, false, 1 }, /*inst_mov_a_rn*/
152 { 0xf0, 0xf0, false, 2 }, /*inst_movx_Sdptr_a*/
153 { 0xf2, 0xf3, false, 2 }, /*inst_movx_Sri_a*/
154 { 0xf4, 0xf4, false, 1 }, /*inst_cpl_a*/
155 { 0xf5, 0xf5, false, 2 }, /*inst_mov_addr_a*/
156 { 0xf6, 0xf7, false, 1 }, /*inst_mov_Sri_a*/
157 { 0xf8, 0xff, false, 1 }, /*inst_mov_rn_a*/
158 };
159
160 /*
161 * Unpacking the timing table for fast indexing
162 */
163
164 static int uc320_timing[0x100];
165
unpack_timing()166 static void unpack_timing()
167 {
168 static bool unpacked;
169 size_t i;
170
171 if (unpacked)
172 return;
173
174 for (i = 0; i < sizeof(uc320_timing_desc) / sizeof(uc320_timing_desc[0]); i++)
175 {
176 struct timing_desc *td = &uc320_timing_desc[i];
177 int opc;
178
179 for (opc = 0; opc < 0x100; opc++)
180 {
181 if ((td->mask && ((opc & td->opc_a) == td->opc_b)) ||
182 (!td->mask && opc >= td->opc_a && opc <= td->opc_b))
183 uc320_timing[opc] = td->cycles;
184 }
185 }
186
187 unpacked = true;
188 }
189
190 /*
191 * Making an 320 CPU object
192 */
193
cl_uc320(struct cpu_entry * Itype,class cl_sim * asim)194 cl_uc320::cl_uc320 (struct cpu_entry *Itype, class cl_sim *asim):
195 cl_uc521 (Itype, asim)
196 {
197 unpack_timing();
198 }
199
200 /*
201 * Setting up SFR area to reset value
202 */
203
204 void
clear_sfr(void)205 cl_uc320::clear_sfr(void)
206 {
207 cl_uc521::clear_sfr();
208 sfr->write(CKCON, 0x01);
209 }
210
211 /*
212 * Execution
213 */
214
215 int
exec_inst(void)216 cl_uc320::exec_inst(void)
217 {
218 int res;
219 t_mem code;
220
221 instPC= PC;
222 pending_ticks= 0;
223 code= rom->read(PC);
224 res= cl_uc521::exec_inst();
225
226 if (res != resNOT_DONE)
227 tick(uc320_timing[code] - pending_ticks);
228
229 return(res);
230 }
231
232 int
tick(int cycles)233 cl_uc320::tick(int cycles)
234 {
235 pending_ticks += 1;
236 return(cl_uc521::tick(cycles));
237 }
238
239 int
tick_hw(int cycles)240 cl_uc320::tick_hw(int cycles)
241 {
242 return(cl_uc521::tick_hw(cycles*3));
243 }
244
245 /*
246 * 0xe0 1 24 MOVX A,@DPTR
247 *____________________________________________________________________________
248 *
249 */
250
251 int
instruction_e0(t_mem code)252 cl_uc320::instruction_e0/*inst_movx_a_Sdptr*/(t_mem/*uchar*/ code)
253 {
254 int res= cl_uc521::instruction_e0(code);
255
256 u8_t stretch= sfr->read(CKCON) & 0x7;
257 cl_uc521::tick(stretch);
258
259 return(res);
260 }
261
262
263 /*
264 * 0xe2-0xe3 1 24 MOVX A,@Ri
265 *____________________________________________________________________________
266 *
267 */
268
269 int
instruction_e2(t_mem code)270 cl_uc320::instruction_e2/*inst_movx_a_Sri*/(t_mem/*uchar*/ code)
271 {
272 int res= cl_uc521::instruction_e2(code);
273
274 u8_t stretch= sfr->read(CKCON) & 0x7;
275 cl_uc521::tick(stretch);
276
277 return(res);
278 }
279
280
281 /*
282 * 0xf0 1 24 MOVX @DPTR,A
283 *____________________________________________________________________________
284 *
285 */
286
287 int
instruction_f0(t_mem code)288 cl_uc320::instruction_f0/*inst_movx_Sdptr_a*/(t_mem/*uchar*/ code)
289 {
290 int res= cl_uc521::instruction_f0(code);
291
292 u8_t stretch= sfr->read(CKCON) & 0x7;
293 cl_uc521::tick(stretch);
294
295 return(res);
296 }
297
298
299 /*
300 * 0xf2-0xf3 1 24 MOVX @Ri,A
301 *____________________________________________________________________________
302 *
303 */
304
305 int
instruction_f2(t_mem code)306 cl_uc320::instruction_f2/*inst_movx_Sri_a*/(t_mem/*uchar*/ code)
307 {
308 int res= cl_uc521::instruction_f2(code);
309
310 u8_t stretch= sfr->read(CKCON) & 0x7;
311 cl_uc521::tick(stretch);
312
313 return(res);
314 }
315