1 /*
2 * Simulator of microcontrollers (uc390.cc)
3 *
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
5 *
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
7 *
8 * uc390.cc - module created by Karl Bongers 2001, karl@turbobit.com
9 */
10
11 /* This file is part of microcontroller simulator: ucsim.
12
13 UCSIM is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 UCSIM is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with UCSIM; see the file COPYING. If not, write to the Free
25 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 02111-1307, USA. */
27 /*@1@*/
28
29 // Bernhard's ToDo list:
30
31 // - implement math accelerator
32 // - consider ACON bits
33 // - buy some memory to run s51 with 2*4 Meg ROM/XRAM
34
35 // strcpy (mem(MEM_ROM) ->addr_format, "0x%06x");
36 // strcpy (mem(MEM_XRAM)->addr_format, "0x%06x");
37
38 #include "ddconfig.h"
39
40 #include <stdio.h>
41 #include <stdlib.h>
42 #include <ctype.h>
43 #include "i_string.h"
44
45 #include "glob.h"
46 #include "uc390cl.h"
47 #include "regs51.h"
48 #include "uc390hwcl.h"
49
50
51 #include "uc52cl.h"
52 #include "regs51.h"
53 #include "timer2cl.h"
54
55 /*
56 * Names of instructions
57 */
58
59 struct dis_entry disass_390f[] = {
60 { 0x00, 0xff, ' ', 1, "NOP"},
61 { 0x01, 0xff, 'A', 3, "AJMP %A"},
62 { 0x02, 0xff, 'L', 4, "LJMP %l"},
63 { 0x03, 0xff, ' ', 1, "RR A"},
64 { 0x04, 0xff, ' ', 1, "INC A"},
65 { 0x05, 0xff, ' ', 2, "INC %a"},
66 { 0x06, 0xff, ' ', 1, "INC @R0"},
67 { 0x07, 0xff, ' ', 1, "INC @R1"},
68 { 0x08, 0xff, ' ', 1, "INC R0"},
69 { 0x09, 0xff, ' ', 1, "INC R1"},
70 { 0x0a, 0xff, ' ', 1, "INC R2"},
71 { 0x0b, 0xff, ' ', 1, "INC R3"},
72 { 0x0c, 0xff, ' ', 1, "INC R4"},
73 { 0x0d, 0xff, ' ', 1, "INC R5"},
74 { 0x0e, 0xff, ' ', 1, "INC R6"},
75 { 0x0f, 0xff, ' ', 1, "INC R7"},
76 { 0x10, 0xff, 'R', 3, "JBC %b,%R"},
77 { 0x11, 0xff, 'a', 3, "ACALL %A"},
78 { 0x12, 0xff, 'l', 4, "LCALL %l"},
79 { 0x13, 0xff, ' ', 1, "RRC A"},
80 { 0x14, 0xff, ' ', 1, "DEC A"},
81 { 0x15, 0xff, ' ', 2, "DEC %a"},
82 { 0x16, 0xff, ' ', 1, "DEC @R0"},
83 { 0x17, 0xff, ' ', 1, "DEC @R1"},
84 { 0x18, 0xff, ' ', 1, "DEC R0"},
85 { 0x19, 0xff, ' ', 1, "DEC R1"},
86 { 0x1a, 0xff, ' ', 1, "DEC R2"},
87 { 0x1b, 0xff, ' ', 1, "DEC R3"},
88 { 0x1c, 0xff, ' ', 1, "DEC R4"},
89 { 0x1d, 0xff, ' ', 1, "DEC R5"},
90 { 0x1e, 0xff, ' ', 1, "DEC R6"},
91 { 0x1f, 0xff, ' ', 1, "DEC R7"},
92 { 0x20, 0xff, 'R', 3, "JB %b,%R"},
93 { 0x21, 0xff, 'A', 3, "AJMP %A"},
94 { 0x22, 0xff, '_', 1, "RET"},
95 { 0x23, 0xff, ' ', 1, "RL A"},
96 { 0x24, 0xff, ' ', 2, "ADD A,#%d"},
97 { 0x25, 0xff, ' ', 2, "ADD A,%a"},
98 { 0x26, 0xff, ' ', 1, "ADD A,@R0"},
99 { 0x27, 0xff, ' ', 1, "ADD A,@R1"},
100 { 0x28, 0xff, ' ', 1, "ADD A,R0"},
101 { 0x29, 0xff, ' ', 1, "ADD A,R1"},
102 { 0x2a, 0xff, ' ', 1, "ADD A,R2"},
103 { 0x2b, 0xff, ' ', 1, "ADD A,R3"},
104 { 0x2c, 0xff, ' ', 1, "ADD A,R4"},
105 { 0x2d, 0xff, ' ', 1, "ADD A,R5"},
106 { 0x2e, 0xff, ' ', 1, "ADD A,R6"},
107 { 0x2f, 0xff, ' ', 1, "ADD A,R7"},
108 { 0x30, 0xff, 'R', 3, "JNB %b,%R"},
109 { 0x31, 0xff, 'a', 3, "ACALL %A"},
110 { 0x32, 0xff, '_', 1, "RETI"},
111 { 0x33, 0xff, ' ', 1, "RLC A"},
112 { 0x34, 0xff, ' ', 2, "ADDC A,#%d"},
113 { 0x35, 0xff, ' ', 2, "ADDC A,%a"},
114 { 0x36, 0xff, ' ', 1, "ADDC A,@R0"},
115 { 0x37, 0xff, ' ', 1, "ADDC A,@R1"},
116 { 0x38, 0xff, ' ', 1, "ADDC A,R0"},
117 { 0x39, 0xff, ' ', 1, "ADDC A,R1"},
118 { 0x3a, 0xff, ' ', 1, "ADDC A,R2"},
119 { 0x3b, 0xff, ' ', 1, "ADDC A,R3"},
120 { 0x3c, 0xff, ' ', 1, "ADDC A,R4"},
121 { 0x3d, 0xff, ' ', 1, "ADDC A,R5"},
122 { 0x3e, 0xff, ' ', 1, "ADDC A,R6"},
123 { 0x3f, 0xff, ' ', 1, "ADDC A,R7"},
124 { 0x40, 0xff, 'r', 2, "JC %r"},
125 { 0x41, 0xff, 'A', 3, "AJMP %A"},
126 { 0x42, 0xff, ' ', 2, "ORL %a,A"},
127 { 0x43, 0xff, ' ', 3, "ORL %a,#%D"},
128 { 0x44, 0xff, ' ', 2, "ORL A,#%d"},
129 { 0x45, 0xff, ' ', 2, "ORL A,%a"},
130 { 0x46, 0xff, ' ', 1, "ORL A,@R0"},
131 { 0x47, 0xff, ' ', 1, "ORL A,@R1"},
132 { 0x48, 0xff, ' ', 1, "ORL A,R0"},
133 { 0x49, 0xff, ' ', 1, "ORL A,R1"},
134 { 0x4a, 0xff, ' ', 1, "ORL A,R2"},
135 { 0x4b, 0xff, ' ', 1, "ORL A,R3"},
136 { 0x4c, 0xff, ' ', 1, "ORL A,R4"},
137 { 0x4d, 0xff, ' ', 1, "ORL A,R5"},
138 { 0x4e, 0xff, ' ', 1, "ORL A,R6"},
139 { 0x4f, 0xff, ' ', 1, "ORL A,R7"},
140 { 0x50, 0xff, 'r', 2, "JNC %r"},
141 { 0x51, 0xff, 'a', 3, "ACALL %A"},
142 { 0x52, 0xff, ' ', 2, "ANL %a,A"},
143 { 0x53, 0xff, ' ', 3, "ANL %a,#%D"},
144 { 0x54, 0xff, ' ', 2, "ANL A,#%d"},
145 { 0x55, 0xff, ' ', 2, "ANL A,%a"},
146 { 0x56, 0xff, ' ', 1, "ANL A,@R0"},
147 { 0x57, 0xff, ' ', 1, "ANL A,@R1"},
148 { 0x58, 0xff, ' ', 1, "ANL A,R0"},
149 { 0x59, 0xff, ' ', 1, "ANL A,R1"},
150 { 0x5a, 0xff, ' ', 1, "ANL A,R2"},
151 { 0x5b, 0xff, ' ', 1, "ANL A,R3"},
152 { 0x5c, 0xff, ' ', 1, "ANL A,R4"},
153 { 0x5d, 0xff, ' ', 1, "ANL A,R5"},
154 { 0x5e, 0xff, ' ', 1, "ANL A,R6"},
155 { 0x5f, 0xff, ' ', 1, "ANL A,R7"},
156 { 0x60, 0xff, 'r', 2, "JZ %r"},
157 { 0x61, 0xff, 'A', 3, "AJMP %A"},
158 { 0x62, 0xff, ' ', 2, "XRL %a,A"},
159 { 0x63, 0xff, ' ', 3, "XRL %a,#%D"},
160 { 0x64, 0xff, ' ', 2, "XRL A,#%d"},
161 { 0x65, 0xff, ' ', 2, "XRL A,%a"},
162 { 0x66, 0xff, ' ', 1, "XRL A,@R0"},
163 { 0x67, 0xff, ' ', 1, "XRL A,@R1"},
164 { 0x68, 0xff, ' ', 1, "XRL A,R0"},
165 { 0x69, 0xff, ' ', 1, "XRL A,R1"},
166 { 0x6a, 0xff, ' ', 1, "XRL A,R2"},
167 { 0x6b, 0xff, ' ', 1, "XRL A,R3"},
168 { 0x6c, 0xff, ' ', 1, "XRL A,R4"},
169 { 0x6d, 0xff, ' ', 1, "XRL A,R5"},
170 { 0x6e, 0xff, ' ', 1, "XRL A,R6"},
171 { 0x6f, 0xff, ' ', 1, "XRL A,R7"},
172 { 0x70, 0xff, 'r', 2, "JNZ %r"},
173 { 0x71, 0xff, 'a', 3, "ACALL %A"},
174 { 0x72, 0xff, ' ', 2, "ORL C,%b"},
175 { 0x73, 0xff, '_', 1, "JMP @A+DPTR"},
176 { 0x74, 0xff, ' ', 2, "MOV A,#%d"},
177 { 0x75, 0xff, ' ', 3, "MOV %a,#%D"},
178 { 0x76, 0xff, ' ', 2, "MOV @R0,#%d"},
179 { 0x77, 0xff, ' ', 2, "MOV @R1,#%d"},
180 { 0x78, 0xff, ' ', 2, "MOV R0,#%d"},
181 { 0x79, 0xff, ' ', 2, "MOV R1,#%d"},
182 { 0x7a, 0xff, ' ', 2, "MOV R2,#%d"},
183 { 0x7b, 0xff, ' ', 2, "MOV R3,#%d"},
184 { 0x7c, 0xff, ' ', 2, "MOV R4,#%d"},
185 { 0x7d, 0xff, ' ', 2, "MOV R5,#%d"},
186 { 0x7e, 0xff, ' ', 2, "MOV R6,#%d"},
187 { 0x7f, 0xff, ' ', 2, "MOV R7,#%d"},
188 { 0x80, 0xff, 's', 2, "SJMP %r"},
189 { 0x81, 0xff, 'A', 3, "AJMP %A"},
190 { 0x82, 0xff, ' ', 2, "ANL C,%b"},
191 { 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"},
192 { 0x84, 0xff, ' ', 1, "DIV AB"},
193 { 0x85, 0xff, ' ', 3, "MOV %8,%a"},
194 { 0x86, 0xff, ' ', 2, "MOV %a,@R0"},
195 { 0x87, 0xff, ' ', 2, "MOV %a,@R1"},
196 { 0x88, 0xff, ' ', 2, "MOV %a,R0"},
197 { 0x89, 0xff, ' ', 2, "MOV %a,R1"},
198 { 0x8a, 0xff, ' ', 2, "MOV %a,R2"},
199 { 0x8b, 0xff, ' ', 2, "MOV %a,R3"},
200 { 0x8c, 0xff, ' ', 2, "MOV %a,R4"},
201 { 0x8d, 0xff, ' ', 2, "MOV %a,R5"},
202 { 0x8e, 0xff, ' ', 2, "MOV %a,R6"},
203 { 0x8f, 0xff, ' ', 2, "MOV %a,R7"},
204 { 0x90, 0xff, ' ', 4, "MOV DPTR,#%l"},
205 { 0x91, 0xff, 'a', 3, "ACALL %A"},
206 { 0x92, 0xff, ' ', 2, "MOV %b,C"},
207 { 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"},
208 { 0x94, 0xff, ' ', 2, "SUBB A,#%d"},
209 { 0x95, 0xff, ' ', 2, "SUBB A,%a"},
210 { 0x96, 0xff, ' ', 1, "SUBB A,@R0"},
211 { 0x97, 0xff, ' ', 1, "SUBB A,@R1"},
212 { 0x98, 0xff, ' ', 1, "SUBB A,R0"},
213 { 0x99, 0xff, ' ', 1, "SUBB A,R1"},
214 { 0x9a, 0xff, ' ', 1, "SUBB A,R2"},
215 { 0x9b, 0xff, ' ', 1, "SUBB A,R3"},
216 { 0x9c, 0xff, ' ', 1, "SUBB A,R4"},
217 { 0x9d, 0xff, ' ', 1, "SUBB A,R5"},
218 { 0x9e, 0xff, ' ', 1, "SUBB A,R6"},
219 { 0x9f, 0xff, ' ', 1, "SUBB A,R7"},
220 { 0xa0, 0xff, ' ', 2, "ORL C,/%b"},
221 { 0xa1, 0xff, 'A', 3, "AJMP %A"},
222 { 0xa2, 0xff, ' ', 2, "MOV C,%b"},
223 { 0xa3, 0xff, ' ', 1, "%i DPTR"},
224 { 0xa4, 0xff, ' ', 1, "MUL AB"},
225 { 0xa5, 0xff, '_', 1, "-"},
226 { 0xa6, 0xff, ' ', 2, "MOV @R0,%a"},
227 { 0xa7, 0xff, ' ', 2, "MOV @R1,%a"},
228 { 0xa8, 0xff, ' ', 2, "MOV R0,%a"},
229 { 0xa9, 0xff, ' ', 2, "MOV R1,%a"},
230 { 0xaa, 0xff, ' ', 2, "MOV R2,%a"},
231 { 0xab, 0xff, ' ', 2, "MOV R3,%a"},
232 { 0xac, 0xff, ' ', 2, "MOV R4,%a"},
233 { 0xad, 0xff, ' ', 2, "MOV R5,%a"},
234 { 0xae, 0xff, ' ', 2, "MOV R6,%a"},
235 { 0xaf, 0xff, ' ', 2, "MOV R7,%a"},
236 { 0xb0, 0xff, ' ', 2, "ANL C,/%b"},
237 { 0xb1, 0xff, 'a', 3, "ACALL %A"},
238 { 0xb2, 0xff, ' ', 2, "CPL %b"},
239 { 0xb3, 0xff, ' ', 1, "CPL C"},
240 { 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"},
241 { 0xb5, 0xff, 'R', 3, "CJNE A,%a,%R"},
242 { 0xb6, 0xff, 'R', 3, "CJNE @R0,#%d,%R"},
243 { 0xb7, 0xff, 'R', 3, "CJNE @R1,#%d,%R"},
244 { 0xb8, 0xff, 'R', 3, "CJNE R0,#%d,%R"},
245 { 0xb9, 0xff, 'R', 3, "CJNE R1,#%d,%R"},
246 { 0xba, 0xff, 'R', 3, "CJNE R2,#%d,%R"},
247 { 0xbb, 0xff, 'R', 3, "CJNE R3,#%d,%R"},
248 { 0xbc, 0xff, 'R', 3, "CJNE R4,#%d,%R"},
249 { 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"},
250 { 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"},
251 { 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"},
252 { 0xc0, 0xff, ' ', 2, "PUSH %a"},
253 { 0xc1, 0xff, 'A', 3, "AJMP %A"},
254 { 0xc2, 0xff, ' ', 2, "CLR %b"},
255 { 0xc3, 0xff, ' ', 1, "CLR C"},
256 { 0xc4, 0xff, ' ', 1, "SWAP A"},
257 { 0xc5, 0xff, ' ', 2, "XCH A,%a"},
258 { 0xc6, 0xff, ' ', 1, "XCH A,@R0"},
259 { 0xc7, 0xff, ' ', 1, "XCH A,@R1"},
260 { 0xc8, 0xff, ' ', 1, "XCH A,R0"},
261 { 0xc9, 0xff, ' ', 1, "XCH A,R1"},
262 { 0xca, 0xff, ' ', 1, "XCH A,R2"},
263 { 0xcb, 0xff, ' ', 1, "XCH A,R3"},
264 { 0xcc, 0xff, ' ', 1, "XCH A,R4"},
265 { 0xcd, 0xff, ' ', 1, "XCH A,R5"},
266 { 0xce, 0xff, ' ', 1, "XCH A,R6"},
267 { 0xcf, 0xff, ' ', 1, "XCH A,R7"},
268 { 0xd0, 0xff, ' ', 2, "POP %a"},
269 { 0xd1, 0xff, 'a', 3, "ACALL %A"},
270 { 0xd2, 0xff, ' ', 2, "SETB %b"},
271 { 0xd3, 0xff, ' ', 1, "SETB C"},
272 { 0xd4, 0xff, ' ', 1, "DA A"},
273 { 0xd5, 0xff, 'R', 3, "DJNZ %a,%R"},
274 { 0xd6, 0xff, ' ', 1, "XCHD A,@R0"},
275 { 0xd7, 0xff, ' ', 1, "XCHD A,@R1"},
276 { 0xd8, 0xff, 'r', 2, "DJNZ R0,%r"},
277 { 0xd9, 0xff, 'r', 2, "DJNZ R1,%r"},
278 { 0xda, 0xff, 'r', 2, "DJNZ R2,%r"},
279 { 0xdb, 0xff, 'r', 2, "DJNZ R3,%r"},
280 { 0xdc, 0xff, 'r', 2, "DJNZ R4,%r"},
281 { 0xdd, 0xff, 'r', 2, "DJNZ R5,%r"},
282 { 0xde, 0xff, 'r', 2, "DJNZ R6,%r"},
283 { 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"},
284 { 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"},
285 { 0xe1, 0xff, 'A', 3, "AJMP %A"},
286 { 0xe2, 0xff, ' ', 1, "MOVX A,@R0"},
287 { 0xe3, 0xff, ' ', 1, "MOVX A,@R1"},
288 { 0xe4, 0xff, ' ', 1, "CLR A"},
289 { 0xe5, 0xff, ' ', 2, "MOV A,%a"},
290 { 0xe6, 0xff, ' ', 1, "MOV A,@R0"},
291 { 0xe7, 0xff, ' ', 1, "MOV A,@R1"},
292 { 0xe8, 0xff, ' ', 1, "MOV A,R0"},
293 { 0xe9, 0xff, ' ', 1, "MOV A,R1"},
294 { 0xea, 0xff, ' ', 1, "MOV A,R2"},
295 { 0xeb, 0xff, ' ', 1, "MOV A,R3"},
296 { 0xec, 0xff, ' ', 1, "MOV A,R4"},
297 { 0xed, 0xff, ' ', 1, "MOV A,R5"},
298 { 0xee, 0xff, ' ', 1, "MOV A,R6"},
299 { 0xef, 0xff, ' ', 1, "MOV A,R7"},
300 { 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"},
301 { 0xf1, 0xff, 'a', 3, "ACALL %A"},
302 { 0xf2, 0xff, ' ', 1, "MOVX @R0,A"},
303 { 0xf3, 0xff, ' ', 1, "MOVX @R1,A"},
304 { 0xf4, 0xff, ' ', 1, "CPL A"},
305 { 0xf5, 0xff, ' ', 2, "MOV %a,A"},
306 { 0xf6, 0xff, ' ', 1, "MOV @R0,A"},
307 { 0xf7, 0xff, ' ', 1, "MOV @R1,A"},
308 { 0xf8, 0xff, ' ', 1, "MOV R0,A"},
309 { 0xf9, 0xff, ' ', 1, "MOV R1,A"},
310 { 0xfa, 0xff, ' ', 1, "MOV R2,A"},
311 { 0xfb, 0xff, ' ', 1, "MOV R3,A"},
312 { 0xfc, 0xff, ' ', 1, "MOV R4,A"},
313 { 0xfd, 0xff, ' ', 1, "MOV R5,A"},
314 { 0xfe, 0xff, ' ', 1, "MOV R6,A"},
315 { 0xff, 0xff, ' ', 1, "MOV R7,A"},
316 { 0, 0, 0, 0, NULL }
317 };
318
319 /*
320 * Making an 390 CPU object
321 */
322
cl_uc390(struct cpu_entry * Itype,class cl_sim * asim)323 cl_uc390::cl_uc390 (struct cpu_entry *Itype, class cl_sim *asim):
324 cl_uc52 (Itype, asim)
325 {
326 //flat24_flag= 0;
327 if (Itype->type == CPU_DS390F)
328 {
329 printf ("24-bit flat mode, warning: lots of sfr-functions not implemented!\n");
330 //flat24_flag = 1;
331 }
332 // todo: add interrupt sources
333 }
334
335 void
mk_hw_elements(void)336 cl_uc390::mk_hw_elements (void)
337 {
338 class cl_hw *h;
339
340 cl_uc52::mk_hw_elements();
341 add_hw(h = new cl_uc390_hw (this));
342 h->init();
343 }
344
345 void
make_memories(void)346 cl_uc390::make_memories(void)
347 {
348 class cl_address_decoder *ad;
349
350 make_address_spaces();
351 dptr= 0;
352 make_chips();
353
354 acc= sfr->get_cell(ACC);
355 psw= sfr->get_cell(PSW);
356
357 decode_regs();
358 decode_rom();
359 decode_iram();
360 decode_sfr();
361 decode_xram();
362 decode_bits();
363 decode_dptr();
364
365 ad= new cl_address_decoder(ixram, ixram_chip, 0, 0xfff, 0);
366 ad->init();
367 ixram->decoders->add(ad);
368 ad->activate(0);
369 }
370
371 void
make_address_spaces(void)372 cl_uc390::make_address_spaces(void)
373 {
374 rom= new cl_address_space("rom", 0, 0x20000, 8);
375 rom->init();
376 address_spaces->add(rom);
377
378 iram= new cl_address_space("iram", 0, 0x100, 8);
379 iram->init();
380 address_spaces->add(iram);
381
382 sfr= new cl_address_space("sfr", 0x80, 0x80, 8);
383 sfr->init();
384 address_spaces->add(sfr);
385
386 xram= new cl_address_space("xram", 0, 0x100000+128, 8);
387 xram->init();
388 address_spaces->add(xram);
389
390 ixram= new cl_address_space("ixram", 0, 0x1000, 8);
391 ixram->init();
392 address_spaces->add(ixram);
393
394 regs= new cl_address_space("regs", 0, 8, 8);
395 regs->init();
396 address_spaces->add(regs);
397
398 bits= new cl_address_space("bits", 0, 0x100, 1);
399 bits->init();
400 address_spaces->add(bits);
401 }
402
403 void
make_chips(void)404 cl_uc390::make_chips(void)
405 {
406 rom_chip= new cl_memory_chip("rom_chip", 0x20000, 8, 0xff);
407 rom_chip->init();
408 memchips->add(rom_chip);
409
410 iram_chip= new cl_memory_chip("iram_chip", 0x100, 8, 0);
411 iram_chip->init();
412 memchips->add(iram_chip);
413
414 xram_chip= new cl_memory_chip("xram_chip", 0x100000+128, 8, 0);
415 xram_chip->init();
416 memchips->add(xram_chip);
417
418 ixram_chip= new cl_memory_chip("ixram_chip", 0x1000, 8);
419 ixram_chip->init();
420 memchips->add(ixram_chip);
421
422 sfr_chip= new cl_memory_chip("sfr_chip", 0x80, 8, 0);
423 sfr_chip->init();
424 memchips->add(sfr_chip);
425 }
426
427 void
decode_rom(void)428 cl_uc390::decode_rom(void)
429 {
430 class cl_address_decoder *ad;
431 ad= new cl_address_decoder(rom, rom_chip, 0, 0x1ffff, 0);
432 ad->init();
433 rom->decoders->add(ad);
434 ad->activate(0);
435 }
436
437 void
decode_xram(void)438 cl_uc390::decode_xram(void)
439 {
440 class cl_address_decoder *ad;
441
442 ad= new cl_address_decoder(xram, xram_chip, 0, 0x10007f, 0);
443 ad->init();
444 xram->decoders->add(ad);
445 ad->activate(0);
446 }
447
448 void
decode_dptr(void)449 cl_uc390::decode_dptr(void)
450 {
451 cl_var *v;
452 vars->add(v= new cl_var(chars("dpl"), sfr, 0x82, ""));
453 v->init();
454 vars->add(v= new cl_var(chars("DPL"), sfr, 0x82, ""));
455 v->init();
456 vars->add(v= new cl_var(chars("dph"), sfr, 0x83, ""));
457 v->init();
458 vars->add(v= new cl_var(chars("DPH"), sfr, 0x83, ""));
459 v->init();
460 }
461
462
463 /*
464 * Setting up SFR area to reset value
465 */
466
467 void
clear_sfr(void)468 cl_uc390::clear_sfr(void)
469 {
470 cl_uc52::clear_sfr();
471 /* SFR value */
472 sfr->write(0x80, 0xff); /* P4 */
473 sfr->write(0x81, 0x07); /* SP */
474 sfr->write(0x86, 0x04); /* DPS */
475 sfr->write(0x90, 0xff); /* P1 */
476 sfr->write(0x92, 0xbf); /* P4CNT */
477 sfr->write(0x9b, 0xfc); /* ESP */
478 if (type->type == CPU_DS390F/*flat24_flag*/)
479 {
480 sfr->/*write*/set(ACON, 0xfa); /* ACON; AM1 set: 24-bit flat */
481 //printf("ACON inited to 0xfa, 24 bit flat mode!\n");
482 //printf("CPU type=%d (%x) flag24=%d\n", type, type, flat24_flag);
483 }
484 else
485 sfr->/*write*/set(ACON, 0xf8); /* ACON */
486 sfr->write(0xa0, 0xff); /* P2 */
487 sfr->write(0xa1, 0xff); /* P5 */
488 sfr->write(0xa3, 0x09); /* COC */
489 sfr->write(0xb0, 0xff); /* P3 */
490 sfr->write(0xb8, 0x80); /* IP */
491 sfr->write(0xc5, 0x10); /* STATUS */
492 sfr->write(0xc6, 0x10); /* MCON */
493 sfr->write(0xc7, 0xff); /* TA */
494 sfr->write(0xc9, 0xe4); /* T2MOD */
495 sfr->write(0xd2, 0x2f); /* MCNT1 */
496 sfr->write(0xe3, 0x09); /* C1C */
497 }
498
499
500 t_mem
read_mem(char * id,t_addr addr)501 cl_uc390::read_mem(char *id/*enum mem_class type*/, t_addr addr)
502 {
503
504 if (strcmp(/*type*/id,/* == */MEM_XRAM_ID)==0 &&
505 addr >= 0x400000 &&
506 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
507 {
508 addr -= 0x400000;
509 id/*type*/ = MEM_IXRAM_ID;
510 }
511 return cl_51core::read_mem(id/*type*/, addr); /* 24 bit */
512 }
513
514 t_mem
get_mem(char * id,t_addr addr)515 cl_uc390::get_mem (char *id/*enum mem_class type*/, t_addr addr)
516 {
517 if (strcmp(/*type*/id/* == */,MEM_XRAM_ID)==0 &&
518 addr >= 0x400000 &&
519 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
520 {
521 addr -= 0x400000;
522 /*type*/id = MEM_IXRAM_ID;
523 }
524 return cl_51core::get_mem (/*type*/id, addr);
525 }
526
527 void
write_mem(char * id,t_addr addr,t_mem val)528 cl_uc390::write_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val)
529 {
530 if (strcmp(/*type ==*/id, MEM_XRAM_ID)==0 &&
531 addr >= 0x400000 &&
532 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
533 {
534 addr -= 0x400000;
535 /*type*/id = MEM_IXRAM_ID;
536 }
537 cl_51core::write_mem (/*type*/id, addr, val);
538 }
539
540 void
set_mem(char * id,t_addr addr,t_mem val)541 cl_uc390::set_mem (/*enum mem_class type*/char *id, t_addr addr, t_mem val)
542 {
543 if (/*type == */strcmp(id,MEM_XRAM_ID)==0 &&
544 addr >= 0x400000 &&
545 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
546 {
547 addr -= 0x400000;
548 /*type*/id = MEM_IXRAM_ID;
549 }
550 cl_51core::set_mem (id/*type*/, addr, val);
551 }
552
553 /*
554 *____________________________________________________________________________
555 */
556
557 void
push_byte(t_mem uc)558 cl_uc390::push_byte (t_mem uc)
559 {
560 t_addr sp;
561
562 sp = sfr->wadd (SP, 1);
563 if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
564 {
565 if (sp == 0) /* overflow SP */
566 sfr->wadd (R51_ESP, 1);
567 sp += (sfr->read (R51_ESP) & 0x3) * 256;
568 write_mem (MEM_IXRAM_ID, sp, uc); // fixme
569 }
570 else
571 {
572 class cl_memory_cell *stck;
573
574 stck = iram->get_cell (sp);
575 stck->write (uc);
576 }
577 }
578
579 t_mem
pop_byte(void)580 cl_uc390::pop_byte (void)
581 {
582 t_mem temp;
583 t_addr sp;
584
585 if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
586 {
587 sp = sfr->read (SP);
588 sp += (sfr->read (R51_ESP) & 0x3) * 256;
589 temp = read_mem (MEM_IXRAM_ID, sp); // fixme
590 sp = sfr->wadd (SP, -1);
591 if (sp == 0xff) /* underflow SP */
592 sfr->wadd (R51_ESP, -1);
593 return temp;
594 }
595 else
596 {
597 class cl_memory_cell *stck;
598
599 stck = iram->get_cell (sfr->get (SP));
600 temp = stck->read();
601 sp = sfr->wadd (SP, -1);
602 return temp;
603 }
604 }
605
606 /*
607 * 0xa3 1 24 INC DPTR
608 *____________________________________________________________________________
609 *
610 */
611
612 int
instruction_a3(t_mem code)613 cl_uc390::instruction_a3/*inst_inc_dptr*/ (t_mem/*uchar*/ code)
614 {
615 ulong dptr;
616
617 uchar pl, ph, px, dps, dec;
618
619 dps = sfr->get (DPS);
620 if (dps & 0x01)
621 {
622 pl = DPL1;
623 ph = DPH1;
624 px = DPX1;
625 dec = 0x80;
626 }
627 else
628 {
629 pl = DPL;
630 ph = DPH;
631 px = DPX;
632 dec = 0x040;
633 }
634
635 dptr = sfr->read (ph) * 256 + sfr->read (pl);
636 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
637 dptr += sfr->read (px) *256*256;
638 if (dps & dec) /* decr set */
639 dptr--;
640 else
641 dptr++;
642
643 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
644 sfr->write (px, (dptr >> 16) & 0xff);
645 sfr->write (ph, (dptr >> 8) & 0xff);
646 sfr->write (pl, dptr & 0xff);
647
648 if (dps & 0x20) /* auto-switch dptr */
649 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
650 tick (1);
651 return resGO;
652 }
653
654 /*
655 * 0x73 1 24 JMP @A+DPTR
656 *____________________________________________________________________________
657 *
658 */
659
660 int
instruction_73(t_mem code)661 cl_uc390::instruction_73/*inst_jmp_Sa_dptr*/ (t_mem/*uchar*/ code)
662 {
663 uchar pl, ph, px, dps;
664
665 dps = sfr->get (DPS);
666 if (dps & 0x01)
667 {
668 pl = DPL1;
669 ph = DPH1;
670 px = DPX1;
671 }
672 else
673 {
674 pl = DPL;
675 ph = DPH;
676 px = DPX;
677 }
678
679 PC = rom->validate_address(sfr->read (ph) * 256 + sfr->read (pl) +
680 acc->read());
681 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
682 PC += sfr->read (px) * 256*256;
683
684 tick (1);
685 return resGO;
686 }
687
688 /*
689 * 0x90 3 24 MOV DPTR,#data
690 *____________________________________________________________________________
691 *
692 */
693
694 int
instruction_90(t_mem code)695 cl_uc390::instruction_90/*inst_mov_dptr_Sdata*/ (t_mem/*uchar*/ code)
696 {
697 uchar pl, ph, px, dps;
698
699 dps = sfr->get (DPS);
700 if (dps & 0x01)
701 {
702 pl = DPL1;
703 ph = DPH1;
704 px = DPX1;
705 }
706 else
707 {
708 pl = DPL;
709 ph = DPH;
710 px = DPX;
711 }
712
713 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
714 sfr->write (px, fetch ());
715 sfr->write (ph, fetch ());
716 sfr->write (pl, fetch ());
717
718 if (dps & 0x20) /* auto-switch dptr */
719 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
720
721 tick (1);
722 return resGO;
723 }
724
725
726 /*
727 * 0x93 1 24 MOVC A,@A+DPTR
728 *____________________________________________________________________________
729 *
730 */
731
732 int
instruction_93(t_mem code)733 cl_uc390::instruction_93/*inst_movc_a_Sa_dptr*/ (t_mem/*uchar*/ code)
734 {
735 uchar pl, ph, px, dps;
736
737 dps = sfr->get (DPS);
738 if (dps & 0x01)
739 {
740 pl = DPL1;
741 ph = DPH1;
742 px = DPX1;
743 }
744 else
745 {
746 pl = DPL;
747 ph = DPH;
748 px = DPX;
749 }
750
751 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
752 acc->write (rom->read ((sfr->read (px) * 256*256 +
753 sfr->read (ph) * 256 + sfr->read (pl) +
754 acc->read())));
755 else
756 acc->write (rom->read ((sfr->read (ph) * 256 + sfr->read (pl) +
757 acc->read())));
758
759 if (dps & 0x20) /* auto-switch dptr */
760 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
761
762 tick (1);
763 return resGO;
764 }
765
766 /*
767 * 0xc0 2 24 PUSH addr
768 *____________________________________________________________________________
769 *
770 */
771
772 int
instruction_c0(t_mem code)773 cl_uc390::instruction_c0/*inst_push*/ (t_mem/*uchar*/ code)
774 {
775 class cl_memory_cell *cell;
776
777 cell = get_direct(fetch());
778 t_addr sp_before= sfr->get(SP);
779 t_mem data;
780 push_byte (data= cell->read());
781 class cl_stack_op *so=
782 new cl_stack_push(instPC, data, sp_before, sfr->get(SP));
783 so->init();
784 stack_write(so);
785 tick (1);
786 return resGO;
787 }
788
789
790 /*
791 * 0xd0 2 24 POP addr
792 *____________________________________________________________________________
793 *
794 */
795
796 int
instruction_d0(t_mem code)797 cl_uc390::instruction_d0/*inst_pop*/ (t_mem/*uchar*/ code)
798 {
799 class cl_memory_cell *cell;
800
801 t_addr sp_before= sfr->get(SP);
802 t_mem data;
803 cell = get_direct (fetch());
804 cell->write (data= pop_byte());
805 class cl_stack_op *so=
806 new cl_stack_pop(instPC, data, sp_before, sfr->get(SP));
807 so->init();
808 stack_read(so);
809 tick (1);
810 return resGO;
811 }
812
813
814 /*
815 * 0xe0 1 24 MOVX A,@DPTR
816 *____________________________________________________________________________
817 *
818 */
819
820 int
instruction_e0(t_mem code)821 cl_uc390::instruction_e0/*inst_movx_a_Sdptr*/ (t_mem/*uchar*/ code)
822 {
823 uchar pl, ph, px, dps;
824
825 dps = sfr->get (DPS);
826 if (dps & 0x01)
827 {
828 pl = DPL1;
829 ph = DPH1;
830 px = DPX1;
831 }
832 else
833 {
834 pl = DPL;
835 ph = DPH;
836 px = DPX;
837 }
838
839 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
840 acc->write (read_mem (MEM_XRAM_ID,
841 sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl)));
842 else
843 acc->write (read_mem (MEM_XRAM_ID,
844 sfr->read (ph) * 256 + sfr->read (pl)));
845
846 if (dps & 0x20) /* auto-switch dptr */
847 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
848
849 tick (1);
850 return resGO;
851 }
852
853 /*
854 * 0xf0 1 24 MOVX @DPTR,A
855 *____________________________________________________________________________
856 *
857 */
858
859 int
instruction_f0(t_mem code)860 cl_uc390::instruction_f0/*inst_movx_Sdptr_a*/ (t_mem/*uchar*/ code)
861 {
862 uchar pl, ph, px, dps;
863
864 dps = sfr->get (DPS);
865 if (dps & 0x01)
866 {
867 pl = DPL1;
868 ph = DPH1;
869 px = DPX1;
870 }
871 else
872 {
873 pl = DPL;
874 ph = DPH;
875 px = DPX;
876 }
877
878 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
879 write_mem (MEM_XRAM_ID,
880 sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl),
881 acc->read());
882 else
883 write_mem (MEM_XRAM_ID,
884 sfr->read (ph) * 256 + sfr->read (pl),
885 acc->read());
886
887 if (dps & 0x20) /* auto-switch dptr */
888 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
889
890 tick (1);
891 return resGO;
892 }
893
894 /*
895 * 0x[02468ace]1 2 24 AJMP addr
896 *____________________________________________________________________________
897 *
898 */
899
900 int
instruction_01(t_mem code)901 cl_uc390::instruction_01/*inst_ajmp_addr*/ (t_mem/*uchar*/ code)
902 {
903 uchar x, h, l;
904
905 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
906 {
907 x = (code >> 5) & 0x07;
908 h = fetch ();
909 l = fetch ();
910 PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
911 }
912 else
913 {
914 h = (code >> 5) & 0x07;
915 l = fetch ();
916 PC = (PC & 0xf800) | (h * 256 + l);
917 }
918 tick (1);
919 return resGO;
920 }
921
922 /*
923 * 0x02 3 24 LJMP addr
924 *____________________________________________________________________________
925 *
926 */
927
928 int
instruction_02(t_mem code)929 cl_uc390::instruction_02/*inst_ljmp*/ (t_mem/*uchar*/ code)
930 {
931 uchar x, h, l;
932
933 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
934 {
935 //printf("LJMP in 24 bit mode! PC=%x\n", PC);
936 x = fetch ();
937 h = fetch ();
938 l = fetch ();
939 PC = x * 256*256 + h * 256 + l;
940 }
941 else
942 {
943 h = fetch ();
944 l = fetch ();
945 PC = h * 256 + l;
946 }
947 tick (1);
948 return resGO;
949 }
950
951 /*
952 * 0x[13579bdf]1 2 24 ACALL addr
953 *____________________________________________________________________________
954 *
955 */
956
957 int
instruction_11(t_mem code)958 cl_uc390::instruction_11/*inst_acall_addr*/ (t_mem/*uchar*/ code)
959 {
960 uchar x, h, l;
961
962 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
963 {
964 x = (code >> 5) & 0x07;
965 h = fetch ();
966 l = fetch ();
967
968 push_byte ( PC & 0xff); /* push low byte */
969 push_byte ((PC >> 8) & 0xff); /* push high byte */
970 push_byte ((PC >> 16) & 0xff); /* push x byte */
971
972 PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
973 }
974 else
975 {
976 /* stock mcs51 mode */
977 class cl_memory_cell *stck;
978 t_mem sp;
979
980 h = (code >> 5) & 0x07;
981 l = fetch();
982 sp = sfr->wadd (SP, 1);
983 stck = iram->get_cell (sp);
984 stck->write (PC & 0xff); // push low byte
985
986 sp = sfr->wadd (SP, 1);
987 stck = iram->get_cell (sp);
988 stck->write ((PC >> 8) & 0xff); // push high byte
989 PC = (PC & 0xf800) | (h*256 + l);
990 }
991 tick (1);
992 return resGO;
993 }
994
995
996 /*
997 * 0x12 3 24 LCALL
998 *____________________________________________________________________________
999 *
1000 */
1001
1002 int
inst_lcall(t_mem code,uint addr,bool intr)1003 cl_uc390::inst_lcall (t_mem/*uchar*/ code, uint addr, bool intr)
1004 {
1005 uchar x = 0, h = 0, l = 0;
1006
1007 if (!intr)
1008 { /* this is a normal lcall */
1009 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1010 x = fetch ();
1011 h = fetch ();
1012 l = fetch ();
1013 }
1014 /* else, this is interrupt processing */
1015
1016 t_addr sp_before= sfr->get(SP);
1017 push_byte ( PC & 0xff); /* push low byte */
1018 push_byte ((PC >> 8) & 0xff); /* push high byte */
1019
1020 t_mem pushed= PC;
1021 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1022 {
1023 push_byte ((PC >> 16) & 0xff); /* push x byte */
1024 if (addr)
1025 PC = addr & 0xfffful; /* if interrupt: x-Byte is 0 */
1026 else
1027 PC = x * 256*256 + h * 256 + l;
1028 }
1029 else
1030 {
1031 class cl_stack_op *so;
1032 if (addr)
1033 {
1034 PC = addr;
1035 so= new cl_stack_intr(instPC, PC, pushed, sp_before, sfr->get(SP));
1036 }
1037 else
1038 {
1039 PC = h * 256 + l;
1040 so= new cl_stack_call(instPC, PC, pushed, sp_before, sfr->get(SP));
1041 }
1042 so->init();
1043 stack_write(so);
1044 }
1045 return resGO;
1046 }
1047
1048 /*
1049 * 0x22 1 24 RET
1050 *____________________________________________________________________________
1051 *
1052 */
1053
1054 int
instruction_22(t_mem code)1055 cl_uc390::instruction_22/*inst_ret*/ (t_mem/*uchar*/ code)
1056 {
1057 uchar x = 0, h, l;
1058
1059 t_addr sp_before= sfr->get(SP);
1060 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1061 x = pop_byte ();
1062 h = pop_byte ();
1063 l = pop_byte ();
1064
1065 tick (1);
1066
1067 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1068 {
1069 tick (1);
1070 PC = x * 256*256 + h * 256 + l;
1071 }
1072 else
1073 PC = h * 256 + l;
1074
1075 class cl_stack_op *so= new cl_stack_ret(instPC, PC, sp_before, sfr->get(SP));
1076 so->init();
1077 stack_read(so);
1078 return resGO;
1079 }
1080
1081 /*
1082 * 0x32 1 24 RETI
1083 *____________________________________________________________________________
1084 *
1085 */
1086
1087 int
instruction_32(t_mem code)1088 cl_uc390::instruction_32/*inst_reti*/ (t_mem/*uchar*/ code)
1089 {
1090 uchar x = 0, h, l;
1091
1092 t_addr sp_before= sfr->get(SP);
1093 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1094 x = pop_byte ();
1095 h = pop_byte ();
1096 l = pop_byte ();
1097 tick (1);
1098
1099 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1100 {
1101 tick (1);
1102 PC = x * 256*256 + h * 256 + l;
1103 }
1104 else
1105 PC = h * 256 + l;
1106
1107 interrupt->was_reti = true;
1108 class it_level *il = (class it_level *) (it_levels->top ());
1109 if (il &&
1110 il->level >= 0)
1111 {
1112 il = (class it_level *) (it_levels->pop ());
1113 delete il;
1114 }
1115
1116 class cl_stack_op *so=
1117 new cl_stack_iret(instPC, PC, sp_before, sfr->get(SP));
1118 so->init();
1119 stack_read(so);
1120 return resGO;
1121 }
1122
1123
1124 /*
1125 * Disassembling an instruction
1126 */
1127
1128 struct dis_entry *
dis_tbl(void)1129 cl_uc390::dis_tbl (void)
1130 {
1131 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1132 return disass_390f;
1133 else
1134 return disass_51;
1135 //t_uc51::dis_tbl ();
1136
1137 }
1138
1139 char *
disass(t_addr addr,const char * sep)1140 cl_uc390::disass (t_addr addr, const char *sep)
1141 {
1142 char work[256], temp[200]/*, c[2]*/;
1143 char *buf, *p, *b, *t, *org_b;
1144 t_mem code;
1145 uchar dps;
1146
1147 if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
1148 return cl_51core::disass (addr, sep);
1149 code = rom->get(addr);
1150
1151 p = work;
1152 b = org_b = strdup(dis_tbl()[code].mnemonic);
1153 while (*b)
1154 {
1155 if (*b == '%')
1156 {
1157 b++;
1158 switch (*(b++))
1159 {
1160 case 'A': // absolute address
1161 // stock:
1162 // sprintf (temp, "%04lx",
1163 // (addr & 0xf800)|
1164 // (((code >> 5) & 0x07) * 256 +
1165 // rom->get (addr + 1)));
1166
1167 sprintf (temp, /*"%06lx"*/rom->addr_format,
1168 (addr & 0xf80000L) |
1169 (((code >> 5) & 0x07) * (256 * 256) +
1170 (rom->get (addr + 1) * 256) +
1171 rom->get (addr + 2)));
1172 break;
1173 case 'l': // long address
1174 sprintf (temp, "%06lx",
1175 rom->get (addr + 1) * (256*256L) +
1176 rom->get (addr + 2) * 256 +
1177 rom->get (addr + 3));
1178 // rom->get (addr + 1) * 256 + rom->get (addr + 2));
1179 break;
1180 case 'a': // addr8 (direct address) at 2nd byte
1181 daddr_name(rom->get(addr+1), temp);
1182 break;
1183 case '8': // addr8 (direct address) at 3rd byte
1184 daddr_name(rom->get(addr+2), temp);
1185 break;
1186 case 'b': // bitaddr at 2nd byte
1187 {
1188 t_addr ba = rom->get (addr+1);
1189 /*if (get_name (ba, bit_tbl(), temp))
1190 break;
1191 if (ba<128)
1192 addr_name((ba/8)+32,iram,temp);
1193 else
1194 addr_name(ba&0xf8,sfr,temp);
1195 strcat (temp, ".");
1196 sprintf (c, "%1d", (int)(ba & 0x07));
1197 strcat (temp, c);
1198 break;*/
1199 baddr_name(ba, temp);
1200 break;
1201 }
1202 case 'r': // rel8 address at 2nd byte
1203 sprintf (temp, "%04x",
1204 /*t_addr*/int (addr + 2 + (signed char) (rom->get (addr + 1))));
1205 break;
1206 case 'R': // rel8 address at 3rd byte
1207 sprintf (temp, "%04x",
1208 /*t_addr*/int (addr + 3 + (signed char) (rom->get (addr + 2))));
1209 break;
1210 case 'd': // data8 at 2nd byte
1211 sprintf (temp, "%02x", (int)rom->get (addr + 1));
1212 break;
1213 case 'D': // data8 at 3rd byte
1214 sprintf (temp, "%02x", (int)rom->get (addr + 2));
1215 break;
1216 case 'i': // inc/dec dptr
1217 dps = sfr->get(DPS);
1218 sprintf (temp, ((dps & 0x01) ? (dps & 0x80) : (dps & 0x40)) ? "DEC" : "INC");
1219 break;
1220 default:
1221 strcpy (temp, "?");
1222 break;
1223 }
1224 t = temp;
1225 while (*t)
1226 *p++ = *t++;
1227 }
1228 else
1229 *p++ = *b++;
1230 }
1231 *p = '\0';
1232
1233 p = strchr (work, ' ');
1234 if (!p)
1235 {
1236 buf = strdup (work);
1237 return buf;
1238 }
1239 if (sep == NULL)
1240 buf = (char *) malloc (6 + strlen (p) + 1);
1241 else
1242 buf = (char *) malloc ((p - work) + strlen (sep) + strlen (p) + 1);
1243 for (p = work, b = buf; *p != ' '; p++, b++)
1244 *b = *p;
1245 p++;
1246 *b = '\0';
1247 if (sep == NULL)
1248 while (strlen (buf) < 6)
1249 strcat (buf, " ");
1250 else
1251 strcat (buf, sep);
1252 strcat (buf, p);
1253 free(org_b);
1254 return buf;
1255 }
1256
1257 void
print_regs(class cl_console_base * con)1258 cl_uc390::print_regs (class cl_console_base *con)
1259 {
1260 t_addr start;
1261 t_mem data;
1262 uchar dps;
1263
1264 if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
1265 {
1266 cl_51core::print_regs (con);
1267 return;
1268 }
1269 start = sfr->get (PSW) & 0x18;
1270 iram->dump (start, start + 7, 8, con/*->get_fout()*/);
1271 con->dd_printf(" R0 R1 R2 R3 R4 R5 R6 R7\n");
1272 data = iram->get (iram->get (start));
1273 con->dd_printf ("@R0 %02x %c", data, isprint (data) ? data : '.');
1274 con->dd_printf (" ACC= 0x%02x %3d %c B= 0x%02x",
1275 sfr->get (ACC), sfr->get (ACC),
1276 isprint (sfr->get (ACC)) ?
1277 (sfr->get (ACC)) : '.', sfr->get (B));
1278 eram2xram ();
1279 dps = sfr->get(DPS);
1280 data = get_mem (MEM_XRAM_ID,
1281 sfr->get (DPX) * 256*256 + sfr->get (DPH) * 256 + sfr->get (DPL));
1282 con->dd_printf (" %cDPTR0= 0x%02x%02x%02x @DPTR0= 0x%02x %3d %c",
1283 dps & 0x01 ? ' ' : dps & 0x20 ? 't' : '*',
1284 sfr->get (DPX), sfr->get (DPH), sfr->get (DPL),
1285 data, data, isprint (data) ? data : '.');
1286 data = get_mem (MEM_XRAM_ID,
1287 sfr->get (DPX1) * 256*256 + sfr->get (DPH1) * 256 + sfr->get (DPL1));
1288 con->dd_printf (" %cDPTR1= 0x%02x%02x%02x @DPTR1= 0x%02x %3d %c\n",
1289 dps & 0x01 ? dps & 0x20 ? 't' : '*' : ' ',
1290 sfr->get (DPX1), sfr->get (DPH1), sfr->get (DPL1),
1291 data, data, isprint (data) ? data : '.');
1292 data = iram->get (iram->get (start + 1));
1293 con->dd_printf ("@R1 %02x %c", data, isprint (data) ? data : '.');
1294 con->dd_printf (" AP= 0x%02x", sfr->get (AP));
1295 data= sfr->get (PSW);
1296 con->dd_printf (" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c ",
1297 data,
1298 (data & bmCY) ? '1' : '0', (data & bmAC) ? '1' : '0',
1299 (data & bmOV) ? '1' : '0', (data & bmP ) ? '1' : '0');
1300 /* show stack pointer */
1301 if (sfr->get (ACON) & 0x04)
1302 {
1303 /* SA: 10 bit stack */
1304 start = (sfr->get (R51_ESP) & 3) * 256 + sfr->get (SP);
1305 con->dd_printf ("SP10 ", start);
1306 ixram->dump (start, start - 7, 8, con/*->get_fout()*/);
1307 }
1308 else
1309 {
1310 start = sfr->get (SP);
1311 con->dd_printf ("SP ", start);
1312 iram->dump (start, start - 7, 8, con/*->get_fout()*/);
1313 }
1314
1315 print_disass (PC, con);
1316 }
1317
1318 /* End of s51.src/uc390.cc */
1319