1 /************************************************************************** 2 * 3 * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #ifndef CAIRO_DRM_INTEL_BRW_STRUCTS_H 29 #define CAIRO_DRM_INTEL_BRW_STRUCTS_H 30 31 #include "cairo.h" 32 #include "cairo-types-private.h" 33 34 /* Command packets: 35 */ 36 struct header { 37 unsigned int length:16; 38 unsigned int opcode:16; 39 }; 40 41 union header_union { 42 struct header bits; 43 unsigned int dword; 44 }; 45 46 struct brw_3d_control { 47 struct { 48 unsigned int length:8; 49 unsigned int notify_enable:1; 50 unsigned int pad:3; 51 unsigned int wc_flush_enable:1; 52 unsigned int depth_stall_enable:1; 53 unsigned int operation:2; 54 unsigned int opcode:16; 55 } header; 56 57 struct { 58 unsigned int pad:2; 59 unsigned int dest_addr_type:1; 60 unsigned int dest_addr:29; 61 } dest; 62 63 unsigned int dword2; 64 unsigned int dword3; 65 }; 66 67 68 struct brw_3d_primitive { 69 struct { 70 unsigned int length:8; 71 unsigned int pad:2; 72 unsigned int topology:5; 73 unsigned int indexed:1; 74 unsigned int opcode:16; 75 } header; 76 77 unsigned int verts_per_instance; 78 unsigned int start_vert_location; 79 unsigned int instance_count; 80 unsigned int start_instance_location; 81 unsigned int base_vert_location; 82 }; 83 84 /* These seem to be passed around as function args, so it works out 85 * better to keep them as #defines: 86 */ 87 #define BRW_FLUSH_READ_CACHE 0x1 88 #define BRW_FLUSH_STATE_CACHE 0x2 89 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 90 #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 91 92 struct brw_mi_flush { 93 unsigned int flags:4; 94 unsigned int pad:12; 95 unsigned int opcode:16; 96 }; 97 98 struct brw_vf_statistics { 99 unsigned int statistics_enable:1; 100 unsigned int pad:15; 101 unsigned int opcode:16; 102 }; 103 104 105 struct brw_binding_table_pointers { 106 struct header header; 107 unsigned int vs; 108 unsigned int gs; 109 unsigned int clp; 110 unsigned int sf; 111 unsigned int wm; 112 }; 113 114 struct brw_blend_constant_color { 115 struct header header; 116 float blend_constant_color[4]; 117 }; 118 119 struct brw_depthbuffer { 120 union header_union header; 121 122 union { 123 struct { 124 unsigned int pitch:18; 125 unsigned int format:3; 126 unsigned int pad:4; 127 unsigned int depth_offset_disable:1; 128 unsigned int tile_walk:1; 129 unsigned int tiled_surface:1; 130 unsigned int pad2:1; 131 unsigned int surface_type:3; 132 } bits; 133 unsigned int dword; 134 } dword1; 135 136 unsigned int dword2_base_addr; 137 138 union { 139 struct { 140 unsigned int pad:1; 141 unsigned int mipmap_layout:1; 142 unsigned int lod:4; 143 unsigned int width:13; 144 unsigned int height:13; 145 } bits; 146 unsigned int dword; 147 } dword3; 148 149 union { 150 struct { 151 unsigned int pad:12; 152 unsigned int min_array_element:9; 153 unsigned int depth:11; 154 } bits; 155 unsigned int dword; 156 } dword4; 157 }; 158 159 struct brw_drawrect { 160 struct header header; 161 unsigned int xmin:16; 162 unsigned int ymin:16; 163 unsigned int xmax:16; 164 unsigned int ymax:16; 165 unsigned int xorg:16; 166 unsigned int yorg:16; 167 }; 168 169 struct brw_global_depth_offset_clamp { 170 struct header header; 171 float depth_offset_clamp; 172 }; 173 174 struct brw_indexbuffer { 175 union { 176 struct { 177 unsigned int length:8; 178 unsigned int index_format:2; 179 unsigned int cut_index_enable:1; 180 unsigned int pad:5; 181 unsigned int opcode:16; 182 } bits; 183 unsigned int dword; 184 } header; 185 unsigned int buffer_start; 186 unsigned int buffer_end; 187 }; 188 189 190 struct brw_line_stipple { 191 struct header header; 192 193 struct { 194 unsigned int pattern:16; 195 unsigned int pad:16; 196 } bits0; 197 198 struct { 199 unsigned int repeat_count:9; 200 unsigned int pad:7; 201 unsigned int inverse_repeat_count:16; 202 } bits1; 203 }; 204 205 struct brw_pipelined_state_pointers { 206 struct header header; 207 208 struct { 209 unsigned int pad:5; 210 unsigned int offset:27; 211 } vs; 212 213 struct { 214 unsigned int enable:1; 215 unsigned int pad:4; 216 unsigned int offset:27; 217 } gs; 218 219 struct { 220 unsigned int enable:1; 221 unsigned int pad:4; 222 unsigned int offset:27; 223 } clp; 224 225 struct { 226 unsigned int pad:5; 227 unsigned int offset:27; 228 } sf; 229 230 struct { 231 unsigned int pad:5; 232 unsigned int offset:27; 233 } wm; 234 235 struct { 236 unsigned int pad:6; 237 unsigned int offset:26; 238 } cc; 239 }; 240 241 struct brw_polygon_stipple_offset { 242 struct header header; 243 244 struct { 245 unsigned int y_offset:5; 246 unsigned int pad:3; 247 unsigned int x_offset:5; 248 unsigned int pad0:19; 249 } bits0; 250 }; 251 252 struct brw_polygon_stipple { 253 struct header header; 254 unsigned int stipple[32]; 255 }; 256 257 struct brw_pipeline_select { 258 struct { 259 unsigned int pipeline_select:1; 260 unsigned int pad:15; 261 unsigned int opcode:16; 262 } header; 263 }; 264 265 struct brw_pipe_control { 266 struct { 267 unsigned int length:8; 268 unsigned int notify_enable:1; 269 unsigned int pad:2; 270 unsigned int instruction_state_cache_flush_enable:1; 271 unsigned int write_cache_flush_enable:1; 272 unsigned int depth_stall_enable:1; 273 unsigned int post_sync_operation:2; 274 275 unsigned int opcode:16; 276 } header; 277 278 struct { 279 unsigned int pad:2; 280 unsigned int dest_addr_type:1; 281 unsigned int dest_addr:29; 282 } bits1; 283 284 unsigned int data0; 285 unsigned int data1; 286 }; 287 288 289 struct brw_urb_fence { 290 struct { 291 unsigned int length:8; 292 unsigned int vs_realloc:1; 293 unsigned int gs_realloc:1; 294 unsigned int clp_realloc:1; 295 unsigned int sf_realloc:1; 296 unsigned int vfe_realloc:1; 297 unsigned int cs_realloc:1; 298 unsigned int pad:2; 299 unsigned int opcode:16; 300 } header; 301 302 struct { 303 unsigned int vs_fence:10; 304 unsigned int gs_fence:10; 305 unsigned int clp_fence:10; 306 unsigned int pad:2; 307 } bits0; 308 309 struct { 310 unsigned int sf_fence:10; 311 unsigned int vf_fence:10; 312 unsigned int cs_fence:10; 313 unsigned int pad:2; 314 } bits1; 315 }; 316 317 struct brw_constant_buffer_state { 318 struct header header; 319 320 struct { 321 unsigned int nr_urb_entries:3; 322 unsigned int pad:1; 323 unsigned int urb_entry_size:5; 324 unsigned int pad0:23; 325 } bits0; 326 }; 327 328 struct brw_constant_buffer { 329 struct { 330 unsigned int length:8; 331 unsigned int valid:1; 332 unsigned int pad:7; 333 unsigned int opcode:16; 334 } header; 335 336 struct { 337 unsigned int buffer_length:6; 338 unsigned int buffer_address:26; 339 } bits0; 340 }; 341 342 struct brw_state_base_address { 343 struct header header; 344 345 struct { 346 unsigned int modify_enable:1; 347 unsigned int pad:4; 348 unsigned int general_state_address:27; 349 } bits0; 350 351 struct { 352 unsigned int modify_enable:1; 353 unsigned int pad:4; 354 unsigned int surface_state_address:27; 355 } bits1; 356 357 struct { 358 unsigned int modify_enable:1; 359 unsigned int pad:4; 360 unsigned int indirect_object_state_address:27; 361 } bits2; 362 363 struct { 364 unsigned int modify_enable:1; 365 unsigned int pad:11; 366 unsigned int general_state_upper_bound:20; 367 } bits3; 368 369 struct { 370 unsigned int modify_enable:1; 371 unsigned int pad:11; 372 unsigned int indirect_object_state_upper_bound:20; 373 } bits4; 374 }; 375 376 struct brw_state_prefetch { 377 struct header header; 378 379 struct { 380 unsigned int prefetch_count:3; 381 unsigned int pad:3; 382 unsigned int prefetch_pointer:26; 383 } bits0; 384 }; 385 386 struct brw_system_instruction_pointer { 387 struct header header; 388 389 struct { 390 unsigned int pad:4; 391 unsigned int system_instruction_pointer:28; 392 } bits0; 393 }; 394 395 396 /* State structs for the various fixed function units: 397 */ 398 399 struct thread0 { 400 unsigned int pad0:1; 401 unsigned int grf_reg_count:3; 402 unsigned int pad1:2; 403 unsigned int kernel_start_pointer:26; 404 }; 405 406 struct thread1 { 407 unsigned int ext_halt_exception_enable:1; 408 unsigned int sw_exception_enable:1; 409 unsigned int mask_stack_exception_enable:1; 410 unsigned int timeout_exception_enable:1; 411 unsigned int illegal_op_exception_enable:1; 412 unsigned int pad0:3; 413 unsigned int depth_coef_urb_read_offset:6; /* WM only */ 414 unsigned int pad1:2; 415 unsigned int floating_point_mode:1; 416 unsigned int thread_priority:1; 417 unsigned int binding_table_entry_count:8; 418 unsigned int pad3:5; 419 unsigned int single_program_flow:1; 420 }; 421 422 struct thread2 { 423 unsigned int per_thread_scratch_space:4; 424 unsigned int pad0:6; 425 unsigned int scratch_space_base_pointer:22; 426 }; 427 428 struct thread3 { 429 unsigned int dispatch_grf_start_reg:4; 430 unsigned int urb_entry_read_offset:6; 431 unsigned int pad0:1; 432 unsigned int urb_entry_read_length:6; 433 unsigned int pad1:1; 434 unsigned int const_urb_entry_read_offset:6; 435 unsigned int pad2:1; 436 unsigned int const_urb_entry_read_length:6; 437 unsigned int pad3:1; 438 }; 439 440 struct brw_clip_unit_state { 441 struct thread0 thread0; 442 struct thread1 thread1; 443 struct thread2 thread2; 444 struct thread3 thread3; 445 446 struct { 447 unsigned int pad0:9; 448 unsigned int gs_output_stats:1; /* not always */ 449 unsigned int stats_enable:1; 450 unsigned int nr_urb_entries:7; 451 unsigned int pad1:1; 452 unsigned int urb_entry_allocation_size:5; 453 unsigned int pad2:1; 454 unsigned int max_threads:6; /* may be less */ 455 unsigned int pad3:1; 456 } thread4; 457 458 struct { 459 unsigned int pad0:13; 460 unsigned int clip_mode:3; 461 unsigned int userclip_enable_flags:8; 462 unsigned int userclip_must_clip:1; 463 unsigned int pad1:1; 464 unsigned int guard_band_enable:1; 465 unsigned int viewport_z_clip_enable:1; 466 unsigned int viewport_xy_clip_enable:1; 467 unsigned int vertex_position_space:1; 468 unsigned int api_mode:1; 469 unsigned int pad2:1; 470 } clip5; 471 472 struct { 473 unsigned int pad0:5; 474 unsigned int clipper_viewport_state_ptr:27; 475 } clip6; 476 477 float viewport_xmin; 478 float viewport_xmax; 479 float viewport_ymin; 480 float viewport_ymax; 481 }; 482 483 struct brw_cc_unit_state { 484 struct { 485 unsigned int pad0:3; 486 unsigned int bf_stencil_pass_depth_pass_op:3; 487 unsigned int bf_stencil_pass_depth_fail_op:3; 488 unsigned int bf_stencil_fail_op:3; 489 unsigned int bf_stencil_func:3; 490 unsigned int bf_stencil_enable:1; 491 unsigned int pad1:2; 492 unsigned int stencil_write_enable:1; 493 unsigned int stencil_pass_depth_pass_op:3; 494 unsigned int stencil_pass_depth_fail_op:3; 495 unsigned int stencil_fail_op:3; 496 unsigned int stencil_func:3; 497 unsigned int stencil_enable:1; 498 } cc0; 499 500 struct { 501 unsigned int bf_stencil_ref:8; 502 unsigned int stencil_write_mask:8; 503 unsigned int stencil_test_mask:8; 504 unsigned int stencil_ref:8; 505 } cc1; 506 507 struct { 508 unsigned int logicop_enable:1; 509 unsigned int pad0:10; 510 unsigned int depth_write_enable:1; 511 unsigned int depth_test_function:3; 512 unsigned int depth_test:1; 513 unsigned int bf_stencil_write_mask:8; 514 unsigned int bf_stencil_test_mask:8; 515 } cc2; 516 517 struct { 518 unsigned int pad0:8; 519 unsigned int alpha_test_func:3; 520 unsigned int alpha_test:1; 521 unsigned int blend_enable:1; 522 unsigned int ia_blend_enable:1; 523 unsigned int pad1:1; 524 unsigned int alpha_test_format:1; 525 unsigned int pad2:16; 526 } cc3; 527 528 struct { 529 unsigned int pad0:5; 530 unsigned int cc_viewport_state_offset:27; 531 } cc4; 532 533 struct { 534 unsigned int pad0:2; 535 unsigned int ia_dest_blend_factor:5; 536 unsigned int ia_src_blend_factor:5; 537 unsigned int ia_blend_function:3; 538 unsigned int statistics_enable:1; 539 unsigned int logicop_func:4; 540 unsigned int pad1:11; 541 unsigned int dither_enable:1; 542 } cc5; 543 544 struct { 545 unsigned int clamp_post_alpha_blend:1; 546 unsigned int clamp_pre_alpha_blend:1; 547 unsigned int clamp_range:2; 548 unsigned int pad0:11; 549 unsigned int y_dither_offset:2; 550 unsigned int x_dither_offset:2; 551 unsigned int dest_blend_factor:5; 552 unsigned int src_blend_factor:5; 553 unsigned int blend_function:3; 554 } cc6; 555 556 struct { 557 union { 558 float f; 559 unsigned char ub[4]; 560 } alpha_ref; 561 } cc7; 562 }; 563 564 struct brw_sf_unit_state { 565 struct thread0 thread0; 566 struct { 567 unsigned int pad0:7; 568 unsigned int sw_exception_enable:1; 569 unsigned int pad1:3; 570 unsigned int mask_stack_exception_enable:1; 571 unsigned int pad2:1; 572 unsigned int illegal_op_exception_enable:1; 573 unsigned int pad3:2; 574 unsigned int floating_point_mode:1; 575 unsigned int thread_priority:1; 576 unsigned int binding_table_entry_count:8; 577 unsigned int pad4:5; 578 unsigned int single_program_flow:1; 579 } sf1; 580 581 struct thread2 thread2; 582 struct thread3 thread3; 583 584 struct { 585 unsigned int pad0:10; 586 unsigned int stats_enable:1; 587 unsigned int nr_urb_entries:7; 588 unsigned int pad1:1; 589 unsigned int urb_entry_allocation_size:5; 590 unsigned int pad2:1; 591 unsigned int max_threads:6; 592 unsigned int pad3:1; 593 } thread4; 594 595 struct { 596 unsigned int front_winding:1; 597 unsigned int viewport_transform:1; 598 unsigned int pad0:3; 599 unsigned int sf_viewport_state_offset:27; 600 } sf5; 601 602 struct { 603 unsigned int pad0:9; 604 unsigned int dest_org_vbias:4; 605 unsigned int dest_org_hbias:4; 606 unsigned int scissor:1; 607 unsigned int disable_2x2_trifilter:1; 608 unsigned int disable_zero_pix_trifilter:1; 609 unsigned int point_rast_rule:2; 610 unsigned int line_endcap_aa_region_width:2; 611 unsigned int line_width:4; 612 unsigned int fast_scissor_disable:1; 613 unsigned int cull_mode:2; 614 unsigned int aa_enable:1; 615 } sf6; 616 617 struct { 618 unsigned int point_size:11; 619 unsigned int use_point_size_state:1; 620 unsigned int subpixel_precision:1; 621 unsigned int sprite_point:1; 622 unsigned int pad0:11; 623 unsigned int trifan_pv:2; 624 unsigned int linestrip_pv:2; 625 unsigned int tristrip_pv:2; 626 unsigned int line_last_pixel_enable:1; 627 } sf7; 628 }; 629 630 struct brw_gs_unit_state { 631 struct thread0 thread0; 632 struct thread1 thread1; 633 struct thread2 thread2; 634 struct thread3 thread3; 635 636 struct { 637 unsigned int pad0:10; 638 unsigned int stats_enable:1; 639 unsigned int nr_urb_entries:7; 640 unsigned int pad1:1; 641 unsigned int urb_entry_allocation_size:5; 642 unsigned int pad2:1; 643 unsigned int max_threads:1; 644 unsigned int pad3:6; 645 } thread4; 646 647 struct { 648 unsigned int sampler_count:3; 649 unsigned int pad0:2; 650 unsigned int sampler_state_pointer:27; 651 } gs5; 652 653 struct { 654 unsigned int max_vp_index:4; 655 unsigned int pad0:26; 656 unsigned int reorder_enable:1; 657 unsigned int pad1:1; 658 } gs6; 659 }; 660 661 struct brw_vs_unit_state { 662 struct thread0 thread0; 663 struct thread1 thread1; 664 struct thread2 thread2; 665 struct thread3 thread3; 666 667 struct { 668 unsigned int pad0:10; 669 unsigned int stats_enable:1; 670 unsigned int nr_urb_entries:7; 671 unsigned int pad1:1; 672 unsigned int urb_entry_allocation_size:5; 673 unsigned int pad2:1; 674 unsigned int max_threads:4; 675 unsigned int pad3:3; 676 } thread4; 677 678 struct { 679 unsigned int sampler_count:3; 680 unsigned int pad0:2; 681 unsigned int sampler_state_pointer:27; 682 } vs5; 683 684 struct { 685 unsigned int vs_enable:1; 686 unsigned int vert_cache_disable:1; 687 unsigned int pad0:30; 688 } vs6; 689 }; 690 691 struct brw_wm_unit_state { 692 struct thread0 thread0; 693 struct thread1 thread1; 694 struct thread2 thread2; 695 struct thread3 thread3; 696 697 struct { 698 unsigned int stats_enable:1; 699 unsigned int pad0:1; 700 unsigned int sampler_count:3; 701 unsigned int sampler_state_pointer:27; 702 } wm4; 703 704 struct { 705 unsigned int enable_8_pix:1; 706 unsigned int enable_16_pix:1; 707 unsigned int enable_32_pix:1; 708 unsigned int pad0:7; 709 unsigned int legacy_global_depth_bias:1; 710 unsigned int line_stipple:1; 711 unsigned int depth_offset:1; 712 unsigned int polygon_stipple:1; 713 unsigned int line_aa_region_width:2; 714 unsigned int line_endcap_aa_region_width:2; 715 unsigned int early_depth_test:1; 716 unsigned int thread_dispatch_enable:1; 717 unsigned int program_uses_depth:1; 718 unsigned int program_computes_depth:1; 719 unsigned int program_uses_killpixel:1; 720 unsigned int legacy_line_rast: 1; 721 unsigned int transposed_urb_read:1; 722 unsigned int max_threads:7; 723 } wm5; 724 725 float global_depth_offset_constant; 726 float global_depth_offset_scale; 727 }; 728 729 /* The hardware supports two different modes for border color. The 730 * default (OpenGL) mode uses floating-point color channels, while the 731 * legacy mode uses 4 bytes. 732 * 733 * More significantly, the legacy mode respects the components of the 734 * border color for channels not present in the source, (whereas the 735 * default mode will ignore the border color's alpha channel and use 736 * alpha==1 for an RGB source, for example). 737 * 738 * The legacy mode matches the semantics specified by the Render 739 * extension. 740 */ 741 struct brw_sampler_default_border_color { 742 float color[4]; 743 }; 744 745 struct brw_sampler_legacy_border_color { 746 uint8_t color[4]; 747 }; 748 749 struct brw_sampler_state { 750 struct { 751 unsigned int shadow_function:3; 752 unsigned int lod_bias:11; 753 unsigned int min_filter:3; 754 unsigned int mag_filter:3; 755 unsigned int mip_filter:2; 756 unsigned int base_level:5; 757 unsigned int pad:1; 758 unsigned int lod_preclamp:1; 759 unsigned int border_color_mode:1; 760 unsigned int pad0:1; 761 unsigned int disable:1; 762 } ss0; 763 764 struct { 765 unsigned int r_wrap_mode:3; 766 unsigned int t_wrap_mode:3; 767 unsigned int s_wrap_mode:3; 768 unsigned int pad:3; 769 unsigned int max_lod:10; 770 unsigned int min_lod:10; 771 } ss1; 772 773 struct { 774 unsigned int pad:5; 775 unsigned int border_color_pointer:27; 776 } ss2; 777 778 struct { 779 unsigned int pad:19; 780 unsigned int max_aniso:3; 781 unsigned int chroma_key_mode:1; 782 unsigned int chroma_key_index:2; 783 unsigned int chroma_key_enable:1; 784 unsigned int monochrome_filter_width:3; 785 unsigned int monochrome_filter_height:3; 786 } ss3; 787 }; 788 789 struct brw_clipper_viewport { 790 float xmin; 791 float xmax; 792 float ymin; 793 float ymax; 794 }; 795 796 struct brw_cc_viewport { 797 float min_depth; 798 float max_depth; 799 }; 800 801 struct brw_sf_viewport { 802 struct { 803 float m00; 804 float m11; 805 float m22; 806 float m30; 807 float m31; 808 float m32; 809 } viewport; 810 811 struct { 812 short xmin; 813 short ymin; 814 short xmax; 815 short ymax; 816 } scissor; 817 }; 818 819 /* Documented in the subsystem/shared-functions/sampler chapter... 820 */ 821 struct brw_surface_state { 822 struct { 823 unsigned int cube_pos_z:1; 824 unsigned int cube_neg_z:1; 825 unsigned int cube_pos_y:1; 826 unsigned int cube_neg_y:1; 827 unsigned int cube_pos_x:1; 828 unsigned int cube_neg_x:1; 829 unsigned int pad:3; 830 unsigned int render_cache_read_mode:1; 831 unsigned int mipmap_layout_mode:1; 832 unsigned int vert_line_stride_ofs:1; 833 unsigned int vert_line_stride:1; 834 unsigned int color_blend:1; 835 unsigned int writedisable_blue:1; 836 unsigned int writedisable_green:1; 837 unsigned int writedisable_red:1; 838 unsigned int writedisable_alpha:1; 839 unsigned int surface_format:9; 840 unsigned int data_return_format:1; 841 unsigned int pad0:1; 842 unsigned int surface_type:3; 843 } ss0; 844 845 struct { 846 unsigned int base_addr; 847 } ss1; 848 849 struct { 850 unsigned int render_target_rotation:2; 851 unsigned int mip_count:4; 852 unsigned int width:13; 853 unsigned int height:13; 854 } ss2; 855 856 struct { 857 unsigned int tile_walk:1; 858 unsigned int tiled_surface:1; 859 unsigned int pad:1; 860 unsigned int pitch:18; 861 unsigned int depth:11; 862 } ss3; 863 864 struct { 865 unsigned int pad:19; 866 unsigned int min_array_elt:9; 867 unsigned int min_lod:4; 868 } ss4; 869 870 struct { 871 unsigned int pad:20; 872 unsigned int y_offset:4; 873 unsigned int pad2:1; 874 unsigned int x_offset:7; 875 } ss5; 876 }; 877 878 struct brw_vertex_buffer_state { 879 struct { 880 unsigned int pitch:11; 881 unsigned int pad:15; 882 unsigned int access_type:1; 883 unsigned int vb_index:5; 884 } vb0; 885 886 unsigned int start_addr; 887 unsigned int max_index; 888 #if 1 889 unsigned int instance_data_step_rate; /* not included for sequential/random vertices? */ 890 #endif 891 }; 892 893 #define BRW_VBP_MAX 17 894 895 struct brw_vb_array_state { 896 struct header header; 897 struct brw_vertex_buffer_state vb[BRW_VBP_MAX]; 898 }; 899 900 struct brw_vertex_element_state { 901 struct { 902 unsigned int src_offset:11; 903 unsigned int pad:5; 904 unsigned int src_format:9; 905 unsigned int pad0:1; 906 unsigned int valid:1; 907 unsigned int vertex_buffer_index:5; 908 } ve0; 909 910 struct { 911 unsigned int dst_offset:8; 912 unsigned int pad:8; 913 unsigned int vfcomponent3:4; 914 unsigned int vfcomponent2:4; 915 unsigned int vfcomponent1:4; 916 unsigned int vfcomponent0:4; 917 } ve1; 918 }; 919 920 #define BRW_VEP_MAX 18 921 922 struct brw_vertex_element_packet { 923 struct header header; 924 struct brw_vertex_element_state ve[BRW_VEP_MAX]; 925 }; 926 927 struct brw_urb_immediate { 928 unsigned int opcode:4; 929 unsigned int offset:6; 930 unsigned int swizzle_control:2; 931 unsigned int pad:1; 932 unsigned int allocate:1; 933 unsigned int used:1; 934 unsigned int complete:1; 935 unsigned int response_length:4; 936 unsigned int msg_length:4; 937 unsigned int msg_target:4; 938 unsigned int pad1:3; 939 unsigned int end_of_thread:1; 940 }; 941 942 /* Instruction format for the execution units: */ 943 944 struct brw_instruction { 945 struct { 946 unsigned int opcode:7; 947 unsigned int pad:1; 948 unsigned int access_mode:1; 949 unsigned int mask_control:1; 950 unsigned int dependency_control:2; 951 unsigned int compression_control:2; 952 unsigned int thread_control:2; 953 unsigned int predicate_control:4; 954 unsigned int predicate_inverse:1; 955 unsigned int execution_size:3; 956 unsigned int destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */ 957 unsigned int pad0:2; 958 unsigned int debug_control:1; 959 unsigned int saturate:1; 960 } header; 961 962 union { 963 struct { 964 unsigned int dest_reg_file:2; 965 unsigned int dest_reg_type:3; 966 unsigned int src0_reg_file:2; 967 unsigned int src0_reg_type:3; 968 unsigned int src1_reg_file:2; 969 unsigned int src1_reg_type:3; 970 unsigned int pad:1; 971 unsigned int dest_subreg_nr:5; 972 unsigned int dest_reg_nr:8; 973 unsigned int dest_horiz_stride:2; 974 unsigned int dest_address_mode:1; 975 } da1; 976 977 struct { 978 unsigned int dest_reg_file:2; 979 unsigned int dest_reg_type:3; 980 unsigned int src0_reg_file:2; 981 unsigned int src0_reg_type:3; 982 unsigned int pad:6; 983 int dest_indirect_offset:10; /* offset against the deref'd address reg */ 984 unsigned int dest_subreg_nr:3; /* subnr for the address reg a0.x */ 985 unsigned int dest_horiz_stride:2; 986 unsigned int dest_address_mode:1; 987 } ia1; 988 989 struct { 990 unsigned int dest_reg_file:2; 991 unsigned int dest_reg_type:3; 992 unsigned int src0_reg_file:2; 993 unsigned int src0_reg_type:3; 994 unsigned int src1_reg_file:2; 995 unsigned int src1_reg_type:3; 996 unsigned int pad0:1; 997 unsigned int dest_writemask:4; 998 unsigned int dest_subreg_nr:1; 999 unsigned int dest_reg_nr:8; 1000 unsigned int pad1:2; 1001 unsigned int dest_address_mode:1; 1002 } da16; 1003 1004 struct { 1005 unsigned int dest_reg_file:2; 1006 unsigned int dest_reg_type:3; 1007 unsigned int src0_reg_file:2; 1008 unsigned int src0_reg_type:3; 1009 unsigned int pad0:6; 1010 unsigned int dest_writemask:4; 1011 int dest_indirect_offset:6; 1012 unsigned int dest_subreg_nr:3; 1013 unsigned int pad1:2; 1014 unsigned int dest_address_mode:1; 1015 } ia16; 1016 } bits1; 1017 1018 1019 union { 1020 struct { 1021 unsigned int src0_subreg_nr:5; 1022 unsigned int src0_reg_nr:8; 1023 unsigned int src0_abs:1; 1024 unsigned int src0_negate:1; 1025 unsigned int src0_address_mode:1; 1026 unsigned int src0_horiz_stride:2; 1027 unsigned int src0_width:3; 1028 unsigned int src0_vert_stride:4; 1029 unsigned int flag_reg_nr:1; 1030 unsigned int pad:6; 1031 } da1; 1032 1033 struct { 1034 int src0_indirect_offset:10; 1035 unsigned int src0_subreg_nr:3; 1036 unsigned int src0_abs:1; 1037 unsigned int src0_negate:1; 1038 unsigned int src0_address_mode:1; 1039 unsigned int src0_horiz_stride:2; 1040 unsigned int src0_width:3; 1041 unsigned int src0_vert_stride:4; 1042 unsigned int flag_reg_nr:1; 1043 unsigned int pad:6; 1044 } ia1; 1045 1046 struct { 1047 unsigned int src0_swz_x:2; 1048 unsigned int src0_swz_y:2; 1049 unsigned int src0_subreg_nr:1; 1050 unsigned int src0_reg_nr:8; 1051 unsigned int src0_abs:1; 1052 unsigned int src0_negate:1; 1053 unsigned int src0_address_mode:1; 1054 unsigned int src0_swz_z:2; 1055 unsigned int src0_swz_w:2; 1056 unsigned int pad0:1; 1057 unsigned int src0_vert_stride:4; 1058 unsigned int flag_reg_nr:1; 1059 unsigned int pad1:6; 1060 } da16; 1061 1062 struct { 1063 unsigned int src0_swz_x:2; 1064 unsigned int src0_swz_y:2; 1065 int src0_indirect_offset:6; 1066 unsigned int src0_subreg_nr:3; 1067 unsigned int src0_abs:1; 1068 unsigned int src0_negate:1; 1069 unsigned int src0_address_mode:1; 1070 unsigned int src0_swz_z:2; 1071 unsigned int src0_swz_w:2; 1072 unsigned int pad0:1; 1073 unsigned int src0_vert_stride:4; 1074 unsigned int flag_reg_nr:1; 1075 unsigned int pad1:6; 1076 } ia16; 1077 1078 } bits2; 1079 1080 union { 1081 struct { 1082 unsigned int src1_subreg_nr:5; 1083 unsigned int src1_reg_nr:8; 1084 unsigned int src1_abs:1; 1085 unsigned int src1_negate:1; 1086 unsigned int pad:1; 1087 unsigned int src1_horiz_stride:2; 1088 unsigned int src1_width:3; 1089 unsigned int src1_vert_stride:4; 1090 unsigned int pad0:7; 1091 } da1; 1092 1093 struct { 1094 unsigned int src1_swz_x:2; 1095 unsigned int src1_swz_y:2; 1096 unsigned int src1_subreg_nr:1; 1097 unsigned int src1_reg_nr:8; 1098 unsigned int src1_abs:1; 1099 unsigned int src1_negate:1; 1100 unsigned int pad0:1; 1101 unsigned int src1_swz_z:2; 1102 unsigned int src1_swz_w:2; 1103 unsigned int pad1:1; 1104 unsigned int src1_vert_stride:4; 1105 unsigned int pad2:7; 1106 } da16; 1107 1108 struct { 1109 int src1_indirect_offset:10; 1110 unsigned int src1_subreg_nr:3; 1111 unsigned int src1_abs:1; 1112 unsigned int src1_negate:1; 1113 unsigned int pad0:1; 1114 unsigned int src1_horiz_stride:2; 1115 unsigned int src1_width:3; 1116 unsigned int src1_vert_stride:4; 1117 unsigned int flag_reg_nr:1; 1118 unsigned int pad1:6; 1119 } ia1; 1120 1121 struct { 1122 unsigned int src1_swz_x:2; 1123 unsigned int src1_swz_y:2; 1124 int src1_indirect_offset:6; 1125 unsigned int src1_subreg_nr:3; 1126 unsigned int src1_abs:1; 1127 unsigned int src1_negate:1; 1128 unsigned int pad0:1; 1129 unsigned int src1_swz_z:2; 1130 unsigned int src1_swz_w:2; 1131 unsigned int pad1:1; 1132 unsigned int src1_vert_stride:4; 1133 unsigned int flag_reg_nr:1; 1134 unsigned int pad2:6; 1135 } ia16; 1136 1137 struct { 1138 int jump_count:16; /* note: signed */ 1139 unsigned int pop_count:4; 1140 unsigned int pad0:12; 1141 } if_else; 1142 1143 struct { 1144 unsigned int function:4; 1145 unsigned int int_type:1; 1146 unsigned int precision:1; 1147 unsigned int saturate:1; 1148 unsigned int data_type:1; 1149 unsigned int pad0:8; 1150 unsigned int response_length:4; 1151 unsigned int msg_length:4; 1152 unsigned int msg_target:4; 1153 unsigned int pad1:3; 1154 unsigned int end_of_thread:1; 1155 } math; 1156 1157 struct { 1158 unsigned int binding_table_index:8; 1159 unsigned int sampler:4; 1160 unsigned int return_format:2; 1161 unsigned int msg_type:2; 1162 unsigned int response_length:4; 1163 unsigned int msg_length:4; 1164 unsigned int msg_target:4; 1165 unsigned int pad1:3; 1166 unsigned int end_of_thread:1; 1167 } sampler; 1168 1169 struct { 1170 uint32_t binding_table_index:8; 1171 uint32_t sampler:4; 1172 uint32_t msg_type:4; 1173 uint32_t response_length:4; 1174 uint32_t msg_length:4; 1175 uint32_t msg_target:4; 1176 uint32_t pad1:3; 1177 uint32_t end_of_thread:1; 1178 } sampler_g4x; 1179 1180 struct brw_urb_immediate urb; 1181 1182 struct { 1183 unsigned int binding_table_index:8; 1184 unsigned int msg_control:4; 1185 unsigned int msg_type:2; 1186 unsigned int target_cache:2; 1187 unsigned int response_length:4; 1188 unsigned int msg_length:4; 1189 unsigned int msg_target:4; 1190 unsigned int pad1:3; 1191 unsigned int end_of_thread:1; 1192 } dp_read; 1193 1194 struct { 1195 unsigned int binding_table_index:8; 1196 unsigned int msg_control:3; 1197 unsigned int pixel_scoreboard_clear:1; 1198 unsigned int msg_type:3; 1199 unsigned int send_commit_msg:1; 1200 unsigned int response_length:4; 1201 unsigned int msg_length:4; 1202 unsigned int msg_target:4; 1203 unsigned int pad1:3; 1204 unsigned int end_of_thread:1; 1205 } dp_write; 1206 1207 struct { 1208 unsigned int pad:16; 1209 unsigned int response_length:4; 1210 unsigned int msg_length:4; 1211 unsigned int msg_target:4; 1212 unsigned int pad1:3; 1213 unsigned int end_of_thread:1; 1214 } generic; 1215 1216 uint32_t ud; 1217 int32_t d; 1218 } bits3; 1219 }; 1220 1221 /* media pipeline */ 1222 1223 struct brw_vfe_state { 1224 struct { 1225 unsigned int per_thread_scratch_space:4; 1226 unsigned int pad3:3; 1227 unsigned int extend_vfe_state_present:1; 1228 unsigned int pad2:2; 1229 unsigned int scratch_base:22; 1230 } vfe0; 1231 1232 struct { 1233 unsigned int debug_counter_control:2; 1234 unsigned int children_present:1; 1235 unsigned int vfe_mode:4; 1236 unsigned int pad2:2; 1237 unsigned int num_urb_entries:7; 1238 unsigned int urb_entry_alloc_size:9; 1239 unsigned int max_threads:7; 1240 } vfe1; 1241 1242 struct { 1243 unsigned int pad4:4; 1244 unsigned int interface_descriptor_base:28; 1245 } vfe2; 1246 }; 1247 1248 struct brw_vld_state { 1249 struct { 1250 unsigned int pad6:6; 1251 unsigned int scan_order:1; 1252 unsigned int intra_vlc_format:1; 1253 unsigned int quantizer_scale_type:1; 1254 unsigned int concealment_motion_vector:1; 1255 unsigned int frame_predict_frame_dct:1; 1256 unsigned int top_field_first:1; 1257 unsigned int picture_structure:2; 1258 unsigned int intra_dc_precision:2; 1259 unsigned int f_code_0_0:4; 1260 unsigned int f_code_0_1:4; 1261 unsigned int f_code_1_0:4; 1262 unsigned int f_code_1_1:4; 1263 } vld0; 1264 1265 struct { 1266 unsigned int pad2:9; 1267 unsigned int picture_coding_type:2; 1268 unsigned int pad:21; 1269 } vld1; 1270 1271 struct { 1272 unsigned int index_0:4; 1273 unsigned int index_1:4; 1274 unsigned int index_2:4; 1275 unsigned int index_3:4; 1276 unsigned int index_4:4; 1277 unsigned int index_5:4; 1278 unsigned int index_6:4; 1279 unsigned int index_7:4; 1280 } desc_remap_table0; 1281 1282 struct { 1283 unsigned int index_8:4; 1284 unsigned int index_9:4; 1285 unsigned int index_10:4; 1286 unsigned int index_11:4; 1287 unsigned int index_12:4; 1288 unsigned int index_13:4; 1289 unsigned int index_14:4; 1290 unsigned int index_15:4; 1291 } desc_remap_table1; 1292 }; 1293 1294 struct brw_interface_descriptor { 1295 struct { 1296 unsigned int grf_reg_blocks:4; 1297 unsigned int pad:2; 1298 unsigned int kernel_start_pointer:26; 1299 } desc0; 1300 1301 struct { 1302 unsigned int pad:7; 1303 unsigned int software_exception:1; 1304 unsigned int pad2:3; 1305 unsigned int maskstack_exception:1; 1306 unsigned int pad3:1; 1307 unsigned int illegal_opcode_exception:1; 1308 unsigned int pad4:2; 1309 unsigned int floating_point_mode:1; 1310 unsigned int thread_priority:1; 1311 unsigned int single_program_flow:1; 1312 unsigned int pad5:1; 1313 unsigned int const_urb_entry_read_offset:6; 1314 unsigned int const_urb_entry_read_len:6; 1315 } desc1; 1316 1317 struct { 1318 unsigned int pad:2; 1319 unsigned int sampler_count:3; 1320 unsigned int sampler_state_pointer:27; 1321 } desc2; 1322 1323 struct { 1324 unsigned int binding_table_entry_count:5; 1325 unsigned int binding_table_pointer:27; 1326 } desc3; 1327 }; 1328 1329 #endif 1330