1 //! Static, named definitions of instruction opcodes. 2 3 /// Empty opcode for use as a default. 4 pub static EMPTY: [u8; 0] = []; 5 6 /// Add with carry flag r{16,32,64} to r/m of the same size. 7 pub static ADC: [u8; 1] = [0x11]; 8 9 /// Add r{16,32,64} to r/m of the same size. 10 pub static ADD: [u8; 1] = [0x01]; 11 12 /// Add imm{16,32} to r/m{16,32,64}, possibly sign-extended. 13 pub static ADD_IMM: [u8; 1] = [0x81]; 14 15 /// Add sign-extended imm8 to r/m{16,32,64}. 16 pub static ADD_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 17 18 /// Add packed double-precision floating-point values from xmm2/mem to xmm1 and store result in 19 /// xmm1 (SSE2). 20 pub static ADDPD: [u8; 3] = [0x66, 0x0f, 0x58]; 21 22 /// Add packed single-precision floating-point values from xmm2/mem to xmm1 and store result in 23 /// xmm1 (SSE). 24 pub static ADDPS: [u8; 2] = [0x0f, 0x58]; 25 26 /// Add the low double-precision floating-point value from xmm2/mem to xmm1 27 /// and store the result in xmm1. 28 pub static ADDSD: [u8; 3] = [0xf2, 0x0f, 0x58]; 29 30 /// Add the low single-precision floating-point value from xmm2/mem to xmm1 31 /// and store the result in xmm1. 32 pub static ADDSS: [u8; 3] = [0xf3, 0x0f, 0x58]; 33 34 /// r/m{16,32,64} AND register of the same size (Intel docs have a typo). 35 pub static AND: [u8; 1] = [0x21]; 36 37 /// imm{16,32} AND r/m{16,32,64}, possibly sign-extended. 38 pub static AND_IMM: [u8; 1] = [0x81]; 39 40 /// r/m{16,32,64} AND sign-extended imm8. 41 pub static AND_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 42 43 /// Return the bitwise logical AND NOT of packed single-precision floating-point 44 /// values in xmm1 and xmm2/mem. 45 pub static ANDNPS: [u8; 2] = [0x0f, 0x55]; 46 47 /// Return the bitwise logical AND of packed single-precision floating-point values 48 /// in xmm1 and xmm2/mem. 49 pub static ANDPS: [u8; 2] = [0x0f, 0x54]; 50 51 /// Bit scan forward (stores index of first encountered 1 from the front). 52 pub static BIT_SCAN_FORWARD: [u8; 2] = [0x0f, 0xbc]; 53 54 /// Bit scan reverse (stores index of first encountered 1 from the back). 55 pub static BIT_SCAN_REVERSE: [u8; 2] = [0x0f, 0xbd]; 56 57 /// Select packed single-precision floating-point values from xmm1 and xmm2/m128 58 /// from mask specified in XMM0 and store the values into xmm1 (SSE4.1). 59 pub static BLENDVPS: [u8; 4] = [0x66, 0x0f, 0x38, 0x14]; 60 61 /// Select packed double-precision floating-point values from xmm1 and xmm2/m128 62 /// from mask specified in XMM0 and store the values into xmm1 (SSE4.1). 63 pub static BLENDVPD: [u8; 4] = [0x66, 0x0f, 0x38, 0x15]; 64 65 /// Call near, relative, displacement relative to next instruction (sign-extended). 66 pub static CALL_RELATIVE: [u8; 1] = [0xe8]; 67 68 /// Move r/m{16,32,64} if overflow (OF=1). 69 pub static CMOV_OVERFLOW: [u8; 2] = [0x0f, 0x40]; 70 71 /// Compare imm{16,32} with r/m{16,32,64} (sign-extended if 64). 72 pub static CMP_IMM: [u8; 1] = [0x81]; 73 74 /// Compare imm8 with r/m{16,32,64}. 75 pub static CMP_IMM8: [u8; 1] = [0x83]; 76 77 /// Compare r{16,32,64} with r/m of the same size. 78 pub static CMP_REG: [u8; 1] = [0x39]; 79 80 /// Compare packed double-precision floating-point value in xmm2/m32 and xmm1 using bits 2:0 of 81 /// imm8 as comparison predicate (SSE2). 82 pub static CMPPD: [u8; 3] = [0x66, 0x0f, 0xc2]; 83 84 /// Compare packed single-precision floating-point value in xmm2/m32 and xmm1 using bits 2:0 of 85 /// imm8 as comparison predicate (SSE). 86 pub static CMPPS: [u8; 2] = [0x0f, 0xc2]; 87 88 /// Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision 89 /// floating-point values in xmm1 (SSE2). 90 pub static CVTDQ2PS: [u8; 2] = [0x0f, 0x5b]; 91 92 /// Convert scalar double-precision floating-point value to scalar single-precision 93 /// floating-point value. 94 pub static CVTSD2SS: [u8; 3] = [0xf2, 0x0f, 0x5a]; 95 96 /// Convert doubleword integer to scalar double-precision floating-point value. 97 pub static CVTSI2SD: [u8; 3] = [0xf2, 0x0f, 0x2a]; 98 99 /// Convert doubleword integer to scalar single-precision floating-point value. 100 pub static CVTSI2SS: [u8; 3] = [0xf3, 0x0f, 0x2a]; 101 102 /// Convert scalar single-precision floating-point value to scalar double-precision 103 /// float-point value. 104 pub static CVTSS2SD: [u8; 3] = [0xf3, 0x0f, 0x5a]; 105 106 /// Convert four packed single-precision floating-point values from xmm2/mem to four packed signed 107 /// doubleword values in xmm1 using truncation (SSE2). 108 pub static CVTTPS2DQ: [u8; 3] = [0xf3, 0x0f, 0x5b]; 109 110 /// Convert with truncation scalar double-precision floating-point value to signed 111 /// integer. 112 pub static CVTTSD2SI: [u8; 3] = [0xf2, 0x0f, 0x2c]; 113 114 /// Convert with truncation scalar single-precision floating-point value to integer. 115 pub static CVTTSS2SI: [u8; 3] = [0xf3, 0x0f, 0x2c]; 116 117 /// Unsigned divide for {16,32,64}-bit. 118 pub static DIV: [u8; 1] = [0xf7]; 119 120 /// Divide packed double-precision floating-point values in xmm1 by packed double-precision 121 /// floating-point values in xmm2/mem (SSE2). 122 pub static DIVPD: [u8; 3] = [0x66, 0x0f, 0x5e]; 123 124 /// Divide packed single-precision floating-point values in xmm1 by packed single-precision 125 /// floating-point values in xmm2/mem (SSE). 126 pub static DIVPS: [u8; 2] = [0x0f, 0x5e]; 127 128 /// Divide low double-precision floating-point value in xmm1 by low double-precision 129 /// floating-point value in xmm2/m64. 130 pub static DIVSD: [u8; 3] = [0xf2, 0x0f, 0x5e]; 131 132 /// Divide low single-precision floating-point value in xmm1 by low single-precision 133 /// floating-point value in xmm2/m32. 134 pub static DIVSS: [u8; 3] = [0xf3, 0x0f, 0x5e]; 135 136 /// Signed divide for {16,32,64}-bit. 137 pub static IDIV: [u8; 1] = [0xf7]; 138 139 /// Signed multiply for {16,32,64}-bit, generic registers. 140 pub static IMUL: [u8; 2] = [0x0f, 0xaf]; 141 142 /// Signed multiply for {16,32,64}-bit, storing into RDX:RAX. 143 pub static IMUL_RDX_RAX: [u8; 1] = [0xf7]; 144 145 /// Insert scalar single-precision floating-point value. 146 pub static INSERTPS: [u8; 4] = [0x66, 0x0f, 0x3a, 0x21]; 147 148 /// Either: 149 /// 1. Jump near, absolute indirect, RIP = 64-bit offset from register or memory. 150 /// 2. Jump far, absolute indirect, address given in m16:64. 151 pub static JUMP_ABSOLUTE: [u8; 1] = [0xff]; 152 153 /// Jump near, relative, RIP = RIP + 32-bit displacement sign extended to 64 bits. 154 pub static JUMP_NEAR_RELATIVE: [u8; 1] = [0xe9]; 155 156 /// Jump near (rel32) if overflow (OF=1). 157 pub static JUMP_NEAR_IF_OVERFLOW: [u8; 2] = [0x0f, 0x80]; 158 159 /// Jump short, relative, RIP = RIP + 8-bit displacement sign extended to 64 bits. 160 pub static JUMP_SHORT: [u8; 1] = [0xeb]; 161 162 /// Jump short (rel8) if equal (ZF=1). 163 pub static JUMP_SHORT_IF_EQUAL: [u8; 1] = [0x74]; 164 165 /// Jump short (rel8) if not equal (ZF=0). 166 pub static JUMP_SHORT_IF_NOT_EQUAL: [u8; 1] = [0x75]; 167 168 /// Jump short (rel8) if overflow (OF=1). 169 pub static JUMP_SHORT_IF_OVERFLOW: [u8; 1] = [0x70]; 170 171 /// Store effective address for m in register r{16,32,64}. 172 pub static LEA: [u8; 1] = [0x8d]; 173 174 /// Count the number of leading zero bits. 175 pub static LZCNT: [u8; 3] = [0xf3, 0x0f, 0xbd]; 176 177 /// Return the maximum packed double-precision floating-point values between xmm1 and xmm2/m128 178 /// (SSE2). 179 pub static MAXPD: [u8; 3] = [0x66, 0x0f, 0x5f]; 180 181 /// Return the maximum packed single-precision floating-point values between xmm1 and xmm2/m128 182 /// (SSE). 183 pub static MAXPS: [u8; 2] = [0x0f, 0x5f]; 184 185 /// Return the maximum scalar double-precision floating-point value between 186 /// xmm2/m64 and xmm1. 187 pub static MAXSD: [u8; 3] = [0xf2, 0x0f, 0x5f]; 188 189 /// Return the maximum scalar single-precision floating-point value between 190 /// xmm2/m32 and xmm1. 191 pub static MAXSS: [u8; 3] = [0xf3, 0x0f, 0x5f]; 192 193 /// Return the minimum packed double-precision floating-point values between xmm1 and xmm2/m128 194 /// (SSE2). 195 pub static MINPD: [u8; 3] = [0x66, 0x0f, 0x5d]; 196 197 /// Return the minimum packed single-precision floating-point values between xmm1 and xmm2/m128 198 /// (SSE). 199 pub static MINPS: [u8; 2] = [0x0f, 0x5d]; 200 201 /// Return the minimum scalar double-precision floating-point value between 202 /// xmm2/m64 and xmm1. 203 pub static MINSD: [u8; 3] = [0xf2, 0x0f, 0x5d]; 204 205 /// Return the minimum scalar single-precision floating-point value between 206 /// xmm2/m32 and xmm1. 207 pub static MINSS: [u8; 3] = [0xf3, 0x0f, 0x5d]; 208 209 /// Move r8 to r/m8. 210 pub static MOV_BYTE_STORE: [u8; 1] = [0x88]; 211 212 /// Move imm{16,32,64} to same-sized register. 213 pub static MOV_IMM: [u8; 1] = [0xb8]; 214 215 /// Move imm{16,32} to r{16,32,64}, sign-extended if 64-bit target. 216 pub static MOV_IMM_SIGNEXTEND: [u8; 1] = [0xc7]; 217 218 /// Move {r/m16, r/m32, r/m64} to same-sized register. 219 pub static MOV_LOAD: [u8; 1] = [0x8b]; 220 221 /// Move r16 to r/m16. 222 pub static MOV_STORE_16: [u8; 2] = [0x66, 0x89]; 223 224 /// Move {r16, r32, r64} to same-sized register or memory. 225 pub static MOV_STORE: [u8; 1] = [0x89]; 226 227 /// Move aligned packed single-precision floating-point values from x/m to xmm (SSE). 228 pub static MOVAPS_LOAD: [u8; 2] = [0x0f, 0x28]; 229 230 /// Move doubleword from r/m32 to xmm (SSE2). Quadword with REX prefix. 231 pub static MOVD_LOAD_XMM: [u8; 3] = [0x66, 0x0f, 0x6e]; 232 233 /// Move doubleword from xmm to r/m32 (SSE2). Quadword with REX prefix. 234 pub static MOVD_STORE_XMM: [u8; 3] = [0x66, 0x0f, 0x7e]; 235 236 /// Move packed single-precision floating-point values low to high (SSE). 237 pub static MOVLHPS: [u8; 2] = [0x0f, 0x16]; 238 239 /// Move scalar double-precision floating-point value (from reg/mem to reg). 240 pub static MOVSD_LOAD: [u8; 3] = [0xf2, 0x0f, 0x10]; 241 242 /// Move scalar double-precision floating-point value (from reg to reg/mem). 243 pub static MOVSD_STORE: [u8; 3] = [0xf2, 0x0f, 0x11]; 244 245 /// Move scalar single-precision floating-point value (from reg to reg/mem). 246 pub static MOVSS_STORE: [u8; 3] = [0xf3, 0x0f, 0x11]; 247 248 /// Move scalar single-precision floating-point-value (from reg/mem to reg). 249 pub static MOVSS_LOAD: [u8; 3] = [0xf3, 0x0f, 0x10]; 250 251 /// Move byte to register with sign-extension. 252 pub static MOVSX_BYTE: [u8; 2] = [0x0f, 0xbe]; 253 254 /// Move word to register with sign-extension. 255 pub static MOVSX_WORD: [u8; 2] = [0x0f, 0xbf]; 256 257 /// Move doubleword to register with sign-extension. 258 pub static MOVSXD: [u8; 1] = [0x63]; 259 260 /// Move unaligned packed single-precision floating-point from x/m to xmm (SSE). 261 pub static MOVUPS_LOAD: [u8; 2] = [0x0f, 0x10]; 262 263 /// Move unaligned packed single-precision floating-point value from xmm to x/m (SSE). 264 pub static MOVUPS_STORE: [u8; 2] = [0x0f, 0x11]; 265 266 /// Move byte to register with zero-extension. 267 pub static MOVZX_BYTE: [u8; 2] = [0x0f, 0xb6]; 268 269 /// Move word to register with zero-extension. 270 pub static MOVZX_WORD: [u8; 2] = [0x0f, 0xb7]; 271 272 /// Unsigned multiply for {16,32,64}-bit. 273 pub static MUL: [u8; 1] = [0xf7]; 274 275 /// Multiply packed double-precision floating-point values from xmm2/mem to xmm1 and store result 276 /// in xmm1 (SSE2). 277 pub static MULPD: [u8; 3] = [0x66, 0x0f, 0x59]; 278 279 /// Multiply packed single-precision floating-point values from xmm2/mem to xmm1 and store result 280 /// in xmm1 (SSE). 281 pub static MULPS: [u8; 2] = [0x0f, 0x59]; 282 283 /// Multiply the low double-precision floating-point value in xmm2/m64 by the 284 /// low double-precision floating-point value in xmm1. 285 pub static MULSD: [u8; 3] = [0xf2, 0x0f, 0x59]; 286 287 /// Multiply the low single-precision floating-point value in xmm2/m32 by the 288 /// low single-precision floating-point value in xmm1. 289 pub static MULSS: [u8; 3] = [0xf3, 0x0f, 0x59]; 290 291 /// Reverse each bit of r/m{16,32,64}. 292 pub static NOT: [u8; 1] = [0xf7]; 293 294 /// r{16,32,64} OR register of same size. 295 pub static OR: [u8; 1] = [0x09]; 296 297 /// imm{16,32} OR r/m{16,32,64}, possibly sign-extended. 298 pub static OR_IMM: [u8; 1] = [0x81]; 299 300 /// r/m{16,32,64} OR sign-extended imm8. 301 pub static OR_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 302 303 /// Return the bitwise logical OR of packed single-precision values in xmm and x/m (SSE). 304 pub static ORPS: [u8; 2] = [0x0f, 0x56]; 305 306 /// Compute the absolute value of bytes in xmm2/m128 and store the unsigned result in xmm1 (SSSE3). 307 pub static PABSB: [u8; 4] = [0x66, 0x0f, 0x38, 0x1c]; 308 309 /// Compute the absolute value of 32-bit integers in xmm2/m128 and store the unsigned result in 310 /// xmm1 (SSSE3). 311 pub static PABSD: [u8; 4] = [0x66, 0x0f, 0x38, 0x1e]; 312 313 /// Compute the absolute value of 16-bit integers in xmm2/m128 and store the unsigned result in 314 /// xmm1 (SSSE3). 315 pub static PABSW: [u8; 4] = [0x66, 0x0f, 0x38, 0x1d]; 316 317 /// Converts 8 packed signed word integers from xmm1 and from xmm2/m128 into 16 packed signed byte 318 /// integers in xmm1 using signed saturation (SSE2). 319 pub static PACKSSWB: [u8; 3] = [0x66, 0x0f, 0x63]; 320 321 /// Converts 4 packed signed doubleword integers from xmm1 and from xmm2/m128 into 8 packed signed 322 /// word integers in xmm1 using signed saturation (SSE2). 323 pub static PACKSSDW: [u8; 3] = [0x66, 0x0f, 0x6b]; 324 325 /// Converts 8 packed signed word integers from xmm1 and from xmm2/m128 into 16 packed unsigned byte 326 /// integers in xmm1 using unsigned saturation (SSE2). 327 pub static PACKUSWB: [u8; 3] = [0x66, 0x0f, 0x67]; 328 329 /// Converts 4 packed signed doubleword integers from xmm1 and from xmm2/m128 into 8 unpacked signed 330 /// word integers in xmm1 using unsigned saturation (SSE4.1). 331 pub static PACKUSDW: [u8; 4] = [0x66, 0x0f, 0x38, 0x2b]; 332 333 /// Add packed byte integers from xmm2/m128 and xmm1 (SSE2). 334 pub static PADDB: [u8; 3] = [0x66, 0x0f, 0xfc]; 335 336 /// Add packed doubleword integers from xmm2/m128 and xmm1 (SSE2). 337 pub static PADDD: [u8; 3] = [0x66, 0x0f, 0xfe]; 338 339 /// Add packed quadword integers from xmm2/m128 and xmm1 (SSE2). 340 pub static PADDQ: [u8; 3] = [0x66, 0x0f, 0xd4]; 341 342 /// Add packed word integers from xmm2/m128 and xmm1 (SSE2). 343 pub static PADDW: [u8; 3] = [0x66, 0x0f, 0xfd]; 344 345 /// Add packed signed byte integers from xmm2/m128 and xmm1 saturate the results (SSE). 346 pub static PADDSB: [u8; 3] = [0x66, 0x0f, 0xec]; 347 348 /// Add packed signed word integers from xmm2/m128 and xmm1 saturate the results (SSE). 349 pub static PADDSW: [u8; 3] = [0x66, 0x0f, 0xed]; 350 351 /// Add packed unsigned byte integers from xmm2/m128 and xmm1 saturate the results (SSE). 352 pub static PADDUSB: [u8; 3] = [0x66, 0x0f, 0xdc]; 353 354 /// Add packed unsigned word integers from xmm2/m128 and xmm1 saturate the results (SSE). 355 pub static PADDUSW: [u8; 3] = [0x66, 0x0f, 0xdd]; 356 357 /// Concatenate destination and source operands, extract a byte-aligned result into xmm1 that is 358 /// shifted to the right by the constant number of bytes in imm8 (SSSE3). 359 pub static PALIGNR: [u8; 4] = [0x66, 0x0f, 0x3a, 0x0f]; 360 361 /// Bitwise AND of xmm2/m128 and xmm1 (SSE2). 362 pub static PAND: [u8; 3] = [0x66, 0x0f, 0xdb]; 363 364 /// Bitwise AND NOT of xmm2/m128 and xmm1 (SSE2). 365 pub static PANDN: [u8; 3] = [0x66, 0x0f, 0xdf]; 366 367 /// Average packed unsigned byte integers from xmm2/m128 and xmm1 with rounding (SSE2). 368 pub static PAVGB: [u8; 3] = [0x66, 0x0f, 0xE0]; 369 370 /// Average packed unsigned word integers from xmm2/m128 and xmm1 with rounding (SSE2). 371 pub static PAVGW: [u8; 3] = [0x66, 0x0f, 0xE3]; 372 373 /// Select byte values from xmm1 and xmm2/m128 from mask specified in the high bit of each byte 374 /// in XMM0 and store the values into xmm1 (SSE4.1). 375 pub static PBLENDVB: [u8; 4] = [0x66, 0x0f, 0x38, 0x10]; 376 377 /// Select words from xmm1 and xmm2/m128 from mask specified in imm8 and store the values into xmm1 378 /// (SSE4.1). 379 pub static PBLENDW: [u8; 4] = [0x66, 0x0f, 0x3a, 0x0e]; 380 381 /// Compare packed data for equal (SSE2). 382 pub static PCMPEQB: [u8; 3] = [0x66, 0x0f, 0x74]; 383 384 /// Compare packed data for equal (SSE2). 385 pub static PCMPEQD: [u8; 3] = [0x66, 0x0f, 0x76]; 386 387 /// Compare packed data for equal (SSE4.1). 388 pub static PCMPEQQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x29]; 389 390 /// Compare packed data for equal (SSE2). 391 pub static PCMPEQW: [u8; 3] = [0x66, 0x0f, 0x75]; 392 393 /// Compare packed signed byte integers for greater than (SSE2). 394 pub static PCMPGTB: [u8; 3] = [0x66, 0x0f, 0x64]; 395 396 /// Compare packed signed doubleword integers for greater than (SSE2). 397 pub static PCMPGTD: [u8; 3] = [0x66, 0x0f, 0x66]; 398 399 /// Compare packed signed quadword integers for greater than (SSE4.2). 400 pub static PCMPGTQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x37]; 401 402 /// Compare packed signed word integers for greater than (SSE2). 403 pub static PCMPGTW: [u8; 3] = [0x66, 0x0f, 0x65]; 404 405 /// Extract doubleword or quadword, depending on REX.W (SSE4.1). 406 pub static PEXTR: [u8; 4] = [0x66, 0x0f, 0x3a, 0x16]; 407 408 /// Extract byte (SSE4.1). 409 pub static PEXTRB: [u8; 4] = [0x66, 0x0f, 0x3a, 0x14]; 410 411 /// Extract word (SSE4.1). There is a 3-byte SSE2 variant that can also move to m/16. 412 pub static PEXTRW: [u8; 4] = [0x66, 0x0f, 0x3a, 0x15]; 413 414 /// Insert doubleword or quadword, depending on REX.W (SSE4.1). 415 pub static PINSR: [u8; 4] = [0x66, 0x0f, 0x3a, 0x22]; 416 417 /// Insert byte (SSE4.1). 418 pub static PINSRB: [u8; 4] = [0x66, 0x0f, 0x3a, 0x20]; 419 420 /// Insert word (SSE2). 421 pub static PINSRW: [u8; 3] = [0x66, 0x0f, 0xc4]; 422 423 /// Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed maximum values in 424 /// xmm1 (SSE4.1). 425 pub static PMAXSB: [u8; 4] = [0x66, 0x0f, 0x38, 0x3c]; 426 427 /// Compare packed signed doubleword integers in xmm1 and xmm2/m128 and store packed maximum 428 /// values in xmm1 (SSE4.1). 429 pub static PMAXSD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3d]; 430 431 /// Compare packed signed word integers in xmm1 and xmm2/m128 and store packed maximum values in 432 /// xmm1 (SSE2). 433 pub static PMAXSW: [u8; 3] = [0x66, 0x0f, 0xee]; 434 435 /// Compare packed unsigned byte integers in xmm1 and xmm2/m128 and store packed maximum values in 436 /// xmm1 (SSE2). 437 pub static PMAXUB: [u8; 3] = [0x66, 0x0f, 0xde]; 438 439 /// Compare packed unsigned doubleword integers in xmm1 and xmm2/m128 and store packed maximum 440 /// values in xmm1 (SSE4.1). 441 pub static PMAXUD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3f]; 442 443 /// Compare packed unsigned word integers in xmm1 and xmm2/m128 and store packed maximum values in 444 /// xmm1 (SSE4.1). 445 pub static PMAXUW: [u8; 4] = [0x66, 0x0f, 0x38, 0x3e]; 446 447 /// Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed minimum values in 448 /// xmm1 (SSE4.1). 449 pub static PMINSB: [u8; 4] = [0x66, 0x0f, 0x38, 0x38]; 450 451 /// Compare packed signed doubleword integers in xmm1 and xmm2/m128 and store packed minimum 452 /// values in xmm1 (SSE4.1). 453 pub static PMINSD: [u8; 4] = [0x66, 0x0f, 0x38, 0x39]; 454 455 /// Compare packed signed word integers in xmm1 and xmm2/m128 and store packed minimum values in 456 /// xmm1 (SSE2). 457 pub static PMINSW: [u8; 3] = [0x66, 0x0f, 0xea]; 458 459 /// Compare packed unsigned byte integers in xmm1 and xmm2/m128 and store packed minimum values in 460 /// xmm1 (SSE2). 461 pub static PMINUB: [u8; 3] = [0x66, 0x0f, 0xda]; 462 463 /// Compare packed unsigned doubleword integers in xmm1 and xmm2/m128 and store packed minimum 464 /// values in xmm1 (SSE4.1). 465 pub static PMINUD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3b]; 466 467 /// Compare packed unsigned word integers in xmm1 and xmm2/m128 and store packed minimum values in 468 /// xmm1 (SSE4.1). 469 pub static PMINUW: [u8; 4] = [0x66, 0x0f, 0x38, 0x3a]; 470 471 /// Sign extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit 472 /// integers in xmm1 (SSE4.1). 473 pub static PMOVSXBW: [u8; 4] = [0x66, 0x0f, 0x38, 0x20]; 474 475 /// Sign extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit 476 /// integers in xmm1 (SSE4.1). 477 pub static PMOVSXWD: [u8; 4] = [0x66, 0x0f, 0x38, 0x23]; 478 479 /// Sign extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit 480 /// integers in xmm1 (SSE4.1). 481 pub static PMOVSXDQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x25]; 482 483 /// Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit 484 /// integers in xmm1 (SSE4.1). 485 pub static PMOVZXBW: [u8; 4] = [0x66, 0x0f, 0x38, 0x30]; 486 487 /// Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit 488 /// integers in xmm1 (SSE4.1). 489 pub static PMOVZXWD: [u8; 4] = [0x66, 0x0f, 0x38, 0x33]; 490 491 /// Zero extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit 492 /// integers in xmm1 (SSE4.1). 493 pub static PMOVZXDQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x35]; 494 495 /// Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the low 16 bits of 496 /// the results in xmm1 (SSE2). 497 pub static PMULLW: [u8; 3] = [0x66, 0x0f, 0xd5]; 498 499 /// Multiply the packed doubleword signed integers in xmm1 and xmm2/m128 and store the low 32 500 /// bits of each product in xmm1 (SSE4.1). 501 pub static PMULLD: [u8; 4] = [0x66, 0x0f, 0x38, 0x40]; 502 503 /// Multiply the packed quadword signed integers in xmm2 and xmm3/m128 and store the low 64 504 /// bits of each product in xmm1 (AVX512VL/DQ). Requires an EVEX encoding. 505 pub static VPMULLQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x40]; 506 507 /// Multiply packed unsigned doubleword integers in xmm1 by packed unsigned doubleword integers 508 /// in xmm2/m128, and store the quadword results in xmm1 (SSE2). 509 pub static PMULUDQ: [u8; 3] = [0x66, 0x0f, 0xf4]; 510 511 /// Multiply the packed word integers, add adjacent doubleword results. 512 pub static PMADDWD: [u8; 3] = [0x66, 0x0f, 0xf5]; 513 514 /// Pop top of stack into r{16,32,64}; increment stack pointer. 515 pub static POP_REG: [u8; 1] = [0x58]; 516 517 /// Returns the count of number of bits set to 1. 518 pub static POPCNT: [u8; 3] = [0xf3, 0x0f, 0xb8]; 519 520 /// Bitwise OR of xmm2/m128 and xmm1 (SSE2). 521 pub static POR: [u8; 3] = [0x66, 0x0f, 0xeb]; 522 523 /// Shuffle bytes in xmm1 according to contents of xmm2/m128 (SSE3). 524 pub static PSHUFB: [u8; 4] = [0x66, 0x0f, 0x38, 0x00]; 525 526 /// Shuffle the doublewords in xmm2/m128 based on the encoding in imm8 and 527 /// store the result in xmm1 (SSE2). 528 pub static PSHUFD: [u8; 3] = [0x66, 0x0f, 0x70]; 529 530 /// Shift words in xmm1 by imm8; the direction and sign-bit behavior is controlled by the RRR 531 /// digit used in the ModR/M byte (SSE2). 532 pub static PS_W_IMM: [u8; 3] = [0x66, 0x0f, 0x71]; 533 534 /// Shift doublewords in xmm1 by imm8; the direction and sign-bit behavior is controlled by the RRR 535 /// digit used in the ModR/M byte (SSE2). 536 pub static PS_D_IMM: [u8; 3] = [0x66, 0x0f, 0x72]; 537 538 /// Shift quadwords in xmm1 by imm8; the direction and sign-bit behavior is controlled by the RRR 539 /// digit used in the ModR/M byte (SSE2). 540 pub static PS_Q_IMM: [u8; 3] = [0x66, 0x0f, 0x73]; 541 542 /// Shift words in xmm1 left by xmm2/m128 while shifting in 0s (SSE2). 543 pub static PSLLW: [u8; 3] = [0x66, 0x0f, 0xf1]; 544 545 /// Shift doublewords in xmm1 left by xmm2/m128 while shifting in 0s (SSE2). 546 pub static PSLLD: [u8; 3] = [0x66, 0x0f, 0xf2]; 547 548 /// Shift quadwords in xmm1 left by xmm2/m128 while shifting in 0s (SSE2). 549 pub static PSLLQ: [u8; 3] = [0x66, 0x0f, 0xf3]; 550 551 /// Shift words in xmm1 right by xmm2/m128 while shifting in 0s (SSE2). 552 pub static PSRLW: [u8; 3] = [0x66, 0x0f, 0xd1]; 553 554 /// Shift doublewords in xmm1 right by xmm2/m128 while shifting in 0s (SSE2). 555 pub static PSRLD: [u8; 3] = [0x66, 0x0f, 0xd2]; 556 557 /// Shift quadwords in xmm1 right by xmm2/m128 while shifting in 0s (SSE2). 558 pub static PSRLQ: [u8; 3] = [0x66, 0x0f, 0xd3]; 559 560 /// Shift words in xmm1 right by xmm2/m128 while shifting in sign bits (SSE2). 561 pub static PSRAW: [u8; 3] = [0x66, 0x0f, 0xe1]; 562 563 /// Shift doublewords in xmm1 right by xmm2/m128 while shifting in sign bits (SSE2). 564 pub static PSRAD: [u8; 3] = [0x66, 0x0f, 0xe2]; 565 566 /// Subtract packed byte integers in xmm2/m128 from packed byte integers in xmm1 (SSE2). 567 pub static PSUBB: [u8; 3] = [0x66, 0x0f, 0xf8]; 568 569 /// Subtract packed word integers in xmm2/m128 from packed word integers in xmm1 (SSE2). 570 pub static PSUBW: [u8; 3] = [0x66, 0x0f, 0xf9]; 571 572 /// Subtract packed doubleword integers in xmm2/m128 from doubleword byte integers in xmm1 (SSE2). 573 pub static PSUBD: [u8; 3] = [0x66, 0x0f, 0xfa]; 574 575 /// Subtract packed quadword integers in xmm2/m128 from xmm1 (SSE2). 576 pub static PSUBQ: [u8; 3] = [0x66, 0x0f, 0xfb]; 577 578 /// Subtract packed signed byte integers in xmm2/m128 from packed signed byte integers in xmm1 579 /// and saturate results (SSE2). 580 pub static PSUBSB: [u8; 3] = [0x66, 0x0f, 0xe8]; 581 582 /// Subtract packed signed word integers in xmm2/m128 from packed signed word integers in xmm1 583 /// and saturate results (SSE2). 584 pub static PSUBSW: [u8; 3] = [0x66, 0x0f, 0xe9]; 585 586 /// Subtract packed unsigned byte integers in xmm2/m128 from packed unsigned byte integers in xmm1 587 /// and saturate results (SSE2). 588 pub static PSUBUSB: [u8; 3] = [0x66, 0x0f, 0xd8]; 589 590 /// Subtract packed unsigned word integers in xmm2/m128 from packed unsigned word integers in xmm1 591 /// and saturate results (SSE2). 592 pub static PSUBUSW: [u8; 3] = [0x66, 0x0f, 0xd9]; 593 594 /// Set ZF if xmm2/m128 AND xmm1 result is all 0s; set CF if xmm2/m128 AND NOT xmm1 result is all 595 /// 0s (SSE4.1). 596 pub static PTEST: [u8; 4] = [0x66, 0x0f, 0x38, 0x17]; 597 598 /// Unpack and interleave high-order bytes from xmm1 and xmm2/m128 into xmm1 (SSE2). 599 pub static PUNPCKHBW: [u8; 3] = [0x66, 0x0f, 0x68]; 600 601 /// Unpack and interleave high-order words from xmm1 and xmm2/m128 into xmm1 (SSE2). 602 pub static PUNPCKHWD: [u8; 3] = [0x66, 0x0f, 0x69]; 603 604 /// Unpack and interleave high-order doublewords from xmm1 and xmm2/m128 into xmm1 (SSE2). 605 pub static PUNPCKHDQ: [u8; 3] = [0x66, 0x0f, 0x6A]; 606 607 /// Unpack and interleave high-order quadwords from xmm1 and xmm2/m128 into xmm1 (SSE2). 608 pub static PUNPCKHQDQ: [u8; 3] = [0x66, 0x0f, 0x6D]; 609 610 /// Unpack and interleave low-order bytes from xmm1 and xmm2/m128 into xmm1 (SSE2). 611 pub static PUNPCKLBW: [u8; 3] = [0x66, 0x0f, 0x60]; 612 613 /// Unpack and interleave low-order words from xmm1 and xmm2/m128 into xmm1 (SSE2). 614 pub static PUNPCKLWD: [u8; 3] = [0x66, 0x0f, 0x61]; 615 616 /// Unpack and interleave low-order doublewords from xmm1 and xmm2/m128 into xmm1 (SSE2). 617 pub static PUNPCKLDQ: [u8; 3] = [0x66, 0x0f, 0x62]; 618 619 /// Unpack and interleave low-order quadwords from xmm1 and xmm2/m128 into xmm1 (SSE2). 620 pub static PUNPCKLQDQ: [u8; 3] = [0x66, 0x0f, 0x6C]; 621 622 /// Push r{16,32,64}. 623 pub static PUSH_REG: [u8; 1] = [0x50]; 624 625 /// Logical exclusive OR (SSE2). 626 pub static PXOR: [u8; 3] = [0x66, 0x0f, 0xef]; 627 628 /// Near return to calling procedure. 629 pub static RET_NEAR: [u8; 1] = [0xc3]; 630 631 /// General rotation opcode. Kind of rotation depends on encoding. 632 pub static ROTATE_CL: [u8; 1] = [0xd3]; 633 634 /// General rotation opcode. Kind of rotation depends on encoding. 635 pub static ROTATE_IMM8: [u8; 1] = [0xc1]; 636 637 /// Round scalar doubl-precision floating-point values. 638 pub static ROUNDSD: [u8; 4] = [0x66, 0x0f, 0x3a, 0x0b]; 639 640 /// Round scalar single-precision floating-point values. 641 pub static ROUNDSS: [u8; 4] = [0x66, 0x0f, 0x3a, 0x0a]; 642 643 /// Subtract with borrow r{16,32,64} from r/m of the same size. 644 pub static SBB: [u8; 1] = [0x19]; 645 646 /// Set byte if overflow (OF=1). 647 pub static SET_BYTE_IF_OVERFLOW: [u8; 2] = [0x0f, 0x90]; 648 649 /// Compute the square root of the packed double-precision floating-point values and store the 650 /// result in xmm1 (SSE2). 651 pub static SQRTPD: [u8; 3] = [0x66, 0x0f, 0x51]; 652 653 /// Compute the square root of the packed double-precision floating-point values and store the 654 /// result in xmm1 (SSE). 655 pub static SQRTPS: [u8; 2] = [0x0f, 0x51]; 656 657 /// Compute square root of scalar double-precision floating-point value. 658 pub static SQRTSD: [u8; 3] = [0xf2, 0x0f, 0x51]; 659 660 /// Compute square root of scalar single-precision value. 661 pub static SQRTSS: [u8; 3] = [0xf3, 0x0f, 0x51]; 662 663 /// Subtract r{16,32,64} from r/m of same size. 664 pub static SUB: [u8; 1] = [0x29]; 665 666 /// Subtract packed double-precision floating-point values in xmm2/mem from xmm1 and store result 667 /// in xmm1 (SSE2). 668 pub static SUBPD: [u8; 3] = [0x66, 0x0f, 0x5c]; 669 670 /// Subtract packed single-precision floating-point values in xmm2/mem from xmm1 and store result 671 /// in xmm1 (SSE). 672 pub static SUBPS: [u8; 2] = [0x0f, 0x5c]; 673 674 /// Subtract the low double-precision floating-point value in xmm2/m64 from xmm1 675 /// and store the result in xmm1. 676 pub static SUBSD: [u8; 3] = [0xf2, 0x0f, 0x5c]; 677 678 /// Subtract the low single-precision floating-point value in xmm2/m32 from xmm1 679 /// and store the result in xmm1. 680 pub static SUBSS: [u8; 3] = [0xf3, 0x0f, 0x5c]; 681 682 /// AND r8 with r/m8; set SF, ZF, PF according to result. 683 pub static TEST_BYTE_REG: [u8; 1] = [0x84]; 684 685 /// AND {r16, r32, r64} with r/m of the same size; set SF, ZF, PF according to result. 686 pub static TEST_REG: [u8; 1] = [0x85]; 687 688 /// Count the number of trailing zero bits. 689 pub static TZCNT: [u8; 3] = [0xf3, 0x0f, 0xbc]; 690 691 /// Compare low double-precision floating-point values in xmm1 and xmm2/mem64 692 /// and set the EFLAGS flags accordingly. 693 pub static UCOMISD: [u8; 3] = [0x66, 0x0f, 0x2e]; 694 695 /// Compare low single-precision floating-point values in xmm1 and xmm2/mem32 696 /// and set the EFLAGS flags accordingly. 697 pub static UCOMISS: [u8; 2] = [0x0f, 0x2e]; 698 699 /// Raise invalid opcode instruction. 700 pub static UNDEFINED2: [u8; 2] = [0x0f, 0x0b]; 701 702 /// Convert four packed unsigned doubleword integers from xmm2/m128/m32bcst to packed 703 /// single-precision floating-point values in xmm1 with writemask k1. Rounding behavior 704 /// is controlled by MXCSR but can be overriden by EVEX.L'L in static rounding mode 705 /// (AVX512VL, AVX512F). 706 pub static VCVTUDQ2PS: [u8; 3] = [0xf2, 0x0f, 0x7a]; 707 708 /// imm{16,32} XOR r/m{16,32,64}, possibly sign-extended. 709 pub static XOR_IMM: [u8; 1] = [0x81]; 710 711 /// r/m{16,32,64} XOR sign-extended imm8. 712 pub static XOR_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 713 714 /// r/m{16,32,64} XOR register of the same size. 715 pub static XOR: [u8; 1] = [0x31]; 716 717 /// Bitwise logical XOR of packed double-precision floating-point values. 718 pub static XORPD: [u8; 3] = [0x66, 0x0f, 0x57]; 719 720 /// Bitwise logical XOR of packed single-precision floating-point values. 721 pub static XORPS: [u8; 2] = [0x0f, 0x57]; 722