1Copyright 2000, 2001 Free Software Foundation, Inc. 2 3This file is part of the GNU MP Library. 4 5The GNU MP Library is free software; you can redistribute it and/or modify 6it under the terms of either: 7 8 * the GNU Lesser General Public License as published by the Free 9 Software Foundation; either version 3 of the License, or (at your 10 option) any later version. 11 12or 13 14 * the GNU General Public License as published by the Free Software 15 Foundation; either version 2 of the License, or (at your option) any 16 later version. 17 18or both in parallel, as here. 19 20The GNU MP Library is distributed in the hope that it will be useful, but 21WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 22or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 23for more details. 24 25You should have received copies of the GNU General Public License and the 26GNU Lesser General Public License along with the GNU MP Library. If not, 27see https://www.gnu.org/licenses/. 28 29 30 31 32 33 INTEL P6 MPN SUBROUTINES 34 35 36 37This directory contains code optimized for Intel P6 class CPUs, meaning 38PentiumPro, Pentium II and Pentium III. The mmx and p3mmx subdirectories 39have routines using MMX instructions. 40 41 42 43STATUS 44 45Times for the loops, with all code and data in L1 cache, are as follows. 46Some of these might be able to be improved. 47 48 cycles/limb 49 50 mpn_add_n/sub_n 3.7 51 52 mpn_copyi 0.75 53 mpn_copyd 1.75 (or 0.75 if no overlap) 54 55 mpn_divrem_1 39.0 56 mpn_mod_1 21.5 57 mpn_divexact_by3 8.5 58 59 mpn_mul_1 5.5 60 mpn_addmul/submul_1 6.35 61 62 mpn_l/rshift 2.5 63 64 mpn_mul_basecase 8.2 cycles/crossproduct (approx) 65 mpn_sqr_basecase 4.0 cycles/crossproduct (approx) 66 or 7.75 cycles/triangleproduct (approx) 67 68Pentium II and III have MMX and get the following improvements. 69 70 mpn_divrem_1 25.0 integer part, 17.5 fractional part 71 72 mpn_l/rshift 1.75 73 74 75 76 77NOTES 78 79Write-allocate L1 data cache means prefetching of destinations is unnecessary. 80 81Mispredicted branches have a penalty of between 9 and 15 cycles, and even up 82to 26 cycles depending how far speculative execution has gone. The 9 cycle 83minimum penalty comes from the issue pipeline being 9 stages. 84 85A copy with rep movs seems to copy 16 bytes at a time, since speeds for 4, 865, 6 or 7 limb operations are all the same. The 0.75 cycles/limb would be 3 87cycles per 16 byte block. 88 89 90 91 92CODING 93 94Instructions in general code have been shown grouped if they can execute 95together, which means up to three instructions with no successive 96dependencies, and with only the first being a multiple micro-op. 97 98P6 has out-of-order execution, so the groupings are really only showing 99dependent paths where some shuffling might allow some latencies to be 100hidden. 101 102 103 104 105REFERENCES 106 107"Intel Architecture Optimization Reference Manual", 1999, revision 001 dated 10802/99, order number 245127 (order number 730795-001 is in the document too). 109Available on-line: 110 111 http://download.intel.com/design/PentiumII/manuals/245127.htm 112 113"Intel Architecture Optimization Manual", 1997, order number 242816. This 114is an older document mostly about P5 and not as good as the above. 115Available on-line: 116 117 http://download.intel.com/design/PentiumII/manuals/242816.htm 118 119 120 121---------------- 122Local variables: 123mode: text 124fill-column: 76 125End: 126