1# CPU, FPU and architecture specifications for ARM. 2# 3# Copyright (C) 2011-2021 Free Software Foundation, Inc. 4# 5# This file is part of GCC. 6# 7# GCC is free software; you can redistribute it and/or modify it under 8# the terms of the GNU General Public License as published by the Free 9# Software Foundation; either version 3, or (at your option) any later 10# version. 11# 12# GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13# WARRANTY; without even the implied warranty of MERCHANTABILITY or 14# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15# for more details. 16# 17# You should have received a copy of the GNU General Public License 18# along with GCC; see the file COPYING3. If not see 19# <http://www.gnu.org/licenses/>. 20 21# This file describes all the various CPUs, FPUs and architectures supported 22# by the compiler. It is pre-processed by parsecpu.awk for a number of 23# purposes. 24# 25# The general form is a sequence of begin..end blocks with the following 26# syntax: 27# begin <object-type> <name> 28# attribute-statement* 29# end <object-type> <name> 30# 31# where object type is one of "cpu" "arch" "fpu". Each object type has 32# a specific set of permitted attributes, some of which are optional; further 33# details can be found below. 34# 35# Some objects cross-reference other objects by name. Objects are permitted 36# in any order and it is not necessary to place a cross-referenced object 37# earlier in the file. 38# 39# The object names for cpu, arch and fpu objects are used for the public option 40# names in the final compiler. The order within each group is preserved and 41# forms the order for the list within the compiler. 42 43# Most objects in this file support forward references. The major 44# exception is feature groups, which may only refer to previously 45# defined features or feature groups. This is done to avoid the risk 46# of feature groups recursively referencing each other and causing 47# the parser to hang. 48 49# Features - general convention: all lower case. 50 51# Architecture rel 4 52define feature armv4 53 54# Thumb aware. 55define feature thumb 56 57# Architecture rel 5t. 58define feature armv5t 59 60# Architecture rel 5te. 61define feature armv5te 62 63# XScale. 64define feature xscale 65 66# Architecture rel 6. 67define feature armv6 68 69# Architecture rel 6k. 70define feature armv6k 71 72# Thumb-2. 73define feature thumb2 74 75# Instructions not present in 'M' profile. 76define feature notm 77 78# Architecture uses be8 mode in big-endian. 79define feature be8 80 81# Thumb division instructions. 82define feature tdiv 83 84# Architecture rel 7e-m. 85define feature armv7em 86 87# Architecture rel 7. 88define feature armv7 89 90# MP extension to ArmV7-A 91define feature mp 92 93# SEC extension to ArmV7-A 94define feature sec 95 96# ARM division instructions. 97define feature adiv 98 99# Architecture rel 8. 100define feature armv8 101 102# ARMv8 CRC32 instructions. 103define feature crc32 104 105# XScale v2 (Wireless MMX). 106define feature iwmmxt 107 108# XScale Wireless MMX2. 109define feature iwmmxt2 110 111# Architecture rel 8.1. 112define feature armv8_1 113 114# Architecture rel 8.2. 115define feature armv8_2 116 117# Architecture rel 8.3. 118define feature armv8_3 119 120# Architecture rel 8.4. 121define feature armv8_4 122 123# Architecture rel 8.5. 124define feature armv8_5 125 126# Architecture rel 8.6. 127define feature armv8_6 128 129# M-Profile security extensions. 130define feature cmse 131 132# Architecture rel 8.1-M. 133define feature armv8_1m_main 134 135# Floating point and Neon extensions. 136# VFPv1 is not supported in GCC. 137 138# Vector floating point v2. 139define feature vfpv2 140 141# Vector floating point v3. 142define feature vfpv3 143 144# Vector floating point v4. 145define feature vfpv4 146 147# Floating point v5. 148define feature fpv5 149 150# ARMv7-A LPAE. 151define feature lpae 152 153# Advanced SIMD instructions. 154define feature neon 155 156# Conversions to/from fp16 (VFPv3 extension). 157define feature fp16conv 158 159# Double precision operations supported. 160define feature fp_dbl 161 162# 32 Double precision registers. 163define feature fp_d32 164 165# Crypto extension to ARMv8. 166define feature crypto 167 168# FP16 data processing (half-precision float). 169define feature fp16 170 171# Dot Product instructions extension to ARMv8.2-a. 172define feature dotprod 173 174# Half-precision floating-point instructions in ARMv8.4-A. 175define feature fp16fml 176 177# ISA Quirks (errata?). Don't forget to add this to the fgroup 178# ALL_QUIRKS below. 179 180# No volatile memory in IT blocks. 181define feature quirk_no_volatile_ce 182 183# Previously mis-identified by GCC. 184define feature quirk_armv6kz 185 186# Cortex-M3 LDRD quirk. 187define feature quirk_cm3_ldrd 188 189# Don't use .cpu assembly directive 190define feature quirk_no_asmcpu 191 192# (Very) slow multiply operations. Should probably be a tuning bit. 193define feature smallmul 194 195# Speculation Barrier Instruction for v8-A architectures, added by 196# default to v8.5-A 197define feature sb 198 199# Execution and Data Prediction Restriction Instruction for 200# v8-A architectures, added by default from v8.5-A 201define feature predres 202 203# M-profile Vector Extension feature bits 204define feature mve 205define feature mve_float 206 207# 8-bit Integer Matrix Multiply extension. Optional from v8.2-A. 208define feature i8mm 209 210# Brain half-precision floating-point extension. Optional from v8.2-A. 211define feature bf16 212 213# Arm Custom Datapath Extension (CDE). 214define feature cdecp0 215define feature cdecp1 216define feature cdecp2 217define feature cdecp3 218define feature cdecp4 219define feature cdecp5 220define feature cdecp6 221define feature cdecp7 222 223# Feature groups. Conventionally all (or mostly) upper case. 224# ALL_FPU lists all the feature bits associated with the floating-point 225# unit; these will all be removed if the floating-point unit is disabled 226# (eg -mfloat-abi=soft). ALL_FPU_INTERNAL must ONLY contain features that 227# form part of a named -mfpu option; it is used to map the capabilities 228# back to a named FPU for the benefit of the assembler. 229# 230# ALL_SIMD_INTERNAL and ALL_SIMD are similarly defined to help with the 231# construction of ALL_FPU and ALL_FPU_INTERNAL; they describe the SIMD 232# extensions that are either part of a named FPU or optional extensions 233# respectively. 234 235 236# List of all cryptographic extensions to stripout if crypto is 237# disabled. Currently, that's trivial, but we define it anyway for 238# consistency with the SIMD and FP disable lists. 239define fgroup ALL_CRYPTO crypto 240 241# List of all SIMD bits to strip out if SIMD is disabled. This does 242# strip off 32 D-registers, but does not remove support for 243# double-precision FP. 244define fgroup ALL_SIMD_INTERNAL fp_d32 neon ALL_CRYPTO 245define fgroup ALL_SIMD_EXTERNAL dotprod fp16fml i8mm 246define fgroup ALL_SIMD ALL_SIMD_INTERNAL ALL_SIMD_EXTERNAL 247 248# List of all FPU bits to strip out if -mfpu is used to override the 249# default. fp16 is deliberately missing from this list. 250define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL 251# Similarly, but including fp16 and other extensions that aren't part of 252# -mfpu support. 253define fgroup ALL_FPU_EXTERNAL fp16 bf16 254 255# Everything related to the FPU extensions (FP or SIMD). 256define fgroup ALL_FP ALL_FPU_EXTERNAL ALL_FPU_INTERNAL ALL_SIMD 257 258define fgroup ARMv4 armv4 notm 259define fgroup ARMv4t ARMv4 thumb 260define fgroup ARMv5t ARMv4t armv5t 261define fgroup ARMv5te ARMv5t armv5te 262define fgroup ARMv5tej ARMv5te 263define fgroup ARMv6 ARMv5te armv6 be8 264define fgroup ARMv6j ARMv6 265define fgroup ARMv6k ARMv6 armv6k 266define fgroup ARMv6z ARMv6 267define fgroup ARMv6kz ARMv6k quirk_armv6kz 268define fgroup ARMv6zk ARMv6k 269define fgroup ARMv6t2 ARMv6 thumb2 270# This is suspect. ARMv6-m doesn't really pull in any useful features 271# from ARMv5* or ARMv6. 272define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8 273# This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and 274# integer SIMD instructions that are in ARMv6T2. */ 275define fgroup ARMv7 ARMv6m thumb2 armv7 276 277define fgroup ARMv7a ARMv7 notm armv6k 278define fgroup ARMv7ve ARMv7a adiv tdiv lpae mp sec 279define fgroup ARMv7r ARMv7a tdiv 280define fgroup ARMv7m ARMv7 tdiv 281define fgroup ARMv7em ARMv7m armv7em 282define fgroup ARMv8a ARMv7ve armv8 283define fgroup ARMv8_1a ARMv8a crc32 armv8_1 284define fgroup ARMv8_2a ARMv8_1a armv8_2 285define fgroup ARMv8_3a ARMv8_2a armv8_3 286define fgroup ARMv8_4a ARMv8_3a armv8_4 287define fgroup ARMv8_5a ARMv8_4a armv8_5 sb predres 288define fgroup ARMv8_6a ARMv8_5a armv8_6 289define fgroup ARMv8m_base ARMv6m armv8 cmse tdiv 290define fgroup ARMv8m_main ARMv7m armv8 cmse 291define fgroup ARMv8r ARMv8a 292define fgroup ARMv8_1m_main ARMv8m_main armv8_1m_main 293 294# Useful combinations. 295define fgroup VFPv2 vfpv2 296define fgroup VFPv3 VFPv2 vfpv3 297define fgroup VFPv4 VFPv3 vfpv4 fp16conv 298define fgroup FPv5 VFPv4 fpv5 299define fgroup MVE mve armv7em 300define fgroup MVE_FP MVE FPv5 fp16 mve_float 301 302define fgroup FP_DBL fp_dbl 303define fgroup FP_D32 FP_DBL fp_d32 304define fgroup FP_ARMv8 FPv5 FP_D32 305define fgroup NEON FP_D32 neon 306define fgroup CRYPTO NEON crypto 307define fgroup DOTPROD NEON dotprod 308 309# Implied feature bits. These are for non-named features shared between fgroups. 310# Shared feature f belonging to fgroups A and B will be erroneously removed if: 311# A and B are enabled by default AND A is disabled by a removal flag. 312# To ensure that f is retained, we must add such bits to the ISA after 313# processing the removal flags. This is implemented by 'implied bits': 314# define implied <name> [<feature-or-fgroup>]+ 315# This indicates that, if any of the listed features are enabled, or if any 316# member of a listed fgroup is enabled, then <name> will be implicitly enabled. 317 318# Enabled for all VFP, MVE and MVE with floating point extensions. 319define implied vfp_base MVE MVE_FP ALL_FP 320 321# List of all quirk bits to strip out when comparing CPU features with 322# architectures. 323# xscale isn't really a 'quirk', but it isn't an architecture either and we 324# need to ignore it for matching purposes. 325define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd xscale quirk_no_asmcpu 326 327define fgroup IGNORE_FOR_MULTILIB cdecp0 cdecp1 cdecp2 cdecp3 cdecp4 cdecp5 cdecp6 cdecp7 328 329# Architecture entries 330# format: 331# begin arch <name> 332# tune for <cpu> 333# [tune flags <list>] 334# base <name> 335# [profile <A|R|M>] 336# isa <isa-flags-list> 337# end arch <name> 338# 339 340begin arch armv4 341 tune for arm7tdmi 342 tune flags CO_PROC 343 base 4 344 isa ARMv4 345end arch armv4 346 347begin arch armv4t 348 tune for arm7tdmi 349 tune flags CO_PROC 350 base 4T 351 isa ARMv4t 352end arch armv4t 353 354begin arch armv5t 355 tune for arm10tdmi 356 tune flags CO_PROC 357 base 5T 358 isa ARMv5t 359end arch armv5t 360 361begin arch armv5te 362 tune for arm1026ej-s 363 tune flags CO_PROC 364 base 5TE 365 isa ARMv5te 366 option fp add VFPv2 FP_DBL 367 optalias vfpv2 fp 368 option nofp remove ALL_FP 369end arch armv5te 370 371begin arch armv5tej 372 tune for arm1026ej-s 373 tune flags CO_PROC 374 base 5TEJ 375 isa ARMv5tej 376 option fp add VFPv2 FP_DBL 377 optalias vfpv2 fp 378 option nofp remove ALL_FP 379end arch armv5tej 380 381begin arch armv6 382 tune for arm1136j-s 383 tune flags CO_PROC 384 base 6 385 isa ARMv6 386 option fp add VFPv2 FP_DBL 387 optalias vfpv2 fp 388 option nofp remove ALL_FP 389end arch armv6 390 391begin arch armv6j 392 tune for arm1136j-s 393 tune flags CO_PROC 394 base 6J 395 isa ARMv6j 396 option fp add VFPv2 FP_DBL 397 optalias vfpv2 fp 398 option nofp remove ALL_FP 399end arch armv6j 400 401begin arch armv6k 402 tune for mpcore 403 tune flags CO_PROC 404 base 6K 405 isa ARMv6k 406 option fp add VFPv2 FP_DBL 407 optalias vfpv2 fp 408 option nofp remove ALL_FP 409end arch armv6k 410 411begin arch armv6z 412 tune for arm1176jz-s 413 tune flags CO_PROC 414 base 6Z 415 isa ARMv6z 416 option fp add VFPv2 FP_DBL 417 optalias vfpv2 fp 418 option nofp remove ALL_FP 419end arch armv6z 420 421begin arch armv6kz 422 tune for arm1176jz-s 423 tune flags CO_PROC 424 base 6KZ 425 isa ARMv6kz 426 option fp add VFPv2 FP_DBL 427 optalias vfpv2 fp 428 option nofp remove ALL_FP 429end arch armv6kz 430 431begin arch armv6zk 432 tune for arm1176jz-s 433 tune flags CO_PROC 434 base 6KZ 435 isa ARMv6kz 436 option fp add VFPv2 FP_DBL 437 optalias vfpv2 fp 438 option nofp remove ALL_FP 439end arch armv6zk 440 441begin arch armv6t2 442 tune for arm1156t2-s 443 tune flags CO_PROC 444 base 6T2 445 isa ARMv6t2 446 option fp add VFPv2 FP_DBL 447 optalias vfpv2 fp 448 option nofp remove ALL_FP 449end arch armv6t2 450 451begin arch armv6-m 452 tune for cortex-m1 453 base 6M 454 profile M 455 isa ARMv6m 456end arch armv6-m 457 458# This is now equivalent to armv6-m, but we keep it because some 459# versions of GAS still distinguish between the two. 460begin arch armv6s-m 461 tune for cortex-m1 462 base 6M 463 profile M 464 isa ARMv6m 465end arch armv6s-m 466 467begin arch armv7 468 tune for cortex-a53 469 tune flags CO_PROC 470 base 7 471 isa ARMv7 472# fp => VFPv3-d16 (only useful for the A+R profile subset). 473 option fp add VFPv3 FP_DBL 474 optalias vfpv3-d16 fp 475 option nofp remove ALL_FP 476end arch armv7 477 478begin arch armv7-a 479 tune for cortex-a53 480 tune flags CO_PROC 481 base 7A 482 profile A 483 isa ARMv7a 484 option mp add mp 485 option sec add sec 486# fp => VFPv3-d16, simd => neon-vfpv3 487 option fp add VFPv3 FP_DBL 488 optalias vfpv3-d16 fp 489 option vfpv3 add VFPv3 FP_D32 490 option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 491 option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 fp16conv 492 option vfpv4-d16 add VFPv4 FP_DBL 493 option vfpv4 add VFPv4 FP_D32 494 option simd add VFPv3 NEON 495 optalias neon simd 496 optalias neon-vfpv3 simd 497 option neon-fp16 add VFPv3 NEON fp16conv 498 option neon-vfpv4 add VFPv4 NEON 499 option nosimd remove ALL_SIMD 500 option nofp remove ALL_FP 501end arch armv7-a 502 503begin arch armv7ve 504 tune for cortex-a53 505 tune flags CO_PROC 506 base 7A 507 profile A 508 isa ARMv7ve 509# fp => VFPv4-d16, simd => neon-vfpv4 510 option vfpv3-d16 add VFPv3 FP_DBL 511 option vfpv3 add VFPv3 FP_D32 512 option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 513 option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 fp16conv 514 option fp add VFPv4 FP_DBL 515 optalias vfpv4-d16 fp 516 option vfpv4 add VFPv4 FP_D32 517 option neon add VFPv3 NEON 518 optalias neon-vfpv3 neon 519 option neon-fp16 add VFPv3 NEON fp16conv 520 option simd add VFPv4 NEON 521 optalias neon-vfpv4 simd 522 option nosimd remove ALL_SIMD 523 option nofp remove ALL_FP 524end arch armv7ve 525 526begin arch armv7-r 527 tune for cortex-r4 528 tune flags CO_PROC 529 base 7R 530 profile R 531 isa ARMv7r 532# ARMv7-r uses VFPv3-d16 533 option fp.sp add VFPv3 534 optalias vfpv3xd fp.sp 535 option fp add VFPv3 FP_DBL 536 optalias vfpv3-d16 fp 537 option vfpv3xd-fp16 add VFPv3 fp16conv 538 option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 539 option idiv add adiv 540 option nofp remove ALL_FP 541 option noidiv remove adiv 542end arch armv7-r 543 544begin arch armv7-m 545 tune for cortex-m3 546 tune flags CO_PROC 547 base 7M 548 profile M 549 isa ARMv7m 550# In theory FP is permitted in v7-m, but in practice no implementations exist. 551# leave it out for now. 552end arch armv7-m 553 554begin arch armv7e-m 555 tune for cortex-m4 556 tune flags CO_PROC 557 base 7EM 558 profile M 559 isa ARMv7em 560# fp => VFPv4-sp-d16; fpv5 => FPv5-sp-d16; fp.dp => FPv5-d16 561 option fp add VFPv4 562 optalias vfpv4-sp-d16 fp 563 option fpv5 add FPv5 564 option fp.dp add FPv5 FP_DBL 565 optalias fpv5-d16 fp.dp 566 option nofp remove ALL_FP 567end arch armv7e-m 568 569begin arch armv8-a 570 tune for cortex-a53 571 tune flags CO_PROC 572 base 8A 573 profile A 574 isa ARMv8a 575 option crc add crc32 576 option simd add FP_ARMv8 NEON 577 option crypto add FP_ARMv8 CRYPTO 578 option nocrypto remove ALL_CRYPTO 579 option nofp remove ALL_FP 580 option sb add sb 581 option predres add predres 582end arch armv8-a 583 584begin arch armv8.1-a 585 tune for cortex-a53 586 tune flags CO_PROC 587 base 8A 588 profile A 589 isa ARMv8_1a 590 option simd add FP_ARMv8 NEON 591 option crypto add FP_ARMv8 CRYPTO 592 option nocrypto remove ALL_CRYPTO 593 option nofp remove ALL_FP 594 option sb add sb 595 option predres add predres 596end arch armv8.1-a 597 598begin arch armv8.2-a 599 tune for cortex-a53 600 tune flags CO_PROC 601 base 8A 602 profile A 603 isa ARMv8_2a 604 option simd add FP_ARMv8 NEON 605 option fp16 add fp16 FP_ARMv8 NEON 606 option fp16fml add fp16fml fp16 FP_ARMv8 NEON 607 option crypto add FP_ARMv8 CRYPTO 608 option nocrypto remove ALL_CRYPTO 609 option nofp remove ALL_FP 610 option dotprod add FP_ARMv8 DOTPROD 611 option sb add sb 612 option predres add predres 613 option i8mm add i8mm FP_ARMv8 NEON 614 option bf16 add bf16 FP_ARMv8 NEON 615end arch armv8.2-a 616 617begin arch armv8.3-a 618 tune for cortex-a53 619 tune flags CO_PROC 620 base 8A 621 profile A 622 isa ARMv8_3a 623 option simd add FP_ARMv8 NEON 624 option fp16 add fp16 FP_ARMv8 NEON 625 option fp16fml add fp16fml fp16 FP_ARMv8 NEON 626 option crypto add FP_ARMv8 CRYPTO 627 option nocrypto remove ALL_CRYPTO 628 option nofp remove ALL_FP 629 option dotprod add FP_ARMv8 DOTPROD 630 option sb add sb 631 option predres add predres 632 option i8mm add i8mm FP_ARMv8 NEON 633 option bf16 add bf16 FP_ARMv8 NEON 634end arch armv8.3-a 635 636begin arch armv8.4-a 637 tune for cortex-a53 638 tune flags CO_PROC 639 base 8A 640 profile A 641 isa ARMv8_4a 642 option simd add FP_ARMv8 DOTPROD 643 option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD 644 option crypto add FP_ARMv8 CRYPTO DOTPROD 645 option nocrypto remove ALL_CRYPTO 646 option nofp remove ALL_FP 647 option sb add sb 648 option predres add predres 649 option i8mm add i8mm FP_ARMv8 DOTPROD 650 option bf16 add bf16 FP_ARMv8 DOTPROD 651end arch armv8.4-a 652 653begin arch armv8.5-a 654 tune for cortex-a53 655 tune flags CO_PROC 656 base 8A 657 profile A 658 isa ARMv8_5a 659 option simd add FP_ARMv8 DOTPROD 660 option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD 661 option crypto add FP_ARMv8 CRYPTO DOTPROD 662 option nocrypto remove ALL_CRYPTO 663 option nofp remove ALL_FP 664 option i8mm add i8mm FP_ARMv8 DOTPROD 665 option bf16 add bf16 FP_ARMv8 DOTPROD 666end arch armv8.5-a 667 668begin arch armv8.6-a 669 tune for cortex-a53 670 tune flags CO_PROC 671 base 8A 672 profile A 673 isa ARMv8_6a 674 option simd add FP_ARMv8 DOTPROD 675 option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD 676 option crypto add FP_ARMv8 CRYPTO DOTPROD 677 option nocrypto remove ALL_CRYPTO 678 option nofp remove ALL_FP 679 option i8mm add i8mm FP_ARMv8 DOTPROD 680 option bf16 add bf16 FP_ARMv8 DOTPROD 681end arch armv8.6-a 682 683begin arch armv8-m.base 684 tune for cortex-m23 685 base 8M_BASE 686 profile M 687 isa ARMv8m_base 688end arch armv8-m.base 689 690begin arch armv8-m.main 691 tune for cortex-m7 692 tune flags CO_PROC 693 base 8M_MAIN 694 profile M 695 isa ARMv8m_main 696 option dsp add armv7em 697# fp => FPv5-sp-d16; fp.dp => FPv5-d16 698 option fp add FPv5 699 option fp.dp add FPv5 FP_DBL 700 option nofp remove ALL_FP 701 option nodsp remove armv7em 702 option cdecp0 add cdecp0 703 option cdecp1 add cdecp1 704 option cdecp2 add cdecp2 705 option cdecp3 add cdecp3 706 option cdecp4 add cdecp4 707 option cdecp5 add cdecp5 708 option cdecp6 add cdecp6 709 option cdecp7 add cdecp7 710end arch armv8-m.main 711 712begin arch armv8-r 713 tune for cortex-r52 714 tune flags CO_PROC 715 base 8R 716 profile R 717 isa ARMv8r 718 option crc add crc32 719# fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision 720# note: no fp option for fp-armv8 (d16) + double precision at the moment 721 option fp.sp add FPv5 722 option simd add FP_ARMv8 NEON 723 option crypto add FP_ARMv8 CRYPTO 724 option nocrypto remove ALL_CRYPTO 725 option nofp remove ALL_FP 726end arch armv8-r 727 728begin arch armv8.1-m.main 729 tune for cortex-m55 730 tune flags CO_PROC 731 base 8M_MAIN 732 profile M 733 isa ARMv8_1m_main 734# fp => FPv5-sp-d16; fp.dp => FPv5-d16 735 option dsp add armv7em 736 option fp add FPv5 fp16 737 option fp.dp add FPv5 FP_DBL fp16 738 option nofp remove ALL_FP 739 option mve add MVE 740 option mve.fp add MVE_FP 741 option cdecp0 add cdecp0 742 option cdecp1 add cdecp1 743 option cdecp2 add cdecp2 744 option cdecp3 add cdecp3 745 option cdecp4 add cdecp4 746 option cdecp5 add cdecp5 747 option cdecp6 add cdecp6 748 option cdecp7 add cdecp7 749end arch armv8.1-m.main 750 751begin arch iwmmxt 752 tune for iwmmxt 753 tune flags LDSCHED STRONG XSCALE 754 base 5TE 755 isa ARMv5te xscale iwmmxt 756end arch iwmmxt 757 758begin arch iwmmxt2 759 tune for iwmmxt2 760 tune flags LDSCHED STRONG XSCALE 761 base 5TE 762 isa ARMv5te xscale iwmmxt iwmmxt2 763end arch iwmmxt2 764 765# CPU entries 766# format: 767# begin cpu <name> 768# [cname <c-compatible-name>] 769# [alias <name>+] 770# [tune for <cpu-name>] 771# [tune flags <list>] 772# architecture <name> 773# [isa <additional-isa-flags-list>] 774# [option <name> add|remove <isa-list>]* 775# [optalias <name> <optname>]* 776# [costs <name>] 777# [vendor <vendor-id> 778# [part <part-id> [minrev [maxrev]]] 779# end cpu <name> 780# 781# If omitted, cname is formed from transforming the cpuname to convert 782# non-valid punctuation characters to '_'. 783# Any number of alias names may be specified for a CPU. If the name starts 784# with a '!' then it will be recognized as a valid name, but will not 785# be printed in any help text listing permitted CPUs. 786# If specified, tune for specifies a CPU target to use for tuning this core. 787# isa flags are appended to those defined by the architecture. 788# Each add option must have a distinct feature set and each remove 789# option must similarly have a distinct feature set. Option aliases can be 790# added with the optalias statement. 791# Vendor, part and revision information is used for native CPU and architecture 792# detection. All values must be in hex (lower case) with the leading '0x' 793# omitted. For example the cortex-a9 will have vendor 41 and part c09. 794# Revision information is used to match a subrange of part 795# revisions: minrev <= detected <= maxrev. 796# If a minrev or maxrev are omitted then minrev defaults to zero and maxrev 797# to infinity. 798# Revision information is not implemented yet; no part uses it. 799 800# V4 Architecture Processors 801begin cpu arm8 802 tune flags LDSCHED 803 architecture armv4 804 costs fastmul 805end cpu arm8 806 807begin cpu arm810 808 tune flags LDSCHED 809 architecture armv4 810 costs fastmul 811end cpu arm810 812 813begin cpu strongarm 814 alias strongarm110 !strongarm1100 !strongarm1110 815 tune flags LDSCHED STRONG 816 architecture armv4 817 costs strongarm 818end cpu strongarm 819 820begin cpu fa526 821 tune flags LDSCHED 822 architecture armv4 823 costs fastmul 824end cpu fa526 825 826begin cpu fa626 827 tune flags LDSCHED 828 architecture armv4 829 costs fastmul 830end cpu fa626 831 832 833# V4T Architecture Processors 834begin cpu arm7tdmi 835 alias arm7tdmi-s 836 tune flags CO_PROC 837 architecture armv4t 838 costs fastmul 839end cpu arm7tdmi 840 841begin cpu arm710t 842 alias arm720t arm740t 843 tune flags WBUF 844 architecture armv4t 845 costs fastmul 846end cpu arm710t 847 848begin cpu arm9 849 tune flags LDSCHED 850 architecture armv4t 851 costs fastmul 852end cpu arm9 853 854begin cpu arm9tdmi 855 tune flags LDSCHED 856 architecture armv4t 857 costs fastmul 858end cpu arm9tdmi 859 860begin cpu arm920t 861 alias arm920 arm922t arm940t ep9312 862 tune flags LDSCHED 863 architecture armv4t 864 costs fastmul 865end cpu arm920t 866 867 868# V5T Architecture Processors 869# These used VFPv1 which isn't supported by GCC 870begin cpu arm10tdmi 871 alias arm1020t 872 tune flags LDSCHED 873 architecture armv5t 874 costs fastmul 875end cpu arm10tdmi 876 877 878# V5TE Architecture Processors 879begin cpu arm9e 880 alias arm946e-s arm966e-s arm968e-s 881 tune flags LDSCHED 882 architecture armv5te+fp 883 option nofp remove ALL_FP 884 costs 9e 885end cpu arm9e 886 887begin cpu arm10e 888 alias arm1020e arm1022e 889 tune flags LDSCHED 890 architecture armv5te+fp 891 option nofp remove ALL_FP 892 costs fastmul 893end cpu arm10e 894 895begin cpu xscale 896 tune flags LDSCHED XSCALE 897 architecture armv5te 898 isa xscale 899 costs xscale 900end cpu xscale 901 902begin cpu iwmmxt 903 tune flags LDSCHED XSCALE 904 architecture iwmmxt 905 costs xscale 906end cpu iwmmxt 907 908begin cpu iwmmxt2 909 tune flags LDSCHED XSCALE 910 architecture iwmmxt2 911 costs xscale 912end cpu iwmmxt2 913 914begin cpu fa606te 915 tune flags LDSCHED 916 architecture armv5te 917 costs 9e 918end cpu fa606te 919 920begin cpu fa626te 921 tune flags LDSCHED 922 architecture armv5te 923 costs 9e 924end cpu fa626te 925 926begin cpu fmp626 927 tune flags LDSCHED 928 architecture armv5te 929 costs 9e 930end cpu fmp626 931 932begin cpu fa726te 933 tune flags LDSCHED 934 architecture armv5te 935 costs fa726te 936end cpu fa726te 937 938 939# V5TEJ Architecture Processors 940begin cpu arm926ej-s 941 cname arm926ejs 942 tune flags LDSCHED 943 architecture armv5tej+fp 944 option nofp remove ALL_FP 945 costs 9e 946 vendor 41 947 part 926 948end cpu arm926ej-s 949 950begin cpu arm1026ej-s 951 cname arm1026ejs 952 tune flags LDSCHED 953 architecture armv5tej+fp 954 option nofp remove ALL_FP 955 costs 9e 956 vendor 41 957 part a26 958end cpu arm1026ej-s 959 960 961# V6 Architecture Processors 962begin cpu arm1136j-s 963 cname arm1136js 964 tune flags LDSCHED 965 architecture armv6j 966 costs 9e 967end cpu arm1136j-s 968 969begin cpu arm1136jf-s 970 cname arm1136jfs 971 tune flags LDSCHED 972 architecture armv6j+fp 973 costs 9e 974 vendor 41 975 part b36 976end cpu arm1136jf-s 977 978begin cpu arm1176jz-s 979 cname arm1176jzs 980 tune flags LDSCHED 981 architecture armv6kz 982 costs 9e 983end cpu arm1176jz-s 984 985begin cpu arm1176jzf-s 986 cname arm1176jzfs 987 tune flags LDSCHED 988 architecture armv6kz+fp 989 costs 9e 990 vendor 41 991 part b76 992end cpu arm1176jzf-s 993 994begin cpu mpcorenovfp 995 tune flags LDSCHED 996 architecture armv6k 997 costs 9e 998end cpu mpcorenovfp 999 1000begin cpu mpcore 1001 tune flags LDSCHED 1002 architecture armv6k+fp 1003 costs 9e 1004 vendor 41 1005 part b02 1006end cpu mpcore 1007 1008begin cpu arm1156t2-s 1009 cname arm1156t2s 1010 tune flags LDSCHED 1011 architecture armv6t2 1012 costs v6t2 1013end cpu arm1156t2-s 1014 1015begin cpu arm1156t2f-s 1016 cname arm1156t2fs 1017 tune flags LDSCHED 1018 architecture armv6t2+fp 1019 costs v6t2 1020 vendor 41 1021 part b56 1022end cpu arm1156t2f-s 1023 1024 1025# V6M Architecture Processors 1026begin cpu cortex-m1 1027 cname cortexm1 1028 tune flags LDSCHED 1029 architecture armv6s-m 1030 costs v6m 1031 vendor 41 1032 part c21 1033end cpu cortex-m1 1034 1035begin cpu cortex-m0 1036 cname cortexm0 1037 tune flags LDSCHED 1038 architecture armv6s-m 1039 costs v6m 1040 vendor 41 1041 part c20 1042end cpu cortex-m0 1043 1044begin cpu cortex-m0plus 1045 cname cortexm0plus 1046 tune flags LDSCHED 1047 architecture armv6s-m 1048 costs v6m 1049end cpu cortex-m0plus 1050 1051 1052# V6M Architecture Processors for small-multiply implementations. 1053begin cpu cortex-m1.small-multiply 1054 cname cortexm1smallmultiply 1055 tune for cortex-m1 1056 tune flags LDSCHED SMALLMUL 1057 architecture armv6s-m 1058 costs v6m 1059end cpu cortex-m1.small-multiply 1060 1061begin cpu cortex-m0.small-multiply 1062 cname cortexm0smallmultiply 1063 tune for cortex-m0 1064 tune flags LDSCHED SMALLMUL 1065 architecture armv6s-m 1066 costs v6m 1067end cpu cortex-m0.small-multiply 1068 1069begin cpu cortex-m0plus.small-multiply 1070 cname cortexm0plussmallmultiply 1071 tune for cortex-m0plus 1072 tune flags LDSCHED SMALLMUL 1073 architecture armv6s-m 1074 costs v6m 1075end cpu cortex-m0plus.small-multiply 1076 1077 1078# V7 Architecture Processors 1079begin cpu generic-armv7-a 1080 cname genericv7a 1081 tune flags LDSCHED 1082 architecture armv7-a+fp 1083 option mp add mp 1084 option sec add sec 1085 option vfpv3-d16 add VFPv3 FP_DBL 1086 option vfpv3 add VFPv3 FP_D32 1087 option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 1088 option vfpv3-fp16 add VFPv3 FP_D32 fp16conv 1089 option vfpv4-d16 add VFPv4 FP_DBL 1090 option vfpv4 add VFPv4 FP_D32 1091 option simd add VFPv3 NEON 1092 optalias neon simd 1093 optalias neon-vfpv3 simd 1094 option neon-fp16 add VFPv3 NEON fp16conv 1095 option neon-vfpv4 add VFPv4 NEON 1096 option nosimd remove ALL_SIMD 1097 option nofp remove ALL_FP 1098 costs cortex 1099end cpu generic-armv7-a 1100 1101begin cpu cortex-a5 1102 cname cortexa5 1103 tune flags LDSCHED 1104 architecture armv7-a+mp+sec+neon-fp16 1105 option nosimd remove ALL_SIMD 1106 option nofp remove ALL_FP 1107 costs cortex_a5 1108 vendor 41 1109 part c05 1110end cpu cortex-a5 1111 1112begin cpu cortex-a7 1113 cname cortexa7 1114 tune flags LDSCHED 1115 architecture armv7ve+simd 1116 option nosimd remove ALL_SIMD 1117 option nofp remove ALL_FP 1118 costs cortex_a7 1119 vendor 41 1120 part c07 1121end cpu cortex-a7 1122 1123begin cpu cortex-a8 1124 cname cortexa8 1125 tune flags LDSCHED 1126 architecture armv7-a+sec+simd 1127 option nofp remove ALL_FP 1128 costs cortex_a8 1129 vendor 41 1130 part c08 1131end cpu cortex-a8 1132 1133begin cpu cortex-a9 1134 cname cortexa9 1135 tune flags LDSCHED 1136 architecture armv7-a+mp+sec+neon-fp16 1137 option nosimd remove ALL_SIMD 1138 option nofp remove ALL_FP 1139 costs cortex_a9 1140 vendor 41 1141 part c09 1142end cpu cortex-a9 1143 1144begin cpu cortex-a12 1145 cname cortexa12 1146 tune for cortex-a17 1147 tune flags LDSCHED 1148 architecture armv7ve+simd 1149 option nofp remove ALL_FP 1150 costs cortex_a12 1151 vendor 41 1152 part c0d 1153end cpu cortex-a12 1154 1155begin cpu cortex-a15 1156 cname cortexa15 1157 tune flags LDSCHED 1158 architecture armv7ve+simd 1159 option nofp remove ALL_FP 1160 costs cortex_a15 1161 vendor 41 1162 part c0f 1163end cpu cortex-a15 1164 1165begin cpu cortex-a17 1166 cname cortexa17 1167 tune flags LDSCHED 1168 architecture armv7ve+simd 1169 option nofp remove ALL_FP 1170 costs cortex_a12 1171 vendor 41 1172 part c0e 1173end cpu cortex-a17 1174 1175begin cpu cortex-r4 1176 cname cortexr4 1177 tune flags LDSCHED 1178 architecture armv7-r 1179 costs cortex 1180end cpu cortex-r4 1181 1182begin cpu cortex-r4f 1183 cname cortexr4f 1184 tune flags LDSCHED 1185 architecture armv7-r+fp 1186 costs cortex 1187 vendor 41 1188 part c14 1189end cpu cortex-r4f 1190 1191begin cpu cortex-r5 1192 cname cortexr5 1193 tune flags LDSCHED 1194 architecture armv7-r+idiv+fp 1195 option nofp.dp remove FP_DBL 1196 option nofp remove ALL_FP 1197 costs cortex 1198 vendor 41 1199 part c15 1200end cpu cortex-r5 1201 1202begin cpu cortex-r7 1203 cname cortexr7 1204 tune flags LDSCHED 1205 architecture armv7-r+idiv+vfpv3-d16-fp16 1206 option nofp.dp remove FP_DBL 1207 option nofp remove ALL_FP 1208 costs cortex 1209 vendor 41 1210 part c17 1211end cpu cortex-r7 1212 1213begin cpu cortex-r8 1214 cname cortexr8 1215 tune for cortex-r7 1216 tune flags LDSCHED 1217 architecture armv7-r+idiv+vfpv3-d16-fp16 1218 option nofp.dp remove FP_DBL 1219 option nofp remove ALL_FP 1220 costs cortex 1221 vendor 41 1222 part c18 1223end cpu cortex-r8 1224 1225begin cpu cortex-m7 1226 cname cortexm7 1227 tune flags LDSCHED 1228 architecture armv7e-m+fp.dp 1229 isa quirk_no_volatile_ce 1230 option nofp.dp remove FP_DBL 1231 option nofp remove ALL_FP 1232 costs cortex_m7 1233end cpu cortex-m7 1234 1235begin cpu cortex-m4 1236 cname cortexm4 1237 tune flags LDSCHED 1238 architecture armv7e-m+fp 1239 option nofp remove ALL_FP 1240 costs v7m 1241 vendor 41 1242 part c24 1243end cpu cortex-m4 1244 1245begin cpu cortex-m3 1246 cname cortexm3 1247 tune flags LDSCHED 1248 architecture armv7-m 1249 isa quirk_cm3_ldrd 1250 costs v7m 1251 vendor 41 1252 part c23 1253end cpu cortex-m3 1254 1255begin cpu marvell-pj4 1256 tune flags LDSCHED 1257 architecture armv7-a+mp+sec+fp 1258 costs marvell_pj4 1259end cpu marvell-pj4 1260 1261 1262# V7 big.LITTLE implementations 1263begin cpu cortex-a15.cortex-a7 1264 cname cortexa15cortexa7 1265 tune for cortex-a7 1266 tune flags LDSCHED 1267 architecture armv7ve+simd 1268 option nofp remove ALL_FP 1269 costs cortex_a15 1270end cpu cortex-a15.cortex-a7 1271 1272begin cpu cortex-a17.cortex-a7 1273 cname cortexa17cortexa7 1274 tune for cortex-a7 1275 tune flags LDSCHED 1276 architecture armv7ve+simd 1277 option nofp remove ALL_FP 1278 costs cortex_a12 1279end cpu cortex-a17.cortex-a7 1280 1281 1282# V8 A-profile Architecture Processors 1283begin cpu cortex-a32 1284 cname cortexa32 1285 tune for cortex-a53 1286 tune flags LDSCHED 1287 architecture armv8-a+crc+simd 1288 option crypto add FP_ARMv8 CRYPTO 1289 option nofp remove ALL_FP 1290 costs cortex_a35 1291 vendor 41 1292 part d01 1293end cpu cortex-a32 1294 1295begin cpu cortex-a35 1296 cname cortexa35 1297 tune for cortex-a53 1298 tune flags LDSCHED 1299 architecture armv8-a+crc+simd 1300 option crypto add FP_ARMv8 CRYPTO 1301 option nofp remove ALL_FP 1302 costs cortex_a35 1303 vendor 41 1304 part d04 1305end cpu cortex-a35 1306 1307begin cpu cortex-a53 1308 cname cortexa53 1309 tune flags LDSCHED 1310 architecture armv8-a+crc+simd 1311 option crypto add FP_ARMv8 CRYPTO 1312 option nofp remove ALL_FP 1313 costs cortex_a53 1314 vendor 41 1315 part d03 1316end cpu cortex-a53 1317 1318begin cpu cortex-a57 1319 cname cortexa57 1320 tune flags LDSCHED 1321 architecture armv8-a+crc+simd 1322 option crypto add FP_ARMv8 CRYPTO 1323 costs cortex_a57 1324 vendor 41 1325 part d07 1326end cpu cortex-a57 1327 1328begin cpu cortex-a72 1329 cname cortexa72 1330 tune for cortex-a57 1331 tune flags LDSCHED 1332 architecture armv8-a+crc+simd 1333 option crypto add FP_ARMv8 CRYPTO 1334 costs cortex_a57 1335 vendor 41 1336 part d08 1337end cpu cortex-a72 1338 1339begin cpu cortex-a73 1340 cname cortexa73 1341 tune for cortex-a57 1342 tune flags LDSCHED 1343 architecture armv8-a+crc+simd 1344 option crypto add FP_ARMv8 CRYPTO 1345 costs cortex_a73 1346 vendor 41 1347 part d09 1348end cpu cortex-a73 1349 1350begin cpu exynos-m1 1351 cname exynosm1 1352 tune flags LDSCHED 1353 architecture armv8-a+crc+simd 1354 option crypto add FP_ARMv8 CRYPTO 1355 costs exynosm1 1356end cpu exynos-m1 1357 1358begin cpu xgene1 1359 tune flags LDSCHED 1360 architecture armv8-a+simd 1361 option crypto add FP_ARMv8 CRYPTO 1362 costs xgene1 1363end cpu xgene1 1364 1365# V8 A-profile big.LITTLE implementations 1366begin cpu cortex-a57.cortex-a53 1367 cname cortexa57cortexa53 1368 tune for cortex-a53 1369 tune flags LDSCHED 1370 architecture armv8-a+crc+simd 1371 option crypto add FP_ARMv8 CRYPTO 1372 costs cortex_a57 1373end cpu cortex-a57.cortex-a53 1374 1375begin cpu cortex-a72.cortex-a53 1376 cname cortexa72cortexa53 1377 tune for cortex-a53 1378 tune flags LDSCHED 1379 architecture armv8-a+crc+simd 1380 option crypto add FP_ARMv8 CRYPTO 1381 costs cortex_a57 1382end cpu cortex-a72.cortex-a53 1383 1384begin cpu cortex-a73.cortex-a35 1385 cname cortexa73cortexa35 1386 tune for cortex-a53 1387 tune flags LDSCHED 1388 architecture armv8-a+crc+simd 1389 option crypto add FP_ARMv8 CRYPTO 1390 costs cortex_a73 1391end cpu cortex-a73.cortex-a35 1392 1393begin cpu cortex-a73.cortex-a53 1394 cname cortexa73cortexa53 1395 tune for cortex-a53 1396 tune flags LDSCHED 1397 architecture armv8-a+crc+simd 1398 option crypto add FP_ARMv8 CRYPTO 1399 costs cortex_a73 1400end cpu cortex-a73.cortex-a53 1401 1402 1403# ARMv8.2 A-profile Architecture Processors 1404begin cpu cortex-a55 1405 cname cortexa55 1406 tune for cortex-a53 1407 tune flags LDSCHED 1408 architecture armv8.2-a+fp16+dotprod 1409 option crypto add FP_ARMv8 CRYPTO 1410 option nofp remove ALL_FP 1411 costs cortex_a53 1412 vendor 41 1413 part d05 1414end cpu cortex-a55 1415 1416begin cpu cortex-a75 1417 cname cortexa75 1418 tune for cortex-a57 1419 tune flags LDSCHED 1420 architecture armv8.2-a+fp16+dotprod 1421 option crypto add FP_ARMv8 CRYPTO 1422 costs cortex_a73 1423 vendor 41 1424 part d0a 1425end cpu cortex-a75 1426 1427begin cpu cortex-a76 1428 cname cortexa76 1429 tune for cortex-a57 1430 tune flags LDSCHED 1431 architecture armv8.2-a+fp16+dotprod 1432 option crypto add FP_ARMv8 CRYPTO 1433 costs cortex_a57 1434 vendor 41 1435 part d0b 1436end cpu cortex-a76 1437 1438begin cpu cortex-a76ae 1439 cname cortexa76ae 1440 tune for cortex-a57 1441 tune flags LDSCHED 1442 architecture armv8.2-a+fp16+dotprod 1443 option crypto add FP_ARMv8 CRYPTO 1444 costs cortex_a57 1445 vendor 41 1446 part d0e 1447end cpu cortex-a76ae 1448 1449begin cpu cortex-a77 1450 cname cortexa77 1451 tune for cortex-a57 1452 tune flags LDSCHED 1453 architecture armv8.2-a+fp16+dotprod 1454 option crypto add FP_ARMv8 CRYPTO 1455 costs cortex_a57 1456 vendor 41 1457 part d0d 1458end cpu cortex-a77 1459 1460begin cpu cortex-a78 1461 cname cortexa78 1462 tune for cortex-a57 1463 tune flags LDSCHED 1464 architecture armv8.2-a+fp16+dotprod 1465 option crypto add FP_ARMv8 CRYPTO 1466 costs cortex_a57 1467 vendor 41 1468 part d41 1469end cpu cortex-a78 1470 1471begin cpu cortex-a78ae 1472 cname cortexa78ae 1473 tune for cortex-a57 1474 tune flags LDSCHED 1475 architecture armv8.2-a+fp16+dotprod 1476 option crypto add FP_ARMv8 CRYPTO 1477 costs cortex_a57 1478 vendor 41 1479 part d42 1480end cpu cortex-a78ae 1481 1482begin cpu cortex-a78c 1483 cname cortexa78c 1484 tune for cortex-a57 1485 tune flags LDSCHED 1486 architecture armv8.2-a+fp16+dotprod 1487 option crypto add FP_ARMv8 CRYPTO 1488 costs cortex_a57 1489 vendor 41 1490 part d4b 1491end cpu cortex-a78c 1492 1493begin cpu cortex-x1 1494 cname cortexx1 1495 tune for cortex-a57 1496 tune flags LDSCHED 1497 architecture armv8.2-a+fp16+dotprod 1498 option crypto add FP_ARMv8 CRYPTO 1499 costs cortex_a57 1500 vendor 41 1501 part d44 1502end cpu cortex-x1 1503 1504begin cpu neoverse-n1 1505 cname neoversen1 1506 alias !ares 1507 tune for cortex-a57 1508 tune flags LDSCHED 1509 architecture armv8.2-a+fp16+dotprod 1510 option crypto add FP_ARMv8 CRYPTO 1511 costs cortex_a57 1512 vendor 41 1513 part d0c 1514end cpu neoverse-n1 1515 1516# ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations 1517begin cpu cortex-a75.cortex-a55 1518 cname cortexa75cortexa55 1519 tune for cortex-a53 1520 tune flags LDSCHED 1521 architecture armv8.2-a+fp16+dotprod 1522 option crypto add FP_ARMv8 CRYPTO 1523 costs cortex_a73 1524end cpu cortex-a75.cortex-a55 1525 1526begin cpu cortex-a76.cortex-a55 1527 cname cortexa76cortexa55 1528 tune for cortex-a53 1529 tune flags LDSCHED 1530 architecture armv8.2-a+fp16+dotprod 1531 option crypto add FP_ARMv8 CRYPTO 1532 costs cortex_a57 1533end cpu cortex-a76.cortex-a55 1534 1535# Armv8.4 A-profile Architecture Processors 1536begin cpu neoverse-v1 1537 cname neoversev1 1538 tune for cortex-a57 1539 tune flags LDSCHED 1540 architecture armv8.4-a+fp16+bf16+i8mm 1541 option crypto add FP_ARMv8 CRYPTO 1542 costs cortex_a57 1543 vendor 41 1544 part 0xd40 1545end cpu neoverse-v1 1546 1547# Armv8.5 A-profile Architecture Processors 1548begin cpu neoverse-n2 1549 cname neoversen2 1550 tune for cortex-a57 1551 tune flags LDSCHED 1552 architecture armv8.5-a+fp16+bf16+i8mm 1553 option crypto add FP_ARMv8 CRYPTO 1554 costs cortex_a57 1555 vendor 41 1556 part 0xd49 1557end cpu neoverse-n2 1558 1559# V8 M-profile implementations. 1560begin cpu cortex-m23 1561 cname cortexm23 1562 tune flags LDSCHED 1563 architecture armv8-m.base 1564 costs v6m 1565end cpu cortex-m23 1566 1567begin cpu cortex-m33 1568 cname cortexm33 1569 tune flags LDSCHED 1570 architecture armv8-m.main+dsp+fp 1571 option nofp remove ALL_FP 1572 option nodsp remove armv7em 1573 costs v7m 1574end cpu cortex-m33 1575 1576begin cpu cortex-m35p 1577 cname cortexm35p 1578 tune flags LDSCHED 1579 architecture armv8-m.main+dsp+fp 1580 option nofp remove ALL_FP 1581 option nodsp remove armv7em 1582 costs v7m 1583end cpu cortex-m35p 1584 1585begin cpu cortex-m55 1586 cname cortexm55 1587 tune flags LDSCHED 1588 architecture armv8.1-m.main+mve.fp+fp.dp 1589 option nomve.fp remove mve_float 1590 option nomve remove mve mve_float 1591 option nofp remove ALL_FP mve_float 1592 option nodsp remove MVE mve_float 1593 isa quirk_no_asmcpu 1594 costs v7m 1595 vendor 41 1596end cpu cortex-m55 1597 1598# V8 R-profile implementations. 1599begin cpu cortex-r52 1600 cname cortexr52 1601 tune flags LDSCHED 1602 architecture armv8-r+crc+simd 1603 option nofp.dp remove FP_DBL ALL_SIMD 1604 costs cortex 1605 vendor 41 1606 part d13 1607end cpu cortex-r52 1608 1609# FPU entries 1610# format: 1611# begin fpu <name> 1612# isa <isa-flags-list> 1613# end fpu <name> 1614 1615begin fpu vfp 1616 isa VFPv2 FP_DBL 1617end fpu vfp 1618 1619begin fpu vfpv2 1620 isa VFPv2 FP_DBL 1621end fpu vfpv2 1622 1623begin fpu vfpv3 1624 isa VFPv3 FP_D32 1625end fpu vfpv3 1626 1627begin fpu vfpv3-fp16 1628 isa VFPv3 FP_D32 fp16conv 1629end fpu vfpv3-fp16 1630 1631begin fpu vfpv3-d16 1632 isa VFPv3 FP_DBL 1633end fpu vfpv3-d16 1634 1635begin fpu vfpv3-d16-fp16 1636 isa VFPv3 FP_DBL fp16conv 1637end fpu vfpv3-d16-fp16 1638 1639begin fpu vfpv3xd 1640 isa VFPv3 1641end fpu vfpv3xd 1642 1643begin fpu vfpv3xd-fp16 1644 isa VFPv3 fp16conv 1645end fpu vfpv3xd-fp16 1646 1647begin fpu neon 1648 isa VFPv3 NEON 1649end fpu neon 1650 1651begin fpu neon-vfpv3 1652 isa VFPv3 NEON 1653end fpu neon-vfpv3 1654 1655begin fpu neon-fp16 1656 isa VFPv3 NEON fp16conv 1657end fpu neon-fp16 1658 1659begin fpu vfpv4 1660 isa VFPv4 FP_D32 1661end fpu vfpv4 1662 1663begin fpu neon-vfpv4 1664 isa VFPv4 NEON 1665end fpu neon-vfpv4 1666 1667begin fpu vfpv4-d16 1668 isa VFPv4 FP_DBL 1669end fpu vfpv4-d16 1670 1671begin fpu fpv4-sp-d16 1672 isa VFPv4 1673end fpu fpv4-sp-d16 1674 1675begin fpu fpv5-sp-d16 1676 isa FPv5 1677end fpu fpv5-sp-d16 1678 1679begin fpu fpv5-d16 1680 isa FPv5 FP_DBL 1681end fpu fpv5-d16 1682 1683begin fpu fp-armv8 1684 isa FP_ARMv8 1685end fpu fp-armv8 1686 1687begin fpu neon-fp-armv8 1688 isa FP_ARMv8 NEON 1689end fpu neon-fp-armv8 1690 1691begin fpu crypto-neon-fp-armv8 1692 isa FP_ARMv8 CRYPTO 1693end fpu crypto-neon-fp-armv8 1694 1695# Compatibility aliases. 1696begin fpu vfp3 1697 isa VFPv3 FP_D32 1698end fpu vfp3 1699