1;; C-SKY FPU instruction descriptions. 2;; Copyright (C) 2018-2021 Free Software Foundation, Inc. 3;; Contributed by C-SKY Microsystems and Mentor Graphics. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. */ 20 21;; ------------------------------------------------------------------------- 22;; Float Abs instructions 23;; ------------------------------------------------------------------------- 24 25(define_insn "abssf2" 26 [(set (match_operand:SF 0 "register_operand" "=v,r") 27 (abs:SF (match_operand:SF 1 "register_operand" "v, r")))] 28 "CSKY_ISA_FEATURE (fpv2_sf)" 29 "@ 30 fabss\t%0, %1 31 bclri\t%0, %1, 31") 32 33(define_insn "absdf2" 34 [(set (match_operand:DF 0 "register_operand" "=v") 35 (abs:DF (match_operand:DF 1 "register_operand" "v")))] 36 "CSKY_ISA_FEATURE (fpv2_df)" 37 "fabsd\t%0, %1") 38 39 40;; ------------------------------------------------------------------------- 41;; Float Neg instructions 42;; ------------------------------------------------------------------------- 43 44(define_insn "negsf2" 45 [(set (match_operand:SF 0 "register_operand" "=v") 46 (neg:SF (match_operand:SF 1 "register_operand" "v")))] 47 "CSKY_ISA_FEATURE (fpv2_sf)" 48 "fnegs\t%0, %1") 49 50(define_insn "negdf2" 51 [(set (match_operand:DF 0 "register_operand" "=v") 52 (neg:DF (match_operand:DF 1 "register_operand" "v")))] 53 "CSKY_ISA_FEATURE (fpv2_df)" 54 "fnegd\t%0, %1") 55 56 57;; ------------------------------------------------------------------------- 58;; Float Sqrt instructions 59;; ------------------------------------------------------------------------- 60 61(define_insn "sqrtsf2" 62 [(set (match_operand:SF 0 "register_operand" "=v") 63 (sqrt:SF (match_operand:SF 1 "register_operand" "v")))] 64 "CSKY_ISA_FEATURE (fpv2_sf)" 65 "fsqrts\t%0, %1") 66 67(define_insn "sqrtdf2" 68 [(set (match_operand:DF 0 "register_operand" "=v") 69 (sqrt:DF (match_operand:DF 1 "register_operand" "v")))] 70 "CSKY_ISA_FEATURE (fpv2_divd)" 71 "fsqrtd\t%0, %1") 72 73 74;; ------------------------------------------------------------------------- 75;; Float Add instructions 76;; ------------------------------------------------------------------------- 77 78(define_insn "addsf3" 79 [(set (match_operand:SF 0 "register_operand" "=v") 80 (plus:SF (match_operand:SF 1 "register_operand" "v") 81 (match_operand:SF 2 "register_operand" "v")))] 82 "CSKY_ISA_FEATURE (fpv2_sf)" 83 "fadds\t%0, %1, %2") 84 85(define_insn "adddf3" 86 [(set (match_operand:DF 0 "register_operand" "=v") 87 (plus:DF (match_operand:DF 1 "register_operand" "v") 88 (match_operand:DF 2 "register_operand" "v")))] 89 "CSKY_ISA_FEATURE (fpv2_df)" 90 "faddd\t%0, %1, %2") 91 92 93;; ------------------------------------------------------------------------- 94;; Float Sub instructions 95;; ------------------------------------------------------------------------- 96 97(define_insn "subsf3" 98 [(set (match_operand:SF 0 "register_operand" "=v") 99 (minus:SF (match_operand:SF 1 "register_operand" "v") 100 (match_operand:SF 2 "register_operand" "v")))] 101 "CSKY_ISA_FEATURE (fpv2_sf)" 102 "fsubs\t%0, %1, %2") 103 104(define_insn "subdf3" 105 [(set (match_operand:DF 0 "register_operand" "=v") 106 (minus:DF (match_operand:DF 1 "register_operand" "v") 107 (match_operand:DF 2 "register_operand" "v")))] 108 "CSKY_ISA_FEATURE (fpv2_df)" 109 "fsubd\t%0, %1, %2") 110 111 112;; ------------------------------------------------------------------------- 113;; Float Mul instructions 114;; ------------------------------------------------------------------------- 115 116(define_insn "mulsf3" 117 [(set (match_operand:SF 0 "register_operand" "=v") 118 (mult:SF (match_operand:SF 1 "register_operand" "v") 119 (match_operand:SF 2 "register_operand" "v")))] 120 "CSKY_ISA_FEATURE (fpv2_sf)" 121 "fmuls\t%0, %1, %2") 122 123(define_insn "muldf3" 124 [(set (match_operand:DF 0 "register_operand" "=v") 125 (mult:DF (match_operand:DF 1 "register_operand" "v") 126 (match_operand:DF 2 "register_operand" "v")))] 127 "CSKY_ISA_FEATURE (fpv2_df)" 128 "fmuld\t%0, %1, %2") 129 130(define_insn "*fpuv2_nmulsf3_1" 131 [(set (match_operand:SF 0 "register_operand" "=v") 132 (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "%v")) 133 (match_operand:SF 2 "register_operand" "v")))] 134 "CSKY_ISA_FEATURE (fpv2_sf) && !flag_rounding_math" 135 "fnmuls\t%0, %1, %2") 136 137(define_insn "*fpuv2_nmulsf3_2" 138 [(set (match_operand:SF 0 "register_operand" "=v") 139 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "v") 140 (match_operand:SF 2 "register_operand" "v"))))] 141 "CSKY_ISA_FEATURE (fpv2_sf)" 142 "fnmuls\t%0, %1, %2") 143 144(define_insn "*fpuv2_nmuldf3_1" 145 [(set (match_operand:DF 0 "register_operand" "=v") 146 (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "%v")) 147 (match_operand:DF 2 "register_operand" "v")))] 148 "CSKY_ISA_FEATURE (fpv2_df) && !flag_rounding_math" 149 "fnmuld\t%0, %1, %2") 150 151(define_insn "*fpuv2_nmuldf3_2" 152 [(set (match_operand:DF 0 "register_operand" "=v") 153 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "v") 154 (match_operand:DF 2 "register_operand" "v"))))] 155 "CSKY_ISA_FEATURE (fpv2_df)" 156 "fnmuld\t%0, %1, %2") 157 158 159;; ------------------------------------------------------------------------- 160;; Float Div instructions 161;; ------------------------------------------------------------------------- 162 163(define_expand "divsf3" 164 [(set (match_operand:SF 0 "register_operand" "") 165 (div:SF (match_operand:SF 1 "csky_arith_float1_operand" "") 166 (match_operand:SF 2 "register_operand" "")))] 167 "CSKY_ISA_FEATURE (fpv2_sf)" 168 "") 169 170(define_insn "*fpuv2_divsf3" 171 [(set (match_operand:SF 0 "register_operand" "=v") 172 (div:SF (match_operand:SF 1 "register_operand" "v") 173 (match_operand:SF 2 "register_operand" "v")))] 174 "CSKY_ISA_FEATURE (fpv2_sf)" 175 "fdivs\t%0, %1, %2") 176 177(define_insn "*fpuv2_1_divsf3" 178 [(set (match_operand:SF 0 "register_operand" "=v") 179 (div:SF (match_operand:SF 1 "csky_const_float1_operand" "i") 180 (match_operand:SF 2 "register_operand" "v")))] 181 "CSKY_ISA_FEATURE (fpv2_sf)" 182 "frecips\t%0, %2") 183 184 185(define_expand "divdf3" 186 [(set (match_operand:DF 0 "register_operand" "") 187 (div:DF (match_operand:DF 1 "csky_arith_float1_operand" "") 188 (match_operand:DF 2 "register_operand" "")))] 189 "CSKY_ISA_FEATURE (fpv2_divd)" 190 "") 191 192(define_insn "*fpuv2_divdf3" 193 [(set (match_operand:DF 0 "register_operand" "=v") 194 (div:DF (match_operand:DF 1 "register_operand" "v") 195 (match_operand:DF 2 "register_operand" "v")))] 196 "CSKY_ISA_FEATURE (fpv2_divd)" 197 "fdivd\t%0, %1, %2") 198 199(define_insn "*fpuv2_1_divdf3" 200 [(set (match_operand:DF 0 "register_operand" "=v") 201 (div:DF (match_operand:DF 1 "csky_const_float1_operand" "i") 202 (match_operand:DF 2 "register_operand" "v")))] 203 "CSKY_ISA_FEATURE (fpv2_divd)" 204 "frecipd\t%0, %2") 205 206 207;; ------------------------------------------------------------------------- 208;; Float add(sub) with mult instructions 209;; ------------------------------------------------------------------------- 210 211;; vrz <= vrz + vrx * vry 212(define_insn "*fpuv2_fmacs" 213 [(set (match_operand:SF 0 "register_operand" "=v") 214 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "v") 215 (match_operand:SF 2 "register_operand" "v")) 216 (match_operand:SF 3 "register_operand" "0")))] 217 "CSKY_ISA_FEATURE (fpv2_sf)" 218 "fmacs\t%0, %1, %2") 219 220(define_insn "*fpuv2_fmacd" 221 [(set (match_operand:DF 0 "register_operand" "=v") 222 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "v") 223 (match_operand:DF 2 "register_operand" "v")) 224 (match_operand:DF 3 "register_operand" "0")))] 225 "CSKY_ISA_FEATURE (fpv2_df)" 226 "fmacd\t%0, %1, %2") 227 228;; vrz <= vrz - vrx * vry 229(define_insn "*fpuv2_fnmacs" 230 [(set (match_operand:SF 0 "register_operand" "=v") 231 (minus:SF (match_operand:SF 1 "register_operand" "0") 232 (mult:SF (match_operand:SF 2 "register_operand" "v") 233 (match_operand:SF 3 "register_operand" "v"))))] 234 "CSKY_ISA_FEATURE (fpv2_sf)" 235 "fnmacs\t%0, %2, %3") 236 237(define_insn "*fpuv2_fnmacd" 238 [(set (match_operand:DF 0 "register_operand" "=v") 239 (minus:DF (match_operand:DF 1 "register_operand" "0") 240 (mult:DF (match_operand:DF 2 "register_operand" "v") 241 (match_operand:DF 3 "register_operand" "v"))))] 242 "CSKY_ISA_FEATURE (fpv2_df)" 243 "fnmacd\t%0, %2, %3") 244 245;; vrz <= vrx * vry - vrz 246(define_insn "*fpuv2_fmscs" 247 [(set (match_operand:SF 0 "register_operand" "=v") 248 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "v") 249 (match_operand:SF 2 "register_operand" "v")) 250 (match_operand:SF 3 "register_operand" "0")))] 251 "CSKY_ISA_FEATURE (fpv2_sf)" 252 "fmscs\t%0, %1, %2") 253 254(define_insn "*fpuv2_fmscd" 255 [(set (match_operand:DF 0 "register_operand" "=v") 256 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "v") 257 (match_operand:DF 2 "register_operand" "v")) 258 (match_operand:DF 3 "register_operand" "0")))] 259 "CSKY_ISA_FEATURE (fpv2_df)" 260 "fmscd\t%0, %1, %2") 261 262;; vrz = - (vrz + vrx * vry) 263(define_insn "*fpuv2_fnmscs_1" 264 [(set (match_operand:SF 0 "register_operand" "=v") 265 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "%v")) 266 (match_operand:SF 2 "register_operand" "v")) 267 (match_operand:SF 3 "register_operand" "0")))] 268 "CSKY_ISA_FEATURE (fpv2_sf)" 269 "fnmscs\t%0, %1, %2") 270 271(define_insn "*fpuv2_fnmscs_2" 272 [(set (match_operand:SF 0 "register_operand" "=v") 273 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "v") 274 (match_operand:SF 2 "register_operand" "v")) 275 (match_operand:SF 3 "register_operand" "0"))))] 276 "CSKY_ISA_FEATURE (fpv2_sf)" 277 "fnmscs\t%0, %1, %2") 278 279(define_insn "*fpuv2_fnmscd_1" 280 [(set (match_operand:DF 0 "register_operand" "=v") 281 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "%v")) 282 (match_operand:DF 2 "register_operand" "v")) 283 (match_operand:DF 3 "register_operand" "0")))] 284 "CSKY_ISA_FEATURE (fpv2_df)" 285 "fnmscd\t%0, %1, %2") 286 287(define_insn "*fpuv2_fnmscd_2" 288 [(set (match_operand:DF 0 "register_operand" "=v") 289 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "v") 290 (match_operand:DF 2 "register_operand" "v")) 291 (match_operand:DF 3 "register_operand" "0"))))] 292 "CSKY_ISA_FEATURE (fpv2_df)" 293 "fnmscd\t%0, %1, %2") 294 295 296;; ------------------------------------------------------------------------- 297;; Float compare instructions 298;; ------------------------------------------------------------------------- 299 300(define_expand "cbranchsf4" 301 [(set (pc) (if_then_else (match_operator 0 "csky_float_comparison_operator" 302 [(match_operand:SF 1 "register_operand") 303 (match_operand:SF 2 "csky_compare_operand_float")]) 304 (label_ref (match_operand 3 "")) 305 (pc)))] 306 "CSKY_ISA_FEATURE (fpv2_sf)" 307 " 308 { 309 enum rtx_code code = GET_CODE (operands[0]); 310 bool invert = csky_emit_compare_float (code, operands[1], operands[2]); 311 312 if (invert) 313 emit_jump_insn (gen_csky_jbf (operands[3])); 314 else 315 emit_jump_insn (gen_csky_jbt (operands[3])); 316 317 DONE; 318 }") 319 320(define_insn "*fpuv2_unordered" 321 [(set (reg:CC 33) (unordered:CC (match_operand:SF 0 "register_operand" "v") 322 (match_operand:SF 1 "register_operand" "v")))] 323 "CSKY_ISA_FEATURE (fpv2_sf)" 324 "fcmpuos\t%0, %1") 325 326(define_insn "*fpuv2_unordered_zero" 327 [(set (reg:CC 33) (unordered:CC (match_operand:SF 0 "register_operand" "v") 328 (match_operand:SF 1 "csky_const_float0_operand" "i")))] 329 "CSKY_ISA_FEATURE (fpv2_sf)" 330 "fcmpuos\t%0, %0") 331 332(define_insn "*fpuv2_ne" 333 [(set (reg:CC 33) (ne:CC (match_operand:SF 0 "register_operand" "v") 334 (match_operand:SF 1 "register_operand" "v")))] 335 "CSKY_ISA_FEATURE (fpv2_sf)" 336 "fcmpnes\t%0, %1") 337 338(define_insn "*fpuv2_gt" 339 [(set (reg:CC 33) (gt:CC (match_operand:SF 0 "register_operand" "v") 340 (match_operand:SF 1 "register_operand" "v")))] 341 "CSKY_ISA_FEATURE (fpv2_sf)" 342 "fcmplts\t%1, %0") 343 344(define_insn "*fpuv2_ge" 345 [(set (reg:CC 33) (ge:CC (match_operand:SF 0 "register_operand" "v") 346 (match_operand:SF 1 "register_operand" "v")))] 347 "CSKY_ISA_FEATURE (fpv2_sf)" 348 "fcmphss\t%0, %1") 349 350(define_insn "*fpuv2_lt" 351 [(set (reg:CC 33) (lt:CC (match_operand:SF 0 "register_operand" "v") 352 (match_operand:SF 1 "register_operand" "v")))] 353 "CSKY_ISA_FEATURE (fpv2_sf)" 354 "fcmplts\t%0, %1") 355 356(define_insn "*fpuv2_le" 357 [(set (reg:CC 33) (le:CC (match_operand:SF 0 "register_operand" "v") 358 (match_operand:SF 1 "register_operand" "v")))] 359 "CSKY_ISA_FEATURE (fpv2_sf)" 360 "fcmphss\t%1, %0") 361 362(define_insn "*fpuv2_gez" 363 [(set (reg:CC 33) (ge:CC (match_operand:SF 0 "register_operand" "v") 364 (match_operand:SF 1 "csky_const_float0_operand" "i")))] 365 "CSKY_ISA_FEATURE (fpv2_sf)" 366 "fcmpzhss\t%0") 367 368(define_insn "*fpuv2_nez" 369 [(set (reg:CC 33) (ne:CC (match_operand:SF 0 "register_operand" "v") 370 (match_operand:SF 1 "csky_const_float0_operand" "i")))] 371 "CSKY_ISA_FEATURE (fpv2_sf)" 372 "fcmpznes\t%0") 373 374 375(define_expand "cbranchdf4" 376 [(set (pc) (if_then_else (match_operator 0 "csky_float_comparison_operator" 377 [(match_operand:DF 1 "register_operand") 378 (match_operand:DF 2 "csky_compare_operand_float")]) 379 (label_ref (match_operand 3 "")) 380 (pc)))] 381 "CSKY_ISA_FEATURE (fpv2_df)" 382 " 383 { 384 enum rtx_code code = GET_CODE (operands[0]); 385 bool invert = csky_emit_compare_float (code, operands[1], operands[2]); 386 387 if (invert) 388 emit_jump_insn (gen_csky_jbf (operands[3])); 389 else 390 emit_jump_insn (gen_csky_jbt (operands[3])); 391 392 DONE; 393}") 394 395(define_insn "*fpuv2_dunordered" 396 [(set (reg:CC 33) (unordered:CC (match_operand:DF 0 "register_operand" "v") 397 (match_operand:DF 1 "register_operand" "v")))] 398 "CSKY_ISA_FEATURE (fpv2_df)" 399 "fcmpuod\t%0, %1") 400 401(define_insn "*fpuv2_dunordered_zero" 402 [(set (reg:CC 33) (unordered:CC (match_operand:DF 0 "register_operand" "v") 403 (match_operand:DF 1 "csky_const_float0_operand" "i")))] 404 "CSKY_ISA_FEATURE (fpv2_df)" 405 "fcmpuod\t%0, %0") 406 407(define_insn "*fpuv2_dne" 408 [(set (reg:CC 33) (ne:CC (match_operand:DF 0 "register_operand" "v") 409 (match_operand:DF 1 "register_operand" "v")))] 410 "CSKY_ISA_FEATURE (fpv2_df)" 411 "fcmpned\t%0, %1") 412 413(define_insn "*fpuv2_dgt" 414 [(set (reg:CC 33) (gt:CC (match_operand:DF 0 "register_operand" "v") 415 (match_operand:DF 1 "register_operand" "v")))] 416 "CSKY_ISA_FEATURE (fpv2_df)" 417 "fcmpltd\t%1, %0") 418 419(define_insn "*fpuv2_dge" 420 [(set (reg:CC 33) (ge:CC (match_operand:DF 0 "register_operand" "v") 421 (match_operand:DF 1 "register_operand" "v")))] 422 "CSKY_ISA_FEATURE (fpv2_df)" 423 "fcmphsd\t%0, %1") 424 425(define_insn "*fpuv2_dlt" 426 [(set (reg:CC 33) (lt:CC (match_operand:DF 0 "register_operand" "v") 427 (match_operand:DF 1 "register_operand" "v")))] 428 "CSKY_ISA_FEATURE (fpv2_df)" 429 "fcmpltd\t%0, %1") 430 431(define_insn "*fpuv2_dle" 432 [(set (reg:CC 33) (le:CC (match_operand:DF 0 "register_operand" "v") 433 (match_operand:DF 1 "register_operand" "v")))] 434 "CSKY_ISA_FEATURE (fpv2_df)" 435 "fcmphsd\t%1, %0") 436 437(define_insn "*fpuv2_dgez" 438 [(set (reg:CC 33) (ge:CC (match_operand:DF 0 "register_operand" "v") 439 (match_operand:DF 1 "csky_const_float0_operand" "i")))] 440 "CSKY_ISA_FEATURE (fpv2_df)" 441 "fcmpzhsd\t%0") 442 443(define_insn "*fpuv2_dnez" 444 [(set (reg:CC 33) (ne:CC (match_operand:DF 0 "register_operand" "v") 445 (match_operand:DF 1 "csky_const_float0_operand" "i")))] 446 "CSKY_ISA_FEATURE (fpv2_df)" 447 "fcmpzned\t%0") 448 449 450;; ------------------------------------------------------------------------- 451;; Float convert instructions 452;; ------------------------------------------------------------------------- 453 454;; DF <- SF 455(define_insn "extendsfdf2" 456 [(set (match_operand:DF 0 "register_operand" "=v") 457 (float_extend:DF (match_operand:SF 1 "register_operand" "v")))] 458 "CSKY_ISA_FEATURE (fpv2_df)" 459 "fstod\t%0, %1") 460 461;; SF <- DF 462(define_insn "truncdfsf2" 463 [(set (match_operand:SF 0 "register_operand" "=v") 464 (float_truncate:SF (match_operand:DF 1 "register_operand" "v")))] 465 "CSKY_ISA_FEATURE (fpv2_df)" 466 "fdtos\t%0, %1") 467 468;; SF <- SI 469(define_insn "floatsisf2" 470 [(set (match_operand:SF 0 "register_operand" "=v") 471 (float:SF (match_operand:SI 1 "register_operand" "v")))] 472 "CSKY_ISA_FEATURE (fpv2_sf)" 473 "fsitos\t%0, %1") 474 475;; DF <- SI 476(define_insn "floatsidf2" 477 [(set (match_operand:DF 0 "register_operand" "=v") 478 (float:DF (match_operand:SI 1 "register_operand" "v")))] 479 "CSKY_ISA_FEATURE (fpv2_df)" 480 "fsitod\t%0, %1") 481 482;; SF <- unsigned SI 483(define_insn "floatunssisf2" 484 [(set (match_operand:SF 0 "register_operand" "=v") 485 (unsigned_float:SF (match_operand:SI 1 "register_operand" "v")))] 486 "CSKY_ISA_FEATURE (fpv2_sf)" 487 "fuitos\t%0, %1") 488 489;; DF <- unsigned SI 490(define_insn "floatunssidf2" 491 [(set (match_operand:DF 0 "register_operand" "=v") 492 (unsigned_float:DF (match_operand:SI 1 "register_operand" "v")))] 493 "CSKY_ISA_FEATURE (fpv2_df)" 494 "fuitod\t%0, %1") 495 496;; SI <- SF 497(define_insn "fix_truncsfsi2" 498 [(set (match_operand:SI 0 "register_operand" "=v") 499 (fix:SI (match_operand:SF 1 "register_operand" "v")))] 500 "CSKY_ISA_FEATURE (fpv2_sf)" 501 "fstosi.rz\t%0, %1") 502 503;; SI <- DF 504(define_insn "fix_truncdfsi2" 505 [(set (match_operand:SI 0 "register_operand" "=v") 506 (fix:SI (match_operand:DF 1 "register_operand" "v")))] 507 "CSKY_ISA_FEATURE (fpv2_df)" 508 "fdtosi.rz\t%0, %1") 509 510;; unsigned SI <- SF 511(define_insn "fixuns_truncsfsi2" 512 [(set (match_operand:SI 0 "register_operand" "=v") 513 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "v")))] 514 "CSKY_ISA_FEATURE (fpv2_sf)" 515 "fstoui.rz\t%0, %1") 516 517;; unsigned SI <- DF 518(define_insn "fixuns_truncdfsi2" 519 [(set (match_operand:SI 0 "register_operand" "=v") 520 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "v")))] 521 "CSKY_ISA_FEATURE (fpv2_df)" 522 "fdtoui.rz\t%0, %1") 523 524 525;; ------------------------------------------------------------------------- 526;; Float mov instructions 527;; ------------------------------------------------------------------------- 528 529;; Note: movsf and movdf patterns are in csky.md. 530 531;; cstore SF 532(define_expand "cstoresf4" 533 [(set (match_operand:SI 0 "register_operand" "") 534 (match_operator 1 "ordered_comparison_operator" 535 [(match_operand:SF 2 "register_operand" "") 536 (match_operand:SF 3 "csky_compare_operand_float" "")]))] 537 "CSKY_ISA_FEATURE (fpv2_sf)" 538 " 539 { 540 bool invert = csky_emit_compare_float (GET_CODE (operands[1]), 541 operands[2], operands[3]); 542 if (invert) 543 emit_insn (gen_mvcv (operands[0])); 544 else 545 emit_insn (gen_mvc (operands[0])); 546 DONE; 547 }" 548) 549 550;; cstore DF 551(define_expand "cstoredf4" 552 [(set (match_operand:SI 0 "register_operand" "") 553 (match_operator 1 "ordered_comparison_operator" 554 [(match_operand:DF 2 "register_operand" "") 555 (match_operand:DF 3 "csky_compare_operand_float" "")]))] 556 "CSKY_ISA_FEATURE (fpv2_df)" 557 " 558 { 559 bool invert = csky_emit_compare_float (GET_CODE (operands[1]), 560 operands[2], operands[3]); 561 if (invert) 562 emit_insn (gen_mvcv (operands[0])); 563 else 564 emit_insn (gen_mvc (operands[0])); 565 DONE; 566 }" 567) 568