1;; Matrix-Multiply Assist (MMA) patterns. 2;; Copyright (C) 2020-2021 Free Software Foundation, Inc. 3;; Contributed by Peter Bergner <bergner@linux.ibm.com> and 4;; Michael Meissner <meissner@linux.ibm.com> 5;; 6;; This file is part of GCC. 7;; 8;; GCC is free software; you can redistribute it and/or modify it 9;; under the terms of the GNU General Public License as published 10;; by the Free Software Foundation; either version 3, or (at your 11;; option) any later version. 12;; 13;; GCC is distributed in the hope that it will be useful, but WITHOUT 14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16;; License for more details. 17;; 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22;; The MMA patterns use the multi-register XOmode and OOmode opaque 23;; modes to implement the target specific __vector_quad and 24;; __vector_pair types that the MMA built-in functions reference. We 25;; use OPAQUE_MODE to prevent anything from trying to open them up. 26 27(define_constants [(MAX_MMA_OPERANDS 7)]) 28 29;; Constants for creating unspecs 30 31(define_c_enum "unspec" 32 [UNSPEC_MMA_ASSEMBLE 33 UNSPEC_MMA_EXTRACT 34 UNSPEC_MMA_PMXVBF16GER2 35 UNSPEC_MMA_PMXVBF16GER2NN 36 UNSPEC_MMA_PMXVBF16GER2NP 37 UNSPEC_MMA_PMXVBF16GER2PN 38 UNSPEC_MMA_PMXVBF16GER2PP 39 UNSPEC_MMA_PMXVF16GER2 40 UNSPEC_MMA_PMXVF16GER2NN 41 UNSPEC_MMA_PMXVF16GER2NP 42 UNSPEC_MMA_PMXVF16GER2PN 43 UNSPEC_MMA_PMXVF16GER2PP 44 UNSPEC_MMA_PMXVF32GER 45 UNSPEC_MMA_PMXVF32GERNN 46 UNSPEC_MMA_PMXVF32GERNP 47 UNSPEC_MMA_PMXVF32GERPN 48 UNSPEC_MMA_PMXVF32GERPP 49 UNSPEC_MMA_PMXVF64GER 50 UNSPEC_MMA_PMXVF64GERNN 51 UNSPEC_MMA_PMXVF64GERNP 52 UNSPEC_MMA_PMXVF64GERPN 53 UNSPEC_MMA_PMXVF64GERPP 54 UNSPEC_MMA_PMXVI16GER2 55 UNSPEC_MMA_PMXVI16GER2PP 56 UNSPEC_MMA_PMXVI16GER2S 57 UNSPEC_MMA_PMXVI16GER2SPP 58 UNSPEC_MMA_PMXVI4GER8 59 UNSPEC_MMA_PMXVI4GER8PP 60 UNSPEC_MMA_PMXVI8GER4 61 UNSPEC_MMA_PMXVI8GER4PP 62 UNSPEC_MMA_PMXVI8GER4SPP 63 UNSPEC_MMA_XVBF16GER2 64 UNSPEC_MMA_XVBF16GER2NN 65 UNSPEC_MMA_XVBF16GER2NP 66 UNSPEC_MMA_XVBF16GER2PN 67 UNSPEC_MMA_XVBF16GER2PP 68 UNSPEC_MMA_XVF16GER2 69 UNSPEC_MMA_XVF16GER2NN 70 UNSPEC_MMA_XVF16GER2NP 71 UNSPEC_MMA_XVF16GER2PN 72 UNSPEC_MMA_XVF16GER2PP 73 UNSPEC_MMA_XVF32GER 74 UNSPEC_MMA_XVF32GERNN 75 UNSPEC_MMA_XVF32GERNP 76 UNSPEC_MMA_XVF32GERPN 77 UNSPEC_MMA_XVF32GERPP 78 UNSPEC_MMA_XVF64GER 79 UNSPEC_MMA_XVF64GERNN 80 UNSPEC_MMA_XVF64GERNP 81 UNSPEC_MMA_XVF64GERPN 82 UNSPEC_MMA_XVF64GERPP 83 UNSPEC_MMA_XVI16GER2 84 UNSPEC_MMA_XVI16GER2PP 85 UNSPEC_MMA_XVI16GER2S 86 UNSPEC_MMA_XVI16GER2SPP 87 UNSPEC_MMA_XVI4GER8 88 UNSPEC_MMA_XVI4GER8PP 89 UNSPEC_MMA_XVI8GER4 90 UNSPEC_MMA_XVI8GER4PP 91 UNSPEC_MMA_XVI8GER4SPP 92 UNSPEC_MMA_XXMFACC 93 UNSPEC_MMA_XXMTACC 94 UNSPEC_MMA_XXSETACCZ 95 ]) 96 97;; MMA instructions with 1 accumulator argument 98(define_int_iterator MMA_ACC [UNSPEC_MMA_XXMFACC 99 UNSPEC_MMA_XXMTACC]) 100 101;; MMA instructions with 2 vector arguments 102(define_int_iterator MMA_VV [UNSPEC_MMA_XVI4GER8 103 UNSPEC_MMA_XVI8GER4 104 UNSPEC_MMA_XVI16GER2 105 UNSPEC_MMA_XVI16GER2S 106 UNSPEC_MMA_XVF16GER2 107 UNSPEC_MMA_XVBF16GER2 108 UNSPEC_MMA_XVF32GER]) 109 110;; MMA instructions with 1 accumulator and 2 vector arguments 111(define_int_iterator MMA_AVV [UNSPEC_MMA_XVI4GER8PP 112 UNSPEC_MMA_XVI8GER4PP 113 UNSPEC_MMA_XVI8GER4SPP 114 UNSPEC_MMA_XVI16GER2PP 115 UNSPEC_MMA_XVI16GER2SPP 116 UNSPEC_MMA_XVF16GER2PP 117 UNSPEC_MMA_XVF16GER2PN 118 UNSPEC_MMA_XVF16GER2NP 119 UNSPEC_MMA_XVF16GER2NN 120 UNSPEC_MMA_XVBF16GER2PP 121 UNSPEC_MMA_XVBF16GER2PN 122 UNSPEC_MMA_XVBF16GER2NP 123 UNSPEC_MMA_XVBF16GER2NN 124 UNSPEC_MMA_XVF32GERPP 125 UNSPEC_MMA_XVF32GERPN 126 UNSPEC_MMA_XVF32GERNP 127 UNSPEC_MMA_XVF32GERNN]) 128 129;; MMA instructions with 1 vector pair and 1 vector arguments 130(define_int_iterator MMA_PV [UNSPEC_MMA_XVF64GER]) 131 132;; MMA instructions with 1 accumulator, 1 vector pair and 1 vector arguments 133(define_int_iterator MMA_APV [UNSPEC_MMA_XVF64GERPP 134 UNSPEC_MMA_XVF64GERPN 135 UNSPEC_MMA_XVF64GERNP 136 UNSPEC_MMA_XVF64GERNN]) 137 138;; MMA instructions with 2 vector, 2 4-bit and 1 8-bit arguments 139(define_int_iterator MMA_VVI4I4I8 [UNSPEC_MMA_PMXVI4GER8]) 140 141;; MMA instructions with 1 accumulator, 2 vector, 2 4-bit and 1 8-bit arguments 142(define_int_iterator MMA_AVVI4I4I8 [UNSPEC_MMA_PMXVI4GER8PP]) 143 144;; MMA instructions with 2 vector, 2 4-bit and 1 2-bit arguments 145(define_int_iterator MMA_VVI4I4I2 [UNSPEC_MMA_PMXVI16GER2 146 UNSPEC_MMA_PMXVI16GER2S 147 UNSPEC_MMA_PMXVF16GER2 148 UNSPEC_MMA_PMXVBF16GER2]) 149 150;; MMA instructions with 1 accumulator, 2 vector, 2 4-bit and 1 2-bit arguments 151(define_int_iterator MMA_AVVI4I4I2 [UNSPEC_MMA_PMXVI16GER2PP 152 UNSPEC_MMA_PMXVI16GER2SPP 153 UNSPEC_MMA_PMXVF16GER2PP 154 UNSPEC_MMA_PMXVF16GER2PN 155 UNSPEC_MMA_PMXVF16GER2NP 156 UNSPEC_MMA_PMXVF16GER2NN 157 UNSPEC_MMA_PMXVBF16GER2PP 158 UNSPEC_MMA_PMXVBF16GER2PN 159 UNSPEC_MMA_PMXVBF16GER2NP 160 UNSPEC_MMA_PMXVBF16GER2NN]) 161 162;; MMA instructions with 2 vector and 2 4-bit arguments 163(define_int_iterator MMA_VVI4I4 [UNSPEC_MMA_PMXVF32GER]) 164 165;; MMA instructions with 1 accumulator, 2 vector and 2 4-bit arguments 166(define_int_iterator MMA_AVVI4I4 [UNSPEC_MMA_PMXVF32GERPP 167 UNSPEC_MMA_PMXVF32GERPN 168 UNSPEC_MMA_PMXVF32GERNP 169 UNSPEC_MMA_PMXVF32GERNN]) 170 171;; MMA instructions with 2 vector, 1 4-bit and 1 2-bit arguments 172(define_int_iterator MMA_PVI4I2 [UNSPEC_MMA_PMXVF64GER]) 173 174;; MMA instructions with 1 accumulator, 2 vector, 1 4-bit and 1 2-bit arguments 175(define_int_iterator MMA_APVI4I2 [UNSPEC_MMA_PMXVF64GERPP 176 UNSPEC_MMA_PMXVF64GERPN 177 UNSPEC_MMA_PMXVF64GERNP 178 UNSPEC_MMA_PMXVF64GERNN]) 179 180;; MMA instructions with 2 vector and 3 4-bit arguments 181(define_int_iterator MMA_VVI4I4I4 [UNSPEC_MMA_PMXVI8GER4]) 182 183;; MMA instructions with 1 accumulator, 2 vector and 3 4-bit arguments 184(define_int_iterator MMA_AVVI4I4I4 [UNSPEC_MMA_PMXVI8GER4PP 185 UNSPEC_MMA_PMXVI8GER4SPP]) 186 187(define_int_attr acc [(UNSPEC_MMA_XXMFACC "xxmfacc") 188 (UNSPEC_MMA_XXMTACC "xxmtacc")]) 189 190(define_int_attr vv [(UNSPEC_MMA_XVI4GER8 "xvi4ger8") 191 (UNSPEC_MMA_XVI8GER4 "xvi8ger4") 192 (UNSPEC_MMA_XVI16GER2 "xvi16ger2") 193 (UNSPEC_MMA_XVI16GER2S "xvi16ger2s") 194 (UNSPEC_MMA_XVF16GER2 "xvf16ger2") 195 (UNSPEC_MMA_XVBF16GER2 "xvbf16ger2") 196 (UNSPEC_MMA_XVF32GER "xvf32ger")]) 197 198(define_int_attr avv [(UNSPEC_MMA_XVI4GER8PP "xvi4ger8pp") 199 (UNSPEC_MMA_XVI8GER4PP "xvi8ger4pp") 200 (UNSPEC_MMA_XVI8GER4SPP "xvi8ger4spp") 201 (UNSPEC_MMA_XVI16GER2PP "xvi16ger2pp") 202 (UNSPEC_MMA_XVI16GER2SPP "xvi16ger2spp") 203 (UNSPEC_MMA_XVF16GER2PP "xvf16ger2pp") 204 (UNSPEC_MMA_XVF16GER2PN "xvf16ger2pn") 205 (UNSPEC_MMA_XVF16GER2NP "xvf16ger2np") 206 (UNSPEC_MMA_XVF16GER2NN "xvf16ger2nn") 207 (UNSPEC_MMA_XVBF16GER2PP "xvbf16ger2pp") 208 (UNSPEC_MMA_XVBF16GER2PN "xvbf16ger2pn") 209 (UNSPEC_MMA_XVBF16GER2NP "xvbf16ger2np") 210 (UNSPEC_MMA_XVBF16GER2NN "xvbf16ger2nn") 211 (UNSPEC_MMA_XVF32GERPP "xvf32gerpp") 212 (UNSPEC_MMA_XVF32GERPN "xvf32gerpn") 213 (UNSPEC_MMA_XVF32GERNP "xvf32gernp") 214 (UNSPEC_MMA_XVF32GERNN "xvf32gernn")]) 215 216(define_int_attr pv [(UNSPEC_MMA_XVF64GER "xvf64ger")]) 217 218(define_int_attr apv [(UNSPEC_MMA_XVF64GERPP "xvf64gerpp") 219 (UNSPEC_MMA_XVF64GERPN "xvf64gerpn") 220 (UNSPEC_MMA_XVF64GERNP "xvf64gernp") 221 (UNSPEC_MMA_XVF64GERNN "xvf64gernn")]) 222 223(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")]) 224 225(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "pmxvi4ger8pp")]) 226 227(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2 "pmxvi16ger2") 228 (UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s") 229 (UNSPEC_MMA_PMXVF16GER2 "pmxvf16ger2") 230 (UNSPEC_MMA_PMXVBF16GER2 "pmxvbf16ger2")]) 231 232(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "pmxvi16ger2pp") 233 (UNSPEC_MMA_PMXVI16GER2SPP "pmxvi16ger2spp") 234 (UNSPEC_MMA_PMXVF16GER2PP "pmxvf16ger2pp") 235 (UNSPEC_MMA_PMXVF16GER2PN "pmxvf16ger2pn") 236 (UNSPEC_MMA_PMXVF16GER2NP "pmxvf16ger2np") 237 (UNSPEC_MMA_PMXVF16GER2NN "pmxvf16ger2nn") 238 (UNSPEC_MMA_PMXVBF16GER2PP "pmxvbf16ger2pp") 239 (UNSPEC_MMA_PMXVBF16GER2PN "pmxvbf16ger2pn") 240 (UNSPEC_MMA_PMXVBF16GER2NP "pmxvbf16ger2np") 241 (UNSPEC_MMA_PMXVBF16GER2NN "pmxvbf16ger2nn")]) 242 243(define_int_attr vvi4i4 [(UNSPEC_MMA_PMXVF32GER "pmxvf32ger")]) 244 245(define_int_attr avvi4i4 [(UNSPEC_MMA_PMXVF32GERPP "pmxvf32gerpp") 246 (UNSPEC_MMA_PMXVF32GERPN "pmxvf32gerpn") 247 (UNSPEC_MMA_PMXVF32GERNP "pmxvf32gernp") 248 (UNSPEC_MMA_PMXVF32GERNN "pmxvf32gernn")]) 249 250(define_int_attr pvi4i2 [(UNSPEC_MMA_PMXVF64GER "pmxvf64ger")]) 251 252(define_int_attr apvi4i2 [(UNSPEC_MMA_PMXVF64GERPP "pmxvf64gerpp") 253 (UNSPEC_MMA_PMXVF64GERPN "pmxvf64gerpn") 254 (UNSPEC_MMA_PMXVF64GERNP "pmxvf64gernp") 255 (UNSPEC_MMA_PMXVF64GERNN "pmxvf64gernn")]) 256 257(define_int_attr vvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4 "pmxvi8ger4")]) 258 259(define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "pmxvi8ger4pp") 260 (UNSPEC_MMA_PMXVI8GER4SPP "pmxvi8ger4spp")]) 261 262 263;; Vector pair support. OOmode can only live in VSRs. 264(define_expand "movoo" 265 [(set (match_operand:OO 0 "nonimmediate_operand") 266 (match_operand:OO 1 "input_operand"))] 267 "TARGET_MMA" 268{ 269 rs6000_emit_move (operands[0], operands[1], OOmode); 270 DONE; 271}) 272 273(define_insn_and_split "*movoo" 274 [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,m,wa") 275 (match_operand:OO 1 "input_operand" "m,wa,wa"))] 276 "TARGET_MMA 277 && (gpc_reg_operand (operands[0], OOmode) 278 || gpc_reg_operand (operands[1], OOmode))" 279 "@ 280 lxvp%X1 %x0,%1 281 stxvp%X0 %x1,%0 282 #" 283 "&& reload_completed 284 && (!MEM_P (operands[0]) && !MEM_P (operands[1]))" 285 [(const_int 0)] 286{ 287 rs6000_split_multireg_move (operands[0], operands[1]); 288 DONE; 289} 290 [(set_attr "type" "vecload,vecstore,veclogical") 291 (set_attr "size" "256") 292 (set_attr "length" "*,*,8")]) 293 294 295;; Vector quad support. XOmode can only live in FPRs. 296(define_expand "movxo" 297 [(set (match_operand:XO 0 "nonimmediate_operand") 298 (match_operand:XO 1 "input_operand"))] 299 "TARGET_MMA" 300{ 301 rs6000_emit_move (operands[0], operands[1], XOmode); 302 DONE; 303}) 304 305(define_insn_and_split "*movxo" 306 [(set (match_operand:XO 0 "nonimmediate_operand" "=d,m,d") 307 (match_operand:XO 1 "input_operand" "m,d,d"))] 308 "TARGET_MMA 309 && (gpc_reg_operand (operands[0], XOmode) 310 || gpc_reg_operand (operands[1], XOmode))" 311 "@ 312 # 313 # 314 #" 315 "&& reload_completed" 316 [(const_int 0)] 317{ 318 rs6000_split_multireg_move (operands[0], operands[1]); 319 DONE; 320} 321 [(set_attr "type" "vecload,vecstore,veclogical") 322 (set_attr "length" "*,*,16") 323 (set_attr "max_prefixed_insns" "2,2,*")]) 324 325(define_expand "vsx_assemble_pair" 326 [(match_operand:OO 0 "vsx_register_operand") 327 (match_operand:V16QI 1 "mma_assemble_input_operand") 328 (match_operand:V16QI 2 "mma_assemble_input_operand")] 329 "TARGET_MMA" 330{ 331 rtx src = gen_rtx_UNSPEC (OOmode, 332 gen_rtvec (2, operands[1], operands[2]), 333 UNSPEC_MMA_ASSEMBLE); 334 emit_move_insn (operands[0], src); 335 DONE; 336}) 337 338(define_insn_and_split "*vsx_assemble_pair" 339 [(set (match_operand:OO 0 "vsx_register_operand" "=wa") 340 (unspec:OO [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa") 341 (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa")] 342 UNSPEC_MMA_ASSEMBLE))] 343 "TARGET_MMA" 344 "#" 345 "&& reload_completed" 346 [(const_int 0)] 347{ 348 rtx src = gen_rtx_UNSPEC (OOmode, 349 gen_rtvec (2, operands[1], operands[2]), 350 UNSPEC_MMA_ASSEMBLE); 351 rs6000_split_multireg_move (operands[0], src); 352 DONE; 353}) 354 355(define_expand "vsx_disassemble_pair" 356 [(match_operand:V16QI 0 "mma_disassemble_output_operand") 357 (match_operand:OO 1 "vsx_register_operand") 358 (match_operand 2 "const_0_to_1_operand")] 359 "TARGET_MMA" 360{ 361 rtx src; 362 int regoff = INTVAL (operands[2]); 363 src = gen_rtx_UNSPEC (V16QImode, 364 gen_rtvec (2, operands[1], GEN_INT (regoff)), 365 UNSPEC_MMA_EXTRACT); 366 emit_move_insn (operands[0], src); 367 DONE; 368}) 369 370(define_insn_and_split "*vsx_disassemble_pair" 371 [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa") 372 (unspec:V16QI [(match_operand:OO 1 "vsx_register_operand" "wa") 373 (match_operand 2 "const_0_to_1_operand")] 374 UNSPEC_MMA_EXTRACT))] 375 "TARGET_MMA 376 && vsx_register_operand (operands[1], OOmode)" 377 "#" 378 "&& reload_completed" 379 [(const_int 0)] 380{ 381 int reg = REGNO (operands[1]); 382 int regoff = INTVAL (operands[2]); 383 rtx src = gen_rtx_REG (V16QImode, reg + regoff); 384 emit_move_insn (operands[0], src); 385 DONE; 386}) 387 388(define_expand "mma_assemble_acc" 389 [(match_operand:XO 0 "fpr_reg_operand") 390 (match_operand:V16QI 1 "mma_assemble_input_operand") 391 (match_operand:V16QI 2 "mma_assemble_input_operand") 392 (match_operand:V16QI 3 "mma_assemble_input_operand") 393 (match_operand:V16QI 4 "mma_assemble_input_operand")] 394 "TARGET_MMA" 395{ 396 rtx src = gen_rtx_UNSPEC (XOmode, 397 gen_rtvec (4, operands[1], operands[2], 398 operands[3], operands[4]), 399 UNSPEC_MMA_ASSEMBLE); 400 emit_move_insn (operands[0], src); 401 DONE; 402}) 403 404(define_insn_and_split "*mma_assemble_acc" 405 [(set (match_operand:XO 0 "fpr_reg_operand" "=d") 406 (unspec:XO [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa") 407 (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa") 408 (match_operand:V16QI 3 "mma_assemble_input_operand" "mwa") 409 (match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")] 410 UNSPEC_MMA_ASSEMBLE))] 411 "TARGET_MMA 412 && fpr_reg_operand (operands[0], XOmode)" 413 "#" 414 "&& reload_completed" 415 [(const_int 0)] 416{ 417 rtx src = gen_rtx_UNSPEC (XOmode, 418 gen_rtvec (4, operands[1], operands[2], 419 operands[3], operands[4]), 420 UNSPEC_MMA_ASSEMBLE); 421 rs6000_split_multireg_move (operands[0], src); 422 DONE; 423}) 424 425(define_expand "mma_disassemble_acc" 426 [(match_operand:V16QI 0 "mma_disassemble_output_operand") 427 (match_operand:XO 1 "fpr_reg_operand") 428 (match_operand 2 "const_0_to_3_operand")] 429 "TARGET_MMA" 430{ 431 rtx src; 432 int regoff = INTVAL (operands[2]); 433 src = gen_rtx_UNSPEC (V16QImode, 434 gen_rtvec (2, operands[1], GEN_INT (regoff)), 435 UNSPEC_MMA_EXTRACT); 436 emit_move_insn (operands[0], src); 437 DONE; 438}) 439 440(define_insn_and_split "*mma_disassemble_acc" 441 [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa") 442 (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d") 443 (match_operand 2 "const_0_to_3_operand")] 444 UNSPEC_MMA_EXTRACT))] 445 "TARGET_MMA 446 && fpr_reg_operand (operands[1], XOmode)" 447 "#" 448 "&& reload_completed" 449 [(const_int 0)] 450{ 451 int reg = REGNO (operands[1]); 452 int regoff = INTVAL (operands[2]); 453 rtx src = gen_rtx_REG (V16QImode, reg + regoff); 454 emit_move_insn (operands[0], src); 455 DONE; 456}) 457 458;; MMA instructions that do not use their accumulators as an input, still 459;; must not allow their vector operands to overlap the registers used by 460;; the accumulator. We enforce this by marking the output as early clobber. 461 462(define_insn "mma_<acc>" 463 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 464 (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")] 465 MMA_ACC))] 466 "TARGET_MMA" 467 "<acc> %A0" 468 [(set_attr "type" "mma")]) 469 470;; We can't have integer constants in XOmode so we wrap this in an UNSPEC. 471 472(define_expand "mma_xxsetaccz" 473 [(set (match_operand:XO 0 "fpr_reg_operand") 474 (const_int 0))] 475 "TARGET_MMA" 476{ 477 rtx xo0 = gen_rtx_UNSPEC (XOmode, gen_rtvec (1, const0_rtx), 478 UNSPEC_MMA_XXSETACCZ); 479 emit_insn (gen_rtx_SET (operands[0], xo0)); 480 DONE; 481}) 482 483(define_insn_and_split "*mma_xxsetaccz" 484 [(set (match_operand:XO 0 "fpr_reg_operand" "=d") 485 (unspec:XO [(match_operand 1 "const_0_to_1_operand" "O")] 486 UNSPEC_MMA_XXSETACCZ))] 487 "TARGET_MMA" 488 "xxsetaccz %A0" 489 "&& reload_completed" 490 [(set (match_dup 0) (unspec:XO [(match_dup 1)] UNSPEC_MMA_XXSETACCZ))] 491 "" 492 [(set_attr "type" "mma") 493 (set_attr "length" "4")]) 494 495(define_insn "mma_<vv>" 496 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 497 (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa") 498 (match_operand:V16QI 2 "vsx_register_operand" "wa")] 499 MMA_VV))] 500 "TARGET_MMA" 501 "<vv> %A0,%x1,%x2" 502 [(set_attr "type" "mma")]) 503 504(define_insn "mma_<avv>" 505 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 506 (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0") 507 (match_operand:V16QI 2 "vsx_register_operand" "wa") 508 (match_operand:V16QI 3 "vsx_register_operand" "wa")] 509 MMA_AVV))] 510 "TARGET_MMA" 511 "<avv> %A0,%x2,%x3" 512 [(set_attr "type" "mma")]) 513 514(define_insn "mma_<pv>" 515 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 516 (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa") 517 (match_operand:V16QI 2 "vsx_register_operand" "wa")] 518 MMA_PV))] 519 "TARGET_MMA" 520 "<pv> %A0,%x1,%x2" 521 [(set_attr "type" "mma")]) 522 523(define_insn "mma_<apv>" 524 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 525 (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0") 526 (match_operand:OO 2 "vsx_register_operand" "wa") 527 (match_operand:V16QI 3 "vsx_register_operand" "wa")] 528 MMA_APV))] 529 "TARGET_MMA" 530 "<apv> %A0,%x2,%x3" 531 [(set_attr "type" "mma")]) 532 533(define_insn "mma_<vvi4i4i8>" 534 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 535 (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa") 536 (match_operand:V16QI 2 "vsx_register_operand" "wa") 537 (match_operand:SI 3 "const_0_to_15_operand" "n") 538 (match_operand:SI 4 "const_0_to_15_operand" "n") 539 (match_operand:SI 5 "u8bit_cint_operand" "n")] 540 MMA_VVI4I4I8))] 541 "TARGET_MMA" 542 "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5" 543 [(set_attr "type" "mma") 544 (set_attr "prefixed" "yes")]) 545 546(define_insn "mma_<avvi4i4i8>" 547 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 548 (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0") 549 (match_operand:V16QI 2 "vsx_register_operand" "wa") 550 (match_operand:V16QI 3 "vsx_register_operand" "wa") 551 (match_operand:SI 4 "const_0_to_15_operand" "n") 552 (match_operand:SI 5 "const_0_to_15_operand" "n") 553 (match_operand:SI 6 "u8bit_cint_operand" "n")] 554 MMA_AVVI4I4I8))] 555 "TARGET_MMA" 556 "<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6" 557 [(set_attr "type" "mma") 558 (set_attr "prefixed" "yes")]) 559 560(define_insn "mma_<vvi4i4i2>" 561 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 562 (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa") 563 (match_operand:V16QI 2 "vsx_register_operand" "wa") 564 (match_operand:SI 3 "const_0_to_15_operand" "n") 565 (match_operand:SI 4 "const_0_to_15_operand" "n") 566 (match_operand:SI 5 "const_0_to_3_operand" "n")] 567 MMA_VVI4I4I2))] 568 "TARGET_MMA" 569 "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5" 570 [(set_attr "type" "mma") 571 (set_attr "prefixed" "yes")]) 572 573(define_insn "mma_<avvi4i4i2>" 574 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 575 (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0") 576 (match_operand:V16QI 2 "vsx_register_operand" "wa") 577 (match_operand:V16QI 3 "vsx_register_operand" "wa") 578 (match_operand:SI 4 "const_0_to_15_operand" "n") 579 (match_operand:SI 5 "const_0_to_15_operand" "n") 580 (match_operand:SI 6 "const_0_to_3_operand" "n")] 581 MMA_AVVI4I4I2))] 582 "TARGET_MMA" 583 "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6" 584 [(set_attr "type" "mma") 585 (set_attr "prefixed" "yes")]) 586 587(define_insn "mma_<vvi4i4>" 588 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 589 (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa") 590 (match_operand:V16QI 2 "vsx_register_operand" "wa") 591 (match_operand:SI 3 "const_0_to_15_operand" "n") 592 (match_operand:SI 4 "const_0_to_15_operand" "n")] 593 MMA_VVI4I4))] 594 "TARGET_MMA" 595 "<vvi4i4> %A0,%x1,%x2,%3,%4" 596 [(set_attr "type" "mma") 597 (set_attr "prefixed" "yes")]) 598 599(define_insn "mma_<avvi4i4>" 600 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 601 (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0") 602 (match_operand:V16QI 2 "vsx_register_operand" "wa") 603 (match_operand:V16QI 3 "vsx_register_operand" "wa") 604 (match_operand:SI 4 "const_0_to_15_operand" "n") 605 (match_operand:SI 5 "const_0_to_15_operand" "n")] 606 MMA_AVVI4I4))] 607 "TARGET_MMA" 608 "<avvi4i4> %A0,%x2,%x3,%4,%5" 609 [(set_attr "type" "mma") 610 (set_attr "prefixed" "yes")]) 611 612(define_insn "mma_<pvi4i2>" 613 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 614 (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa") 615 (match_operand:V16QI 2 "vsx_register_operand" "wa") 616 (match_operand:SI 3 "const_0_to_15_operand" "n") 617 (match_operand:SI 4 "const_0_to_3_operand" "n")] 618 MMA_PVI4I2))] 619 "TARGET_MMA" 620 "<pvi4i2> %A0,%x1,%x2,%3,%4" 621 [(set_attr "type" "mma") 622 (set_attr "prefixed" "yes")]) 623 624(define_insn "mma_<apvi4i2>" 625 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 626 (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0") 627 (match_operand:OO 2 "vsx_register_operand" "wa") 628 (match_operand:V16QI 3 "vsx_register_operand" "wa") 629 (match_operand:SI 4 "const_0_to_15_operand" "n") 630 (match_operand:SI 5 "const_0_to_3_operand" "n")] 631 MMA_APVI4I2))] 632 "TARGET_MMA" 633 "<apvi4i2> %A0,%x2,%x3,%4,%5" 634 [(set_attr "type" "mma") 635 (set_attr "prefixed" "yes")]) 636 637(define_insn "mma_<vvi4i4i4>" 638 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 639 (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa") 640 (match_operand:V16QI 2 "vsx_register_operand" "wa") 641 (match_operand:SI 3 "const_0_to_15_operand" "n") 642 (match_operand:SI 4 "const_0_to_15_operand" "n") 643 (match_operand:SI 5 "const_0_to_15_operand" "n")] 644 MMA_VVI4I4I4))] 645 "TARGET_MMA" 646 "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5" 647 [(set_attr "type" "mma") 648 (set_attr "prefixed" "yes")]) 649 650(define_insn "mma_<avvi4i4i4>" 651 [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") 652 (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0") 653 (match_operand:V16QI 2 "vsx_register_operand" "wa") 654 (match_operand:V16QI 3 "vsx_register_operand" "wa") 655 (match_operand:SI 4 "const_0_to_15_operand" "n") 656 (match_operand:SI 5 "const_0_to_15_operand" "n") 657 (match_operand:SI 6 "const_0_to_15_operand" "n")] 658 MMA_AVVI4I4I4))] 659 "TARGET_MMA" 660 "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6" 661 [(set_attr "type" "mma") 662 (set_attr "prefixed" "yes")]) 663