1 /**************************************************************************
2 
3 Copyright (c) 2007, Chelsio Inc.
4 All rights reserved.
5 
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8 
9  1. Redistributions of source code must retain the above copyright notice,
10     this list of conditions and the following disclaimer.
11 
12  2. Neither the name of the Chelsio Corporation nor the names of its
13     contributors may be used to endorse or promote products derived from
14     this software without specific prior written permission.
15 
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27 
28 ***************************************************************************/
29 #ifndef _FIRMWARE_EXPORTS_H_
30 #define _FIRMWARE_EXPORTS_H_
31 
32 /* WR OPCODES supported by the firmware.
33  */
34 #define FW_WROPCODE_FORWARD         0x01
35 #define FW_WROPCODE_BYPASS          0x05
36 
37 #define FW_WROPCODE_TUNNEL_TX_PKT       0x03
38 
39 #define FW_WROPOCDE_ULPTX_DATA_SGL      0x00
40 #define FW_WROPCODE_ULPTX_MEM_READ      0x02
41 #define FW_WROPCODE_ULPTX_PKT           0x04
42 #define FW_WROPCODE_ULPTX_INVALIDATE        0x06
43 
44 #define FW_WROPCODE_TUNNEL_RX_PKT       0x07
45 
46 #define FW_WROPCODE_OFLD_GETTCB_RPL     0x08
47 #define FW_WROPCODE_OFLD_CLOSE_CON      0x09
48 #define FW_WROPCODE_OFLD_TP_ABORT_CON_REQ   0x0A
49 #define FW_WROPCODE_OFLD_HOST_ABORT_CON_RPL 0x0F
50 #define FW_WROPCODE_OFLD_HOST_ABORT_CON_REQ 0x0B
51 #define FW_WROPCODE_OFLD_TP_ABORT_CON_RPL   0x0C
52 #define FW_WROPCODE_OFLD_TX_DATA        0x0D
53 #define FW_WROPCODE_OFLD_TX_DATA_ACK        0x0E
54 
55 #define FW_WROPCODE_RI_RDMA_INIT        0x10
56 #define FW_WROPCODE_RI_RDMA_WRITE       0x11
57 #define FW_WROPCODE_RI_RDMA_READ_REQ        0x12
58 #define FW_WROPCODE_RI_RDMA_READ_RESP       0x13
59 #define FW_WROPCODE_RI_SEND         0x14
60 #define FW_WROPCODE_RI_TERMINATE        0x15
61 #define FW_WROPCODE_RI_RDMA_READ        0x16
62 #define FW_WROPCODE_RI_RECEIVE          0x17
63 #define FW_WROPCODE_RI_BIND_MW          0x18
64 #define FW_WROPCODE_RI_FASTREGISTER_MR      0x19
65 #define FW_WROPCODE_RI_LOCAL_INV        0x1A
66 #define FW_WROPCODE_RI_MODIFY_QP        0x1B
67 #define FW_WROPCODE_RI_BYPASS           0x1C
68 
69 #define FW_WROPOCDE_RSVD            0x1E
70 
71 #define FW_WROPCODE_SGE_EGRESSCONTEXT_RR    0x1F
72 
73 #define FW_WROPCODE_MNGT            0x1D
74 #define FW_MNGTOPCODE_PKTSCHED_SET      0x00
75 
76 /* Maximum size of a WR sent from the host, limited by the SGE.
77  *
78  * Note: WR coming from ULP or TP are only limited by CIM.
79  */
80 #define FW_WR_SIZE          128
81 
82 /* Maximum number of outstanding WRs sent from the host. Value must be
83  * programmed in the CTRL/TUNNEL/QP SGE Egress Context and used by
84  * offload modules to limit the number of WRs per connection.
85  */
86 #define FW_T3_WR_NUM            16
87 #define FW_N3_WR_NUM            7
88 
89 #ifndef N3
90 # define FW_WR_NUM          FW_T3_WR_NUM
91 #else
92 # define FW_WR_NUM          FW_N3_WR_NUM
93 #endif
94 
95 /* FW_TUNNEL_NUM corresponds to the number of supported TUNNEL Queues. These
96  * queues must start at SGE Egress Context FW_TUNNEL_SGEEC_START and must
97  * start at 'TID' (or 'uP Token') FW_TUNNEL_TID_START.
98  *
99  * Ingress Traffic (e.g. DMA completion credit)  for TUNNEL Queue[i] is sent
100  * to RESP Queue[i].
101  */
102 #define FW_TUNNEL_NUM           8
103 #define FW_TUNNEL_SGEEC_START       8
104 #define FW_TUNNEL_TID_START     65544
105 
106 
107 /* FW_CTRL_NUM corresponds to the number of supported CTRL Queues. These queues
108  * must start at SGE Egress Context FW_CTRL_SGEEC_START and must start at 'TID'
109  * (or 'uP Token') FW_CTRL_TID_START.
110  *
111  * Ingress Traffic for CTRL Queue[i] is sent to RESP Queue[i].
112  */
113 #define FW_CTRL_NUM         8
114 #define FW_CTRL_SGEEC_START     65528
115 #define FW_CTRL_TID_START       65536
116 
117 /* FW_OFLD_NUM corresponds to the number of supported OFFLOAD Queues. These
118  * queues must start at SGE Egress Context FW_OFLD_SGEEC_START.
119  *
120  * Note: the 'uP Token' in the SGE Egress Context fields is irrelevant for
121  * OFFLOAD Queues, as the host is responsible for providing the correct TID in
122  * every WR.
123  *
124  * Ingress Trafffic for OFFLOAD Queue[i] is sent to RESP Queue[i].
125  */
126 #define FW_OFLD_NUM         8
127 #define FW_OFLD_SGEEC_START     0
128 
129 /*
130  *
131  */
132 #define FW_RI_NUM           1
133 #define FW_RI_SGEEC_START       65527
134 #define FW_RI_TID_START         65552
135 
136 /*
137  * The RX_PKT_TID
138  */
139 #define FW_RX_PKT_NUM           1
140 #define FW_RX_PKT_TID_START     65553
141 
142 /* FW_WRC_NUM corresponds to the number of Work Request Context that supported
143  * by the firmware.
144  */
145 #define FW_WRC_NUM          \
146     (65536 + FW_TUNNEL_NUM + FW_CTRL_NUM + FW_RI_NUM + FW_RX_PKT_NUM)
147 
148 /*
149  * FW type and version.
150  */
151 #define S_FW_VERSION_TYPE       28
152 #define M_FW_VERSION_TYPE       0xF
153 #define V_FW_VERSION_TYPE(x)        ((x) << S_FW_VERSION_TYPE)
154 #define G_FW_VERSION_TYPE(x)        \
155     (((x) >> S_FW_VERSION_TYPE) & M_FW_VERSION_TYPE)
156 
157 #define S_FW_VERSION_MAJOR      16
158 #define M_FW_VERSION_MAJOR      0xFFF
159 #define V_FW_VERSION_MAJOR(x)       ((x) << S_FW_VERSION_MAJOR)
160 #define G_FW_VERSION_MAJOR(x)       \
161     (((x) >> S_FW_VERSION_MAJOR) & M_FW_VERSION_MAJOR)
162 
163 #define S_FW_VERSION_MINOR      8
164 #define M_FW_VERSION_MINOR      0xFF
165 #define V_FW_VERSION_MINOR(x)       ((x) << S_FW_VERSION_MINOR)
166 #define G_FW_VERSION_MINOR(x)       \
167     (((x) >> S_FW_VERSION_MINOR) & M_FW_VERSION_MINOR)
168 
169 #define S_FW_VERSION_MICRO      0
170 #define M_FW_VERSION_MICRO      0xFF
171 #define V_FW_VERSION_MICRO(x)       ((x) << S_FW_VERSION_MICRO)
172 #define G_FW_VERSION_MICRO(x)       \
173     (((x) >> S_FW_VERSION_MICRO) & M_FW_VERSION_MICRO)
174 
175 #endif /* _FIRMWARE_EXPORTS_H_ */
176